[Tests][TIRx] Localize hardware test gates

[tlopex]

This PR removes the suite-wide TIRx compute-capability gate and localizes hardware skips to CUDA codegen and tile-primitive tests. It keeps the original test parameterization unchanged, allowing parser, printer, IR, transform, and other non-hardware TIRx tests to run in regular CI while device-dependent cases are skipped when SM100 hardware is unavailable. CUDA codegen helpers use explicit target architectures where needed, and the run-only benchmark utility tests retain a local SM100 gate.

This intentionally avoids adding separate compile/run parameter cases. A follow-up PR can audit slow frontend execution tests and define a focused runtime regression budget for real TIRx kernels.

Local validation:

• pytest -n auto -m "not gpu" tests/python/tirx: 486 passed, 79 skipped.
• pytest -n auto -m gpu tests/python/tirx without matching hardware: 1509 skipped.
• Pre-commit passed on all changed files.

[gemini-code-assist]

Code Review

This pull request removes the suite-level hardware gate for TIRX tests, updates target handling in CUDA codegen tests, and adds @pytest.mark.gpu decorators to several test cases. Feedback focuses on correcting an inaccurate return type annotation in _get_source and removing the @pytest.mark.gpu decorators from compile-only tests. Since these compile-only tests do not execute on physical hardware, removing the decorators and specifying concrete target architectures (like sm_90a or sm_100a) inside the tests will allow them to run in CPU-only CI environments.

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[tlopex]

@tvm-bot rerun