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…in a multi-master configuration
…erving legacy behavior.
…added stopTransmissionWIRE to allow sync closeout, handle errors and continue processing the transaction queue
…g ISR called APIs
…or pin assignment validation
- Fix misleading indentation in retry logic (lines 847, 857) - Remove ambiguous overload for Wire.begin() with integer literals (uint16_t version now requires explicit enableGeneralCall parameter) - Remove unused variable in SPI.cpp - Remove redundant unsigned < 0 check in setPending()
- Add __attribute__((weak)) to all SPI interrupt handlers (SERCOM4, SPI1, etc) This allows variants to override them when SERCOM is used for other peripherals (e.g., MKR variants use SERCOM4 for Serial2/UART) - Explicitly cast slave addresses to uint8_t in Wire examples to avoid any potential overload resolution issues on different compiler versions
This was referenced Sep 27, 2026
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Configure CRC16 or CRC32 for an allocated DMA channel, preserve interrupt state, and release ownership after completion or abort.
This was referenced Oct 5, 2026
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Summary
SPI.end()abort active transfers and clear queued source pointers before callers release their buffers. Preserve the incoming interrupt-mask state.This replaces #385. The original PR remains available for its discussion and history, but its
sercom-async-dmahead diverged before the SAME5x integration work. This replacement allows CI and review to run against the branch containing the SAME5x integration without rewriting the old public branch.Validation
Current SPI fix validation
GitHub CI: all 12 jobs pass on the updated PR head.
Full local 12-job CI matrix: 287 successful example compiles, zero failures, and 433 existing skips at
76492a7993f63a2c4687fcdeb5a57853a2272598.Native SPI buffer-lifetime reproduction: all eight cases pass.
Earlier validation
0b814e16.Hardware validation
Dependencies
057f6734f589680072de3a467b3b4051e57f3a9e25e92a0811b364a068989c43788727c18803fc77SPI buffer lifetime regression
SPI.end()previously left the DMA engine and queued transaction pointers active after returning. The change toSERCOM::resetSPI()cancels transfer activity and clears those references before releasing caller-owned memory.The native reproduction failed against the previous implementation and passes against this commit. A SAME54 J-Link probe independently reproduced the stale DMA ownership and verified cancellation after the fix. This also supports NeoPixel SERCOM output, which retains each encoded source buffer until SPI completion.
Optional Wire CRC integration
Wire now supports opt-in CRC-32/ISO-HDLC for each data-bearing I2C phase. The four-byte little-endian trailer is separate from all 255 payload bytes. Address-only probes carry no trailer. CRC remains disabled by default; SPI and UART are unchanged by this integration. Framework retains DMA selection, CRC engine ownership and physical completion. Interrupt-driven phases feed CRCDATAIN rather than silently omitting protection. Failed or truncated receives deliver zero bytes.
The shared DmacCrc dependency is merged from #398. Two preceding receive-retirement guards are a separate fix commit. A native reproduction failed before that correction and passed afterward; paired D21/E54 repeated-START tests also passed at the original full-buffer boundary.
Additional validation includes all 43 Framework native cases; 106 paired corruption/truncation cases with valid 255-byte recovery in both bus directions; three full-capacity repeated-START phases; address-NACK recovery; and 100 iterations of the older slave-TX stall reproduction at 100 kHz. Device acceptance verified real register rejection, signed firmware validation, unchanged inactive flash after every rejected page, and unchanged flash/offset after valid-page replay. Hardware tests used the integrated bundle's matching CRC source.
All 12 local Arduino CI configurations pass on exact branch commit
431bd1931c53a27a0d7fca257a9691d4395874cd, including TinyUSB builds using that branch's own pinned library. Earlier interrupted/overridden-library runs remain recorded separately.