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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| export PLATFORM = asap7 | ||
| export DESIGN_NAME = picorv32 | ||
|
|
||
| export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/picorv32/*.sv)) | ||
| export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc | ||
|
|
||
| export ASAP7_USE_VT = RVT LVT SLVT | ||
|
|
||
| # Synthesis | ||
| export SYNTH_OPERATIONS_ARGS = -booth | ||
| export REMOVE_ABC_BUFFERS = 1 | ||
| export SYNTH_RETIME_MODULES = $(DESIGN_NAME) | ||
| export SYNTH_HDL_FRONTEND = slang | ||
| export LEC_CHECK = 0 | ||
|
|
||
| # Floorplan | ||
| export CORE_UTILIZATION = 60 | ||
| export CORE_ASPECT_RATIO = 1 | ||
| export CORE_MARGIN = 2 | ||
|
|
||
| export TNS_END_PERCENT = 100 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,10 @@ | ||
| set_units -time ps -capacitance fF -resistance kOhm -voltage V -current mA -power pW | ||
| current_design picorv32 | ||
|
|
||
| set clk_period 300 | ||
| set io_delay [expr 0.20 * $clk_period] | ||
| create_clock -name core_clock -period $clk_period [get_ports clk] | ||
| create_clock -name vclk_core -period $clk_period | ||
| set_max_fanout 16 [current_design] | ||
| set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks] | ||
| set_output_delay $io_delay -clock vclk_core [all_outputs] | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,112 @@ | ||
| { | ||
| "synth__canonical_netlist__hash": { | ||
| "value": "e4ff1176ec5b0f3d0fe6b92a6a8dfd6c2f841d84", | ||
| "compare": "==", | ||
| "level": "warning" | ||
| }, | ||
| "synth__netlist__hash": { | ||
| "value": "f224cc0c978bde0570734d1aff0a28360b477a40", | ||
| "compare": "==", | ||
| "level": "warning" | ||
| }, | ||
| "synth__design__instance__area__stdcell": { | ||
| "value": 2620.0, | ||
| "compare": "<=" | ||
| }, | ||
| "constraints__clocks__count": { | ||
| "value": 2, | ||
| "compare": "==" | ||
| }, | ||
| "placeopt__design__instance__area": { | ||
| "value": 2762, | ||
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| }, | ||
| "placeopt__design__instance__count__stdcell": { | ||
| "value": 24496, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedplace__design__violations": { | ||
| "value": 0, | ||
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| }, | ||
| "cts__design__instance__count__setup_buffer": { | ||
| "value": 2130, | ||
| "compare": "<=" | ||
| }, | ||
| "cts__design__instance__count__hold_buffer": { | ||
| "value": 2130, | ||
| "compare": "<=" | ||
| }, | ||
| "cts__timing__setup__ws": { | ||
| "value": -429.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__setup__tns": { | ||
| "value": -18000.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__hold__ws": { | ||
| "value": -20.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__hold__tns": { | ||
| "value": -80.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__antenna_diodes_count": { | ||
| "value": 100, | ||
| "compare": "<=" | ||
| }, | ||
| "globalroute__timing__setup__ws": { | ||
| "value": -461.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__setup__tns": { | ||
| "value": -22000.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__hold__ws": { | ||
| "value": -20.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__hold__tns": { | ||
| "value": -80.0, | ||
| "compare": ">=" | ||
| }, | ||
| "detailedroute__route__wirelength": { | ||
| "value": 87408, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__route__drc_errors": { | ||
| "value": 0, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__antenna__violating__nets": { | ||
| "value": 0, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__antenna_diodes_count": { | ||
| "value": 100, | ||
| "compare": "<=" | ||
| }, | ||
| "finish__timing__setup__ws": { | ||
| "value": -417.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__setup__tns": { | ||
| "value": -18600.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__hold__ws": { | ||
| "value": -20.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__hold__tns": { | ||
| "value": -80.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__design__instance__area": { | ||
| "value": 2885, | ||
| "compare": "<=" | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| export PLATFORM = asap7 | ||
| export DESIGN_NAME = tpu | ||
|
|
||
| export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/tpu/*.sv)) | ||
| export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc | ||
|
|
||
| export ASAP7_USE_VT = RVT LVT SLVT | ||
|
|
||
| # Synthesis | ||
| export SYNTH_HDL_FRONTEND = slang | ||
| export LEC_CHECK = 0 | ||
|
|
||
| # Floorplan | ||
| export CORE_UTILIZATION = 60 | ||
| export CORE_ASPECT_RATIO = 1 | ||
| export CORE_MARGIN = 2 | ||
|
|
||
| export TNS_END_PERCENT = 100 | ||
|
|
||
| # Routing | ||
| export MAX_ROUTING_LAYER = M9 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,10 @@ | ||
| set_units -time ps -capacitance fF -resistance kOhm -voltage V -current mA -power pW | ||
| current_design tpu | ||
|
|
||
| set clk_period 200 | ||
| set io_delay [expr 0.20 * $clk_period] | ||
| create_clock -name core_clock -period $clk_period [get_ports clk] | ||
| create_clock -name vclk_core -period $clk_period | ||
| set_max_fanout 16 [current_design] | ||
| set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks] | ||
| set_output_delay $io_delay -clock vclk_core [all_outputs] |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,112 @@ | ||
| { | ||
| "synth__canonical_netlist__hash": { | ||
| "value": "d93c1a668eaa8748f4ddbc8ed4ce3334d5b0ec1b", | ||
| "compare": "==", | ||
| "level": "warning" | ||
| }, | ||
| "synth__netlist__hash": { | ||
| "value": "b76c679a52aa60fd98a6195d467f06e647c75ad6", | ||
| "compare": "==", | ||
| "level": "warning" | ||
| }, | ||
| "synth__design__instance__area__stdcell": { | ||
| "value": 6020.0, | ||
| "compare": "<=" | ||
| }, | ||
| "constraints__clocks__count": { | ||
| "value": 2, | ||
| "compare": "==" | ||
| }, | ||
| "placeopt__design__instance__area": { | ||
| "value": 5926, | ||
| "compare": "<=" | ||
| }, | ||
| "placeopt__design__instance__count__stdcell": { | ||
| "value": 52923, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedplace__design__violations": { | ||
| "value": 0, | ||
| "compare": "==" | ||
| }, | ||
| "cts__design__instance__count__setup_buffer": { | ||
| "value": 4602, | ||
| "compare": "<=" | ||
| }, | ||
| "cts__design__instance__count__hold_buffer": { | ||
| "value": 4602, | ||
| "compare": "<=" | ||
| }, | ||
| "cts__timing__setup__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__setup__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__hold__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__hold__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__antenna_diodes_count": { | ||
| "value": 100, | ||
| "compare": "<=" | ||
| }, | ||
| "globalroute__timing__setup__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__setup__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__hold__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__hold__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "detailedroute__route__wirelength": { | ||
| "value": 119542, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__route__drc_errors": { | ||
| "value": 0, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__antenna__violating__nets": { | ||
| "value": 0, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__antenna_diodes_count": { | ||
| "value": 100, | ||
| "compare": "<=" | ||
| }, | ||
| "finish__timing__setup__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__setup__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__hold__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__hold__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__design__instance__area": { | ||
| "value": 6092, | ||
| "compare": "<=" | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,63 @@ | ||
| export PLATFORM = asap7 | ||
| export DESIGN_NAME = CoupledL2 | ||
| export DESIGN_NICKNAME = xiangshan_coupledl2 | ||
|
|
||
| export VERILOG_FILES = $(sort \ | ||
| $(wildcard $(DESIGN_HOME)/src/xiangshan_coupledl2/*.sv) \ | ||
| $(wildcard $(DESIGN_HOME)/src/xiangshan_coupledl2/deps/*.sv)) \ | ||
| $(PLATFORM_DIR)/verilog/array_2048x137_bk_bb.sv \ | ||
| $(PLATFORM_DIR)/verilog/array_256x104_bb.sv \ | ||
| $(PLATFORM_DIR)/verilog/array_256x13_bb.sv \ | ||
| $(PLATFORM_DIR)/verilog/array_256x164_bb.sv \ | ||
| $(PLATFORM_DIR)/verilog/array_256x16_bb.sv \ | ||
| $(PLATFORM_DIR)/verilog/array_256x8_0_bb.sv | ||
| export VERILOG_DEFINES += -D SYNTHESIS | ||
| export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc | ||
|
|
||
| # Fakeram macros for the SRAM arrays; fakeram.cfg in this directory records how | ||
| # the platform views were generated. | ||
| export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/array_2048x137_bk.lef \ | ||
| $(PLATFORM_DIR)/lef/array_256x104.lef \ | ||
| $(PLATFORM_DIR)/lef/array_256x13.lef \ | ||
| $(PLATFORM_DIR)/lef/array_256x164.lef \ | ||
| $(PLATFORM_DIR)/lef/array_256x16.lef \ | ||
| $(PLATFORM_DIR)/lef/array_256x8_0.lef | ||
| export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/array_2048x137_bk.lib \ | ||
| $(PLATFORM_DIR)/lib/NLDM/array_256x104.lib \ | ||
| $(PLATFORM_DIR)/lib/NLDM/array_256x13.lib \ | ||
| $(PLATFORM_DIR)/lib/NLDM/array_256x164.lib \ | ||
| $(PLATFORM_DIR)/lib/NLDM/array_256x16.lib \ | ||
| $(PLATFORM_DIR)/lib/NLDM/array_256x8_0.lib | ||
| export GDS_ALLOW_EMPTY = (fakeram.*|DFFHQN[VH][24].*|array_.*) | ||
|
|
||
| export ASAP7_USE_VT = RVT LVT SLVT | ||
|
|
||
| # Synthesis | ||
| export SYNTH_HIERARCHICAL = 1 | ||
| export SYNTH_MINIMUM_KEEP_SIZE ?= 10000 | ||
| export SYNTH_HDL_FRONTEND = slang | ||
| export LEC_CHECK = 0 | ||
|
|
||
| # Floorplan | ||
| export CORE_UTILIZATION = 50 | ||
| export CORE_ASPECT_RATIO = 1 | ||
| export CORE_MARGIN = 2 | ||
| export MACRO_PLACE_HALO = 5 5 | ||
|
|
||
| # Placement and timing repair | ||
| export GPL_TIMING_DRIVEN = 0 | ||
| export GPL_ROUTABILITY_DRIVEN = 0 | ||
| export TNS_END_PERCENT = 5 | ||
| export SKIP_CTS_REPAIR_TIMING = 1 | ||
| export SKIP_INCREMENTAL_REPAIR = 1 | ||
| export ENABLE_RESISTANCE_AWARE = 0 | ||
|
|
||
| # Routing | ||
| export GLOBAL_ROUTE_ARGS = -congestion_iterations 5 -congestion_report_iter_step 5 -verbose -allow_congestion | ||
| # FlexDR on current master reports DRT-0206 terminal-connectivity errors for | ||
| # this design, so detailed routing is skipped and the Final report uses | ||
| # global-route estimated parasitics. | ||
| export SKIP_DETAILED_ROUTE = 1 | ||
| export DETAILED_ROUTE_END_ITERATION = 32 | ||
| export SKIP_ANTENNA_REPAIR = 1 | ||
| export SKIP_ANTENNA_REPAIR_POST_DRT = 1 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,15 @@ | ||
| set_units -time ps -capacitance fF -resistance kOhm -voltage V -current mA -power pW | ||
| current_design CoupledL2 | ||
|
|
||
| # The 1400 ps target keeps the public CI runtime bounded while leaving setup | ||
| # violations for optimization experiments; it is not a measured Fmax of this | ||
| # 128 KiB MinimalConfig L2. | ||
| set clk_period 1400 | ||
| set io_delay [expr 0.20 * $clk_period] | ||
| create_clock -name core_clock -period $clk_period [get_ports clock] | ||
| create_clock -name vclk_core -period $clk_period | ||
| set_max_fanout 16 [current_design] | ||
| # Exclude the asynchronous reset from data-path timing optimization. | ||
| set_false_path -from [get_ports reset] | ||
| set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks] | ||
| set_output_delay $io_delay -clock vclk_core [all_outputs] |
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I think this is wrong and non-idiomatic for a CPU. set_input_delay causes hold cell infestation and a CPU is going to be connected to a system bus and that system bus is going to be connected to a clock crossing bridge, so set_input/output_delay is wrong here. See asap7/constraints.sdc for how OpenROAD today can best create idiomatic constraints for a CPU that sits as a macro in a core clock domain.