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Signed-off-by: João Mai <jmai@precisioninno.com>
designs/asap7/aes_lvt/rules-base.json updates: | Metric | Old | New | Type | | ------ | --- | --- | ---- | | cts__timing__hold__ws | -18.0 | -15.5 | Tighten | | cts__timing__hold__tns | -72.0 | -62.0 | Tighten | | globalroute__timing__setup__tns | -72.0 | -233.0 | Failing | | globalroute__timing__hold__ws | -18.0 | -15.5 | Tighten | | globalroute__timing__hold__tns | -72.0 | -62.0 | Tighten | | finish__timing__hold__ws | -18.0 | -15.5 | Tighten | | finish__timing__hold__tns | -72.0 | -62.0 | Tighten | Signed-off-by: João Mai <jmai@precisioninno.com>
Signed-off-by: João Mai <jmai@precisioninno.com>
| Metric | Old | New | Type | | ------ | --- | --- | ---- | | synth__canonical_netlist__hash | 932c3068d46acd0c052faec6ef5b4d27a4a6cca4 | a7804e6ee6043e5d2c706ee4a9eb1d5f505ec129 | Failing | | synth__netlist__hash | 3cc489cede7cd5ec5ace3dc04045cbd21f476225 | 517ca60b728cecc2932dca1dd3ef4589d46e7c86 | Failing | | placeopt__design__instance__area | 2635 | 3130 | Failing | | placeopt__design__instance__count__stdcell | 178 | 213 | Failing | | cts__timing__setup__ws | 0.0 | -0.086 | Failing | | cts__timing__setup__tns | -0.18 | -0.488 | Failing | | cts__timing__hold__ws | -0.045 | -0.04 | Tighten | | cts__timing__hold__tns | -0.18 | -0.16 | Tighten | | globalroute__timing__setup__ws | -0.0426 | -0.167 | Failing | | globalroute__timing__setup__tns | -0.2 | -1.84 | Failing | | globalroute__timing__hold__ws | -0.045 | -0.04 | Tighten | | globalroute__timing__hold__tns | -0.18 | -0.16 | Tighten | | detailedroute__route__wirelength | 4630 | 4025 | Tighten | | finish__timing__setup__ws | -0.045 | -0.0977 | Failing | | finish__timing__setup__tns | -0.18 | -0.743 | Failing | | finish__timing__hold__ws | -0.045 | -0.04 | Tighten | | finish__timing__hold__tns | -0.18 | -0.16 | Tighten | | finish__design__instance__area | 2756 | 3261 | Failing | Signed-off-by: João Mai <jmai@precisioninno.com>
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This pull request updates the clock period constraints and corresponding timing, area, and hash rules for the 'asap7/aes_lvt' and 'ihp-sg13g2/spi' designs. Additionally, the 'ihp-sg13g2/spi' configuration is modified to increase core utilization and placement density. The review feedback suggests removing a commented-out line of code in the SPI configuration file to keep it clean and maintainable.
Signed-off-by: João Mai <jmai@precisioninno.com>
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🔍 QoR checkMetrics reflect the PR merge build — i.e. what will land on the target branch. Commit 62 design(s) checked — 2 with regression(s), 1 without a comparable baseline. ❌ asap7/aes_lvt base — 1 failing metric(s)
❌ ihp-sg13g2/spi base — 5 failing metric(s)
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Tighten configs to make timing fail for the designs.