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CYFS3
changed the title
[bsp/renesas][drivers] Skip invalid chip select writes in SPI drivers
[bsp/renesas][drivers] Fix SPI configuration faults
Aug 24, 2026
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拉取/合并请求描述:(PR description)
[
为什么提交这份PR (why to submit this PR)
Renesas SPI 和 SCI SPI 驱动在配置软件片选时没有检查
RT_SPI_NO_CS和PIN_NONE。无片选设备通过rt_spi_bus_attach_device()挂载后,无效引脚号会被 RA GPIO 驱动当作 PFS 索引使用,从而触发总线异常。此外,SPI 驱动将 FSP 生成的
const扩展配置强制转换为可写指针,并让波特率计算函数直接写入该配置。在 RA8P1 M85 上,该配置位于 Flash,写入时会触发IMPRECISERR。SPI 控制器已经打开后也无法直接应用下一档时钟配置,导致时钟矩阵测试不能连续运行。你的解决方案是什么 (what is your solution)
分别修改
bsp/renesas/libraries/HAL_Drivers/drivers/drv_sci.c和drv_spi.c:RT_SPI_NO_CS或cs_pin == PIN_NONE时跳过 CS 引脚写操作;RT_SPI_CS_HIGH设置正确的空闲电平;请提供验证的bsp和config (provide the config and bsp)
BSP:
bsp/renesas/ra8d1-vision-boardsci2s,MOSI/MISO 回环,最大时钟 1 MHz,components.drivers.spi.loopback测试通过。BSP:
bsp/renesas/ra8p1-titan-board/m85spi0,MOSI/MISO 回环,时钟矩阵最大 10 MHz,components.drivers.spi.loopback测试通过。.config:
CONFIG_BSP_USING_SCI2=y、CONFIG_BSP_USING_SCI2_SPI=y、CONFIG_RT_UTEST_SPI_LOOPBACK=y、CONFIG_RT_UTEST_SPI_LOOPBACK_BUS_NAME="sci2s"、CONFIG_RT_UTEST_SPI_LOOPBACK_MAX_HZ=1000000CONFIG_BSP_USING_SPI0=y、CONFIG_RT_UTEST_SPI_LOOPBACK=y、CONFIG_RT_UTEST_SPI_LOOPBACK_BUS_NAME="spi0"、CONFIG_RT_UTEST_SPI_LOOPBACK_MAX_HZ=10000000action:
]
当前拉取/合并请求的状态 Intent for your PR
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我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
#if 0代码,不包含已经被注释了的代码 All redundant code is removed and cleaned up