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1.1.0: WLAN/WPA2, PIO lockstep, cycle-accurate timing, SiliconTwin packaging
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Aug 26, 2026
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1.1.0: WLAN/WPA2, PIO lockstep, cycle-accurate timing, SiliconTwin packaging
#64
begeistert
merged 16 commits into
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PyMCU/RP2040Sharp:master
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feat/silicontwin-packaging
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Rename the TestKits to SiliconTwin.* and check entitlement
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Cpu: pluggable instruction decoders (Switch/NativeLut/Lut) for Cortex-M0+
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Peripherals: read-only state snapshots for tooling/UI views
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GdbHost: standalone GDB server + PIO inspection CLI
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Cpu: cycle-accurate timing matching rp2040js (always-on, branchless)
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license: broaden the BUSL grant; private CI via a separate entitlement, not the licence
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Cpu: core 1 is a first-class core
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Sio: start the divider on a dividend write, and let pads settle on their pulls
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Peripherals: I2C NACKs an empty bus, and the ADC has its temperature sensor
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Pio: stop re-running a blocked instruction whose inputs have not moved
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TestKit: RunCycles charges the cycles actually spent
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Cyw43: WPA2, outbound sockets, DNS, and one MAC per chip
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Pio: run the state machines in lockstep, and fix what the registers report
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Pio: only trust a stall fingerprint within a tick, never across one
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IoBank0: a floating pad reads its pull resistor, whichever side asks
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test: fold the CYW43 firmware fetch into the pinned manifest
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