fpga_diff: organize UVHS flow and debug tools - #149
Open
xiaokamikami wants to merge 1 commit into
Open
Conversation
xiaokamikami
force-pushed
the
uvhs
branch
6 times, most recently
from
July 20, 2026 06:30
53db552 to
e42ef73
Compare
xiaokamikami
force-pushed
the
uvhs
branch
2 times, most recently
from
July 28, 2026 07:04
e7624da to
72a4f74
Compare
Add the reusable Hejian UVHS FPGA DiffTest build/runtime flow, preserve NutShell integration, and support the board-validated single-FPGA XiangShan configuration at 25 MHz.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This PR adds Hejian UVHS support to the fpga_diff NutShell SoC flow, including frontend/backend generation, XDMA and DDR integration, UART, clock/reset handling, and CDC fixes.
It supports CPU-dependent DDR interface widths: 64-bit for NutShell and 256-bit for XiangShan-based designs. It also adds UVHS environment setup, board constraints, timing/CDC checks, bitstream packaging, and tagged runtime programming.
The UVHS NutShell flow has been tested successfully on hardware and completed FPGA DiffTest with HIT GOOD TRAP.
The existing Vivado project-generation flow is reorganized under vivado/ to keep it separate from the UVHS flow. Static flow checks, Makefile dry-runs, 64/256-bit RTL lint, and merge-conflict validation also pass.