Skip to content

refactor: generate compiler libdevice math dispatch - #1649

Closed
uurl wants to merge 4 commits into
NVIDIA:mainfrom
uurl:feat/libdevice-math-generated-dispatch
Closed

refactor: generate compiler libdevice math dispatch#1649
uurl wants to merge 4 commits into
NVIDIA:mainfrom
uurl:feat/libdevice-math-generated-dispatch

Conversation

@uurl

@uurl uurl commented Oct 26, 2026 •
edited
Loading

Copy link
Copy Markdown
Contributor

Summary

Replace duplicated compiler math mapping tables with shared dispatch generated from the libdevice_math shard.

Preserve all 82 existing f32/f64 libm exports and the core-only powi/fmuladd routes, including the scalar functions and frexp adapter introduced by the prerequisite PRs. This migration adds no new math exports.

Depends on #1638, #1645, and #1646. This branch includes their prerequisite changes.

Refs #1224.

Changes

  • Generate the shared math enum, placeholder constants, compiler paths, aliases, operand counts, libdevice/LLVM symbols, cmath allowlist, and link requirements.
  • Make the importer, MIR lowerer, and rustc collector consume the shared dispatch.
  • Remove their duplicated handwritten mapping lists.
  • Extend the shard to schema 2 and capture all 74 required libdevice ABI signatures.
  • Include compiler dispatch in generation, drift checks, and stale-output reconciliation while preserving the hardware catalog and ABI ledger.
  • Add a regression fixture covering 214 pre-migration compiler paths, plus negative and control tests.
  • Preserve the handwritten semantic expansions for frexp, sincos, min/max, and fast arithmetic.

Testing

  • just check: formatting, Clippy, tests, guards, generated outputs, ABI history, documentation, and doctests passed.
  • Generator suite: 336 tests passed.
  • verify-libdevice against installed CUDA: 74 signatures verified.
  • Isolated CLI controls: unchanged generated output accepted; modified compiler dispatch rejected as stale.
  • cargo oxide run math_special: 776 checks passed.
  • cargo oxide run libm_math: all lanes matched host math.
  • cargo oxide run math_hyperbolic: 288 comparisons passed.

Checklist

  • All commits signed off (git commit -s).
  • SPDX headers on new source files.

uurl added 4 commits October 25, 2026 19:16
@uurl
feat: add staged libdevice math generation
d45223c 
Signed-off-by: Raul Estrada <raulestradaa@gmail.com>
@uurl
feat: lower tgamma, ilogb and ldexp through libdevice
5068a87 
Signed-off-by: Raul Estrada <raulestradaa@gmail.com>
@uurl
feat: add libdevice frexp tuple adapter
c430870 
Signed-off-by: Raul Estrada <raulestradaa@gmail.com>
@uurl
refactor: generate compiler libdevice math dispatch
080f5d6 
Signed-off-by: Raul Estrada <raulestradaa@gmail.com>
@copy-pr-bot

copy-pr-bot Bot commented Oct 26, 2026

Copy link
Copy Markdown

This pull request requires additional validation before any workflows can run on NVIDIA's runners.

Pull request vetters can view their responsibilities here.

Contributors can view more details about this message here.

@uurl uurl mentioned this pull request Oct 26, 2026
Closed
5 tasks done
@uurl
uurl marked this pull request as ready for review October 26, 2026 06:53
@uurl
uurl requested a review from nihalpasham as a code owner October 26, 2026 06:53
@nihalpasham nihalpasham added the cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book label Oct 29, 2026
@nihalpasham

nihalpasham commented Oct 29, 2026

Copy link
Copy Markdown
Collaborator

Thanks! Since #1660 contains the full 9-commit #1224 stack in linear order (including this commit with your authorship preserved), I am landing the entire series together through #1660 and closing this intermediate stack PR.

nihalpasham added a commit that referenced this pull request Oct 29, 2026
@uurl @nihalpasham
feat(cuda-oxide): generate libm-to-libdevice math dispatch and lower …
9fcd57f 
…120 libm exports (#1660)

## What This PR Does

Implements `#1224` across the 9-commit `libdevice_math` series (`#1638`,
`#1645`, `#1646`, `#1649`, `#1650`, `#1651`, `#1652`, `#1653`, `#1660`),
replacing hand-maintained math dispatch tables across three crates with
a single generated table backed by `libdevice.10.bc` evidence and
expanding `libm 0.2.16` coverage from 72 to **120 of 124 `f32`/`f64`
exports**:

1. **Add `intrinsics/overlay/libdevice_math.toml` + `libdevice.10.bc`
signature verification and generate `dialect-mir` math dispatch
(`cuda-intrinsics-gen`, `dialect-mir`, `mir-importer`,
`rustc-codegen-cuda`)**
2. **Extract float-math lowering into
`mir-lower/src/convert/ops/float_math.rs` driven by generated
`RustFloatMathLowering` (`mir-lower`)**
3. **Lower scalar aliases (`tgamma`, `ilogb`, `ldexp`, `erf`, `j0`,
`y0`, ...), entry-block out-parameter adapters (`frexp`, `modf`,
`remquo`), `lgamma_r`, C23 `fmaximum`/`fminimum`, and `j1` (`mir-lower`,
`examples/math_special`)**

---

### 1. Generated `libm -> libdevice` Dispatch (`#1224`)

Previously, wiring a single `libm` or `std::sys::cmath` function
required hand-editing ~10 sites across
`rustc-codegen-cuda/src/collector.rs`, `mir-importer`, `dialect-mir`,
and `mir-lower`:

```text
BEFORE (hand-maintained across 4 crates):
  collector.rs       ──► hardcoded `std::sys::cmath::*` match list
  mir-importer       ──► hand-written `RustFloatMathIntrinsic` enum + `from_core_path` / `from_libm_path`
  dialect-mir        ──► hand-written `CALLEE_*` constants + `is_libdevice_backed_placeholder`
  mir-lower          ──► hand-written placeholder -> `__nv_*` match table

AFTER (`intrinsics/overlay/libdevice_math.toml` -> `cuda-intrinsics-gen`):
  libdevice_math.toml + cuda-13.0.json (102 signatures verified against libdevice.10.bc)
    │
    ▼
  crates/dialect-mir/src/generated/libdevice_math.rs
    ├──► collector.rs   `is_intrinsic_lowered_cmath_shim(fn_path)`
    ├──► mir-importer   `from_core_path` + `from_libm_path` -> `CALLEE_*`
    ├──► codegen        `link_requirement()` -> `MathLink::{Always, Libnvvm, Never}`
    └──► mir-lower      `RustFloatMathIntrinsic::lowering(self) -> RustFloatMathLowering`
```

---

### 2. Entry-Block Out-Parameter Adapters & IEEE Edge-Case Lowerings
(`mir-lower`)

```text
Function Family                Lowering in `mir-lower/src/convert/ops/float_math.rs`
─────────────────────────────  ──────────────────────────────────────────────────────────────────────────
`frexp`, `modf`, `remquo`      Hoists `llvm.alloca` to function entry block (`0` `.local` traffic after
                               `opt -O2` SROA); normalizes `frexp(+-inf/NaN) -> (x, 0)` and `remquo` NaN -> `quo = 0`
`lgamma_r`, `lgammaf_r`        Composes `__nv_lgamma`, `__nv_floor`, and `__nv_fmod(floor(x), 2.0)` with
                               `-0.0 -> (+inf, -1)`, negative integer poles `-> (+inf, +1)`, `-inf -> (+inf, +1)`
C23 `fmaximum*` / `fminimum*`  Pure LLVM `fcmp` (empty fast-math flags) + sign-bit tie-break (`-0.0 < +0.0`)
`j1`, `j1f`                    Calls `__nv_j1{,f}` and normalizes `|x| == inf -> +0.0`
```

---

## Verification

* **RTX 5090 (`sm_120a`) GPU Execution & Sanitizer**:
* `cargo oxide run math_special`: **2,822 / 2,822 `f32` and `f64` checks
PASS** (`compute-sanitizer --tool memcheck`: `0 errors`, `0` `.local`
instructions emitted for `frexp`, `modf`, `remquo`, `lgamma_r`, and C23
`minmax`).
* `cargo oxide run libm_math` & `cargo oxide run libdevice_math`:
**PASS**.
* **Generator & Bitcode Verification**:
* `cargo run -p cuda-intrinsics-gen -- check` & `verify-libdevice`:
**PASS** (`102` `libdevice.10.bc` signatures verified).
* **Tests, Lints & Guards**:
* `cargo test -p cuda-intrinsics-gen -p dialect-mir -p mir-importer -p
mir-lower -p cuda-oxide-codegen --all-targets`: **3,494 tests PASS**
* `just fmt-check`, `just clippy`, `scripts/sync-example-locks.sh
--check`, and all 18 `scripts/check-*.sh` guards: **all PASS**

Closes #1224

---------

Signed-off-by: Raul Estrada <raulestradaa@gmail.com>
Signed-off-by: nihalpasham <nihalp@nvidia.com>
Co-authored-by: nihalpasham <nihalp@nvidia.com>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

@nihalpasham nihalpasham Awaiting requested review from nihalpasham nihalpasham is a code owner

Assignees

No one assigned

Labels

cuda-oxide SIMT programming model: rustc backend, cargo oxide, cuda-device, cuda-host, book

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

2 participants

@uurl @nihalpasham