[Common] Fix Grouped MXFP8 work mapping and TMA synchronization - #3483
[Common] Fix Grouped MXFP8 work mapping and TMA synchronization#3483Oleg-Goncharov wants to merge 7 commits into
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Greptile SummaryThis PR corrects Grouped MXFP8 direct work mapping and TMA descriptor synchronization.
Confidence Score: 5/5The PR appears safe to merge; the previously identified incomplete-warp descriptor publication is corrected and no new actionable failure remains. The updater now executes descriptor publication with a full warp, pairs GPU-scope release and acquire operations across CTAs, and prevents asynchronous TMA traffic from corrupting mapper metadata. The only relevant change since the previous review is formatting of the corrected launch. Important Files Changed
Sequence DiagramsequenceDiagram
participant Host
participant U as Descriptor updater CTA
participant G as Global CUtensorMap
participant Q as Quantize/dequantize CTA
Host->>U: Launch one full warp per tensor
U->>U: Copy and modify aligned shared descriptor
U->>G: Warp-collective copy with release.gpu
Host->>Q: Launch grouped kernel in same stream
Q->>G: acquire.gpu tensor-map fence
G-->>Q: Published descriptor
Q->>Q: Resolve expert and expert-relative row
Q->>Q: Execute TMA operation
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Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
for more information, see https://pre-commit.ci
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
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for more information, see https://pre-commit.ci
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This PR fixes the reported MXFP8 MoE illegal-memory-access regression in #3474. We reran the reproducer using the current PR head (be88f0c), applied to the exact first-bad TransformerEngine revision (c3066f8), and confirmed that the patched sources were rebuilt.
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Description
This PR fixes three correctness issues in the Grouped MXFP8 quantization kernels introduced by the optimized work mapper:
the direct
VARYING_FIRST_DIMpath assumed that every tensor's first dimension was aligned to the 128-row kernel tile, but only the combined logical dimension was validated. This could allow a CTA to cross an expert boundary and use incorrect per-expert metadata.device-modified TMA descriptors were copied from shared to global memory without the release/acquire protocol required by the TMA memory model. The descriptor updater now follows the recommended warp-collective publication sequence.
the direct mapper stored per-expert metadata in dynamic shared memory that was also used as the destination of asynchronous TMA loads. A TMA load could therefore overwrite the metadata before every warp had consumed it, resulting in corrupted tensor metadata and invalid global-memory addresses. The mapper metadata is now kept in dedicated static shared memory, and the row offset is computed relative to the current expert.
Addresses #3474
Type of change
Changes
Please list the changes introduced in this PR:
VARYING_FIRST_DIMtensor has a first dimension divisible by the 128-row kernel tile.CUtensorMapstorage to 128 bytes.tensormap.cp_fenceproxyoperation using GPU-scope release semantics.Checklist: