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Start working on write operation Scala CI #51: Commit 5d35e46 pushed by outercloudstudio
45s master
master
45s
Working load command Scala CI #50: Commit a2f098b pushed by outercloudstudio
42s master
master
42s
load almost working Scala CI #49: Commit 6f17a7b pushed by outercloudstudio
51s master
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51s
Working operation lock in thread Scala CI #48: Commit 224f598 pushed by outercloudstudio
45s master
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45s
Update before operation changes Scala CI #47: Commit 93790ab pushed by outercloudstudio
46s master
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46s
Progress on integrating lsu in threads Scala CI #46: Commit a3f9442 pushed by outercloudstudio
43s master
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43s
Add writing full instruction for debug Scala CI #45: Commit 61f1ed6 pushed by outercloudstudio
57s master
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57s
Fix metals extension Scala CI #44: Commit 03ed9c7 pushed by outercloudstudio
49s master
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49s
I can't spell apparantly Scala CI #43: Commit a43f73f pushed by outercloudstudio
44s master
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44s
Rename liscence Scala CI #42: Commit 51d7b53 pushed by outercloudstudio
47s master
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Create LISCENCE.md Scala CI #41: Commit 54ec9b2 pushed by outercloudstudio
48s master
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Working memory pipelining Scala CI #40: Commit 93e191e pushed by outercloudstudio
49s master
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49s
Add tasks.json Scala CI #39: Commit ed047e5 pushed by outercloudstudio
59s master
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59s
Fix namings and gitignore Scala CI #38: Commit 3102289 pushed by outercloudstudio
53s master
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53s
added iverilog testbench and vivado test project Scala CI #37: Commit ea92057 pushed by arghunter
1m 11s master
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1m 11s
vivado gitignore Scala CI #36: Commit f019c64 pushed by arghunter
1m 1s master
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1m 1s
Reduce delay in parsing read instructions by one clock cycle Scala CI #35: Commit a57d5f8 pushed by outercloudstudio
46s master
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46s
Reduce delay between idle and read start by one cycle Scala CI #34: Commit 47c5d22 pushed by outercloudstudio
1m 6s master
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1m 6s
Do some cleanup on the ALU Scala CI #33: Commit e979cf2 pushed by outercloudstudio
1m 17s master
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1m 17s
Implement move immediate op Scala CI #32: Commit 840aeaf pushed by outercloudstudio
55s master
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55s
Implement move register op Scala CI #31: Commit 1777fcf pushed by outercloudstudio
53s master
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Fix reading incorrect location from memory Scala CI #30: Commit 5dd198d pushed by outercloudstudio
54s master
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54s
Implement register codes Scala CI #29: Commit 9a38fad pushed by outercloudstudio
57s master
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Add operation on registers Scala CI #28: Commit 3edf40f pushed by outercloudstudio
1m 0s master
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1m 0s
Loading 24 bits of memory per instruction Scala CI #27: Commit f022b7c pushed by outercloudstudio
52s master
master
52s