chore(deps): update dependency flashinfer-python to v0.6.14#123
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This PR contains the following updates:
==0.6.12→==0.6.14Release Notes
flashinfer-ai/flashinfer (flashinfer-python)
v0.6.14Compare Source
Manual Intervention Needed⚠️
Please modify your install instructions as you bump the version to 0.6.14.
See also #3808
Highlights
This release pushes FlashInfer's coverage onto Blackwell RTX PRO and DGX Spark silicon, lands the CuTe-DSL rewrite of the gated-delta-rule (GDN) kernels behind Qwen3.5/3.6, and makes those kernels production-ready inside vLLM.
Gemma 4 and W4A16 on Blackwell RTX Pro and DGX Spark
Blackwell SM12x parts (RTX PRO 6000, DGX Spark / GB10) previously trailed Blackwell GB200 NVL72 (and B300 SM103) on attention shape and quantization coverage. This release closes the gap for Gemma 4 and weight-only-quantized inference: head_dim=512 attention for Gemma 4's global layers now runs on SM120/121, the FMHAv2 prefill path gains head_dim=256/512 and sliding-window masking on SM120, the new mm_bf16_fp4 W4A16 GEMM is tuned for DGX Spark (completing W4A16 across both dense GEMM and MoE), and gated tanh-GELU brings Gemma 4 MoE onto the CUTLASS backend.
GDN / gated delta rule: CuTe-DSL overhaul (Qwen3.5/3.6)
The gated-delta-rule kernels behind the Qwen3.5/3.6 family were rewritten from CUTLASS C++ to CuTe-DSL (#3491). The rewrite eliminates the C++ JIT compilation pain reported by customers and establishes the base for context-parallel delta-rule kernels — covering SM90 prefill and its context-parallel variant, SM120 prefill, and a ~20–25% GDN prefill speedup from mainloop efficiency work.
GDN production-ready in vLLM
Two gaps blocked GDN serving in vLLM (#3602); both are now resolved. GDN kernels are compilation batch-size agnostic, so a single compiled cubin is reused across batch shapes instead of recompiling on every new batch size at inference time, and a new BF16 state recovery/decode kernel writes SSM state into preallocated space to supply the MTP-compatible spec-decode path vLLM needs.
DeepSeek-class sparse MLA on Blackwell, FP8 KV on Hopper
New sparse-MLA paged-attention kernels extend the DeepSeek-V4 (d_qk=512) and DeepSeek-V3.2 / GLM-5.1 (d_qk=576) families onto SM120/121 through the existing flashinfer.mla APIs, with DSv4 coverage broadened to 8/16/32 head counts. On Hopper SM90, native FP8 KV cache support eliminates SGLang's per-layer cast workaround, saving an HBM round-trip per layer on DeepSeek-V3/V4 while staying bit-identical to the BF16 path.
This release pushes FlashInfer's coverage onto Blackwell RTX PRO and DGX Spark silicon, lands the CuTe-DSL rewrite of the gated-delta-rule (GDN) kernels behind Qwen3.5/3.6, and makes those kernels production-ready inside vLLM.
What's Changed
FilteredTopKoverflow refinement by @awgu in #3529mm_fp4cute-dslbackend when M is not a multiple of 8. by @b8zhong in #3667New Contributors
Full Changelog: flashinfer-ai/flashinfer@v0.6.13rc2...v0.6.14
v0.6.13Compare Source
What's Changed
bmm_fp8and cuDNNbmm_fp8/mm_fp4by @bkryu in #3437nvfp4_quantize(backend='cuda')silently corrupts scale factors when global_scale is not float32 by @bkryu in #3497New Contributors
Full Changelog: flashinfer-ai/flashinfer@v0.6.12rc3...v0.6.13
Configuration
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