4-Bit Gray Code Counter

Overview

This design implements a 4-bit Gray code counter using sequential logic.

The counter generates the complete 4-bit Gray code sequence, where only one bit changes between consecutive states. The circuit was designed and simulated using the Digital logic simulator and also implemented in SystemVerilog with a separate testbench for verification.

Gray Code Sequence

Decimal	Gray Code
0	0000
1	0001
2	0011
3	0010
4	0110
5	0111
6	0101
7	0100
8	1100
9	1101
10	1111
11	1110
12	1010
13	1011
14	1001
15	1000

Features

• 4-bit Gray code counter
• 16-state counting sequence
• Single-bit transition between consecutive states
• Clock-based sequential operation
• Digital circuit implementation
• SystemVerilog implementation
• Separate testbench for verification

Implementation

The counter is implemented as a sequential state-based design. Each clock transition moves the counter to the next state in the 4-bit Gray code sequence.

The hardware design is simulated in the Digital logic simulator, while the HDL implementation is verified separately using a SystemVerilog testbench.

Tools

• Digital Logic Simulator
• SystemVerilog

Repository Structure

• Digital_Design - Digital circuit simulation file
• SystemVerilog - HDL source code and testbench

Digital Design

Simulation Output