Integrate the DFlash7 artifact with draft-loader separation - #136
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FujitsuPolycom wants to merge 3 commits into
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Integrate the DFlash7 artifact with draft-loader separation#136FujitsuPolycom wants to merge 3 commits into
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Construct a DFlash7-labelled image from the shared 31-file vLLM Python overlay while retaining da4d7be native extensions, B12X b1d541f, and SparkCache reconstructed-page placement at 5d571018. Prepared receipts name the external DFlash7 workload and preserve exact source, native, CUDA placement, patch, and lease-contract verification. Add TP4/DCP1 profiles for global safetensors and fastsafetensors. Both use seven DFlash tokens, draft TP4, FP8 target KV, 32 sequences, 256-token blocks, page-tail copy-on-write publication, and canonical SparkCache CUDA restore keys. Safetensors is implemented but unqualified on the composed image; fastsafetensors is research-only pending live draft-loading and peak-memory gates. Cache compatibility: the external DFlash weights digest and page-tail publication schema select a namespace distinct from embedded MTP and snapshot-v1 entries. The two loader profiles share model identity but use separate test roots and clear tokens. No wire value, digest salt, or logical geometry changes. Validation: 24 focused GPU-free tests passed; an exact prepared context verified 31 vLLM files and DFlash7 image labels; Ruff, Python compilation, JSON parsing, Bash syntax, git diff, and prose checks passed. A broader unchanged GLM README assertion remains failing at the stacked base.
Integrate the exact-input DFlash draft-load-config patch into the DFlash7 image pins, prepared-context receipt, rendered Containerfile, image labels, installed-source verifier, and profile resolver. The mixed profile now uses global fastsafetensors queue one for the target and speculative_config.draft_load_config=safetensors for the external DFlash draft. The conservative profile continues to use global safetensors. Both remain implemented but unqualified until four-rank live gates pass. Compatibility: target and draft checkpoint identities, page-tail publication schema, cache wire values, digest salts, and 256-token geometry are unchanged. The two loader profiles retain separate test roots and clear tokens while sharing the same model-state namespace. Validation: 29 focused tests passed; an exact prepared context recorded and verified one DFlash loader patch and DFlash7 labels; maintained suite reported 1,964 passed and 9 skipped with one unrelated stacked-base README assertion failure; Ruff, Python, JSON, Bash, diff, and prose checks passed.
This was referenced Aug 30, 2026
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FujitsuPolycom
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August 31, 2026 01:55
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Result
Stacks the exact DFlash7 image and TP4 profile artifacts on the DFlash draft-loader patch.
The DFlash7 image preparation carries the exact patch SHA-256 and installed postimage through pins, source-context receipts, the rendered Containerfile, OCI labels, and composed-runtime verification. Image metadata identifies external DFlash7 and does not claim adaptive MTP.
Loader profiles
Both profiles are implemented but unqualified until an immutable image passes four-rank target and draft loading, semantic generation, draft counters, SparkCache store and restore, CUDA restore, failure recovery, concurrency, and peak-memory gates.
Compatibility
Target and draft checkpoint identities, DFlash depth seven, draft TP4, FP8 target KV, 32 sequences, 256-token blocks, page-tail publication, cache wire values, digest salts, and logical geometry are unchanged. Loader variants share model-state identity but use separate qualification roots and clear tokens.
Validation
No image was built or published, and no service was modified.