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fix(callgrind): suppress L3 warning for explicit LL settings #52

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Merged
not-matthias merged 1 commit into from
Oct 20, 2026
Merged

fix(callgrind): suppress L3 warning for explicit LL settings #52

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9 changes: 9 additions & 0 deletions CODSPEED-CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,15 @@

This file documents changes made to Valgrind for CodSpeed integration, beyond the baseline Valgrind distribution.

## Fixes

### Cache simulation: suppress the host L3 warning for explicit LL settings

Callgrind and Cachegrind no longer print the warning about using the host's
last-level cache when `--LL` (or its `--L2` alias) supplies the cache configuration.
The warning remains when LL is auto-detected. Cache geometry and simulation
results are unchanged.

## Features

### Skip `.plt.sec` in `--skip-plt`
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10 changes: 6 additions & 4 deletions cachegrind/cg_arch.c
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,8 @@
#include "cg_arch.h"

static void configure_caches(cache_t* I1c, cache_t* D1c, cache_t* LLc,
Bool all_caches_clo_defined);
Bool all_caches_clo_defined,
Bool ll_clo_defined);

// Checks cache config is ok. Returns NULL if ok, or a pointer to an error
// string otherwise.
Expand Down Expand Up @@ -294,7 +295,8 @@ void VG_(post_clo_init_configure_caches)(cache_t* I1c,

// Set the cache config (using auto-detection, if supported by the
// architecture).
configure_caches( I1c, D1c, LLc, all_caches_clo_defined );
configure_caches( I1c, D1c, LLc, all_caches_clo_defined,
DEFINED(clo_LLc) );

maybe_tweak_LLc( LLc );

Expand Down Expand Up @@ -350,7 +352,7 @@ locate_cache(const VexCacheInfo *ci, VexCacheKind kind, UInt level)
// overridden by any cache configurations specified on the command line.
static void
configure_caches(cache_t *I1c, cache_t *D1c, cache_t *LLc,
Bool all_caches_clo_defined)
Bool all_caches_clo_defined, Bool ll_clo_defined)
{
VexArchInfo vai;
const VexCacheInfo *ci;
Expand All @@ -368,7 +370,7 @@ configure_caches(cache_t *I1c, cache_t *D1c, cache_t *LLc,
VG_(dmsg)("warning: L2 cache not installed, ignore LL results.\n");
}

if (ll && ci->num_levels > 2) {
if (ll && ci->num_levels > 2 && !ll_clo_defined) {
VG_(dmsg)("warning: L%u cache found, using its data for the "
"LL simulation.\n", ci->num_levels);
}
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