[AdaWorldAPI]

Summary

mul_add on the float wrappers now rounds once on every backend. This makes it IEEE 754 fusedMultiplyAdd: one rounding of the exact a * b + c, bit-identical across all eight realizations. Backend selection stays compile-time only (simd.rs → simd_{arch}.rs). No dependency is added.

Before this PR:

• wasm F32x16/F64x8 computed mul then add, which rounds twice. Under relaxed-simd they used relaxed_madd, which fuses on some engines and not others.
• Targets without an FMA instruction (scalar backend, x86-64-v2, AVX without FMA3) called f32::mul_add / f64::mul_add. There these lower to a call into the toolchain's compiler_builtins fma/fmaf, which picks its implementation at run time by CPUID (fma_with_fma / fma_with_fma4 / fma_fallback). That is run-time dispatch inside the polyfill, which the polyfill exists to rule out. It also put VEX FMA instructions into the v2 and AVX binaries, which simd-matrix's instruction scans correctly flagged.
• AVX2 F32x16/F64x8 ran mul_add as a scalar loop even when FMA3 was available.

The mul_add contract (reference for further SIMD work)

Result. a.mul_add(b, c) is the correctly rounded a * b + c, with round-to-nearest-even and one rounding. Subnormals are included, and NaN in gives NaN out. A backend that has the instruction must use it (FMA is mandatory where the CPU has it). A backend that lacks it must emulate it exactly, never as mul + add, and never through libm.

backend (selected in simd.rs)	F32x16 / F32x8	F64x8 / F64x4	scalar mul_add_f32/f64
AVX-512 (simd_avx512.rs)	_mm512_fmadd_ps	_mm512_fmadd_pd	mul_add → vfmadd
AVX2 + FMA3 (simd_avx2.rs, F32x8/F64x4 in simd_avx512.rs)	_mm256_fmadd_ps on each half	_mm256_fmadd_pd on each half	mul_add → vfmadd
AVX without FMA3, x86-64-v2, scalar (simd_scalar.rs)	exact emulation per lane (simd_fma::fma_f32)	exact emulation per lane (simd_fma::fma_f64)	the same
NEON (simd_neon.rs)	vfmaq_f32	vfmaq_f64	mul_add → fmadd
wasm simd128 (simd_wasm.rs)	f64 product + round-to-odd sum, vectorized	Dekker + round-to-odd, vectorized; out-of-range lanes go to simd_fma::fma_f64	simd_fma
nightly core::simd (simd_nightly/)	StdFloat::mul_add	StdFloat::mul_add	—

Where it lives.

• src/simd_fma.rs (new, pub(crate)) holds the one ExactFma trait. With target_feature = "fma" on x86, and on aarch64, it is mul_add, i.e. the hardware instruction. Otherwise it is the exact integer emulation:
  • fma_f32: the product is exact in f64. TwoSum gives the error of p + c, the sum is rounded to odd (one ulp toward the error when inexact and even), and the single rounding to f32 is then correct (Boldo & Melquiond, Emulation of FMA and correctly rounded sums: proved algorithms using rounding to odd, IEEE Trans. Computers 57(4), 2008).
  • fma_f64: the significands multiply exactly in a u128, c is aligned into the same window with a sticky bit, and the sum is rounded to nearest-even once, including into the subnormal range and overflow.
• crate::simd::mul_add_f32 / mul_add_f64 (in simd_ops.rs, re-exported from simd.rs) are the scalar entry points. Scalar tails such as add_mul_f32/f64 and the gemm_f64_tiled_fma tail now use them instead of hand-rolling f32::mul_add.
• wasm (simd_wasm.rs) keeps the vector path from the first commit:
  • F32x16: promote, exact f64 product, add_round_to_odd, demote.
  • F64x8: Dekker split (2^27 + 1), TwoSum, round-to-odd sum of the error terms, one final rounding.
  • That F64x8 path is exact only while the split cannot overflow or underflow (2^-460 <= |a|, |b| <= 2^460, |c| <= 2^960, finite, non-zero). A v128 pair with any lane outside that range goes lane by lane through simd_fma::fma_f64, no longer through f64::mul_add.

Reverted. An intermediate commit whitelisted the libm fma symbols in the simd-matrix instruction scans (a03450e, ebefc2f). That hid the run-time dispatch instead of removing it, and is reverted (b21226b, c6b285d). The workflow is identical to master.

Verification

• Parity group 0x11xx in crates/simd-masking-parity:

  • It compares each backend's mul_add bit-exactly against an independent reference, oracle_fma_f32 / oracle_fma_f64. The reference is a 4608-bit integer place-value sum and contains no mul_add.
  • Fixtures: random bit patterns over every exponent, near-cancelling c, exact f32 and f64 ties that a tiny c must break, exact f64 midpoints that must round to the even neighbour, and f64 lanes outside the wasm fast range.
  • Anti-vacuity: the unfused result must differ on at least 256 lanes per type.
  • oracle_tests checks the reference itself against hardware FMA.

• All 8 arms on b41760d, 18 groups bit-identical: native v4, native v3, avx-qemu (Sandy Bridge), v2-qemu (Nehalem), neon-qemu, wasm (simd128), wasm-scalar, nightly core::simd. Each arm prints its own CPU flags, and those were read.

• The unmodified simd-matrix scans on the parity binaries: v2 (%ymm|%zmm|%k[0-7]|VEX xmm) gives 0 hits. avx (AVX2 ymm integer ops, FMA3, F16C) gives 0 hits. objdump -t finds no fma_with_fma* symbol in either binary.

• simd_fma unit tests (on v4 against hardware mul_add; also run on v2): 200,000 f32 and 200,000 f64 random cases; more than 1000 of them must differ from unfused, so the test has teeth. Special values are checked too: every triple drawn from {±0, ±1, 1.5, 3, MIN_POSITIVE, ±smallest subnormal, ±MAX, ±inf, NaN}, which covers signed-zero sums, overflow and subnormal results.

• Disable runs, each red:

  removed	fails at
  wasm f32 round-to-odd (plain f64 add)	0x112e
  wasm f64 round-to-odd in the error-term sum	0x1150
  the whole wasm f32 path (unfused mul + add)	0x1110
  simd_fma::fma_f32 round-to-odd, on the v2 arm	0x112e, plus the simd_fma unit test
  simd_fma::fma_f64 ties-to-even → ties-away, on the v2 arm	0x1160, plus both simd_fma unit tests

  The last row first came back green in the parity group (the unit test alone caught it). Every f64 tie round added a tiny c that broke the tie, so the final rounding never saw an exact midpoint. Round 4 (b41760d) now cancels the product's middle terms, so a*b + c is exactly halfway between two f64 neighbours. The even neighbour is below on some lanes and above on others, in both signs, over 2^±900. The D2 row was re-run after that change and still fails at 0x1150. The two f32 wasm rows were run before b41760d, which does not touch the f32 rounds. All disable runs were done before the rebase onto simd: saturating narrows down the 512-bit ladder (16x32 -> 32x16 -> 64x8) #373. The rebase only merged the narrow ladder next to this code; the mul_add paths are unchanged.

• Clippy --all-targets -D warnings on v4, v3 and v2: clean. No-std (--no-default-features, also with approx,serde) under -D warnings: clean. simd_fma is gated on std like every module that uses it (a119298). The CI no-std jobs had failed on b27d401 because of this.

• Codegen on b41760d (probe crate, objdump): on v4 mul_add_f32/f64 is one vfmadd213ss/sd, and F32x16/F64x8::mul_add is one vfmadd on zmm. On v3 the scalar entry points are one vfmadd213ss/sd, and the vectors are two vfmadd213ps/pd on ymm (the halves). On v2 there is no FMA instruction and no libm call: the f32 emulation is inlined, and F64x8 calls simd_fma::fma_f64 per lane. With constant arguments, v4/v3 and the v2 f32 path fold to the constant; the v2 f64 path does not (see below).

• Scalar call sites: the 9 scalar f32/f64::mul_add calls in src/hpc (randomized_signature, signature_pde, renderer) and the two lane loops of BF16x16/F16x16::fma now call simd::mul_add_f32/f64 (efdc7d3). Their module tests pass on v2, where the emulation is the active path (68 tests).

Not covered

• On targets without FMA, simd_fma::fma_f64 (u128 integer path) does not constant-fold. A call with constant arguments stays a runtime call there, and F64x8::mul_add makes 8 out-of-line calls per vector.
• No timing was taken. The emulated paths are much slower than the instruction and exist only where there is no instruction.
• The F16/BF16 fma in simd_half still rounds twice. That is a separate issue.
• numeric/impl_numeric.rs (var/std) calls the generic num_traits::Float::mul_add. On a no-FMA build that still reaches compiler_builtins. It is generic upstream ndarray code and is not changed here.
• The nightly arm's StdFloat::mul_add was only verified with FMA (v4). It was not checked on a build without FMA.
• Rebased onto master after simd: saturating narrows down the 512-bit ladder (16x32 -> 32x16 -> 64x8) #373 (the narrow ladder) merged; the parity group list now carries both check_narrow_ladder and check_mul_add_single_rounding.

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https://claude.ai/code/session_01G22yT6htkcdyXsihxxXdrg

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