[AdaWorldAPI]

Found while building the ONNX facade in lance-graph (#1754): vml::vsneg could not be an alias for ONNX Neg, and vml::vsexp was wrong at +inf. Every existing test of these kernels used fewer than 16 elements, so none ever reached the 16-lane SIMD body.

Defects (each reproduced by a failing test before its fix)

kernel	input	before	after
vsneg	+0.0	+0.0	-0.0
vsceil	-0.5, -0.0	+0.0	-0.0
vstrunc	-0.5, -0.0	+0.0	-0.0
vsexp / simd_exp_f32	+inf, 200	1.7e38	+inf
vsexp	x > ~88.38	half the true value (n clamped to 127)	correct up to ln(f32::MAX)
vsexp	-inf, x < -87.34	~1.18e-38	+0.0, with correct subnormals in between
vsround (AVX2/scalar/nightly arms)	0.5, 2.5, -0.5	1.0, 3.0, -1.0 (body ≠ its own round_ties_even tail)	0.0, 2.0, -0.0
GELU (models::layers::gelu, gpt2 gelu_simd)	x ≳ 10 once exp overflows to +inf	NaN (inf/inf)	x

Changes

• neg / ceil / trunc: the SIMD bodies computed 0.0 - v. They now use Neg, which flips the sign bit on every backend.
• simd_exp_f32:
  • The clamp is now [-110, ln(f32::MAX)]. Lanes with n = 128 use 2^(n-1)·2; lanes with n < -126 use 2^(n+64)·2^-64. Each first product is exact, so each result is rounded once.
  • Range reduction uses a Cody–Waite ln2 hi/lo split (LN2_HI = 355/512, 9 significant bits, so n·LN2_HI and x − n·LN2_HI are exact).
• Bit-identical across backends. This follows the rule gemm_f64_tiled in simd_ops already uses for its reference tier:
  • exp uses plain * and +, never mul_add. Vector mul_add is fused on AVX-512, AVX2+FMA, NEON, scalar and nightly, but unfused on wasm; with relaxed-simd its fusion is implementation-defined.
  • n = floor(x/ln2 + 0.5) instead of round(). round broke ties differently per backend (next item).
  • The Cody–Waite split already makes the fused form unnecessary for accuracy.
• F32x16/F64x8::round breaks ties to even on every backend. AVX2, scalar and nightly used f32::round (ties away from zero); AVX-512 roundscale, NEON and wasm already used ties-to-even, and the docs already said so.
• GELU: tanh is now computed as 1 − 2/(e+1).
• Re-pinned: three simd::tests asserted the old saturating exp contract. They now assert IEEE +inf / +inf / +0.0.
• wasm parity self-check: gains check_exp_and_round, which runs under node. Return code 70 means exp ≠ the unfused scalar sequence bit for bit; 71 means round does not break ties to even.

Evidence

• Tests landed first, in separate commits: 896d287 (5 failing on master) and 4519689 (vsround: red on the AVX2 arm, green on AVX-512).
• Native: simd_exp_f32_matches_the_unfused_scalar_sequence_bit_for_bit checks every lane against the same op sequence in scalar f32. Disables: round() instead of floor, a fused lo step, and a fused Horner each turn it red.
• wasm (node): the self-check passes. With round() back in, it fails with rc=70. Together with the native test, this gives exp wasm == native bit for bit. scripts/masking-parity.sh wasm still passes.
• Accuracy disables (each red): a single-constant ln2 fails the accuracy test at x = −90.45; dropping the n−1 path halves vsexp(88.38); dropping the n+64 path gives vsexp(-inf) = 1.45e-38. An explicit overflow mask stayed green under its disable, so it was removed as unreachable.
• cargo test --release --lib: native (AVX-512) 2586 passed; --config .cargo/config-v3.toml (AVX2) 2535 passed. Clippy -D warnings and fmt are clean.
• Not run locally: the NEON arm, and the nightly backend (no nightly toolchain here; CI's nightly check row covers the per-lane round_ties_even change).

Not changed (findings, for review)

Census of all 79 non-test mul_add sites. Scalar f32::mul_add is fused on wasm too, so only vector mul_add diverges.

• Wasm-reachable sites whose result feeds a discrete choice: hpc::cam_pq::squared_l2 (codebook argmin), and the gpt2/openchat logits (greedy argmax).
• An unfused tier alone would not make those bit-identical, because they also use reduce_sum, whose order differs on wasm (balanced tree).
• Fixing them needs a reference tier with a fixed reduction order, like gemm_f64_tiled. That is a separate decision.
• simd_half's BF16/F16 fma uses scalar f32::mul_add and RNE conversion, so it is already consistent.

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