From 9c4d2a4ff496fb69568181035b6330000c4f24c8 Mon Sep 17 00:00:00 2001 From: Arjan Date: Tue, 23 Jun 2026 15:34:08 +0200 Subject: [PATCH 01/31] Bump GD32F30x SPL to v3.0.3 and API fixes Upgrade GD32F30x standard peripheral headers/sources to firmware V3.0.3 (2026). Updates include copyright year bumps and header version tags. ADC: renamed many occurrences of "regular" to "routine" (comments, macros and flags), adjusted ADC register/macro names and renamed several APIs (e.g. adc_regular_channel_config -> adc_routine_channel_config, adc_regular_data_read -> adc_routine_data_read) and related parameter name changes. CAN: fix incorrect filter register offsets, correct numerous typos in identifiers/comments, adjust struct/type names (can_trasnmit_message_struct -> can_transmit_message_struct), add mailbox-empty mask, and change some API signatures/return types. DAC: refactor register/macros to per-DAC-instance style (DAC_CTL0, DAC_SWT(dacx), DAC_OUT0_R12DH, etc.), simplify device count to DAC0, and update related bitfield macros and trigger defines. Miscellaneous cleanups across peripheral headers/sources for consistency and correctness. --- .../Include/gd32f30x_adc.h | 154 +- .../Include/gd32f30x_bkp.h | 7 +- .../Include/gd32f30x_can.h | 33 +- .../Include/gd32f30x_crc.h | 7 +- .../Include/gd32f30x_ctc.h | 7 +- .../Include/gd32f30x_dac.h | 299 +- .../Include/gd32f30x_dbg.h | 7 +- .../Include/gd32f30x_dma.h | 7 +- .../Include/gd32f30x_enet.h | 38 +- .../Include/gd32f30x_exmc.h | 7 +- .../Include/gd32f30x_exti.h | 7 +- .../Include/gd32f30x_fmc.h | 7 +- .../Include/gd32f30x_fwdgt.h | 7 +- .../Include/gd32f30x_gpio.h | 20 +- .../Include/gd32f30x_i2c.h | 8 +- .../Include/gd32f30x_misc.h | 114 +- .../Include/gd32f30x_pmu.h | 9 +- .../Include/gd32f30x_rcu.h | 7 +- .../Include/gd32f30x_rtc.h | 7 +- .../Include/gd32f30x_sdio.h | 7 +- .../Include/gd32f30x_spi.h | 9 +- .../Include/gd32f30x_timer.h | 7 +- .../Include/gd32f30x_usart.h | 7 +- .../Include/gd32f30x_wwdgt.h | 7 +- .../Source/gd32f30x_adc.c | 234 +- .../Source/gd32f30x_bkp.c | 21 +- .../Source/gd32f30x_can.c | 173 +- .../Source/gd32f30x_crc.c | 12 +- .../Source/gd32f30x_ctc.c | 30 +- .../Source/gd32f30x_dac.c | 465 ++- .../Source/gd32f30x_dbg.c | 13 +- .../Source/gd32f30x_dma.c | 13 +- .../Source/gd32f30x_enet.c | 2557 +++++++++-------- .../Source/gd32f30x_exmc.c | 19 +- .../Source/gd32f30x_exti.c | 27 +- .../Source/gd32f30x_fmc.c | 52 +- .../Source/gd32f30x_fwdgt.c | 99 +- .../Source/gd32f30x_gpio.c | 37 +- .../Source/gd32f30x_i2c.c | 27 +- .../Source/gd32f30x_misc.c | 206 +- .../Source/gd32f30x_pmu.c | 26 +- .../Source/gd32f30x_rcu.c | 23 +- .../Source/gd32f30x_rtc.c | 13 +- .../Source/gd32f30x_sdio.c | 24 +- .../Source/gd32f30x_spi.c | 32 +- .../Source/gd32f30x_timer.c | 37 +- .../Source/gd32f30x_usart.c | 19 +- .../Source/gd32f30x_wwdgt.c | 14 +- 48 files changed, 2650 insertions(+), 2312 deletions(-) diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h index 7b0be2e9..35ba1689 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_adc.h @@ -2,14 +2,11 @@ \file gd32f30x_adc.h \brief definitions for the ADC - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -59,24 +56,24 @@ OF SUCH DAMAGE. #define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ #define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ #define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC routine sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC routine sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC routine sequence register 2 */ #define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ #define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ #define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ #define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ #define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC routine data register */ #define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */ /* bits definitions */ /* ADC_STAT */ #define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of sequence conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< end of inserted sequence conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted sequence start flag */ +#define ADC_STAT_STRC BIT(4) /*!< routine sequence start flag */ /* ADC_CTL0 */ #define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ @@ -85,13 +82,13 @@ OF SUCH DAMAGE. #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ #define ADC_CTL0_SM BIT(8) /*!< scan mode */ #define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted sequence conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */ #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ #define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ #define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on routine channels */ #define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ /* ADC_CTL1 */ @@ -103,10 +100,10 @@ OF SUCH DAMAGE. #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ #define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ -#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for routine channel */ #define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ -#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on routine channel */ #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ /* ADC_SAMPTx x=0..1 */ @@ -122,19 +119,19 @@ OF SUCH DAMAGE. #define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ /* ADC_RSQx */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in routine sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< routine sequence length */ /* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in inserted sequence */ #define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ /* ADC_IDATAx x=0..3*/ #define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */ /* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ -#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< routine data */ +#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 routine channel data */ /* ADC_OVSAMPCTL */ #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ @@ -147,57 +144,57 @@ OF SUCH DAMAGE. /* constants definitions */ /* ADC status flag */ #define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted sequence start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< routine sequence start flag */ /* adc_ctl0 register value */ #define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ /* ADC special function definitions */ #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */ #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ /* ADC synchronization mode */ #define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ -#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ -#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined routine parallel + inserted parallel mode */ +#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined routine parallel + trigger rotation mode */ +#define ADC_DAUL_INSERTED_PARALLEL_ROUTINE_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ +#define ADC_DAUL_INSERTED_PARALLEL_ROUTINE_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ #define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ -#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ -#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ -#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ +#define ADC_DAUL_ROUTINE_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in routine parallel mode only */ +#define ADC_DAUL_ROUTINE_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ +#define ADC_DAUL_ROUTINE_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ +#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ /* ADC data alignment */ #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ -/* ADC external trigger select for regular channel */ +/* ADC external trigger select for routine sequence */ #define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< timer 2 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< timer 3 CC3 event select */ -#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< timer 7 TRGO event select */ -#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ -#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ - -#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< timer 2 CC0 event select */ -#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< timer 1 CC2 event select */ -#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ -#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< timer 7 CC0 event select */ -#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< timer 7 TRGO event select */ -#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< timer 4 CC0 event select */ -#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< timer 4 CC2 event select */ - -/* ADC external trigger select for inserted channel */ +#define ADC0_1_EXTTRIG_ROUTINE_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */ +#define ADC0_1_EXTTRIG_ROUTINE_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */ +#define ADC0_1_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC0_1_EXTTRIG_ROUTINE_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */ +#define ADC0_1_EXTTRIG_ROUTINE_T2_TRGO CTL1_ETSRC(4) /*!< timer 2 TRGO event select */ +#define ADC0_1_EXTTRIG_ROUTINE_T3_CH3 CTL1_ETSRC(5) /*!< timer 3 CC3 event select */ +#define ADC0_1_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(6) /*!< timer 7 TRGO event select */ +#define ADC0_1_EXTTRIG_ROUTINE_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC0_1_2_EXTTRIG_ROUTINE_NONE CTL1_ETSRC(7) /*!< software trigger */ + +#define ADC2_EXTTRIG_ROUTINE_T2_CH0 CTL1_ETSRC(0) /*!< timer 2 CC0 event select */ +#define ADC2_EXTTRIG_ROUTINE_T1_CH2 CTL1_ETSRC(1) /*!< timer 1 CC2 event select */ +#define ADC2_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */ +#define ADC2_EXTTRIG_ROUTINE_T7_CH0 CTL1_ETSRC(3) /*!< timer 7 CC0 event select */ +#define ADC2_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(4) /*!< timer 7 TRGO event select */ +#define ADC2_EXTTRIG_ROUTINE_T4_CH0 CTL1_ETSRC(5) /*!< timer 4 CC0 event select */ +#define ADC2_EXTTRIG_ROUTINE_T4_CH2 CTL1_ETSRC(6) /*!< timer 4 CC2 event select */ + +/* ADC external trigger select for inserted sequence */ #define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */ #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */ @@ -278,12 +275,11 @@ OF SUCH DAMAGE. #define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ #define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ - -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ +/* ADC channel sequence definitions */ +#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< adc routine sequence */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted sequence */ +#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted sequence */ /* ADC inserted channel definitions */ #define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ @@ -313,13 +309,13 @@ OF SUCH DAMAGE. /* ADC interrupt */ #define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt */ /* ADC interrupt flag */ #define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt flag */ /* function declarations */ /* reset ADC */ @@ -342,7 +338,7 @@ void adc_tempsensor_vrefint_disable(void); /* configure ADC resolution */ void adc_resolution_config(uint32_t adc_periph , uint32_t resolution); /* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); +void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_sequence , uint8_t length); /* configure the ADC mode */ void adc_mode_config(uint32_t mode); @@ -350,24 +346,24 @@ void adc_mode_config(uint32_t mode); void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); /* configure ADC data alignment */ void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); +/* configure the length of routine sequence or inserted sequence */ +void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t length); +/* configure ADC routine channel */ +void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); /* configure ADC inserted channel */ void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); /* configure ADC inserted channel offset */ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); /* enable ADC external trigger */ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_sequence, ControlStatus newvalue); /* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t external_trigger_source); /* enable ADC software trigger */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence); -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(uint32_t adc_periph); -/* read ADC inserted group data register */ +/* read ADC routine sequence data register */ +uint16_t adc_routine_data_read(uint32_t adc_periph); +/* read ADC inserted sequence data register */ uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); /* read the last ADC0 and ADC1 conversion result data in sync mode */ uint32_t adc_sync_mode_convert_value_read(void); @@ -387,8 +383,8 @@ void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt); /* configure ADC analog watchdog single channel */ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); +/* configure ADC analog watchdog sequence channel */ +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph, uint8_t adc_sequence); /* disable ADC analog watchdog */ void adc_watchdog_disable(uint32_t adc_periph); /* configure ADC analog watchdog threshold */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h index a249c7d2..ea5ed987 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_bkp.h @@ -2,14 +2,11 @@ \file gd32f30x_bkp.h \brief definitions for the BKP - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_can.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_can.h index f6d4fb28..1cffb474 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_can.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_can.h @@ -2,15 +2,11 @@ \file gd32f30x_can.h \brief definitions for the CAN - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2019-11-27, V2.0.1, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -102,7 +98,7 @@ OF SUCH DAMAGE. #define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */ #define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */ #define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */ -#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x000002F8U) /*!< CAN filter 23 data 0 register */ #define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */ #define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */ #define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */ @@ -124,7 +120,7 @@ OF SUCH DAMAGE. #define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */ #define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */ #define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */ -#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x000002CCU) /*!< CAN filter 17 data 1 register */ #define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */ #define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */ #define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */ @@ -396,7 +392,7 @@ typedef enum { CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ } can_interrupt_flag_enum; -/* CAN initiliaze parameters structure */ +/* CAN initialize parameters structure */ typedef struct { uint8_t working_mode; /*!< CAN working mode */ uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ @@ -419,7 +415,7 @@ typedef struct { uint8_t tx_ft; /*!< type of frame, data or remote */ uint8_t tx_dlen; /*!< data length */ uint8_t tx_data[8]; /*!< transmit data */ -} can_trasnmit_message_struct; +} can_transmit_message_struct; /* CAN receive message structure */ typedef struct { @@ -449,12 +445,12 @@ typedef struct { typedef enum { CAN_ERROR_NONE = 0, /*!< no error */ CAN_ERROR_FILL, /*!< fill error */ - CAN_ERROR_FORMATE, /*!< format error */ + CAN_ERROR_FORMAT, /*!< format error */ CAN_ERROR_ACK, /*!< ACK error */ CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ - CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ + CAN_ERROR_BITDOMINANT, /*!< bit dominant error */ CAN_ERROR_CRC, /*!< CRC error */ - CAN_ERROR_SOFTWARECFG, /*!< software configure */ + CAN_ERROR_SOFTWARECFG, /*!< software configuration */ } can_error_enum; /* transmit states */ @@ -466,7 +462,7 @@ typedef enum { } can_transmit_state_enum; typedef enum { - CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ + CAN_INIT_STRUCT = 0U, /* CAN initialize parameters struct */ CAN_FILTER_STRUCT, /* CAN filter parameters struct */ CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ @@ -590,7 +586,7 @@ typedef enum { #define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ #define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ -/* CAN resynchronisation jump width */ +/* CAN resynchronization jump width */ #define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ #define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ #define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ @@ -667,6 +663,9 @@ typedef enum { /* CAN timeout */ #define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ +/* CAN mailbox empty status mask */ +#define CAN_ALL_MAILBOX_EMPTY ((uint32_t)0x1C000000U) /*!< CAN mailbox empty status mask */ + /* interrupt enable bits */ #define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ #define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ @@ -709,11 +708,11 @@ void can_time_trigger_mode_disable(uint32_t can_periph); /* transmit functions */ /* transmit CAN message */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); +uint8_t can_message_transmit(uint32_t can_periph, can_transmit_message_struct *transmit_message); /* get CAN transmit state */ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); /* stop CAN transmission */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); +ErrStatus can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); /* CAN receive message */ void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); /* CAN release FIFO */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h index a92db6af..f4c4183c 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_crc.h @@ -2,14 +2,11 @@ \file gd32f30x_crc.h \brief definitions for the CRC - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h index 61efe688..04b77647 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_ctc.h @@ -2,14 +2,11 @@ \file gd32f30x_ctc.h \brief definitions for the CTC - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h index 8563095d..afa3e2e5 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dac.h @@ -1,15 +1,12 @@ /*! \file gd32f30x_dac.h \brief definitions for the DAC - - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,211 +37,213 @@ OF SUCH DAMAGE. #include "gd32f30x.h" -/* DACx(x=0,1) definitions */ -#define DAC DAC_BASE -#define DAC0 0U -#define DAC1 1U +/* DACx(x=0) definitions */ +#define DAC0 (DAC_BASE) /* registers definitions */ -#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ -#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ -#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ -#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ -#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ -#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ -#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ -#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ -#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ -#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ -#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ -#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ -#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ +#define DAC_CTL0(dacx) REG32((dacx) + 0x00000000U) /*!< DACx control register 0 */ +#define DAC_SWT(dacx) REG32((dacx) + 0x00000004U) /*!< DACx software trigger register */ + +#define DAC_OUT0_R12DH(dacx) REG32((dacx) + 0x00000008U) /*!< DACx_OUT0 12-bit right-aligned data holding register */ +#define DAC_OUT0_L12DH(dacx) REG32((dacx) + 0x0000000CU) /*!< DACx_OUT0 12-bit left-aligned data holding register */ +#define DAC_OUT0_R8DH(dacx) REG32((dacx) + 0x00000010U) /*!< DACx_OUT0 8-bit right-aligned data holding register */ +#define DAC_OUT1_R12DH(dacx) REG32((dacx) + 0x00000014U) /*!< DACx_OUT1 12-bit right-aligned data holding register */ +#define DAC_OUT1_L12DH(dacx) REG32((dacx) + 0x00000018U) /*!< DACx_OUT1 12-bit left-aligned data holding register */ +#define DAC_OUT1_R8DH(dacx) REG32((dacx) + 0x0000001CU) /*!< DACx_OUT1 8-bit right-aligned data holding register */ +#define DACC_R12DH(dacx) REG32((dacx) + 0x00000020U) /*!< DACx concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH(dacx) REG32((dacx) + 0x00000024U) /*!< DACx concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH(dacx) REG32((dacx) + 0x00000028U) /*!< DACx concurrent mode 8-bit right-aligned data holding register */ +#define DAC_OUT0_DO(dacx) REG32((dacx) + 0x0000002CU) /*!< DACx_OUT0 data output register */ +#define DAC_OUT1_DO(dacx) REG32((dacx) + 0x00000030U) /*!< DACx_OUT1 data output register */ /* bits definitions */ -/* DAC_CTL */ -#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ -#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ -#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ -#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ -#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ -#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ -#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ -#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ -#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ -#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ -#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ -#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ +/* DAC_CTL0 */ +#define DAC_CTL0_DEN0 BIT(0) /*!< DACx_OUT0 enable */ +#define DAC_CTL0_DBOFF0 BIT(1) /*!< DACx_OUT0 output buffer turn off */ +#define DAC_CTL0_DTEN0 BIT(2) /*!< DACx_OUT0 trigger enable */ +#define DAC_CTL0_DTSEL0 BITS(3,5) /*!< DACx_OUT0 trigger selection */ +#define DAC_CTL0_DWM0 BITS(6,7) /*!< DACx_OUT0 noise wave mode */ +#define DAC_CTL0_DWBW0 BITS(8,11) /*!< DACx_OUT0 noise wave bit width */ +#define DAC_CTL0_DDMAEN0 BIT(12) /*!< DACx_OUT0 DMA enable */ + +#define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable */ +#define DAC_CTL0_DBOFF1 BIT(17) /*!< DACx_OUT1 output buffer turn off */ +#define DAC_CTL0_DTEN1 BIT(18) /*!< DACx_OUT1 trigger enable */ +#define DAC_CTL0_DTSEL1 BITS(19,21) /*!< DACx_OUT1 trigger selection */ +#define DAC_CTL0_DWM1 BITS(22,23) /*!< DACx_OUT1 noise wave mode */ +#define DAC_CTL0_DWBW1 BITS(24,27) /*!< DACx_OUT1 noise wave bit width */ +#define DAC_CTL0_DDMAEN1 BIT(28) /*!< DACx_OUT1 DMA enable */ /* DAC_SWT */ -#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ -#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DACx_OUT0 software trigger */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DACx_OUT1 software trigger */ -/* DAC0_R12DH */ -#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ +/* DAC_OUT0_R12DH */ +#define DAC_OUT0_DH_R12 BITS(0,11) /*!< DACx_OUT0 12-bit right-aligned data */ -/* DAC0_L12DH */ -#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ +/* DAC_OUT0_L12DH */ +#define DAC_OUT0_DH_L12 BITS(4,15) /*!< DACx_OUT0 12-bit left-aligned data */ -/* DAC0_R8DH */ -#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ +/* DAC_OUT0_R8DH */ +#define DAC_OUT0_DH_R8 BITS(0,7) /*!< DACx_OUT0 8-bit right-aligned data */ -/* DAC1_R12DH */ -#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ +/* DAC_OUT1_R12DH */ +#define DAC_OUT1_DH_R12 BITS(0,11) /*!< DACx_OUT1 12-bit right-aligned data */ -/* DAC1_L12DH */ -#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ +/* DAC_OUT1_L12DH */ +#define DAC_OUT1_DH_L12 BITS(4,15) /*!< DACx_OUT1 12-bit left-aligned data */ -/* DAC1_R8DH */ -#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ +/* DAC_OUT1_R8DH */ +#define DAC_OUT1_DH_R8 BITS(0,7) /*!< DACx_OUT1 8-bit right-aligned data */ /* DACC_R12DH */ -#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ -#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ +#define DACC_OUT0_DH_R12 BITS(0,11) /*!< DAC concurrent mode DACx_OUT0 12-bit right-aligned data */ +#define DACC_OUT1_DH_R12 BITS(16,27) /*!< DAC concurrent mode DACx_OUT1 12-bit right-aligned data */ /* DACC_L12DH */ -#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ -#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ +#define DACC_OUT0_DH_L12 BITS(4,15) /*!< DAC concurrent mode DACx_OUT0 12-bit left-aligned data */ +#define DACC_OUT1_DH_L12 BITS(20,31) /*!< DAC concurrent mode DACx_OUT1 12-bit left-aligned data */ /* DACC_R8DH */ -#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ -#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ +#define DACC_OUT0_DH_R8 BITS(0,7) /*!< DAC concurrent mode DACx_OUT0 8-bit right-aligned data */ +#define DACC_OUT1_DH_R8 BITS(8,15) /*!< DAC concurrent mode DACx_OUT1 8-bit right-aligned data */ -/* DAC0_DO */ -#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ +/* DAC_OUT0_DO */ +#define DAC_OUT0_DO_BITS BITS(0,11) /*!< DACx_OUT0 12-bit output data */ -/* DAC1_DO */ -#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ +/* DAC_OUT1_DO */ +#define DAC_OUT1_DO_BITS BITS(0,11) /*!< DACx_OUT1 12-bit output data */ /* constants definitions */ /* DAC trigger source */ -#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define CTL0_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL0_DTSEL(0) /*!< TIMER5 TRGO */ #if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) -#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */ +#define DAC_TRIGGER_T7_TRGO CTL0_DTSEL(1) /*!< TIMER7 TRGO */ #elif defined(GD32F30X_CL) -#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ +#define DAC_TRIGGER_T2_TRGO CTL0_DTSEL(1) /*!< TIMER2 TRGO */ #endif /* GD32F30X_HD and GD32F30X_XD */ -#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ -#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ -#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ -#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ -#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ -#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ +#define DAC_TRIGGER_T6_TRGO CTL0_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL0_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL0_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL0_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL0_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL0_DTSEL(7) /*!< software trigger */ /* DAC noise wave mode */ -#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) -#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ -#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ -#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ +#define CTL0_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL0_DWM(0) /*!< wave disabled */ +#define DAC_WAVE_MODE_LFSR CTL0_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL0_DWM(2) /*!< triangle noise mode */ /* DAC noise wave bit width */ -#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ -#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ -#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ -#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ -#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ -#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ -#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ -#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ -#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ -#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ -#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ -#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ +#define DWBW(regval) (BITS(8, 11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ /* unmask LFSR bits in DAC LFSR noise mode */ -#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ -#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ -#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ -#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ -#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ -#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ -#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ -#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ -#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ -#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ -#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ -#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ /* DAC data alignment */ -#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ -#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ -#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< 12-bit right-aligned data */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< 12-bit left-aligned data */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< 8-bit right-aligned data */ -/* triangle amplitude in DAC triangle noise mode */ -#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ -#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ -#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ -#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ -#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ -#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ -#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ -#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ -#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ -#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ -#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ -#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ +/* DAC output channel definitions */ +#define DAC_OUT0 ((uint8_t)0x00U) /*!< DACx_OUT0 channel */ +#define DAC_OUT1 ((uint8_t)0x01U) /*!< DACx_OUT1 channel */ /* function declarations */ -/* initialization functions */ +/* DAC initialization functions */ /* deinitialize DAC */ -void dac_deinit(void); +void dac_deinit(uint32_t dac_periph); /* enable DAC */ -void dac_enable(uint32_t dac_periph); +void dac_enable(uint32_t dac_periph, uint8_t dac_out); /* disable DAC */ -void dac_disable(uint32_t dac_periph); -/* enable DAC DMA */ -void dac_dma_enable(uint32_t dac_periph); -/* disable DAC DMA */ -void dac_dma_disable(uint32_t dac_periph); +void dac_disable(uint32_t dac_periph, uint8_t dac_out); +/* enable DAC DMA function */ +void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out); +/* disable DAC DMA function */ +void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out); + +/* DAC buffer functions */ /* enable DAC output buffer */ -void dac_output_buffer_enable(uint32_t dac_periph); +void dac_output_buffer_enable(uint32_t dac_periph, uint8_t dac_out); /* disable DAC output buffer */ -void dac_output_buffer_disable(uint32_t dac_periph); -/* get the last data output value */ -uint16_t dac_output_value_get(uint32_t dac_periph); +void dac_output_buffer_disable(uint32_t dac_periph, uint8_t dac_out); + +/* read and write operation functions */ +/* get DAC output value */ +uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out); /* set DAC data holding register value */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); +void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data); /* DAC trigger configuration */ /* enable DAC trigger */ -void dac_trigger_enable(uint32_t dac_periph); +void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out); /* disable DAC trigger */ -void dac_trigger_disable(uint32_t dac_periph); +void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out); /* configure DAC trigger source */ -void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource); /* enable DAC software trigger */ -void dac_software_trigger_enable(uint32_t dac_periph); -/* disable DAC software trigger */ -void dac_software_trigger_disable(uint32_t dac_periph); +void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out); /* DAC wave mode configuration */ /* configure DAC wave mode */ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); -/* configure DAC wave bit width */ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); +void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode); /* configure DAC LFSR noise mode */ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); +void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits); /* configure DAC triangle noise mode */ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); +void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude); /* DAC concurrent mode configuration */ /* enable DAC concurrent mode */ -void dac_concurrent_enable(void); +void dac_concurrent_enable(uint32_t dac_periph); /* disable DAC concurrent mode */ -void dac_concurrent_disable(void); +void dac_concurrent_disable(uint32_t dac_periph); /* enable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_enable(void); -/* disable DAC concurrent software trigger */ -void dac_concurrent_software_trigger_disable(void); +void dac_concurrent_software_trigger_enable(uint32_t dac_periph); /* enable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_enable(void); +void dac_concurrent_output_buffer_enable(uint32_t dac_periph); /* disable DAC concurrent buffer function */ -void dac_concurrent_output_buffer_disable(void); +void dac_concurrent_output_buffer_disable(uint32_t dac_periph); /* set DAC concurrent mode data holding register value */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); +void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data0, uint16_t data1); #endif /* GD32F30X_DAC_H */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h index bd273326..4721cc24 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dbg.h @@ -2,14 +2,11 @@ \file gd32f30x_dbg.h \brief definitions for the DBG - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h index bda47875..29b42cb3 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_dma.h @@ -2,14 +2,11 @@ \file gd32f30x_dma.h \brief definitions for the DMA - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h index 5b050d5e..65ff502a 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h @@ -2,15 +2,11 @@ \file gd32f30x_enet.h \brief definitions for the ENET - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-04-02, V2.0.1, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -62,9 +58,13 @@ OF SUCH DAMAGE. #define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ #endif -/* #define SELECT_DESCRIPTORS_ENHANCED_MODE */ +#ifndef SELECT_DESCRIPTORS_ENHANCED_MODE +#define SELECT_DESCRIPTORS_ENHANCED_MODE 0 +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ -/* #define USE_DELAY */ +#ifndef USE_DELAY +#define USE_DELAY 0 +#endif /* USE_DELAY */ #ifndef _PHY_H_ #define DP83848 0 @@ -550,7 +550,7 @@ OF SUCH DAMAGE. /* ENET DMA Tx descriptor TDES3 */ #define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#if SELECT_DESCRIPTORS_ENHANCED_MODE /* ENET DMA Tx descriptor TDES6 */ #define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ @@ -594,7 +594,7 @@ OF SUCH DAMAGE. /* ENET DMA Rx descriptor RDES3 */ #define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#if SELECT_DESCRIPTORS_ENHANCED_MODE /* ENET DMA Rx descriptor RDES4 */ #define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ #define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ @@ -974,7 +974,7 @@ typedef struct uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#if SELECT_DESCRIPTORS_ENHANCED_MODE uint32_t extended_status; /*!< extended status */ uint32_t reserved; /*!< reserved */ uint32_t timestamp_low; /*!< timestamp low */ @@ -1231,7 +1231,7 @@ typedef struct #define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ #define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ -#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ +#define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is substracted from system time */ /* ptp_ppsctl register value */ #define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ @@ -1419,7 +1419,7 @@ typedef struct #define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ #define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#if SELECT_DESCRIPTORS_ENHANCED_MODE #define ETH_DMATXDESC_SIZE 0x20U /*!< TxDMA enhanced descriptor size */ #define ETH_DMARXDESC_SIZE 0x20U /*!< RxDMA enhanced descriptor size */ #else @@ -1540,10 +1540,10 @@ ErrStatus enet_phyloopback_disable(void); void enet_forward_feature_enable(uint32_t feature); /* disable ENET forward feature */ void enet_forward_feature_disable(uint32_t feature); -/* enable ENET fliter feature */ -void enet_fliter_feature_enable(uint32_t feature); -/* disable ENET fliter feature */ -void enet_fliter_feature_disable(uint32_t feature); +/* enable ENET filter feature */ +void enet_filter_feature_enable(uint32_t feature); +/* disable ENET filter feature */ +void enet_filter_feature_disable(uint32_t feature); /* flow control function */ /* generate the pause frame, ENET will send pause frame after enable transmit flow control */ @@ -1595,7 +1595,7 @@ void enet_dma_feature_disable(uint32_t feature); /* special enhanced mode function */ -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#if SELECT_DESCRIPTORS_ENHANCED_MODE /* get the bit of extended status flag in ENET DMA descriptor */ uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status); /* configure descriptor to work in enhanced mode */ @@ -1691,7 +1691,7 @@ FlagStatus enet_ptp_flag_get(uint32_t flag); /* internal function */ /* reset the ENET initpara struct, call it before using enet_initpara_config() */ void enet_initpara_reset(void); -#ifdef USE_DELAY +#if USE_DELAY /* user can provide more timing precise _ENET_DELAY_ function */ #define _ENET_DELAY_ delay_ms #else diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h index fcc55c2a..f36e0688 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_exmc.h @@ -2,14 +2,11 @@ \file gd32f30x_exmc.h \brief definitions for the EXMC - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h index ae92ee6a..9e424e9f 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_exti.h @@ -2,14 +2,11 @@ \file gd32f30x_exti.h \brief definitions for the EXTI - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h index e6e97df0..622f12db 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_fmc.h @@ -2,14 +2,11 @@ \file gd32f30x_fmc.h \brief definitions for the FMC - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h index 8df53c7c..f3006367 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_fwdgt.h @@ -2,14 +2,11 @@ \file gd32f30x_fwdgt.h \brief definitions for the FWDGT - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h index 4054b7bc..9b8be77c 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_gpio.h @@ -2,14 +2,11 @@ \file gd32f30x_gpio.h \brief definitions for the GPIO - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -260,8 +257,7 @@ OF SUCH DAMAGE. #define AFIO_PCF0_ENET_PHY_SEL BIT(23) /*!< ethernet MII or RMII PHY selection */ #define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ -#define AFIO_PCF0_TIMER1ITR0_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ -#define AFIO_PCF0_TIMER1ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 0 remapping */ +#define AFIO_PCF0_TIMER1ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ #define AFIO_PCF0_PTP_PPS_REMAP BIT(30) /*!< ethernet PTP PPS remapping */ #else @@ -279,9 +275,9 @@ OF SUCH DAMAGE. #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ #define AFIO_PCF0_ADC0_ETRGINS_REMAP BIT(17) /*!< ADC 0 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC0_ETRGREG_REMAP BIT(18) /*!< ADC 0 external trigger regular conversion remapping */ +#define AFIO_PCF0_ADC0_ETRGROU_REMAP BIT(18) /*!< ADC 0 external trigger routine conversion remapping */ #define AFIO_PCF0_ADC1_ETRGINS_REMAP BIT(19) /*!< ADC 1 external trigger inserted conversion remapping */ -#define AFIO_PCF0_ADC1_ETRGREG_REMAP BIT(20) /*!< ADC 1 external trigger regular conversion remapping */ +#define AFIO_PCF0_ADC1_ETRGROU_REMAP BIT(20) /*!< ADC 1 external trigger routine conversion remapping */ #define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ #endif /* GD32F30X_CL */ @@ -449,9 +445,9 @@ typedef FlagStatus bit_status; #endif /* GD32F30X_HD||GD32F30X_XD */ #if (defined(GD32F30X_HD) || defined(GD32F30X_XD)) #define GPIO_ADC0_ETRGINS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGINS_REMAP >> 16)) /*!< ADC0 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ -#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGREG_REMAP >> 16)) /*!< ADC0 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_ADC0_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGROU_REMAP >> 16)) /*!< ADC0 external trigger routine conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ #define GPIO_ADC1_ETRGINS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGINS_REMAP >> 16)) /*!< ADC1 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ -#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGREG_REMAP >> 16)) /*!< ADC1 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ +#define GPIO_ADC1_ETRGREG_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGROU_REMAP >> 16)) /*!< ADC1 external trigger routine conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) */ #endif /* GD32F30X_HD||GD32F30X_XD */ #define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(1) >> 16)) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ #define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(2) >> 16)) /*!< JTAG-DP disabled and SW-DP enabled */ @@ -462,7 +458,7 @@ typedef FlagStatus bit_status; #define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D0000U | PCF0_CAN_REMAP(3)) /*!< CAN0 full remapping(only for GD32F30X_CL devices) */ #define GPIO_ENET_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ENET_REMAP >> 16)) /*!< ENET remapping(only for GD32F30X_CL devices) */ #define GPIO_CAN1_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_CAN1_REMAP >> 16)) /*!< CAN1 remapping(only for GD32F30X_CL devices) */ -#define GPIO_TIMER1ITR0_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER1ITR0_REMAP >> 16)) /*!< TIMER1 internal trigger 0 remapping(only for GD32F30X_CL devices) */ +#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER1ITI1_REMAP >> 16)) /*!< TIMER1 internal trigger 1 remapping(only for GD32F30X_CL devices) */ #define GPIO_PTP_PPS_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_PTP_PPS_REMAP >> 16)) /*!< ethernet PTP PPS remapping(only for GD32F30X_CL devices) */ #endif /* GD32F30X_CL */ #define GPIO_TIMER8_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER8_REMAP) /*!< TIMER8 remapping */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h index 609b740b..9361865f 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_i2c.h @@ -2,15 +2,11 @@ \file gd32f30x_i2c.h \brief definitions for the I2C - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2019-04-16, V2.0.1, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h index 49099acd..e345d4f6 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_misc.h @@ -2,14 +2,11 @@ \file gd32f30x_misc.h \brief definitions for the MISC - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -71,17 +68,104 @@ OF SUCH DAMAGE. #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ +#if (__MPU_PRESENT == 1) + +#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) /*!< MPU region number 0 */ +#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) /*!< MPU region number 1 */ +#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) /*!< MPU region number 2 */ +#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) /*!< MPU region number 3 */ +#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) /*!< MPU region number 4 */ +#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) /*!< MPU region number 5 */ +#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) /*!< MPU region number 6 */ +#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) /*!< MPU region number 7 */ + +#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) /*!< MPU region size is 32 bytes, the smallest supported region size is 32 bytes */ +#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) /*!< MPU region size is 64 bytes */ +#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) /*!< MPU region size is 128 bytes */ +#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) /*!< MPU region size is 256 bytes */ +#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) /*!< MPU region size is 512 bytes */ +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) /*!< MPU region size is 1K bytes */ +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) /*!< MPU region size is 2K bytes */ +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) /*!< MPU region size is 4K bytes */ +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) /*!< MPU region size is 8K bytes */ +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) /*!< MPU region size is 16K bytes */ +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) /*!< MPU region size is 32K bytes */ +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) /*!< MPU region size is 64K bytes */ +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) /*!< MPU region size is 128K bytes */ +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) /*!< MPU region size is 256K bytes */ +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) /*!< MPU region size is 512K bytes */ +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) /*!< MPU region size is 1M bytes */ +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) /*!< MPU region size is 2M bytes */ +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) /*!< MPU region size is 4M bytes */ +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) /*!< MPU region size is 8M bytes */ +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) /*!< MPU region size is 16M bytes */ +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) /*!< MPU region size is 32M bytes */ +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) /*!< MPU region size is 64M bytes */ +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) /*!< MPU region size is 128M bytes */ +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) /*!< MPU region size is 256M bytes */ +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) /*!< MPU region size is 512M bytes */ +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) /*!< MPU region size is 1G bytes */ +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) /*!< MPU region size is 2G bytes */ +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) /*!< MPU region size is 4G bytes */ + +#define MPU_SUBREGION_ENABLE ((uint8_t)0x00U) /*!< Subregion enable */ +#define MPU_SUBREGION_DISABLE ((uint8_t)0x01U) /*!< Subregion disable */ + +#define MPU_TEX_TYPE0 ((uint8_t)0x00U) /*!< MPU TEX type 0 */ +#define MPU_TEX_TYPE1 ((uint8_t)0x01U) /*!< MPU TEX type 1 */ +#define MPU_TEX_TYPE2 ((uint8_t)0x02U) /*!< MPU TEX type 2 */ + +#define MPU_AP_NO_ACCESS 0U /*!< MPU access permission no access */ +#define MPU_AP_PRIV_RW 1U /*!< MPU access permission privileged access only */ +#define MPU_AP_PRIV_RW_UNPRIV_RO 2U /*!< MPU access permission unprivileged access read-only */ +#define MPU_AP_FULL_ACCESS 3U /*!< MPU access permission full access */ +#define MPU_AP_PRIV_RO 5U /*!< MPU access permission privileged access read-only */ +#define MPU_AP_PRIV_UNPRIV_RO 6U /*!< MPU access permission privileged and unprivileged read-only access */ + +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) /*!< MPU access shareable */ +#define MPU_ACCESS_NON_SHAREABLE ((uint8_t)0x00U) /*!< MPU access non-shareable */ + +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) /*!< MPU access cacheable */ +#define MPU_ACCESS_NON_CACHEABLE ((uint8_t)0x00U) /*!< MPU access non-cacheable */ + +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) /*!< MPU access bufferable */ +#define MPU_ACCESS_NON_BUFFERABLE ((uint8_t)0x00U) /*!< MPU access non-bufferable */ + +#define MPU_INSTRUCTION_EXEC_PERMIT ((uint8_t)0x00U) /*!< execution of an instruction fetched from this region permitted */ +#define MPU_INSTRUCTION_EXEC_NOT_PERMIT ((uint8_t)0x01U) /*!< execution of an instruction fetched from this region not permitted */ + +#define MPU_MODE_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< HFNMIENA and PRIVDEFENA are 0 */ +#define MPU_MODE_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< use the MPU for memory accesses by HardFault and NMI handlers only */ +#define MPU_MODE_PRIV_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< enables the default memory map as a background region for privileged access only */ +#define MPU_MODE_HFNMI_PRIVDEF ((uint32_t)MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< HFNMIENA and PRIVDEFENA are 1 */ + +/* MPU region init parameter struct definitions */ +typedef struct { + uint32_t region_base_address; /*!< region base address */ + uint8_t region_number; /*!< region number */ + uint8_t region_size; /*!< region size */ + uint8_t subregion_disable; /*!< subregion disable */ + uint8_t tex_type; /*!< tex type */ + uint8_t access_permission; /*!< access permissions(AP) field */ + uint8_t access_shareable; /*!< shareable */ + uint8_t access_cacheable; /*!< cacheable */ + uint8_t access_bufferable; /*!< bufferable */ + uint8_t instruction_exec; /*!< execute never */ +} mpu_region_init_struct; + +#endif /* __MPU_PRESENT */ + /* function declarations */ /* set the priority group */ void nvic_priority_group_set(uint32_t nvic_prigroup); /* enable NVIC request */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); +void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority); /* disable NVIC request */ -void nvic_irq_disable(uint8_t nvic_irq); +void nvic_irq_disable(IRQn_Type nvic_irq); /* set the NVIC vector table base address */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); +void nvic_vector_table_set(uint32_t nvic_vect_tab, uint32_t offset); /* set the state of the low power mode */ void system_lowpower_set(uint8_t lowpower_mode); @@ -91,4 +175,18 @@ void system_lowpower_reset(uint8_t lowpower_mode); /* set the systick clock source */ void systick_clksource_set(uint32_t systick_clksource); +#if (__MPU_PRESENT == 1) +/* enable arm mpu */ +void armv7_mpu_enable(uint32_t mpu_control); +/* disable arm mpu */ +void armv7_mpu_disable(void); +/* mpu set region */ +void armv7_mpu_set_region(uint32_t rbar, uint32_t rasr); +/* initialize mpu_region_init_struct with the default values */ +void mpu_region_struct_para_init(mpu_region_init_struct *mpu_init_struct); +/* configure the MPU region */ +void mpu_region_config(mpu_region_init_struct *mpu_init_struct); +/* enable the MPU region */ +void mpu_region_enable(void); +#endif /* __MPU_PRESENT */ #endif /* GD32F30X_MISC_H */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h index f2c909af..fd8e1725 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_pmu.h @@ -2,14 +2,11 @@ \file gd32f30x_pmu.h \brief definitions for the PMU - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -148,6 +145,8 @@ void pmu_lvd_select(uint32_t lvdt_n); void pmu_ldo_output_select(uint32_t ldo_output); /* disable PMU lvd */ void pmu_lvd_disable(void); +/* enable PMU lvd */ +void pmu_lvd_enable(void); /* functions of low-driver mode and high-driver mode in deep-sleep mode */ /* switch high-driver mode */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h index 24a230f3..9ae67eac 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_rcu.h @@ -2,14 +2,11 @@ \file gd32f30x_rcu.h \brief definitions for the RCU - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h index 68bc90ed..bbe1c73c 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_rtc.h @@ -2,14 +2,11 @@ \file gd32f30x_rtc.h \brief definitions for the RTC - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h index acc4e936..a2f0ffdc 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_sdio.h @@ -2,14 +2,11 @@ \file gd32f30x_sdio.h \brief definitions for the SDIO - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h index 24da60a6..cc566d6e 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_spi.h @@ -2,14 +2,11 @@ \file gd32f30x_spi.h \brief definitions for the SPI - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -214,7 +211,7 @@ typedef struct /* I2S standard */ #define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_PHILIPS I2SCTL_I2SSTD(0) /*!< I2S philips standard */ #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ #define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h index 5da3d455..dffe34ab 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_timer.h @@ -2,14 +2,11 @@ \file gd32f30x_timer.h \brief definitions for the TIMER - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h index 7eaac57a..25094f93 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_usart.h @@ -2,14 +2,11 @@ \file gd32f30x_usart.h \brief definitions for the USART - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h index 471970ea..c2580744 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_wwdgt.h @@ -2,14 +2,11 @@ \file gd32f30x_wwdgt.h \brief definitions for the WWDGT - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c index 14247232..1a4dbe9f 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_adc.c @@ -2,14 +2,11 @@ \file gd32f30x_adc.c \brief ADC driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -114,8 +111,8 @@ void adc_calibration_enable(uint32_t adc_periph) } /*! - \brief enable DMA request - \param[in] adc_periph: ADCx,x=0,1,2 + \brief enable DMA request + \param[in] adc_periph: ADCx,x=0,2 only one among these parameters can be selected \param[out] none \retval none @@ -126,8 +123,8 @@ void adc_dma_mode_enable(uint32_t adc_periph) } /*! - \brief disable DMA request - \param[in] adc_periph: ADCx,x=0,1,2 + \brief disable DMA request + \param[in] adc_periph: ADCx,x=0,2 only one among these parameters can be selected \param[out] none \retval none @@ -184,21 +181,21 @@ void adc_resolution_config(uint32_t adc_periph , uint32_t resolution) \brief configure ADC discontinuous mode \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one among these parameters can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of routine & inserted sequence \param[in] length: number of conversions in discontinuous mode,the number can be 1..8 - for regular channel ,the number has no effect for inserted channel + for routine sequence ,the number has no effect for inserted sequence \param[out] none \retval none */ -void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length) +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_sequence, uint8_t length) { ADC_CTL0(adc_periph) &= ~((uint32_t)( ADC_CTL0_DISRC | ADC_CTL0_DISIC )); - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: + switch(adc_sequence){ + case ADC_ROUTINE_CHANNEL: /* config the number of conversions in discontinuous mode */ ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM); ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - 1U)); @@ -219,15 +216,15 @@ void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_grou \param[in] mode: ADC mode only one among these parameters can be selected \arg ADC_MODE_FREE: all the ADCs work independently - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode - \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode - \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined routine parallel + inserted parallel mode + \arg ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined routine parallel + trigger rotation mode + \arg ADC_DAUL_INSERTED_PARALLEL_ROUTINE_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode + \arg ADC_DAUL_INSERTED_PARALLEL_ROUTINE_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only - \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only - \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only - \arg ADC_DAUL_INSERTED_TRRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only + \arg ADC_DAUL_ROUTINE_PARALLEL: ADC0 and ADC1 work in routine parallel mode only + \arg ADC_DAUL_ROUTINE_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only + \arg ADC_DAUL_ROUTINE_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only + \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only \param[out] none \retval none */ @@ -244,7 +241,7 @@ void adc_mode_config(uint32_t mode) \param[in] function: the function to config one or more parameters can be selected below \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_INSERTED_CHANNEL_AUTO: inserted sequence convert automatically \arg ADC_CONTINUOUS_MODE: continuous mode select \param[in] newvalue: ENABLE or DISABLE \param[out] none @@ -296,23 +293,23 @@ void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment) } /*! - \brief configure the length of regular channel group or inserted channel group + \brief configure the channel length of routine sequence or inserted sequence \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] length: the length of the sequence + routine sequence 1-16 + inserted sequence 1-4 \param[out] none \retval none */ -void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length) +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t length) { - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: + switch(adc_sequence){ + case ADC_ROUTINE_CHANNEL: ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL); ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-1U)); @@ -328,10 +325,10 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u } /*! - \brief configure ADC regular channel + \brief configure ADC routine channel \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15 + \param[in] rank: the routine sequence rank,this parameter must be between 0 to 15 \param[in] adc_channel: the selected ADC channel only one among these parameters can be selected \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx @@ -348,11 +345,11 @@ void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, u \param[out] none \retval none */ -void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) +void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time) { uint32_t rsq,sampt; - /* ADC regular sequence config */ + /* ADC routine sequence config */ if(rank < 6U){ rsq = ADC_RSQ2(adc_periph); rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U*rank))); @@ -370,7 +367,7 @@ void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc ADC_RSQ0(adc_periph) = rsq; }else{ } - + /* ADC sampling time config */ if(adc_channel < 10U){ sampt = ADC_SAMPT1(adc_periph); @@ -390,7 +387,7 @@ void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc \brief configure ADC inserted channel \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] rank: the inserted sequencer rank,this parameter must be between 0 to 3 \param[in] adc_channel: the selected ADC channel only one among these parameters can be selected \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx @@ -415,8 +412,8 @@ void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t ad inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U); isq = ADC_ISQ(adc_periph); - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (5U * ((3 + rank) - inserted_length)))); - isq |= ((uint32_t)adc_channel << (5U * ((3 + rank) - inserted_length))); + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (5U * ((3U + rank) - inserted_length)))); + isq |= ((uint32_t)adc_channel << (5U * ((3U + rank) - inserted_length))); ADC_ISQ(adc_periph) = isq; /* ADC sampling time config */ @@ -468,28 +465,28 @@ void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_c \brief enable ADC external trigger \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence one or more parameters can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence \param[in] newvalue: ENABLE or DISABLE \param[out] none \retval none */ -void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue) +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_sequence, ControlStatus newvalue) { if(newvalue){ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + if(0U != (adc_sequence & ADC_ROUTINE_CHANNEL)){ ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC; } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + if(0U != (adc_sequence & ADC_INSERTED_CHANNEL)){ ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC; } }else{ - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + if(0U != (adc_sequence & ADC_ROUTINE_CHANNEL)){ ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC; } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + if(0U != (adc_sequence & ADC_INSERTED_CHANNEL)){ ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC; } } @@ -499,30 +496,30 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, \brief configure ADC external trigger source \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence only one parameter can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \param[in] external_trigger_source: routine or inserted sequence trigger source only one parameter can be selected - for regular channel: - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: timer 0 CC0 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: timer 0 CC1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select - \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: timer 1 CC1 event select - \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: timer 2 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: timer 3 CC3 event select - \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select - \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11 : external interrupt line 11 - \arg ADC2_EXTTRIG_REGULAR_T2_CH0: timer 2 CC0 event select - \arg ADC2_EXTTRIG_REGULAR_T1_CH2: timer 1 CC2 event select - \arg ADC2_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select - \arg ADC2_EXTTRIG_REGULAR_T7_CH0: timer 7 CC0 event select - \arg ADC2_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select - \arg ADC2_EXTTRIG_REGULAR_T4_CH0: timer 4 CC0 event select - \arg ADC2_EXTTRIG_REGULAR_T4_CH2: timer 4 CC2 event select - \arg ADC0_1_2_EXTTRIG_REGULAR_NONE: software trigger - for inserted channel: + for routine sequence: + \arg ADC0_1_EXTTRIG_ROUTINE_T0_CH0: timer 0 CC0 event select + \arg ADC0_1_EXTTRIG_ROUTINE_T0_CH1: timer 0 CC1 event select + \arg ADC0_1_EXTTRIG_ROUTINE_T0_CH2: timer 0 CC2 event select + \arg ADC0_1_EXTTRIG_ROUTINE_T1_CH1: timer 1 CC1 event select + \arg ADC0_1_EXTTRIG_ROUTINE_T2_TRGO: timer 2 TRGO event select + \arg ADC0_1_EXTTRIG_ROUTINE_T3_CH3: timer 3 CC3 event select + \arg ADC0_1_EXTTRIG_ROUTINE_T7_TRGO: timer 7 TRGO event select + \arg ADC0_1_EXTTRIG_ROUTINE_EXTI_11 : external interrupt line 11 + \arg ADC2_EXTTRIG_ROUTINE_T2_CH0: timer 2 CC0 event select + \arg ADC2_EXTTRIG_ROUTINE_T1_CH2: timer 1 CC2 event select + \arg ADC2_EXTTRIG_ROUTINE_T0_CH2: timer 0 CC2 event select + \arg ADC2_EXTTRIG_ROUTINE_T7_CH0: timer 7 CC0 event select + \arg ADC2_EXTTRIG_ROUTINE_T7_TRGO: timer 7 TRGO event select + \arg ADC2_EXTTRIG_ROUTINE_T4_CH0: timer 4 CC0 event select + \arg ADC2_EXTTRIG_ROUTINE_T4_CH2: timer 4 CC2 event select + \arg ADC0_1_2_EXTTRIG_ROUTINE_NONE: software trigger + for inserted sequence: \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: timer 1 TRGO event select @@ -542,10 +539,10 @@ void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, \param[out] none \retval none */ -void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source) +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_sequence, uint32_t external_trigger_source) { - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: + switch(adc_sequence){ + case ADC_ROUTINE_CHANNEL: ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC); ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source; break; @@ -562,38 +559,37 @@ void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel \brief enable ADC software trigger \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] adc_channel_group: select the channel group + \param[in] adc_sequence: select the sequence one or more parameters can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence \param[out] none \retval none */ -void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group) +void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence) { - if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){ + if(0U != (adc_sequence & ADC_ROUTINE_CHANNEL)){ ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST; } - if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){ + if(0U != (adc_sequence & ADC_INSERTED_CHANNEL)){ ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST; } } /*! - \brief read ADC regular group data register + \brief read ADC routine sequence data register \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] none \param[out] none \retval the conversion value */ -uint16_t adc_regular_data_read(uint32_t adc_periph) +uint16_t adc_routine_data_read(uint32_t adc_periph) { return (uint16_t)(ADC_RDATA(adc_periph)); } /*! - \brief read ADC inserted group data register + \brief read ADC inserted sequence data register \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected \param[in] inserted_channel : insert channel select @@ -648,10 +644,10 @@ uint32_t adc_sync_mode_convert_value_read(void) \param[in] adc_flag: the adc flag bits only one parameter can be selected \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence \param[out] none \retval FlagStatus: SET or RESET */ @@ -671,10 +667,10 @@ FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag) \param[in] adc_flag: the adc flag bits one or more parameters can be selected \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group + \arg ADC_FLAG_EOC: end of sequence conversion flag + \arg ADC_FLAG_EOIC: end of inserted sequence conversion flag + \arg ADC_FLAG_STIC: start flag of inserted sequence + \arg ADC_FLAG_STRC: start flag of routine sequence \param[out] none \retval none */ @@ -689,9 +685,9 @@ void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag) only one among these parameters can be selected \param[in] adc_interrupt: the adc interrupt bits only oneparameter can be selected - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt flag \param[out] none \retval FlagStatus: SET or RESET */ @@ -731,9 +727,9 @@ FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt) only one among these parameters can be selected \param[in] adc_interrupt: the adc status flag one or more parameters can be selected - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag + \arg ADC_INT_FLAG_EOC: end of sequence conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted sequence conversion interrupt flag \param[out] none \retval none */ @@ -748,9 +744,9 @@ void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt) only one among these parameters can be selected \param[in] adc_interrupt: the adc interrupt one or more parameters can be selected - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \arg ADC_INT_WDE: analog watchdog interrupt + \arg ADC_INT_EOC: end of sequence conversion interrupt + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt \param[out] none \retval none */ @@ -773,11 +769,11 @@ void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt) \brief disable ADC interrupt \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] adc_interrupt: the adc interrupt flag + \param[in] adc_interrupt: the adc interrupt one or more parameters can be selected - \arg ADC_INT_WDE: analog watchdog interrupt flag - \arg ADC_INT_EOC: end of group conversion interrupt flag - \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag + \arg ADC_INT_WDE: analog watchdog interrupt + \arg ADC_INT_EOC: end of sequence conversion interrupt + \arg ADC_INT_EOIC: end of inserted sequence conversion interrupt \param[out] none \retval none */ @@ -815,29 +811,29 @@ void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel } /*! - \brief configure ADC analog watchdog group channel + \brief configure ADC analog watchdog sequence channel \param[in] adc_periph: ADCx,x=0,1,2 only one among these parameters can be selected - \param[in] adc_channel_group: the channel group use analog watchdog + \param[in] adc_sequence: the sequence use analog watchdog only one parameter can be selected - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \arg ADC_ROUTINE_CHANNEL: routine sequence + \arg ADC_INSERTED_CHANNEL: inserted sequence + \arg ADC_ROUTINE_INSERTED_CHANNEL: both routine and inserted sequence \param[out] none \retval none */ -void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group) +void adc_watchdog_sequence_channel_enable(uint32_t adc_periph, uint8_t adc_sequence) { ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); - /* select the group */ - switch(adc_channel_group){ - case ADC_REGULAR_CHANNEL: + /* select the sequence */ + switch(adc_sequence){ + case ADC_ROUTINE_CHANNEL: ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN; break; case ADC_INSERTED_CHANNEL: ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN; break; - case ADC_REGULAR_INSERTED_CHANNEL: + case ADC_ROUTINE_INSERTED_CHANNEL: ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); break; default: @@ -886,7 +882,7 @@ void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 4-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c index bb286818..97cdf470 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_bkp.c @@ -2,14 +2,11 @@ \file gd32f30x_bkp.c \brief BKP driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -203,7 +200,7 @@ void bkp_rtc_calibration_value_set(uint8_t value) uint16_t ctl; ctl = BKP_OCTL; - ctl &= ~(uint16_t)BKP_OCTL_RCCV; + ctl &= (uint16_t)~BKP_OCTL_RCCV; ctl |= (uint16_t)OCTL_RCCV(value); BKP_OCTL = ctl; } @@ -279,11 +276,13 @@ void bkp_tamper_interrupt_disable(void) */ FlagStatus bkp_flag_get(uint16_t flag) { + FlagStatus ret; if(RESET != (BKP_TPCS & flag)){ - return SET; + ret = SET; }else{ - return RESET; + ret = RESET; } + return ret; } /*! @@ -307,11 +306,13 @@ void bkp_flag_clear(uint16_t flag) */ FlagStatus bkp_interrupt_flag_get(uint16_t flag) { + FlagStatus ret; if(RESET != (BKP_TPCS & flag)){ - return SET; + ret = SET; }else{ - return RESET; + ret = RESET; } + return ret; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_can.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_can.c index 1cb0504e..283393fc 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_can.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_can.c @@ -2,17 +2,11 @@ \file gd32f30x_can.c \brief CAN driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2019-11-27, V2.0.1, firmware for GD32F30x - \version 2020-03-02, V2.0.2, firmware for GD32F30x - \version 2020-07-14, V2.0.3, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -120,14 +114,14 @@ void can_struct_para_init(can_struct_type_enum type, void *p_struct) /* used for can_message_transmit() */ case CAN_TX_MESSAGE_STRUCT: for(i = 0U; i < 8U; i++) { - ((can_trasnmit_message_struct *)p_struct)->tx_data[i] = 0U; + ((can_transmit_message_struct *)p_struct)->tx_data[i] = 0U; } - ((can_trasnmit_message_struct *)p_struct)->tx_dlen = 0u; - ((can_trasnmit_message_struct *)p_struct)->tx_efid = 0U; - ((can_trasnmit_message_struct *)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; - ((can_trasnmit_message_struct *)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; - ((can_trasnmit_message_struct *)p_struct)->tx_sfid = 0U; + ((can_transmit_message_struct *)p_struct)->tx_dlen = 0u; + ((can_transmit_message_struct *)p_struct)->tx_efid = 0U; + ((can_transmit_message_struct *)p_struct)->tx_ff = (uint8_t)CAN_FF_STANDARD; + ((can_transmit_message_struct *)p_struct)->tx_ft = (uint8_t)CAN_FT_DATA; + ((can_transmit_message_struct *)p_struct)->tx_sfid = 0U; break; /* used for can_message_receive() */ @@ -154,7 +148,7 @@ void can_struct_para_init(can_struct_type_enum type, void *p_struct) \brief initialize CAN \param[in] can_periph \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] can_parameter_init: parameters for CAN initializtion + \param[in] can_parameter_init: parameters for CAN initialization \arg working_mode: CAN_NORMAL_MODE, CAN_LOOPBACK_MODE, CAN_SILENT_MODE, CAN_SILENT_LOOPBACK_MODE \arg resync_jump_width: CAN_BT_SJW_xTQ(x=1, 2, 3, 4) \arg time_segment_1: CAN_BT_BS1_xTQ(1..16) @@ -443,7 +437,7 @@ void can_time_trigger_mode_disable(uint32_t can_periph) \param[out] none \retval mailbox_number */ -uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message) +uint8_t can_message_transmit(uint32_t can_periph, can_transmit_message_struct *transmit_message) { uint8_t mailbox_number = CAN_MAILBOX0; @@ -457,36 +451,41 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *t } else { mailbox_number = CAN_NOMAILBOX; } - /* return no mailbox empty */ - if(CAN_NOMAILBOX == mailbox_number) { - return CAN_NOMAILBOX; - } - - CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; - if(CAN_FF_STANDARD == transmit_message->tx_ff) { - /* set transmit mailbox standard identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ - transmit_message->tx_ft); - } else { - /* set transmit mailbox extended identifier */ - CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ - transmit_message->tx_ff | \ - transmit_message->tx_ft); + /* got one empty mailbox */ + if(CAN_NOMAILBOX != mailbox_number) { + + CAN_TMI(can_periph, mailbox_number) &= CAN_TMI_TEN; + if(CAN_FF_STANDARD == transmit_message->tx_ff) { + /* set transmit mailbox standard identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_SFID(transmit_message->tx_sfid) | \ + transmit_message->tx_ft); + } else { + /* set transmit mailbox extended identifier */ + CAN_TMI(can_periph, mailbox_number) |= (uint32_t)(TMI_EFID(transmit_message->tx_efid) | \ + transmit_message->tx_ff | \ + transmit_message->tx_ft); + } + /* set the data length */ + CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; + + /* Classic CAN frame data length does not exceed 8 */ + if (transmit_message->tx_dlen > 8U) { + transmit_message->tx_dlen = 8U; + } + + CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; + /* set the data */ + CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ + TMDATA0_DB2(transmit_message->tx_data[2]) | \ + TMDATA0_DB1(transmit_message->tx_data[1]) | \ + TMDATA0_DB0(transmit_message->tx_data[0]); + CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ + TMDATA1_DB6(transmit_message->tx_data[6]) | \ + TMDATA1_DB5(transmit_message->tx_data[5]) | \ + TMDATA1_DB4(transmit_message->tx_data[4]); + /* enable transmission */ + CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; } - /* set the data length */ - CAN_TMP(can_periph, mailbox_number) &= ~CAN_TMP_DLENC; - CAN_TMP(can_periph, mailbox_number) |= transmit_message->tx_dlen; - /* set the data */ - CAN_TMDATA0(can_periph, mailbox_number) = TMDATA0_DB3(transmit_message->tx_data[3]) | \ - TMDATA0_DB2(transmit_message->tx_data[2]) | \ - TMDATA0_DB1(transmit_message->tx_data[1]) | \ - TMDATA0_DB0(transmit_message->tx_data[0]); - CAN_TMDATA1(can_periph, mailbox_number) = TMDATA1_DB7(transmit_message->tx_data[7]) | \ - TMDATA1_DB6(transmit_message->tx_data[6]) | \ - TMDATA1_DB5(transmit_message->tx_data[5]) | \ - TMDATA1_DB4(transmit_message->tx_data[4]); - /* enable transmission */ - CAN_TMI(can_periph, mailbox_number) |= CAN_TMI_TEN; return mailbox_number; } @@ -497,7 +496,7 @@ uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *t \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL \param[in] mailbox_number only one parameter can be selected which is shown as below: - \arg CAN_MAILBOX(x=0,1,2) + \arg CAN_MAILBOXx(x=0,1,2) \param[out] none \retval can_transmit_state_enum */ @@ -558,25 +557,63 @@ can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox only one parameter can be selected which is shown as below: \arg CAN_MAILBOXx(x=0,1,2) \param[out] none - \retval none + \retval ErrStatus: ERROR or SUCCESS */ -void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) +ErrStatus can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number) { + ErrStatus reval = SUCCESS; + /* timeout for CAN_TSTAT_MSTx bits */ + uint32_t timeout = CAN_TIMEOUT; + uint32_t reg_value0 = 0U; + uint32_t reg_value1 = 0U; + + /* get the status of transmit FIFO order */ + reg_value0 = CAN_CTL(can_periph) & CAN_CTL_TFO; + if(CAN_MAILBOX0 == mailbox_number) { - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; - while(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) { + reg_value1 = CAN_TSTAT(can_periph) & (CAN_TSTAT_TMLS0 | CAN_ALL_MAILBOX_EMPTY); + if((CAN_CTL_TFO == reg_value0) && (CAN_TSTAT_TMLS0 == reg_value1)){ + reval = ERROR; + } else { + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST0; + while((CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)) && (0U != timeout)) { + timeout--; + } + if(CAN_TSTAT_MST0 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST0)){ + reval = ERROR; + } } } else if(CAN_MAILBOX1 == mailbox_number) { - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; - while(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) { + reg_value1 = CAN_TSTAT(can_periph) & (CAN_TSTAT_TMLS1 | CAN_ALL_MAILBOX_EMPTY); + if((CAN_CTL_TFO == reg_value0) && (CAN_TSTAT_TMLS1 == reg_value1)){ + reval = ERROR; + }else{ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST1; + while((CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)) && (0U != timeout)) { + timeout--; + } + if(CAN_TSTAT_MST1 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST1)){ + reval = ERROR; + } } + } else if(CAN_MAILBOX2 == mailbox_number) { - CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; - while(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) { + reg_value1 = CAN_TSTAT(can_periph) & (CAN_TSTAT_TMLS2 | CAN_ALL_MAILBOX_EMPTY); + if((CAN_CTL_TFO == reg_value0) && (CAN_TSTAT_TMLS2 == reg_value1)){ + reval = ERROR; + }else{ + CAN_TSTAT(can_periph) |= CAN_TSTAT_MST2; + while((CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)) && (0U != timeout)) { + timeout--; + } + if(CAN_TSTAT_MST2 == (CAN_TSTAT(can_periph) & CAN_TSTAT_MST2)){ + reval = ERROR; + } } } else { /* illegal parameters */ } + return reval; } /*! @@ -684,7 +721,7 @@ uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number) \brief set CAN working mode \param[in] can_periph \arg CANx(x=0,1),the CAN1 only for GD32F30X_CL - \param[in] can_working_mode + \param[in] working_mode only one parameter can be selected which is shown as below: \arg CAN_MODE_INITIALIZE \arg CAN_MODE_NORMAL @@ -703,7 +740,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_SLPWMOD); /* set initialize mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_IWMOD; - /* wait the acknowledge */ + /* wait the acknowledgment */ while((CAN_STAT_IWS != (CAN_STAT(can_periph) & CAN_STAT_IWS)) && (0U != timeout)) { timeout--; } @@ -715,7 +752,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) } else if(CAN_MODE_NORMAL == working_mode) { /* enter normal mode */ CAN_CTL(can_periph) &= ~(uint32_t)(CAN_CTL_SLPWMOD | CAN_CTL_IWMOD); - /* wait the acknowledge */ + /* wait the acknowledgment */ while((0U != (CAN_STAT(can_periph) & (CAN_STAT_IWS | CAN_STAT_SLPWS))) && (0U != timeout)) { timeout--; } @@ -729,7 +766,7 @@ ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode) CAN_CTL(can_periph) &= (~(uint32_t)CAN_CTL_IWMOD); /* set sleep mode */ CAN_CTL(can_periph) |= (uint8_t)CAN_CTL_SLPWMOD; - /* wait the acknowledge */ + /* wait the acknowledgment */ while((CAN_STAT_SLPWS != (CAN_STAT(can_periph) & CAN_STAT_SLPWS)) && (0U != timeout)) { timeout--; } @@ -779,10 +816,10 @@ ErrStatus can_wakeup(uint32_t can_periph) \retval can_error_enum \arg CAN_ERROR_NONE: no error \arg CAN_ERROR_FILL: fill error - \arg CAN_ERROR_FORMATE: format error + \arg CAN_ERROR_FORMAT: format error \arg CAN_ERROR_ACK: ACK error \arg CAN_ERROR_BITRECESSIVE: bit recessive - \arg CAN_ERROR_BITDOMINANTER: bit dominant error + \arg CAN_ERROR_BITDOMINANT: bit dominant error \arg CAN_ERROR_CRC: CRC error \arg CAN_ERROR_SOFTWARECFG: software configure */ @@ -872,12 +909,16 @@ uint8_t can_transmit_error_number_get(uint32_t can_periph) */ FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag) { + FlagStatus reval = RESET; + /* get flag and interrupt enable state */ if(RESET != (CAN_REG_VAL(can_periph, flag) & BIT(CAN_BIT_POS(flag)))) { - return SET; + reval = SET; } else { - return RESET; + reval = RESET; } + + return reval; } /*! @@ -998,6 +1039,8 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f { uint32_t ret1 = RESET; uint32_t ret2 = RESET; + + FlagStatus reval = RESET; /* get the status of interrupt flag */ if(flag == CAN_INT_FLAG_RFL0) { @@ -1012,10 +1055,12 @@ FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum f /* get the status of interrupt enable bit */ ret2 = CAN_INTEN(can_periph) & BIT(CAN_BIT_POS1(flag)); if(ret1 && ret2) { - return SET; + reval = SET; } else { - return RESET; + reval = RESET; } + + return reval; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c index 5aefea52..8337514d 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_crc.c @@ -2,14 +2,11 @@ \file gd32f30x_crc.c \brief CRC driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -123,8 +120,11 @@ uint32_t crc_single_data_calculate(uint32_t sdata) uint32_t crc_block_data_calculate(const uint32_t *array, uint32_t size) { uint32_t index; + uint32_t data = (uint32_t)array; + for(index = 0U; index < size; index++){ - CRC_DATA = *(array+index); + CRC_DATA = *(uint32_t *)data; + data += 4U; } return (CRC_DATA); } diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c index b39261a4..209eb1fd 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_ctc.c @@ -2,14 +2,11 @@ \file gd32f30x_ctc.c \brief CTC driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -220,11 +217,14 @@ uint16_t ctc_counter_capture_value_read(void) */ FlagStatus ctc_counter_direction_read(void) { + FlagStatus status; + if(RESET != (CTC_STAT & CTC_STAT_REFDIR)){ - return SET; + status = SET; }else{ - return RESET; + status = RESET; } + return status; } /*! @@ -269,11 +269,14 @@ uint8_t ctc_irc48m_trim_value_read(void) */ FlagStatus ctc_flag_get(uint32_t flag) { + FlagStatus status; + if(RESET != (CTC_STAT & flag)){ - return SET; + status = SET; }else{ - return RESET; + status = RESET; } + return status; } /*! @@ -348,7 +351,8 @@ void ctc_interrupt_disable(uint32_t interrupt) FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) { uint32_t interrupt_flag = 0U, intenable = 0U; - + FlagStatus status; + /* check whether the interrupt is enabled */ if(RESET != (int_flag & CTC_FLAG_MASK)){ intenable = CTC_CTL0 & CTC_CTL0_ERRIE; @@ -360,10 +364,12 @@ FlagStatus ctc_interrupt_flag_get(uint32_t int_flag) interrupt_flag = CTC_STAT & int_flag; if(interrupt_flag && intenable){ - return SET; + status = SET; }else{ - return RESET; + status = RESET; } + + return status; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c index 359e2169..0bec8e47 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dac.c @@ -1,15 +1,12 @@ /*! \file gd32f30x_dac.c \brief DAC driver - - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -38,332 +35,335 @@ OF SUCH DAMAGE. #include "gd32f30x_dac.h" /* DAC register bit offset */ -#define DAC1_REG_OFFSET ((uint32_t)16U) -#define DH_12BIT_OFFSET ((uint32_t)16U) -#define DH_8BIT_OFFSET ((uint32_t)8U) +#define OUT1_REG_OFFSET ((uint32_t)0x00000010U) +#define DH_12BIT_OFFSET ((uint32_t)0x00000010U) +#define DH_8BIT_OFFSET ((uint32_t)0x00000008U) /*! \brief deinitialize DAC - \param[in] none + \param[in] dac_periph: DACx(x=0) \param[out] none \retval none */ -void dac_deinit(void) +void dac_deinit(uint32_t dac_periph) { - rcu_periph_reset_enable(RCU_DACRST); - rcu_periph_reset_disable(RCU_DACRST); + switch(dac_periph){ + case DAC0: + /* reset DAC0 */ + rcu_periph_reset_enable(RCU_DACRST); + rcu_periph_reset_disable(RCU_DACRST); + break; + default: + break; + } } /*! \brief enable DAC - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \param[out] none \retval none */ -void dac_enable(uint32_t dac_periph) +void dac_enable(uint32_t dac_periph, uint8_t dac_out) { - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DEN0; + if(DAC_OUT0 == dac_out){ + DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN0; + }else if(DAC_OUT1 == dac_out){ + DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN1; }else{ - DAC_CTL |= DAC_CTL_DEN1; + /* illegal parameters */ } -} +} /*! \brief disable DAC - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \param[out] none \retval none */ -void dac_disable(uint32_t dac_periph) +void dac_disable(uint32_t dac_periph, uint8_t dac_out) { - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DEN0; + if(DAC_OUT0 == dac_out){ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN0); + }else if(DAC_OUT1 == dac_out){ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN1); }else{ - DAC_CTL &= ~DAC_CTL_DEN1; + /* illegal parameters */ } } /*! \brief enable DAC DMA function - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \param[out] none \retval none */ -void dac_dma_enable(uint32_t dac_periph) +void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out) { - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DDMAEN0; + if(DAC_OUT0 == dac_out){ + DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN0; + }else if(DAC_OUT1 == dac_out){ + DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN1; }else{ - DAC_CTL |= DAC_CTL_DDMAEN1; + /* illegal parameters */ } } /*! \brief disable DAC DMA function - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \param[out] none \retval none */ -void dac_dma_disable(uint32_t dac_periph) +void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out) { - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DDMAEN0; + if(DAC_OUT0 == dac_out){ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN0); + }else if(DAC_OUT1 == dac_out){ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN1); }else{ - DAC_CTL &= ~DAC_CTL_DDMAEN1; + /* illegal parameters */ } } /*! \brief enable DAC output buffer - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \param[out] none \retval none */ -void dac_output_buffer_enable(uint32_t dac_periph) +void dac_output_buffer_enable(uint32_t dac_periph, uint8_t dac_out) { - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DBOFF0; + if(DAC_OUT0 == dac_out){ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DBOFF0); + }else if(DAC_OUT1 == dac_out){ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DBOFF1); }else{ - DAC_CTL &= ~DAC_CTL_DBOFF1; + /* illegal parameters */ } } /*! \brief disable DAC output buffer - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \param[out] none \retval none */ -void dac_output_buffer_disable(uint32_t dac_periph) +void dac_output_buffer_disable(uint32_t dac_periph, uint8_t dac_out) { - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DBOFF0; + if(DAC_OUT0 == dac_out){ + DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DBOFF0; + }else if(DAC_OUT1 == dac_out){ + DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DBOFF1; }else{ - DAC_CTL |= DAC_CTL_DBOFF1; + /* illegal parameters */ } } /*! \brief get DAC output value - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \param[out] none - \retval DAC output data + \retval DAC output data: 0~4095 */ -uint16_t dac_output_value_get(uint32_t dac_periph) +uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out) { uint16_t data = 0U; - if(DAC0 == dac_periph){ - /* store the DAC0 output value */ - data = (uint16_t)DAC0_DO; + + if(DAC_OUT0 == dac_out){ + /* store the DACx_OUT0 output value */ + data = (uint16_t)DAC_OUT0_DO(dac_periph); + }else if(DAC_OUT1 == dac_out){ + /* store the DACx_OUT1 output value */ + data = (uint16_t)DAC_OUT1_DO(dac_periph); }else{ - /* store the DAC1 output value */ - data = (uint16_t)DAC1_DO; + /* illegal parameters */ } + return data; } /*! - \brief set the DAC specified data holding register value - \param[in] dac_periph: DACx(x = 0,1) - \param[in] dac_align: data alignment + \brief set DAC data holding register value + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) + \param[in] dac_align: DAC data alignment mode only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8 bit alignment - \arg DAC_ALIGN_12B_R: data right 12 bit alignment - \arg DAC_ALIGN_12B_L: data left 12 bit alignment - \param[in] data: data to be loaded + \arg DAC_ALIGN_12B_R: 12-bit right-aligned data + \arg DAC_ALIGN_12B_L: 12-bit left-aligned data + \arg DAC_ALIGN_8B_R: 8-bit right-aligned data + \param[in] data: data to be loaded(0~4095) \param[out] none \retval none */ -void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data) +void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data) { - if(DAC0 == dac_periph){ + /* DAC_OUT0 data alignment */ + if(DAC_OUT0 == dac_out){ switch(dac_align){ - /* data right 12 bit alignment */ + /* 12-bit right-aligned data */ case DAC_ALIGN_12B_R: - DAC0_R12DH = data; + DAC_OUT0_R12DH(dac_periph) = data; break; - /* data left 12 bit alignment */ + /* 12-bit left-aligned data */ case DAC_ALIGN_12B_L: - DAC0_L12DH = data; + DAC_OUT0_L12DH(dac_periph) = data; break; - /* data right 8 bit alignment */ + /* 8-bit right-aligned data */ case DAC_ALIGN_8B_R: - DAC0_R8DH = data; + DAC_OUT0_R8DH(dac_periph) = data; break; default: break; } - }else{ + }else if(DAC_OUT1 == dac_out){ + /* DAC_OUT1 data alignment */ switch(dac_align){ - /* data right 12 bit alignment */ + /* 12-bit right-aligned data */ case DAC_ALIGN_12B_R: - DAC1_R12DH = data; + DAC_OUT1_R12DH(dac_periph) = data; break; - /* data left 12 bit alignment */ + /* 12-bit left-aligned data */ case DAC_ALIGN_12B_L: - DAC1_L12DH = data; + DAC_OUT1_L12DH(dac_periph) = data; break; - /* data right 8 bit alignment */ + /* 8-bit right-aligned data */ case DAC_ALIGN_8B_R: - DAC1_R8DH = data; + DAC_OUT1_R8DH(dac_periph) = data; break; default: break; } + }else{ + /* illegal parameters */ } } /*! \brief enable DAC trigger - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \param[out] none \retval none */ -void dac_trigger_enable(uint32_t dac_periph) +void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out) { - if(DAC0 == dac_periph){ - DAC_CTL |= DAC_CTL_DTEN0; + if(DAC_OUT0 == dac_out){ + DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN0; + }else if(DAC_OUT1 == dac_out){ + DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN1; }else{ - DAC_CTL |= DAC_CTL_DTEN1; + /* illegal parameters */ } } /*! \brief disable DAC trigger - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \param[out] none \retval none */ -void dac_trigger_disable(uint32_t dac_periph) +void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out) { - if(DAC0 == dac_periph){ - DAC_CTL &= ~DAC_CTL_DTEN0; + if(DAC_OUT0 == dac_out){ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN0); + }else if(DAC_OUT1 == dac_out){ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN1); }else{ - DAC_CTL &= ~DAC_CTL_DTEN1; + /* illegal parameters */ } } /*! - \brief set DAC trigger source - \param[in] dac_periph: DACx(x = 0,1) - \param[in] triggersource: external triggers of DAC + \brief configure DAC trigger source + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) + \param[in] triggersource: external trigger of DAC only one parameter can be selected which is shown as below: - \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO - \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32F30X_CL) - \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO - \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO + \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO, only for GD32F30X_CL devices + \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO, only for GD32F30X_HD, GD32F30X_XD devices \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO - \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32F30X_HD and GD32F30X_XD) + \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO + \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO + \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event \arg DAC_TRIGGER_SOFTWARE: software trigger \param[out] none \retval none */ -void dac_trigger_source_config(uint32_t dac_periph,uint32_t triggersource) +void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource) { - if(DAC0 == dac_periph){ - /* configure DAC0 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL0; - DAC_CTL |= triggersource; + if(DAC_OUT0 == dac_out){ + /* configure DACx_OUT0 trigger source */ + DAC_CTL0(dac_periph) &= (uint32_t)(~(DAC_CTL0_DTSEL0)); + DAC_CTL0(dac_periph) |= triggersource; + }else if(DAC_OUT1 == dac_out){ + /* configure DACx_OUT1 trigger source */ + DAC_CTL0(dac_periph) &= (uint32_t)(~(DAC_CTL0_DTSEL1)); + DAC_CTL0(dac_periph) |= (triggersource << OUT1_REG_OFFSET); }else{ - /* configure DAC1 trigger source */ - DAC_CTL &= ~DAC_CTL_DTSEL1; - DAC_CTL |= (triggersource << DAC1_REG_OFFSET); + /* illegal parameters */ } } /*! \brief enable DAC software trigger - \param[in] dac_periph: DACx(x = 0,1) + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) \retval none */ -void dac_software_trigger_enable(uint32_t dac_periph) +void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out) { - if(DAC0 == dac_periph){ - DAC_SWT |= DAC_SWT_SWTR0; + if(DAC_OUT0 == dac_out){ + DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR0; + }else if(DAC_OUT1 == dac_out){ + DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR1; }else{ - DAC_SWT |= DAC_SWT_SWTR1; - } -} - -/*! - \brief disable DAC software trigger - \param[in] dac_periph: DACx(x = 0,1) - \param[out] none - \retval none -*/ -void dac_software_trigger_disable(uint32_t dac_periph) -{ - if(DAC0 == dac_periph){ - DAC_SWT &= ~DAC_SWT_SWTR0; - }else{ - DAC_SWT &= ~DAC_SWT_SWTR1; + /* illegal parameters */ } } /*! \brief configure DAC wave mode - \param[in] dac_periph: DACx(x = 0,1) - \param[in] wave_mode: noise wave mode + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) + \param[in] wave_mode: DAC wave mode only one parameter can be selected which is shown as below: - \arg DAC_WAVE_DISABLE: wave disable + \arg DAC_WAVE_DISABLE: wave mode disable \arg DAC_WAVE_MODE_LFSR: LFSR noise mode \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode \param[out] none \retval none */ -void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode) -{ - if(DAC0 == dac_periph){ - /* configure DAC0 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM0; - DAC_CTL |= wave_mode; - }else{ - /* configure DAC1 wave mode */ - DAC_CTL &= ~DAC_CTL_DWM1; - DAC_CTL |= (wave_mode << DAC1_REG_OFFSET); - } -} - -/*! - \brief configure DAC wave bit width - \param[in] dac_periph: DACx(x = 0,1) - \param[in] bit_width: noise wave bit width - only one parameter can be selected which is shown as below: - \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1 - \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2 - \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3 - \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4 - \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5 - \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6 - \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7 - \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8 - \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9 - \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10 - \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11 - \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12 - \param[out] none - \retval none -*/ -void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) +void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode) { - if(DAC0 == dac_periph){ - /* configure DAC0 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= bit_width; + if(DAC_OUT0 == dac_out){ + /* configure DACx_OUT0 wave mode */ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM0); + DAC_CTL0(dac_periph) |= wave_mode; + }else if(DAC_OUT1 == dac_out){ + /* configure DACx_OUT1 wave mode */ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM1); + DAC_CTL0(dac_periph) |= (wave_mode << OUT1_REG_OFFSET); }else{ - /* configure DAC1 wave bit width */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (bit_width << DAC1_REG_OFFSET); + /* illegal parameters */ } } /*! \brief configure DAC LFSR noise mode - \param[in] dac_periph: DACx(x = 0,1) - \param[in] unmask_bits: unmask LFSR bits in DAC LFSR noise mode + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) + \param[in] unmask_bits: LFSR noise unmask bits only one parameter can be selected which is shown as below: \arg DAC_LFSR_BIT0: unmask the LFSR bit0 \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0] @@ -380,23 +380,26 @@ void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width) \param[out] none \retval none */ -void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) +void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits) { - if(DAC0 == dac_periph){ - /* configure DAC0 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= unmask_bits; + if(DAC_OUT0 == dac_out){ + /* configure DACx_OUT0 LFSR noise mode */ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0); + DAC_CTL0(dac_periph) |= unmask_bits; + }else if(DAC_OUT1 == dac_out){ + /* configure DACx_OUT1 LFSR noise mode */ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1); + DAC_CTL0(dac_periph) |= (unmask_bits << OUT1_REG_OFFSET); }else{ - /* configure DAC1 LFSR noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (unmask_bits << DAC1_REG_OFFSET); + /* illegal parameters */ } } /*! \brief configure DAC triangle noise mode - \param[in] dac_periph: DACx(x = 0,1) - \param[in] amplitude: triangle amplitude in DAC triangle noise mode + \param[in] dac_periph: DACx(x=0) + \param[in] dac_out: DAC_OUTx(x=0,1) + \param[in] amplitude: the amplitude of the triangle only one parameter can be selected which is shown as below: \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1 \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3 @@ -413,127 +416,123 @@ void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits) \param[out] none \retval none */ -void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude) +void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude) { - if(DAC0 == dac_periph){ - /* configure DAC0 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW0; - DAC_CTL |= amplitude; + if(DAC_OUT0 == dac_out){ + /* configure DACx_OUT0 triangle noise mode */ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0); + DAC_CTL0(dac_periph) |= amplitude; + }else if(DAC_OUT1 == dac_out){ + /* configure DACx_OUT1 triangle noise mode */ + DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1); + DAC_CTL0(dac_periph) |= (amplitude << OUT1_REG_OFFSET); }else{ - /* configure DAC1 triangle noise mode */ - DAC_CTL &= ~DAC_CTL_DWBW1; - DAC_CTL |= (amplitude << DAC1_REG_OFFSET); + /* illegal parameters */ } } /*! \brief enable DAC concurrent mode - \param[in] none + \param[in] dac_periph: DACx(x=0) \param[out] none \retval none */ -void dac_concurrent_enable(void) +void dac_concurrent_enable(uint32_t dac_periph) { uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL |= (ctl); + + ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1); + DAC_CTL0(dac_periph) |= (uint32_t)ctl; } /*! \brief disable DAC concurrent mode - \param[in] none + \param[in] dac_periph: DACx(x=0) \param[out] none \retval none */ -void dac_concurrent_disable(void) +void dac_concurrent_disable(uint32_t dac_periph) { uint32_t ctl = 0U; - ctl = DAC_CTL_DEN0 | DAC_CTL_DEN1; - DAC_CTL &= (~ctl); -} -/*! - \brief enable DAC concurrent software trigger function - \param[in] none - \param[out] none - \retval none -*/ -void dac_concurrent_software_trigger_enable(void) -{ - uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT |= (swt); + ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1); + DAC_CTL0(dac_periph) &= (uint32_t)(~ctl); } /*! - \brief disable DAC concurrent software trigger function - \param[in] none + \brief enable DAC concurrent software trigger + \param[in] dac_periph: DACx(x=0) \param[out] none \retval none */ -void dac_concurrent_software_trigger_disable(void) +void dac_concurrent_software_trigger_enable(uint32_t dac_periph) { uint32_t swt = 0U; - swt = DAC_SWT_SWTR0 | DAC_SWT_SWTR1; - DAC_SWT &= (~swt); + + swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1); + DAC_SWT(dac_periph) |= (uint32_t)swt; } /*! \brief enable DAC concurrent buffer function - \param[in] none + \param[in] dac_periph: DACx(x=0) \param[out] none \retval none */ -void dac_concurrent_output_buffer_enable(void) +void dac_concurrent_output_buffer_enable(uint32_t dac_periph) { uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL &= (~ctl); + + ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1); + DAC_CTL0(dac_periph) &= (uint32_t)(~ctl); } /*! \brief disable DAC concurrent buffer function - \param[in] none + \param[in] dac_periph: DACx(x=0) \param[out] none \retval none */ -void dac_concurrent_output_buffer_disable(void) +void dac_concurrent_output_buffer_disable(uint32_t dac_periph) { uint32_t ctl = 0U; - ctl = DAC_CTL_DBOFF0 | DAC_CTL_DBOFF1; - DAC_CTL |= (ctl); + + ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1); + DAC_CTL0(dac_periph) |= (uint32_t)ctl; } /*! \brief set DAC concurrent mode data holding register value - \param[in] dac_align: data alignment + \param[in] dac_periph: DACx(x=0) + \param[in] dac_align: DAC data alignment mode only one parameter can be selected which is shown as below: - \arg DAC_ALIGN_8B_R: data right 8b alignment - \arg DAC_ALIGN_12B_R: data right 12b alignment - \arg DAC_ALIGN_12B_L: data left 12b alignment - \param[in] data0: data to be loaded - \param[in] data1: data to be loaded + \arg DAC_ALIGN_12B_R: 12-bit right-aligned data + \arg DAC_ALIGN_12B_L: 12-bit left-aligned data + \arg DAC_ALIGN_8B_R: 8-bit right-aligned data + \param[in] data0: data to be loaded(0~4095) + \param[in] data1: data to be loaded(0~4095) \param[out] none \retval none */ -void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1) +void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data0, uint16_t data1) { uint32_t data = 0U; + switch(dac_align){ - /* data right 12b alignment */ + /* 12-bit right-aligned data */ case DAC_ALIGN_12B_R: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_R12DH = data; + data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0); + DACC_R12DH(dac_periph) = (uint32_t)data; break; - /* data left 12b alignment */ + /* 12-bit left-aligned data */ case DAC_ALIGN_12B_L: - data = ((uint32_t)data1 << DH_12BIT_OFFSET) | data0; - DACC_L12DH = data; + data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0); + DACC_L12DH(dac_periph) = (uint32_t)data; break; - /* data right 8b alignment */ + /* 8-bit right-aligned data */ case DAC_ALIGN_8B_R: - data = ((uint32_t)data1 << DH_8BIT_OFFSET) | data0; - DACC_R8DH = data; + data = (uint32_t)(((uint32_t)data1 << DH_8BIT_OFFSET) | data0); + DACC_R8DH(dac_periph) = (uint32_t)data; break; default: break; diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c index 714b4c68..b6890e93 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dbg.c @@ -2,14 +2,11 @@ \file gd32f30x_dbg.c \brief DBG driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -80,9 +77,9 @@ void dbg_low_power_enable(uint32_t dbg_low_power) \brief disable low power behavior when the mcu is in debug mode \param[in] dbg_low_power: this parameter can be any combination of the following values: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \arg DBG_LOW_POWER_SLEEP: do not keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: do not keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: do not keep debugger connection during standby mode \param[out] none \retval none */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c index e0bb2262..53e5b8fb 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_dma.c @@ -2,14 +2,11 @@ \file gd32f30x_dma.c \brief DMA driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -616,6 +613,7 @@ void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t fla FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag) { uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + FlagStatus reval = RESET; switch(flag){ case DMA_INT_FLAG_FTF: @@ -635,10 +633,11 @@ FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx } if(interrupt_flag && interrupt_enable){ - return SET; + reval = SET; }else{ - return RESET; + reval = RESET; } + return reval; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c index 91169c1e..fa0e1e92 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_enet.c @@ -2,37 +2,33 @@ \file gd32f30x_enet.c \brief ENET driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-04-02, V2.0.1, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. - Redistribution and use in source and binary forms, with or without modification, + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, this + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ @@ -42,13 +38,13 @@ OF SUCH DAMAGE. #ifdef GD32F30X_CL #if defined (__CC_ARM) /*!< ARM compiler */ -__align(4) +__align(4) enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM]; /*!< ENET RxDMA descriptor */ -__align(4) +__align(4) enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM]; /*!< ENET TxDMA descriptor */ -__align(4) +__align(4) uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive buffer */ -__align(4) +__align(4) uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ #elif defined ( __ICCARM__ ) /*!< IAR compiler */ @@ -62,10 +58,10 @@ uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE]; /*!< ENET receive bu uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE]; /*!< ENET transmit buffer */ #elif defined (__GNUC__) /* GNU Compiler */ -enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET RxDMA descriptor */ -enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__ ((aligned (4))); /*!< ENET TxDMA descriptor */ -uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET receive buffer */ -uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__ ((aligned (4))); /*!< ENET transmit buffer */ +enet_descriptors_struct rxdesc_tab[ENET_RXBUF_NUM] __attribute__((aligned(4))); /*!< ENET RxDMA descriptor */ +enet_descriptors_struct txdesc_tab[ENET_TXBUF_NUM] __attribute__((aligned(4))); /*!< ENET TxDMA descriptor */ +uint8_t rx_buff[ENET_RXBUF_NUM][ENET_RXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET receive buffer */ +uint8_t tx_buff[ENET_TXBUF_NUM][ENET_TXBUF_SIZE] __attribute__((aligned(4))); /*!< ENET transmit buffer */ #endif /* __CC_ARM */ @@ -78,25 +74,30 @@ enet_descriptors_struct *dma_current_ptp_txdesc = NULL; enet_descriptors_struct *dma_current_ptp_rxdesc = NULL; /* init structure parameters for ENET initialization */ -static enet_initpara_struct enet_initpara ={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; +static enet_initpara_struct enet_initpara = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static uint32_t enet_unknow_err = 0U; /* array of register offset for debug information get */ static const uint16_t enet_reg_tab[] = { -0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, -0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, - -0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, - -0x0700, 0x0704,0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, - -0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, -0x104C, 0x1050, 0x1054}; + 0x0000, 0x0004, 0x0008, 0x000C, 0x0010, 0x0014, 0x0018, 0x001C, 0x0028, 0x002C, 0x0034, + 0x0038, 0x003C, 0x0040, 0x0044, 0x0048, 0x004C, 0x0050, 0x0054, 0x0058, 0x005C, 0x1080, + + 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 0x014C, 0x0150, 0x0168, 0x0194, 0x0198, 0x01C4, + + 0x0700, 0x0704, 0x0708, 0x070C, 0x0710, 0x0714, 0x0718, 0x071C, 0x0720, 0x0728, 0x072C, + + 0x1000, 0x1004, 0x1008, 0x100C, 0x1010, 0x1014, 0x1018, 0x101C, 0x1020, 0x1024, 0x1048, + 0x104C, 0x1050, 0x1054 +}; /* initialize ENET peripheral with generally concerned parameters, call it by enet_init() */ static void enet_default_init(void); +/* check whether the PHY is linked up */ +static ErrStatus enet_phy_link_check(void); +/* perform auto-negotiation operation, call it by enet_init() */ +static ErrStatus enet_phy_negoiation(uint32_t *mediamode_result); -#ifndef USE_DELAY +#if (0 == USE_DELAY) /* insert a delay time */ static void enet_delay(uint32_t ncount); #endif /* USE_DELAY */ @@ -116,16 +117,16 @@ void enet_deinit(void) /*! \brief configure the parameters which are usually less cared for initialization - note -- this function must be called before enet_init(), otherwise + note -- this function must be called before enet_init(), otherwise configuration will be no effect - \param[in] option: different function option, which is related to several parameters, + \param[in] option: different function option, which is related to several parameters, only one parameter can be selected which is shown as below, refer to enet_option_enum \arg FORWARD_OPTION: choose to configure the frame forward related parameters \arg DMABUS_OPTION: choose to configure the DMA bus mode related parameters \arg DMA_MAXBURST_OPTION: choose to configure the DMA max burst related parameters \arg DMA_ARBITRATION_OPTION: choose to configure the DMA arbitration related parameters \arg STORE_OPTION: choose to configure the store forward mode related parameters - \arg DMA_OPTION: choose to configure the DMA descriptor related parameters + \arg DMA_OPTION: choose to configure the DMA descriptor related parameters \arg VLAN_OPTION: choose to configure vlan related parameters \arg FLOWCTL_OPTION: choose to configure flow control related parameters \arg HASHH_OPTION: choose to configure hash high @@ -134,7 +135,7 @@ void enet_deinit(void) \arg HALFDUPLEX_OPTION: choose to configure halfduplex mode related parameters \arg TIMER_OPTION: choose to configure time counter related parameters \arg INTERFRAMEGAP_OPTION: choose to configure the inter frame gap related parameters - \param[in] para: the related parameters according to the option + \param[in] para: the related parameters according to the option all the related parameters should be configured which are shown as below FORWARD_OPTION related parameters: - ENET_AUTO_PADCRC_DROP_ENABLE/ ENET_AUTO_PADCRC_DROP_DISABLE ; @@ -144,7 +145,7 @@ void enet_deinit(void) DMABUS_OPTION related parameters: - ENET_ADDRESS_ALIGN_ENABLE/ ENET_ADDRESS_ALIGN_DISABLE ; - ENET_FIXED_BURST_ENABLE/ ENET_FIXED_BURST_DISABLE ; - - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; + - ENET_MIXED_BURST_ENABLE/ ENET_MIXED_BURST_DISABLE ; DMA_MAXBURST_OPTION related parameters: - ENET_RXDP_1BEAT/ ENET_RXDP_2BEAT/ ENET_RXDP_4BEAT/ ENET_RXDP_8BEAT/ ENET_RXDP_16BEAT/ ENET_RXDP_32BEAT/ @@ -180,7 +181,7 @@ void enet_deinit(void) FLOWCTL_OPTION related parameters: - MAC_FCTL_PTM(regval) ; - ENET_ZERO_QUANTA_PAUSE_ENABLE/ ENET_ZERO_QUANTA_PAUSE_DISABLE ; - - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ + - ENET_PAUSETIME_MINUS4/ ENET_PAUSETIME_MINUS28/ ENET_PAUSETIME_MINUS144/ENET_PAUSETIME_MINUS256 ; - ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT/ ENET_UNIQUE_PAUSEDETECT ; - ENET_RX_FLOWCONTROL_ENABLE/ ENET_RX_FLOWCONTROL_DISABLE ; @@ -227,92 +228,92 @@ void enet_deinit(void) */ void enet_initpara_config(enet_option_enum option, uint32_t para) { - switch(option){ - case FORWARD_OPTION: - /* choose to configure forward_frame, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; - enet_initpara.forward_frame = para; - break; - case DMABUS_OPTION: - /* choose to configure dmabus_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; - enet_initpara.dmabus_mode = para; - break; - case DMA_MAXBURST_OPTION: - /* choose to configure dma_maxburst, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; - enet_initpara.dma_maxburst = para; - break; - case DMA_ARBITRATION_OPTION: - /* choose to configure dma_arbitration, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; - enet_initpara.dma_arbitration = para; - break; - case STORE_OPTION: - /* choose to configure store_forward_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)STORE_OPTION; - enet_initpara.store_forward_mode = para; - break; - case DMA_OPTION: - /* choose to configure dma_function, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)DMA_OPTION; - -#ifndef SELECT_DESCRIPTORS_ENHANCED_MODE - para &= ~ENET_ENHANCED_DESCRIPTOR; -#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ - - enet_initpara.dma_function = para; - break; - case VLAN_OPTION: - /* choose to configure vlan_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; - enet_initpara.vlan_config = para; - break; - case FLOWCTL_OPTION: - /* choose to configure flow_control, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; - enet_initpara.flow_control = para; - break; - case HASHH_OPTION: - /* choose to configure hashtable_high, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; - enet_initpara.hashtable_high = para; - break; - case HASHL_OPTION: - /* choose to configure hashtable_low, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; - enet_initpara.hashtable_low = para; - break; - case FILTER_OPTION: - /* choose to configure framesfilter_mode, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; - enet_initpara.framesfilter_mode = para; - break; - case HALFDUPLEX_OPTION: - /* choose to configure halfduplex_param, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; - enet_initpara.halfduplex_param = para; - break; - case TIMER_OPTION: - /* choose to configure timer_config, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; - enet_initpara.timer_config = para; - break; - case INTERFRAMEGAP_OPTION: - /* choose to configure interframegap, and save the configuration parameters */ - enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; - enet_initpara.interframegap = para; - break; - default: - break; - } -} - -/*! - \brief initialize ENET peripheral with generally concerned parameters and the less cared + switch(option) { + case FORWARD_OPTION: + /* choose to configure forward_frame, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FORWARD_OPTION; + enet_initpara.forward_frame = para; + break; + case DMABUS_OPTION: + /* choose to configure dmabus_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMABUS_OPTION; + enet_initpara.dmabus_mode = para; + break; + case DMA_MAXBURST_OPTION: + /* choose to configure dma_maxburst, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_MAXBURST_OPTION; + enet_initpara.dma_maxburst = para; + break; + case DMA_ARBITRATION_OPTION: + /* choose to configure dma_arbitration, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_ARBITRATION_OPTION; + enet_initpara.dma_arbitration = para; + break; + case STORE_OPTION: + /* choose to configure store_forward_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)STORE_OPTION; + enet_initpara.store_forward_mode = para; + break; + case DMA_OPTION: + /* choose to configure dma_function, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)DMA_OPTION; + +#if (0U == SELECT_DESCRIPTORS_ENHANCED_MODE) + para &= ~ENET_ENHANCED_DESCRIPTOR; +#endif /* 0U == SELECT_DESCRIPTORS_ENHANCED_MODE */ + + enet_initpara.dma_function = para; + break; + case VLAN_OPTION: + /* choose to configure vlan_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)VLAN_OPTION; + enet_initpara.vlan_config = para; + break; + case FLOWCTL_OPTION: + /* choose to configure flow_control, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FLOWCTL_OPTION; + enet_initpara.flow_control = para; + break; + case HASHH_OPTION: + /* choose to configure hashtable_high, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHH_OPTION; + enet_initpara.hashtable_high = para; + break; + case HASHL_OPTION: + /* choose to configure hashtable_low, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HASHL_OPTION; + enet_initpara.hashtable_low = para; + break; + case FILTER_OPTION: + /* choose to configure framesfilter_mode, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)FILTER_OPTION; + enet_initpara.framesfilter_mode = para; + break; + case HALFDUPLEX_OPTION: + /* choose to configure halfduplex_param, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)HALFDUPLEX_OPTION; + enet_initpara.halfduplex_param = para; + break; + case TIMER_OPTION: + /* choose to configure timer_config, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)TIMER_OPTION; + enet_initpara.timer_config = para; + break; + case INTERFRAMEGAP_OPTION: + /* choose to configure interframegap, and save the configuration parameters */ + enet_initpara.option_enable |= (uint32_t)INTERFRAMEGAP_OPTION; + enet_initpara.interframegap = para; + break; + default: + break; + } +} + +/*! + \brief initialize ENET peripheral with generally concerned parameters and the less cared parameters \param[in] mediamode: PHY mode and mac loopback configurations, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum + which is shown as below, refer to enet_mediamode_enum \arg ENET_AUTO_NEGOTIATION: PHY auto negotiation \arg ENET_100M_FULLDUPLEX: 100Mbit/s, full-duplex \arg ENET_100M_HALFDUPLEX: 100Mbit/s, half-duplex @@ -320,302 +321,260 @@ void enet_initpara_config(enet_option_enum option, uint32_t para) \arg ENET_10M_HALFDUPLEX: 10Mbit/s, half-duplex \arg ENET_LOOPBACKMODE: MAC in loopback mode at the MII \param[in] checksum: IP frame checksum offload function, only one parameter can be selected - which is shown as below, refer to enet_mediamode_enum + which is shown as below, refer to enet_mediamode_enum \arg ENET_NO_AUTOCHECKSUM: disable IP frame checksum function \arg ENET_AUTOCHECKSUM_DROP_FAILFRAMES: enable IP frame checksum function \arg ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES: enable IP frame checksum function, and the received frame with only payload error but no other errors will not be dropped \param[in] recept: frame filter function, only one parameter can be selected - which is shown as below, refer to enet_frmrecept_enum + which is shown as below, refer to enet_frmrecept_enum \arg ENET_PROMISCUOUS_MODE: promiscuous mode enabled \arg ENET_RECEIVEALL: all received frame are forwarded to application \arg ENET_BROADCAST_FRAMES_PASS: the address filters pass all received broadcast frames \arg ENET_BROADCAST_FRAMES_DROP: the address filters filter all incoming broadcast frames - \param[out] none + \param[out] none \retval ErrStatus: ERROR or SUCCESS */ -ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept) +ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, + enet_frmrecept_enum recept) { - uint32_t reg_value=0U, reg_temp = 0U, temp = 0U; + uint32_t reg_value = 0U, reg_temp = 0U, temp = 0U; uint32_t media_temp = 0U; - uint32_t timeout = 0U; - uint16_t phy_value = 0U; - ErrStatus phy_state= ERROR, enet_state = ERROR; + uint16_t phy_value = 0U; + ErrStatus phy_state = ERROR, enet_state = SUCCESS; /* PHY interface configuration, configure SMI clock and reset PHY chip */ - if(ERROR == enet_phy_config()){ + if(ERROR == enet_phy_config()) { _ENET_DELAY_(PHY_RESETDELAY); - if(ERROR == enet_phy_config()){ - return enet_state; + if(ERROR == enet_phy_config()) { + enet_state = ERROR; } } - /* initialize ENET peripheral with generally concerned parameters */ - enet_default_init(); - - /* 1st, configure mediamode */ - media_temp = (uint32_t)mediamode; - /* if is PHY auto negotiation */ - if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp){ - /* wait for PHY_LINKED_STATUS bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_LINKED_STATUS; - timeout++; - }while((RESET == phy_value) && (timeout < PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - /* enable auto-negotiation */ - phy_value = PHY_AUTONEGOTIATION; - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; + if(SUCCESS == enet_state) { + /* initialize ENET peripheral with generally concerned parameters */ + enet_default_init(); + + /* 1st, configure mediamode */ + media_temp = (uint32_t)mediamode; + /* if is PHY auto negotiation */ + if((uint32_t)ENET_AUTO_NEGOTIATION == media_temp) { + /* Obtain the auto-negotiation result. */ + enet_state = enet_phy_negoiation(&media_temp); + } else { + phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); + phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(!phy_state) { + /* return ERROR due to write timeout */ + enet_state = ERROR; + } + /* PHY configuration need some time */ + _ENET_DELAY_(PHY_CONFIGDELAY); } + } + if(SUCCESS == enet_state) { + /* after configuring the PHY, use mediamode to configure registers */ + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM | ENET_MAC_CFG_LBM)); + reg_value |= media_temp; + ENET_MAC_CFG = reg_value; - /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ - do{ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); - phy_value &= PHY_AUTONEGO_COMPLETE; - timeout++; - }while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); - /* return ERROR due to timeout */ - if(PHY_READ_TO == timeout){ - return enet_state; - } - /* reset timeout counter */ - timeout = 0U; - /* read the result of the auto-negotiation */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); - /* configure the duplex mode of MAC following the auto-negotiation result */ - if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)){ - media_temp = ENET_MODE_FULLDUPLEX; - }else{ - media_temp = ENET_MODE_HALFDUPLEX; - } - /* configure the communication speed of MAC following the auto-negotiation result */ - if((uint16_t)RESET !=(phy_value & PHY_SPEED_STATUS)){ - media_temp |= ENET_SPEEDMODE_10M; - }else{ - media_temp |= ENET_SPEEDMODE_100M; - } - }else{ - phy_value = (uint16_t)((media_temp & ENET_MAC_CFG_DPM) >> 3); - phy_value |= (uint16_t)((media_temp & ENET_MAC_CFG_SPD) >> 1); - phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); - if(!phy_state){ - /* return ERROR due to write timeout */ - return enet_state; + /* 2st, configure checksum */ + if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)) { + ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; + + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~ENET_DMA_CTL_DTCERFD; + reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); + ENET_DMA_CTL = reg_value; } - /* PHY configuration need some time */ - _ENET_DELAY_(PHY_CONFIGDELAY); - } - /* after configuring the PHY, use mediamode to configure registers */ - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_SPD |ENET_MAC_CFG_DPM |ENET_MAC_CFG_LBM)); - reg_value |= media_temp; - ENET_MAC_CFG = reg_value; - /* 2st, configure checksum */ - if(RESET != ((uint32_t)checksum & ENET_CHECKSUMOFFLOAD_ENABLE)){ - ENET_MAC_CFG |= ENET_CHECKSUMOFFLOAD_ENABLE; + /* 3rd, configure recept */ + ENET_MAC_FRMF |= (uint32_t)recept; + + /* 4th, configure different function options */ + /* configure forward_frame related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)) { + reg_temp = enet_initpara.forward_frame; + + reg_value = ENET_MAC_CFG; + temp = reg_temp; + /* configure ENET_MAC_CFG register */ + reg_value &= (~(ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD)); + temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); + reg_value |= temp; + ENET_MAC_CFG = reg_value; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)); + temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF) << 2); + reg_value |= (temp >> 2); + ENET_DMA_CTL = reg_value; + } - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~ENET_DMA_CTL_DTCERFD; - reg_value |= ((uint32_t)checksum & ENET_DMA_CTL_DTCERFD); - ENET_DMA_CTL = reg_value; - } + /* configure dmabus_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)) { + temp = enet_initpara.dmabus_mode; - /* 3rd, configure recept */ - ENET_MAC_FRMF |= (uint32_t)recept; + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ + | ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } - /* 4th, configure different function options */ - /* configure forward_frame related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FORWARD_OPTION)){ - reg_temp = enet_initpara.forward_frame; + /* configure dma_maxburst related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)) { + temp = enet_initpara.dma_maxburst; - reg_value = ENET_MAC_CFG; - temp = reg_temp; - /* configure ENET_MAC_CFG register */ - reg_value &= (~(ENET_MAC_CFG_TFCD |ENET_MAC_CFG_APCD)); - temp &= (ENET_MAC_CFG_TFCD | ENET_MAC_CFG_APCD); - reg_value |= temp; - ENET_MAC_CFG = reg_value; + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RXDP | ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } - reg_value = ENET_DMA_CTL; - temp = reg_temp; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_FERF |ENET_DMA_CTL_FUF)); - temp &= ((ENET_DMA_CTL_FERF | ENET_DMA_CTL_FUF)<<2); - reg_value |= (temp >> 2); - ENET_DMA_CTL = reg_value; - } + /* configure dma_arbitration related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)) { + temp = enet_initpara.dma_arbitration; - /* configure dmabus_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMABUS_OPTION)){ - temp = enet_initpara.dmabus_mode; + reg_value = ENET_DMA_BCTL; + /* configure ENET_DMA_BCTL register */ + reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_AA | ENET_DMA_BCTL_FB \ - |ENET_DMA_BCTL_FPBL | ENET_DMA_BCTL_MB); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } + /* configure store_forward_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)) { + temp = enet_initpara.store_forward_mode; - /* configure dma_maxburst related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_MAXBURST_OPTION)){ - temp = enet_initpara.dma_maxburst; + reg_value = ENET_DMA_CTL; + /* configure ENET_DMA_CTL register */ + reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD | ENET_DMA_CTL_RTHC | ENET_DMA_CTL_TTHC); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + } - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RXDP| ENET_DMA_BCTL_PGBL | ENET_DMA_BCTL_UIP); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } + /* configure dma_function related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)) { + reg_temp = enet_initpara.dma_function; + + reg_value = ENET_DMA_CTL; + temp = reg_temp; + /* configure ENET_DMA_CTL register */ + reg_value &= (~(ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF)); + temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); + reg_value |= temp; + ENET_DMA_CTL = reg_value; + + reg_value = ENET_DMA_BCTL; + temp = reg_temp; + /* configure ENET_DMA_BCTL register */ + reg_value &= (~ENET_DMA_BCTL_DFM); + temp &= ENET_DMA_BCTL_DFM; + reg_value |= temp; + ENET_DMA_BCTL = reg_value; + } - /* configure dma_arbitration related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_ARBITRATION_OPTION)){ - temp = enet_initpara.dma_arbitration; + /* configure vlan_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)) { + reg_temp = enet_initpara.vlan_config; - reg_value = ENET_DMA_BCTL; - /* configure ENET_DMA_BCTL register */ - reg_value &= ~(ENET_DMA_BCTL_RTPR | ENET_DMA_BCTL_DAB); - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } + reg_value = ENET_MAC_VLT; + /* configure ENET_MAC_VLT register */ + reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); + reg_value |= reg_temp; + ENET_MAC_VLT = reg_value; + } - /* configure store_forward_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)STORE_OPTION)){ - temp = enet_initpara.store_forward_mode; - - reg_value = ENET_DMA_CTL; - /* configure ENET_DMA_CTL register */ - reg_value &= ~(ENET_DMA_CTL_RSFD | ENET_DMA_CTL_TSFD| ENET_DMA_CTL_RTHC| ENET_DMA_CTL_TTHC); - reg_value |= temp; - ENET_DMA_CTL = reg_value; - } + /* configure flow_control related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)) { + reg_temp = enet_initpara.flow_control; + + reg_value = ENET_MAC_FCTL; + temp = reg_temp; + /* configure ENET_MAC_FCTL register */ + reg_value &= ~(ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + temp &= (ENET_MAC_FCTL_PTM | ENET_MAC_FCTL_DZQP | ENET_MAC_FCTL_PLTS \ + | ENET_MAC_FCTL_UPFDT | ENET_MAC_FCTL_RFCEN | ENET_MAC_FCTL_TFCEN); + reg_value |= temp; + ENET_MAC_FCTL = reg_value; + + reg_value = ENET_MAC_FCTH; + temp = reg_temp; + /* configure ENET_MAC_FCTH register */ + reg_value &= ~(ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD); + temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD) << 8); + reg_value |= (temp >> 8); + ENET_MAC_FCTH = reg_value; + } - /* configure dma_function related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)DMA_OPTION)){ - reg_temp = enet_initpara.dma_function; - - reg_value = ENET_DMA_CTL; - temp = reg_temp; - /* configure ENET_DMA_CTL register */ - reg_value &= (~(ENET_DMA_CTL_DAFRF |ENET_DMA_CTL_OSF)); - temp &= (ENET_DMA_CTL_DAFRF | ENET_DMA_CTL_OSF); - reg_value |= temp; - ENET_DMA_CTL = reg_value; - - reg_value = ENET_DMA_BCTL; - temp = reg_temp; - /* configure ENET_DMA_BCTL register */ - reg_value &= (~ENET_DMA_BCTL_DFM); - temp &= ENET_DMA_BCTL_DFM; - reg_value |= temp; - ENET_DMA_BCTL = reg_value; - } + /* configure hashtable_high related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)) { + ENET_MAC_HLH = enet_initpara.hashtable_high; + } - /* configure vlan_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)VLAN_OPTION)){ - reg_temp = enet_initpara.vlan_config; - - reg_value = ENET_MAC_VLT; - /* configure ENET_MAC_VLT register */ - reg_value &= ~(ENET_MAC_VLT_VLTI | ENET_MAC_VLT_VLTC); - reg_value |= reg_temp; - ENET_MAC_VLT = reg_value; - } + /* configure hashtable_low related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)) { + ENET_MAC_HLL = enet_initpara.hashtable_low; + } - /* configure flow_control related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FLOWCTL_OPTION)){ - reg_temp = enet_initpara.flow_control; - - reg_value = ENET_MAC_FCTL; - temp = reg_temp; - /* configure ENET_MAC_FCTL register */ - reg_value &= ~(ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - temp &= (ENET_MAC_FCTL_PTM |ENET_MAC_FCTL_DZQP |ENET_MAC_FCTL_PLTS \ - | ENET_MAC_FCTL_UPFDT |ENET_MAC_FCTL_RFCEN |ENET_MAC_FCTL_TFCEN); - reg_value |= temp; - ENET_MAC_FCTL = reg_value; - - reg_value = ENET_MAC_FCTH; - temp = reg_temp; - /* configure ENET_MAC_FCTH register */ - reg_value &= ~(ENET_MAC_FCTH_RFA |ENET_MAC_FCTH_RFD); - temp &= ((ENET_MAC_FCTH_RFA | ENET_MAC_FCTH_RFD )<<8); - reg_value |= (temp >> 8); - ENET_MAC_FCTH = reg_value; - } - - /* configure hashtable_high related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHH_OPTION)){ - ENET_MAC_HLH = enet_initpara.hashtable_high; - } + /* configure framesfilter_mode related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)) { + reg_temp = enet_initpara.framesfilter_mode; + + reg_value = ENET_MAC_FRMF; + /* configure ENET_MAC_FRMF register */ + reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ + | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ + | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); + reg_value |= reg_temp; + ENET_MAC_FRMF = reg_value; + } - /* configure hashtable_low related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HASHL_OPTION)){ - ENET_MAC_HLL = enet_initpara.hashtable_low; - } + /* configure halfduplex_param related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)) { + reg_temp = enet_initpara.halfduplex_param; - /* configure framesfilter_mode related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)FILTER_OPTION)){ - reg_temp = enet_initpara.framesfilter_mode; - - reg_value = ENET_MAC_FRMF; - /* configure ENET_MAC_FRMF register */ - reg_value &= ~(ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT | ENET_MAC_FRMF_DAIFLT \ - | ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT | ENET_MAC_FRMF_MFD \ - | ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_PCFRM); - reg_value |= reg_temp; - ENET_MAC_FRMF = reg_value; - } + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ + | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } - /* configure halfduplex_param related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)HALFDUPLEX_OPTION)){ - reg_temp = enet_initpara.halfduplex_param; + /* configure timer_config related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)) { + reg_temp = enet_initpara.timer_config; - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_CSD | ENET_MAC_CFG_ROD | ENET_MAC_CFG_RTD \ - | ENET_MAC_CFG_BOL | ENET_MAC_CFG_DFC); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } - /* configure timer_config related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)TIMER_OPTION)){ - reg_temp = enet_initpara.timer_config; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~(ENET_MAC_CFG_WDD | ENET_MAC_CFG_JBD); - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; - } + /* configure interframegap related registers */ + if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)) { + reg_temp = enet_initpara.interframegap; - /* configure interframegap related registers */ - if(RESET != (enet_initpara.option_enable & (uint32_t)INTERFRAMEGAP_OPTION)){ - reg_temp = enet_initpara.interframegap; - - reg_value = ENET_MAC_CFG; - /* configure ENET_MAC_CFG register */ - reg_value &= ~ENET_MAC_CFG_IGBS; - reg_value |= reg_temp; - ENET_MAC_CFG = reg_value; + reg_value = ENET_MAC_CFG; + /* configure ENET_MAC_CFG register */ + reg_value &= ~ENET_MAC_CFG_IGBS; + reg_value |= reg_temp; + ENET_MAC_CFG = reg_value; + } } - - enet_state = SUCCESS; return enet_state; } @@ -635,13 +594,13 @@ ErrStatus enet_software_reset(void) ENET_DMA_BCTL |= ENET_DMA_BCTL_SWR; /* wait for reset operation complete */ - do{ + do { dma_flag = (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR); timeout++; - }while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); + } while((RESET != dma_flag) && (ENET_DELAY_TO != timeout)); - /* reset operation complete */ - if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)){ + /* reset operation complete */ + if(RESET == (ENET_DMA_BCTL & ENET_DMA_BCTL_SWR)) { enet_state = SUCCESS; } @@ -658,65 +617,59 @@ uint32_t enet_rxframe_size_get(void) { uint32_t size = 0U; uint32_t status; - + /* get rdes0 information of current RxDMA descriptor */ status = dma_current_rxdesc->status; - - /* if the desciptor is owned by DMA */ - if((uint32_t)RESET != (status & ENET_RDES0_DAV)){ - return 0U; - } - - /* if has any error, or the frame uses two or more descriptors */ - if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || - (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || - (((uint32_t)RESET) == (status & ENET_RDES0_FDES))){ + + /* if the descriptor is owned by DMA */ + if((uint32_t)RESET != (status & ENET_RDES0_DAV)) { + size = 0U; + /* if has any error, or the frame uses two or more descriptors */ + } else if((((uint32_t)RESET) != (status & ENET_RDES0_ERRS)) || + (((uint32_t)RESET) == (status & ENET_RDES0_LDES)) || + (((uint32_t)RESET) == (status & ENET_RDES0_FDES))) { /* drop current receive frame */ enet_rxframe_drop(); - - return 1U; + size = 1U; } -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#if SELECT_DESCRIPTORS_ENHANCED_MODE /* if is an ethernet-type frame, and IP frame payload error occurred */ - if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && - ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)){ + else if(((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FRMT) && + ((uint32_t)RESET) != (dma_current_rxdesc->extended_status & ENET_RDES4_IPPLDERR)) { /* drop current receive frame */ enet_rxframe_drop(); - - return 1U; + size = 1U; } #else /* if is an ethernet-type frame, and IP frame payload error occurred */ - if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && - (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))){ - /* drop current receive frame */ - enet_rxframe_drop(); - - return 1U; + else if((((uint32_t)RESET) != (status & ENET_RDES0_FRMT)) && + (((uint32_t)RESET) != (status & ENET_RDES0_PCERR))) { + /* drop current receive frame */ + enet_rxframe_drop(); + size = 1U; } -#endif +#endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ /* if CPU owns current descriptor, no error occured, the frame uses only one descriptor */ - if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && - (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (status & ENET_RDES0_FDES))){ + else if((((uint32_t)RESET) == (status & ENET_RDES0_DAV)) && + (((uint32_t)RESET) == (status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (status & ENET_RDES0_FDES))) { /* get the size of the received data including CRC */ size = GET_RDES0_FRML(status); - /* substract the CRC size */ + /* substract the CRC size */ size = size - 4U; - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))){ + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (status & ENET_RDES0_FRMT))) { size = size + 4U; } - }else{ + } else { enet_unknow_err++; enet_rxframe_drop(); - - return 1U; + size = 1U; } - /* return packet size */ + /* return packet size */ return size; } @@ -734,10 +687,10 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) uint32_t num = 0U, count = 0U, maxsize = 0U; uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; - uint8_t *buf; + uint8_t *buf; /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; @@ -750,7 +703,7 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; @@ -762,32 +715,32 @@ void enet_descriptors_chain_init(enet_dmadirection_enum direction) desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; /* configure each descriptor */ - for(num=0U; num < count; num++){ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t) desc_tab; + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t) desc_tab; } } } @@ -807,59 +760,59 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc; enet_descriptors_struct *desc_tab; - uint8_t *buf; + uint8_t *buf; /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; + maxsize = ENET_TXBUF_SIZE; /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; + maxsize = ENET_RXBUF_SIZE; /* enable receiving */ desc_status = ENET_RDES0_DAV; /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - /* configure DMA Rx descriptor table address register */ + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } dma_current_ptp_rxdesc = NULL; dma_current_ptp_txdesc = NULL; - /* configure each descriptor */ - for(num=0U; num < count; num++){ + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } @@ -877,73 +830,77 @@ void enet_descriptors_ring_init(enet_dmadirection_enum direction) ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize) { uint32_t offset = 0U, size = 0U; - + ErrStatus status = SUCCESS; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status); - size = size - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + status = ERROR; + } else { + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if((((uint32_t)RESET) == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + (((uint32_t)RESET) != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status); + size = size - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && + (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize) { + status = ERROR; + } else { + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); + } + } + + } else { + /* return ERROR */ + status = ERROR; } + } + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; + } - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offsetbuffer1_addr) + offset)); + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptors table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } - - }else{ - /* return ERROR */ - return ERROR; - } - } - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); } } - return SUCCESS; + return status; } /*! - \brief handle application buffer data to transmit it + \brief handle application buffer data to transmit it \param[in] buffer: pointer to the frame data to be transmitted, note -- if the input is NULL, user should handle the data in application by himself \param[in] length: the length of frame data to be transmitted @@ -954,59 +911,59 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) { uint32_t offset = 0U; uint32_t dma_tbu_flag, dma_tu_flag; + ErrStatus status = SUCCESS; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + status = ERROR; + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + } else if(length > ENET_MAX_FRAME_SIZE) { + status = ERROR; + } else { + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } } - } - /* set the frame length */ - dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; + } - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptors table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + + ETH_DMATXDESC_SIZE + (GET_DMA_BCTL_DPSL(ENET_DMA_BCTL))); + } } } - return SUCCESS; + return status; } /*! @@ -1023,13 +980,15 @@ ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length) */ ErrStatus enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum) { - if(NULL != desc){ + ErrStatus status = SUCCESS; + if(NULL != desc) { desc->status &= ~ENET_TDES0_CM; desc->status |= checksum; - return SUCCESS; - }else{ - return ERROR; + status = SUCCESS; + } else { + status = ERROR; } + return status; } /*! @@ -1057,18 +1016,18 @@ void enet_disable(void) } /*! - \brief configure MAC address - \param[in] mac_addr: select which MAC address will be set, - only one parameter can be selected which is shown as below + \brief configure MAC address + \param[in] mac_addr: select which MAC address will be set, + only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: set MAC address 0 filter \arg ENET_MAC_ADDRESS1: set MAC address 1 filter \arg ENET_MAC_ADDRESS2: set MAC address 2 filter \arg ENET_MAC_ADDRESS3: set MAC address 3 filter \param[in] paddr: the buffer pointer which stores the MAC address - (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as MAC address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \param[out] none \retval none -*/ +*/ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) { REG32(ENET_ADDRH_BASE + (uint32_t)mac_addr) = ENET_SET_MACADDRH(paddr); @@ -1076,7 +1035,7 @@ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) } /*! - \brief get MAC address + \brief get MAC address \param[in] mac_addr: select which MAC address will be get, only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS0: get MAC address 0 filter @@ -1084,15 +1043,16 @@ void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]) \arg ENET_MAC_ADDRESS2: get MAC address 2 filter \arg ENET_MAC_ADDRESS3: get MAC address 3 filter \param[out] paddr: the buffer pointer which is stored the MAC address - (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) + (little-ending store, such as mac address is aa:bb:cc:dd:ee:22, the buffer is {22, ee, dd, cc, bb, aa}) \param[in] bufsize: refer to the size of the buffer which stores the MAC address \arg 6 - 255 \retval ErrStatus: ERROR, SUCCESS -*/ +*/ ErrStatus enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[], uint8_t bufsize) { - if(bufsize < 6U){ - return ERROR; + ErrStatus status = SUCCESS; + if(bufsize < 6U) { + status = ERROR; } paddr[0] = ENET_GET_MACADDR(mac_addr, 0U); paddr[1] = ENET_GET_MACADDR(mac_addr, 1U); @@ -1100,16 +1060,16 @@ ErrStatus enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[], u paddr[3] = ENET_GET_MACADDR(mac_addr, 3U); paddr[4] = ENET_GET_MACADDR(mac_addr, 4U); paddr[5] = ENET_GET_MACADDR(mac_addr, 5U); - return SUCCESS; + return status; } /*! - \brief get the ENET MAC/MSC/PTP/DMA status flag + \brief get the ENET MAC/MSC/PTP/DMA status flag \param[in] enet_flag: ENET status flag, refer to enet_flag_enum, only one parameter can be selected which is shown as below - \arg ENET_MAC_FLAG_MPKR: magic packet received flag + \arg ENET_MAC_FLAG_MPKR: magic packet received flag \arg ENET_MAC_FLAG_WUFR: wakeup frame received flag - \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag + \arg ENET_MAC_FLAG_FLOWCONTROL: flow control status flag \arg ENET_MAC_FLAG_WUM: WUM status flag \arg ENET_MAC_FLAG_MSC: MSC status flag \arg ENET_MAC_FLAG_MSCR: MSC receive status flag @@ -1149,15 +1109,15 @@ ErrStatus enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[], u */ FlagStatus enet_flag_get(enet_flag_enum enet_flag) { - if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))){ - return SET; - }else{ - return RESET; + FlagStatus status = RESET; + if(RESET != (ENET_REG_VAL(enet_flag) & BIT(ENET_BIT_POS(enet_flag)))) { + status = SET; } + return status; } /*! - \brief clear the ENET DMA status flag + \brief clear the ENET DMA status flag \param[in] enet_flag: ENET DMA flag clear, refer to enet_flag_clear_enum only one parameter can be selected which is shown as below \arg ENET_DMA_FLAG_TS_CLR: transmit status flag clear @@ -1185,7 +1145,7 @@ void enet_flag_clear(enet_flag_clear_enum enet_flag) } /*! - \brief enable ENET MAC/MSC/DMA interrupt + \brief enable ENET MAC/MSC/DMA interrupt \param[in] enet_int: ENET interrupt, only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask @@ -1216,17 +1176,17 @@ void enet_flag_clear(enet_flag_clear_enum enet_flag) */ void enet_interrupt_enable(enet_int_enum enet_int) { - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { /* ENET_DMA_INTEN register interrupt */ ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); - }else{ + } else { /* other INTMSK register interrupt */ ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); } } /*! - \brief disable ENET MAC/MSC/DMA interrupt + \brief disable ENET MAC/MSC/DMA interrupt \param[in] enet_int: ENET interrupt, only one parameter can be selected which is shown as below \arg ENET_MAC_INT_WUMIM: WUM interrupt mask @@ -1257,17 +1217,17 @@ void enet_interrupt_enable(enet_int_enum enet_int) */ void enet_interrupt_disable(enet_int_enum enet_int) { - if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)){ + if(DMA_INTEN_REG_OFFSET == ((uint32_t)enet_int >> 6)) { /* ENET_DMA_INTEN register interrupt */ ENET_REG_VAL(enet_int) &= ~BIT(ENET_BIT_POS(enet_int)); - }else{ + } else { /* other INTMSK register interrupt */ ENET_REG_VAL(enet_int) |= BIT(ENET_BIT_POS(enet_int)); } } /*! - \brief get ENET MAC/MSC/DMA interrupt flag + \brief get ENET MAC/MSC/DMA interrupt flag \param[in] int_flag: ENET interrupt flag, only one parameter can be selected which is shown as below \arg ENET_MAC_INT_FLAG_WUM: WUM status flag @@ -1304,15 +1264,15 @@ void enet_interrupt_disable(enet_int_enum enet_int) */ FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag) { - if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))){ - return SET; - }else{ - return RESET; + FlagStatus status = RESET; + if(RESET != (ENET_REG_VAL(int_flag) & BIT(ENET_BIT_POS(int_flag)))) { + status = SET; } + return status; } /*! - \brief clear ENET DMA interrupt flag + \brief clear ENET DMA interrupt flag \param[in] int_flag_clear: clear ENET interrupt flag, only one parameter can be selected which is shown as below \arg ENET_DMA_INT_FLAG_TS_CLR: transmit status flag @@ -1359,7 +1319,7 @@ void enet_tx_enable(void) \retval none */ void enet_tx_disable(void) -{ +{ ENET_DMA_CTL &= ~ENET_DMA_CTL_STE; enet_txfifo_flush(); ENET_MAC_CFG &= ~ENET_MAC_CFG_TEN; @@ -1390,10 +1350,10 @@ void enet_rx_disable(void) } /*! - \brief put registers value into the application buffer + \brief put registers value into the application buffer \param[in] type: register type which will be get, refer to enet_registers_type_enum, only one parameter can be selected which is shown as below - \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH + \arg ALL_MAC_REG: get the registers within the offset scope between ENET_MAC_CFG and ENET_MAC_FCTH \arg ALL_MSC_REG: get the registers within the offset scope between ENET_MSC_CTL and ENET_MSC_RGUFCNT \arg ALL_PTP_REG: get the registers within the offset scope between ENET_PTP_TSCTL and ENET_PTP_PPSCTL \arg ALL_DMA_REG: get the registers within the offset scope between ENET_DMA_BCTL and ENET_DMA_CRBADDR @@ -1407,16 +1367,16 @@ void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t offset = (uint32_t)type; max = (uint32_t)type + num; - limit = sizeof(enet_reg_tab)/sizeof(uint16_t); + limit = sizeof(enet_reg_tab) / sizeof(uint16_t); /* prevent element in this array is out of range */ - if(max > limit){ + if(max > limit) { max = limit; } - for(; offset < max; offset++){ + for(; offset < max; offset++) { /* get value of the corresponding register */ - *preg = REG32((ENET) + enet_reg_tab[offset]); + *preg = REG32((ENET) + enet_reg_tab[offset]); preg++; } } @@ -1444,34 +1404,34 @@ uint32_t enet_debug_status_get(uint32_t mac_debug) { uint32_t temp_state = 0U; - switch(mac_debug){ - case ENET_RX_ASYNCHRONOUS_FIFO_STATE: - temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); - break; - case ENET_RXFIFO_READ_STATUS: - temp_state = GET_MAC_DBG_RXFRS(ENET_MAC_DBG); - break; - case ENET_RXFIFO_STATE: - temp_state = GET_MAC_DBG_RXFS(ENET_MAC_DBG); - break; - case ENET_MAC_TRANSMITTER_STATUS: - temp_state = GET_MAC_DBG_SOMT(ENET_MAC_DBG); - break; - case ENET_TXFIFO_READ_STATUS: - temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); - break; - default: - if(RESET != (ENET_MAC_DBG & mac_debug)){ - temp_state = 0x1U; - } - break; + switch(mac_debug) { + case ENET_RX_ASYNCHRONOUS_FIFO_STATE: + temp_state = GET_MAC_DBG_RXAFS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_RXFRS(ENET_MAC_DBG); + break; + case ENET_RXFIFO_STATE: + temp_state = GET_MAC_DBG_RXFS(ENET_MAC_DBG); + break; + case ENET_MAC_TRANSMITTER_STATUS: + temp_state = GET_MAC_DBG_SOMT(ENET_MAC_DBG); + break; + case ENET_TXFIFO_READ_STATUS: + temp_state = GET_MAC_DBG_TXFRS(ENET_MAC_DBG); + break; + default: + if(RESET != (ENET_MAC_DBG & mac_debug)) { + temp_state = 0x1U; + } + break; } return temp_state; } /*! - \brief enable the MAC address filter - \param[in] mac_addr: select which MAC address will be enable + \brief enable the MAC address filter + \param[in] mac_addr: select which MAC address will be enable \arg ENET_MAC_ADDRESS1: enable MAC address 1 filter \arg ENET_MAC_ADDRESS2: enable MAC address 2 filter \arg ENET_MAC_ADDRESS3: enable MAC address 3 filter @@ -1484,7 +1444,7 @@ void enet_address_filter_enable(enet_macaddress_enum mac_addr) } /*! - \brief disable the MAC address filter + \brief disable the MAC address filter \param[in] mac_addr: select which MAC address will be disable, only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: disable MAC address 1 filter @@ -1499,7 +1459,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) } /*! - \brief configure the MAC address filter + \brief configure the MAC address filter \param[in] mac_addr: select which MAC address will be configured, only one parameter can be selected which is shown as below \arg ENET_MAC_ADDRESS1: configure MAC address 1 filter @@ -1508,7 +1468,7 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) \param[in] addr_mask: select which MAC address bytes will be mask, one or more parameters can be selected which are shown as below \arg ENET_ADDRESS_MASK_BYTE0: mask ENET_MAC_ADDR1L[7:0] bits - \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits + \arg ENET_ADDRESS_MASK_BYTE1: mask ENET_MAC_ADDR1L[15:8] bits \arg ENET_ADDRESS_MASK_BYTE2: mask ENET_MAC_ADDR1L[23:16] bits \arg ENET_ADDRESS_MASK_BYTE3: mask ENET_MAC_ADDR1L [31:24] bits \arg ENET_ADDRESS_MASK_BYTE4: mask ENET_MAC_ADDR1H [7:0] bits @@ -1520,7 +1480,8 @@ void enet_address_filter_disable(enet_macaddress_enum mac_addr) \param[out] none \retval none */ -void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type) +void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, + uint32_t filter_type) { uint32_t reg; @@ -1538,13 +1499,13 @@ void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mas \param[in] none \param[out] none \retval ErrStatus: SUCCESS or ERROR -*/ +*/ ErrStatus enet_phy_config(void) { uint32_t ahbclk; uint32_t reg; uint16_t phy_value; - ErrStatus enet_state = ERROR; + ErrStatus status = SUCCESS; /* clear the previous MDC clock */ reg = ENET_MAC_PHY_CTL; @@ -1554,38 +1515,38 @@ ErrStatus enet_phy_config(void) ahbclk = rcu_clock_freq_get(CK_AHB); /* configure MDC clock according to HCLK frequency range */ - if(ENET_RANGE(ahbclk, 20000000U, 35000000U)){ + if(ENET_RANGE(ahbclk, 20000000U, 35000000U)) { reg |= ENET_MDC_HCLK_DIV16; - }else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)){ + } else if(ENET_RANGE(ahbclk, 35000000U, 60000000U)) { reg |= ENET_MDC_HCLK_DIV26; - }else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)){ + } else if(ENET_RANGE(ahbclk, 60000000U, 100000000U)) { reg |= ENET_MDC_HCLK_DIV42; - }else if((ENET_RANGE(ahbclk, 100000000U, 168000000U))||(168000000U == ahbclk)){ - reg |= ENET_MDC_HCLK_DIV62; - }else{ - return enet_state; + } else if((ENET_RANGE(ahbclk, 100000000U, 168000000U)) || (168000000U == ahbclk)) { + reg |= ENET_MDC_HCLK_DIV62; + } else { + status = ERROR; } ENET_MAC_PHY_CTL = reg; /* reset PHY */ phy_value = PHY_RESET; - if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; + if(ERROR == (enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { + status = ERROR; } - /* PHY reset need some time */ + /* PHY reset need some time */ _ENET_DELAY_(ENET_DELAY_TO); - + /* check whether PHY reset is complete */ - if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))){ - return enet_state; + if(ERROR == (enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &phy_value))) { + status = ERROR; } /* PHY reset complete */ - if(RESET == (phy_value & PHY_RESET)){ - enet_state = SUCCESS; + if(RESET != (phy_value & PHY_RESET)) { + status = ERROR; } - return enet_state; + return status; } /*! @@ -1595,41 +1556,41 @@ ErrStatus enet_phy_config(void) \arg ENET_PHY_READ: read data from phy register \param[in] phy_address: 0x0 - 0x1F \param[in] phy_reg: 0x0 - 0x1F - \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction + \param[in] pvalue: the value will be written to the PHY register in ENET_PHY_WRITE direction \param[out] pvalue: the value will be read from the PHY register in ENET_PHY_READ direction \retval ErrStatus: SUCCESS or ERROR */ -ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue) +ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, + uint16_t phy_reg, uint16_t *pvalue) { uint32_t reg, phy_flag; uint32_t timeout = 0U; ErrStatus enet_state = ERROR; - /* configure ENET_MAC_PHY_CTL with write/read operation */ + /* configure ENET_MAC_PHY_CTL with write/read operation */ reg = ENET_MAC_PHY_CTL; reg &= ~(ENET_MAC_PHY_CTL_PB | ENET_MAC_PHY_CTL_PW | ENET_MAC_PHY_CTL_PR | ENET_MAC_PHY_CTL_PA); reg |= (direction | MAC_PHY_CTL_PR(phy_reg) | MAC_PHY_CTL_PA(phy_address) | ENET_MAC_PHY_CTL_PB); /* if do the write operation, write value to the register */ - if(ENET_PHY_WRITE == direction){ + if(ENET_PHY_WRITE == direction) { ENET_MAC_PHY_DATA = *pvalue; } /* do PHY write/read operation, and wait the operation complete */ ENET_MAC_PHY_CTL = reg; - do{ + do { phy_flag = (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB); timeout++; - } - while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); + } while((RESET != phy_flag) && (ENET_DELAY_TO != timeout)); /* write/read operation complete */ - if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)){ + if(RESET == (ENET_MAC_PHY_CTL & ENET_MAC_PHY_CTL_PB)) { enet_state = SUCCESS; } /* if do the read operation, get value from the register */ - if(ENET_PHY_READ == direction){ + if(ENET_PHY_READ == direction) { *pvalue = (uint16_t)ENET_MAC_PHY_DATA; } @@ -1648,7 +1609,7 @@ ErrStatus enet_phyloopback_enable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* enable the PHY loopback mode */ temp_phy |= PHY_LOOPBACK; @@ -1671,7 +1632,7 @@ ErrStatus enet_phyloopback_disable(void) ErrStatus phy_state = ERROR; /* get the PHY configuration to update it */ - enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BCR, &temp_phy); /* disable the PHY loopback mode */ temp_phy &= (uint16_t)~PHY_LOOPBACK; @@ -1725,10 +1686,10 @@ void enet_forward_feature_disable(uint32_t feature) mask = (feature & (~(ENET_AUTO_PADCRC_DROP | ENET_TYPEFRAME_CRC_DROP))); ENET_DMA_CTL &= ~(mask >> 2); } - -/*! - \brief enable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, + +/*! + \brief enable ENET filter feature + \param[in] feature: the feature of ENET filter mode, one or more parameters can be selected which are shown as below \arg ENET_SRC_FILTER: filter source address function \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function @@ -1740,14 +1701,14 @@ void enet_forward_feature_disable(uint32_t feature) \param[out] none \retval none */ -void enet_fliter_feature_enable(uint32_t feature) +void enet_filter_feature_enable(uint32_t feature) { ENET_MAC_FRMF |= feature; } /*! - \brief disable ENET fliter feature - \param[in] feature: the feature of ENET fliter mode, + \brief disable ENET filter feature + \param[in] feature: the feature of ENET filter mode, one or more parameters can be selected which are shown as below \arg ENET_SRC_FILTER: filter source address function \arg ENET_SRC_FILTER_INVERSE: inverse source address filtering result function @@ -1759,7 +1720,7 @@ void enet_fliter_feature_enable(uint32_t feature) \param[out] none \retval none */ -void enet_fliter_feature_disable(uint32_t feature) +void enet_filter_feature_disable(uint32_t feature) { ENET_MAC_FRMF &= ~feature; } @@ -1772,17 +1733,17 @@ void enet_fliter_feature_disable(uint32_t feature) \retval ErrStatus: ERROR or SUCCESS */ ErrStatus enet_pauseframe_generate(void) -{ - ErrStatus enet_state =ERROR; +{ + ErrStatus enet_state = ERROR; uint32_t temp = 0U; /* in full-duplex mode, must make sure this bit is 0 before writing register */ temp = ENET_MAC_FCTL & ENET_MAC_FCTL_FLCBBKPA; - if(RESET == temp){ + if(RESET == temp) { ENET_MAC_FCTL |= ENET_MAC_FCTL_FLCBBKPA; enet_state = SUCCESS; } - return enet_state; + return enet_state; } /*! @@ -1791,7 +1752,7 @@ ErrStatus enet_pauseframe_generate(void) only one parameter can be selected which is shown as below \arg ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT: besides the unique multicast address, MAC can also use the MAC0 address to detecting pause frame - \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified + \arg ENET_UNIQUE_PAUSEDETECT: only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected \param[out] none \retval none @@ -1824,7 +1785,7 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) /*! \brief configure the threshold of the flow control(deactive and active threshold) \param[in] deactive: the threshold of the deactive flow control, this value - should always be less than active flow control value, only one + should always be less than active flow control value, only one parameter can be selected which is shown as below \arg ENET_DEACTIVE_THRESHOLD_256BYTES: threshold level is 256 bytes \arg ENET_DEACTIVE_THRESHOLD_512BYTES: threshold level is 512 bytes @@ -1847,7 +1808,7 @@ void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold) */ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) { - ENET_MAC_FCTH = ((deactive | active) >> 8); + ENET_MAC_FCTH = ((deactive | active) >> 8); } /*! @@ -1863,7 +1824,7 @@ void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active) */ void enet_flowcontrol_feature_enable(uint32_t feature) { - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { ENET_MAC_FCTL &= ~ENET_ZERO_QUANTA_PAUSE; } feature &= ~ENET_ZERO_QUANTA_PAUSE; @@ -1883,7 +1844,7 @@ void enet_flowcontrol_feature_enable(uint32_t feature) */ void enet_flowcontrol_feature_disable(uint32_t feature) { - if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)){ + if(RESET != (feature & ENET_ZERO_QUANTA_PAUSE)) { ENET_MAC_FCTL |= ENET_ZERO_QUANTA_PAUSE; } feature &= ~ENET_ZERO_QUANTA_PAUSE; @@ -1892,7 +1853,7 @@ void enet_flowcontrol_feature_disable(uint32_t feature) /*! \brief get the dma transmit/receive process state - \param[in] direction: choose the direction of dma process which users want to check, + \param[in] direction: choose the direction of dma process which users want to check, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below \arg ENET_DMA_TX: dma transmit process \arg ENET_DMA_RX: dma receive process @@ -1911,9 +1872,9 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) } /*! - \brief poll the DMA transmission/reception enable by writing any value to the + \brief poll the DMA transmission/reception enable by writing any value to the ENET_DMA_TPEN/ENET_DMA_RPEN register, this will make the DMA to resume transmission/reception - \param[in] direction: choose the direction of DMA process which users want to resume, + \param[in] direction: choose the direction of DMA process which users want to resume, refer to enet_dmadirection_enum, only one parameter can be selected which is shown as below \arg ENET_DMA_TX: DMA transmit process \arg ENET_DMA_RX: DMA receive process @@ -1922,15 +1883,15 @@ uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction) */ void enet_dmaprocess_resume(enet_dmadirection_enum direction) { - if(ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { ENET_DMA_TPEN = 0U; - }else{ + } else { ENET_DMA_RPEN = 0U; } } /*! - \brief check and recover the Rx process + \brief check and recover the Rx process \param[in] none \param[out] none \retval none @@ -1939,15 +1900,15 @@ void enet_rxprocess_check_recovery(void) { uint32_t status; - /* get DAV information of current RxDMA descriptor */ + /* get DAV information of current RxDMA descriptor */ status = dma_current_rxdesc->status; status &= ENET_RDES0_DAV; - /* if current descriptor is owned by DMA, but the descriptor address mismatches with + /* if current descriptor is owned by DMA, but the descriptor address mismatches with receive descriptor address pointer updated by RxDMA controller */ if((ENET_DMA_CRDADDR != ((uint32_t)dma_current_rxdesc)) && - (ENET_RDES0_DAV == status)){ - dma_current_rxdesc = (enet_descriptors_struct*)ENET_DMA_CRDADDR; + (ENET_RDES0_DAV == status)) { + dma_current_rxdesc = (enet_descriptors_struct *)ENET_DMA_CRDADDR; } } @@ -1964,14 +1925,14 @@ ErrStatus enet_txfifo_flush(void) ErrStatus enet_state = ERROR; /* set the FTF bit for flushing transmit FIFO */ - ENET_DMA_CTL |= ENET_DMA_CTL_FTF; + ENET_DMA_CTL |= ENET_DMA_CTL_FTF; /* wait until the flush operation completes */ - do{ - flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; + do { + flush_state = ENET_DMA_CTL & ENET_DMA_CTL_FTF; timeout++; - }while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); + } while((RESET != flush_state) && (timeout < ENET_DELAY_TO)); /* return ERROR due to timeout */ - if(RESET == flush_state){ + if(RESET == flush_state) { enet_state = SUCCESS; } @@ -1990,14 +1951,14 @@ ErrStatus enet_txfifo_flush(void) \arg ENET_TX_CURRENT_DESC: the start descriptor address of the current transmit descriptor read by the TxDMA controller \arg ENET_TX_CURRENT_BUFFER: the current transmit buffer address being read by the TxDMA controller - \param[out] none + \param[out] none \retval address value */ uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get) { uint32_t reval = 0U; - reval = REG32((ENET) +(uint32_t)addr_get); + reval = REG32((ENET) + (uint32_t)addr_get); return reval; } @@ -2019,38 +1980,38 @@ uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate { uint32_t reval = 0xFFFFFFFFU; - switch(info_get){ - case RXDESC_BUFFER_1_SIZE: - reval = GET_RDES1_RB1S(desc->control_buffer_size); - break; - case RXDESC_BUFFER_2_SIZE: - reval = GET_RDES1_RB2S(desc->control_buffer_size); - break; - case RXDESC_FRAME_LENGTH: - reval = GET_RDES0_FRML(desc->status); - if(reval > 4U){ - reval = reval - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))){ - reval = reval + 4U; + switch(info_get) { + case RXDESC_BUFFER_1_SIZE: + reval = GET_RDES1_RB1S(desc->control_buffer_size); + break; + case RXDESC_BUFFER_2_SIZE: + reval = GET_RDES1_RB2S(desc->control_buffer_size); + break; + case RXDESC_FRAME_LENGTH: + reval = GET_RDES0_FRML(desc->status); + if(reval > 4U) { + reval = reval - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (desc->status & ENET_RDES0_FRMT))) { + reval = reval + 4U; + } + } else { + reval = 0U; } - }else{ - reval = 0U; - } - break; - case RXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_BUFFER_1_ADDR: - reval = desc->buffer1_addr; - break; - case TXDESC_COLLISION_COUNT: - reval = GET_TDES0_COCNT(desc->status); - break; - default: - break; + break; + case RXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_BUFFER_1_ADDR: + reval = desc->buffer1_addr; + break; + case TXDESC_COLLISION_COUNT: + reval = GET_TDES0_COCNT(desc->status); + break; + default: + break; } return reval; } @@ -2076,7 +2037,7 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \param[in] desc: the descriptor pointer which users want to get flag \param[in] desc_flag: the bit flag of ENET DMA descriptor, only one parameter can be selected which is shown as below - \arg ENET_TDES0_DB: deferred + \arg ENET_TDES0_DB: deferred \arg ENET_TDES0_UFE: underflow error \arg ENET_TDES0_EXD: excessive deferral \arg ENET_TDES0_VFRM: VLAN frame @@ -2089,18 +2050,18 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_TDES0_JT: jabber timeout \arg ENET_TDES0_ES: error summary \arg ENET_TDES0_IPHE: IP header error - \arg ENET_TDES0_TTMSS: transmit timestamp status + \arg ENET_TDES0_TTMSS: transmit timestamp status \arg ENET_TDES0_TCHM: the second address chained mode \arg ENET_TDES0_TERM: transmit end of ring mode \arg ENET_TDES0_TTSEN: transmit timestamp function enable - \arg ENET_TDES0_DPAD: disable adding pad + \arg ENET_TDES0_DPAD: disable adding pad \arg ENET_TDES0_DCRC: disable CRC \arg ENET_TDES0_FSG: first segment \arg ENET_TDES0_LSG: last segment \arg ENET_TDES0_INTC: interrupt on completion \arg ENET_TDES0_DAV: DAV bit - - \arg ENET_RDES0_PCERR: payload checksum error + + \arg ENET_RDES0_PCERR: payload checksum error \arg ENET_RDES0_EXSV: extended status valid \arg ENET_RDES0_CERR: CRC error \arg ENET_RDES0_DBERR: dribble bit error @@ -2113,7 +2074,7 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) \arg ENET_RDES0_LDES: last descriptor \arg ENET_RDES0_FDES: first descriptor \arg ENET_RDES0_VTAG: VLAN tag - \arg ENET_RDES0_OERR: overflow error + \arg ENET_RDES0_OERR: overflow error \arg ENET_RDES0_LERR: length error \arg ENET_RDES0_SAFF: SA filter fail \arg ENET_RDES0_DERR: descriptor error @@ -2126,8 +2087,8 @@ void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop) FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag) { FlagStatus enet_flag = RESET; - - if((uint32_t)RESET != (desc->status & desc_flag)){ + + if((uint32_t)RESET != (desc->status & desc_flag)) { enet_flag = SET; } @@ -2185,7 +2146,7 @@ void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag) } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will immediately set \param[in] desc: the descriptor pointer which users want to configure \param[out] none \retval none @@ -2196,13 +2157,14 @@ void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct * } /*! - \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time + \brief when receiving completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time \param[in] desc: the descriptor pointer which users want to configure \param[in] delay_time: delay a time of 256*delay_time HCLK, this value must be between 0 and 0xFF \param[out] none \retval none */ -void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time) +void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, + uint32_t delay_time) { desc->control_buffer_size |= ENET_RDES1_DINTC; ENET_DMA_RSWDC = DMA_RSWDC_WDCFRS(delay_time); @@ -2220,33 +2182,34 @@ void enet_rxframe_drop(void) dma_current_rxdesc->status = ENET_RDES0_DAV; /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - if(NULL != dma_current_ptp_rxdesc){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + if(NULL != dma_current_ptp_rxdesc) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ + if(0U != dma_current_ptp_rxdesc->status) { /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* pointer to the next ptp descriptor */ dma_current_ptp_rxdesc++; } - }else{ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); + } else { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - if(NULL != dma_current_ptp_rxdesc){ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + if(NULL != dma_current_ptp_rxdesc) { + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); } - }else{ + } else { /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - if(NULL != dma_current_ptp_rxdesc){ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + if(NULL != dma_current_ptp_rxdesc) { dma_current_ptp_rxdesc++; } } @@ -2281,7 +2244,7 @@ void enet_dma_feature_disable(uint32_t feature) ENET_DMA_CTL &= ~feature; } -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#if SELECT_DESCRIPTORS_ENHANCED_MODE /*! \brief get the bit of extended status flag in ENET DMA descriptor \param[in] desc: the descriptor pointer which users want to get the extended status flag @@ -2302,22 +2265,22 @@ void enet_dma_feature_disable(uint32_t feature) uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status) { uint32_t reval = 0xFFFFFFFFU; - - switch (desc_status){ - case ENET_RDES4_IPPLDT: - reval = GET_RDES4_IPPLDT(desc->extended_status); - break; - case ENET_RDES4_PTPMT: - reval = GET_RDES4_PTPMT(desc->extended_status); - break; - default: - if ((uint32_t)RESET != (desc->extended_status & desc_status)){ - reval = 1U; - }else{ - reval = 0U; - } + + switch(desc_status) { + case ENET_RDES4_IPPLDT: + reval = GET_RDES4_IPPLDT(desc->extended_status); + break; + case ENET_RDES4_PTPMT: + reval = GET_RDES4_PTPMT(desc->extended_status); + break; + default: + if((uint32_t)RESET != (desc->extended_status & desc_status)) { + reval = 1U; + } else { + reval = 0U; + } } - + return reval; } @@ -2347,59 +2310,59 @@ void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc, *desc_tab; uint8_t *buf; - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; - + maxsize = ENET_TXBUF_SIZE; + /* select chain mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* select receive chained mode and set buffer1 size */ desc_bufsize = ENET_RDES1_RCHM | (uint32_t)ENET_RXBUF_SIZE; - + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } - - /* configuration each descriptor */ - for(num = 0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ - /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + } else { + /* when it is the last descriptor, the next descriptor address + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; } - } + } } /*! @@ -2417,69 +2380,69 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) uint32_t desc_status = 0U, desc_bufsize = 0U; enet_descriptors_struct *desc; enet_descriptors_struct *desc_tab; - uint8_t *buf; - + uint8_t *buf; + /* configure descriptor skip length */ ENET_DMA_BCTL &= ~ENET_DMA_BCTL_DPSL; ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); - + /* if want to initialize DMA Tx descriptors */ - if (ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; + maxsize = ENET_TXBUF_SIZE; /* select ring mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TTSEN; - + /* configure DMA Tx descriptor table address register */ ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; - + maxsize = ENET_RXBUF_SIZE; + /* enable receiving */ desc_status = ENET_RDES0_DAV; /* set buffer1 size */ desc_bufsize = ENET_RXBUF_SIZE; - - /* configure DMA Rx descriptor table address register */ + + /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; - dma_current_rxdesc = desc_tab; + dma_current_rxdesc = desc_tab; } - - /* configure each descriptor */ - for(num=0U; num < count; num++){ + + /* configure each descriptor */ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; - desc->control_buffer_size = desc_bufsize; - desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + desc->status = desc_status; + desc->control_buffer_size = desc_bufsize; + desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); + /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ - /* configure transmit end of ring mode */ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { + /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } } - } + } } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode \param[in] bufsize: the size of buffer which is the parameter in function \param[out] buffer: pointer to the application buffer note -- if the input is NULL, user should copy data in application by himself @@ -2487,97 +2450,102 @@ void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction) note -- if the input is NULL, timestamp is ignored \retval ErrStatus: SUCCESS or ERROR */ -ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) +ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, + uint32_t timestamp[]) { uint32_t offset = 0U, size = 0U; uint32_t timeout = 0U; uint32_t rdes0_tsv_flag; - + ErrStatus status = SUCCESS; + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ - size = size + 4U; - } - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + status = ERROR; + } else { + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && + (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize) { + status = ERROR; + } else { + + /* copy data from Rx buffer to application buffer */ + for(offset = 0; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); + } + } + } else { + status = ERROR; } + } - /* copy data from Rx buffer to application buffer */ - for(offset = 0; offset < size; offset++){ - (*(buffer + offset)) = (*(__IO uint8_t *)((dma_current_rxdesc->buffer1_addr) + offset)); + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if((NULL != timestamp) && (SUCCESS == status)) { + /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and + write to the RDES6 and RDES7 */ + do { + rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); + timeout++; + } while((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + status = ERROR; + } else { + /* clear the ENET_RDES0_TSV flag */ + dma_current_rxdesc->status &= ~ENET_RDES0_TSV; + /* get the timestamp value of the received frame */ + timestamp[0] = dma_current_rxdesc->timestamp_low; + timestamp[1] = dma_current_rxdesc->timestamp_high; } - }else{ - return ERROR; } - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_RDES0_TSV flag to be set, the timestamp value is taken and - write to the RDES6 and RDES7 */ - do{ - rdes0_tsv_flag = (dma_current_rxdesc->status & ENET_RDES0_TSV); - timeout++; - }while ((RESET == rdes0_tsv_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; + + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* Clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0; } - - /* clear the ENET_RDES0_TSV flag */ - dma_current_rxdesc->status &= ~ENET_RDES0_TSV; - /* get the timestamp value of the received frame */ - timestamp[0] = dma_current_rxdesc->timestamp_low; - timestamp[1] = dma_current_rxdesc->timestamp_high; - } - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* Clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0; - } - - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_rxdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptors table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_rxdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } } } - - return SUCCESS; + return status; } /*! - \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode + \brief send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode \param[in] buffer: pointer on the application buffer note -- if the input is NULL, user should copy data in application by himself \param[in] length: the length of frame data to be transmitted @@ -2586,84 +2554,84 @@ ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, \param[out] none \retval ErrStatus: SUCCESS or ERROR */ -ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) +ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, + uint32_t timestamp[]) { uint32_t offset = 0; uint32_t dma_tbu_flag, dma_tu_flag; uint32_t tdes0_ttmss_flag; - uint32_t timeout = 0; - + uint32_t timeout = 0; + ErrStatus status = SUCCESS; + /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0; offset < length; offset++){ - (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + status = ERROR; + } else if(length > ENET_MAX_FRAME_SIZE) { + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + status = ERROR; + } else { + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0; offset < length; offset++) { + (*(__IO uint8_t *)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } } - } - /* set the frame length */ - dma_current_txdesc->control_buffer_size = length; - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if ((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* Clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0; - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ - tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); - timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; + /* set the frame length */ + dma_current_txdesc->control_buffer_size = length; + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* Clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0; } - - /* clear the ENET_TDES0_TTMSS flag */ - dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; - /* get the timestamp value of the transmit frame */ - timestamp[0] = dma_current_txdesc->timestamp_low; - timestamp[1] = dma_current_txdesc->timestamp_high; - } - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table*/ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_txdesc->buffer2_next_desc_addr); - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) ((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp) { + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do { + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + status = ERROR; + } else { + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->timestamp_low; + timestamp[1] = dma_current_txdesc->timestamp_high; + } } - } - return SUCCESS; + /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptors table*/ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_txdesc->buffer2_next_desc_addr); + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + } + } + } + return status; } #else @@ -2689,7 +2657,8 @@ void enet_desc_select_normal_mode(void) \param[out] none \retval none */ -void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, + enet_descriptors_struct *desc_ptptab) { uint32_t num = 0U, count = 0U, maxsize = 0U; uint32_t desc_status = 0U, desc_bufsize = 0U; @@ -2697,12 +2666,12 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en uint8_t *buf; /* if want to initialize DMA Tx descriptors */ - if(ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; + maxsize = ENET_TXBUF_SIZE; /* select chain mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TCHM | ENET_TDES0_TTSEN; @@ -2711,13 +2680,13 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; dma_current_ptp_txdesc = desc_ptptab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; buf = &rx_buff[0][0]; count = ENET_RXBUF_NUM; - maxsize = ENET_RXBUF_SIZE; + maxsize = ENET_RXBUF_SIZE; /* enable receiving */ desc_status = ENET_RDES0_DAV; @@ -2727,27 +2696,27 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en /* configure DMA Rx descriptor table address register */ ENET_DMA_RDTADDR = (uint32_t)desc_tab; dma_current_rxdesc = desc_tab; - dma_current_ptp_rxdesc = desc_ptptab; + dma_current_ptp_rxdesc = desc_ptptab; } /* configure each descriptor */ - for(num = 0U; num < count; num++){ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; /* configure descriptors */ - desc->status = desc_status; + desc->status = desc_status; desc->control_buffer_size = desc_bufsize; desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); - + /* if is not the last descriptor */ - if(num < (count - 1U)){ + if(num < (count - 1U)) { /* configure the next descriptor address */ desc->buffer2_next_desc_addr = (uint32_t)(desc_tab + num + 1U); - }else{ + } else { /* when it is the last descriptor, the next descriptor address - equals to first descriptor address in descriptor table */ - desc->buffer2_next_desc_addr = (uint32_t)desc_tab; + equals to first descriptor address in descriptor table */ + desc->buffer2_next_desc_addr = (uint32_t)desc_tab; } /* set desc_ptptab equal to desc_tab */ (&desc_ptptab[num])->buffer1_addr = desc->buffer1_addr; @@ -2755,7 +2724,7 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en } /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; } /*! @@ -2768,7 +2737,8 @@ void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, en \param[out] none \retval none */ -void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab) +void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, + enet_descriptors_struct *desc_ptptab) { uint32_t num = 0U, count = 0U, maxsize = 0U; uint32_t desc_status = 0U, desc_bufsize = 0U; @@ -2780,12 +2750,12 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene ENET_DMA_BCTL |= DMA_BCTL_DPSL(0); /* if want to initialize DMA Tx descriptors */ - if(ENET_DMA_TX == direction){ + if(ENET_DMA_TX == direction) { /* save a copy of the DMA Tx descriptors */ desc_tab = txdesc_tab; buf = &tx_buff[0][0]; count = ENET_TXBUF_NUM; - maxsize = ENET_TXBUF_SIZE; + maxsize = ENET_TXBUF_SIZE; /* select ring mode, and enable transmit timestamp function */ desc_status = ENET_TDES0_TTSEN; @@ -2794,7 +2764,7 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene ENET_DMA_TDTADDR = (uint32_t)desc_tab; dma_current_txdesc = desc_tab; dma_current_ptp_txdesc = desc_ptptab; - }else{ + } else { /* if want to initialize DMA Rx descriptors */ /* save a copy of the DMA Rx descriptors */ desc_tab = rxdesc_tab; @@ -2814,7 +2784,7 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene } /* configure each descriptor */ - for(num = 0U; num < count; num++){ + for(num = 0U; num < count; num++) { /* get the pointer to the next descriptor of the descriptor table */ desc = desc_tab + num; @@ -2824,11 +2794,11 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene desc->buffer1_addr = (uint32_t)(&buf[num * maxsize]); /* when it is the last descriptor */ - if(num == (count - 1U)){ - if (ENET_DMA_TX == direction){ + if(num == (count - 1U)) { + if(ENET_DMA_TX == direction) { /* configure transmit end of ring mode */ desc->status |= ENET_TDES0_TERM; - }else{ + } else { /* configure receive end of ring mode */ desc->control_buffer_size |= ENET_RDES1_RERM; } @@ -2839,11 +2809,11 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene } /* when it is the last ptp descriptor, preserve the first descriptor address of desc_ptptab in ptp descriptor status */ - (&desc_ptptab[num-1U])->status = (uint32_t)desc_ptptab; + (&desc_ptptab[num - 1U])->status = (uint32_t)desc_ptptab; } /*! - \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode + \brief receive a packet data with timestamp values to application buffer, when the DMA is in normal mode \param[in] bufsize: the size of buffer which is the parameter in function \param[out] timestamp: pointer to the table which stores the timestamp high and low \param[out] buffer: pointer to the application buffer @@ -2853,86 +2823,90 @@ void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, ene ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]) { uint32_t offset = 0U, size = 0U; - + ErrStatus status = SUCCESS; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has copied data in application */ - if(NULL != buffer){ - /* if no error occurs, and the frame uses only one descriptor */ - if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && - ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))){ - - /* get the frame length except CRC */ - size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; - /* if is a type frame, and CRC is not included in forwarding frame */ - if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))){ - size = size + 4U; + if((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_DAV)) { + status = ERROR; + } else { + + /* if buffer pointer is null, indicates that users has copied data in application */ + if(NULL != buffer) { + /* if no error occurs, and the frame uses only one descriptor */ + if(((uint32_t)RESET == (dma_current_rxdesc->status & ENET_RDES0_ERRS)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_LDES)) && + ((uint32_t)RESET != (dma_current_rxdesc->status & ENET_RDES0_FDES))) { + + /* get the frame length except CRC */ + size = GET_RDES0_FRML(dma_current_rxdesc->status) - 4U; + /* if is a type frame, and CRC is not included in forwarding frame */ + if((RESET != (ENET_MAC_CFG & ENET_MAC_CFG_TFCD)) && + (RESET != (dma_current_rxdesc->status & ENET_RDES0_FRMT))) { + size = size + 4U; + } + + /* to avoid situation that the frame size exceeds the buffer length */ + if(size > bufsize) { + status = ERROR; + } else { + + /* copy data from Rx buffer to application buffer */ + for(offset = 0U; offset < size; offset++) { + (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); + } + } + + } else { + status = ERROR; } - - /* to avoid situation that the frame size exceeds the buffer length */ - if(size > bufsize){ - return ERROR; - } - - /* copy data from Rx buffer to application buffer */ - for(offset = 0U; offset < size; offset++){ - (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_rxdesc->buffer1_addr) + offset)); - } - - }else{ - return ERROR; } - } - /* copy timestamp value from Rx descriptor to application array */ - timestamp[0] = dma_current_rxdesc->buffer1_addr; - timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; - dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; - dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; + /* copy timestamp value from Rx descriptor to application array */ + timestamp[0] = dma_current_rxdesc->buffer1_addr; + timestamp[1] = dma_current_rxdesc->buffer2_next_desc_addr; - /* enable reception, descriptor is owned by DMA */ - dma_current_rxdesc->status = ENET_RDES0_DAV; - - /* check Rx buffer unavailable flag status */ - if ((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)){ - /* clear RBU flag */ - ENET_DMA_STAT = ENET_DMA_STAT_RBU; - /* resume DMA reception by writing to the RPEN register*/ - ENET_DMA_RPEN = 0U; - } + dma_current_rxdesc->buffer1_addr = dma_current_ptp_rxdesc ->buffer1_addr ; + dma_current_rxdesc->buffer2_next_desc_addr = dma_current_ptp_rxdesc ->buffer2_next_desc_addr; - /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)){ - dma_current_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_rxdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_rxdesc++; + /* enable reception, descriptor is owned by DMA */ + dma_current_rxdesc->status = ENET_RDES0_DAV; + + /* check Rx buffer unavailable flag status */ + if((uint32_t)RESET != (ENET_DMA_STAT & ENET_DMA_STAT_RBU)) { + /* clear RBU flag */ + ENET_DMA_STAT = ENET_DMA_STAT_RBU; + /* resume DMA reception by writing to the RPEN register*/ + ENET_DMA_RPEN = 0U; } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_rxdesc = (enet_descriptors_struct*) (ENET_DMA_RDTADDR); - /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with RxDMA descriptor */ - dma_current_ptp_rxdesc = (enet_descriptors_struct*) (dma_current_ptp_rxdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_rxdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_rxdesc + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_rxdesc ++; + + /* update the current RxDMA descriptor pointer to the next decriptor in RxDMA decriptors table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RCHM)) { + dma_current_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_rxdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* pointer to the next ptp descriptor */ + dma_current_ptp_rxdesc++; + } + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_rxdesc->control_buffer_size & ENET_RDES1_RERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_rxdesc = (enet_descriptors_struct *)(ENET_DMA_RDTADDR); + /* RDES2 and RDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with RxDMA descriptor */ + dma_current_ptp_rxdesc = (enet_descriptors_struct *)(dma_current_ptp_rxdesc->status); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_rxdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_rxdesc + + ETH_DMARXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_rxdesc ++; + } } } - - return SUCCESS; + return status; } /*! @@ -2947,98 +2921,100 @@ ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, u ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]) { uint32_t offset = 0U, timeout = 0U; - uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + uint32_t dma_tbu_flag, dma_tu_flag, tdes0_ttmss_flag; + ErrStatus status = SUCCESS; /* the descriptor is busy due to own by the DMA */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)){ - return ERROR; - } - - /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ - if(length > ENET_MAX_FRAME_SIZE){ - return ERROR; - } - - /* if buffer pointer is null, indicates that users has handled data in application */ - if(NULL != buffer){ - /* copy frame data from application buffer to Tx buffer */ - for(offset = 0U; offset < length; offset++){ - (*(__IO uint8_t *) (uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_DAV)) { + status = ERROR; + } else if(length > ENET_MAX_FRAME_SIZE) { + /* only frame length no more than ENET_MAX_FRAME_SIZE is allowed */ + status = ERROR; + } else { + + /* if buffer pointer is null, indicates that users has handled data in application */ + if(NULL != buffer) { + /* copy frame data from application buffer to Tx buffer */ + for(offset = 0U; offset < length; offset++) { + (*(__IO uint8_t *)(uint32_t)((dma_current_ptp_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); + } } - } - /* set the frame length */ - dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); - /* set the segment of frame, frame is transmitted in one descriptor */ - dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; - /* enable the DMA transmission */ - dma_current_txdesc->status |= ENET_TDES0_DAV; - - /* check Tx buffer unavailable flag status */ - dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); - dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); - - if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)){ - /* clear TBU and TU flag */ - ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); - /* resume DMA transmission by writing to the TPEN register*/ - ENET_DMA_TPEN = 0U; - } - - /* if timestamp pointer is null, indicates that users don't care timestamp in application */ - if(NULL != timestamp){ - /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ - do{ - tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); - timeout++; - }while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); - - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - return ERROR; + /* set the frame length */ + dma_current_txdesc->control_buffer_size = (length & (uint32_t)0x1FFF); + /* set the segment of frame, frame is transmitted in one descriptor */ + dma_current_txdesc->status |= ENET_TDES0_LSG | ENET_TDES0_FSG; + /* enable the DMA transmission */ + dma_current_txdesc->status |= ENET_TDES0_DAV; + + /* check Tx buffer unavailable flag status */ + dma_tbu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TBU); + dma_tu_flag = (ENET_DMA_STAT & ENET_DMA_STAT_TU); + + if((RESET != dma_tbu_flag) || (RESET != dma_tu_flag)) { + /* clear TBU and TU flag */ + ENET_DMA_STAT = (dma_tbu_flag | dma_tu_flag); + /* resume DMA transmission by writing to the TPEN register*/ + ENET_DMA_TPEN = 0U; } - /* clear the ENET_TDES0_TTMSS flag */ - dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; - /* get the timestamp value of the transmit frame */ - timestamp[0] = dma_current_txdesc->buffer1_addr; - timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; - } - dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; - dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; - - /* update the current TxDMA descriptor pointer to the next decriptor in TxDMA decriptor table */ - /* chained mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)){ - dma_current_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->buffer2_next_desc_addr); - /* if it is the last ptp descriptor */ - if(0U != dma_current_ptp_txdesc->status){ - /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* ponter to the next ptp descriptor */ - dma_current_ptp_txdesc++; + /* if timestamp pointer is null, indicates that users don't care timestamp in application */ + if(NULL != timestamp) { + /* wait for ENET_TDES0_TTMSS flag to be set, a timestamp was captured */ + do { + tdes0_ttmss_flag = (dma_current_txdesc->status & ENET_TDES0_TTMSS); + timeout++; + } while((RESET == tdes0_ttmss_flag) && (timeout < ENET_DELAY_TO)); + + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + status = ERROR; + } else { + + /* clear the ENET_TDES0_TTMSS flag */ + dma_current_txdesc->status &= ~ENET_TDES0_TTMSS; + /* get the timestamp value of the transmit frame */ + timestamp[0] = dma_current_txdesc->buffer1_addr; + timestamp[1] = dma_current_txdesc->buffer2_next_desc_addr; + } } - }else{ - /* ring mode */ - if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)){ - /* if is the last descriptor in table, the next descriptor is the table header */ - dma_current_txdesc = (enet_descriptors_struct*) (ENET_DMA_TDTADDR); - /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, - use the same table with TxDMA descriptor */ - dma_current_ptp_txdesc = (enet_descriptors_struct*) (dma_current_ptp_txdesc->status); - }else{ - /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ - dma_current_txdesc = (enet_descriptors_struct*) (uint32_t)((uint32_t)dma_current_txdesc + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); - dma_current_ptp_txdesc ++; + dma_current_txdesc->buffer1_addr = dma_current_ptp_txdesc ->buffer1_addr ; + dma_current_txdesc->buffer2_next_desc_addr = dma_current_ptp_txdesc ->buffer2_next_desc_addr; + + /* update the current TxDMA descriptor pointer to the next descriptors in TxDMA descriptors table */ + /* chained mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TCHM)) { + dma_current_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->buffer2_next_desc_addr); + /* if it is the last ptp descriptor */ + if(0U != dma_current_ptp_txdesc->status) { + /* pointer back to the first ptp descriptor address in the desc_ptptab list address */ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { + /* pointer to the next ptp descriptor */ + dma_current_ptp_txdesc++; + } + } else { + /* ring mode */ + if((uint32_t)RESET != (dma_current_txdesc->status & ENET_TDES0_TERM)) { + /* if is the last descriptor in table, the next descriptor is the table header */ + dma_current_txdesc = (enet_descriptors_struct *)(ENET_DMA_TDTADDR); + /* TDES2 and TDES3 will not be covered by buffer address, so do not need to preserve a new table, + use the same table with TxDMA descriptor */ + dma_current_ptp_txdesc = (enet_descriptors_struct *)(dma_current_ptp_txdesc->status); + } else { + /* the next descriptor is the current address, add the descriptor size, and descriptor skip length */ + dma_current_txdesc = (enet_descriptors_struct *)(uint32_t)((uint32_t)dma_current_txdesc + + ETH_DMATXDESC_SIZE + GET_DMA_BCTL_DPSL(ENET_DMA_BCTL)); + dma_current_ptp_txdesc ++; + } } } - return SUCCESS; + return status; } #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ /*! - \brief wakeup frame filter register pointer reset + \brief wakeup frame filter register pointer reset \param[in] none \param[out] none \retval none @@ -3049,7 +3025,7 @@ void enet_wum_filter_register_pointer_reset(void) } /*! - \brief set the remote wakeup frame registers + \brief set the remote wakeup frame registers \param[in] pdata: pointer to buffer data which is written to remote wakeup frame registers (8 words total) \param[out] none \retval none @@ -3059,13 +3035,13 @@ void enet_wum_filter_config(uint32_t pdata[]) uint32_t num = 0U; /* configure ENET_MAC_RWFF register */ - for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++){ + for(num = 0U; num < ETH_WAKEUP_REGISTER_LENGTH; num++) { ENET_MAC_RWFF = pdata[num]; } } /*! - \brief enable wakeup management features + \brief enable wakeup management features \param[in] feature: one or more parameters can be selected which are shown as below \arg ENET_WUM_POWER_DOWN: power down mode \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception @@ -3080,7 +3056,7 @@ void enet_wum_feature_enable(uint32_t feature) } /*! - \brief disable wakeup management features + \brief disable wakeup management features \param[in] feature: one or more parameters can be selected which are shown as below \arg ENET_WUM_MAGIC_PACKET_FRAME: enable a wakeup event due to magic packet reception \arg ENET_WUM_WAKE_UP_FRAME: enable a wakeup event due to wakeup frame reception @@ -3094,8 +3070,8 @@ void enet_wum_feature_disable(uint32_t feature) } /*! - \brief reset the MAC statistics counters - \param[in] none + \brief reset the MAC statistics counters + \param[in] none \param[out] none \retval none */ @@ -3130,11 +3106,11 @@ void enet_msc_feature_enable(uint32_t feature) */ void enet_msc_feature_disable(uint32_t feature) { - ENET_MSC_CTL &= (~feature); + ENET_MSC_CTL &= (~feature); } /*! - \brief configure MAC statistics counters preset mode + \brief configure MAC statistics counters preset mode \param[in] mode: MSC counters preset mode, refer to enet_msc_preset_enum, only one parameter can be selected which is shown as below \arg ENET_MSC_PRESET_NONE: do not preset MSC counter @@ -3150,7 +3126,7 @@ void enet_msc_counters_preset_config(enet_msc_preset_enum mode) } /*! - \brief get MAC statistics counter + \brief get MAC statistics counter \param[in] counter: MSC counters which is selected, refer to enet_msc_counter_enum, only one parameter can be selected which is shown as below \arg ENET_MSC_TX_SCCNT: MSC transmitted good frames after a single collision counter @@ -3172,7 +3148,7 @@ uint32_t enet_msc_counters_get(enet_msc_counter_enum counter) } /*! - \brief change subsecond to nanosecond + \brief change subsecond to nanosecond \param[in] subsecond: subsecond value \param[out] none \retval the nanosecond value @@ -3185,7 +3161,7 @@ uint32_t enet_ptp_subsecond_2_nanosecond(uint32_t subsecond) } /*! - \brief change nanosecond to subsecond + \brief change nanosecond to subsecond \param[in] nanosecond: nanosecond value \param[out] none \retval the subsecond value @@ -3265,61 +3241,61 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) uint32_t timeout = 0U; ErrStatus enet_state = SUCCESS; - switch(func){ - case ENET_CKNT_ORDINARY: - case ENET_CKNT_BOUNDARY: - case ENET_CKNT_END_TO_END: - case ENET_CKNT_PEER_TO_PEER: - ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; - ENET_PTP_TSCTL |= (uint32_t)func; - break; - case ENET_PTP_ADDEND_UPDATE: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; - } - break; - case ENET_PTP_SYSTIME_UPDATE: - /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ - do{ - temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; - } - break; - case ENET_PTP_SYSTIME_INIT: - /* this bit must be read as zero before application set it */ - do{ - temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; - timeout++; - }while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); - /* return ERROR due to timeout */ - if(ENET_DELAY_TO == timeout){ - enet_state = ERROR; - }else{ - ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; - } - break; - default: - temp_config = (uint32_t)func & (~BIT(31)); - if(RESET != ((uint32_t)func & BIT(31))){ - ENET_PTP_TSCTL |= temp_config; - }else{ - ENET_PTP_TSCTL &= ~temp_config; - } - break; + switch(func) { + case ENET_CKNT_ORDINARY: + case ENET_CKNT_BOUNDARY: + case ENET_CKNT_END_TO_END: + case ENET_CKNT_PEER_TO_PEER: + ENET_PTP_TSCTL &= ~ENET_PTP_TSCTL_CKNT; + ENET_PTP_TSCTL |= (uint32_t)func; + break; + case ENET_PTP_ADDEND_UPDATE: + /* this bit must be read as zero before application set it */ + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSARU; + timeout++; + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSARU; + } + break; + case ENET_PTP_SYSTIME_UPDATE: + /* both the TMSSTU and TMSSTI bits must be read as zero before application set this bit */ + do { + temp_state = ENET_PTP_TSCTL & (ENET_PTP_TSCTL_TMSSTU | ENET_PTP_TSCTL_TMSSTI); + timeout++; + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTU; + } + break; + case ENET_PTP_SYSTIME_INIT: + /* this bit must be read as zero before application set it */ + do { + temp_state = ENET_PTP_TSCTL & ENET_PTP_TSCTL_TMSSTI; + timeout++; + } while((RESET != temp_state) && (timeout < ENET_DELAY_TO)); + /* return ERROR due to timeout */ + if(ENET_DELAY_TO == timeout) { + enet_state = ERROR; + } else { + ENET_PTP_TSCTL |= ENET_PTP_TSCTL_TMSSTI; + } + break; + default: + temp_config = (uint32_t)func & (~BIT(31)); + if(RESET != ((uint32_t)func & BIT(31))) { + ENET_PTP_TSCTL |= temp_config; + } else { + ENET_PTP_TSCTL &= ~temp_config; + } + break; } return enet_state; @@ -3327,7 +3303,7 @@ ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func) /*! \brief configure system time subsecond increment value - \param[in] subsecond: the value will be added to the subsecond value of system time, + \param[in] subsecond: the value will be added to the subsecond value of system time, this value must be between 0 and 0xFF \param[out] none \retval none @@ -3355,7 +3331,7 @@ void enet_ptp_timestamp_addend_config(uint32_t add) \arg ENET_PTP_ADD_TO_TIME: timestamp update value is added to system time \arg ENET_PTP_SUBSTRACT_FROM_TIME: timestamp update value is subtracted from system time \param[in] second: initializing or adding/subtracting to second of the system time - \param[in] subsecond: the current subsecond of the system time + \param[in] subsecond: the current subsecond of the system time with 0.46 ns accuracy if required accuracy is 20 ns \param[out] none \retval none @@ -3382,7 +3358,7 @@ void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond) /*! \brief get the current system time \param[in] none - \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains + \param[out] systime_struct: pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF @@ -3394,11 +3370,11 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) { uint32_t temp_sec = 0U, temp_subs = 0U; - /* get the value of sysytem time registers */ + /* get the value of system time registers */ temp_sec = (uint32_t)ENET_PTP_TSH; temp_subs = (uint32_t)ENET_PTP_TSL; - - /* get sysytem time and construct the enet_ptp_systime_struct structure */ + + /* get system time and construct the enet_ptp_systime_struct structure */ systime_struct->second = temp_sec; systime_struct->nanosecond = GET_PTP_TSL_STMSS(temp_subs); systime_struct->nanosecond = enet_ptp_subsecond_2_nanosecond(systime_struct->nanosecond); @@ -3410,15 +3386,15 @@ void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct) \param[in] freq: PPS output frequency, only one parameter can be selected which is shown as below \arg ENET_PPSOFC_1HZ: PPS output 1Hz frequency - \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency - \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency - \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency - \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency - \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency + \arg ENET_PPSOFC_2HZ: PPS output 2Hz frequency + \arg ENET_PPSOFC_4HZ: PPS output 4Hz frequency + \arg ENET_PPSOFC_8HZ: PPS output 8Hz frequency + \arg ENET_PPSOFC_16HZ: PPS output 16Hz frequency + \arg ENET_PPSOFC_32HZ: PPS output 32Hz frequency \arg ENET_PPSOFC_64HZ: PPS output 64Hz frequency \arg ENET_PPSOFC_128HZ: PPS output 128Hz frequency \arg ENET_PPSOFC_256HZ: PPS output 256Hz frequency - \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency + \arg ENET_PPSOFC_512HZ: PPS output 512Hz frequency \arg ENET_PPSOFC_1024HZ: PPS output 1024Hz frequency \arg ENET_PPSOFC_2048HZ: PPS output 2048Hz frequency \arg ENET_PPSOFC_4096HZ: PPS output 4096Hz frequency @@ -3445,7 +3421,8 @@ void enet_ptp_pps_output_frequency_config(uint32_t freq) \param[out] none \retval none */ -void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, uint32_t carry_cfg, uint32_t accuracy_cfg) +void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subsec, + uint32_t carry_cfg, uint32_t accuracy_cfg) { /* mask the timestamp trigger interrupt */ enet_interrupt_disable(ENET_MAC_INT_TMSTIM); @@ -3456,12 +3433,12 @@ void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subse /* configure system time subsecond increment based on the PTP clock frequency */ enet_ptp_subsecond_increment_config(accuracy_cfg); - if(ENET_PTP_FINEMODE == updatemethod){ + if(ENET_PTP_FINEMODE == updatemethod) { /* fine correction method: configure the timestamp addend, then update */ enet_ptp_timestamp_addend_config(carry_cfg); enet_ptp_timestamp_function_config(ENET_PTP_ADDEND_UPDATE); /* wait until update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)){ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_ADDEND_UPDATE)) { } } @@ -3472,7 +3449,7 @@ void enet_ptp_start(int32_t updatemethod, uint32_t init_sec, uint32_t init_subse enet_ptp_timestamp_update_config(ENET_PTP_ADD_TO_TIME, init_sec, init_subsec); enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); -#ifdef SELECT_DESCRIPTORS_ENHANCED_MODE +#if SELECT_DESCRIPTORS_ENHANCED_MODE enet_desc_select_enhanced_mode(); #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ } @@ -3516,7 +3493,7 @@ void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_s enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_UPDATE); /* wait until the update is completed */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)){ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_UPDATE)) { } /* write back the carry_cfg value, then update */ @@ -3526,7 +3503,7 @@ void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_s /*! \brief set system time in fine method - \param[in] systime_struct: : pointer to a enet_ptp_systime_struct structure which contains + \param[in] systime_struct: : pointer to a enet_ptp_systime_struct structure which contains parameters of PTP system time members of the structure and the member values are shown as below: second: 0x0 - 0xFFFF FFFF @@ -3535,7 +3512,7 @@ void enet_ptp_coarsecorrection_systime_update(enet_ptp_systime_struct *systime_s \param[out] none \retval none */ -void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) +void enet_ptp_finecorrection_settime(enet_ptp_systime_struct *systime_struct) { uint32_t subsecond_val; @@ -3544,15 +3521,15 @@ void enet_ptp_finecorrection_settime(enet_ptp_systime_struct * systime_struct) /* initialize the system time */ enet_ptp_timestamp_update_config(systime_struct->sign, systime_struct->second, subsecond_val); enet_ptp_timestamp_function_config(ENET_PTP_SYSTIME_INIT); - + /* wait until the system time initialzation finished */ - while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)){ + while(SET == enet_ptp_flag_get((uint32_t)ENET_PTP_SYSTIME_INIT)) { } } /*! \brief get the ptp flag status - \param[in] flag: ptp flag status to be checked + \param[in] flag: ptp flag status to be checked \arg ENET_PTP_ADDEND_UPDATE: addend register update \arg ENET_PTP_SYSTIME_UPDATE: timestamp update \arg ENET_PTP_SYSTIME_INIT: timestamp initialize @@ -3563,7 +3540,7 @@ FlagStatus enet_ptp_flag_get(uint32_t flag) { FlagStatus bitstatus = RESET; - if ((uint32_t)RESET != (ENET_PTP_TSCTL & flag)){ + if((uint32_t)RESET != (ENET_PTP_TSCTL & flag)) { bitstatus = SET; } @@ -3584,7 +3561,7 @@ void enet_initpara_reset(void) enet_initpara.dma_maxburst = 0U; enet_initpara.dma_arbitration = 0U; enet_initpara.store_forward_mode = 0U; - enet_initpara.dma_function = 0U; + enet_initpara.dma_function = 0U; enet_initpara.vlan_config = 0U; enet_initpara.flow_control = 0U; enet_initpara.hashtable_high = 0U; @@ -3596,7 +3573,7 @@ void enet_initpara_reset(void) } /*! - \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() + \brief initialize ENET peripheral with generally concerned parameters, call it by enet_init() \param[in] none \param[out] none \retval none @@ -3610,20 +3587,20 @@ static void enet_default_init(void) reg_value = ENET_MAC_CFG; reg_value &= MAC_CFG_MASK; reg_value |= ENET_WATCHDOG_ENABLE | ENET_JABBER_ENABLE | ENET_INTERFRAMEGAP_96BIT \ - | ENET_SPEEDMODE_10M |ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ - | ENET_CARRIERSENSE_ENABLE | ENET_RECEIVEOWN_ENABLE \ - | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ - | ENET_DEFERRALCHECK_DISABLE \ - | ENET_TYPEFRAME_CRC_DROP_DISABLE \ - | ENET_AUTO_PADCRC_DROP_DISABLE \ - | ENET_CHECKSUMOFFLOAD_DISABLE; + | ENET_SPEEDMODE_10M | ENET_MODE_HALFDUPLEX | ENET_LOOPBACKMODE_DISABLE \ + | ENET_CARRIERSENSE_DISABLE | ENET_RECEIVEOWN_ENABLE \ + | ENET_RETRYTRANSMISSION_ENABLE | ENET_BACKOFFLIMIT_10 \ + | ENET_DEFERRALCHECK_DISABLE \ + | ENET_TYPEFRAME_CRC_DROP_DISABLE \ + | ENET_AUTO_PADCRC_DROP_DISABLE \ + | ENET_CHECKSUMOFFLOAD_DISABLE; ENET_MAC_CFG = reg_value; /* configure ENET_MAC_FRMF register */ - ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE |ENET_DEST_FILTER_INVERSE_DISABLE \ - |ENET_MULTICAST_FILTER_PERFECT |ENET_UNICAST_FILTER_PERFECT \ - |ENET_PCFRM_PREVENT_ALL |ENET_BROADCASTFRAMES_ENABLE \ - |ENET_PROMISCUOUS_DISABLE |ENET_RX_FILTER_ENABLE; + ENET_MAC_FRMF = ENET_SRC_FILTER_DISABLE | ENET_DEST_FILTER_INVERSE_DISABLE \ + | ENET_MULTICAST_FILTER_PERFECT | ENET_UNICAST_FILTER_PERFECT \ + | ENET_PCFRM_PREVENT_ALL | ENET_BROADCASTFRAMES_ENABLE \ + | ENET_PROMISCUOUS_DISABLE | ENET_RX_FILTER_ENABLE; /* configure ENET_MAC_HLH, ENET_MAC_HLL register */ ENET_MAC_HLH = 0x0U; @@ -3633,35 +3610,139 @@ static void enet_default_init(void) /* configure ENET_MAC_FCTL, ENET_MAC_FCTH register */ reg_value = ENET_MAC_FCTL; reg_value &= MAC_FCTL_MASK; - reg_value |= MAC_FCTL_PTM(0) |ENET_ZERO_QUANTA_PAUSE_DISABLE \ - |ENET_PAUSETIME_MINUS4 |ENET_UNIQUE_PAUSEDETECT \ - |ENET_RX_FLOWCONTROL_DISABLE |ENET_TX_FLOWCONTROL_DISABLE; + reg_value |= MAC_FCTL_PTM(0) | ENET_ZERO_QUANTA_PAUSE_DISABLE \ + | ENET_PAUSETIME_MINUS4 | ENET_UNIQUE_PAUSEDETECT \ + | ENET_RX_FLOWCONTROL_DISABLE | ENET_TX_FLOWCONTROL_DISABLE; ENET_MAC_FCTL = reg_value; /* configure ENET_MAC_VLT register */ - ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT |MAC_VLT_VLTI(0); + ENET_MAC_VLT = ENET_VLANTAGCOMPARISON_16BIT | MAC_VLT_VLTI(0); + + /* disable MAC interrupt */ + ENET_MAC_INTMSK |= ENET_MAC_INTMSK_TMSTIM | ENET_MAC_INTMSK_WUMIM; + + /* MSC */ + /* disable MSC Rx interrupt */ + ENET_MSC_RINTMSK |= ENET_MSC_RINTMSK_RFAEIM | ENET_MSC_RINTMSK_RFCEIM \ + | ENET_MSC_RINTMSK_RGUFIM; + + /* disable MSC Tx interrupt */ + ENET_MSC_TINTMSK |= ENET_MSC_TINTMSK_TGFIM | ENET_MSC_TINTMSK_TGFMSCIM \ + | ENET_MSC_TINTMSK_TGFSCIM; /* DMA */ /* configure ENET_DMA_CTL register */ reg_value = ENET_DMA_CTL; reg_value &= DMA_CTL_MASK; - reg_value |= ENET_TCPIP_CKSUMERROR_DROP |ENET_RX_MODE_STOREFORWARD \ - |ENET_FLUSH_RXFRAME_ENABLE |ENET_TX_MODE_STOREFORWARD \ - |ENET_TX_THRESHOLD_64BYTES |ENET_RX_THRESHOLD_64BYTES \ - |ENET_SECONDFRAME_OPT_DISABLE; + reg_value |= ENET_TCPIP_CKSUMERROR_DROP | ENET_RX_MODE_STOREFORWARD \ + | ENET_FLUSH_RXFRAME_ENABLE | ENET_TX_MODE_STOREFORWARD \ + | ENET_TX_THRESHOLD_64BYTES | ENET_RX_THRESHOLD_64BYTES \ + | ENET_SECONDFRAME_OPT_DISABLE; ENET_DMA_CTL = reg_value; /* configure ENET_DMA_BCTL register */ reg_value = ENET_DMA_BCTL; reg_value &= DMA_BCTL_MASK; - reg_value = ENET_ADDRESS_ALIGN_ENABLE |ENET_ARBITRATION_RXTX_2_1 \ - |ENET_RXDP_32BEAT |ENET_PGBL_32BEAT |ENET_RXTX_DIFFERENT_PGBL \ - |ENET_FIXED_BURST_ENABLE |ENET_MIXED_BURST_DISABLE \ - |ENET_NORMAL_DESCRIPTOR; - ENET_DMA_BCTL = reg_value; + reg_value = ENET_ADDRESS_ALIGN_ENABLE | ENET_ARBITRATION_RXTX_2_1 \ + | ENET_RXDP_32BEAT | ENET_PGBL_32BEAT | ENET_RXTX_DIFFERENT_PGBL \ + | ENET_FIXED_BURST_ENABLE | ENET_MIXED_BURST_DISABLE \ + | ENET_NORMAL_DESCRIPTOR; + ENET_DMA_BCTL = reg_value; +} + +/*! + \brief check whether the PHY is linked up + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +static ErrStatus enet_phy_link_check(void) +{ + uint32_t timeout = 0U; + uint16_t phy_value; + ErrStatus phy_state, enet_state = SUCCESS; + /* wait for PHY_LINKED_STATUS bit be set */ + do { + phy_state = enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_LINKED_STATUS; + timeout++; + } while(((uint16_t)RESET == phy_value) && (timeout < PHY_READ_TO)); + /* Set enet_state to ERROR due to timeout or phy operation fail */ + if((PHY_READ_TO == timeout) || (SUCCESS != phy_state)) { + enet_state = ERROR; + } else { + /* This code is written to avoid MISRA 15.7 (no 'else' at end of 'is ... else if' chain) */ + } + return enet_state; +} + +/*! + \brief perform auto-negotiation operation + \param[in] none + \param[out] media_mode: auto-negotiation result + \retval ErrStatus: ERROR or SUCCESS +*/ +static ErrStatus enet_phy_negoiation(uint32_t *mediamode_result) +{ + ErrStatus phy_state, enet_state = SUCCESS; + uint16_t phy_value; + uint32_t timeout = 0U; + + /* check whether the PHY is linked up */ + enet_state = enet_phy_link_check(); + if(SUCCESS == enet_state) { + /* enable auto-negotiation */ + phy_value = PHY_AUTONEGOTIATION; + phy_state = enet_phy_write_read(ENET_PHY_WRITE, PHY_ADDRESS, PHY_REG_BCR, &phy_value); + if(SUCCESS != phy_state) { + /* return ERROR due to write timeout */ + enet_state = ERROR; + } else { + /* This code is written to avoid MISRA 15.7 (no 'else' at end of 'is ... else if' chain) */ + } + /* wait for the PHY_AUTONEGO_COMPLETE bit be set */ + do { + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_REG_BSR, &phy_value); + phy_value &= PHY_AUTONEGO_COMPLETE; + timeout++; + } while((RESET == phy_value) && (timeout < (uint32_t)PHY_READ_TO)); + /* Set enet_state to ERROR due to timeout or phy operation fail */ + if((PHY_READ_TO == timeout) || (SUCCESS != phy_state)) { + enet_state = ERROR; + } else { + /* This code is written to avoid MISRA 15.7 (no 'else' at end of 'is ... else if' chain) */ + } + + /* read the result of the auto-negotiation */ + enet_phy_write_read(ENET_PHY_READ, PHY_ADDRESS, PHY_SR, &phy_value); + if(SUCCESS != phy_state) { + /* return ERROR due to write timeout */ + enet_state = ERROR; + } else { + /* This code is written to avoid MISRA 15.7 (no 'else' at end of 'is ... else if' chain) */ + } + + /* configure the duplex mode of MAC following the auto-negotiation result */ + if((uint16_t)RESET != (phy_value & PHY_DUPLEX_STATUS)) { + *mediamode_result = ENET_MODE_FULLDUPLEX; + } else { + *mediamode_result = ENET_MODE_HALFDUPLEX; + } + + /* configure the communication speed of MAC following the auto-negotiation result */ + if((uint16_t)RESET != (phy_value & PHY_SPEED_STATUS)) { + *mediamode_result |= ENET_SPEEDMODE_10M; + } else { + *mediamode_result |= ENET_SPEEDMODE_100M; + } + + } else { + enet_state = ERROR; + } + return enet_state; } -#ifndef USE_DELAY +#if (0 == USE_DELAY) /*! \brief insert a delay time \param[in] ncount: specifies the delay time length @@ -3672,7 +3753,7 @@ static void enet_delay(uint32_t ncount) { __IO uint32_t delay_time = 0U; - for(delay_time = ncount; delay_time != 0U; delay_time--){ + for(delay_time = ncount; delay_time != 0U; delay_time--) { } } #endif /* USE_DELAY */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c index 0915ca6f..edde144b 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_exmc.c @@ -2,14 +2,11 @@ \file gd32f30x_exmc.c \brief EXMC driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -586,17 +583,19 @@ void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt) FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag) { uint32_t status = 0x00000000U; + FlagStatus retval = RESET; /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(exmc_bank); if ((status & flag) != (uint32_t)flag ){ /* flag is reset */ - return RESET; + retval = RESET; }else{ /* flag is set */ - return SET; + retval = SET; } + return retval; } /*! @@ -639,6 +638,7 @@ void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag) FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt) { uint32_t status = 0x00000000U,interrupt_enable = 0x00000000U,interrupt_state = 0x00000000U; + FlagStatus retval = RESET; /* NAND bank1,bank2 or PC card bank3 */ status = EXMC_NPINTEN(exmc_bank); @@ -648,11 +648,12 @@ FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt) if ((interrupt_enable) && (interrupt_state)){ /* interrupt flag is set */ - return SET; + retval = SET; }else{ /* interrupt flag is reset */ - return RESET; + retval = RESET; } + return retval; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c index 7f728e9f..2fc60656 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_exti.c @@ -2,14 +2,11 @@ \file gd32f30x_exti.c \brief EXTI driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -201,11 +198,15 @@ void exti_software_interrupt_disable(exti_line_enum linex) */ FlagStatus exti_flag_get(exti_line_enum linex) { + FlagStatus status; + if(RESET != (EXTI_PD & (uint32_t)linex)){ - return SET; - }else{ - return RESET; - } + status = SET; + } else { + status = RESET; + } + + return status; } /*! @@ -231,11 +232,15 @@ void exti_flag_clear(exti_line_enum linex) */ FlagStatus exti_interrupt_flag_get(exti_line_enum linex) { + FlagStatus status; + if(RESET != (EXTI_PD & (uint32_t)linex)) { - return SET; + status = SET; } else { - return RESET; + status = RESET; } + + return status; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c index 706463b2..cc5f188c 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_fmc.c @@ -2,14 +2,11 @@ \file gd32f30x_fmc.c \brief FMC driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -176,6 +173,8 @@ fmc_state_enum fmc_page_erase(uint32_t page_address) FMC_CTL0 |= FMC_CTL0_PER; FMC_ADDR0 = page_address; FMC_CTL0 |= FMC_CTL0_START; + __NOP(); + __NOP(); /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PER bit */ @@ -192,6 +191,8 @@ fmc_state_enum fmc_page_erase(uint32_t page_address) FMC_ADDR0 = page_address; } FMC_CTL1 |= FMC_CTL1_START; + __NOP(); + __NOP(); /* wait for the FMC ready */ fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PER bit */ @@ -205,6 +206,8 @@ fmc_state_enum fmc_page_erase(uint32_t page_address) FMC_CTL0 |= FMC_CTL0_PER; FMC_ADDR0 = page_address; FMC_CTL0 |= FMC_CTL0_START; + __NOP(); + __NOP(); /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); /* reset the PER bit */ @@ -224,6 +227,8 @@ fmc_state_enum fmc_page_erase(uint32_t page_address) fmc_state_enum fmc_mass_erase(void) { fmc_state_enum fmc_state; + fmc_state_enum fmc_state_bank1; + if(FMC_BANK0_SIZE < FMC_SIZE){ /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); @@ -233,22 +238,23 @@ fmc_state_enum fmc_mass_erase(void) FMC_CTL0 |= FMC_CTL0_START; /* wait for the FMC ready */ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY != fmc_state){ - return fmc_state; - } /* reset the MER bit */ FMC_CTL0 &= ~FMC_CTL0_MER; } - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); - if(FMC_READY == fmc_state){ + fmc_state_bank1 = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + if(FMC_READY == fmc_state_bank1){ /* start whole chip erase */ FMC_CTL1 |= FMC_CTL1_MER; FMC_CTL1 |= FMC_CTL1_START; /* wait for the FMC ready */ - fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); + fmc_state_bank1 = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT); /* reset the MER bit */ FMC_CTL1 &= ~FMC_CTL1_MER; } + /* return bank1 state if bank0 is ready, otherwise return bank0 state */ + if(FMC_READY == fmc_state){ + fmc_state = fmc_state_bank1; + } }else{ fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT); if(FMC_READY == fmc_state){ @@ -778,6 +784,7 @@ FlagStatus ob_spc_get(void) }else{ spc_state = RESET; } + return spc_state; } @@ -829,11 +836,15 @@ void fmc_interrupt_disable(uint32_t interrupt) */ FlagStatus fmc_flag_get(uint32_t flag) { + FlagStatus flag_status = RESET; + if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){ - return SET; + flag_status = SET; }else{ - return RESET; + flag_status = RESET; } + + return flag_status; } /*! @@ -871,24 +882,27 @@ FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag) { FlagStatus ret1 = RESET; FlagStatus ret2 = RESET; + FlagStatus result = RESET; if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){ - /* get the staus of interrupt flag */ + /* get the status of interrupt flag */ ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ + /* get the status of interrupt enable bit */ ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag))); }else{ - /* get the staus of interrupt flag */ + /* get the status of interrupt flag */ ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag))); - /* get the staus of interrupt enale bit */ + /* get the status of interrupt enable bit */ ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag))); } if(ret1 && ret2){ - return SET; + result = SET; }else{ - return RESET; + result = RESET; } + + return result; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c index f6f5c824..5ebce22f 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_fwdgt.c @@ -2,14 +2,11 @@ \file gd32f30x_fwdgt.c \brief FWDGT driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,11 +34,6 @@ OF SUCH DAMAGE. #include "gd32f30x_fwdgt.h" -/* write value to FWDGT_CTL_CMD bit field */ -#define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - /*! \brief enable write access to FWDGT_PSC and FWDGT_RLD \param[in] none @@ -92,24 +84,25 @@ void fwdgt_enable(void) ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) { uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; + uint32_t flag_status; + ErrStatus status = SUCCESS; /* enable write access to FWDGT_PSC */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + /* configure FWDGT_PSC */ + FWDGT_PSC = (uint32_t)prescaler_value; + /* wait until the PUD flag to be reset */ do { flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + } while((--timeout > 0U) && (0U != flag_status)); - if((uint32_t)RESET != flag_status) { - return ERROR; + if(0U != flag_status) { + status = ERROR; } - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_value; - - return SUCCESS; + return status; } /*! @@ -121,23 +114,25 @@ ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) ErrStatus fwdgt_reload_value_config(uint16_t reload_value) { uint32_t timeout = FWDGT_RLD_TIMEOUT; - uint32_t flag_status = RESET; + uint32_t flag_status; + ErrStatus status = SUCCESS; /* enable write access to FWDGT_RLD */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + /* configure FWDGT_RLD */ + FWDGT_RLD = RLD_RLD(reload_value); + /* wait until the RUD flag to be reset */ do { flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + } while((--timeout > 0U) && (0U != flag_status)); - if((uint32_t)RESET != flag_status) { - return ERROR; + if(0U != flag_status) { + status = ERROR; } - FWDGT_RLD = RLD_RLD(reload_value); - - return SUCCESS; + return status; } /*! @@ -169,39 +164,47 @@ void fwdgt_counter_reload(void) ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) { uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; + uint32_t flag_status; + ErrStatus status = SUCCESS; + + /* start the free watchdog timer counter */ + FWDGT_CTL = FWDGT_KEY_ENABLE; /* enable write access to FWDGT_PSC,and FWDGT_RLD */ FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - /* wait until the PUD flag to be reset */ + /* configure FWDGT_PSC */ + FWDGT_PSC = (uint32_t)prescaler_div; + do { flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + } while((--timeout > 0U) && (0U != flag_status)); - if((uint32_t)RESET != flag_status) { - return ERROR; + if(0U != flag_status) { + status = ERROR; } - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; + if(SUCCESS == status) { + /* configure FWDGT_RLD */ + FWDGT_RLD = RLD_RLD(reload_value); - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do { - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + /* wait until the RUD flag to be reset */ + timeout = FWDGT_RLD_TIMEOUT; + do { + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + } while((--timeout > 0U) && (0U != flag_status)); - if((uint32_t)RESET != flag_status) { - return ERROR; + if(0U != flag_status) { + status = ERROR; + } } - FWDGT_RLD = RLD_RLD(reload_value); - - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; + if(SUCCESS == status) { + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + } - return SUCCESS; + return status; } /*! @@ -215,9 +218,9 @@ ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) */ FlagStatus fwdgt_flag_get(uint16_t flag) { - if(FWDGT_STAT & flag) { - return SET; + FlagStatus flag_status = RESET; + if(RESET != (FWDGT_STAT & flag)) { + flag_status = SET; } - - return RESET; + return flag_status; } diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c index c0972f13..486b180f 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_gpio.c @@ -2,14 +2,11 @@ \file gd32f30x_gpio.c \brief GPIO driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -277,11 +274,15 @@ void gpio_port_write(uint32_t gpio_periph,uint16_t data) */ FlagStatus gpio_input_bit_get(uint32_t gpio_periph,uint32_t pin) { + FlagStatus reval; + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){ - return SET; + reval = SET; }else{ - return RESET; + reval = RESET; } + + return reval; } /*! @@ -306,11 +307,15 @@ uint16_t gpio_input_port_get(uint32_t gpio_periph) */ FlagStatus gpio_output_bit_get(uint32_t gpio_periph,uint32_t pin) { + FlagStatus reval; + if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){ - return SET; + reval = SET; }else{ - return RESET; + reval = RESET; } + + return reval; } /*! @@ -349,16 +354,16 @@ uint16_t gpio_output_port_get(uint32_t gpio_periph) \arg GPIO_PD01_REMAP: PD01 remapping \arg GPIO_TIMER4CH3_IREMAP: TIMER4 channel3 internal remapping \arg GPIO_ADC0_ETRGINS_REMAP: ADC0 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) - \arg GPIO_ADC0_ETRGREG_REMAP: ADC0 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ADC0_ETRGROU_REMAP: ADC0 external trigger routine conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) \arg GPIO_ADC1_ETRGINS_REMAP: ADC1 external trigger inserted conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) - \arg GPIO_ADC1_ETRGREG_REMAP: ADC1 external trigger regular conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) + \arg GPIO_ADC1_ETRGROU_REMAP: ADC1 external trigger routine conversion remapping(only for GD32F30X_HD devices and GD32F30X_XD devices) \arg GPIO_ENET_REMAP: ENET remapping(only for GD32F30X_CL devices) \arg GPIO_CAN1_REMAP: CAN1 remapping(only for GD32F30X_CL devices) \arg GPIO_SWJ_NONJTRST_REMAP: full SWJ(JTAG-DP + SW-DP),but without NJTRST \arg GPIO_SWJ_SWDPENABLE_REMAP: JTAG-DP disabled and SW-DP enabled \arg GPIO_SWJ_DISABLE_REMAP: JTAG-DP disabled and SW-DP disabled \arg GPIO_SPI2_REMAP: SPI2 remapping - \arg GPIO_TIMER1ITR0_REMAP: TIMER1 internal trigger 0 remapping(only for GD32F30X_CL devices) + \arg GPIO_TIMER1ITI1_REMAP: TIMER1 internal trigger 1 remapping(only for GD32F30X_CL devices) \arg GPIO_PTP_PPS_REMAP: ethernet PTP PPS remapping(only for GD32F30X_CL devices) \arg GPIO_TIMER8_REMAP: TIMER8 remapping \arg GPIO_TIMER9_REMAP: TIMER9 remapping @@ -575,9 +580,13 @@ void gpio_compensation_config(uint32_t compensation) */ FlagStatus gpio_compensation_flag_get(void) { + FlagStatus reval; + if(((uint32_t)RESET) != (AFIO_CPSCTL & AFIO_CPSCTL_CPS_RDY)){ - return SET; + reval = SET; }else{ - return RESET; + reval = RESET; } + + return reval; } diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c index c6d3bc67..4b854c96 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_i2c.c @@ -2,15 +2,11 @@ \file gd32f30x_i2c.c \brief I2C driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2019-04-16, V2.0.1, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2026, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -473,7 +469,7 @@ void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) /*! \brief configure I2C PEC calculation \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: + \param[in] pecstate: only one parameter can be selected which is shown as below: \arg I2C_PEC_ENABLE: PEC calculation on \arg I2C_PEC_DISABLE: PEC calculation off @@ -547,7 +543,7 @@ void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara) /*! \brief configure I2C ARP protocol in SMBus \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: + \param[in] arpstate: only one parameter can be selected which is shown as below: \arg I2C_ARP_ENABLE: enable ARP \arg I2C_ARP_DISABLE: disable ARP @@ -596,11 +592,14 @@ void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate) */ FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) { + FlagStatus ret; + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))){ - return SET; + ret = SET; }else{ - return RESET; + ret = RESET; } + return ret; } /*! @@ -687,6 +686,7 @@ void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) { uint32_t intenable = 0U, flagstatus = 0U, bufie; + FlagStatus ret; /* check BUFIE */ bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; @@ -704,16 +704,17 @@ FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum i } } if((0U != flagstatus) && (0U != intenable)){ - return SET; + ret = SET; }else{ - return RESET; + ret = RESET; } + return ret; } /*! \brief clear I2C interrupt flag status \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] intflag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum only one parameter can be selected which is shown as below: \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c index a31eeaac..1babf1b3 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_misc.c @@ -2,14 +2,11 @@ \file gd32f30x_misc.c \brief MISC driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2025, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -62,38 +59,34 @@ void nvic_priority_group_set(uint32_t nvic_prigroup) \param[out] none \retval none */ -void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, +void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority) { - uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U; - /* use the priority group value to get the temp_pre and the temp_sub */ - if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){ - temp_pre=0U; - temp_sub=0x4U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){ - temp_pre=1U; - temp_sub=0x3U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){ - temp_pre=2U; - temp_sub=0x2U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){ - temp_pre=3U; - temp_sub=0x1U; - }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){ - temp_pre=4U; - temp_sub=0x0U; - }else{ + uint32_t nvic_prigroup, nvic_priority; + + /* check current priority group */ + switch(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) { + case NVIC_PRIGROUP_PRE0_SUB4: + case NVIC_PRIGROUP_PRE1_SUB3: + case NVIC_PRIGROUP_PRE2_SUB2: + case NVIC_PRIGROUP_PRE3_SUB1: + case NVIC_PRIGROUP_PRE4_SUB0: + break; + default: nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2); - temp_pre=2U; - temp_sub=0x2U; + break; } - /* get the temp_priority to fill the NVIC->IP register */ - temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre); - temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub)); - temp_priority = temp_priority << 0x04U; - NVIC->IP[nvic_irq] = (uint8_t)temp_priority; + + /* get the priority group value */ + nvic_prigroup = NVIC_GetPriorityGrouping(); + + /* encoding the pre-emption, subpriority priority */ + nvic_priority = NVIC_EncodePriority(nvic_prigroup, (uint32_t)nvic_irq_pre_priority, (uint32_t)nvic_irq_sub_priority); + /* set priority */ + NVIC_SetPriority(nvic_irq, nvic_priority); + /* enable the selected IRQ */ - NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU); + NVIC_EnableIRQ(nvic_irq); } /*! @@ -102,34 +95,34 @@ void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority, \param[out] none \retval none */ -void nvic_irq_disable(uint8_t nvic_irq) +void nvic_irq_disable(IRQn_Type nvic_irq) { /* disable the selected IRQ.*/ - NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F); + NVIC_DisableIRQ(nvic_irq); } /*! \brief set the NVIC vector table base address - \param[in] nvic_vict_tab: the RAM or FLASH base address + \param[in] nvic_vect_tab: the RAM or FLASH base address \arg NVIC_VECTTAB_RAM: RAM base address - \are NVIC_VECTTAB_FLASH: Flash base address + \arg NVIC_VECTTAB_FLASH: Flash base address \param[in] offset: Vector Table offset \param[out] none \retval none */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +void nvic_vector_table_set(uint32_t nvic_vect_tab, uint32_t offset) { - SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); + SCB->VTOR = nvic_vect_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); __DSB(); } /*! \brief set the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if choose this para, the system always enter low power mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + \arg SCB_LPM_DEEPSLEEP: if choose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if choose this para, the lowpower mode can be woken up by all the enable and disable interrupts \param[out] none \retval none @@ -142,11 +135,11 @@ void system_lowpower_set(uint8_t lowpower_mode) /*! \brief reset the state of the low power mode \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + \arg SCB_LPM_SLEEP_EXIT_ISR: if choose this para, the system will exit low power mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be - woke up by the enable interrupts + \arg SCB_LPM_DEEPSLEEP: if choose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if choose this para, the lowpower mode only can be + woken up by the enable interrupts \param[out] none \retval none */ @@ -174,3 +167,126 @@ void systick_clksource_set(uint32_t systick_clksource) SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; } } + +#if (__MPU_PRESENT == 1) + +/*! + \brief enable arm mpu + \param[in] mpu_control: MPU control value + \arg MPU_MODE_HFNMI_PRIVDEF_NONE: HFNMIENA and PRIVDEFENA are 0 + \arg MPU_MODE_HARDFAULT_NMI: use the MPU for memory accesses by HardFault and NMI handlers only + \arg MPU_MODE_PRIV_DEFAULT: enables the default memory map as a background region for privileged access only + \arg MPU_MODE_HFNMI_PRIVDEF: HFNMIENA and PRIVDEFENA are 1 + \param[out] none + \retval none +*/ +void armv7_mpu_enable(uint32_t mpu_control) +{ + __DMB(); + MPU->CTRL = mpu_control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/*! + \brief disable arm mpu + \param[in] none + \param[out] none + \retval none +*/ +void armv7_mpu_disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/*! + \brief mpu set region + \param[in] rbar: rbar register value + \param[in] rasr: rasr register value + \param[out] none + \retval none +*/ +void armv7_mpu_set_region(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/*! + \brief initialize mpu_region_init_struct with the default values + \param[in] mpu_init_struct: pointer to a mpu_region_init_struct structure + \param[out] none + \retval none +*/ +void mpu_region_struct_para_init(mpu_region_init_struct *mpu_init_struct) +{ + mpu_init_struct->region_number = MPU_REGION_NUMBER0; + mpu_init_struct->region_base_address = 0x00000000U; + mpu_init_struct->instruction_exec = MPU_INSTRUCTION_EXEC_PERMIT; + mpu_init_struct->access_permission = MPU_AP_NO_ACCESS; + mpu_init_struct->tex_type = MPU_TEX_TYPE0; + mpu_init_struct->access_shareable = MPU_ACCESS_SHAREABLE; + mpu_init_struct->access_cacheable = MPU_ACCESS_CACHEABLE; + mpu_init_struct->access_bufferable = MPU_ACCESS_BUFFERABLE; + mpu_init_struct->subregion_disable = MPU_SUBREGION_ENABLE; + mpu_init_struct->region_size = MPU_REGION_SIZE_32B; +} + +/*! + \brief configure the MPU region + \param[in] mpu_init_struct: MPU initialization structure + region_number: region number + MPU_REGION_NUMBERn (n=0,..,7) + region_base_address: region base address + region_size: MPU_REGION_SIZE_32B, MPU_REGION_SIZE_64B, MPU_REGION_SIZE_128B, MPU_REGION_SIZE_256B, MPU_REGION_SIZE_512B, + MPU_REGION_SIZE_1KB, MPU_REGION_SIZE_2KB, MPU_REGION_SIZE_4KB, MPU_REGION_SIZE_8KB, MPU_REGION_SIZE_16KB, + MPU_REGION_SIZE_32KB, MPU_REGION_SIZE_64KB, MPU_REGION_SIZE_128KB, MPU_REGION_SIZE_256KB, MPU_REGION_SIZE_512KB, + MPU_REGION_SIZE_1MB, MPU_REGION_SIZE_2MB, MPU_REGION_SIZE_4MB, MPU_REGION_SIZE_8MB, MPU_REGION_SIZE_16MB, + MPU_REGION_SIZE_32MB, MPU_REGION_SIZE_64MB, MPU_REGION_SIZE_128MB, MPU_REGION_SIZE_256MB, MPU_REGION_SIZE_512MB, + MPU_REGION_SIZE_1GB, MPU_REGION_SIZE_2GB, MPU_REGION_SIZE_4GB + subregion_disable: MPU_SUBREGION_ENABLE, MPU_SUBREGION_DISABLE or 0x00~0xFF + tex_type: MPU_TEX_TYPE0, MPU_TEX_TYPE1, MPU_TEX_TYPE2 or 0x00~0x07 + access_permission: MPU_AP_NO_ACCESS, MPU_AP_PRIV_RW, MPU_AP_PRIV_RW_UNPRIV_RO, MPU_AP_FULL_ACCESS, MPU_AP_PRIV_RO, + MPU_AP_PRIV_UNPRIV_RO + access_shareable: MPU_ACCESS_SHAREABLE, MPU_ACCESS_NON_SHAREABLE + access_cacheable: MPU_ACCESS_CACHEABLE, MPU_ACCESS_NON_CACHEABLE + access_bufferable: MPU_ACCESS_BUFFERABLE, MPU_ACCESS_NON_BUFFERABLE + instruction_exec: MPU_INSTRUCTION_EXEC_PERMIT, MPU_INSTRUCTION_EXEC_NOT_PERMIT + \param[out] none + \retval none +*/ +void mpu_region_config(mpu_region_init_struct *mpu_init_struct) +{ + MPU->RNR = mpu_init_struct->region_number; + MPU->RBAR = mpu_init_struct->region_base_address; + MPU->RASR = ((uint32_t)mpu_init_struct->instruction_exec << MPU_RASR_XN_Pos) | + ((uint32_t)mpu_init_struct->access_permission << MPU_RASR_AP_Pos) | + ((uint32_t)mpu_init_struct->tex_type << MPU_RASR_TEX_Pos)| + ((uint32_t)mpu_init_struct->access_shareable << MPU_RASR_S_Pos) | + ((uint32_t)mpu_init_struct->access_cacheable << MPU_RASR_C_Pos) | + ((uint32_t)mpu_init_struct->access_bufferable << MPU_RASR_B_Pos) | + ((uint32_t)mpu_init_struct->subregion_disable << MPU_RASR_SRD_Pos)| + ((uint32_t)mpu_init_struct->region_size << MPU_RASR_SIZE_Pos); +} + +/*! + \brief enable the MPU region + \param[in] none + \param[out] none + \retval none +*/ +void mpu_region_enable(void) +{ + MPU->RASR |= MPU_RASR_ENABLE_Msk; +} + +#endif /* __MPU_PRESENT */ diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c index e88eff1e..11a255e1 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_pmu.c @@ -2,14 +2,11 @@ \file gd32f30x_pmu.c \brief PMU driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2025, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -105,6 +102,17 @@ void pmu_lvd_disable(void) PMU_CTL &= ~PMU_CTL_LVDEN; } +/*! + \brief enable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_enable(void) +{ + PMU_CTL |= PMU_CTL_LVDEN; +} + /*! \brief switch high-driver mode this bit set by software only when IRC16M or HXTAL used as system clock @@ -213,6 +221,8 @@ void pmu_to_sleepmode(uint8_t sleepmodecmd) if(WFI_CMD == sleepmodecmd) { __WFI(); } else { + __SEV(); + __WFE(); __WFE(); } } @@ -368,11 +378,13 @@ void pmu_wakeup_pin_disable(void) */ FlagStatus pmu_flag_get(uint32_t flag) { + FlagStatus reval = RESET; if(PMU_CS & flag) { - return SET; + reval = SET; } else { - return RESET; + reval = RESET; } + return reval; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c index 5f5418f9..cb58dafb 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_rcu.c @@ -2,14 +2,11 @@ \file gd32f30x_rcu.c \brief RCU driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2025, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -1225,12 +1222,16 @@ uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) */ FlagStatus rcu_flag_get(rcu_flag_enum flag) { + FlagStatus r_rcu_flag = RESET; + /* get the rcu flag */ if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))){ - return SET; + r_rcu_flag = SET; }else{ - return RESET; + r_rcu_flag = RESET; } + + return r_rcu_flag; } /*! @@ -1262,12 +1263,16 @@ void rcu_all_reset_flag_clear(void) */ FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) { + FlagStatus r_rcu_int_flag = RESET; + /* get the rcu interrupt flag */ if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))){ - return SET; + r_rcu_int_flag = SET; }else{ - return RESET; + r_rcu_int_flag = RESET; } + + return r_rcu_int_flag; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c index 2d20fc0d..152d7888 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_rtc.c @@ -2,14 +2,11 @@ \file gd32f30x_rtc.c \brief RTC driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2025, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -205,11 +202,13 @@ uint32_t rtc_divider_get(void) */ FlagStatus rtc_flag_get(uint32_t flag) { + FlagStatus status = RESET; if(RESET != (RTC_CTL & flag)){ - return SET; + status = SET; }else{ - return RESET; + status = RESET; } + return status; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c index f2ef95a8..c7699f9a 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_sdio.c @@ -2,14 +2,11 @@ \file gd32f30x_sdio.c \brief SDIO driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2025, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -195,6 +192,9 @@ void sdio_clock_disable(void) void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type) { uint32_t cmd_config = 0U; + + /* disable the CSM */ + SDIO_CMDCTL &= ~SDIO_CMDCTL_CSMEN; /* reset the command index, command argument and response type */ SDIO_CMDAGMT &= ~SDIO_CMDAGMT_CMDAGMT; SDIO_CMDAGMT = cmd_argument; @@ -469,10 +469,13 @@ void sdio_dma_disable(void) */ FlagStatus sdio_flag_get(uint32_t flag) { + FlagStatus status; if(RESET != (SDIO_STAT & flag)){ - return SET; + status = SET; + }else{ + status = RESET; } - return RESET; + return status; } /*! @@ -605,10 +608,13 @@ void sdio_interrupt_disable(uint32_t int_flag) */ FlagStatus sdio_interrupt_flag_get(uint32_t int_flag) { + FlagStatus status; if(RESET != (SDIO_STAT & int_flag)){ - return SET; + status = SET; + }else{ + status = RESET; } - return RESET; + return status; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c index 4df21d04..e6fb5fcd 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_spi.c @@ -2,14 +2,11 @@ \file gd32f30x_spi.c \brief SPI driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2025, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -84,7 +81,7 @@ void spi_i2s_deinit(uint32_t spi_periph) /*! \brief initialize the parameters of SPI struct with default values \param[in] none - \param[out] spi_parameter_struct: the initialized struct spi_parameter_struct pointer + \param[out] spi_struct: the initialized struct spi_parameter_struct pointer \retval none */ void spi_struct_para_init(spi_parameter_struct *spi_struct) @@ -176,7 +173,7 @@ void spi_disable(uint32_t spi_periph) \arg I2S_MODE_MASTERRX: I2S master receive mode \param[in] i2s_standard: I2S standard only one parameter can be selected which is shown as below: - \arg I2S_STD_PHILLIPS: I2S phillips standard + \arg I2S_STD_PHILIPS: I2S philips standard \arg I2S_STD_MSB: I2S MSB standard \arg I2S_STD_LSB: I2S LSB standard \arg I2S_STD_PCMSHORT: I2S PCM short standard @@ -486,6 +483,7 @@ uint16_t spi_i2s_data_receive(uint32_t spi_periph) only one parameter can be selected which is shown as below: \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \param[out] none \retval none */ void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) @@ -582,11 +580,14 @@ void spi_crc_next(uint32_t spi_periph) */ uint16_t spi_crc_get(uint32_t spi_periph,uint8_t crc) { + uint16_t val; + if(SPI_CRC_TX == crc){ - return ((uint16_t)(SPI_TCRC(spi_periph))); + val = ((uint16_t)(SPI_TCRC(spi_periph))); }else{ - return ((uint16_t)(SPI_RCRC(spi_periph))); + val = ((uint16_t)(SPI_RCRC(spi_periph))); } + return val; } /*! @@ -793,6 +794,7 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) { uint32_t reg1 = SPI_STAT(spi_periph); uint32_t reg2 = SPI_CTL1(spi_periph); + FlagStatus ret; switch(interrupt){ /* SPI/I2S transmit buffer empty interrupt */ @@ -835,10 +837,11 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) } /*get SPI/I2S interrupt flag status */ if(reg1 && reg2){ - return SET; + ret = SET; }else{ - return RESET; + ret = RESET; } + return ret; } /*! @@ -865,9 +868,12 @@ FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) */ FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) { + FlagStatus ret; + if(SPI_STAT(spi_periph) & flag){ - return SET; + ret = SET; }else{ - return RESET; + ret = RESET; } + return ret; } diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c index 87ac0bf1..a970de9d 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_timer.c @@ -2,14 +2,11 @@ \file gd32f30x_timer.c \brief TIMER driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2025, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -474,13 +471,16 @@ void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) */ FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) { + FlagStatus timer_interrupt_flag = RESET; uint32_t val; val = (TIMER_DMAINTEN(timer_periph) & interrupt); if((RESET != (TIMER_INTF(timer_periph) & interrupt) ) && (RESET != val)){ - return SET; + timer_interrupt_flag = SET; }else{ - return RESET; + timer_interrupt_flag = RESET; } + + return timer_interrupt_flag; } /*! @@ -526,11 +526,14 @@ void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) */ FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) { + FlagStatus timer_flag = RESET; if(RESET != (TIMER_INTF(timer_periph) & flag)){ - return SET; + timer_flag = SET; }else{ - return RESET; + timer_flag = RESET; } + + return timer_flag; } /*! @@ -562,7 +565,7 @@ void timer_flag_clear(uint32_t timer_periph, uint32_t flag) \brief enable the TIMER DMA \param[in] timer_periph: please refer to the following parameters \param[in] dma: specify which DMA to enable - only one parameter can be selected which is shown as below: + one or more parameters can be selected which is shown as below: \arg TIMER_DMA_UPD: update DMA enable,TIMERx(x=0..7) \arg TIMER_DMA_CH0D: channel 0 DMA enable,TIMERx(x=0..4,7) \arg TIMER_DMA_CH1D: channel 1 DMA enable,TIMERx(x=0..4,7) @@ -1743,13 +1746,13 @@ void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t o \param[in] timer_periph: TIMERx(x=0..4,7,8,11) \param[in] slavemode: only one parameter can be selected which is shown as below: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable - \arg TIMER_ENCODER_MODE0: encoder mode 0 - \arg TIMER_ENCODER_MODE1: encoder mode 1 - \arg TIMER_ENCODER_MODE2: encoder mode 2 - \arg TIMER_SLAVE_MODE_RESTART: restart mode - \arg TIMER_SLAVE_MODE_PAUSE: pause mode - \arg TIMER_SLAVE_MODE_EVENT: event mode + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11)) + \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7)) + \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7)) + \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11)) + \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11)) \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0. \param[out] none \retval none diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c index b218900a..938ef128 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_usart.c @@ -2,14 +2,11 @@ \file gd32f30x_usart.c \brief USART driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2025, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -744,11 +741,13 @@ void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmacmd) */ FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) { + FlagStatus retval = RESET; if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))){ - return SET; + retval = SET; }else{ - return RESET; + retval = RESET; } + return retval; } /*! @@ -839,6 +838,7 @@ void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interru */ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) { + FlagStatus retval = RESET; uint32_t intenable = 0U, flagstatus = 0U; /* get the interrupt enable bit status */ intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); @@ -846,10 +846,11 @@ FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_ flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); if((0U != flagstatus) && (0U != intenable)){ - return SET; + retval = SET; }else{ - return RESET; + retval = RESET; } + return retval; } /*! diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c index 5b1e9884..7fc5f0e2 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Source/gd32f30x_wwdgt.c @@ -2,14 +2,11 @@ \file gd32f30x_wwdgt.c \brief WWDGT driver - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ /* - Copyright (c) 2020, GigaDevice Semiconductor Inc. + Copyright (c) 2025, GigaDevice Semiconductor Inc. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -98,11 +95,12 @@ void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) */ FlagStatus wwdgt_flag_get(void) { + FlagStatus ret = RESET; + if(WWDGT_STAT & WWDGT_STAT_EWIF) { - return SET; + ret = SET; } - - return RESET; + return ret; } /*! From 1e762788b2d4bfe5e7a2c2397c481953b8dfa614 Mon Sep 17 00:00:00 2001 From: Arjan Date: Tue, 23 Jun 2026 15:34:25 +0200 Subject: [PATCH 02/31] gd32: add firmware ops and tidy includes Add Gd32FirmwareOps.mk to centralize GCC warning suppressions for GD32 firmware builds. Update common/make/gd32/Includes.mk to mark CMSIS and lib-gd32 headers as -isystem (reducing external-header warnings), reorder and consolidate include paths, and keep local ./include. Update firmware-template-gd32/lib/Rules.mk to include the new ops file and apply GD32FIRMWAREOPS to C compilation; also remove a redundant generic C compile rule. These changes aim to silence third-party header warnings and simplify include handling for GD32 builds. --- common/make/gd32/Gd32FirmwareOps.mk | 3 +++ common/make/gd32/Includes.mk | 17 +++++++++-------- firmware-template-gd32/lib/Rules.mk | 6 ++---- 3 files changed, 14 insertions(+), 12 deletions(-) create mode 100644 common/make/gd32/Gd32FirmwareOps.mk diff --git a/common/make/gd32/Gd32FirmwareOps.mk b/common/make/gd32/Gd32FirmwareOps.mk new file mode 100644 index 00000000..3608a4cb --- /dev/null +++ b/common/make/gd32/Gd32FirmwareOps.mk @@ -0,0 +1,3 @@ +$(info "Gd32FirmwareOpts.mk") + +GD32FIRMWAREOPS=-Wno-error=unused-parameter -Wno-error=unused-but-set-variable -Wno-error=conversion -Wno-error=old-style-cast \ No newline at end of file diff --git a/common/make/gd32/Includes.mk b/common/make/gd32/Includes.mk index 8ead6bd3..a8396c5b 100644 --- a/common/make/gd32/Includes.mk +++ b/common/make/gd32/Includes.mk @@ -1,13 +1,14 @@ $(info "Includes.mk") -INCLUDES:=-I./include -INCLUDES+=-I../common/include -I../include -INCLUDES+=-I../firmware-template-gd32/include -INCLUDES+=-I../CMSIS/Core/Include -INCLUDES+=-I../lib-gd32/${FAMILY}/${FAMILY_UC}_standard_peripheral/Include -INCLUDES+=-I../lib-gd32/${FAMILY}/CMSIS/GD/${FAMILY_UC}/Include -INCLUDES+=-I../lib-gd32/include +INCLUDES:=-I../include +INCLUDES+=-isystem ../CMSIS/Core/Include +INCLUDES+=-isystem ../lib-gd32/${FAMILY}/${FAMILY_UC}_standard_peripheral/Include +INCLUDES+=-isystem ../lib-gd32/${FAMILY}/CMSIS/GD/${FAMILY_UC}/Include +INCLUDES+=-isystem ../lib-gd32/include +INCLUDES+=-isystem ../firmware-template-gd32/include +INCLUDES+=-I../common/include INCLUDES+=-I../lib-hwclock/include +INCLUDES+=-I./include INCLUDES+=$(addprefix -I,$(EXTRA_INCLUDES)) @@ -104,5 +105,5 @@ ifdef USB_HOST_MSC INCLUDES+=-I../lib-fatfs endif -INCLUDES:= $(strip -I../${PROJECT}/include $(sort $(INCLUDES))) +#INCLUDES:= $(strip -I../${PROJECT}/include $(sort $(INCLUDES))) $(info $$INCLUDES [${INCLUDES}]) \ No newline at end of file diff --git a/firmware-template-gd32/lib/Rules.mk b/firmware-template-gd32/lib/Rules.mk index 0eceb694..2ba46583 100644 --- a/firmware-template-gd32/lib/Rules.mk +++ b/firmware-template-gd32/lib/Rules.mk @@ -39,6 +39,7 @@ COPS+=-Wconversion endif include ../common/make/CppOps.mk +include ../common/make/gd32/Gd32FirmwareOps.mk BUILD=build_gd32/ BUILD_DIRS:=$(addprefix build_gd32/,$(SRCDIR)) @@ -60,7 +61,7 @@ $(info $$TARGET [${TARGET}]) define compile-objects $(info $1) $(BUILD)$1/%.o: $1/%.c - $(CC) -MD -MP $(COPS) -c $$< -o $$@ + $(CC) -MD -MP $(COPS) $(GD32FIRMWAREOPS) -c $$< -o $$@ $(BUILD)$1/%.o: $1/%.cpp $(CPP) -MD -MP $(COPS) $(CPPOPS) -c $$< -o $$@ @@ -84,9 +85,6 @@ clean: rm -rf build_gd32 rm -rf lib_gd32 -$(BUILD)%.o: %.c - $(CC) $(COPS) -c $< -o $@ - $(TARGET): Makefile.GD32 $(OBJECTS) $(AR) -r $(TARGET) $(OBJECTS) $(PREFIX)objdump -d $(TARGET) | $(PREFIX)c++filt > lib_gd32/lib.list From b4b531652e35b219b74bed5207a14c0f01b83843 Mon Sep 17 00:00:00 2001 From: Arjan Date: Tue, 23 Jun 2026 15:34:46 +0200 Subject: [PATCH 03/31] Add GD32F30X_XD support and cleanup pragmas Extend GD32F30x include detection to handle the GD32F30X_XD variant and update the MCU guard macro accordingly. Remove surrounding C++ diagnostic push/pop and pragma ignores from gd32xxxx.h to simplify the header. Add conditional IRQ name/number mapping for the XD variant in softuart0 uart0.cpp and simplify the TIMER_INTF interrupt clear by removing an unnecessary cast. --- lib-gd32/include/gd32xxxx.h | 21 +-------------------- lib-gd32/include/mcu/gd32f30x_mcu.h | 2 +- lib-gd32/src/softuart0/uart0.cpp | 7 ++++++- 3 files changed, 8 insertions(+), 22 deletions(-) diff --git a/lib-gd32/include/gd32xxxx.h b/lib-gd32/include/gd32xxxx.h index 19abbcc7..94d827bc 100644 --- a/lib-gd32/include/gd32xxxx.h +++ b/lib-gd32/include/gd32xxxx.h @@ -26,26 +26,11 @@ #ifndef GD32FXXX_H_ #define GD32FXXX_H_ -// Needed for GD32 Firmware and CMSIS - -#ifdef __cplusplus -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wuseless-cast" -#pragma GCC diagnostic ignored "-Wold-style-cast" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wsign-conversion" -#if __cplusplus > 201402 -// error: compound assignment with 'volatile'-qualified left operand is -// deprecated -#pragma GCC diagnostic ignored "-Wvolatile" -#endif -#endif - #if defined(GD32F10X_HD) || defined(GD32F10X_CL) #include "gd32f10x.h" // IWYU pragma: keep #elif defined(GD32F20X_CL) #include "gd32f20x.h" // IWYU pragma: keep -#elif defined(GD32F30X_HD) +#elif defined(GD32F30X_HD) || defined(GD32F30X_XD) #include "gd32f30x.h" // IWYU pragma: keep #elif defined(GD32F407) || defined(GD32F450) || defined(GD32F470) #include "gd32f4xx.h" // IWYU pragma: keep @@ -56,8 +41,4 @@ #error MCU is not supported #endif -#ifdef __cplusplus -#pragma GCC diagnostic pop -#endif - #endif // GD32FXXX_H_ */ diff --git a/lib-gd32/include/mcu/gd32f30x_mcu.h b/lib-gd32/include/mcu/gd32f30x_mcu.h index 190d0903..2aa1166d 100644 --- a/lib-gd32/include/mcu/gd32f30x_mcu.h +++ b/lib-gd32/include/mcu/gd32f30x_mcu.h @@ -26,7 +26,7 @@ #ifndef MCU_GD32F30X_MCU_H_ #define MCU_GD32F30X_MCU_H_ -#if !defined(GD32F30X_HD) +#if !defined(GD32F30X) # error This file should not be included #endif diff --git a/lib-gd32/src/softuart0/uart0.cpp b/lib-gd32/src/softuart0/uart0.cpp index b7334dbd..54e24455 100644 --- a/lib-gd32/src/softuart0/uart0.cpp +++ b/lib-gd32/src/softuart0/uart0.cpp @@ -35,8 +35,13 @@ #elif defined(GD32F30X) #define TIMERx TIMER7 #define RCU_TIMERx RCU_TIMER7 +#if defined (GD32F30X_XD) +#define TIMERx_IRQHandler TIMER7_UP_TIMER12_IRQHandler +#define TIMERx_IRQn TIMER7_UP_TIMER12_IRQn +#else #define TIMERx_IRQHandler TIMER7_UP_IRQHandler #define TIMERx_IRQn TIMER7_UP_IRQn +#endif #else #define TIMERx TIMER9 #define RCU_TIMERx RCU_TIMER9 @@ -147,7 +152,7 @@ void TIMERx_IRQHandler() { } } - TIMER_INTF(TIMERx) = static_cast(~kIntFlag); + TIMER_INTF(TIMERx) = ~kIntFlag; } #if defined(SOFTUART0_ENABLE_RX) void SOFTUART_RX_EXTIx_IRQHandler() { From 0afa0bd73ecac4418962b795e667f7ae9010837b Mon Sep 17 00:00:00 2001 From: Arjan Date: Tue, 23 Jun 2026 15:35:01 +0200 Subject: [PATCH 04/31] Fix DMX input indexing and simplify timer clears Use an explicit index variable when storing DMX data to avoid the post-increment-in-assignment pattern (prevents potential undefined behavior/overflow when updating slots_in_packet). Also remove redundant static_cast around bitwise negation when clearing timer interrupt flags in multiple IRQ handlers (TIMER1, TIMER4, TIMER6 and their channel clears) to simplify the code and improve clarity. --- lib-dmx/.settings/language.settings.xml | 2 +- lib-dmx/src/gd32/dmx.cpp | 25 ++++++++++++++----------- 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/lib-dmx/.settings/language.settings.xml b/lib-dmx/.settings/language.settings.xml index c51812af..5a4b2b51 100644 --- a/lib-dmx/.settings/language.settings.xml +++ b/lib-dmx/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + diff --git a/lib-dmx/src/gd32/dmx.cpp b/lib-dmx/src/gd32/dmx.cpp index 232968fc..c3c7a144 100644 --- a/lib-dmx/src/gd32/dmx.cpp +++ b/lib-dmx/src/gd32/dmx.cpp @@ -372,8 +372,11 @@ void IrqHandlerDmxRdmInput() { case dmx::TxRxState::kDmxData: { #if defined(CONFIG_DMX_DOUBLE_INPUT_BUFFER) dmx_data_buffer.slots_in_packet &= ~dmx::kDmxSlotsCompleteFlag; - dmx_data_buffer.data[dmx_data_buffer.slots_in_packet++] = kData; - + auto index = dmx_data_buffer.slots_in_packet; + dmx_data_buffer.data[index] = kData; + index++; + dmx_data_buffer.slots_in_packet = index; + if (dmx_data_buffer.slots_in_packet > dmx::kChannelsMax) { dmx_data_buffer.slots_in_packet |= dmx::kDmxSlotsCompleteFlag; @@ -604,7 +607,7 @@ void TIMER1_IRQHandler() { } } - TIMER_INTF(TIMER1) = static_cast(~TIMER_INT_FLAG_CH0); + TIMER_INTF(TIMER1) = ~TIMER_INT_FLAG_CH0; } #endif // defined(DMX_USE_USART0) // USART 1 @@ -673,7 +676,7 @@ void TIMER1_IRQHandler() { assert(false); } - TIMER_INTF(TIMER1) = static_cast(~TIMER_INT_FLAG_CH1); + TIMER_INTF(TIMER1) = ~TIMER_INT_FLAG_CH1; } #endif // defined(DMX_USE_USART1) // USART 2 @@ -743,7 +746,7 @@ void TIMER1_IRQHandler() { assert(false); } - TIMER_INTF(TIMER1) = static_cast(~TIMER_INT_FLAG_CH2); + TIMER_INTF(TIMER1) = ~TIMER_INT_FLAG_CH2; } #endif // defined(DMX_USE_USART2) // UART 3 @@ -811,7 +814,7 @@ void TIMER1_IRQHandler() { assert(false); } - TIMER_INTF(TIMER1) = static_cast(~TIMER_INT_FLAG_CH3); + TIMER_INTF(TIMER1) = ~TIMER_INT_FLAG_CH3; } #endif // defined(DMX_USE_UART3) // Clear all remaining interrupt flags (safety measure) @@ -888,7 +891,7 @@ void TIMER4_IRQHandler() { assert(false); } - TIMER_INTF(TIMER4) = static_cast(~TIMER_INT_FLAG_CH0); + TIMER_INTF(TIMER4) = ~TIMER_INT_FLAG_CH0; } #endif // defined(DMX_USE_UART4) // USART 5 @@ -959,7 +962,7 @@ void TIMER4_IRQHandler() { assert(false); } - TIMER_INTF(TIMER4) = static_cast(~TIMER_INT_FLAG_CH1); + TIMER_INTF(TIMER4) = ~TIMER_INT_FLAG_CH1; } #endif // defined(DMX_USE_USART5) // UART 6 @@ -1020,7 +1023,7 @@ void TIMER4_IRQHandler() { assert(false); } - TIMER_INTF(TIMER4) = static_cast(~TIMER_INT_FLAG_CH2); + TIMER_INTF(TIMER4) = ~TIMER_INT_FLAG_CH2; } #endif // defined(DMX_USE_UART6) // UART 7 @@ -1081,7 +1084,7 @@ void TIMER4_IRQHandler() { assert(false); } - TIMER_INTF(TIMER4) = static_cast(~TIMER_INT_FLAG_CH3); + TIMER_INTF(TIMER4) = ~TIMER_INT_FLAG_CH3; } #endif // defined(DMX_USE_UART7) // Clear all remaining interrupt flags (safety measure) @@ -1103,7 +1106,7 @@ void TIMER6_IRQHandler() { } // Clear all remaining interrupt flags (safety measure) - TIMER_INTF(TIMER6) = static_cast(~kIntFlag); + TIMER_INTF(TIMER6) = ~kIntFlag; } // USART 0 From 071752a94db160d638d2f0682ba249d326bc9901 Mon Sep 17 00:00:00 2001 From: Arjan Date: Tue, 23 Jun 2026 16:35:24 +0200 Subject: [PATCH 05/31] Remove redundant cast in TIMER6 IRQ handler Replace static_cast(~kIntFlag) with ~kIntFlag in TIMER6_IRQHandler. This removes an unnecessary explicit cast when writing the interrupt-clear value to TIMER_INTF, keeping behavior the same and avoiding potential compiler warnings about redundant conversions. --- lib-gd32/src/timer6.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib-gd32/src/timer6.cpp b/lib-gd32/src/timer6.cpp index 148e456c..a070f9b4 100644 --- a/lib-gd32/src/timer6.cpp +++ b/lib-gd32/src/timer6.cpp @@ -41,7 +41,7 @@ void TIMER6_IRQHandler() { gv_seconds.uptime = gv_seconds.uptime + 1; } - TIMER_INTF(TIMER6) = static_cast(~kIntFlag); + TIMER_INTF(TIMER6) = ~kIntFlag; } #endif } From 4544ab81aa68989b7235b3898a03f3b36528032b Mon Sep 17 00:00:00 2001 From: Arjan Date: Tue, 23 Jun 2026 17:56:23 +0200 Subject: [PATCH 06/31] Remove redundant cast in UART transmit assignments Simplify assignments to USART_TDATA in gd32_uart.cpp by removing explicit (uint32_t) casts when masking and writing byte data. Updated both Gd32UartTransmit and Gd32UartTransmitString for the GD32H7XX branch to rely on implicit integer promotion, reducing unnecessary casts and potential compiler warnings. --- lib-gd32/src/gd32_uart.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib-gd32/src/gd32_uart.cpp b/lib-gd32/src/gd32_uart.cpp index 20ffba7e..6c2948d2 100644 --- a/lib-gd32/src/gd32_uart.cpp +++ b/lib-gd32/src/gd32_uart.cpp @@ -309,7 +309,7 @@ void Gd32UartTransmit(uint32_t usart_periph, const uint8_t* data, uint32_t lengt while (length-- != 0) { while (RESET == usart_flag_get(usart_periph, USART_FLAG_TBE)); #if defined(GD32H7XX) - USART_TDATA(usart_periph) = USART_TDATA_TDATA & (uint32_t)*data++; + USART_TDATA(usart_periph) = USART_TDATA_TDATA & *data++; #else USART_DATA(usart_periph) = (USART_DATA_DATA & *data++); #endif @@ -324,7 +324,7 @@ void Gd32UartTransmitString(uint32_t usart_periph, const char* data) { while (*data != '\0') { while (RESET == usart_flag_get(USART0, USART_FLAG_TBE)); #if defined(GD32H7XX) - USART_TDATA(usart_periph) = USART_TDATA_TDATA & (uint32_t)*data++; + USART_TDATA(usart_periph) = USART_TDATA_TDATA & *data++; #else USART_DATA(usart_periph) = (USART_DATA_DATA & *data++); #endif From a2329fe2d8ca809fbec1e5e9b279592f9e4846ec Mon Sep 17 00:00:00 2001 From: Arjan Date: Sun, 28 Jun 2026 16:16:16 +0200 Subject: [PATCH 07/31] Adjust compiler warning flags for GD32 builds Update makefile compiler options to improve build compatibility: add `-Dcplusplus` to C++ flags and expand GD32 firmware warning overrides into separate entries, including new `-Wno-error` rules for `unused-function`, `unused-variable`, and `duplicated-cond`. --- common/make/CppOps.mk | 3 ++- common/make/gd32/Gd32FirmwareOps.mk | 8 +++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/common/make/CppOps.mk b/common/make/CppOps.mk index ed076fc1..bcb7bcb0 100755 --- a/common/make/CppOps.mk +++ b/common/make/CppOps.mk @@ -4,4 +4,5 @@ CPPOPS=-std=c++20 CPPOPS+=-Wnon-virtual-dtor -Woverloaded-virtual -Wnull-dereference -fno-rtti -fno-exceptions -fno-unwind-tables CPPOPS+=-Wuseless-cast -Wold-style-cast CPPOPS+=-fno-threadsafe-statics -fno-use-cxa-atexit -CPPOPS+=-Wshadow -Wshadow=local \ No newline at end of file +CPPOPS+=-Wshadow -Wshadow=local +CPPOPS+=-Dcplusplus \ No newline at end of file diff --git a/common/make/gd32/Gd32FirmwareOps.mk b/common/make/gd32/Gd32FirmwareOps.mk index 3608a4cb..1e11064e 100644 --- a/common/make/gd32/Gd32FirmwareOps.mk +++ b/common/make/gd32/Gd32FirmwareOps.mk @@ -1,3 +1,9 @@ $(info "Gd32FirmwareOpts.mk") -GD32FIRMWAREOPS=-Wno-error=unused-parameter -Wno-error=unused-but-set-variable -Wno-error=conversion -Wno-error=old-style-cast \ No newline at end of file +GD32FIRMWAREOPS =-Wno-error=unused-parameter +GD32FIRMWAREOPS+=-Wno-error=unused-but-set-variable +GD32FIRMWAREOPS+=-Wno-error=conversion +GD32FIRMWAREOPS+=-Wno-error=old-style-cast +GD32FIRMWAREOPS+=-Wno-error=unused-function +GD32FIRMWAREOPS+=-Wno-error=unused-variable +GD32FIRMWAREOPS+=-Wno-error=duplicated-cond \ No newline at end of file From 07076905d7c6c2f70c7ef5264469516ef7bcf9f1 Mon Sep 17 00:00:00 2001 From: Arjan Date: Sun, 28 Jun 2026 16:16:26 +0200 Subject: [PATCH 08/31] Tidy debug_dump header and NDEBUG stub MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reformatted `debug_dump.h` to match the project’s brace/loop style without changing dump behavior. In release builds, the no-op `Dump` function is now declared `static inline`, giving it internal linkage in each translation unit. --- common/include/firmware/debug/debug_dump.h | 42 ++++++++-------------- 1 file changed, 14 insertions(+), 28 deletions(-) diff --git a/common/include/firmware/debug/debug_dump.h b/common/include/firmware/debug/debug_dump.h index ef6f4f61..f0becbe5 100755 --- a/common/include/firmware/debug/debug_dump.h +++ b/common/include/firmware/debug/debug_dump.h @@ -31,41 +31,34 @@ #include #if defined(H3) -namespace uart0 -{ +namespace uart0 { int Printf(const char* fmt, ...); } #define printf uart0::Printf // NOLINT #endif -namespace debug -{ -namespace dump -{ +namespace debug { +namespace dump { inline constexpr uint32_t kCharsPerLine = 16; } #ifdef NDEBUG -inline void Dump([[maybe_unused]] const void* data, [[maybe_unused]] uint32_t size) {} +static inline void Dump([[maybe_unused]] const void* data, [[maybe_unused]] uint32_t size) {} #else -inline void Dump(const void* data, uint32_t size) -{ +inline void Dump(const void* data, uint32_t size) { uint32_t chars = 0; const auto* p = reinterpret_cast(data); printf("%p:%d\n", data, size); - do - { + do { uint32_t chars_this_line = 0; printf("%04x ", chars); const auto* q = p; - while ((chars_this_line < dump::kCharsPerLine) && (chars < size)) - { - if (chars_this_line % 8 == 0) - { + while ((chars_this_line < dump::kCharsPerLine) && (chars < size)) { + if (chars_this_line % 8 == 0) { printf(" "); } @@ -78,10 +71,8 @@ inline void Dump(const void* data, uint32_t size) auto chars_dot_line = chars_this_line; - for (; chars_this_line < dump::kCharsPerLine; chars_this_line++) - { - if (chars_this_line % 8 == 0) - { + for (; chars_this_line < dump::kCharsPerLine; chars_this_line++) { + if (chars_this_line % 8 == 0) { printf(" "); } printf(" "); @@ -89,20 +80,15 @@ inline void Dump(const void* data, uint32_t size) chars_this_line = 0; - while (chars_this_line < chars_dot_line) - { - if (chars_this_line % 8 == 0) - { + while (chars_this_line < chars_dot_line) { + if (chars_this_line % 8 == 0) { printf(" "); } int ch = *q; - if (isprint(ch)) - { + if (isprint(ch)) { printf("%c", ch); - } - else - { + } else { printf("."); } From fb94154f1e161200b77e626767859746c3bbc79c Mon Sep 17 00:00:00 2001 From: Arjan Date: Sun, 28 Jun 2026 16:16:39 +0200 Subject: [PATCH 09/31] Tighten enum and integer type conversions Add explicit underlying type for `dmxnode::FailSafe` and introduce targeted casts/unsigned literals in ADC, SPI, BKP, and FT245RL code paths. These changes make integer promotions explicit and avoid implicit conversion warnings while preserving existing behavior. --- lib-dmxnode/include/dmxnode.h | 2 +- lib-gd32/src/f/gd32_adc.cpp | 8 ++++---- lib-gd32/src/f/gd32_spi.cpp | 2 +- lib-gd32/src/gd32_bkp.cpp | 4 ++-- lib-usb/src/gd32/ft245rl.cpp | 18 +++++++++--------- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/lib-dmxnode/include/dmxnode.h b/lib-dmxnode/include/dmxnode.h index 75c0ced9..defe53c3 100755 --- a/lib-dmxnode/include/dmxnode.h +++ b/lib-dmxnode/include/dmxnode.h @@ -80,7 +80,7 @@ inline static constexpr const char kLtpUpper[] = "LTP"; enum class Direction { kInput, kOutput, kDisable }; -enum class FailSafe { kHold, kOff, kOn, kPlayback, kRecord }; +enum class FailSafe : uint8_t { kHold, kOff, kOn, kPlayback, kRecord }; namespace failsafe { inline static constexpr const char kHold[] = "hold"; diff --git a/lib-gd32/src/f/gd32_adc.cpp b/lib-gd32/src/f/gd32_adc.cpp index c26e6a43..f16ae7e2 100644 --- a/lib-gd32/src/f/gd32_adc.cpp +++ b/lib-gd32/src/f/gd32_adc.cpp @@ -23,7 +23,7 @@ * THE SOFTWARE. */ -#include "gd32.h" +#include "gd32.h" // IWYU pragma: keep #include "timing.h" void Gd32AdcInit() { @@ -86,20 +86,20 @@ void Gd32AdcInit() { } float G32AdcGetTemp() { - const float kTemperature = (1.43f - ADC_IDATA0(ADC0) * 3.3f / 4096U) * 1000U / 4.3f + 25U; + const float kTemperature = (1.43f - static_cast(ADC_IDATA0(ADC0)) * 3.3f / 4096U) * 1000U / 4.3f + 25U; adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL); return kTemperature; } float Gd32AdcGetVref() { - const float kVrefValue = (ADC_IDATA1(ADC0) * 3.3f / 4096U); + const float kVrefValue = static_cast(ADC_IDATA1(ADC0)) * 3.3f / 4096U; adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL); return kVrefValue; } #if defined(GD32F4XX) float Gd32AdcGetVbat() { - const float kVrefValue = (ADC_IDATA2(ADC0) * 3.3f / 4096U) * 4U; + const float kVrefValue = (static_cast(ADC_IDATA2(ADC0)) * 3.3f / 4096U) * 4U; adc_software_trigger_enable(ADC0, ADC_INSERTED_CHANNEL); return kVrefValue; } diff --git a/lib-gd32/src/f/gd32_spi.cpp b/lib-gd32/src/f/gd32_spi.cpp index f149af9c..6565e7a5 100644 --- a/lib-gd32/src/f/gd32_spi.cpp +++ b/lib-gd32/src/f/gd32_spi.cpp @@ -265,7 +265,7 @@ static inline char BitbangSpiWriteRead(char c) { GPIO_BOP(SPI_BITBANG_SCK_GPIOx) = SPI_BITBANG_SCK_GPIO_PINx; if ((GPIO_ISTAT(SPI_BITBANG_MISO_GPIOx) & SPI_BITBANG_MISO_GPIO_PINx) == SPI_BITBANG_MISO_GPIO_PINx) { - r |= (mask); + r |= static_cast(mask); } __ISB(); diff --git a/lib-gd32/src/gd32_bkp.cpp b/lib-gd32/src/gd32_bkp.cpp index 8b500074..9f47970f 100644 --- a/lib-gd32/src/gd32_bkp.cpp +++ b/lib-gd32/src/gd32_bkp.cpp @@ -44,10 +44,10 @@ void bkp_data_write(bkp_data_register_enum register_number, uint16_t data) { uint16_t bkp_data_read(bkp_data_register_enum register_number) { switch (register_number) { case BKP_DATA_0: - return RTC_BKP0; + return static_cast(RTC_BKP0); break; case BKP_DATA_1: - return RTC_BKP1; + return static_cast(RTC_BKP1); break; default: assert(false && "Invalid register_number"); diff --git a/lib-usb/src/gd32/ft245rl.cpp b/lib-usb/src/gd32/ft245rl.cpp index d3ea16cd..88042c35 100644 --- a/lib-usb/src/gd32/ft245rl.cpp +++ b/lib-usb/src/gd32/ft245rl.cpp @@ -155,15 +155,15 @@ uint8_t FT245RL_read_data() const auto kInGpioA = static_cast(GPIO_ISTAT(GPIOA)); const auto kInGpioB = static_cast(GPIO_ISTAT(GPIOB)); - data |= ((kInGpioA & (GPIO_PIN_6)) ? 4 : 0); - data |= ((kInGpioA & (GPIO_PIN_14)) ? 8 : 0); - data |= ((kInGpioA & (GPIO_PIN_15)) ? 16 : 0); - - data |= ((kInGpioB & (GPIO_PIN_9)) ? 1 : 0); - data |= ((kInGpioB & (GPIO_PIN_8)) ? 2 : 0); - data |= ((kInGpioB & (GPIO_PIN_4)) ? 32 : 0); - data |= ((kInGpioB & (GPIO_PIN_5)) ? 64 : 0); - data |= ((kInGpioB & (GPIO_PIN_3)) ? 128 : 0); + data |= ((kInGpioA & (GPIO_PIN_6)) ? 4U : 0); + data |= ((kInGpioA & (GPIO_PIN_14)) ? 8U : 0); + data |= ((kInGpioA & (GPIO_PIN_15)) ? 16U : 0); + + data |= ((kInGpioB & (GPIO_PIN_9)) ? 1U : 0); + data |= ((kInGpioB & (GPIO_PIN_8)) ? 2U : 0); + data |= ((kInGpioB & (GPIO_PIN_4)) ? 32U : 0); + data |= ((kInGpioB & (GPIO_PIN_5)) ? 64U : 0); + data |= ((kInGpioB & (GPIO_PIN_3)) ? 128U : 0); // Bring RD# back up so the FT245 can let go of the data. Gd32GpioSet(_RD); From 1e73fcd7d04d897b02871598374d8ca98f73a860 Mon Sep 17 00:00:00 2001 From: Arjan Date: Sun, 28 Jun 2026 17:05:19 +0200 Subject: [PATCH 10/31] Use uint8_t in RTC BCD conversion helpers Update `BCD2DEC` and `DEC2BCD` in `hwclockrtc.cpp` to return `uint8_t` and use explicit `static_cast`/unsigned literals in the math. This tightens type safety for RTC BCD conversions and avoids implicit signed-integer behavior. --- lib-hwclock/src/gd32/internal/hwclockrtc.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib-hwclock/src/gd32/internal/hwclockrtc.cpp b/lib-hwclock/src/gd32/internal/hwclockrtc.cpp index afe9b299..6de8aee7 100644 --- a/lib-hwclock/src/gd32/internal/hwclockrtc.cpp +++ b/lib-hwclock/src/gd32/internal/hwclockrtc.cpp @@ -47,12 +47,12 @@ #include "gd32.h" #if defined(GD32F4XX) || defined(GD32H7XX) -static int BCD2DEC(int val) { - return (((val) & 0x0f) + (val >> 4) * 10); +static uint8_t BCD2DEC(int val) { + return static_cast(((val) & 0x0f) + static_cast(val >> 4) * 10U); } -static int DEC2BCD(int val) { - return ((((val) / 10) << 4) + val % 10); +static uint8_t DEC2BCD(int val) { + return static_cast(((static_cast(val) / 10U) << 4) + (static_cast(val) % 10U)); } #define RTC_CLOCK_SOURCE_LXTAL static rtc_parameter_struct rtc_initpara; From e8cba3255489420f3fec859e59e14f3f021d5e1b Mon Sep 17 00:00:00 2001 From: Arjan Date: Sun, 28 Jun 2026 18:29:01 +0200 Subject: [PATCH 11/31] Adjust GD32 build warning handling Relax the GD32 firmware build by allowing missing field initializers and implicit function declarations without failing, and include extra C/C++ source directories in `SRCDIR` so additional sources are picked up during object generation. --- common/make/gd32/Gd32FirmwareOps.mk | 4 +++- common/make/lib/Objects.mk | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/common/make/gd32/Gd32FirmwareOps.mk b/common/make/gd32/Gd32FirmwareOps.mk index 1e11064e..518ddbed 100644 --- a/common/make/gd32/Gd32FirmwareOps.mk +++ b/common/make/gd32/Gd32FirmwareOps.mk @@ -6,4 +6,6 @@ GD32FIRMWAREOPS+=-Wno-error=conversion GD32FIRMWAREOPS+=-Wno-error=old-style-cast GD32FIRMWAREOPS+=-Wno-error=unused-function GD32FIRMWAREOPS+=-Wno-error=unused-variable -GD32FIRMWAREOPS+=-Wno-error=duplicated-cond \ No newline at end of file +GD32FIRMWAREOPS+=-Wno-error=duplicated-cond +GD32FIRMWAREOPS+=-Wno-error=missing-field-initializers +GD32FIRMWAREOPS+=-Wno-error=implicit-function-declaration \ No newline at end of file diff --git a/common/make/lib/Objects.mk b/common/make/lib/Objects.mk index 37dfa4d9..7ff3594a 100755 --- a/common/make/lib/Objects.mk +++ b/common/make/lib/Objects.mk @@ -17,3 +17,4 @@ ifneq ($(EXTRA_CPP_SOURCE_FILES),) endif OBJECTS:=$(strip $(ASM_OBJECTS) $(C_OBJECTS) $(CPP_OBJECTS) $(EXTRA_C_OBJECTS) $(EXTRA_CPP_OBJECTS)) +SRCDIR+=$(EXTRA_C_DIRECTORIES) $(EXTRA_CPP_DIRECTORIES) \ No newline at end of file From 926e8c13a63372ba011f16e1e65599f52f0c6170 Mon Sep 17 00:00:00 2001 From: Arjan Date: Mon, 29 Jun 2026 15:11:55 +0200 Subject: [PATCH 12/31] Update GD32F30x CMSIS HAL to v3.0.3 Update CMSIS HAL files to firmware version 3.0.3 with enhanced stability during clock frequency switching. Key changes include: - Improved RCU_MODIFY macro for Vcore fluctuation prevention - Added software delay function to stabilize transitions - Converted direct register writes to read-modify-write pattern in clock functions - Added firmware version query support - Updated copyright year to 2026 - Removed deprecated GCC diagnostic pragmas - Added HardFault_IRQn to interrupt enumeration --- .../CMSIS/GD/GD32F30x/Include/gd32f30x.h | 77 ++++--- .../GD/GD32F30x/Include/system_gd32f30x.h | 8 + .../GD/GD32F30x/Source/GCC/newlib/syscalls.c | 190 ++++++++++++++++++ .../GD/GD32F30x/Source/system_gd32f30x.c | 175 ++++++++++++---- 4 files changed, 365 insertions(+), 85 deletions(-) create mode 100644 lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Source/GCC/newlib/syscalls.c diff --git a/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Include/gd32f30x.h b/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Include/gd32f30x.h index dffd4284..0fe4cc91 100644 --- a/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Include/gd32f30x.h +++ b/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Include/gd32f30x.h @@ -2,50 +2,42 @@ \file gd32f30x.h \brief general definitions for GD32F30x - \version 2017-02-10, V1.0.0, firmware for GD32F30x - \version 2018-10-10, V1.1.0, firmware for GD32F30x - \version 2018-12-25, V2.0.0, firmware for GD32F30x - \version 2020-09-30, V2.1.0, firmware for GD32F30x + \version 2026-2-6, V3.0.3, firmware for GD32F30x */ -/* - Copyright (c) 2020, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ +/* Copyright (c) 2012 ARM LIMITED + Copyright (c) 2026, GigaDevice Semiconductor Inc. + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ #ifndef GD32F30X_H #define GD32F30X_H -/* AvV BEGIN */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wunused-function" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wduplicated-cond" -/* AvV END */ - #ifdef __cplusplus extern "C" { #endif @@ -100,10 +92,10 @@ OF SUCH DAMAGE. #define LXTAL_VALUE ((uint32_t)32768) #endif /* low speed crystal oscillator value */ -/* GD32F30x firmware library version number V1.0 */ -#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +/* GD32F30x firmware library version number V3.0.3 */ +#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */ #define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ #define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\ |(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\ @@ -120,7 +112,8 @@ OF SUCH DAMAGE. typedef enum IRQn { /* Cortex-M4 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */ + NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */ + HardFault_IRQn = -13, /*!< hard-fault interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */ diff --git a/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Include/system_gd32f30x.h b/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Include/system_gd32f30x.h index 4bfdc70c..1a277af1 100644 --- a/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Include/system_gd32f30x.h +++ b/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Include/system_gd32f30x.h @@ -5,6 +5,7 @@ */ /* Copyright (c) 2012 ARM LIMITED + Copyright (c) 2026, GigaDevice Semiconductor Inc. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -30,6 +31,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ + /* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ #ifndef SYSTEM_GD32F30X_H @@ -43,12 +45,18 @@ extern "C" { /* system clock frequency (core clock) */ extern uint32_t SystemCoreClock; +/* firmware version can be aquired by uncommenting the macro */ +#define __FIRMWARE_VERSION_DEFINE /* function declarations */ /* initialize the system and update the SystemCoreClock variable */ extern void SystemInit (void); /* update the SystemCoreClock with current core clock retrieved from cpu registers */ extern void SystemCoreClockUpdate (void); +#ifdef __FIRMWARE_VERSION_DEFINE +/* get firmware version */ +extern uint32_t gd32f30x_firmware_version_get(void); +#endif /* __FIRMWARE_VERSION_DEFINE */ #ifdef __cplusplus } diff --git a/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Source/GCC/newlib/syscalls.c b/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Source/GCC/newlib/syscalls.c new file mode 100644 index 00000000..a4454f37 --- /dev/null +++ b/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Source/GCC/newlib/syscalls.c @@ -0,0 +1,190 @@ +/*! + \file syscall.c + \brief system calls file + + \version 2026-2-6, V3.0.3, firmware for GD32F30x +*/ + +/* + Copyright (c) 2026, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include <_ansi.h> +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#undef errno +extern int errno; + +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +caddr_t _sbrk(int incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if((curbrk + incr < _end) || (curbrk + incr > _heap_end)) { + return NULL - 1; + } + + curbrk += incr; + return curbrk - incr; +} + +/* _gettimeofday primitive (Stub function) */ +int _gettimeofday(struct timeval *tp, struct timezone *tzp) +{ + /* Return fixed data for the timezone. */ + if(tzp) { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit(int status) +{ + _kill(status, -1); + while(1) { + } +} + +int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for(DataIdx = 0; DataIdx < len; DataIdx++) { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + return -1; +} + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for(DataIdx = 0; DataIdx < len; DataIdx++) { + *ptr++ = __io_getchar(); + } + + return len; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} diff --git a/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c b/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c index 388cea74..4c9e5d66 100644 --- a/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c +++ b/lib-gd32/gd32f30x/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c @@ -5,6 +5,7 @@ */ /* Copyright (c) 2012 ARM LIMITED + Copyright (c) 2026, GigaDevice Semiconductor Inc. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -30,6 +31,7 @@ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ + /* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ #include "gd32f30x.h" @@ -54,14 +56,45 @@ //#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000) #define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000) -#define RCU_MODIFY(__delay) do{ \ - volatile uint32_t i; \ - if(0 != __delay){ \ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \ - for(i=0; i<__delay; i++){ \ +/* The following is to prevent Vcore fluctuations caused by frequency switching. + It is strongly recommended to include it to avoid issues caused by self-removal. */ +#define RCU_MODIFY_4(__delay) do{ \ + volatile uint32_t i, reg; \ + if(0U != (__delay)){ \ + /* Insert a software delay */ \ + for(i=0U; i<(__delay); i++){ \ + } \ + reg = RCU_CFG0; \ + reg &= ~(RCU_CFG0_AHBPSC); \ + reg |= RCU_AHB_CKSYS_DIV2; \ + /* AHB = SYSCLK/2 */ \ + RCU_CFG0 = reg; \ + /* Insert a software delay */ \ + for(i=0U; i<(__delay); i++){ \ + } \ + reg = RCU_CFG0; \ + reg &= ~(RCU_CFG0_AHBPSC); \ + reg |= RCU_AHB_CKSYS_DIV4; \ + /* AHB = SYSCLK/4 */ \ + RCU_CFG0 = reg; \ + /* Insert a software delay */ \ + for(i=0U; i<(__delay); i++){ \ + } \ + reg = RCU_CFG0; \ + reg &= ~(RCU_CFG0_AHBPSC); \ + reg |= RCU_AHB_CKSYS_DIV8; \ + /* AHB = SYSCLK/8 */ \ + RCU_CFG0 = reg; \ + /* Insert a software delay */ \ + for(i=0U; i<(__delay); i++){ \ } \ - RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \ - for(i=0; i<__delay; i++){ \ + reg = RCU_CFG0; \ + reg &= ~(RCU_CFG0_AHBPSC); \ + reg |= RCU_AHB_CKSYS_DIV16; \ + /* AHB = SYSCLK/16 */ \ + RCU_CFG0 = reg; \ + /* Insert a software delay */ \ + for(i=0U; i<(__delay); i++){ \ } \ } \ }while(0) @@ -106,6 +139,16 @@ static void system_clock_120m_hxtal(void); /* configure the system clock */ static void system_clock_config(void); +static void _soft_delay_(uint32_t time); + +/* software delay to prevent the impact of Vcore fluctuations. + It is strongly recommended to include it to avoid issues caused by self-removal. */ +static void _soft_delay_(uint32_t time) +{ + __IO uint32_t i; + for(i=0U; i> clk_exp; } + +#ifdef __FIRMWARE_VERSION_DEFINE +/*! + \brief get firmware version + \param[in] none + \param[out] none + \retval firmware version +*/ +uint32_t gd32f30x_firmware_version_get(void) +{ + return (uint32_t)__GD32F30x_STDPERIPH_VERSION; +} +#endif /* __FIRMWARE_VERSION_DEFINE */ From 46ee22d7c4c2905ae9f11fde46585a8f246834d0 Mon Sep 17 00:00:00 2001 From: Arjan Date: Mon, 29 Jun 2026 15:12:03 +0200 Subject: [PATCH 13/31] Cast UART0 DMA count to uint16_t Add an explicit `static_cast` when computing `sv_rx_count.rx` in `USART0_IRQHandler` to avoid implicit narrowing from `dma_transfer_number_get(...)` and make the intended RX counter type conversion clear. --- lib-gd32/src/uart0/uart0.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib-gd32/src/uart0/uart0.cpp b/lib-gd32/src/uart0/uart0.cpp index bea1b738..a2a43b35 100644 --- a/lib-gd32/src/uart0/uart0.cpp +++ b/lib-gd32/src/uart0/uart0.cpp @@ -56,7 +56,7 @@ extern "C" void USART0_IRQHandler() { if (RESET != usart_interrupt_flag_get(USART0, USART_INT_FLAG_IDLE)) { usart_data_receive(USART0); - sv_rx_count.rx = kSizeRxBuffer - (dma_transfer_number_get(USART0_DMAx, USART0_RX_DMA_CHx)); + sv_rx_count.rx = static_cast(kSizeRxBuffer - (dma_transfer_number_get(USART0_DMAx, USART0_RX_DMA_CHx))); sv_receive_flag = 1; auto chtl = DMA_CHCTL(USART0_DMAx, USART0_RX_DMA_CHx); From 791202f0f10ffa71c0c86ccc6b8dd6a3252ad32a Mon Sep 17 00:00:00 2001 From: Arjan Date: Fri, 3 Jul 2026 13:49:05 +0200 Subject: [PATCH 14/31] Fix copyright emails and improve parameter names Fix duplicate 'info@' in email addresses in delete.cpp and dso_handle.cpp. Update copyright year to 2026 in delete.cpp and new.cpp. Rename parameter `p` to `pointer` in delete operators and add `noexcept` to non-sized overloads. Name previously unnamed `size` parameter in placement new. --- lib-clib/src/c++/delete.cpp | 18 +++++++++--------- lib-clib/src/c++/dso_handle.cpp | 2 +- lib-clib/src/c++/new.cpp | 4 ++-- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/lib-clib/src/c++/delete.cpp b/lib-clib/src/c++/delete.cpp index ac49d3ac..21330dec 100755 --- a/lib-clib/src/c++/delete.cpp +++ b/lib-clib/src/c++/delete.cpp @@ -2,7 +2,7 @@ * @file delete.cpp * */ -/* Copyright (C) 2017-2025 by Arjan van Vught mailto:info@info@gd32-dmx.org +/* Copyright (C) 2017-2026 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,12 +31,12 @@ * These are the global operator delete overloads for single objects (delete) and arrays (delete[]). */ -void operator delete(void *p) { - free(p); +void operator delete(void *pointer) noexcept { + free(pointer); } -void operator delete[](void *p) { - free(p); +void operator delete[](void *pointer) noexcept { + free(pointer); } /* @@ -44,12 +44,12 @@ void operator delete[](void *p) { * These overloads include the size of the object being deleted as an additional parameter (std::size_t size). */ -void operator delete(void *p, [[maybe_unused]] std::size_t size) noexcept { - free(p); +void operator delete(void *pointer, [[maybe_unused]] std::size_t size) noexcept { + free(pointer); } -void operator delete[](void *p, [[maybe_unused]]std::size_t size) noexcept { - free(p); +void operator delete[](void *pointer, [[maybe_unused]]std::size_t size) noexcept { + free(pointer); } /* diff --git a/lib-clib/src/c++/dso_handle.cpp b/lib-clib/src/c++/dso_handle.cpp index 2b06c2e4..9b9e1c70 100755 --- a/lib-clib/src/c++/dso_handle.cpp +++ b/lib-clib/src/c++/dso_handle.cpp @@ -2,7 +2,7 @@ * @file dso_handle.cpp * */ -/* Copyright (C) 2023 by Arjan van Vught mailto:info@info@gd32-dmx.org +/* Copyright (C) 2023 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal diff --git a/lib-clib/src/c++/new.cpp b/lib-clib/src/c++/new.cpp index 37717447..d2f079da 100755 --- a/lib-clib/src/c++/new.cpp +++ b/lib-clib/src/c++/new.cpp @@ -2,7 +2,7 @@ * @file new.cpp * */ -/* Copyright (C) 2017-2025 by Arjan van Vught mailto:info@gd32-dmx.org +/* Copyright (C) 2017-2026 by Arjan van Vught mailto:info@gd32-dmx.org * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -49,6 +49,6 @@ void *operator new[](std::size_t size) { * Placement new does not allocate memory. */ -void *operator new([[maybe_unused]] std::size_t, void *ptr) noexcept { +void *operator new([[maybe_unused]] std::size_t size, void *ptr) noexcept { return ptr; } From b154fed57ab8a0c2ec9fd199532b8fe39549c4d3 Mon Sep 17 00:00:00 2001 From: Arjan Date: Fri, 3 Jul 2026 13:49:22 +0200 Subject: [PATCH 15/31] Reorganize LCD config to config::lcd namespace Moved lib-display/include/spi/config.h to lib-display/include/spi/config/config_lcd.h and updated the namespace from `config` to `config::lcd` for better organization and clarity. Updated all include paths and namespace references in ili9341.h, paint.h, spilcd.h, st7735s.h, and st7789.h. Also fixed macro definition formatting for consistency. --- .../spi/{config.h => config/config_lcd.h} | 46 +++++++++---------- lib-display/include/spi/ili9341.h | 18 ++++---- lib-display/include/spi/paint.h | 10 ++-- lib-display/include/spi/spilcd.h | 2 +- lib-display/include/spi/st7735s.h | 18 ++++---- lib-display/include/spi/st7789.h | 18 ++++---- 6 files changed, 56 insertions(+), 56 deletions(-) rename lib-display/include/spi/{config.h => config/config_lcd.h} (67%) mode change 100755 => 100644 diff --git a/lib-display/include/spi/config.h b/lib-display/include/spi/config/config_lcd.h old mode 100755 new mode 100644 similarity index 67% rename from lib-display/include/spi/config.h rename to lib-display/include/spi/config/config_lcd.h index b9d66b83..38de3b95 --- a/lib-display/include/spi/config.h +++ b/lib-display/include/spi/config/config_lcd.h @@ -1,5 +1,5 @@ /** - * @file config.h + * @file config_lcd.h * */ /* Copyright (C) 2022-2026 by Arjan van Vught mailto:info@gd32-dmx.org @@ -28,7 +28,7 @@ #include -namespace config { +namespace config::lcd { #if defined(SPI_LCD_240X240) inline constexpr uint32_t kWidth = 240; inline constexpr uint32_t kHeight = 240; @@ -44,38 +44,38 @@ inline constexpr uint32_t kHeight = 160; #else #error lib-display spi config #endif -} // namespace config +} // namespace config::lcd #if defined(H3) -#define SPI_LCD_RST_GPIO GPIO_EXT_7 // GPIO6 -#define SPI_LCD_DC_GPIO GPIO_EXT_26 // GPIO10 -#define SPI_LCD_BL_GPIO GPIO_EXT_22 // GPIO2 +#define SPI_LCD_RST_GPIO GPIO_EXT_7 // GPIO6 +#define SPI_LCD_DC_GPIO GPIO_EXT_26 // GPIO10 +#define SPI_LCD_BL_GPIO GPIO_EXT_22 // GPIO2 #if defined(SPI_LCD_HAVE_CS_GPIO) -#define SPI_LCD_CS_GPIO GPIO_EXT_24 // GPIO13 / SPI CS0 -#endif // defined(SPI_LCD_HAVE_CS_GPIO) -#elif defined(GD32) // See board file +#define SPI_LCD_CS_GPIO GPIO_EXT_24 // GPIO13 / SPI CS0 +#endif // defined(SPI_LCD_HAVE_CS_GPIO) +#elif defined(GD32) // See board file #elif defined(RASPPI) #include "gpio_rasppi.h" -#define SPI_LCD_RST_GPIO GPIO_EXT_7 // GPIO4 -#define SPI_LCD_DC_GPIO GPIO_EXT_31 // GPIO6 -#define SPI_LCD_BL_GPIO GPIO_EXT_29 // GPIO5 +#define SPI_LCD_RST_GPIO GPIO_EXT_7 // GPIO4 +#define SPI_LCD_DC_GPIO GPIO_EXT_31 // GPIO6 +#define SPI_LCD_BL_GPIO GPIO_EXT_29 // GPIO5 #if defined(SPI_LCD_HAVE_CS_GPIO) -#define SPI_LCD_CS_GPIO GPIO_EXT_22 // GPIO25 -#endif // defined(SPI_LCD_HAVE_CS_GPIO) +#define SPI_LCD_CS_GPIO GPIO_EXT_22 // GPIO25 +#endif // defined(SPI_LCD_HAVE_CS_GPIO) #elif defined(ODROID) #include "gpio_odroid.h" -#define SPI_LCD_RST_GPIO GPIO_EXT_7 // GPIO4 -#define SPI_LCD_DC_GPIO GPIO_EXT_31 // GPIO6 -#define SPI_LCD_BL_GPIO GPIO_EXT_29 // GPIO5 +#define SPI_LCD_RST_GPIO GPIO_EXT_7 // GPIO4 +#define SPI_LCD_DC_GPIO GPIO_EXT_31 // GPIO6 +#define SPI_LCD_BL_GPIO GPIO_EXT_29 // GPIO5 #if defined(SPI_LCD_HAVE_CS_GPIO) -#define SPI_LCD_CS_GPIO GPIO_EXT_22 // GPIO25 -#endif // defined(SPI_LCD_HAVE_CS_GPIO) +#define SPI_LCD_CS_GPIO GPIO_EXT_22 // GPIO25 +#endif // defined(SPI_LCD_HAVE_CS_GPIO) #else -#define SPI_LCD_RST_GPIO 0 -#define SPI_LCD_DC_GPIO 0 -#define SPI_LCD_BL_GPIO 0 +#define SPI_LCD_RST_GPIO 0 +#define SPI_LCD_DC_GPIO 0 +#define SPI_LCD_BL_GPIO 0 #if defined(SPI_LCD_HAVE_CS_GPIO) -#define SPI_LCD_CS_GPIO 0 +#define SPI_LCD_CS_GPIO 0 #endif // defined(SPI_LCD_HAVE_CS_GPIO) #endif diff --git a/lib-display/include/spi/ili9341.h b/lib-display/include/spi/ili9341.h index a1734cde..1a50d144 100755 --- a/lib-display/include/spi/ili9341.h +++ b/lib-display/include/spi/ili9341.h @@ -29,7 +29,7 @@ #include #include -#include "spi/config.h" +#include "spi/config/config_lcd.h" namespace ili9341 { namespace cmd { @@ -178,23 +178,23 @@ class ILI9341 : public Paint { switch (nRotation) { case 0: WriteDataByte(ili9341::data::kMadctlBgr); - width_ = config::kWidth; - height_ = config::kHeight; + width_ = config::lcd::kWidth; + height_ = config::lcd::kHeight; break; case 1: WriteDataByte(ili9341::data::kMadctlMx | ili9341::data::kMadctlMv | ili9341::data::kMadctlBgr); - width_ = config::kHeight; - height_ = config::kWidth; + width_ = config::lcd::kHeight; + height_ = config::lcd::kWidth; break; case 2: WriteDataByte(ili9341::data::kMadctlMx | ili9341::data::kMadctlMy | ili9341::data::kMadctlBgr); - width_ = config::kWidth; - height_ = config::kHeight; + width_ = config::lcd::kWidth; + height_ = config::lcd::kHeight; break; case 3: WriteDataByte(ili9341::data::kMadctlMy | ili9341::data::kMadctlMv | ili9341::data::kMadctlBgr); - width_ = config::kHeight; - height_ = config::kWidth; + width_ = config::lcd::kHeight; + height_ = config::lcd::kWidth; break; default: assert(0); diff --git a/lib-display/include/spi/paint.h b/lib-display/include/spi/paint.h index a82078d9..8959a994 100755 --- a/lib-display/include/spi/paint.h +++ b/lib-display/include/spi/paint.h @@ -32,7 +32,7 @@ #include "spi/lcd_font.h" #include "spi/spilcd.h" -#include "spi/config.h" +#include "spi/config/config_lcd.h" #include "firmware/debug/debug_debug.h" class Paint : public SpiLcd { @@ -57,7 +57,7 @@ class Paint : public SpiLcd { ClearCS(); SetDC(); - for (uint32_t i = 0; i < config::kHeight / kFrameBufferRows; i++) { + for (uint32_t i = 0; i < config::lcd::kHeight / kFrameBufferRows; i++) { WriteDataContinue(reinterpret_cast(s_frame_buffer), sizeof(s_frame_buffer)); } @@ -225,8 +225,8 @@ class Paint : public SpiLcd { } protected: - uint32_t width_{config::kWidth}; - uint32_t height_{config::kHeight}; + uint32_t width_{config::lcd::kWidth}; + uint32_t height_{config::lcd::kHeight}; uint32_t rotate_{0}; #if !defined(SPI_LCD_kFrameBufferRows) @@ -235,7 +235,7 @@ class Paint : public SpiLcd { static constexpr uint32_t kFrameBufferRows = SPI_LCD_kFrameBufferRows; #endif - static inline uint16_t s_frame_buffer[config::kWidth * kFrameBufferRows]; + static inline uint16_t s_frame_buffer[config::lcd::kWidth * kFrameBufferRows]; }; #endif // SPI_PAINT_H_ diff --git a/lib-display/include/spi/spilcd.h b/lib-display/include/spi/spilcd.h index 47c967fa..3704ef98 100755 --- a/lib-display/include/spi/spilcd.h +++ b/lib-display/include/spi/spilcd.h @@ -27,7 +27,7 @@ #define SPI_SPILCD_H_ #include "timing.h" -#include "spi/config.h" +#include "spi/config/config_lcd.h" #include "spi.h" #include "gpio.h" #include "firmware/debug/debug_debug.h" diff --git a/lib-display/include/spi/st7735s.h b/lib-display/include/spi/st7735s.h index 199bdf71..08304f97 100755 --- a/lib-display/include/spi/st7735s.h +++ b/lib-display/include/spi/st7735s.h @@ -38,7 +38,7 @@ #include #include -#include "spi/config.h" +#include "spi/config/config_lcd.h" #include "spi/st77xx.h" #include "firmware/debug/debug_debug.h" @@ -128,29 +128,29 @@ class ST7735S : public ST77XX { WriteDataByte(st77xx::data::kMadctlMx | st77xx::data::kMadctlMy | st77xx::data::kMadctlBgr); shift_x_ = st7735s::kRotation0ShiftX; shift_y_ = st7735s::kRotation0ShiftY; - width_ = config::kWidth; - height_ = config::kHeight; + width_ = config::lcd::kWidth; + height_ = config::lcd::kHeight; break; case 1: WriteDataByte(st77xx::data::kMadctlMy | st77xx::data::kMadctlMv | st77xx::data::kMadctlBgr); shift_x_ = st7735s::kRotation1ShiftX; shift_y_ = st7735s::kRotation1ShiftY; - width_ = config::kHeight; - height_ = config::kWidth; + width_ = config::lcd::kHeight; + height_ = config::lcd::kWidth; break; case 2: WriteDataByte(st77xx::data::kMadctlBgr); shift_x_ = st7735s::kRotation2ShiftX; shift_y_ = st7735s::kRotation2ShiftY; - width_ = config::kWidth; - height_ = config::kHeight; + width_ = config::lcd::kWidth; + height_ = config::lcd::kHeight; break; case 3: WriteDataByte(st77xx::data::kMadctlMx | st77xx::data::kMadctlMv | st77xx::data::kMadctlBgr); shift_x_ = st7735s::kRotation3ShiftX; shift_y_ = st7735s::kRotation3ShiftY; - width_ = config::kHeight; - height_ = config::kWidth; + width_ = config::lcd::kHeight; + height_ = config::lcd::kWidth; break; default: assert(0); diff --git a/lib-display/include/spi/st7789.h b/lib-display/include/spi/st7789.h index bdfb96df..081c32f0 100755 --- a/lib-display/include/spi/st7789.h +++ b/lib-display/include/spi/st7789.h @@ -29,7 +29,7 @@ #include #include -#include "spi/config.h" +#include "spi/config/config_lcd.h" #include "spi/st77xx.h" #include "timing.h" #include "firmware/debug/debug_debug.h" @@ -143,29 +143,29 @@ class ST7789 : public ST77XX { WriteDataByte(st77xx::data::kMadctlMx | st77xx::data::kMadctlMy | st77xx::data::kMadctlRgb); shift_x_ = st7789::kRotation0ShiftX; shift_y_ = st7789::kRotation0ShiftY; - width_ = config::kWidth; - height_ = config::kHeight; + width_ = config::lcd::kWidth; + height_ = config::lcd::kHeight; break; case 1: WriteDataByte(st77xx::data::kMadctlMy | st77xx::data::kMadctlMv | st77xx::data::kMadctlRgb); shift_x_ = st7789::kRotation1ShiftX; shift_y_ = st7789::kRotation1ShiftY; - width_ = config::kHeight; - height_ = config::kWidth; + width_ = config::lcd::kHeight; + height_ = config::lcd::kWidth; break; case 2: WriteDataByte(st77xx::data::kMadctlRgb); shift_x_ = st7789::kRotation2ShiftX; shift_y_ = st7789::kRotation2ShiftY; - width_ = config::kWidth; - height_ = config::kHeight; + width_ = config::lcd::kWidth; + height_ = config::lcd::kHeight; break; case 3: WriteDataByte(st77xx::data::kMadctlMx | st77xx::data::kMadctlMv | st77xx::data::kMadctlRgb); shift_x_ = st7789::kRotation3ShiftX; shift_y_ = st7789::kRotation3ShiftY; - width_ = config::kHeight; - height_ = config::kWidth; + width_ = config::lcd::kHeight; + height_ = config::lcd::kWidth; break; default: assert(0); From d63dbf8f51ba3ba8e41e2ac7040c2b6df172d71f Mon Sep 17 00:00:00 2001 From: Arjan Date: Fri, 3 Jul 2026 13:49:38 +0200 Subject: [PATCH 16/31] Centralize GD32 unique ID access Extract unique ID memory access into a dedicated header file (gd32_unique_id.h) to eliminate code duplication across macaddress, serialnumber, and uuid modules. This provides a single source of truth for device-specific memory addresses and simplifies future maintenance. --- .../Include/gd32f30x_enet.h | 9 +- lib-gd32/include/gd32_unique_id.h | 55 +++++++++++ lib-gd32/src/macaddress.cpp | 23 ++--- lib-gd32/src/serialnumber.cpp | 17 ++-- lib-gd32/src/softuart0/uart0.cpp | 91 +++++++++++++------ lib-gd32/src/uuid.cpp | 36 ++------ 6 files changed, 143 insertions(+), 88 deletions(-) create mode 100644 lib-gd32/include/gd32_unique_id.h diff --git a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h index 65ff502a..f3e99414 100644 --- a/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h +++ b/lib-gd32/gd32f30x/GD32F30x_standard_peripheral/Include/gd32f30x_enet.h @@ -67,9 +67,12 @@ OF SUCH DAMAGE. #endif /* USE_DELAY */ #ifndef _PHY_H_ -#define DP83848 0 -#define LAN8700 1 -#define PHY_TYPE DP83848 +#define DP83848 0 +#define LAN8700 1 +#define RTL8201F 2 // AvV +#ifndef PHY_TYPE // AvV +#define PHY_TYPE DP83848 // AvV +#endif // AvV #define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ diff --git a/lib-gd32/include/gd32_unique_id.h b/lib-gd32/include/gd32_unique_id.h new file mode 100644 index 00000000..ecf44a5a --- /dev/null +++ b/lib-gd32/include/gd32_unique_id.h @@ -0,0 +1,55 @@ +/** + * @file gd32_unique_id.h + * + */ +/* Copyright (C) 2026 by Arjan van Vught mailto:info@gd32-dmx.org +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: + +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. + +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ + +#ifndef GD32_UNIQUE_ID_H_ +#define GD32_UNIQUE_ID_H_ + +#include + +namespace gd32::uid { +#if defined(GD32H7XX) +static constexpr uintptr_t kBase = 0x1FF0F7E8; +#elif defined(GD32F4XX) +static constexpr uintptr_t kBase = 0x1FFF7A10; +#else +static constexpr uintptr_t kBase = 0x1FFFF7E8; +#endif + +static inline uint32_t Word(uint32_t index) { + return *reinterpret_cast(kBase + (index * sizeof(uint32_t))); +} + +static inline uint32_t Word0() { + return Word(0); +} +static inline uint32_t Word1() { + return Word(1); +} +static inline uint32_t Word2() { + return Word(2); +} +} // namespace gd32::uid + +#endif // GD32_UNIQUE_ID_H_ diff --git a/lib-gd32/src/macaddress.cpp b/lib-gd32/src/macaddress.cpp index 7810b397..fc502e3f 100644 --- a/lib-gd32/src/macaddress.cpp +++ b/lib-gd32/src/macaddress.cpp @@ -30,25 +30,18 @@ #include #include "firmware/debug/debug_debug.h" +#include "gd32_unique_id.h" void MacAddress(uint8_t paddr[]) { -#if defined(GD32H7XX) - const auto kMacaddressHigh = *reinterpret_cast(0x1FF0F7E8); - const auto kMacAddressLow = *reinterpret_cast(0x1FF0F7EC); -#elif defined(GD32F4XX) - const auto kMacaddressHigh = *reinterpret_cast(0x1FFF7A10); - const auto kMacAddressLow = *reinterpret_cast(0x1FFF7A14); -#else - const auto kMacaddressHigh = *reinterpret_cast(0x1FFFF7E8); - const auto kMacAddressLow = *reinterpret_cast(0x1FFFF7EC); -#endif + const auto kId0 = gd32::uid::Word0(); + const auto kId1 = gd32::uid::Word1(); paddr[0] = 2; - paddr[1] = static_cast((kMacAddressLow >> 0) & 0xFF); - paddr[2] = static_cast((kMacaddressHigh >> 24) & 0xFF); - paddr[3] = static_cast((kMacaddressHigh >> 16) & 0xFF); - paddr[4] = static_cast((kMacaddressHigh >> 8) & 0xFF); - paddr[5] = static_cast((kMacaddressHigh >> 0) & 0xFF); + paddr[1] = static_cast((kId1 >> 0) & 0xFF); + paddr[2] = static_cast((kId0 >> 24) & 0xFF); + paddr[3] = static_cast((kId0 >> 16) & 0xFF); + paddr[4] = static_cast((kId0 >> 8) & 0xFF); + paddr[5] = static_cast((kId0 >> 0) & 0xFF); DEBUG_PRINTF("%02x:%02x:%02x:%02x:%02x:%02x", paddr[0], paddr[1], paddr[2], paddr[3], paddr[4], paddr[5]); } diff --git a/lib-gd32/src/serialnumber.cpp b/lib-gd32/src/serialnumber.cpp index 8a4c770a..54bfec7e 100644 --- a/lib-gd32/src/serialnumber.cpp +++ b/lib-gd32/src/serialnumber.cpp @@ -26,18 +26,13 @@ #include #include "serialnumber.h" +#include "gd32_unique_id.h" void SerialNumber(uint8_t sn[kSnSize]) { -#if defined(GD32H7XX) - const auto kMacaddressHigh = *reinterpret_cast(0x1FF0F7E8); -#elif defined(GD32F4XX) - const auto kMacaddressHigh = *reinterpret_cast(0x1FFF7A10); -#else - const auto kMacaddressHigh = *reinterpret_cast(0x1FFFF7E8); -#endif + const auto kId0 = gd32::uid::Word0(); - sn[0] = static_cast((kMacaddressHigh >> 0) & 0xFF); - sn[1] = static_cast((kMacaddressHigh >> 8) & 0xFF); - sn[2] = static_cast((kMacaddressHigh >> 16) & 0xFF); - sn[3] = static_cast((kMacaddressHigh >> 24) & 0xFF); + sn[0] = static_cast((kId0 >> 0) & 0xFF); + sn[1] = static_cast((kId0 >> 8) & 0xFF); + sn[2] = static_cast((kId0 >> 16) & 0xFF); + sn[3] = static_cast((kId0 >> 24) & 0xFF); } diff --git a/lib-gd32/src/softuart0/uart0.cpp b/lib-gd32/src/softuart0/uart0.cpp index 54e24455..3ee72bdf 100644 --- a/lib-gd32/src/softuart0/uart0.cpp +++ b/lib-gd32/src/softuart0/uart0.cpp @@ -22,61 +22,61 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ - + #include #include "gd32.h" -#if defined(GD32H7XX) -#define TIMERx TIMER15 -#define RCU_TIMERx RCU_TIMER15 +#if defined(GD32H7XX) // GD32H7XX +#define TIMERx TIMER15 +#define RCU_TIMERx RCU_TIMER15 #define TIMERx_IRQHandler TIMER15_IRQHandler -#define TIMERx_IRQn TIMER15_IRQn -#elif defined(GD32F30X) -#define TIMERx TIMER7 -#define RCU_TIMERx RCU_TIMER7 -#if defined (GD32F30X_XD) +#define TIMERx_IRQn TIMER15_IRQn +#elif defined(GD32F30X) // GD32F30X +#define TIMERx TIMER7 +#define RCU_TIMERx RCU_TIMER7 +#if defined(GD32F30X_XD) // GD32F30X_XD #define TIMERx_IRQHandler TIMER7_UP_TIMER12_IRQHandler -#define TIMERx_IRQn TIMER7_UP_TIMER12_IRQn +#define TIMERx_IRQn TIMER7_UP_TIMER12_IRQn #else #define TIMERx_IRQHandler TIMER7_UP_IRQHandler -#define TIMERx_IRQn TIMER7_UP_IRQn +#define TIMERx_IRQn TIMER7_UP_IRQn #endif #else -#define TIMERx TIMER9 -#define RCU_TIMERx RCU_TIMER9 +#define TIMERx TIMER9 +#define RCU_TIMERx RCU_TIMER9 #define TIMERx_IRQHandler TIMER0_UP_TIMER9_IRQHandler -#define TIMERx_IRQn TIMER0_UP_TIMER9_IRQn +#define TIMERx_IRQn TIMER0_UP_TIMER9_IRQn #endif #if defined(GD32H7XX) -#define TIMER_CLOCK_FREQ (AHB_CLOCK_FREQ) +#define TIMER_CLOCK_FREQ (AHB_CLOCK_FREQ) #elif defined(GD32F4XX) -#define TIMER_CLOCK_FREQ (APB2_CLOCK_FREQ * 2) +#define TIMER_CLOCK_FREQ (APB2_CLOCK_FREQ * 2) #else -#define TIMER_CLOCK_FREQ (APB2_CLOCK_FREQ) +#define TIMER_CLOCK_FREQ (APB2_CLOCK_FREQ) #endif #if !defined(SOFTUART_TX_PINx) -#define SOFTUART_TX_PINx GPIO_PIN_9 -#define SOFTUART_TX_GPIOx GPIOA -#define SOFTUART_TX_RCU_GPIOx RCU_GPIOA +#define SOFTUART_TX_PINx GPIO_PIN_9 +#define SOFTUART_TX_GPIOx GPIOA +#define SOFTUART_TX_RCU_GPIOx RCU_GPIOA #endif #if defined(SOFTUART0_ENABLE_RX) #if !defined(SOFTUART_RX_PINx) -#define SOFTUART_RX_PINx GPIO_PIN_10 -#define SOFTUART_RX_GPIOx GPIOA -#define SOFTUART_RX_RCU_GPIOx RCU_GPIOA +#define SOFTUART_RX_PINx GPIO_PIN_10 +#define SOFTUART_RX_GPIOx GPIOA +#define SOFTUART_RX_RCU_GPIOx RCU_GPIOA #if defined(GD32H7XX) #error #else -#define SOFTUART_RX_TIMERx TIMER0 -#define SOFTUART_RX_RCU_TIMERx RCU_TIMER0 -#define SOFTUART_RX_EXTIx_IRQHandler EXTI10_15_IRQHandler -#define SOFTUART_RX_EXTIx_IRQn EXTI10_15_IRQn -#define SOFTUART_RX_GPIO_PORT_SOURCE_GPIOx GPIO_PORT_SOURCE_GPIOB -#define SOFTUART_RX_GPIO_PIN_SOURCE_x GPIO_PIN_SOURCE_14 +#define SOFTUART_RX_TIMERx TIMER11 +#define SOFTUART_RX_RCU_TIMERx RCU_TIMER11 +#define SOFTUART_RX_EXTIx_IRQHandler EXTI10_15_IRQHandler +#define SOFTUART_RX_EXTIx_IRQn EXTI10_15_IRQn +#define SOFTUART_RX_GPIO_PORT_SOURCE_GPIOx GPIO_PORT_SOURCE_GPIOB +#define SOFTUART_RX_GPIO_PIN_SOURCE_x GPIO_PIN_SOURCE_14 #endif #endif // !defined(SOFTUART_RX_PINx) static_assert(TIMERx != SOFTUART_RX_TIMERx); @@ -92,7 +92,7 @@ static constexpr uint32_t kTimerPeriod = ((TIMER_CLOCK_FREQ / kBaudRate) - 1U); static constexpr uint32_t kBufferSize = 128U; enum class TxState { kIdle, kStartBit, kData, kStopBit }; -enum class RxState { kIdle, kVerifyStart, kData, kStopBit }; +enum class RxState { kIdle, kStart, kData, kStop }; struct CircularBuffer { uint8_t buffer[kBufferSize]; @@ -108,6 +108,8 @@ static volatile uint8_t s_tx_shift; #if defined(SOFTUART0_ENABLE_RX) static volatile CircularBuffer s_rx_buffer __attribute__((aligned(4))); static volatile RxState s_rx_state; +static volatile uint8_t s_rx_data; +static volatile uint8_t s_rx_shift; #endif // defined(SOFTUART0_ENABLE_RX) extern "C" { @@ -156,6 +158,35 @@ void TIMERx_IRQHandler() { } #if defined(SOFTUART0_ENABLE_RX) void SOFTUART_RX_EXTIx_IRQHandler() { + if (RESET == exti_interrupt_flag_get(EXTI_14)) { + return; + } + + exti_interrupt_flag_clear(EXTI_14); + + if (s_rx_state != RxState::kIdle) { + return; + } + + if ((GPIO_ISTAT(SOFTUART_RX_GPIOx) & SOFTUART_RX_PINx) != 0U) { + return; + } + + s_rx_state = RxState::kStart; + s_rx_data = 0; + s_rx_shift = 0; + + exti_interrupt_disable(EXTI_14); + + timer_disable(SOFTUART_RX_TIMERx); + timer_counter_value_config(SOFTUART_RX_TIMERx, 0); + + // First sample = middle of first data bit + // = 1.5 bit times after falling edge. + timer_channel_output_pulse_value_config(SOFTUART_RX_TIMERx, TIMER_CH_0, (kTimerPeriod * 3U) / 2U); + + timer_interrupt_flag_clear(SOFTUART_RX_TIMERx, TIMER_INT_FLAG_CH0); + timer_enable(SOFTUART_RX_TIMERx); } #endif } diff --git a/lib-gd32/src/uuid.cpp b/lib-gd32/src/uuid.cpp index 5c0f55ce..2d63f62a 100644 --- a/lib-gd32/src/uuid.cpp +++ b/lib-gd32/src/uuid.cpp @@ -23,41 +23,19 @@ * THE SOFTWARE. */ -#if !defined(__clang__) -#pragma GCC push_options -#pragma GCC optimize("O2") -#pragma GCC optimize("no-tree-loop-distribute-patterns") -#pragma GCC optimize("-funroll-loops") -#endif - #include #include #include -#include "gd32.h" // IWYU pragma: keep - -typedef union pcast32 { - uuid_t uuid; - uint32_t u32[4]; -} _pcast32; +#include "gd32_unique_id.h" void UuidCopy(uuid_t out) { - _pcast32 cast; + uint32_t words[4]; -#if defined(GD32H7XX) - cast.u32[0] = REG32(0x1FF0F7E8); - cast.u32[1] = REG32(0x1FF0F7EC); - cast.u32[2] = REG32(0x1FF0F7F0); -#elif defined(GD32F4XX) - cast.u32[0] = REG32(0x1FFF7A10); - cast.u32[1] = REG32(0x1FFF7A14); - cast.u32[2] = REG32(0x1FFF7A18); -#else - cast.u32[0] = REG32(0x1FFFF7E8); - cast.u32[1] = REG32(0x1FFFF7EC); - cast.u32[2] = REG32(0x1FFFF7F0); -#endif - cast.u32[3] = cast.u32[0] + cast.u32[1] + cast.u32[2]; + words[0] = gd32::uid::Word0(); + words[1] = gd32::uid::Word1(); + words[2] = gd32::uid::Word2(); + words[3] = words[0] + words[1] + words[2]; - memcpy(out, cast.uuid, sizeof(uuid_t)); + memcpy(out, words, sizeof(uuid_t)); } From e267701859dece5c8311e46d01293548469b15ac Mon Sep 17 00:00:00 2001 From: Arjan Date: Fri, 3 Jul 2026 13:49:48 +0200 Subject: [PATCH 17/31] Add DMX slot timing constants Introduce DMX slot and baud-rate constants in `dmxconst.h`, and reformat the direction/send enums for consistency. This provides shared values for start-code plus channel counts and the standard DMX250k baud timing. --- lib-dmx/include/dmxconst.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/lib-dmx/include/dmxconst.h b/lib-dmx/include/dmxconst.h index 4bce18b3..580c905e 100755 --- a/lib-dmx/include/dmxconst.h +++ b/lib-dmx/include/dmxconst.h @@ -29,18 +29,29 @@ #include namespace dmx { -enum class Direction { kInput, kOutput, kDisable }; +enum class Direction { + kInput, ///< + kOutput, ///< + kDisable ///< +}; enum class OutputStyle { kDelta, ///< DMX frame is triggered kConstant ///< DMX output is continuous }; -enum class SendStyle { kDirect, kSync }; +enum class SendStyle { + kDirect, ///< + kSync ///< +}; inline constexpr uint32_t kStartCode = 0; ///< The start code for DMX512 data. This is often referred to as NSC for "Null Start Code". inline constexpr uint32_t kChannelsMin = 2; inline constexpr uint32_t kChannelsMax = 512; +inline constexpr uint32_t kSlotsMax = 1 + kChannelsMax; ///< Start code + channels +inline constexpr uint32_t kSlotTime = 44; ///< 40us + 4us space +inline constexpr uint32_t kBaudRate = 250000; + namespace transmit { inline constexpr uint32_t kBreakTimeMin = 92; ///< 92 us From 80c96cb3cbfa8073ab5c27feffa35d33f7535eb8 Mon Sep 17 00:00:00 2001 From: Arjan Date: Fri, 3 Jul 2026 13:49:57 +0200 Subject: [PATCH 18/31] Normalize header brace style Tightens brace formatting in the RDM headers and cleans up a minor endif spacing inconsistency without changing behavior. --- lib-rdm/include/rdm_message_print.h | 3 +- lib-rdm/include/rdm_preset_playback.h | 3 +- lib-rdm/include/rdm_selftest.h | 5 +- lib-rdm/include/rdm_tod.h | 145 +++++++++----------------- 4 files changed, 56 insertions(+), 100 deletions(-) diff --git a/lib-rdm/include/rdm_message_print.h b/lib-rdm/include/rdm_message_print.h index a12e6d94..cab487d1 100755 --- a/lib-rdm/include/rdm_message_print.h +++ b/lib-rdm/include/rdm_message_print.h @@ -28,8 +28,7 @@ #include -namespace rdm::message -{ +namespace rdm::message { void Print(const uint8_t* rdm_data); void PrintNoStartcode(const uint8_t* rdm_data_no_sc); } // namespace rdm::message diff --git a/lib-rdm/include/rdm_preset_playback.h b/lib-rdm/include/rdm_preset_playback.h index fba912c7..e8045d8e 100755 --- a/lib-rdm/include/rdm_preset_playback.h +++ b/lib-rdm/include/rdm_preset_playback.h @@ -28,8 +28,7 @@ #include -namespace rdm::preset_playback -{ +namespace rdm::preset_playback { inline constexpr uint16_t kOff = 0x0000; inline constexpr uint16_t kAll = 0xFFFF; diff --git a/lib-rdm/include/rdm_selftest.h b/lib-rdm/include/rdm_selftest.h index 0d1d7285..2223a833 100755 --- a/lib-rdm/include/rdm_selftest.h +++ b/lib-rdm/include/rdm_selftest.h @@ -28,11 +28,10 @@ #include -namespace rdm::selftest -{ +namespace rdm::selftest { uint8_t Get(); bool Set(uint8_t self_test); const char* GetDescription(uint8_t self_test, uint32_t& length); } // namespace rdm::selftest -#endif // RDM_SELFTEST_H_ +#endif // RDM_SELFTEST_H_ diff --git a/lib-rdm/include/rdm_tod.h b/lib-rdm/include/rdm_tod.h index 42919cee..45ff480e 100755 --- a/lib-rdm/include/rdm_tod.h +++ b/lib-rdm/include/rdm_tod.h @@ -36,10 +36,8 @@ #include "rdmconst.h" #include "firmware/debug/debug_debug.h" -namespace rdm -{ -class Tod -{ +namespace rdm { +class Tod { public: #if !defined(RDM_DISCOVERY_TOD_TABLE_SIZE) #define RDM_DISCOVERY_TOD_TABLE_SIZE 200U @@ -48,45 +46,36 @@ class Tod static constexpr uint32_t kMutesTableSize = (kTableSize + 32) / 32; static constexpr uint32_t kInvalidEntry = UINT32_MAX; - Tod() - { - for (uint32_t i = 0; i < kTableSize; i++) - { + Tod() { + for (uint32_t i = 0; i < kTableSize; i++) { memcpy(&tod_[i], rdm::kUidAll, rdm::kUidSize); } - for (uint32_t i = 0; i < kMutesTableSize; i++) - { + for (uint32_t i = 0; i < kMutesTableSize; i++) { mutes_[i] = 0; } } ~Tod() = default; - void Reset() - { - for (uint32_t i = 0; i < entries_; i++) - { + void Reset() { + for (uint32_t i = 0; i < entries_; i++) { memcpy(&tod_[i], rdm::kUidAll, rdm::kUidSize); } entries_ = 0; - for (uint32_t i = 0; i < kMutesTableSize; i++) - { + for (uint32_t i = 0; i < kMutesTableSize; i++) { mutes_[i] = 0; } } - bool AddUid(const uint8_t* uid) - { - if (entries_ == kTableSize) - { + bool AddUid(const uint8_t* uid) { + if (entries_ == kTableSize) { return false; } - if (Exist(uid)) - { + if (Exist(uid)) { return false; } @@ -97,10 +86,8 @@ class Tod uint32_t UidCount() const { return entries_; } - bool CopyUidEntry(uint32_t index, uint8_t uid[rdm::kUidSize]) - { - if (index > entries_) - { + bool CopyUidEntry(uint32_t index, uint8_t uid[rdm::kUidSize]) { + if (index > entries_) { memcpy(uid, rdm::kUidAll, rdm::kUidSize); return false; } @@ -109,8 +96,7 @@ class Tod return true; } - void Copy(uint8_t* table) - { + void Copy(uint8_t* table) { DEBUG_ENTRY(); DEBUG_PRINTF("entries_=%u", static_cast(entries_)); assert(table != nullptr); @@ -118,42 +104,33 @@ class Tod const auto* src = reinterpret_cast(tod_); auto* dst = table; - for (uint32_t i = 0; i < (entries_ * rdm::kUidSize); i++) - { + for (uint32_t i = 0; i < (entries_ * rdm::kUidSize); i++) { *dst++ = *src++; } DEBUG_EXIT(); } - bool Delete(const uint8_t* uid) - { + bool Delete(const uint8_t* uid) { bool found = false; - uint32_t i; + uint32_t entry; - for (i = 0; i < entries_; i++) - { - if (memcmp(&tod_[i], uid, rdm::kUidSize) == 0) - { + for (entry = 0; entry < entries_; entry++) { + if (memcmp(&tod_[entry], uid, rdm::kUidSize) == 0) { found = true; break; } } - if (!found) - { + if (!found) { return false; } - if (i == kTableSize - 1) - { - memcpy(&tod_[i], rdm::kUidAll, rdm::kUidSize); - } - else - { - for (; i < entries_; i++) - { - memcpy(&tod_[i], &tod_[i + 1], rdm::kUidSize); + if (entry == kTableSize - 1) { + memcpy(&tod_[entry], rdm::kUidAll, rdm::kUidSize); + } else { + for (; entry < entries_; entry++) { + memcpy(&tod_[entry], &tod_[entry + 1], rdm::kUidSize); } } @@ -162,12 +139,9 @@ class Tod return true; } - bool Exist(const uint8_t* uid) - { - for (uint32_t index = 0; index < entries_; index++) - { - if (memcmp(&tod_[index], uid, rdm::kUidSize) == 0) - { + bool Exist(const uint8_t* uid) { + for (uint32_t index = 0; index < entries_; index++) { + if (memcmp(&tod_[index], uid, rdm::kUidSize) == 0) { saved_index_ = index; return true; } @@ -177,84 +151,70 @@ class Tod return false; } - const uint8_t* Next() - { + const uint8_t* Next() { saved_index_++; - if (saved_index_ == entries_) - { + if (saved_index_ == entries_) { saved_index_ = 0; } return tod_[saved_index_].uid; } - void Mute() - { - if (saved_index_ == kInvalidEntry) - { + void Mute() { + if (saved_index_ == kInvalidEntry) { return; } - const auto kI = saved_index_ / 32; - const auto kShift = saved_index_ - (kI * 32); + const auto kIndex = saved_index_ / 32; + const auto kShift = saved_index_ - (kIndex * 32); - mutes_[kI] |= (1U << kShift); + mutes_[kIndex] |= (1U << kShift); } - void UnMute() - { - if (saved_index_ == kInvalidEntry) - { + void UnMute() { + if (saved_index_ == kInvalidEntry) { return; } - const auto kI = saved_index_ / 32; - const auto kShift = saved_index_ - (kI * 32); + const auto kIndex = saved_index_ / 32; + const auto kShift = saved_index_ - (kIndex * 32); - mutes_[kI] &= ~(1U << kShift); + mutes_[kIndex] &= ~(1U << kShift); } - void UnMuteAll() - { - for (uint32_t i = 0; i < kMutesTableSize; i++) - { + void UnMuteAll() { + for (uint32_t i = 0; i < kMutesTableSize; i++) { mutes_[i] = 0; } } - bool IsMuted() - { - if (saved_index_ == kInvalidEntry) - { + bool IsMuted() { + if (saved_index_ == kInvalidEntry) { return true; } - const auto kI = saved_index_ / 32; - const auto kMutes = mutes_[kI]; - const auto kShift = saved_index_ - (kI * 32); + const auto kIndex = saved_index_ / 32; + const auto kMutes = mutes_[kIndex]; + const auto kShift = saved_index_ - (kIndex * 32); return (kMutes & (1U << kShift)) == (1U << kShift); } - void Dump([[maybe_unused]] uint32_t count) - { + void Dump([[maybe_unused]] uint32_t count) { #ifndef NDEBUG - if (count > kTableSize) - { + if (count > kTableSize) { count = kTableSize; } printf("[%u]\n", static_cast(count)); - for (uint32_t i = 0; i < count; i++) - { + for (uint32_t i = 0; i < count; i++) { printf("%.2x%.2x:%.2x%.2x%.2x%.2x\n", tod_[i].uid[0], tod_[i].uid[1], tod_[i].uid[2], tod_[i].uid[3], tod_[i].uid[4], tod_[i].uid[5]); } #endif } - void Dump() - { + void Dump() { #ifndef NDEBUG Dump(entries_); #endif @@ -264,8 +224,7 @@ class Tod uint32_t entries_{0}; uint32_t saved_index_{kInvalidEntry}; uint32_t mutes_[kMutesTableSize]; - struct Uid - { + struct Uid { uint8_t uid[rdm::kUidSize]; }; Uid tod_[kTableSize]; From adc476d673e8ad20e76ad343f4bf5a6e39b6972a Mon Sep 17 00:00:00 2001 From: Arjan Date: Fri, 3 Jul 2026 14:02:58 +0200 Subject: [PATCH 19/31] Add GD32 device info lookups Extend `flash.py` to read GD32 chip UID and flash size, resolve series/part numbers from `gd32.json`, and add `--get-size`, `--get-uid`, and `--go` CLI options. The flasher also now handles serial reads more safely and includes a reusable memory read helper. --- common/scripts/gd32/flash.py | 452 ++++++++++++++++++++++++++++------- 1 file changed, 366 insertions(+), 86 deletions(-) diff --git a/common/scripts/gd32/flash.py b/common/scripts/gd32/flash.py index 1392cacc..99dde91a 100755 --- a/common/scripts/gd32/flash.py +++ b/common/scripts/gd32/flash.py @@ -1,17 +1,120 @@ #!/usr/bin/env python3 -import serial -import time -import sys import argparse -import subprocess -import os +import json +import sys +import time from pathlib import Path +import serial + +def load_gd32_db(filename="gd32.json"): + path = Path(__file__).resolve().parent / filename + + if not path.is_file(): + print(f"Warning: device database '{path}' not found.") + return {} + + try: + with path.open("r", encoding="utf-8") as f: + return json.load(f) + except json.JSONDecodeError as e: + print(f"Error parsing '{path}': {e}") + except OSError as e: + print(f"Error reading '{path}': {e}") + + return {} + +def normalize_chip_id(chip_id): + chip_id = str(chip_id).lower() + if chip_id.startswith("0x"): + chip_id = chip_id[2:] + return chip_id.zfill(4) + + +def db_get_family(db, chip_id): + chip_id = normalize_chip_id(chip_id) + + for key, value in db.items(): + if normalize_chip_id(key) == chip_id: + return value + + return None + +def lookup_part_number(family, series, flash_size_kb): + flash = family.get("flash", {}) + size_key = str(flash_size_kb) + + # Simple format: + # "flash": { "512": "GD32F207XEXX" } + part_number = flash.get(size_key) + if isinstance(part_number, str): + return part_number + + # Nested format with exact resolved series: + # "flash": { "GD32F407": { "512": "GD32F407XEXX" } } + # This is used after a probe has changed the generic family series + # "GD32F407/GD32F450" into the concrete series "GD32F407". + series_flash = flash.get(series) + if isinstance(series_flash, dict): + part_number = series_flash.get(size_key) + if isinstance(part_number, str): + return part_number + + # Fallback for generic or unresolved series names, for example when + # series is still "GD32F407/GD32F450" or when probing was not available. + # Search all nested flash maps and return the part when the flash size is + # unambiguous. + matches = [] + for value in flash.values(): + if not isinstance(value, dict): + continue + part_number = value.get(size_key) + if isinstance(part_number, str): + matches.append(part_number) + + if len(matches) == 1: + return matches[0] + + return "Unknown" + +def lookup_device(db, chip_id, flash_size_kb, flasher=None): + family = db_get_family(db, chip_id) + if family is None: + return { + "series": "Unknown", + "part_number": "Unknown" + } + + series = family.get("series", "Unknown") + + probes = family.get("probes", {}) + + if "tli_apb2en_bit26" in probes and flasher is not None: + probe = probes["tli_apb2en_bit26"] + + detected = flasher.probe_register_bit( + int(probe["address"], 0), + int(probe["bit"]) + ) + + if detected is True: + series = probe.get("set", series) + elif detected is False: + series = probe.get("clear", series) + + part_number = lookup_part_number(family, series, flash_size_kb) + + return { + "series": series, + "part_number": part_number + } + + class GD32Flasher: ACK = 0x79 NACK = 0x1F - + CMD_GET = 0x00 CMD_GET_VERSION = 0x01 CMD_GET_ID = 0x02 @@ -20,24 +123,24 @@ class GD32Flasher: CMD_WRITE_MEMORY = 0x31 CMD_ERASE = 0x43 CMD_EXTENDED_ERASE = 0x44 - + def __init__(self, port, baud=57600, timeout=5): self.port_name = port self.baud = baud self.timeout = timeout self.port = None - + def open(self): self.port = serial.Serial( self.port_name, self.baud, parity=serial.PARITY_EVEN, - timeout=self.timeout + timeout=self.timeout, ) self.port.dtr = False self.port.rts = False time.sleep(0.1) - + def close(self): if self.port: self.port.dtr = False @@ -46,64 +149,132 @@ def close(self): self.port.rts = False self.port.close() print("Done. Reset the MCU manually before the next bootloader session.") - + def enter_bootloader(self): - """Enter ROM bootloader mode using DTR/RTS""" print("Entering bootloader mode...") - + for dtr_state in [True, False]: self.port.dtr = dtr_state time.sleep(0.05) - + self.port.rts = True time.sleep(0.1) self.port.rts = False time.sleep(0.3) - + self.port.reset_input_buffer() - + if self._try_sync(): return True - + print(" FAILED: No bootloader response") return False - + def _try_sync(self, attempts=3): - for i in range(attempts): + for _ in range(attempts): self.port.write(bytes([0x7F])) time.sleep(0.1) resp = self.port.read(1) if resp and resp[0] == self.ACK: return True return False - + def _send_command(self, cmd): self.port.write(bytes([cmd, cmd ^ 0xFF])) resp = self.port.read(1) return resp and resp[0] == self.ACK - + def _wait_ack(self): resp = self.port.read(1) return resp and resp[0] == self.ACK - + def get_version(self): if not self._send_command(self.CMD_GET_VERSION): return None - version = self.port.read(1)[0] + + version_data = self.port.read(1) + if len(version_data) != 1: + return None + + version = version_data[0] self.port.read(2) self._wait_ack() return version - + def get_id(self): if not self._send_command(self.CMD_GET_ID): return None - n = self.port.read(1)[0] + + n_data = self.port.read(1) + if len(n_data) != 1: + return None + + n = n_data[0] chip_id = self.port.read(n + 1) + if len(chip_id) != n + 1: + return None + self._wait_ack() return chip_id.hex() + + def read_memory(self, address, length): + if not 1 <= length <= 256: + raise ValueError("length must be 1..256") + + if not self._send_command(self.CMD_READ_MEMORY): + return None + + addr_bytes = address.to_bytes(4, "big") + checksum = 0 + for b in addr_bytes: + checksum ^= b + + self.port.write(addr_bytes + bytes([checksum])) + + if not self._wait_ack(): + return None + + n = length - 1 + self.port.write(bytes([n, n ^ 0xFF])) + + if not self._wait_ack(): + return None + + data = self.port.read(length) + if len(data) != length: + return None + + return data + + def get_flash_size_kb(self, family): + if family in (0x0410, 0x0414, 0x0440, 0x0418): + flash_size_addr = 0x1FFFF7E0 + elif family == 0x0419: + flash_size_addr = 0x1FFF7A22 + else: + flash_size_addr = 0x1FFF77DE + + data = self.read_memory(flash_size_addr, 2) + if data is None or len(data) != 2: + return None + + return int.from_bytes(data, "little") + + def get_uid(self, family): + if family == 0x0419: + uid_addr = 0x1FFF7A10 + else: + uid_addr = 0x1FFFF7E8 + data = self.read_memory(uid_addr, 12) + if data is None or len(data) != 12: + return None + + return data.hex().upper() + def erase_all(self): print("Erasing flash...") + if not self._send_command(self.CMD_EXTENDED_ERASE): if not self._send_command(self.CMD_ERASE): print(" Erase command not supported") @@ -111,147 +282,226 @@ def erase_all(self): self.port.write(bytes([0xFF, 0x00])) else: self.port.write(bytes([0xFF, 0xFF, 0x00])) - + self.port.timeout = 30 result = self._wait_ack() self.port.timeout = self.timeout + print(" Erase " + ("OK" if result else "FAILED")) return result - + def write_memory(self, address, data): if not self._send_command(self.CMD_WRITE_MEMORY): return False - - addr_bytes = address.to_bytes(4, 'big') + + addr_bytes = address.to_bytes(4, "big") checksum = 0 for b in addr_bytes: checksum ^= b + self.port.write(addr_bytes + bytes([checksum])) - + if not self._wait_ack(): return False - + n = len(data) - 1 checksum = n for b in data: checksum ^= b + self.port.write(bytes([n]) + data + bytes([checksum])) - + return self._wait_ack() - + + def read_u32(self, address): + data = self.read_memory(address, 4) + if data is None or len(data) != 4: + return None + return int.from_bytes(data, "little") + + + def write_u32(self, address, value): + return self.write_memory(address, value.to_bytes(4, "little")) + + + def probe_register_bit(self, address, bit): + mask = 1 << bit + + original = self.read_u32(address) + if original is None: + return None + + if not self.write_u32(address, original | mask): + return None + + changed = self.read_u32(address) + + # Always restore original register value. + self.write_u32(address, original) + + if changed is None: + return None + + return bool(changed & mask) + def flash_file(self, filename, address, label=""): data = Path(filename).read_bytes() prefix = f"[{label}] " if label else "" + print(f"{prefix}Flashing {len(data)} bytes to 0x{address:08X}...") print(f"{prefix}File: {filename}") - + chunk_size = 256 offset = 0 - + while offset < len(data): chunk = data[offset:offset + chunk_size] current_addr = address + offset - + if not self.write_memory(current_addr, chunk): print(f"\n{prefix} Write failed at 0x{current_addr:08X}") return False - + offset += len(chunk) progress = offset * 100 // len(data) - print(f"\r{prefix} Progress: {progress}% ({offset}/{len(data)} bytes)", end='', flush=True) - + print( + f"\r{prefix} Progress: {progress}% ({offset}/{len(data)} bytes)", + end="", + flush=True, + ) + print(f"\n{prefix} Flash complete!") return True - + def run(self, address): print(f"Starting execution at 0x{address:08X}...") + if not self._send_command(self.CMD_GO): return False - - addr_bytes = address.to_bytes(4, 'big') + + addr_bytes = address.to_bytes(4, "big") checksum = 0 for b in addr_bytes: checksum ^= b + self.port.write(addr_bytes + bytes([checksum])) - + return self._wait_ack() +def print_device_info(flasher, gd32_db): + chip_id = flasher.get_id() + if chip_id is None: + print("Failed to read chip ID") + return False + + family = int(chip_id, 16) + size_kb = flasher.get_flash_size_kb(family) + if size_kb is None: + print("Failed to read flash size") + return False + + device = lookup_device(gd32_db, chip_id, size_kb, flasher) + + print(f"Chip ID : {chip_id}") + + if device: + print(f"Series : {device['series']}") + print(f"Flash size : {size_kb} KB") + print(f"Part number : {device['part_number']}") + else: + print("Series : Unknown") + print(f"Flash size : {size_kb} KB") + print("Part number : Unknown") + + return True + + def start_monitor(port, baud=115200, reset=True): - """Start a UART monitor on the specified port with auto-reconnect""" + """Start a UART monitor on the specified port with auto-reconnect.""" print(f"\n=== Starting UART Monitor on {port} at {baud} baud ===") print("Press Ctrl+C to exit\n") - + ser = None first_connect = True - + try: while True: - # Try to connect/reconnect if ser is None or not ser.is_open: try: ser = serial.Serial(port, baud, timeout=0.1) - + if first_connect: print("[Connected]") else: print("\n[Reconnected]") - - # Set normal boot mode - ser.dtr = True # BOOT0 = low (normal boot from flash) - + + ser.dtr = True # BOOT0 = low, normal boot from flash + if reset and first_connect: print("[Resetting board...]\n") - ser.rts = True # Assert reset + ser.rts = True time.sleep(0.1) - ser.rts = False # Release reset - board boots + ser.rts = False else: ser.rts = False - + first_connect = False - + except serial.SerialException: - # Port not available, wait briefly and retry time.sleep(0.05) continue - - # Read data + try: data = ser.read(1024) if data: try: - text = data.decode('utf-8', errors='replace') - print(text, end='', flush=True) - except: - print(data.hex(), end=' ', flush=True) + text = data.decode("utf-8", errors="replace") + print(text, end="", flush=True) + except UnicodeError: + print(data.hex(), end=" ", flush=True) except (serial.SerialException, OSError): - # Device disconnected print("\n[Disconnected - waiting for reconnect...]", flush=True) try: ser.close() - except: + except serial.SerialException: pass ser = None - + except KeyboardInterrupt: print("\n\nMonitor stopped.") finally: if ser and ser.is_open: ser.close() + def main(): - parser = argparse.ArgumentParser(description='Flash GD32 board') - parser.add_argument('--port', '-p', default='/dev/ttyUSB0', help='Serial port') - parser.add_argument('--baud', '-b', type=int, default=57600, help='Baud rate for flashing') - parser.add_argument('--monitor', action='store_true', help='Start UART monitor') - parser.add_argument('--get-version', action='store_true', help='Read bootloader version') - parser.add_argument('--get-id', action='store_true', help='Read chip ID') - parser.add_argument('--mass-erase', action='store_true', help='Erase entire flash') - parser.add_argument('--flash', metavar='FILE', help='Flash binary file') - parser.add_argument('--address', '-a', type=lambda x: int(x, 0), - default=0x08000000, - help='Flash start address (default: 0x08000000)') - parser.add_argument('--label', default='', help='Optional label for flash output') + parser = argparse.ArgumentParser(description="Flash GD32 board") + parser.add_argument("--port", "-p", default="/dev/ttyUSB0", help="Serial port") + parser.add_argument("--baud", "-b", type=int, default=57600, help="Baud rate for flashing") + parser.add_argument("--monitor", action="store_true", help="Start UART monitor") + parser.add_argument("--get-version", action="store_true", help="Read bootloader version") + parser.add_argument("--get-id", action="store_true", help="Read chip ID") + parser.add_argument("--get-uid", action="store_true", help="Read chip UID") + parser.add_argument("--get-size", action="store_true", help="Read flash size, series and part number") + parser.add_argument("--db", default="gd32.json", help="GD32 JSON database file") + parser.add_argument("--mass-erase", action="store_true", help="Erase entire flash") + parser.add_argument("--flash", metavar="FILE", help="Flash binary file") + parser.add_argument( + "--address", + "-a", + type=lambda x: int(x, 0), + default=0x08000000, + help="Flash start address (default: 0x08000000)", + ) + parser.add_argument("--label", default="", help="Optional label for flash output") + parser.add_argument("--go", action="store_true", help="Start execution after flashing") + parser.add_argument( + "--go-address", + type=lambda x: int(x, 0), + default=0x08000000, + help="Execution start address for --go (default: 0x08000000)", + ) args = parser.parse_args() @@ -263,14 +513,19 @@ def main(): needs_bootloader = any([ args.get_version, args.get_id, + args.get_uid, + args.get_size, args.mass_erase, - args.flash + args.flash, + args.go, ]) if not needs_bootloader: parser.print_help() return 0 + gd32_db = load_gd32_db(args.db) + flasher = GD32Flasher(args.port, args.baud) flasher.open() @@ -278,19 +533,36 @@ def main(): if not flasher.enter_bootloader(): return 1 + chip_id_already_printed = False + if args.get_version: version = flasher.get_version() if version is None: print("Failed to read bootloader version") - else: - print(f"Bootloader version: 0x{version:02X}") + return 1 + print(f"Bootloader version: 0x{version:02X}") + + if args.get_id and not args.get_size: + chip_id = flasher.get_id() + if chip_id is None: + print("Failed to read chip ID") + return 1 + print(f"Chip ID: {chip_id}") + chip_id_already_printed = True - if args.get_id: + if args.get_size: + if not print_device_info(flasher, gd32_db): + return 1 + chip_id_already_printed = True + + if args.get_uid: chip_id = flasher.get_id() if chip_id is None: print("Failed to read chip ID") - else: - print(f"Chip ID: {chip_id}") + return False + + chip_uid = flasher.get_uid(int(chip_id, 16)) + print(f"Chip UID : {chip_uid}") if args.mass_erase: if not flasher.erase_all(): @@ -300,10 +572,18 @@ def main(): if not flasher.flash_file(args.flash, args.address, args.label): return 1 + if args.go: + if not flasher.run(args.go_address): + return 1 + + # Keep variable useful for future extension and avoid lint warnings in strict editors. + _ = chip_id_already_printed + finally: flasher.close() return 0 - -if __name__ == '__main__': + + +if __name__ == "__main__": sys.exit(main()) From ea564b6a36c6d5ee8585d2fd44548ffae06c9655 Mon Sep 17 00:00:00 2001 From: Arjan Date: Fri, 3 Jul 2026 21:30:36 +0200 Subject: [PATCH 20/31] Drop obsolete include paths from .cproject Remove `${workspace_loc:/lib-hal/include}` and `${workspace_loc:/lib-properties/include}` from multiple Eclipse CDT `.cproject` files to align project include settings with current dependencies and avoid stale include search paths. --- gd32_dmx_usb_pro/.cproject | 1 - gd32_rdm_responder/.cproject | 1 - lib-configstore/.cproject | 3 --- lib-device/.cproject | 3 --- lib-display/.cproject | 1 - lib-displayudf/.cproject | 2 -- lib-dmx/.cproject | 2 -- lib-flashcode/.cproject | 4 ---- lib-pixel/.cproject | 3 --- lib-pixeldmx/.cproject | 3 --- lib-rdm/.cproject | 2 -- lib-rdmsensor/.cproject | 1 - lib-rdmsubdevice/.cproject | 1 - lib-widget/.cproject | 2 -- 14 files changed, 29 deletions(-) diff --git a/gd32_dmx_usb_pro/.cproject b/gd32_dmx_usb_pro/.cproject index c2fee85c..b314d266 100755 --- a/gd32_dmx_usb_pro/.cproject +++ b/gd32_dmx_usb_pro/.cproject @@ -130,7 +130,6 @@ @@ -350,7 +348,6 @@ - diff --git a/lib-rdm/.cproject b/lib-rdm/.cproject index f19d254a..c696228c 100644 --- a/lib-rdm/.cproject +++ b/lib-rdm/.cproject @@ -38,13 +38,11 @@