From feda8caab5f66956f75e70aba24a47f9e3407c59 Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Mon, 3 Aug 2026 13:35:34 +0530 Subject: [PATCH 1/4] QCLINUX: Revert "WORKAROUND: arm64: dts: qcom: monaco-evk: Enable Bluetooth support" This reverts commit ba349026e79209ce6e7817f9cb53f63ae48809c8. Signed-off-by: Wei Deng --- .../boot/dts/qcom/monaco-evk-common.dtsi | 42 ------------------- 1 file changed, 42 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi index 2434d1f9f58ba..c6714e0df6670 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-evk-common.dtsi @@ -16,7 +16,6 @@ ethernet0 = ðernet0; i2c1 = &i2c1; serial0 = &uart7; - serial1 = &uart2; serial2 = &uart6; }; @@ -208,29 +207,6 @@ pinctrl-0 = <&cam2_avdd_2v8_en_default>; pinctrl-names = "default"; }; - - vreg_dcin_12v: regulator-dcin-12v { - compatible = "regulator-fixed"; - - regulator-name = "VREG_DCIN_12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - - regulator-boot-on; - regulator-always-on; - }; - - vreg_wcn_3p3: regulator-wcn-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_WCN_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&vreg_dcin_12v>; - - regulator-boot-on; - }; }; &apps_rsc { @@ -967,24 +943,6 @@ }; }; -&uart2 { - status = "okay"; - - bluetooth: bluetooth { - compatible = "qcom,wcn6855-bt"; - max-speed = <3200000>; - - vddrfacmn-supply = <&vreg_wcn_3p3>; - vddaon-supply = <&vreg_wcn_3p3>; - vddwlcx-supply = <&vreg_wcn_3p3>; - vddwlmx-supply = <&vreg_wcn_3p3>; - vddbtcmx-supply = <&vreg_wcn_3p3>; - vddrfa0p8-supply = <&vreg_wcn_3p3>; - vddrfa1p2-supply = <&vreg_wcn_3p3>; - vddrfa1p8-supply = <&vreg_wcn_3p3>; - }; -}; - &uart6 { status = "okay"; }; From 4d3d7e33c9c3c7bd7435f82d9f1ff690bec2da81 Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Wed, 29 Jul 2026 07:55:18 +0530 Subject: [PATCH 2/4] FROMLIST: arm64: dts: qcom: monaco: Add compatible to the PCIe Root Port Add 'compatible = "pciclass,0604"' to the pcieport0 node in monaco.dtsi to allow the PCI subsystem to associate the DT node with the PCI-to-PCI bridge device. This is required for downstream DT nodes (such as M.2 connectors described as graph endpoints of the Root Port) to be matched to PCI devices. Link: https://lore.kernel.org/r/20260729-b4-monaco-evk-m2-v1-v2-1-0548e1dab760@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Wei Deng --- arch/arm64/boot/dts/qcom/monaco.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 7ecb1e4d1f824..ba93e05cc148d 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2446,6 +2446,7 @@ }; pcieport0: pcie@0 { + compatible = "pciclass,0604"; device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From a3b2b282d70f497cccee70f75c89c0fbcf676565 Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Wed, 29 Jul 2026 07:56:07 +0530 Subject: [PATCH 3/4] FROMLIST: arm64: dts: qcom: monaco: Add graph port/endpoint anchors to pcieport0 and uart2 Add empty graph port/endpoint nodes to pcieport0 and uart2 in monaco.dtsi so that board files can reference the endpoint labels (pcieport0_ep, uart2_ep) to describe connections to M.2 Key E connectors via remote-endpoint overrides. Link: https://lore.kernel.org/r/20260729-b4-monaco-evk-m2-v1-v2-2-0548e1dab760@oss.qualcomm.com/ Suggested-by: Konrad Dybcio Signed-off-by: Wei Deng --- arch/arm64/boot/dts/qcom/monaco.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index ba93e05cc148d..1a385c84f3113 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -1244,6 +1244,10 @@ power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; + + port { + uart2_ep: endpoint {}; + }; }; i2c3: i2c@98c000 { @@ -2455,6 +2459,10 @@ #size-cells = <2>; ranges; phys = <&pcie0_phy>; + + port { + pcieport0_ep: endpoint {}; + }; }; }; From afed08d409a2195baa213fdb7a9972dd9b00a923 Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Mon, 3 Aug 2026 13:36:34 +0530 Subject: [PATCH 4/4] FROMLIST: arm64: dts: qcom: monaco-evk: Describe the PCIe M.2 Key E connector The monaco EVK has a PCIe M.2 Mechanical Key E connector to connect wireless connectivity cards over PCIe and UART interfaces. Hence, describe the connector node and link it with the PCIe 0 Root Port and UART2 nodes through graph port/endpoint. The M.2 Key E connector is powered by a 3.3V fixed regulator (vreg_wcn_3p3) which is sourced from the board's 12V DC input rail (vreg_dcin_12v). Both regulators are always-on and are required by the pcie-m2-e-connector binding. Also add the serial1 = &uart2 alias, which is required for the Bluetooth serdev device to be enumerated on the UART2 interface. The graph endpoint anchors (pcieport0_ep, uart2_ep) referenced here are defined in monaco.dtsi (see "arm64: dts: qcom: monaco: Add graph port/endpoint anchors to pcieport0 and uart2"). Link: https://lore.kernel.org/r/20260729-b4-monaco-evk-m2-v1-v2-3-0548e1dab760@oss.qualcomm.com/ Signed-off-by: Wei Deng --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 71 +++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 56422ab42b27a..e98cd8306dde6 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -11,6 +11,42 @@ model = "Qualcomm Technologies, Inc. Monaco EVK"; compatible = "qcom,monaco-evk", "qcom,qcs8300"; + aliases { + serial1 = &uart2; + }; + + connector-3 { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <&vreg_wcn_3p3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcieport0_ep>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_uart_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&uart2_ep>; + }; + }; + }; + }; + /* This comes from a PMIC handled within the SAIL domain */ vreg_s2s: vreg-s2s { compatible = "regulator-fixed"; @@ -19,6 +55,33 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + vreg_dcin_12v: regulator-dcin-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_DCIN_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + regulator-boot-on; + regulator-always-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_dcin_12v>; + + regulator-boot-on; + }; +}; + +&pcieport0_ep { + remote-endpoint = <&m2_e_pcie_ep>; }; &sdhc_1 { @@ -32,3 +95,11 @@ status = "okay"; }; +&uart2 { + status = "okay"; +}; + +&uart2_ep { + remote-endpoint = <&m2_e_uart_ep>; +}; +