From 3061fd7246634d25efd76578d6642ed6f39597ca Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 23 Sep 2026 16:32:42 +0530 Subject: [PATCH 1/4] FROMLIST: arm64: dts: qcom: maili: Add support for cambistmclkcc and camcc Add the device nodes for the cambistmclkcc and camcc on Qualcomm Maili SoC. Signed-off-by: Taniya Das Signed-off-by: Nihal Kumar Gupta Link: https://lore.kernel.org/all/20260923-hawi-maili-camss-v1-11-cbbb42e534ef@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/maili.dtsi | 43 +++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi index 7c74d9e4834cd..69c827f3528b1 100644 --- a/arch/arm64/boot/dts/qcom/maili.dtsi +++ b/arch/arm64/boot/dts/qcom/maili.dtsi @@ -3,9 +3,11 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include #include #include #include +#include #include #include #include @@ -2040,6 +2042,25 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,maili-cambistmclkcc", + "qcom,kaanapali-cambistmclkcc"; + reg = <0x0 0x01760000 0x0 0x6000>; + + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + mmss_noc: interconnect@1780000 { compatible = "qcom,maili-mmss-noc"; reg = <0x0 0x01780000 0x0 0x5f800>; @@ -4637,6 +4658,28 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + camcc: clock-controller@956d000 { + compatible = "qcom,maili-camcc"; + reg = <0x0 0x0956d000 0x0 0x80000>; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + usb: usb@a600000 { compatible = "qcom,maili-dwc3", "qcom,snps-dwc3"; reg = <0x0 0x0a600000 0x0 0xfc100>; From 3be9b61b82e108a72146a9ec5ecb7f1c7675f515 Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Wed, 23 Sep 2026 16:32:43 +0530 Subject: [PATCH 2/4] FROMLIST: arm64: dts: qcom: maili: Add CAMSS and CSIPHY nodes for Maili Maili uses the same CAMSS IP as Hawi with five CSIPHY instances instead of six. Add CAMSS and CSIPHY nodes reusing the Hawi-compatible driver. 5 x CSIPHY 3 x TPG 3 x CSID 2 x CSID Lite 3 x IFE 2 x IFE Lite Acked-by: Konrad Dybcio Signed-off-by: Nihal Kumar Gupta Link: https://lore.kernel.org/all/20260923-hawi-maili-camss-v1-12-cbbb42e534ef@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/maili.dtsi | 412 ++++++++++++++++++++++++++++ 1 file changed, 412 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi index 69c827f3528b1..e027d32b7e9cd 100644 --- a/arch/arm64/boot/dts/qcom/maili.dtsi +++ b/arch/arm64/boot/dts/qcom/maili.dtsi @@ -539,6 +539,28 @@ }; }; + csiphy_mxc_opp_table: opp-table-mxc { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs_d1_1>, + <&rpmhpd_opp_low_svs_d1_1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d0>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_nom>; + }; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <2>; @@ -4658,6 +4680,396 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + camss: isp@9253000 { + compatible = "qcom,maili-camss", "qcom,hawi-camss"; + + reg = <0x0 0x09253000 0x0 0x5e80>, + <0x0 0x09263000 0x0 0x5e80>, + <0x0 0x09273000 0x0 0x5e80>, + <0x0 0x092d3000 0x0 0x3880>, + <0x0 0x092e7000 0x0 0x3880>, + <0x0 0x093fd000 0x0 0x400>, + <0x0 0x093fe000 0x0 0x400>, + <0x0 0x093ff000 0x0 0x400>, + <0x0 0x09151000 0x0 0x20000>, + <0x0 0x09171000 0x0 0x20000>, + <0x0 0x09191000 0x0 0x20000>, + <0x0 0x092dc000 0x0 0x6800>, + <0x0 0x092f0000 0x0 0x6800>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csitpg0", + "csitpg1", + "csitpg2", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_DCD_XO_CLK>, + <&camcc CAM_CC_CAM_TOP_AHB_CLK>, + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>, + <&camcc CAM_CC_TITAN_MNOC_HF_CLK>, + <&camcc CAM_CC_TITAN_MNOC_SF_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_CLK>, + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_CLK>, + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_CLK>, + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>; + clock-names = "camnoc_nrt_axi", + "camnoc_rt_axi", + "camnoc_dcd_xo", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_mnoc_hf", + "cpas_mnoc_sf", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csid_csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "qdss_debug_xo"; + + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc"; + + iommus = <&apps_smmu 0x1800 0x00>; + + power-domains = <&camcc CAM_CC_TFE_0_GDSC>, + <&camcc CAM_CC_TFE_1_GDSC>, + <&camcc CAM_CC_TFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + camss_csiphy0_inep: endpoint { + remote-endpoint = <&csiphy0_out_ep>; + }; + }; + + port@1 { + reg = <1>; + + camss_csiphy1_inep: endpoint { + remote-endpoint = <&csiphy1_out_ep>; + }; + }; + + port@2 { + reg = <2>; + + camss_csiphy2_inep: endpoint { + remote-endpoint = <&csiphy2_out_ep>; + }; + }; + + port@3 { + reg = <3>; + + camss_csiphy3_inep: endpoint { + remote-endpoint = <&csiphy3_out_ep>; + }; + }; + + port@4 { + reg = <4>; + + camss_csiphy4_inep: endpoint { + remote-endpoint = <&csiphy4_out_ep>; + }; + }; + }; + }; + + csiphy0: phy@9523000 { + compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy"; + reg = <0x0 0x09523000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy0_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy0_out_ep: endpoint { + remote-endpoint = <&camss_csiphy0_inep>; + }; + }; + }; + }; + + csiphy1: phy@9525000 { + compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy"; + reg = <0x0 0x09525000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy1_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy1_out_ep: endpoint { + remote-endpoint = <&camss_csiphy1_inep>; + }; + }; + }; + }; + + csiphy2: phy@9527000 { + compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy"; + reg = <0x0 0x09527000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy2_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy2_out_ep: endpoint { + remote-endpoint = <&camss_csiphy2_inep>; + }; + }; + }; + }; + + csiphy3: phy@9529000 { + compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy"; + reg = <0x0 0x09529000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy3_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy3_out_ep: endpoint { + remote-endpoint = <&camss_csiphy3_inep>; + }; + }; + }; + }; + + csiphy4: phy@952b000 { + compatible = "qcom,maili-csi2-phy", "qcom,kaanapali-csi2-phy"; + reg = <0x0 0x0952b000 0x0 0x2000>; + + clocks = <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>; + clock-names = "core", + "timer", + "ahb"; + + interrupts = ; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>, + <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + power-domain-names = "top", + "mmcx", + "mx"; + + operating-points-v2 = <&csiphy_mxc_opp_table>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy4_in_ep: endpoint { + }; + }; + + port@1 { + reg = <1>; + + csiphy4_out_ep: endpoint { + remote-endpoint = <&camss_csiphy4_inep>; + }; + }; + }; + }; + camcc: clock-controller@956d000 { compatible = "qcom,maili-camcc"; reg = <0x0 0x0956d000 0x0 0x80000>; From 4dac264ce0c9254d121caf87346a10b96a558bf0 Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Wed, 23 Sep 2026 16:32:44 +0530 Subject: [PATCH 3/4] FROMLIST: arm64: dts: qcom: maili: Add camera MCLK pinctrl for Maili Define pinctrl definitions to enable camera master clocks on Maili. Reviewed-by: Konrad Dybcio Signed-off-by: Nihal Kumar Gupta Link: https://lore.kernel.org/all/20260923-hawi-maili-camss-v1-13-cbbb42e534ef@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/maili.dtsi | 42 +++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi index e027d32b7e9cd..bd9181031b37c 100644 --- a/arch/arm64/boot/dts/qcom/maili.dtsi +++ b/arch/arm64/boot/dts/qcom/maili.dtsi @@ -6348,6 +6348,48 @@ bias-disable; }; + mclk0_default: mclk0-default-state { + pins = "gpio95"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + mclk1_default: mclk1-default-state { + pins = "gpio90"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + mclk2_default: mclk2-default-state { + pins = "gpio91"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + mclk3_default: mclk3-default-state { + pins = "gpio92"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + mclk4_default: mclk4-default-state { + pins = "gpio93"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + mclk5_default: mclk5-default-state { + pins = "gpio94"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; sram@14680000 { From 5f68e103fbdf11fed5233067abaca0d3a2c2d7c1 Mon Sep 17 00:00:00 2001 From: Nihal Kumar Gupta Date: Wed, 23 Sep 2026 16:32:45 +0530 Subject: [PATCH 4/4] FROMLIST: arm64: dts: qcom: maili-mtp: Enable S5KJN5 camera for Maili MTP Qualcomm Maili MTP carries a Samsung S5KJN5 rear camera sensor on QUP I2C9, connected to CSIPHY2 via 4-lane CSI-2 D-PHY. Reviewed-by: Konrad Dybcio Signed-off-by: Nihal Kumar Gupta Link: https://lore.kernel.org/all/20260923-hawi-maili-camss-v1-14-cbbb42e534ef@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/maili-mtp.dts | 64 ++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/maili-mtp.dts b/arch/arm64/boot/dts/qcom/maili-mtp.dts index b7ed4a88a6900..a7d5e007155d9 100644 --- a/arch/arm64/boot/dts/qcom/maili-mtp.dts +++ b/arch/arm64/boot/dts/qcom/maili-mtp.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -861,6 +862,28 @@ }; }; +&camss { + status = "okay"; +}; + +&camss_csiphy2_inep { + data-lanes = <1 2 3 4>; +}; + +&csiphy2 { + vdda-0p9-supply = <&vreg_l1d_0p9>; + vdda-1p2-supply = <&vreg_l3g_1p2>; + + status = "okay"; +}; + +&csiphy2_in_ep { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&s5kjn5_ep>; +}; + &i2c3 { status = "okay"; @@ -888,6 +911,40 @@ }; }; +&i2c9 { + clock-frequency = <400000>; + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + status = "okay"; + + camera@10 { + compatible = "samsung,s5kjn5"; + reg = <0x10>; + + reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&mclk2_default &cam2_reset_default>; + pinctrl-names = "default"; + + clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + assigned-clocks = <&cambistmclkcc CAM_BIST_MCLK_CC_MCLK2_CLK>; + assigned-clock-rates = <19200000>; + + afvdd-supply = <&vreg_l5m_2p8>; + vdda-supply = <&vreg_l7m_2p2>; + vddd-supply = <&vreg_l1m_1p0>; + vddio-supply = <&vreg_l4n_1p8>; + vddio1p2-supply = <&vreg_l2n_1p2>; + + port { + s5kjn5_ep: endpoint { + link-frequencies = /bits/ 64 <1248000000>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csiphy2_in_ep>; + }; + }; + }; +}; + &lpass_vamacro { pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; @@ -1099,6 +1156,13 @@ <144 2>, /* CXM UART */ <211 1>; /* NFC Secure IO */ + cam2_reset_default: cam2-reset-default-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio161"; function = "gpio";