From fb3d57ea2471182f79ca094504aa14d43cdeeb8d Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 21 Sep 2026 16:28:12 +0530 Subject: [PATCH 1/6] FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add qcs8300 16 GT/s PHY The QCS8300 16 GT/s x4 QMP PCIe PHY was previously described using only the qcom,sa8775p-qmp-gen4x4-pcie-phy compatible, since no QCS8300-specific compatible existed for this PHY. This was a mistake, as it left the PHY undocumented as QCS8300 hardware and indistinguishable from SA8775P in the binding. Correct this by documenting a dedicated "qcom,qcs8300-qmp-gen4x4-pcie-phy" compatible, with "qcom,sa8775p-qmp-gen4x4-pcie-phy" listed as its fallback compatible. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-1-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 87 ++++++++++--------- 1 file changed, 46 insertions(+), 41 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index b353b7bfb839c..34d3a714716bb 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -15,47 +15,52 @@ description: properties: compatible: - enum: - - qcom,eliza-qmp-gen3x1-pcie-phy - - qcom,eliza-qmp-gen3x2-pcie-phy - - qcom,glymur-qmp-gen4x2-pcie-phy - - qcom,glymur-qmp-gen5x4-pcie-phy - - qcom,hawi-qmp-gen3x2-pcie-phy - - qcom,hawi-qmp-gen4x1-pcie-phy - - qcom,kaanapali-qmp-gen3x2-pcie-phy - - qcom,qcs615-qmp-gen3x1-pcie-phy - - qcom,qcs8300-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x4-pcie-phy - - qcom,sar2130p-qmp-gen3x2-pcie-phy - - qcom,sc8180x-qmp-pcie-phy - - qcom,sc8280xp-qmp-gen3x1-pcie-phy - - qcom,sc8280xp-qmp-gen3x2-pcie-phy - - qcom,sc8280xp-qmp-gen3x4-pcie-phy - - qcom,sdm845-qhp-pcie-phy - - qcom,sdm845-qmp-pcie-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sdx65-qmp-gen4x2-pcie-phy - - qcom,sm8150-qmp-gen3x1-pcie-phy - - qcom,sm8150-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8350-qmp-gen3x1-pcie-phy - - qcom,sm8350-qmp-gen3x2-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy - - qcom,sm8475-qmp-gen3x1-pcie-phy - - qcom,sm8550-qmp-gen3x2-pcie-phy - - qcom,sm8550-qmp-gen4x2-pcie-phy - - qcom,sm8650-qmp-gen3x2-pcie-phy - - qcom,sm8650-qmp-gen4x2-pcie-phy - - qcom,sm8750-qmp-gen3x2-pcie-phy - - qcom,x1e80100-qmp-gen3x2-pcie-phy - - qcom,x1e80100-qmp-gen4x2-pcie-phy - - qcom,x1e80100-qmp-gen4x4-pcie-phy - - qcom,x1e80100-qmp-gen4x8-pcie-phy - - qcom,x1p42100-qmp-gen4x4-pcie-phy + oneOf: + - items: + - enum: + - qcom,qcs8300-qmp-gen4x4-pcie-phy + - const: qcom,sa8775p-qmp-gen4x4-pcie-phy + - enum: + - qcom,eliza-qmp-gen3x1-pcie-phy + - qcom,eliza-qmp-gen3x2-pcie-phy + - qcom,glymur-qmp-gen4x2-pcie-phy + - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,hawi-qmp-gen3x2-pcie-phy + - qcom,hawi-qmp-gen4x1-pcie-phy + - qcom,kaanapali-qmp-gen3x2-pcie-phy + - qcom,qcs615-qmp-gen3x1-pcie-phy + - qcom,qcs8300-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x4-pcie-phy + - qcom,sar2130p-qmp-gen3x2-pcie-phy + - qcom,sc8180x-qmp-pcie-phy + - qcom,sc8280xp-qmp-gen3x1-pcie-phy + - qcom,sc8280xp-qmp-gen3x2-pcie-phy + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy + - qcom,sdx65-qmp-gen4x2-pcie-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8150-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy + - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8350-qmp-gen3x2-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy + - qcom,sm8475-qmp-gen3x1-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen4x2-pcie-phy + - qcom,sm8650-qmp-gen3x2-pcie-phy + - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,sm8750-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen3x2-pcie-phy + - qcom,x1e80100-qmp-gen4x2-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1e80100-qmp-gen4x8-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy reg: minItems: 1 From d0d24fa8260722d09ac056522aa547e3c04aba15 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 21 Sep 2026 16:28:13 +0530 Subject: [PATCH 2/6] FROMLIST: dt-bindings: PCI: qcom-ep: Add QCS8300 compatible The QCS8300 PCIe Endpoint controller is compatible with the SA8775P PCIe Endpoint controller and uses the same programming model. Document the QCS8300 compatible string and its fallback to the SA8775P compatible. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-2-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index bed9a40b186bc..7f9a0bc958d1b 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -13,10 +13,15 @@ properties: compatible: oneOf: - enum: + - qcom,qcs8300-pcie-ep - qcom,sa8775p-pcie-ep - qcom,sar2130p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep + - items: + - enum: + - qcom,qcs8300-pcie-ep + - const: qcom,sa8775p-pcie-ep - items: - const: qcom,sdx65-pcie-ep - const: qcom,sdx55-pcie-ep From 8a1f3f17b78ea70b986e1979baf1ad3080e79ce0 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 21 Sep 2026 16:28:14 +0530 Subject: [PATCH 3/6] FROMLIST: phy: qcom: qmp-pcie: Add endpoint PHY configuration for QCS8300 Monaco supports PCIe Endpoint mode on both PCIe controllers. Reuse the existing SA8775P Endpoint PHY programming for the 16 GT/s x2 PHY and add a new 16 GT/s x4 Endpoint PHY configuration with the required RX tuning parameters. This allows both Monaco PCIe controllers to operate reliably in Endpoint mode. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-3-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 105 +++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index da83358c97ead..cf169d7cbd92b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -1231,6 +1231,58 @@ static const struct qmp_phy_init_tbl qcs8300_qmp_gen4x2_pcie_rx_alt_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), }; +static const struct qmp_phy_init_tbl qcs8300_qmp_gen4x4_pcie_rx_alt_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9b), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0xd2), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9b), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xd2), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08), +}; + static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -4583,6 +4635,56 @@ static const struct qmp_phy_cfg qcs8300_qmp_gen4x2_pciephy_cfg = { .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), }, + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { + .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, + .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), + .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), + .pcs = sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl, + .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl), + }, + + .reset_list = sdm845_pciephy_reset_l, + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = pciephy_v5_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, +}; + +static const struct qmp_phy_cfg qcs8300_qmp_gen4x4_pciephy_cfg = { + .lanes = 4, + .offsets = &qmp_pcie_offsets_v5_30, + + .tbls = { + .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl, + .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl), + .tx = sa8775p_qmp_gen4_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl), + .rx = qcs8300_qmp_gen4x4_pcie_rx_alt_tbl, + .rx_num = ARRAY_SIZE(qcs8300_qmp_gen4x4_pcie_rx_alt_tbl), + .pcs = sa8775p_qmp_gen4_pcie_pcs_alt_tbl, + .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_alt_tbl), + .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl), + }, + + .tbls_rc = &(const struct qmp_phy_cfg_tbls) { + .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl, + .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl), + .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), + }, + + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { + .serdes = sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl, + .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl), + .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), + }, + .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -6411,6 +6513,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy", .data = &qcs8300_qmp_gen4x2_pciephy_cfg, + }, { + .compatible = "qcom,qcs8300-qmp-gen4x4-pcie-phy", + .data = &qcs8300_qmp_gen4x4_pciephy_cfg, }, { .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy", .data = &sa8775p_qmp_gen4x2_pciephy_cfg, From 9995d9f5d6d193c534bbe79381d372f55ef33eaa Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 21 Sep 2026 16:28:15 +0530 Subject: [PATCH 4/6] FROMLIST: PCI: qcom-ep: Set initial interconnect bandwidth before enabling clocks Some Qualcomm platforms require the interconnect bandwidth constraints to be set before enabling the interconnect clocks, otherwise some clocks get stuck in the off state. Move the icc_set_bw() call before clk_bulk_prepare_enable() so the bandwidth vote is in place first. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-4-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 34 +++++++++++------------ 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 56184e6ca6e69..0b23d7181539d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -331,9 +331,23 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) struct dw_pcie *pci = &pcie_ep->pci; int ret; + /* + * Some Qualcomm platforms require interconnect bandwidth constraints + * to be set before enabling interconnect clocks. + * + * Set an initial peak bandwidth corresponding to single-lane Gen 1 + * for the pcie-mem path. + */ + ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); + if (ret) { + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", + ret); + return ret; + } + ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); if (ret) - return ret; + goto err_disable_icc; ret = qcom_pcie_ep_core_reset(pcie_ep); if (ret) @@ -351,28 +365,14 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) if (ret) goto err_phy_exit; - /* - * Some Qualcomm platforms require interconnect bandwidth constraints - * to be set before enabling interconnect clocks. - * - * Set an initial peak bandwidth corresponding to single-lane Gen 1 - * for the pcie-mem path. - */ - ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); - if (ret) { - dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", - ret); - goto err_phy_off; - } - return 0; -err_phy_off: - phy_power_off(pcie_ep->phy); err_phy_exit: phy_exit(pcie_ep->phy); err_disable_clk: clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks); +err_disable_icc: + icc_set_bw(pcie_ep->icc_mem, 0, 0); return ret; } From 68d122ec174c6d7c098b861d258e8161f0d60a34 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 21 Sep 2026 16:28:16 +0530 Subject: [PATCH 5/6] FROMLIST: arm64: qcom: monaco: Fix pcie1_phy compatible to list qcs8300 first The existing pcie1_phy node only listed qcom,sa8775p-qmp-gen4x4-pcie-phy compatible, since no QCS8300-specific compatible was documented for this PHY at the time. Now that qcom,qcs8300-qmp-gen4x4-pcie-phy is documented, list it first with qcom,sa8775p-qmp-gen4x4-pcie-phy as its fallback, matching the order used by the pcie0_ep and pcie1_ep nodes. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-5-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/monaco.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index cfe39f923224f..d7d135e87a8c7 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2597,7 +2597,8 @@ }; pcie1_phy: phy@1c14000 { - compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + compatible = "qcom,qcs8300-qmp-gen4x4-pcie-phy", + "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg = <0x0 0x01c14000 0x0 0x4000>; clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, From 20f8ccf6a8f0a1121afaed6cd2c47b0171e7fe31 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 21 Sep 2026 16:28:17 +0530 Subject: [PATCH 6/6] FROMLIST: arm64: qcom: monaco: Add PCIe Endpoint nodes Monaco has two PCIe controllers that can operate in Endpoint mode. Describe the Endpoint nodes for both controllers, including their register regions, clocks, interrupts, interconnects, IOMMU mappings, resets, power domains, and PHY connections etc. Link: https://lore.kernel.org/r/20260921-monaco_ep-v1-6-63c5282fb0db@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/monaco.dtsi | 144 +++++++++++++++++++++++++++ 1 file changed, 144 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index d7d135e87a8c7..8f2f0941383aa 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2405,6 +2405,55 @@ }; }; + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,qcs8300-pcie-ep", "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x1fe00000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc GCC_PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + pinctrl-0 = <&pcie0_ep_default_state>; + pinctrl-names = "default"; + num-lanes = <2>; + linux,pci-domain = <0>; + + status = "disabled"; + }; + pcie0_phy: phy@1c04000 { compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; reg = <0x0 0x01c04000 0x0 0x2000>; @@ -2596,6 +2645,55 @@ }; }; + pcie1_ep: pcie-ep@1c10000 { + compatible = "qcom,qcs8300-pcie-ep", "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x1fe00000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x0080 0x7f>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc GCC_PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + pinctrl-0 = <&pcie1_ep_default_state>; + pinctrl-names = "default"; + num-lanes = <4>; + linux,pci-domain = <1>; + + status = "disabled"; + }; + pcie1_phy: phy@1c14000 { compatible = "qcom,qcs8300-qmp-gen4x4-pcie-phy", "qcom,sa8775p-qmp-gen4x4-pcie-phy"; @@ -6225,6 +6323,52 @@ #interrupt-cells = <2>; wakeup-parent = <&pdc>; + pcie0_ep_default_state: pcie0-ep-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + output-low; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + + pcie1_ep_default_state: pcie1-ep-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + output-low; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + cam0_default: cam0-default-state { pins = "gpio67"; function = "cam_mclk";