The current implementation uses a compact memory organization suitable for a small RTL processor and simulation environment.
The design currently contains:
- Instruction memory
- Register/data storage
- Program Counter
- Instruction fetch path
- Register read/write paths
The current implementation is intentionally small and uses a 16-entry instruction address space.
This document describes the current implemented memory organization, not a future expanded memory subsystem.
The current processor uses the following organization:
flowchart TB
PC["Program Counter<br/>4-bit"]
IM["Instruction Memory<br/><br/>Depth: 16<br/>Width: 16 bits"]
DEC["Instruction Decoder"]
RF["Register File<br/><br/>16 Registers<br/>16 bits / register"]
ALU["ALU<br/>16-bit"]
WB["Register File<br/>Write-back"]
PC -->|Instruction Address| IM
IM -->|16-bit Instruction| DEC
DEC -->|Register Addresses| RF
RF -->|Operands| ALU
ALU -->|Result| WB
The instruction memory stores the program executed by the processor.
Current organization:
| Parameter | Value |
|---|---|
| Data width | 16 bits |
| Memory depth | 16 |
| Address width | 4 bits |
| Address range | 0–15 |
| Instruction width | 16 bits |
Therefore:
Instruction Memory = 16 × 16 bits
The Program Counter selects one of the 16 instruction locations.
The current Program Counter is 4 bits wide.
PC[3:0]
This provides:
0000 → Address 0
0001 → Address 1
0010 → Address 2
...
1111 → Address 15
The complete address range is therefore:
0x0 – 0xF
The current implementation also supports sequential PC wrapping:
PC = 15
|
| PC + 1
v
PC = 0
This behavior is explicitly verified.
Instruction fetch follows the path:
Program Counter
|
v
Instruction Memory
|
v
16-bit Instruction
|
v
Instruction Decoder
For example:
PC = 4
selects instruction memory location:
Instruction Memory[4]
The resulting 16-bit instruction is then decoded.
The instruction memory is directly associated with the Program Counter.
Normal sequential execution:
PC = N
|
v
Fetch Instruction[N]
|
v
Execute
|
v
PC = N + 1
For a JMP instruction:
PC = N
|
v
Fetch JMP
|
v
Decode Target
|
v
PC = Target
For HALT:
PC = N
|
v
Fetch HALT
|
v
PC remains N
The current processor contains 16 registers.
Number of registers : 16
Register width : 16 bits
Address width : 4 bits
Organization:
+-------+----------------+
| Reg | Data |
+-------+----------------+
| R0 | 16 bits |
| R1 | 16 bits |
| R2 | 16 bits |
| R3 | 16 bits |
| R4 | 16 bits |
| R5 | 16 bits |
| R6 | 16 bits |
| R7 | 16 bits |
| R8 | 16 bits |
| R9 | 16 bits |
| R10 | 16 bits |
| R11 | 16 bits |
| R12 | 16 bits |
| R13 | 16 bits |
| R14 | 16 bits |
| R15 | 16 bits |
+-------+----------------+
Total register storage:
16 × 16 = 256 bits
The register file provides two source register selections.
RS1 → Source Operand 1
RS2 → Source Operand 2
Conceptually:
+----------------+
RS1 --------->| |----> Operand A
| Register File |
RS2 --------->| |----> Operand B
| |
+----------------+
This allows instructions such as ADD and SUB to access two source registers.
Example:
ADD R2, R0, R1
uses:
RS1 = R0
RS2 = R1
RD = R2
Instructions that produce a register result use:
ALU Result
|
v
Write Data
|
v
Register File
|
v
RD
The write occurs only when the corresponding control signal enables register write-back.
The verification environment explicitly checks that ALU operations write only the selected destination register.
Every register stores 16 bits.
Example:
R5 = 16'b1010_1100_0101_0011
or:
R5 = 16'hAC53
The datapath therefore maintains 16-bit values throughout normal ALU execution.
The current processor does not implement a separate general-purpose load/store data-memory subsystem as part of the verified instruction set.
The current implemented ISA contains:
ADD
SUB
AND
OR
XOR
NOT
SHL
SHR
SLT
EQ
MOV
NOP
JMP
HALT
There are currently no verified:
LOAD
STORE
instructions.
Therefore, the current memory architecture should be understood as:
Instruction Memory
+
Register File
rather than a conventional CPU with separate instruction RAM and data RAM interfaces.
The current instruction address space is limited by the 4-bit Program Counter.
PC width = 4 bits
Therefore:
2^4 = 16
instruction addresses are available.
Address map:
| Address | Purpose |
|---|---|
0x0 |
Instruction 0 |
0x1 |
Instruction 1 |
0x2 |
Instruction 2 |
0x3 |
Instruction 3 |
0x4 |
Instruction 4 |
0x5 |
Instruction 5 |
0x6 |
Instruction 6 |
0x7 |
Instruction 7 |
0x8 |
Instruction 8 |
0x9 |
Instruction 9 |
0xA |
Instruction 10 |
0xB |
Instruction 11 |
0xC |
Instruction 12 |
0xD |
Instruction 13 |
0xE |
Instruction 14 |
0xF |
Instruction 15 |
A normal ALU instruction follows:
1. PC selects instruction.
2. Instruction is fetched.
3. Instruction fields are decoded.
4. Register file supplies operands.
5. ALU performs operation.
6. Result is written to RD.
7. PC advances.
No external data-memory transaction is required for these instructions.
JMP directly affects instruction-memory addressing through the Program Counter.
Example:
PC = 0
|
v
JMP 7
|
v
PC = 7
|
v
Instruction Memory[7]
The verification environment tests JMP targets across the available instruction address range.
Verified cases include:
Forward jump
Backward jump
Jump to zero
Self-loop
Jump chains
Targets 1–15
When HALT is reached, normal instruction progression stops.
The processor does not continue fetching subsequent instructions.
Conceptually:
HALT
|
v
+--------------+
| Hold PC |
| Hold State |
+--------------+
RESET can restart processor execution.
The verification environment explicitly tests:
HALT
RESET while HALTed
RESET initializes the processor's architectural execution state.
The verified reset behavior includes:
PC = 0
Flags = 0
RESET also prevents write-back of the instruction being processed during reset.
The instruction memory itself is not treated as architectural state that is rewritten by normal RESET operation.
When the processor is stalled or disabled:
PC
does not advance.
Consequently, the processor remains associated with the same instruction address until execution resumes.
Conceptually:
EN = 0
PC = N
|
+----> Instruction[N]
|
v
Hold State
When:
EN = 1
normal execution resumes.
The verification environment tests multiple consecutive stall cycles and alternating enable states.
The current verification environment checks the processor's memory-addressing behavior through CPU-level control-flow tests.
Verified cases include:
0 → 1 → 2 → ... → 15
15 → 0
0 → target
0 → 7 → 2 → 15
PC remains constant
PC → 0
PC remains constant while disabled
The current architecture can be summarized as:
flowchart TB
IM["Instruction Memory<br/><br/>16 × 16-bit"]
INSTR["Instruction"]
DEC["Decoder"]
RF["Register File<br/><br/>16 × 16-bit"]
OPERANDS["16-bit<br/>Operands"]
ALU["ALU<br/>16-bit"]
RESULT["16-bit Result"]
WB["Register Write-back"]
IM --> INSTR
INSTR --> DEC
DEC --> RF
RF --> OPERANDS
OPERANDS --> ALU
ALU --> RESULT
RESULT --> WB
Possible future extensions include:
4-bit PC
↓
8-bit PC
↓
16-bit PC
with corresponding increases in instruction memory depth.
A future ISA could introduce:
LOAD
STORE
and a dedicated data-memory interface.
Peripheral registers could eventually occupy defined memory addresses.
Separate instruction and data interfaces could be introduced:
CPU
/ \
/ \
v v
Instruction Data
Memory Memory
Future pipelined versions could introduce instruction/data access stages and associated memory interfaces.