Skip to content

instruction-set.md

Latest commit

 

History

History
829 lines (563 loc) · 9.89 KB

instruction-set.md

File metadata and controls

829 lines (563 loc) · 9.89 KB
Raw

Instruction Set Architecture

1. Overview

It uses a fixed-width 16-bit instruction format.

Each instruction contains four 4-bit fields:

15            12 11             8 7             4 3             0
+---------------+----------------+---------------+---------------+
|    OPCODE     |       RD       |      RS2      |      RS1      |
+---------------+----------------+---------------+---------------+
     4 bits           4 bits           4 bits           4 bits

The opcode determines the operation performed by the processor.

The register fields identify the destination and source registers where applicable.

2. Opcode Map

The current processor implements 14 instructions.

Opcode Instruction Type Description
0000 ADD ALU Add two operands
0001 SUB ALU Subtract two operands
0010 AND ALU Bitwise AND
0011 OR ALU Bitwise OR
0100 XOR ALU Bitwise XOR
0101 NOT ALU Bitwise NOT
0110 SHL ALU Logical left shift
0111 SHR ALU Logical right shift
1000 SLT ALU Set if less than
1001 EQ ALU Equality comparison
1010 MOV Data Move operand
1011 RESERVED — Reserved opcode
1100 RESERVED — Reserved opcode
1101 NOP Control No operation
1110 JMP Control Jump to target
1111 HALT Control Halt execution

Coverage

Implemented instructions : 14 / 14
Instruction coverage      : 100%
Reserved opcodes          : 2

3. Register Fields

The processor contains 16 registers:

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15

Each register is 16 bits wide.

A register is selected using a 4-bit register address:

0000 → R0
0001 → R1
0010 → R2
...
1111 → R15

4. ALU Instructions

4.1 ADD

Opcode

0000

Operation

RD = RS1 + RS2

Conceptually:

R[RD] ← R[RS1] + R[RS2]

Example:

ADD R2, R0, R1

Encoding:

0000 0010 0001 0000

0x0210

The ADD operation can update the relevant status flags.

The verification environment explicitly tests:

  • Normal addition
  • Carry-out
  • Zero result
  • Negative result
  • Signed overflow
  • Boundary values
  • Walking-bit patterns
  • Random operands

4.2 SUB

Opcode

0001

Operation

RD = RS1 - RS2

Conceptually:

R[RD] ← R[RS1] - R[RS2]

Example:

SUB R2, R0, R1

Encoding:

0001 0010 0001 0000

0x1210

SUB verification includes:

  • Normal subtraction
  • Borrow cases
  • Zero result
  • Negative result
  • Signed overflow
  • Boundary values
  • Random operands

4.3 AND

Opcode

0010

Operation

RD = RS1 & RS2

Example:

AND R2, R0, R1

4.4 OR

Opcode

0011

Operation

RD = RS1 | RS2

Example:

OR R2, R0, R1

4.5 XOR

Opcode

0100

Operation

RD = RS1 ^ RS2

Example:

XOR R2, R0, R1

4.6 NOT

Opcode

0101

Operation

RD = ~RS1

The operation performs a bitwise inversion of the first source operand.

Example:

NOT R2, R0

5. Shift Instructions

5.1 SHL

Opcode

0110

Operation

RD = RS1 << RS2

The current implementation uses the relevant lower bits of the shift operand.

The verification environment tests all shift amounts:

0 through 15

Coverage:

SHL amounts : 16 / 16 = 100%

Example:

SHL R2, R0, R1

Encoding:

0110 0010 0001 0000

0x6210

5.2 SHR

Opcode

0111

Operation

RD = RS1 >> RS2

The verification environment tests all shift amounts from 0 through 15.

Coverage:

SHR amounts : 16 / 16 = 100%

Example:

SHR R2, R0, R1

Encoding:

0111 0010 0001 0000

0x7210

6. Comparison Instructions

6.1 SLT

Opcode

1000

Operation

RD = (RS1 < RS2) ? 1 : 0

The result is:

0x0001

when the comparison is true, and:

0x0000

when the comparison is false.

Both true and false comparison cases are included in functional coverage.

6.2 EQ

Opcode

1001

Operation

RD = (RS1 == RS2) ? 1 : 0

Result:

0x0001 → equal
0x0000 → not equal

Both equality outcomes are covered by the verification environment.

7. MOV

Opcode

1010

Operation

RD = RS1

Conceptually:

R[RD] ← R[RS1]

Example:

MOV R2, R0

The source value is copied to the destination register.

8. Reserved Opcodes

Two opcode values are currently reserved:

1011
1100

These opcodes do not represent implemented instructions.

The processor treats them safely as operations that do not produce unintended register writes.

The verification environment explicitly tests both reserved opcode values with multiple register-field combinations.

Coverage:

Reserved opcodes tested : 1011 / 1100

9. NOP

Opcode

1101

NOP means No Operation.

No architectural register update is performed.

Conceptually:

No operation

The verification environment confirms that NOP does not modify:

Registers
Flags

The Program Counter continues according to normal processor control.

10. JMP

Opcode

1110

JMP changes the normal sequential program flow.

Instead of continuing with:

PC + 1

the processor loads the jump target defined by the current instruction encoding.

The verification environment tests:

  • Forward jumps
  • Backward jumps
  • Jump to address 0
  • Self-loop
  • Jump chains
  • All targets from 1 through 15
  • Ignored non-target instruction bits

Example control-flow sequence:

PC 0
 |
 +---- JMP 7
          |
          v
         PC 7
          |
          +---- JMP 2
                   |
                   v
                  PC 2

11. HALT

Opcode

1111

HALT stops normal processor execution.

When the processor reaches HALT, the Program Counter remains frozen.

The verification environment confirms that HALT freezes:

PC
Registers
Flags

HALT is also tested with execution enabled and disabled.

HALT at address zero is separately verified.

12. Status Flags

The processor currently uses four status flags.

Flag Name Description
CF Carry Indicates carry/no-borrow condition
ZF Zero Indicates zero result
NF Negative Indicates negative result
VF Overflow Indicates signed arithmetic overflow

12.1 Carry Flag

For addition, CF represents carry-out from the most significant bit.

For subtraction, the implementation verifies the corresponding no-borrow/carry convention.

The verification environment includes dedicated carry and borrow tests.

12.2 Zero Flag

ZF indicates whether the resulting ALU value is zero.

Result = 0 → ZF = 1
Result ≠ 0 → ZF = 0

12.3 Negative Flag

NF reflects the sign bit of the 16-bit result.

Result[15] = 1 → NF = 1
Result[15] = 0 → NF = 0

12.4 Overflow Flag

VF indicates signed arithmetic overflow.

The verification environment checks overflow for both:

ADD
SUB

including signed boundary cases.

13. Instruction Examples

ADD

Instruction:
ADD R2, R0, R1

Encoding:
0000 0010 0001 0000

Hex:
0x0210

SUB

Instruction:
SUB R2, R0, R1

Encoding:
0001 0010 0001 0000

Hex:
0x1210

SHL

Instruction:
SHL R2, R0, R1

Encoding:
0110 0010 0001 0000

Hex:
0x6210

SHR

Instruction:
SHR R2, R0, R1

Encoding:
0111 0010 0001 0000

Hex:
0x7210

14. Instruction Categories

The current ISA can be grouped into four functional categories.

Arithmetic

ADD
SUB

Logical / Bit Manipulation

AND
OR
XOR
NOT
SHL
SHR

Comparison / Data Movement

SLT
EQ
MOV

Control

NOP
JMP
HALT

Reserved:

1011
1100

15. ISA Verification Coverage

The current verification environment achieves complete instruction coverage for the implemented ISA.

Instruction Coverage
====================

ADD   : PASS
SUB   : PASS
AND   : PASS
OR    : PASS
XOR   : PASS
NOT   : PASS
SHL   : PASS
SHR   : PASS
SLT   : PASS
EQ    : PASS
MOV   : PASS
NOP   : PASS
JMP   : PASS
HALT  : PASS

Total:
14 / 14 = 100%

Register-field coverage:

Destination registers : 16 / 16
RS1 registers         : 16 / 16
RS2 registers         : 16 / 16

Shift coverage:

SHL:
0–15 → 16 / 16

SHR:
0–15 → 16 / 16

16. ISA Status

The current instruction set provides the basic functionality required by the verified processor:

16-bit arithmetic
16-bit logical operations
Bit shifting
Comparisons
Register movement
Sequential execution
Conditional-free jump control
NOP
HALT

The ISA can be extended in future revisions while preserving the current instruction encoding as a compatibility baseline.

Possible future extensions include:

  • Additional branch instructions
  • Immediate operands
  • Memory load/store instructions
  • Stack operations
  • Subroutine call/return
  • Interrupt support
  • System/control instructions

These features are not part of the current verified ISA.