diff --git a/acpi/ipu6/_cam_common_ar0234.asl b/acpi/ipu6/_cam_common_ar0234.asl
new file mode 100644
index 00000000..5958452f
--- /dev/null
+++ b/acpi/ipu6/_cam_common_ar0234.asl
@@ -0,0 +1,97 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (c) 2026 Intel Corporation.
+ *
+ * CAM-level defines expected by caller:
+ * DESCH_SER_REF - Path to parent SER (e.g. \_SB.PC00.DESx.CHxx.SERx), used in _DEP
+ * DESCH_SER_PATH - Path to parent SER (e.g. "\\_SB.PC00.DESx.CHxx.SERx"), used in CSI2Bus and GpioIo
+ * DESCH_SER_GPIOREF - GPIO controller path for SER (e.g. ^^SERx), used in gpio resources (e.g. reset-gpios)
+ * CAM_LANES - Number of MIPI data lanes for the camera
+ */
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F) // bit 0: device is present, bit 1: device is enabled, bit 2: device is shown in UI, bit 3: device is functional
+ }
+
+ Method (_HID, 0, NotSerialized) // _HID: Hardware ID
+ {
+ Return ("INTC10C0") // AR0234
+ }
+
+ Name (_DEP, Package (0x01) // _DEP: Dependencies
+ {
+ DESCH_SER_REF // Path to parent SER (e.g "\\_SB.PC00.DESx.CHxx.SERx")
+ })
+
+ Name(_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+{
+ /*
+ * mipi-disco-img.c will use the information in CSI2Bus to create fwnode.
+ * CAMx Local Port -> SERx Remote Port
+ * CAMx PRT0 -> SERx PRT0
+ */
+ CSI2Bus(
+ DeviceInitiated, // SlaveMode
+ 1, // PhyType (1 for DPHY)
+ 0, // LocalPort (AR0234 only 1 PHY)
+ DESCH_SER_PATH, // ResourceSource (Path to parent SERx, e.g. "\\_SB.PC00.DESx.CHxx.SERx")
+ 0, // ResourceSourceIndex (e.g. 0 for SERx PRT0)
+ , // ResourceUsage
+ , // DescriptorName
+ ) // VendorData
+
+ I2cSerialBusV2 (
+ 0x0010, // SlaveAddress (0x10 based on AR0234 hardware)
+ ControllerInitiated, // SlaveMode
+ 0x00061A80, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ DESCH_SER_PATH, // ResourceSource (Path to parent SER, e.g. "\\_SB.PC00.DESx.CHxx.SERx")
+ 0x00, // ResourceSourceIndex
+ ResourceConsumer, // ResourceUsage
+ , // DescriptorName
+ Exclusive, // Shared
+ ) // VendorData
+})
+
+Name (_DSD, Package () // _DSD: Device-Specific Data
+{
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties for _DSD
+ Package ()
+ {
+ Package () { "mipi-img-clock-frequency", 96000000 }, // 96 MHz
+
+ /*
+ * Sensor specific GPIOs, reset-gpios will be used by ar0234.c
+ * when devm_gpiod_get_optional is being called with "reset" consumer.
+ * For details, please refer to ACPI GPIO binding documentation
+ * https://www.kernel.org/doc/html/latest/firmware-guide/acpi/gpio-properties.html
+ *
+ * DESCH_SER_GPIOREF is the GPIO controller from parent SERx
+ * 0 is the GPIO pin group in parent SERx
+ * 0 is the index of pin in the GPIO pin group in parent SERx
+ * 1 is active low for reset
+ *
+ */
+ Package () { "reset-gpios", Package () { DESCH_SER_GPIOREF, 0, 0, 1 } },
+ },
+ ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), // Hierarchical Data Extension
+ Package ()
+ {
+ /* mipi-img-port here are NOT actual MIPI ports, but is used by mipi-disco-img.c to create fwnode. */
+ Package () { "mipi-img-port-0", "PRT0" }, // Connected to SERx PRTx (used by CAMx CSI2Bus LocalPort)
+ },
+})
+
+Name (PRT0, Package()
+{
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
+ Package ()
+ {
+ Package () { "mipi-img-clock-lanes", 0 },
+ #if CAM_LANES == 4
+ Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
+ #else
+ Package () { "mipi-img-data-lanes", Package() { 1, 2 } },
+ #endif
+ },
+})
\ No newline at end of file
diff --git a/acpi/ipu6/_cam_common_d457.asl b/acpi/ipu6/_cam_common_d457.asl
index 38930bc0..e17865ce 100644
--- a/acpi/ipu6/_cam_common_d457.asl
+++ b/acpi/ipu6/_cam_common_d457.asl
@@ -87,7 +87,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if CAM_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
#elif CAM_LANES == 2
diff --git a/acpi/ipu6/_cam_common_isx031.asl b/acpi/ipu6/_cam_common_isx031.asl
index b68f6b8b..1ab9c3f7 100644
--- a/acpi/ipu6/_cam_common_isx031.asl
+++ b/acpi/ipu6/_cam_common_isx031.asl
@@ -101,7 +101,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if CAM_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
#elif CAM_LANES == 2
diff --git a/acpi/ipu6/_des_ch_common_ar0234.asl b/acpi/ipu6/_des_ch_common_ar0234.asl
new file mode 100644
index 00000000..e27a3390
--- /dev/null
+++ b/acpi/ipu6/_des_ch_common_ar0234.asl
@@ -0,0 +1,55 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (c) 2026 Intel Corporation.
+ *
+ * Description: Common template for each AR0234 GMSL camera under each deserializer link,
+ * where each link is represented as an ATR channel device.
+ *
+ * DES-level defines expected by caller:
+ * DES_PATH - DESx ACPI path string (e.g., "\\_SB.PC00.DES0")
+ * DES_REF - DESx ACPI namespace reference (e.g., \_SB.PC00.DES0)
+ *
+ * Channel-level defines expected by caller:
+ * DESCH_CH - Channel device name (e.g., CH00)
+ * DESCH_SER - Serializer device name (e.g., SER0)
+ * DESCH_CAM - Camera device name (e.g., CAM0)
+ * DESCH_CH_PATH - CHxx ACPI path string (e.g., "\\_SB.PC00.DES0.CH00")
+ * DESCH_SER_PATH - SERx ACPI path string (e.g., "\\_SB.PC00.DES0.CH00.SER0")
+ * DESCH_SER_REF - SERx ACPI namespace reference (e.g., \_SB.PC00.DES0.CH00.SER0)
+ * DESCH_SER_I2C - SERx I2C address (e.g., 0x40)
+ * DESCH_LINK_NUM - Channel/link number (0, 1, 2, 3) - used for _ADR, reg, and SER remote port
+ * DESCH_SER_GPIOREF - SERx GPIO controller reference (e.g., ^^SER0, ^^SER1, etc.)
+ * CAM_LANES - CAMx Number of MIPI data lanes for the camera (e.g., 2, 4)
+ * Optional defines:
+ * DESCH_SER_EXTRA_GPIO_PIN - SERx Additional GPIO pin number (e.g., 7 for MFP7 in MAX9295A)
+ * DESCH_SER_X/Y/Z/U_VC - SERx VC filter for Pipe X/Y/Z/U, specifically for MAX96717 driver
+ */
+
+Device (DESCH_CH) // New CHxx Device under parent DESx device for each DES channel/link
+{
+ /*
+ * Channel is the naming convention used by i2c-mux or i2c-atr in ACPI namespace
+ * In GMSL context, it can directly be translated as Link 0/1/2/3 of the Deserializer
+ */
+
+ Name (_ADR, DESCH_LINK_NUM) // _ADR: Address for the channel (e.g. 0 for Link 0, 1 for Link 1)
+
+ Name (_DSD, Package () // _DSD: Device Specific Data
+ {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
+ Package ()
+ {
+ Package () { "reg", DESCH_LINK_NUM }, // used by i2c-atr driver. Represents the channel / link number
+ }
+ })
+
+ Device (DESCH_SER) // SERx device under parent DESx.CHxx
+ {
+ #include "_ser_common_max9295.asl"
+
+ Device (DESCH_CAM) // CAMx device under parent DESx.CHxx.SERx
+ {
+ #include "_cam_common_ar0234.asl"
+ }
+ }
+}
\ No newline at end of file
diff --git a/acpi/ipu6/_des_common_max9296.asl b/acpi/ipu6/_des_common_max9296.asl
index 5f47f02b..32f5b957 100644
--- a/acpi/ipu6/_des_common_max9296.asl
+++ b/acpi/ipu6/_des_common_max9296.asl
@@ -85,7 +85,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package () { 1, 2, 3, 4} },
},
})
@@ -95,7 +95,7 @@ Name (PRT1, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
})
@@ -105,7 +105,7 @@ Name (PRT2, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 2
Package () { "mipi-img-data-lanes", Package() { 1, 2 } },
#else
@@ -120,7 +120,7 @@ Name (PRT3, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 2
Package () { "mipi-img-data-lanes", Package() { 1, 2 } },
#else
diff --git a/acpi/ipu6/_des_common_max96724.asl b/acpi/ipu6/_des_common_max96724.asl
index f21653ab..604b4e41 100644
--- a/acpi/ipu6/_des_common_max96724.asl
+++ b/acpi/ipu6/_des_common_max96724.asl
@@ -100,7 +100,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package () { 1, 2, 3, 4} },
},
})
@@ -110,7 +110,7 @@ Name (PRT1, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
@@ -121,7 +121,7 @@ Name (PRT2, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package () { 1, 2, 3, 4 } },
},
})
@@ -131,7 +131,7 @@ Name (PRT3, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
@@ -142,7 +142,7 @@ Name (PRT4, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0},
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
@@ -159,8 +159,14 @@ Name (PRT5, Package()
{
Package () { "mipi-img-clock-lanes", 0 },
#if DES_LANES == 4
+ #if DES_PHY_TYPE == 1
+ Package () { "mipi-img-clock-lane", 5 }, // DPHY uses alternate CKCP PHY0 clock lane
+ #else
+ Package () { "mipi-img-clock-lane", 0 },
+ #endif
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2 } }, // 2 lanes for CPHY/DPHY on Intel MIPI CRD
#endif
Package () { "mipi-img-link-frequencies", Package() { 1000000000 } }, // 1 GHz to be used by Intel IPU driver as link frequency
@@ -172,7 +178,7 @@ Name (PRT6, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0},
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
@@ -187,7 +193,7 @@ Name (PRT7, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
diff --git a/acpi/ipu6/_ser_common_max9295.asl b/acpi/ipu6/_ser_common_max9295.asl
index 465a9938..6bd3b263 100644
--- a/acpi/ipu6/_ser_common_max9295.asl
+++ b/acpi/ipu6/_ser_common_max9295.asl
@@ -105,7 +105,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if CAM_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 data lanes
#elif CAM_LANES == 2
@@ -121,7 +121,7 @@ Name (PRT1, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
})
diff --git a/acpi/ipu6/max9296_d3_ar0234.asl b/acpi/ipu6/max9296_d3_ar0234.asl
new file mode 100644
index 00000000..a71a2d22
--- /dev/null
+++ b/acpi/ipu6/max9296_d3_ar0234.asl
@@ -0,0 +1,118 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0
+ * Copyright (c) 2026 Intel Corporation.
+ *
+ * SSDT overlay: D3 AR0234 GMSL camera configuration with MAX9296A deserializer on IPU6EPMTL platform.
+ * One MAX9296A deserializer (DES0, two GMSL links) with DPHY connection to IPU6EPMTL platform,
+ * carrying two AR0234 cameras over GMSL Links 0..1, fronted by MAX9295A serializers.
+ *
+ *
+ * DES-level defines (set per DESx, undef'd at the end of each Device):
+ * DES_PHY_TYPE - DES PHY type (0 for CPHY, 1 for DPHY)
+ * DES_I2C_ADDR - DES I2C slave address (e.g. 0x0048 for MAX9296A)
+ * DES_LANES - Number of MIPI data lanes (e.g. 2, 4)
+ * DES_INTERNAL_PHY - DES internal PHY index (MAX9296A: 1 or 2)
+ * DES_TO_MIPI_PORT - DES connected to IPU0 MIPI port (e.g. 0/1/2/3)
+ * DES_I2C_BUS - DES I2C bus path (e.g. "\\_SB.PC00.I2C1")
+ * DES_PATH - DES ACPI path string (e.g. "\\_SB.PC00.DES0")
+ * DES_REF - DES ACPI namespace reference (e.g. \_SB.PC00.DES0)
+ *
+ * Channel-level defines (set per CHxx, undef'd by _des_ch_common_ar0234.asl):
+ * DESCH_LINK_NUM - Channel/link number (0..1 for MAX9296A) - used for _ADR, reg, SER remote port
+ * DESCH_CH - Channel device name (e.g. CH00)
+ * DESCH_SER - Serializer device name (e.g. SER0)
+ * DESCH_CAM - Camera device name (e.g. CAM0)
+ * DESCH_SER_I2C - SER I2C slave address (e.g. 0x40 for MAX9295A)
+ * DESCH_CH_PATH - CHxx ACPI path string (e.g. "\\_SB.PC00.DES0.CH00")
+ * DESCH_SER_PATH - SERx ACPI path string (e.g. "\\_SB.PC00.DES0.CH00.SER0")
+ * DESCH_SER_REF - SERx ACPI namespace reference (e.g. \_SB.PC00.DES0.CH00.SER0)
+ * DESCH_SER_GPIOREF - SERx GPIO controller reference (e.g. ^^SER0)
+ * CAM_ALIAS - Camera alias I2C address used in i2c-alias-pool of the SER
+ * CAM_LANES - Number of MIPI data lanes for the camera (e.g. 2, 4)
+ */
+
+DefinitionBlock ("", "SSDT", 2, "", "IMG_IPU", 0x20260715)
+{
+ External (_SB.PC00, DeviceObj)
+
+ Include ("_ipu.asl")
+
+ Scope (\_SB.PC00)
+ {
+ Device (DES0)
+ {
+ //DES-level defines for DES0
+ #define DES_PHY_TYPE 1
+ #define DES_I2C_ADDR 0x0048
+ #define DES_LANES 4
+ #define DES_INTERNAL_PHY 2
+ #define DES_TO_MIPI_PORT 0
+ #define DES_I2C_BUS "\\_SB.PC00.I2C1"
+ #define DES_PATH "\\_SB.PC00.DES0"
+ #define DES_REF \_SB.PC00.DES0
+ #define LINK_FREQ 700000000
+ #include "_des_common_max9296.asl"
+
+ // Channel 0
+ #define DESCH_LINK_NUM 0
+ #define DESCH_CH CH00
+ #define DESCH_SER SER0
+ #define DESCH_CAM CAM0
+ #define DESCH_SER_I2C 0x40
+ #define DESCH_CH_PATH "\\_SB.PC00.DES0.CH00"
+ #define DESCH_SER_PATH "\\_SB.PC00.DES0.CH00.SER0"
+ #define DESCH_SER_REF \_SB.PC00.DES0.CH00.SER0
+ #define DESCH_SER_GPIOREF ^^SER0
+ #define CAM_ALIAS 0x54
+ #define CAM_LANES 2
+ #include "_des_ch_common_ar0234.asl"
+ #undef DESCH_CH
+ #undef DESCH_SER
+ #undef DESCH_CAM
+ #undef DESCH_CH_PATH
+ #undef DESCH_SER_PATH
+ #undef DESCH_SER_REF
+ #undef DESCH_LINK_NUM
+ #undef DESCH_SER_I2C
+ #undef DESCH_SER_GPIOREF
+ #undef CAM_ALIAS
+ #undef CAM_LANES
+
+ // Channel 1
+ #define DESCH_LINK_NUM 1
+ #define DESCH_CH CH01
+ #define DESCH_SER SER1
+ #define DESCH_CAM CAM1
+ #define DESCH_SER_I2C 0x40
+ #define DESCH_CH_PATH "\\_SB.PC00.DES0.CH01"
+ #define DESCH_SER_PATH "\\_SB.PC00.DES0.CH01.SER1"
+ #define DESCH_SER_REF \_SB.PC00.DES0.CH01.SER1
+ #define DESCH_SER_GPIOREF ^^SER1
+ #define CAM_ALIAS 0x55
+ #define CAM_LANES 2
+ #include "_des_ch_common_ar0234.asl"
+ #undef DESCH_CH
+ #undef DESCH_SER
+ #undef DESCH_CAM
+ #undef DESCH_CH_PATH
+ #undef DESCH_SER_PATH
+ #undef DESCH_SER_REF
+ #undef DESCH_LINK_NUM
+ #undef DESCH_SER_I2C
+ #undef DESCH_SER_GPIOREF
+ #undef CAM_ALIAS
+ #undef CAM_LANES
+
+ // Clean up DES-level defines
+ #undef DES_PHY_TYPE
+ #undef DES_I2C_ADDR
+ #undef DES_LANES
+ #undef DES_INTERNAL_PHY
+ #undef DES_TO_MIPI_PORT
+ #undef DES_I2C_BUS
+ #undef DES_PATH
+ #undef DES_REF
+ #undef LINK_FREQ
+ }
+ }
+}
\ No newline at end of file
diff --git a/acpi/ipu6/max96724_dphy_d3_isx031.asl b/acpi/ipu6/max96724_dphy_d3_isx031.asl
index 180bb1f4..471c88f6 100644
--- a/acpi/ipu6/max96724_dphy_d3_isx031.asl
+++ b/acpi/ipu6/max96724_dphy_d3_isx031.asl
@@ -176,7 +176,7 @@ DefinitionBlock ("", "SSDT", 2, "", "IMG_IPU", 0x20260513)
// DES-level defines for DES1.
#define DES_PHY_TYPE 1
#define DES_I2C_ADDR 0x0027
- #define DES_LANES 2
+ #define DES_LANES 4
#define DES_INTERNAL_PHY 6
#define DES_TO_MIPI_PORT 4
#define DES_I2C_BUS "\\_SB.PC00.I2C0"
diff --git a/acpi/ipu7/_cam_common_d457.asl b/acpi/ipu7/_cam_common_d457.asl
index 7fbd05dd..74f93cac 100644
--- a/acpi/ipu7/_cam_common_d457.asl
+++ b/acpi/ipu7/_cam_common_d457.asl
@@ -91,7 +91,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if CAM_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
#elif CAM_LANES == 2
diff --git a/acpi/ipu7/_cam_common_isx031.asl b/acpi/ipu7/_cam_common_isx031.asl
index d4231542..a4e9fc5d 100644
--- a/acpi/ipu7/_cam_common_isx031.asl
+++ b/acpi/ipu7/_cam_common_isx031.asl
@@ -105,7 +105,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if CAM_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
#elif CAM_LANES == 2
diff --git a/acpi/ipu7/_des_common_max96724.asl b/acpi/ipu7/_des_common_max96724.asl
index 2a268f48..d3030cc9 100644
--- a/acpi/ipu7/_des_common_max96724.asl
+++ b/acpi/ipu7/_des_common_max96724.asl
@@ -104,7 +104,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package () { 1, 2, 3, 4} },
},
})
@@ -114,7 +114,7 @@ Name (PRT1, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
@@ -125,7 +125,7 @@ Name (PRT2, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package () { 1, 2, 3, 4 } },
},
})
@@ -135,7 +135,7 @@ Name (PRT3, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
@@ -146,7 +146,7 @@ Name (PRT4, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
@@ -161,7 +161,7 @@ Name (PRT5, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
@@ -176,7 +176,7 @@ Name (PRT6, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
@@ -191,7 +191,7 @@ Name (PRT7, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
diff --git a/acpi/ipu7/_ser_common_max9295.asl b/acpi/ipu7/_ser_common_max9295.asl
index e874e863..066ecfea 100644
--- a/acpi/ipu7/_ser_common_max9295.asl
+++ b/acpi/ipu7/_ser_common_max9295.asl
@@ -109,7 +109,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if CAM_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 data lanes
#elif CAM_LANES == 2
@@ -125,7 +125,7 @@ Name (PRT1, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
})
diff --git a/acpi/ipu8/_cam_common_d457.asl b/acpi/ipu8/_cam_common_d457.asl
index 38930bc0..e17865ce 100644
--- a/acpi/ipu8/_cam_common_d457.asl
+++ b/acpi/ipu8/_cam_common_d457.asl
@@ -87,7 +87,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if CAM_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
#elif CAM_LANES == 2
diff --git a/acpi/ipu8/_cam_common_isx031.asl b/acpi/ipu8/_cam_common_isx031.asl
index b68f6b8b..1ab9c3f7 100644
--- a/acpi/ipu8/_cam_common_isx031.asl
+++ b/acpi/ipu8/_cam_common_isx031.asl
@@ -101,7 +101,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if CAM_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
#elif CAM_LANES == 2
diff --git a/acpi/ipu8/_des_common_max96724.asl b/acpi/ipu8/_des_common_max96724.asl
index 5535c05b..60450fd7 100644
--- a/acpi/ipu8/_des_common_max96724.asl
+++ b/acpi/ipu8/_des_common_max96724.asl
@@ -100,7 +100,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package () { 1, 2, 3, 4} },
},
})
@@ -110,7 +110,7 @@ Name (PRT1, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
@@ -121,7 +121,7 @@ Name (PRT2, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package () { 1, 2, 3, 4 } },
},
})
@@ -131,7 +131,7 @@ Name (PRT3, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
@@ -142,7 +142,7 @@ Name (PRT4, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
@@ -157,7 +157,7 @@ Name (PRT5, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
@@ -172,7 +172,7 @@ Name (PRT6, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
@@ -187,7 +187,7 @@ Name (PRT7, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if DES_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 lanes for DPHY on Intel MIPI CRD
#else
diff --git a/acpi/ipu8/_ser_common_max9295.asl b/acpi/ipu8/_ser_common_max9295.asl
index 465a9938..6bd3b263 100644
--- a/acpi/ipu8/_ser_common_max9295.asl
+++ b/acpi/ipu8/_ser_common_max9295.asl
@@ -105,7 +105,7 @@ Name (PRT0, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
#if CAM_LANES == 4
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } }, // 4 data lanes
#elif CAM_LANES == 2
@@ -121,7 +121,7 @@ Name (PRT1, Package()
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), // Device Properties
Package ()
{
- Package () { "mipi-img-clock-lanes", 0 },
+ Package () { "mipi-img-clock-lane", 0 },
Package () { "mipi-img-data-lanes", Package() { 1, 2, 3, 4 } },
},
})
diff --git a/config/ar0234/ipu6epmtl/sensors/ar0234.xml b/config/ar0234/ipu6epmtl/sensors/ar0234.xml
index a8a98e73..06941f10 100644
--- a/config/ar0234/ipu6epmtl/sensors/ar0234.xml
+++ b/config/ar0234/ipu6epmtl/sensors/ar0234.xml
@@ -154,4 +154,108 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/drivers/media/i2c/maxim-serdes/max96717.c b/drivers/media/i2c/maxim-serdes/max96717.c
index 9fc72fd2..6107e18a 100644
--- a/drivers/media/i2c/maxim-serdes/max96717.c
+++ b/drivers/media/i2c/maxim-serdes/max96717.c
@@ -820,6 +820,30 @@ static int max96717_gpio_set(struct gpio_chip *gc, unsigned int offset, int valu
return max96717_conf_pin_config_set_one(priv, offset, config);
}
+static int max96717_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
+ unsigned long config)
+{
+ struct max96717_priv *priv = gpiochip_get_data(gc);
+ unsigned int mask, val;
+
+ switch (pinconf_to_config_param(config)) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ /* OUT_TYPE = 0 -> open-drain; leave pull resistor config unchanged */
+ mask = MAX96717_GPIO_B_OUT_TYPE;
+ val = 0;
+ break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ /* OUT_TYPE = 1 -> push-pull */
+ mask = MAX96717_GPIO_B_OUT_TYPE;
+ val = field_prep(MAX96717_GPIO_B_OUT_TYPE, 1);
+ break;
+ default:
+ return max96717_conf_pin_config_set_one(priv, offset, config);
+ }
+
+ return regmap_update_bits(priv->regmap, MAX96717_GPIO_B(offset), mask, val);
+}
+
static unsigned int max96717_pipe_id(struct max96717_priv *priv,
struct max_ser_pipe *pipe)
{
@@ -1728,7 +1752,7 @@ static int max96717_gpiochip_probe(struct max96717_priv *priv)
.can_sleep = true,
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
- .set_config = gpiochip_generic_config,
+ .set_config = max96717_gpio_set_config,
.get_direction = max96717_gpio_get_direction,
.direction_input = max96717_gpio_direction_input,
.direction_output = max96717_gpio_direction_output,
diff --git a/drivers/media/i2c/maxim-serdes/max96724.c b/drivers/media/i2c/maxim-serdes/max96724.c
index 13791b5e..ce2dd3c6 100644
--- a/drivers/media/i2c/maxim-serdes/max96724.c
+++ b/drivers/media/i2c/maxim-serdes/max96724.c
@@ -80,7 +80,7 @@
#define MAX96724_BACKTOP32_BPP10DBL1_MODE BIT(7)
#define MAX96724_MIPI_PHY0 0x8a0
-#define MAX96724_MIPI_PHY0_PHY_CONFIG GENMASK(4, 0)
+#define MAX96724_MIPI_PHY0_PHY_CONFIG GENMASK(6, 0)
#define MAX96724_MIPI_PHY0_PHY_4X2 BIT(0)
#define MAX96724_MIPI_PHY0_PHY_2X4 BIT(2)
#define MAX96724_MIPI_PHY0_PHY_1X4A_2X2 BIT(3)
@@ -122,11 +122,12 @@
#define MAX96724_MIPI_PHY27_PHY_PKT_CNT(x) (GENMASK(3, 0) << (4 * ((x) % 2)))
#define MAX96724_MIPI_TX3(x) (0x903 + (x) * 0x40)
-#define MAX96724_MIPI_TX3_DESKEW_INIT_8X32K FIELD_PREP(GENMASK(2, 0), 0b001)
+#define MAX96724_MIPI_TX3_DESKEW_INIT_8X32K FIELD_PREP(GENMASK(2, 0), 0b111)
#define MAX96724_MIPI_TX3_DESKEW_INIT_AUTO BIT(7)
#define MAX96724_MIPI_TX4(x) (0x904 + (x) * 0x40)
-#define MAX96724_MIPI_TX4_DESKEW_PER_2K FIELD_PREP(GENMASK(2, 0), 0b001)
+#define MAX96724_MIPI_TX4_DESKEW_PER_8 FIELD_PREP(GENMASK(2, 0), 0b111)
+#define MAX96724_MIPI_TX4_DESKEW_PER_INT_1FRAME FIELD_PREP(GENMASK(5, 3), 0b000)
#define MAX96724_MIPI_TX4_DESKEW_PER_AUTO BIT(7)
#define MAX96724_MIPI_TX10(x) (0x90a + (x) * 0x40)
@@ -401,6 +402,7 @@ static const unsigned int max96724_phys_configs_reg_val[] = {
MAX96724_MIPI_PHY0_PHY_1X4A_2X2,
MAX96724_MIPI_PHY0_PHY_1X4B_2X2,
MAX96724_MIPI_PHY0_PHY_2X4,
+ MAX96724_MIPI_PHY0_PHY_1X4A_2X2 | MAX96724_MIPI_PHY0_CLK_PHY0,
};
static const struct max_serdes_phys_config max96724_phys_configs[] = {
@@ -422,6 +424,7 @@ static const struct max_serdes_phys_config max96724_phys_configs[] = {
{ { 4, 0, 2, 2 } },
{ { 2, 2, 4, 0 } },
{ { 4, 0, 4, 0 } },
+ { { 0, 4, 2, 2 }, { 0, MAX96724_PHY1_ALT_CLOCK, 0, 0 } },
};
static int max96724_init_tpg(struct max_des *des)
@@ -510,7 +513,6 @@ static int max96724_init_phy(struct max_des *des, struct max_des_phy *phy)
MAX96724_MIPI_TX10_CSI2_CPHY_EN, is_cphy);
if (ret)
return ret;
-
/* Configure lane mapping. */
val = 0;
for (i = 0; i < num_hw_data_lanes ; i++) {
@@ -571,17 +573,18 @@ static int max96724_init_phy(struct max_des *des, struct max_des_phy *phy)
}
if (!is_cphy && dpll_freq > 1500000000ull) {
- /* Enable initial deskew with 2 x 32k UI. */
+ /* Enable initial deskew with 8 x 32k UI. */
ret = regmap_write(priv->regmap, MAX96724_MIPI_TX3(index),
MAX96724_MIPI_TX3_DESKEW_INIT_AUTO |
MAX96724_MIPI_TX3_DESKEW_INIT_8X32K);
if (ret)
return ret;
- /* Enable periodic deskew with 2 x 1k UI.. */
+ /* Enable periodic deskew with 8 x 1k UI. */
ret = regmap_write(priv->regmap, MAX96724_MIPI_TX4(index),
MAX96724_MIPI_TX4_DESKEW_PER_AUTO |
- MAX96724_MIPI_TX4_DESKEW_PER_2K);
+ MAX96724_MIPI_TX4_DESKEW_PER_INT_1FRAME |
+ MAX96724_MIPI_TX4_DESKEW_PER_8);
if (ret)
return ret;
} else {
@@ -692,11 +695,48 @@ static int max96724_set_pipe_remap(struct max_des *des,
struct max_des_remap *remap)
{
struct max96724_priv *priv = des_to_priv(des);
- struct max_des_phy *phy = &des->phys[remap->phy];
- unsigned int phy_id = max96724_phy_id(des, phy);
+ struct max_des_phy *phy = NULL;
+ unsigned int phy_id;
unsigned int index = pipe->index;
+ unsigned int j;
int ret;
+ /*
+ * Route MAP_DPHY_DEST to the output PHY selected by the core for this
+ * route (remap->phy), but only when that PHY is a valid active output
+ * (enabled and with non-zero hw data lanes). This keeps multiple
+ * simultaneous output PHYs (e.g. 2x4/4x2) routed correctly.
+ */
+ if (remap->phy < des->ops->num_phys &&
+ des->phys[remap->phy].enabled &&
+ max_des_phy_hw_data_lanes(des, &des->phys[remap->phy]))
+ phy = &des->phys[remap->phy];
+
+ /*
+ * Otherwise fall back to the first enabled PHY with non-zero hw data
+ * lanes. In 1x4A mode this is PHY1 (the master that carries the clock
+ * lane); the routing-context PHY can point at an inactive PHY (e.g.
+ * PHY0 with 0 lanes), which must not be programmed as the destination.
+ */
+ if (!phy) {
+ for (j = 0; j < des->ops->num_phys; j++) {
+ if (des->phys[j].enabled &&
+ max_des_phy_hw_data_lanes(des, &des->phys[j])) {
+ phy = &des->phys[j];
+ break;
+ }
+ }
+ }
+
+ if (!phy) {
+ dev_err(priv->dev,
+ "No active output PHY for pipe %u remap %u\n", index, i);
+ return -EINVAL;
+ }
+
+ /* Translate logical PHY index to the physical MIPI controller id. */
+ phy_id = max96724_phy_id(des, phy);
+
/* Set source Data Type and Virtual Channel. */
/* TODO: implement extended Virtual Channel. */
ret = regmap_write(priv->regmap, MAX96724_MIPI_TX13(index, i),
diff --git a/ipu7-drivers b/ipu7-drivers
index 22ce0dda..bed9b71d 160000
--- a/ipu7-drivers
+++ b/ipu7-drivers
@@ -1 +1 @@
-Subproject commit 22ce0dda426bd0c84695e6245139bc30fb554e54
+Subproject commit bed9b71d5be56d0e24c771c7a6ec83fd0a9db433
diff --git a/patches/6.18/0006-media-pci-ipu7-Add-D4XX-support-to-IPU7.patch b/patches/6.18/0006-media-pci-ipu7-Add-D4XX-support-to-IPU7.patch
index 8e36a03f..c0742f43 100644
--- a/patches/6.18/0006-media-pci-ipu7-Add-D4XX-support-to-IPU7.patch
+++ b/patches/6.18/0006-media-pci-ipu7-Add-D4XX-support-to-IPU7.patch
@@ -41,7 +41,7 @@
WARN_ON(1);
--- a/ipu7-drivers/drivers/media/pci/intel/ipu7/ipu7-isys-video.c
+++ b/ipu7-drivers/drivers/media/pci/intel/ipu7/ipu7-isys-video.c
-@@ -84,11 +84,20 @@ const struct ipu7_isys_pixelformat ipu7_isys_pfmts[] = {
+@@ -84,12 +84,21 @@ const struct ipu7_isys_pixelformat ipu7_isys_pfmts[] = {
{V4L2_PIX_FMT_UYVY, 16, 16, MEDIA_BUS_FMT_UYVY8_1X16,
IPU_INSYS_FRAME_FORMAT_UYVY},
{V4L2_PIX_FMT_YUYV, 16, 16, MEDIA_BUS_FMT_YUYV8_1X16,
@@ -62,7 +62,8 @@
+ IPU_INSYS_FRAME_FORMAT_RAW8},
};
- static int video_open(struct file *file)
+ #ifdef CONFIG_VIDEO_INTEL_IPU7_ISYS_RESET
+ static int video_release(struct file *file)
--- a/ipu7-drivers/drivers/media/pci/intel/ipu7/ipu7-isys.h
+++ b/ipu7-drivers/drivers/media/pci/intel/ipu7/ipu7-isys.h
@@ -45,7 +45,7 @@ struct ipu7_isys_stream;
diff --git a/script/acpi/mc-setup.sh b/script/acpi/mc-setup.sh
index e8719386..192554bf 100755
--- a/script/acpi/mc-setup.sh
+++ b/script/acpi/mc-setup.sh
@@ -100,10 +100,12 @@
declare -A SENSOR_MODEL=(
[INTC10CD]=d4xx
[INTC113C]=isx031
+ [INTC10C0]=ar0234
)
declare -A SENSOR_PREFIX=(
[INTC10CD]="DS5 mux"
[INTC113C]="isx031"
+ [INTC10C0]="ar0234"
)
# ---- Serializer / Deserializer HID -> v4l entity prefix ---------------------
@@ -128,10 +130,12 @@ declare -A MAX_LINKS_BY_PREFIX=(
declare -A MODEL_STREAMS=(
[d4xx]="depth rgb ir imu"
[isx031]="yuv"
+ [ar0234]="raw"
)
declare -A MODEL_DEFAULT_STREAMS=(
[d4xx]="depth rgb"
[isx031]="yuv"
+ [ar0234]="raw"
)
# STREAM_NODE: per-stream capture-node index (also used as the v4l2
@@ -143,6 +147,7 @@ declare -A STREAM_NODE=(
[ir]=2
[imu]=3
[yuv]=0
+ [raw]=0
)
# Keep capture-node groups consistent across 2-link and 4-link deserializers:
@@ -171,6 +176,7 @@ declare -A STREAM_FMT=(
[ir]=${STREAM_FMT_ir:-VYUY8_1X16}
[imu]=${STREAM_FMT_imu:-Y8_1X8}
[yuv]=${STREAM_FMT_yuv:-UYVY8_1X16}
+ [raw]=${STREAM_FMT_raw:-SGRBG10_1X10}
)
declare -A STREAM_SIZE=(
[depth]=${STREAM_SIZE_depth:-$D4XX_SIZE}
@@ -178,6 +184,7 @@ declare -A STREAM_SIZE=(
[ir]=${STREAM_SIZE_ir:-$D4XX_SIZE}
[imu]=${STREAM_SIZE_imu:-38x1}
[yuv]=${STREAM_SIZE_yuv:-1920x1536}
+ [raw]=${STREAM_SIZE_raw:-1280x960}
)
# ---- Media-bus -> V4L2 pixelformat fourcc (used on capture nodes) -----------
@@ -186,6 +193,7 @@ declare -A MBUS_TO_PIXFMT=(
[YUYV8_1X16]="YUYV"
[VYUY8_1X16]="Y8I " # IR -> interleaved 8-bit greyscale
[Y8_1X8]="GREY"
+ [SGRBG10_1X10]="BA10" # AR0234 RAW Bayer SGRBG 10-bit
)
# =============================================================================
@@ -781,7 +789,7 @@ for k in "${!CFG_LINKS[@]}"; do
unset is_selected
;;
- isx031)
+ isx031|ar0234)
ser_route_parts=()
for s in "${sel_streams[@]}"; do
sid=${STREAM_NODE[$s]}
@@ -844,6 +852,9 @@ for k in "${!CFG_LINKS[@]}"; do
isx031)
mc_v "\"isx031 ${cam}\":0/${sid} [fmt:${fmt}/${size} field:none]"
;;
+ ar0234)
+ mc_v "\"ar0234 ${cam}\":0/${sid} [fmt:${fmt}/${size} field:none]"
+ ;;
esac
mc_v "\"${ser_pfx} ${ser}\":0/${sid} [fmt:${fmt}/${size} field:none]"
mc_v "\"${ser_pfx} ${ser}\":1/${sid} [fmt:${fmt}/${size} field:none]"