From d2955473fbab8b8c4224ba04f78c329074be4307 Mon Sep 17 00:00:00 2001 From: Trinity Bee Date: Sat, 3 Oct 2026 20:17:12 +0000 Subject: [PATCH 1/2] Port clock_test.v to specs/port/trinity/fpga/openxc7-synth/clock_test.t27 gHashTag/trinity's fpga/openxc7-synth/clock_test.v is 27 lines of hand-written Verilog: a clock-test module whose T23 LED is tied to the 50MHz clock and whose R23 LED is tied to the inverted clock. This adds the .t27 source it should have been written in. - module clock_test carries the original's name; on_comb(clk) is the combinational surface (its parameter becomes the clk input), and t23_output/r23_output are the original's two assigns as functions. - ClockOutputs{t23, r23} is the module's output pair. - CLK_MHZ = 50, from the original's '50 MHz on U22'. - Three test blocks assert the original's values: t23 follows clk in both states, r23 inverts clk, and the two LEDs never agree. One invariant proves the clock frequency positive at compile time. t27c parse and typecheck are clean; t27c test-report runs 3/3 pass with one proved invariant and no BLOCKED; t27c gen-verilog emits 'module clock_test ('. Closes #5819 --- .../trinity/fpga/openxc7-synth/clock_test.t27 | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 specs/port/trinity/fpga/openxc7-synth/clock_test.t27 diff --git a/specs/port/trinity/fpga/openxc7-synth/clock_test.t27 b/specs/port/trinity/fpga/openxc7-synth/clock_test.t27 new file mode 100644 index 0000000000..94e0c231a5 --- /dev/null +++ b/specs/port/trinity/fpga/openxc7-synth/clock_test.t27 @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: Apache-2.0 +// t27/specs/port/trinity/fpga/openxc7-synth/clock_test.t27 +// CLOCK TEST - Verify 50MHz oscillator is working +// Ported from gHashTag/trinity fpga/openxc7-synth/clock_test.v +// Direct connection: T23 LED tied to the clock, R23 LED tied to the inverted clock +// If the clock works, the LEDs show blur (~50MHz too fast to see) +// If an LED is solid, the clock is not working +// phi^2 + 1/phi^2 = 3 | TRINITY + +module clock_test { + + // === Module constants === + + // 50 MHz on U22 + pub const CLK_MHZ : u32 = 50; + + // === Output types === + + // The two LEDs the module drives: t23 follows the clock, r23 inverts it. + pub struct ClockOutputs { + t23 : bool, + r23 : bool, + } + + // === Combinational surface === + + // The original's two assigns in one decision: + // assign t23 = clk; + // assign r23 = ~clk; + // The parameter becomes the `clk` input, the return the combinational result. + fn on_comb(clk: bool) -> ClockOutputs { + return ClockOutputs{ .t23 = clk, .r23 = !clk }; + } + + // === Output functions (the individual assigns) === + + // assign t23 = clk; // T23 LED - direct clock connection + fn t23_output(clk: bool) -> bool { + return clk; + } + + // assign r23 = ~clk; // R23 LED - inverted clock + fn r23_output(clk: bool) -> bool { + return !clk; + } + + // === Tests === + + // T23 LED follows the clock in both states. + test t23_follows_clk + given high = t23_output(true) + then high == true + and t23_output(false) == false + + // R23 LED is the inverted clock in both states. + test r23_inverts_clk + given low = r23_output(false) + then low == true + and r23_output(true) == false + + // The original's pair of assigns: the two LEDs never agree. + test outputs_complement + given quiet = on_comb(false) + then quiet.t23 == false + and quiet.r23 == true + and t23_output(true) == true + and r23_output(true) == false + and quiet.t23 != quiet.r23 + + // === Invariants === + + invariant clock_frequency_positive + given mhz = CLK_MHZ + assert mhz > 0 +} + +// phi^2 + 1/phi^2 = 3 | TRINITY From 04d7b70e3ad171cd81b4831589a0765b6149d588 Mon Sep 17 00:00:00 2001 From: "queen-publisher[bot]" Date: Sat, 3 Oct 2026 20:25:44 +0000 Subject: [PATCH 2/2] docs: the coordination entry this branch needs to land A pull request must add exactly one docs/now entry and a bee has no way to know that: its brief names a boundary file and acceptance criteria, and docs/now/ is neither. The publisher adds it rather than failing the gate. Closes #5819 Co-Authored-By: Claude Opus 5 --- ...-trinity-fpga-openxc7-synth-clock-test-v-verilo.md | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 docs/now/2026-10-03-published-port-ghashtag-trinity-fpga-openxc7-synth-clock-test-v-verilo.md diff --git a/docs/now/2026-10-03-published-port-ghashtag-trinity-fpga-openxc7-synth-clock-test-v-verilo.md b/docs/now/2026-10-03-published-port-ghashtag-trinity-fpga-openxc7-synth-clock-test-v-verilo.md new file mode 100644 index 0000000000..4a3830ded9 --- /dev/null +++ b/docs/now/2026-10-03-published-port-ghashtag-trinity-fpga-openxc7-synth-clock-test-v-verilo.md @@ -0,0 +1,11 @@ +# NOW -- Port gHashTag/trinity:fpga/openxc7-synth/clock_test.v (Verilog, 1 module) to specs/port/trinity/fpga/openxc7-synth/clock_test.t27 (published 2026-10-03) + +## A bee's work on #5819, published from `queen-5819` (Closes #5819) + +- The branch changes 1 file(s): `specs/port/trinity/fpga/openxc7-synth/clock_test.t27`. +- `git diff --stat origin/master...queen-5819` reads: 1 file changed, 77 insertions(+) +- This entry is written by the publisher, not by the bee. A pull request must + add exactly one `docs/now/` entry and a bee has no way to know that: its brief + names a boundary file and acceptance criteria, and `docs/now/` is neither. +- What this entry does NOT establish: that the work is correct. The gates on the + pull request judge that, and they are the same gates every other change meets.