From 946bcdbfcbbc3d84e0a475fadc8d03382c93e30f Mon Sep 17 00:00:00 2001 From: by Date: Wed, 15 Jul 2026 07:23:15 +0800 Subject: [PATCH] fix(msp430): correct memset and memcpy assembly operand order for TI syntax --- core/src/cpus/msp430.zig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/core/src/cpus/msp430.zig b/core/src/cpus/msp430.zig index c0ddf51b9..4df67a5cb 100644 --- a/core/src/cpus/msp430.zig +++ b/core/src/cpus/msp430.zig @@ -136,7 +136,7 @@ export fn memset(dest: [*]u8, ch: u8, count: usize) callconv(.c) [*]u8 { _ = count; // R14 asm volatile ( \\ MOV R12, R5 - \\ ADD R5, R14 + \\ ADD R14, R5 \\memset_loop: \\ CMP R5, R12 \\ JEQ memset_done @@ -144,7 +144,7 @@ export fn memset(dest: [*]u8, ch: u8, count: usize) callconv(.c) [*]u8 { \\ INC R12 \\ JMP memset_loop \\memset_done: - \\ SUB R12, R14 + \\ SUB R14, R12 ::: .{ .r5 = true, // r12 doesn't go in the clobbers because it is restored before exiting @@ -160,8 +160,8 @@ export fn memcpy(dest: [*]u8, src: [*]const u8, count: usize) callconv(.c) [*]u8 _ = src; // R13 _ = count; // R14 asm volatile ( - \\ MOV R5, R12 - \\ ADD R5, R14 + \\ MOV R12, R5 + \\ ADD R14, R5 \\memcpy_loop: \\ CMP R5, R12 \\ JEQ memcpy_done @@ -169,7 +169,7 @@ export fn memcpy(dest: [*]u8, src: [*]const u8, count: usize) callconv(.c) [*]u8 \\ INC R12 \\ INC R13 \\memcpy_done: - \\ SUB R12, R14 + \\ SUB R14, R12 ::: .{ .r5 = true, // r12 doesn't go in the clobbers because it is restored before exiting