From e073e48395254e52fee11b5524d217fc294c6375 Mon Sep 17 00:00:00 2001 From: So1aric Date: Sun, 6 Sep 2026 22:42:59 +0800 Subject: [PATCH 1/2] wch(ch32h): add initial support for CH32H417 LED toggling works, but dual-core untested. --- build.zig | 2 + build.zig.zon | 1 + examples/wch/ch32h/build.zig | 26 + examples/wch/ch32h/build.zig.zon | 14 + examples/wch/ch32h/src/v3f.zig | 35 + examples/wch/ch32h/src/v5f.zig | 35 + port/wch/ch32h/build.zig | 195 + port/wch/ch32h/build.zig.zon | 16 + port/wch/ch32h/src/chips/ch32h417.svd | 66898 ++++++++++++++++ port/wch/ch32h/src/cpus/main.zig | 542 + port/wch/ch32h/src/cpus/qingkev3f.zig | 179 + port/wch/ch32h/src/cpus/qingkev5f.zig | 181 + port/wch/ch32h/src/hals/ch32h417.zig | 17 + .../wch/ch32h/tools/merge_dual_core_image.zig | 108 + 14 files changed, 68249 insertions(+) create mode 100644 examples/wch/ch32h/build.zig create mode 100644 examples/wch/ch32h/build.zig.zon create mode 100644 examples/wch/ch32h/src/v3f.zig create mode 100644 examples/wch/ch32h/src/v5f.zig create mode 100644 port/wch/ch32h/build.zig create mode 100644 port/wch/ch32h/build.zig.zon create mode 100644 port/wch/ch32h/src/chips/ch32h417.svd create mode 100644 port/wch/ch32h/src/cpus/main.zig create mode 100644 port/wch/ch32h/src/cpus/qingkev3f.zig create mode 100644 port/wch/ch32h/src/cpus/qingkev5f.zig create mode 100644 port/wch/ch32h/src/hals/ch32h417.zig create mode 100644 port/wch/ch32h/tools/merge_dual_core_image.zig diff --git a/build.zig b/build.zig index 52eea883e..c4ba1d7df 100644 --- a/build.zig +++ b/build.zig @@ -31,6 +31,7 @@ const port_list: []const struct { .{ .name = "rp2xxx", .dep_name = "port/raspberrypi/rp2xxx" }, .{ .name = "stm32", .dep_name = "port/stmicro/stm32" }, .{ .name = "ch32v", .dep_name = "port/wch/ch32v" }, + .{ .name = "ch32h", .dep_name = "port/wch/ch32h" }, .{ .name = "msp430", .dep_name = "port/texasinstruments/msp430" }, .{ .name = "mspm0", .dep_name = "port/texasinstruments/mspm0" }, .{ .name = "tm4c", .dep_name = "port/texasinstruments/tm4c" }, @@ -70,6 +71,7 @@ pub const PortSelect = struct { rp2xxx: bool = false, stm32: bool = false, ch32v: bool = false, + ch32h: bool = false, msp430: bool = false, mspm0: bool = false, tm4c: bool = false, diff --git a/build.zig.zon b/build.zig.zon index f64afda82..31de2b272 100644 --- a/build.zig.zon +++ b/build.zig.zon @@ -45,6 +45,7 @@ .@"port/texasinstruments/mspm0" = .{ .path = "port/texasinstruments/mspm0", .lazy = true }, .@"port/texasinstruments/tm4c" = .{ .path = "port/texasinstruments/tm4c", .lazy = true }, .@"port/wch/ch32v" = .{ .path = "port/wch/ch32v", .lazy = true }, + .@"port/wch/ch32h" = .{ .path = "port/wch/ch32h", .lazy = true }, }, .paths = .{ "README.md", diff --git a/examples/wch/ch32h/build.zig b/examples/wch/ch32h/build.zig new file mode 100644 index 000000000..e0b550f45 --- /dev/null +++ b/examples/wch/ch32h/build.zig @@ -0,0 +1,26 @@ +const std = @import("std"); +const microzig = @import("microzig"); + +const MicroBuild = microzig.MicroBuild(.{ + .ch32h = true, +}); + +pub fn build(b: *std.Build) void { + const optimize = b.standardOptimizeOption(.{ .preferred_optimize_mode = .small }); + + const mz_dep = b.dependency("microzig", .{}); + const mb = MicroBuild.init(b, mz_dep) orelse return; + + const fw = mb.ports.ch32h.addDualCoreFirmware(mb, .{ + .name = "dual_blinky", + .v3f_root_source_file = b.path("src/v3f.zig"), + .v5f_root_source_file = b.path("src/v5f.zig"), + .optimize = optimize, + }); + + mb.ports.ch32h.installFirmware(mb, fw); + + // // Also install the individual per-core ELFs for debugging. + // mb.install_firmware(fw.v3f, .{ .format = .elf }); + // mb.install_firmware(fw.v5f, .{ .format = .elf }); +} diff --git a/examples/wch/ch32h/build.zig.zon b/examples/wch/ch32h/build.zig.zon new file mode 100644 index 000000000..466b3885e --- /dev/null +++ b/examples/wch/ch32h/build.zig.zon @@ -0,0 +1,14 @@ +.{ + .name = .examples_wch_ch32h, + .fingerprint = 0x98c6b66930eca2b, + .version = "0.0.0", + .dependencies = .{ + .microzig = .{ .path = "../../.." }, + }, + + .paths = .{ + "build.zig", + "build.zig.zon", + "src", + }, +} diff --git a/examples/wch/ch32h/src/v3f.zig b/examples/wch/ch32h/src/v3f.zig new file mode 100644 index 000000000..621631a2b --- /dev/null +++ b/examples/wch/ch32h/src/v3f.zig @@ -0,0 +1,35 @@ +const microzig = @import("microzig"); + +pub const panic = microzig.panic; + +pub const std_options = microzig.std_options(.{}); + +comptime { + _ = microzig.export_startup(); +} + +const RCC = microzig.chip.peripherals.RCC; +const GPIOC = microzig.chip.peripherals.GPIOC; + +const pin: u4 = 2; + +fn delay(cycles: u32) void { + for (0..cycles) |_| { + asm volatile ("nop"); + } +} + +pub fn main() !void { + // Enable the GPIOA peripheral clock (IOPAEN = RCC_HB2PCENR bit 2). + RCC.HB2PCENR.modify(.{ .IOPCEN = 1 }); + + // PC2: general purpose open-drain output, 50 MHz. + GPIOC.CFGLR.modify(.{ .MODE2 = 0b11, .CNF2 = 0b01 }); + + while (true) { + microzig.hal.gpio.write(GPIOC, pin, 1); + delay(100_000); + microzig.hal.gpio.write(GPIOC, pin, 0); + delay(100_000); + } +} diff --git a/examples/wch/ch32h/src/v5f.zig b/examples/wch/ch32h/src/v5f.zig new file mode 100644 index 000000000..e906e4463 --- /dev/null +++ b/examples/wch/ch32h/src/v5f.zig @@ -0,0 +1,35 @@ +const microzig = @import("microzig"); + +pub const panic = microzig.panic; + +pub const std_options = microzig.std_options(.{}); + +comptime { + _ = microzig.export_startup(); +} + +const RCC = microzig.chip.peripherals.RCC; +const GPIOA = microzig.chip.peripherals.GPIOA; + +const pin: u4 = 1; + +fn delay(cycles: u32) void { + for (0..cycles) |_| { + asm volatile ("nop"); + } +} + +pub fn main() !void { + // Enable the GPIOA peripheral clock (IOPAEN = RCC_HB2PCENR bit 2). + RCC.HB2PCENR.modify(.{ .IOPAEN = 1 }); + + // PA1: general purpose push-pull output, 50 MHz (MODE=0b11, CNF=0b00). + GPIOA.CFGLR.modify(.{ .MODE1 = 0b11, .CNF1 = 0b00 }); + + while (true) { + microzig.hal.gpio.write(GPIOA, pin, 1); + delay(250_000); + microzig.hal.gpio.write(GPIOA, pin, 0); + delay(250_000); + } +} diff --git a/port/wch/ch32h/build.zig b/port/wch/ch32h/build.zig new file mode 100644 index 000000000..68845d474 --- /dev/null +++ b/port/wch/ch32h/build.zig @@ -0,0 +1,195 @@ +const std = @import("std"); +const microzig = @import("microzig/build-internals"); + +const Self = @This(); + +const KiB = 1024; + +pub fn build(b: *std.Build) void { + _ = b; +} + +pub const default_v5f_image_offset: u64 = 0x10000; +pub const total_flash_size: u64 = 960 * KiB; + +chips: struct { + ch32h417_v3f: *const microzig.Target, + ch32h417_v5f: *const microzig.Target, +}, + +boards: struct {}, + +fn create_core( + dep: *std.Build.Dependency, + cpu_name: []const u8, + cpu_impl_file: std.Build.LazyPath, + memory_regions: []const microzig.MemoryRegion, +) *microzig.Target { + const b = dep.builder; + + const cpu_imports = b.allocator.dupe(std.Build.Module.Import, &.{ + .{ + .name = "riscv32-common", + .module = b.dependency("microzig/modules/riscv32-common", .{}).module("riscv32-common"), + }, + .{ + .name = "cpu_impl", + .module = std.Build.Module.create(b, .{ .root_source_file = cpu_impl_file }), + }, + }) catch @panic("out of memory"); + + const core = b.allocator.create(microzig.Target) catch @panic("out of memory"); + core.* = .{ + .dep = dep, + .preferred_binary_format = .binary, + .zig_target = .{ + .cpu_arch = .riscv32, + .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 }, + .cpu_features_add = cpu_common_features, + .os_tag = .freestanding, + .abi = .eabi, + }, + .cpu = .{ + .name = cpu_name, + .root_source_file = dep.path("src/cpus/main.zig"), + .imports = cpu_imports, + }, + .chip = .{ + .name = "CH32H417", + .url = "https://www.wch-ic.com/products/CH32H417.html", + .register_definition = .{ .svd = b.path("src/chips/ch32h417.svd") }, + .memory_regions = memory_regions, + }, + .hal = .{ + .root_source_file = dep.path("src/hals/ch32h417.zig"), + }, + }; + + return core; +} + +const cpu_common_features = std.Target.riscv.featureSet(&.{ + .i, .m, .a, .f, .c, .b, .xwchc, .zicsr, .zifencei, +}); + +pub fn init(dep: *std.Build.Dependency) ?Self { + // const b = dep.builder; + + const chip_v3f = create_core(dep, "qingkev3f", dep.path("src/cpus/qingkev3f.zig"), &.{ + .{ .name = "FLASH", .tag = .flash, .offset = 0x0000_0000, .length = default_v5f_image_offset, .access = .rx }, + .{ .name = "SRAM", .tag = .ram, .offset = 0x2010_0000, .length = 512 * KiB, .access = .rwx }, + }); + const chip_v5f = create_core(dep, "qingkev5f", dep.path("src/cpus/qingkev5f.zig"), &.{ + // V5F image lives right behind the V3F image in the merged binary. + .{ .name = "FLASH", .tag = .flash, .offset = default_v5f_image_offset, .length = total_flash_size - default_v5f_image_offset, .access = .rx }, + // DTCM: 256 KB zero-wait data RAM, private to the V5F. + // Listed first so the default stack lands at its end. + .{ .name = "DTCM", .tag = .ram, .offset = 0x200C_0000, .length = 256 * KiB, .access = .rw }, + // ITCM: 128 KB zero-wait code RAM, private to the V5F. + .{ .name = "ITCM", .tag = .ram, .offset = 0x200A_0000, .length = 128 * KiB, .access = .rwx }, + }); + + return .{ + .chips = .{ + .ch32h417_v3f = chip_v3f, + .ch32h417_v5f = chip_v5f, + }, + .boards = .{}, + }; +} + +/// Options for building a dual-core (V3F + V5F) firmware image. +pub const DualCoreFirmwareOptions = struct { + /// Base name of the firmware; the per-core executables are named + /// `_v3f` / `_v5f`, the merged image `.bin`. + name: []const u8, + + /// Root source file of the V3F (boot core) application, e.g. `src/v3f.zig`. + v3f_root_source_file: std.Build.LazyPath, + + /// Root source file of the V5F (application core) application, e.g. `src/v5f.zig`. + v5f_root_source_file: std.Build.LazyPath, + + /// Optimization level for both cores. + optimize: std.builtin.OptimizeMode, +}; + +/// A pair of firmware builds plus their merged flash image. +pub fn DualCoreFirmware(comptime mb_type: type) type { + const Firmware = std.meta.Child(mb_type).Firmware; + return struct { + /// Firmware's name. + name: []const u8, + /// Firmware running on the V3F boot core (CORE0). + v3f: *Firmware, + /// Firmware running on the V5F application core (CORE1). + v5f: *Firmware, + /// Merged flash image. + merged_bin: std.Build.LazyPath, + }; +} + +/// Builds the V3F and V5F applications as two independent firmwares and merges +/// both flat binaries into one flash image, gap padded with 0xFF. +pub fn addDualCoreFirmware( + self: Self, + mb: anytype, + options: DualCoreFirmwareOptions, +) DualCoreFirmware(@TypeOf(mb)) { + const b = mb.builder; + + const fw_v3f = mb.add_firmware(.{ + .name = b.fmt("{s}_v3f", .{options.name}), + .root_source_file = options.v3f_root_source_file, + .target = self.chips.ch32h417_v3f, + .optimize = options.optimize, + }); + + const fw_v5f = mb.add_firmware(.{ + .name = b.fmt("{s}_v5f", .{options.name}), + .root_source_file = options.v5f_root_source_file, + .target = self.chips.ch32h417_v5f, + .optimize = options.optimize, + }); + + // Host tool that concatenates the two flat binaries at the given offset. + const merge_exe = b.addExecutable(.{ + .name = "merge_dual_core_image", + .root_module = b.createModule(.{ + .root_source_file = self.chips.ch32h417_v3f.dep.path("tools/merge_dual_core_image.zig"), + .target = b.graph.host, + .optimize = .ReleaseSafe, + }), + }); + + const merge_run = b.addRunArtifact(merge_exe); + merge_run.addFileArg(fw_v3f.get_emitted_elf()); + merge_run.addFileArg(fw_v5f.get_emitted_elf()); + merge_run.addArg(b.fmt("0x{x}", .{default_v5f_image_offset})); + const merged_bin = merge_run.addOutputFileArg(b.fmt("{s}.bin", .{options.name})); + + return .{ + .name = options.name, + .v3f = fw_v3f, + .v5f = fw_v5f, + .merged_bin = merged_bin, + }; +} + +/// Install the merged image at `firmware/.bin`. +pub fn installFirmware( + self: Self, + mb: anytype, + firmware: DualCoreFirmware(@TypeOf(mb)), +) void { + _ = self; + + const b = mb.builder; + + const install = b.addInstallFileWithDir( + firmware.merged_bin, + .{ .custom = "firmware" }, + b.fmt("{s}.bin", .{firmware.name}), + ); + b.getInstallStep().dependOn(&install.step); +} diff --git a/port/wch/ch32h/build.zig.zon b/port/wch/ch32h/build.zig.zon new file mode 100644 index 000000000..dff8d8b0d --- /dev/null +++ b/port/wch/ch32h/build.zig.zon @@ -0,0 +1,16 @@ +.{ + .name = .mz_port_wch_ch32h, + .version = "0.0.0", + .fingerprint = 0x731af18d92d6c086, + .dependencies = .{ + .@"microzig/build-internals" = .{ .path = "../../../build-internals" }, + .@"microzig/modules/riscv32-common" = .{ .path = "../../../modules/riscv32-common" }, + }, + .paths = .{ + "README.md", + "build.zig", + "build.zig.zon", + "src", + "tools", + }, +} diff --git a/port/wch/ch32h/src/chips/ch32h417.svd b/port/wch/ch32h/src/chips/ch32h417.svd new file mode 100644 index 000000000..854ac745a --- /dev/null +++ b/port/wch/ch32h/src/chips/ch32h417.svd @@ -0,0 +1,66898 @@ + + + WCH Ltd. + WCH + CH32H417 + 1.2 + CH32H417 View File + + + + 8 + + 32 + + 0x20 + 0x00 + 0xFFFFFFFF + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x00 + 0x400 + registers + + + RCC + RCC global interrupt + 35 + + + + CTLR + CTLR + Clock control register + 0x00 + 0x20 + 0x00000083 + + + HSION + Internal High Speed clock + enable + 0 + 1 + read-write + + + HSIRDY + Internal High Speed clock ready + flag + 1 + 1 + read-only + + + HSITRIM + Internal High Speed clock + trimming + 3 + 5 + read-write + + + HSEON + External High Speed clock + enable + 16 + 1 + read-write + + + HSERDY + External High Speed clock ready + flag + 17 + 1 + read-only + + + HSEBYP + External High Speed clock + Bypass + 18 + 1 + read-write + + + CSSON + Clock Security System + enable + 19 + 1 + read-write + + + USBHS_PLLON + USBHS PLL clock enable + 20 + 1 + read-write + + + USBHS_PLLRDY + USBHS PLL clock ready + flag + 21 + 1 + read-only + + + USBSS_PLLON + USBSS PLL clock enable + 22 + 1 + read-write + + + USBSS_PLLRDY + USBSS PLL clock ready + flag + 23 + 1 + read-only + + + PLLON + PLL clock enable + 24 + 1 + read-write + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + ETH_PLLON + ETH PLL clock enable + 26 + 1 + read-write + + + ETH_PLLRDY + ETH PLL clock ready flag + 27 + 1 + read-only + + + SERDES_PLLON + SERDES PLL clock enable + 28 + 1 + read-write + + + SERDES_PLLRDY + SERDES PLL clock ready flag + 29 + 1 + read-only + + + CSS_HSE_DIS + Upon the occurrence of an HSE failure event with CSSON enabled + 31 + 1 + read-write + + + + + CFGR0 + CFGR0 + Clock configuration register + (RCC_CFGR0) + 0x04 + 0x20 + 0x00000000 + + + SW + System clock Switch + 0 + 2 + read-write + + + SWS + System Clock Switch Status + 2 + 2 + read-only + + + HPRE + HB prescaler + 4 + 4 + read-write + + + PPRE1 + Timer prescaler + (PB1) + 8 + 3 + read-write + + + PPRE2 + TIMER or ADC clock prescaler + (PB2) + 11 + 3 + read-write + + + ADCPRE + ADC prescaler + 14 + 2 + read-write + + + FPRE + HCLK prescaler + 16 + 1 + read-write + + + PLLXTPRE + HSE divider for PLL entry + 17 + 1 + read-write + + + RGMIION + GMII clock gating enable + 21 + 1 + read-write + + + PIPEON + USBSS_PLL clock gating enable + 22 + 1 + read-write + + + UTMION + UTMI clock gating enable + 23 + 1 + read-write + + + MCO + Microcontroller clock + output + 24 + 4 + read-write + + + ADC_DUTY_SEL + ADC clock duty cycle selection + 30 + 1 + read-write + + + ADCSRC + ADC intput clock source selection + 31 + 1 + read-write + + + + + + PLLCFGR + PLLCFGR + PLL clock configuration register + (RCC_PLLCFGR) + 0x08 + 0x20 + 0x00000004 + + + PLLMUL + PLL clock multiplication factor + 0 + 5 + read-write + + + PLLSRC + PLL intput clock source selection + 5 + 3 + read-write + + + PLL_SRC_DIV + PLL intput clock source prescaler + 8 + 6 + read-write + + + SYSPLL_SEL + Switch the System clock to PLL selection + 28 + 3 + read-write + + + SYSPLL_GATE + Switch the System clock to PLL gate + 31 + 1 + read-write + + + + + + INTR + INTR + Clock interrupt register + (RCC_INTR) + 0x0C + 0x20 + 0x00000000 + + + LSIRDYF + LSI Ready Interrupt flag + 0 + 1 + read-only + + + LSERDYF + LSE Ready Interrupt flag + 1 + 1 + read-only + + + HSIRDYF + HSI Ready Interrupt flag + 2 + 1 + read-only + + + HSERDYF + HSE Ready Interrupt flag + 3 + 1 + read-only + + + PLLRDYF + PLL Ready Interrupt flag + 4 + 1 + read-only + + + ETHPLLRDYF + ETH Ready Interrupt flag + 5 + 1 + read-only + + + SERDESPLLRDYF + SERDES_PLL Ready Interrupt flag + 6 + 1 + read-only + + + CSSF + Clock Security System Interrupt + flag + 7 + 1 + read-only + + + LSIRDYIE + LSI Ready Interrupt Enable + 8 + 1 + read-write + + + LSERDYIE + LSE Ready Interrupt Enable + 9 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable + 10 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable + 11 + 1 + read-write + + + PLLRDYIE + PLL Ready Interrupt Enable + 12 + 1 + read-write + + + ETHPLLRDYIE + ETHPLL Ready Interrupt Enable + 13 + 1 + read-write + + + SERDESPLLRDYIE + SERDESPLL Ready Interrupt Enable + 14 + 1 + read-write + + + LSIRDYC + LSI Ready Interrupt Clear + 16 + 1 + write-only + + + LSERDYC + LSE Ready Interrupt Clear + 17 + 1 + write-only + + + HSIRDYC + HSI Ready Interrupt Clear + 18 + 1 + write-only + + + HSERDYC + HSE Ready Interrupt Clear + 19 + 1 + write-only + + + PLLRDYC + PLL Ready Interrupt Clear + 20 + 1 + write-only + + + ETHPLLRDYC + ETH PLL Ready Interrupt Clear + 21 + 1 + write-only + + + SERDESPLLRDYC + SERDES Ready Interrupt Clear + 22 + 1 + write-only + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + + + HB2PRSTR + HB2PRSTR + HB2 peripheral reset register + (RCC_HB2PRSTR) + 0x10 + 0x20 + read-write + 0x00000000 + + + AFIORST + Alternate function I/O + reset + 0 + 1 + + + HSADCRST + HSADC reset + 1 + 1 + + + IOPARST + IO port A reset + 2 + 1 + + + IOPBRST + IO port B reset + 3 + 1 + + + IOPCRST + IO port C reset + 4 + 1 + + + IOPDRST + IO port D reset + 5 + 1 + + + IOPERST + IO port E reset + 6 + 1 + + + IOPFRST + IO port F reset + 7 + 1 + + + ADC1RST + ADC 1 interface reset + 9 + 1 + + + ADC2RST + ADC 2 interface reset + 10 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + TIM8RST + TIM8 timer reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + I2C4RST + I2C4 reset + 15 + 1 + + + SAIRST + SAI reset + 16 + 1 + + + SDIORST + SDIO reset + 18 + 1 + + + TIM9RST + TIM9 timer reset + 19 + 1 + + + TIM10RST + TIM10 timer reset + 20 + 1 + + + TIM11RST + TIM11 timer reset + 21 + 1 + + + TIM12RST + TIM12 timer reset + 22 + 1 + + + OPCMRST + OPA and CMP reset + 23 + 1 + + + DFSDMRST + DFSDM reset + 25 + 1 + + + ECDCRST + ECDC reset + 26 + 1 + + + GPHARST + GPHA reset + 27 + 1 + + + LTDCRST + LTDC reset + 30 + 1 + + + I3CRST + I3C reset + 31 + 1 + + + + + HB1PRSTR + HB1PRSTR + HB1 peripheral reset register + (RCC_HB1PRSTR) + 0x14 + 0x20 + read-write + 0x00000000 + + + TIM2RST + Timer 2 reset + 0 + 1 + + + TIM3RST + Timer 3 reset + 1 + 1 + + + TIM4RST + Timer 4 reset + 2 + 1 + + + TIM5RST + Timer 5 reset + 3 + 1 + + + TIM6RST + Timer 6 reset + 4 + 1 + + + TIM7RST + Timer 7 reset + 5 + 1 + + + USART6RST + USART 6 reset + 6 + 1 + + + USART7RST + USART 7 reset + 7 + 1 + + + USART8RST + USART 8 reset + 8 + 1 + + + LPTIM1RST + LPTIM1 reset + 9 + 1 + + + LPTIM2RST + LPTIM2 reset + 10 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + QSPI1RST + QSPI1 reset + 12 + 1 + + + QSPI2RST + QSPI2 reset + 13 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + SPI4RST + SPI4 reset + 16 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + USART4RST + USART 4 reset + 19 + 1 + + + USART5RST + USART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + CAN3RST + CAN3 reset + 24 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + BKPRST + Backup interface reset + 27 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DACRST + DAC interface reset + 29 + 1 + + + I2C3RST + I2C3 reset + 30 + 1 + + + SWPMIRST + SWPMI reset + 31 + 1 + + + + + HBPCENR + HBPCENR + HB Peripheral Clock enable register + (RCC_HBPCENR) + 0x18 + 0x20 + read-write + 0x00000000 + + + DMA1EN + DMA clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + FMCEN + FMC clock enable + 8 + 1 + + + RNGEN + RNG clock enable + 9 + 1 + + + SDMMCEN + SDMMC clock enable + 10 + 1 + + + USBHSEN + USBHS clock enable + 11 + 1 + + + USBSSEN + USBSS clock enable + 12 + 1 + + + DVPEN + DVP clock enable + 13 + 1 + + + ETHMACEN + Ethernet MAC clock enable + 14 + 1 + + + OTGFSEN + USBFS_OTG_FS clock + enable + 17 + 1 + + + UHSIFEN + UHSIF clock + enable + 18 + 1 + + + USBPDEN + USBPD clock enable + 19 + 1 + + + SERDESEN + SERDES clock enable + 20 + 1 + + + POICEN + POIC clock enable + 22 + 1 + + + + + HB2PCENR + HB2PCENR + HB2 peripheral clock enable register + (RCC_HB2PCENR) + 0x1C + 0x20 + read-write + 0x00000000 + + + AFIOEN + Alternate function I/O clock + enable + 0 + 1 + + + HSADCEN + HSADC clock + enable + 1 + 1 + + + IOPAEN + I/O port A clock enable + 2 + 1 + + + IOPBEN + I/O port B clock enable + 3 + 1 + + + IOPCEN + I/O port C clock enable + 4 + 1 + + + IOPDEN + I/O port D clock enable + 5 + 1 + + + IOPEEN + I/O port E clock enable + 6 + 1 + + + IOPFEN + I/O port F clock enable + 7 + 1 + + + ADC1EN + ADC1 interface clock + enable + 9 + 1 + + + ADC2EN + ADC 2 interface clock + enable + 10 + 1 + + + TIM1EN + TIM1 Timer clock enable + 11 + 1 + + + SPI1EN + SPI 1 clock enable + 12 + 1 + + + TIM8EN + TIM8 Timer clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + I2C4EN + I2C4 clock enable + 15 + 1 + + + SAIEN + SAI clock enable + 16 + 1 + + + SDIOEN + SDIO clock enable + 18 + 1 + + + TIM9EN + TIM9 Timer clock enable + 19 + 1 + + + TIM10EN + TIM10 Timer clock enable + 20 + 1 + + + TIM11EN + TIM11 Timer clock enable + 21 + 1 + + + TIM12EN + TIM12 Timer clock enable + 22 + 1 + + + OPCMEN + OPA and CMP clock enable + 23 + 1 + + + DFSDMEN + DFSDM clock enable + 25 + 1 + + ECDCEN + ECDC clock enable + 26 + 1 + + GPHAEN + GPHA clock enable + 27 + 1 + + + LTDCEN + LTDC clock enable + 30 + 1 + + + I3CEN + I3C clock enable + 31 + 1 + + + + + HB1PCENR + HB1PCENR + HB1 peripheral clock enable register + (RCC_HB1PCENR) + 0x20 + 0x20 + read-write + 0x00000000 + + + TIM2EN + Timer 2 clock enable + 0 + 1 + + + TIM3EN + Timer 3 clock enable + 1 + 1 + + + TIM4EN + Timer 4 clock enable + 2 + 1 + + + TIM5EN + Timer 5 clock enable + 3 + 1 + + + TIM6EN + Timer 6 clock enable + 4 + 1 + + + TIM7EN + Timer 7 clock enable + 5 + 1 + + + USART6EN + USART 6 clock enable + 6 + 1 + + + USART7EN + USART 7 clock enable + 7 + 1 + + + USART8EN + USART 8 clock enable + 8 + 1 + + + LPTIM1EN + LPTIM1 clock enable + 9 + 1 + + + LPTIM2EN + LPTIM2 clock enable + 10 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + QSPI1EN + QSPI1 clock enable + 12 + 1 + + + QSPI2EN + QSPI2 clock enable + 13 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + SPI4EN + SPI4 clock enable + 16 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + USART5EN + USART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + CAN3EN + CAN3 clock enable + 24 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + BKPEN + Backup interface clock + enable + 27 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DACEN + DAC interface clock enable + 29 + 1 + + + I2C3EN + I2C3 clock enable + 30 + 1 + + + SWPMIEN + SWPMI clock enable + 31 + 1 + + + + + + BDCTLR + BDCTLR + Backup domain control register + (RCC_BDCTLR) + 0x24 + 0x20 + 0x00000000 + + + LSEON + External Low Speed oscillator + enable + 0 + 1 + read-write + + + LSERDY + External Low Speed oscillator + ready + 1 + 1 + read-only + + + LSEBYP + External Low Speed oscillator + bypass + 2 + 1 + read-write + + + CCO + calibrate the clock output selection + 3 + 1 + read-write + + + ASOE + TAMPER pin enables pulse output + 4 + 1 + read-write + + + ASOS + TAMPER pin alarm/second pulse output + 5 + 1 + read-write + + + RTCSEL + RTC clock source selection + 6 + 2 + read-write + + + RTCEN + RTC clock enable + 8 + 1 + read-write + + + RTCCAL + RTC calibration value + 9 + 7 + read-write + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + + + + RSTSCKR + RSTSCKR + Control/status register + (RCC_RSTSCKR) + 0x28 + 0x20 + 0x08000000 + + + LSION + Internal low speed oscillator + enable + 0 + 1 + read-write + + + LSIRDY + Internal low speed oscillator + ready + 1 + 1 + read-only + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + LKUPRSTF + LOCKUP reset flag + 31 + 1 + read-write + + + + + + HBRSTR + HBRSTR + HB reset register + (RCC_PHBRSTR) + 0x2C + 0x20 + 0x00000000 + + + DMA1RST + DMA1 reset + 0 + 1 + read-write + + + DMA2RST + DMA2 reset + 1 + 1 + read-write + + + FMCRST + FMC reset + 8 + 1 + read-write + + + RNGRST + RNG reset + 9 + 1 + read-write + + + SDMMCRST + SDMMC reset + 10 + 1 + read-write + + + USBHSRST + USBHS reset + 11 + 1 + read-write + + + USBSSRST + USBSS reset + 12 + 1 + read-write + + + DVPRST + DVP reset + 13 + 1 + read-write + + + ETHMACRST + Ethernet MAC reset + 14 + 1 + read-write + + + OTGFSRST + USBFS_OTG_FS eset + 17 + 1 + read-write + + + UHSIFRST + UHSIF reset + 18 + 1 + read-write + + + USBPDRST + USBPD reset + 19 + 1 + read-write + + + SERDESRST + SERDES reset + 20 + 1 + read-write + + + POICRST + POIC reset + 22 + 1 + read-write + + + + + + CFGR2 + CFGR2 + Clock configuration register2 + (RCC_CFGR2) + 0x30 + 0x20 + read-write + 0x00000000 + + + UHSIFDIV + UHSIF division factor + 0 + 6 + + + UHSIFSRC + UHSIF clock source selection + 6 + 2 + + + LTDCDIV + LTDC division factor + 8 + 6 + + + LTDCSRC + LTDC clock source selection + 14 + 2 + + + USBFSDIV + USBFS 48M division factor + 16 + 4 + + + USBFSSRC + USBFS 48M clock source selection + 20 + 1 + + + RNGSRC + RNG clock source selection + 23 + 1 + + + I2S2SRC + I2S2 clock source selection + 24 + 1 + + + I2S3SRC + I2S3 clock source selection + 25 + 1 + + + HSADCSRC + HSADC clock source selection + 28 + 2 + + + ETH1GSRC + ETH1G clock source selection + 30 + 2 + + + + + PLLCFGR2 + PLLCFGR2 + PLL Clock configuration register2 + (RCC_PLLCFGR2) + 0x34 + 0x20 + read-write + 0x00080020 + + + USBHSPLLSRC + USBHS clock source selection + 0 + 2 + + + USBHSPLL_REFSEL + USBHS_PLL reference clock frequency selection + 2 + 2 + + + USBSSPLL_REFSEL + USBSS_PLL reference clock frequency selection + 4 + 2 + + + USBHSPLL_IN_DIV + USBHS_PLL intput clock source SYS_PLL division setting + 8 + 5 + + + SERDESPLL_MUL + SERDESPLL clock multiplication factor + 16 + 4 + + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x00 + 0x400 + registers + + + + CTLR + CTLR + Power control register + (PWR_CTRL) + 0x00 + 0x20 + read-write + 0x00000000 + + + LPDS + Low Power Deep Sleep + 0 + 1 + + + PVDE + Power Voltage Detector + Enable + 4 + 1 + + + PLS + PVD Level Selection + 5 + 3 + + + DBP + Disable Backup Domain write + protection + 8 + 1 + + + VIO_SW_CR + VIO18 power regulation mode selection + 9 + 1 + + + VSEL_VIO18 + VIO18 power supply adjustment position + 10 + 3 + + + + + + CSR + CSR + Power control register + (PWR_CSR) + 0x04 + 0x20 + 0x00000000 + + + PVDO + PVD Output + 0 + 1 + read-only + + + VIO18_SR + VIO18 power supply initial status indicator + 8 + 2 + read-only + + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x00 + 0x400 + registers + + + + DATAR + DATAR + Data register + 0x00 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDATAR + IDATAR + Independent Data register + 0x4 + 0x08 + read-write + 0x00 + + + IDR + Independent Data register + 0 + 8 + + + + + CTLR + CTLR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x00 + 0x400 + registers + + + RTC + RTC global interrupt + 143 + + + RTCAlarm + RTC Alarm-clock interrupt + 66 + + + + CTLRH + CTLRH + RTC Control Register High + 0x00 + 0x10 + read-write + 0x0000 + + + SECIE + Second interrupt Enable + 0 + 1 + + + ALRIE + Alarm interrupt Enable + 1 + 1 + + + OWIE + Overflow interrupt Enable + 2 + 1 + + + + + CTLRL + CTLRL + RTC Control Register Low + 0x04 + 0x10 + 0x0020 + + + SECF + Second Flag + 0 + 1 + read-write + + + ALRF + Alarm Flag + 1 + 1 + read-write + + + OWF + Overflow Flag + 2 + 1 + read-write + + + RSF + Registers Synchronized + Flag + 3 + 1 + read-write + + + CNF + Configuration Flag + 4 + 1 + read-write + + + RTOFF + RTC operation OFF + 5 + 1 + read-only + + + + + PSCRH + PSCRH + RTC Prescaler Load Register + High + 0x08 + 0x10 + write-only + 0x0000 + + + PRL + RTC Prescaler Load Register + High + 0 + 4 + + + + + PSCRL + PSCRL + RTC Prescaler Load Register + Low + 0xC + 0x10 + write-only + 0x0000 + + + PRL + RTC Prescaler Divider Register + Low + 0 + 16 + + + + + DIVH + DIVH + RTC Prescaler Divider Register + High + 0x10 + 0x10 + read-only + 0x0000 + + + DIV + RTC prescaler divider register + high + 0 + 4 + + + + + DIVL + DIVL + RTC Prescaler Divider Register + Low + 0x14 + 0x10 + read-only + 0x0000 + + + DIV + RTC prescaler divider register + Low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x10 + read-write + 0x0000 + + + CNTH + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x10 + read-write + 0x0000 + + + CNTL + RTC counter register Low + 0 + 16 + + + + + ALRMH + ALRMH + RTC Alarm Register High + 0x20 + 0x10 + write-only + 0x0000 + + + ALR + RTC alarm register high + 0 + 16 + + + + + ALRML + ALRML + RTC Alarm Register Low + 0x24 + 0x10 + write-only + 0x0000 + + + ALR + RTC alarm register low + 0 + 16 + + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + CTLR + CTLR + Key register (IWDG_CTLR) + 0x0 + 0x20 + write-only + 0x0000 + + + KEY + Key value + 0 + 16 + write-only + + + + + PSCR + PSCR + Prescaler register (IWDG_PSCR) + 0x4 + 0x20 + read-write + 0x0000 + + + PR + Prescaler divider + 0 + 3 + read-write + + + + + RLDR + RLDR + Reload register (IWDG_RLDR) + 0x8 + 0x20 + read-write + 0x0FFF + + + RL + Watchdog counter reload + value + 0 + 12 + read-write + + + + + STATR + STATR + Status register (IWDG_SR) + 0xC + 0x20 + read-only + 0x0000 + + + PVU + Watchdog prescaler value + update + 0 + 1 + read-only + + + RVU + Watchdog counter reload value + update + 1 + 1 + read-only + + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 32 + + + + CTLR + CTLR + Control register (WWDG_CR) + 0x0 + 0x20 + read-write + 0x007F + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + read-write + + + WDGA + Activation bit + 7 + 1 + read-write + + + + + CFGR + CFGR + Configuration register + (WWDG_CFGR) + 0x4 + 0x20 + read-write + 0x007F + + + W + 7-bit window value + 0 + 7 + read-write + + + WDGTB + Timer Base + 7 + 2 + read-write + + + EWI + Early Wakeup Interrupt + 9 + 1 + read-write + + + + + STATR + STATR + Status register (WWDG_SR) + 0x8 + 0x20 + read-write + 0x0000 + + + EWIF + Early Wakeup Interrupt Flag + 0 + 1 + read-write + + + + + + + + GPIOA + General purpose I/O + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + Port configuration register low + (GPIOn_CFGLR) + 0x0 + 0x20 + read-write + 0x44444444 + + + MODE0 + Port n.0 mode bits + 0 + 2 + + + CNF0 + Port n.0 configuration + bits + 2 + 2 + + + MODE1 + Port n.1 mode bits + 4 + 2 + + + CNF1 + Port n.1 configuration + bits + 6 + 2 + + + MODE2 + Port n.2 mode bits + 8 + 2 + + + CNF2 + Port n.2 configuration + bits + 10 + 2 + + + MODE3 + Port n.3 mode bits + 12 + 2 + + + CNF3 + Port n.3 configuration + bits + 14 + 2 + + + MODE4 + Port n.4 mode bits + 16 + 2 + + + CNF4 + Port n.4 configuration + bits + 18 + 2 + + + MODE5 + Port n.5 mode bits + 20 + 2 + + + CNF5 + Port n.5 configuration + bits + 22 + 2 + + + MODE6 + Port n.6 mode bits + 24 + 2 + + + CNF6 + Port n.6 configuration + bits + 26 + 2 + + + MODE7 + Port n.7 mode bits + 28 + 2 + + + CNF7 + Port n.7 configuration + bits + 30 + 2 + + + + + CFGHR + CFGHR + Port configuration register high + (GPIOn_CFGHR) + 0x4 + 0x20 + read-write + 0x44444444 + + + MODE8 + Port n.8 mode bits + 0 + 2 + + + CNF8 + Port n.8 configuration + bits + 2 + 2 + + + MODE9 + Port n.9 mode bits + 4 + 2 + + + CNF9 + Port n.9 configuration + bits + 6 + 2 + + + MODE10 + Port n.10 mode bits + 8 + 2 + + + CNF10 + Port n.10 configuration + bits + 10 + 2 + + + MODE11 + Port n.11 mode bits + 12 + 2 + + + CNF11 + Port n.11 configuration + bits + 14 + 2 + + + MODE12 + Port n.12 mode bits + 16 + 2 + + + CNF12 + Port n.12 configuration + bits + 18 + 2 + + + MODE13 + Port n.13 mode bits + 20 + 2 + + + CNF13 + Port n.13 configuration + bits + 22 + 2 + + + MODE14 + Port n.14 mode bits + 24 + 2 + + + CNF14 + Port n.14 configuration + bits + 26 + 2 + + + MODE15 + Port n.15 mode bits + 28 + 2 + + + CNF15 + Port n.15 configuration + bits + 30 + 2 + + + + + INDR + INDR + Port input data register + (GPIOn_INDR) + 0x8 + 0x20 + read-only + 0x00000000 + + + IDR0 + Port input data + 0 + 1 + + + IDR1 + Port input data + 1 + 1 + + + IDR2 + Port input data + 2 + 1 + + + IDR3 + Port input data + 3 + 1 + + + IDR4 + Port input data + 4 + 1 + + + IDR5 + Port input data + 5 + 1 + + + IDR6 + Port input data + 6 + 1 + + + IDR7 + Port input data + 7 + 1 + + + IDR8 + Port input data + 8 + 1 + + + IDR9 + Port input data + 9 + 1 + + + IDR10 + Port input data + 10 + 1 + + + IDR11 + Port input data + 11 + 1 + + + IDR12 + Port input data + 12 + 1 + + + IDR13 + Port input data + 13 + 1 + + + IDR14 + Port input data + 14 + 1 + + + IDR15 + Port input data + 15 + 1 + + + + + OUTDR + OUTDR + Port output data register + (GPIOn_OUTDR) + 0xC + 0x20 + read-write + 0x00000000 + + + ODR0 + Port output data + 0 + 1 + + + ODR1 + Port output data + 1 + 1 + + + ODR2 + Port output data + 2 + 1 + + + ODR3 + Port output data + 3 + 1 + + + ODR4 + Port output data + 4 + 1 + + + ODR5 + Port output data + 5 + 1 + + + ODR6 + Port output data + 6 + 1 + + + ODR7 + Port output data + 7 + 1 + + + ODR8 + Port output data + 8 + 1 + + + ODR9 + Port output data + 9 + 1 + + + ODR10 + Port output data + 10 + 1 + + + ODR11 + Port output data + 11 + 1 + + + ODR12 + Port output data + 12 + 1 + + + ODR13 + Port output data + 13 + 1 + + + ODR14 + Port output data + 14 + 1 + + + ODR15 + Port output data + 15 + 1 + + + + + BSHR + BSHR + Port bit set/reset register + (GPIOn_BSHR) + 0x10 + 0x20 + write-only + 0x00000000 + + + BS0 + Set bit 0 + 0 + 1 + + + BS1 + Set bit 1 + 1 + 1 + + + BS2 + Set bit 1 + 2 + 1 + + + BS3 + Set bit 3 + 3 + 1 + + + BS4 + Set bit 4 + 4 + 1 + + + BS5 + Set bit 5 + 5 + 1 + + + BS6 + Set bit 6 + 6 + 1 + + + BS7 + Set bit 7 + 7 + 1 + + + BS8 + Set bit 8 + 8 + 1 + + + BS9 + Set bit 9 + 9 + 1 + + + BS10 + Set bit 10 + 10 + 1 + + + BS11 + Set bit 11 + 11 + 1 + + + BS12 + Set bit 12 + 12 + 1 + + + BS13 + Set bit 13 + 13 + 1 + + + BS14 + Set bit 14 + 14 + 1 + + + BS15 + Set bit 15 + 15 + 1 + + + BR0 + Reset bit 0 + 16 + 1 + + + BR1 + Reset bit 1 + 17 + 1 + + + BR2 + Reset bit 2 + 18 + 1 + + + BR3 + Reset bit 3 + 19 + 1 + + + BR4 + Reset bit 4 + 20 + 1 + + + BR5 + Reset bit 5 + 21 + 1 + + + BR6 + Reset bit 6 + 22 + 1 + + + BR7 + Reset bit 7 + 23 + 1 + + + BR8 + Reset bit 8 + 24 + 1 + + + BR9 + Reset bit 9 + 25 + 1 + + + BR10 + Reset bit 10 + 26 + 1 + + + BR11 + Reset bit 11 + 27 + 1 + + + BR12 + Reset bit 12 + 28 + 1 + + + BR13 + Reset bit 13 + 29 + 1 + + + BR14 + Reset bit 14 + 30 + 1 + + + BR15 + Reset bit 15 + 31 + 1 + + + + + BCR + BCR + Port bit reset register + (GPIOn_BCR) + 0x14 + 0x20 + write-only + 0x00000000 + + + BR0 + Reset bit 0 + 0 + 1 + + + BR1 + Reset bit 1 + 1 + 1 + + + BR2 + Reset bit 1 + 2 + 1 + + + BR3 + Reset bit 3 + 3 + 1 + + + BR4 + Reset bit 4 + 4 + 1 + + + BR5 + Reset bit 5 + 5 + 1 + + + BR6 + Reset bit 6 + 6 + 1 + + + BR7 + Reset bit 7 + 7 + 1 + + + BR8 + Reset bit 8 + 8 + 1 + + + BR9 + Reset bit 9 + 9 + 1 + + + BR10 + Reset bit 10 + 10 + 1 + + + BR11 + Reset bit 11 + 11 + 1 + + + BR12 + Reset bit 12 + 12 + 1 + + + BR13 + Reset bit 13 + 13 + 1 + + + BR14 + Reset bit 14 + 14 + 1 + + + BR15 + Reset bit 15 + 15 + 1 + + + + + LCKR + LCKR + Port configuration lock + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LCK0 + Port A Lock bit 0 + 0 + 1 + + + LCK1 + Port A Lock bit 1 + 1 + 1 + + + LCK2 + Port A Lock bit 2 + 2 + 1 + + + LCK3 + Port A Lock bit 3 + 3 + 1 + + + LCK4 + Port A Lock bit 4 + 4 + 1 + + + LCK5 + Port A Lock bit 5 + 5 + 1 + + + LCK6 + Port A Lock bit 6 + 6 + 1 + + + LCK7 + Port A Lock bit 7 + 7 + 1 + + + LCK8 + Port A Lock bit 8 + 8 + 1 + + + LCK9 + Port A Lock bit 9 + 9 + 1 + + + LCK10 + Port A Lock bit 10 + 10 + 1 + + + LCK11 + Port A Lock bit 11 + 11 + 1 + + + LCK12 + Port A Lock bit 12 + 12 + 1 + + + LCK13 + Port A Lock bit 13 + 13 + 1 + + + LCK14 + Port A Lock bit 14 + 14 + 1 + + + LCK15 + Port A Lock bit 15 + 15 + 1 + + + LCKK + Lock key + 16 + 1 + + + + + + + + GPIOB + 0x40010C00 + + + + GPIOC + 0x40011000 + + + + GPIOD + 0x40011400 + + + + GPIOE + 0x40011800 + + + + GPIOF + 0x40011C00 + + + + AFIO + Alternate function I/O + AFIO + 0x40010000 + + 0x0 + 0x400 + registers + + + + PCFR1 + PCFR1 + AF remap and debug I/O configuration + register (AFIO_PCFR1) + 0x0 + 0x20 + 0x00000000 + + + PD0PD1_RM + PD0PD1 remapping + 0 + 1 + read-write + + + ADC1_ETRGINJ_RM + ADC1_ETRGINJ remapping + 2 + 1 + read-write + + + ADC1_ETRGREG_RM + ADC1_ETRGREG remapping + 1 + 1 + read-write + + + ADC2_ETRGINJ_RM + ADC2_ETRGINJ remapping + 4 + 1 + read-write + + + ADC2_ETRGREG_RM + ADC2_ETRGREG remapping + 3 + 1 + read-write + + + UHSIF_CLK_RM + UHSIF_CLK remapping + 6 + 2 + read-write + + + UHSIF_PORT_RM + UHSIF_PORT remapping + 8 + 2 + read-write + + + SDMMC_RM + SDMMC remapping + 10 + 2 + read-write + + + TIM2ITR1_RM + TIM2ITR1 remapping + 12 + 1 + read-write + + + VIO18_IO_HSLV + VIO18 IO speed configuration at low voltage + 16 + 1 + read-write + + + VIO33_IO_HSLV + VIO33 IO speed configuration at low voltage + 17 + 1 + read-write + + + VDD33_IO_HSLV + VDD33 IO speed configuration at low voltage + 18 + 1 + read-write + + + USBPD_CC_HVT + CC pin intput channel threshold adjustment + 20 + 1 + read-write + + + SW_CFG + Serial wire JTAG + configuration + 24 + 3 + read-write + + + + + + GPIOA_AFLR + GPIOA_AFLR + PA port multiplexing function register + 0x04 + 0x20 + 0x00000000 + + + AFR0 + selection of multiplexing function for pin 0 of PA port + 0 + 4 + read-write + + + AFR1 + selection of multiplexing function for pin 1 of PA port + 4 + 4 + read-write + + + AFR2 + selection of multiplexing function for pin 2 of PA port + 8 + 4 + read-write + + + AFR3 + selection of multiplexing function for pin 3 of PA port + 12 + 4 + read-write + + + AFR4 + selection of multiplexing function for pin 4 of PA port + 16 + 4 + read-write + + + AFR5 + selection of multiplexing function for pin 5 of PA port + 20 + 4 + read-write + + + AFR6 + selection of multiplexing function for pin 6 of PA port + 24 + 4 + read-write + + + AFR7 + selection of multiplexing function for pin 7 of PA port + 28 + 4 + read-write + + + + + + GPIOA_AFHR + GPIOA_AFHR + PA port multiplexing function register + 0x08 + 0x20 + 0x00000000 + + + AFR8 + selection of multiplexing function for pin 8 of PA port + 0 + 4 + read-write + + + AFR9 + selection of multiplexing function for pin 9 of PA port + 4 + 4 + read-write + + + AFR10 + selection of multiplexing function for pin 10 of PA port + 8 + 4 + read-write + + + AFR11 + selection of multiplexing function for pin 11 of PA port + 12 + 4 + read-write + + + AFR12 + selection of multiplexing function for pin 12 of PA port + 16 + 4 + read-write + + + AFR13 + selection of multiplexing function for pin 13 of PA port + 20 + 4 + read-write + + + AFR14 + selection of multiplexing function for pin 14 of PA port + 24 + 4 + read-write + + + AFR15 + selection of multiplexing function for pin 15 of PA port + 28 + 4 + read-write + + + + + + GPIOB_AFLR + GPIOB_AFLR + PB port multiplexing function register + 0x0C + 0x20 + 0x00000000 + + + AFR0 + selection of multiplexing function for pin 0 of PB port + 0 + 4 + read-write + + + AFR1 + selection of multiplexing function for pin 1 of PB port + 4 + 4 + read-write + + + AFR2 + selection of multiplexing function for pin 2 of PB port + 8 + 4 + read-write + + + AFR3 + selection of multiplexing function for pin 3 of PB port + 12 + 4 + read-write + + + AFR4 + selection of multiplexing function for pin 4 of PB port + 16 + 4 + read-write + + + AFR5 + selection of multiplexing function for pin 5 of PB port + 20 + 4 + read-write + + + AFR6 + selection of multiplexing function for pin 6 of PB port + 24 + 4 + read-write + + + AFR7 + selection of multiplexing function for pin 7 of PB port + 28 + 4 + read-write + + + + + + GPIOB_AFHR + GPIOB_AFHR + PB port multiplexing function register + 0x10 + 0x20 + 0x00000000 + + + AFR8 + selection of multiplexing function for pin 8 of PA port + 0 + 4 + read-write + + + AFR9 + selection of multiplexing function for pin 9 of PB port + 4 + 4 + read-write + + + AFR10 + selection of multiplexing function for pin 10 of PB port + 8 + 4 + read-write + + + AFR11 + selection of multiplexing function for pin 11 of PB port + 12 + 4 + read-write + + + AFR12 + selection of multiplexing function for pin 12 of PB port + 16 + 4 + read-write + + + AFR13 + selection of multiplexing function for pin 13 of PB port + 20 + 4 + read-write + + + AFR14 + selection of multiplexing function for pin 14 of PB port + 24 + 4 + read-write + + + AFR15 + selection of multiplexing function for pin 15 of PB port + 28 + 4 + read-write + + + + + + GPIOC_AFLR + GPIOC_AFLR + PC port multiplexing function register + 0x14 + 0x20 + 0x00000000 + + + AFR0 + selection of multiplexing function for pin 0 of PC port + 0 + 4 + read-write + + + AFR1 + selection of multiplexing function for pin 1 of PC port + 4 + 4 + read-write + + + AFR2 + selection of multiplexing function for pin 2 of PC port + 8 + 4 + read-write + + + AFR3 + selection of multiplexing function for pin 3 of PC port + 12 + 4 + read-write + + + AFR4 + selection of multiplexing function for pin 4 of PC port + 16 + 4 + read-write + + + AFR5 + selection of multiplexing function for pin 5 of PC port + 20 + 4 + read-write + + + AFR6 + selection of multiplexing function for pin 6 of PC port + 24 + 4 + read-write + + + AFR7 + selection of multiplexing function for pin 7 of PC port + 28 + 4 + read-write + + + + + + GPIOC_AFHR + GPIOC_AFHR + PC port multiplexing function register + 0x18 + 0x20 + 0x00000000 + + + AFR8 + selection of multiplexing function for pin 8 of PC port + 0 + 4 + read-write + + + AFR9 + selection of multiplexing function for pin 9 of PC port + 4 + 4 + read-write + + + AFR10 + selection of multiplexing function for pin 10 of PC port + 8 + 4 + read-write + + + AFR11 + selection of multiplexing function for pin 11 of PC port + 12 + 4 + read-write + + + AFR12 + selection of multiplexing function for pin 12 of PC port + 16 + 4 + read-write + + + AFR13 + selection of multiplexing function for pin 13 of PC port + 20 + 4 + read-write + + + AFR14 + selection of multiplexing function for pin 14 of PC port + 24 + 4 + read-write + + + AFR15 + selection of multiplexing function for pin 15 of PC port + 28 + 4 + read-write + + + + + + GPIOD_AFLR + GPIOD_AFLR + PD port multiplexing function register + 0x1C + 0x20 + 0x00000000 + + + AFR0 + selection of multiplexing function for pin 0 of PD port + 0 + 4 + read-write + + + AFR1 + selection of multiplexing function for pin 1 of PD port + 4 + 4 + read-write + + + AFR2 + selection of multiplexing function for pin 2 of PD port + 8 + 4 + read-write + + + AFR3 + selection of multiplexing function for pin 3 of PA port + 12 + 4 + read-write + + + AFR4 + selection of multiplexing function for pin 4 of PD port + 16 + 4 + read-write + + + AFR5 + selection of multiplexing function for pin 5 of PD port + 20 + 4 + read-write + + + AFR6 + selection of multiplexing function for pin 6 of PD port + 24 + 4 + read-write + + + AFR7 + selection of multiplexing function for pin 7 of PD port + 28 + 4 + read-write + + + + + + GPIOD_AFHR + GPIOD_AFHR + PD port multiplexing function register + 0x20 + 0x20 + 0x00000000 + + + AFR8 + selection of multiplexing function for pin 8 of PD port + 0 + 4 + read-write + + + AFR9 + selection of multiplexing function for pin 9 of PD port + 4 + 4 + read-write + + + AFR10 + selection of multiplexing function for pin 10 of PD port + 8 + 4 + read-write + + + AFR11 + selection of multiplexing function for pin 11 of PD port + 12 + 4 + read-write + + + AFR12 + selection of multiplexing function for pin 12 of PD port + 16 + 4 + read-write + + + AFR13 + selection of multiplexing function for pin 13 of PD port + 20 + 4 + read-write + + + AFR14 + selection of multiplexing function for pin 14 of PD port + 24 + 4 + read-write + + + AFR15 + selection of multiplexing function for pin 15 of PD port + 28 + 4 + read-write + + + + + + GPIOE_AFLR + GPIOE_AFLR + PE port multiplexing function register + 0x24 + 0x20 + 0x00000000 + + + AFR0 + selection of multiplexing function for pin 0 of PE port + 0 + 4 + read-write + + + AFR1 + selection of multiplexing function for pin 1 of PE port + 4 + 4 + read-write + + + AFR2 + selection of multiplexing function for pin 2 of PE port + 8 + 4 + read-write + + + AFR3 + selection of multiplexing function for pin 3 of PE port + 12 + 4 + read-write + + + AFR4 + selection of multiplexing function for pin 4 of PE port + 16 + 4 + read-write + + + AFR5 + selection of multiplexing function for pin 5 of PE port + 20 + 4 + read-write + + + AFR6 + selection of multiplexing function for pin 6 of PE port + 24 + 4 + read-write + + + AFR7 + selection of multiplexing function for pin 7 of PE port + 28 + 4 + read-write + + + + + + GPIOE_AFHR + GPIOE_AFHR + PA port multiplexing function register + 0x28 + 0x20 + 0x00000000 + + + AFR8 + selection of multiplexing function for pin 8 of PE port + 0 + 4 + read-write + + + AFR9 + selection of multiplexing function for pin 9 of PE port + 4 + 4 + read-write + + + AFR10 + selection of multiplexing function for pin 10 of PE port + 8 + 4 + read-write + + + AFR11 + selection of multiplexing function for pin 11 of PE port + 12 + 4 + read-write + + + AFR12 + selection of multiplexing function for pin 12 of PE port + 16 + 4 + read-write + + + AFR13 + selection of multiplexing function for pin 13 of PE port + 20 + 4 + read-write + + + AFR14 + selection of multiplexing function for pin 14 of PE port + 24 + 4 + read-write + + + AFR15 + selection of multiplexing function for pin 15 of PE port + 28 + 4 + read-write + + + + + + GPIOF_AFLR + GPIOF_AFLR + PF port multiplexing function register + 0x2C + 0x20 + 0x00000000 + + + AFR0 + selection of multiplexing function for pin 0 of PF port + 0 + 4 + read-write + + + AFR1 + selection of multiplexing function for pin 1 of PF port + 4 + 4 + read-write + + + AFR2 + selection of multiplexing function for pin 2 of PF port + 8 + 4 + read-write + + + AFR3 + selection of multiplexing function for pin 3 of PF port + 12 + 4 + read-write + + + AFR4 + selection of multiplexing function for pin 4 of PF port + 16 + 4 + read-write + + + AFR5 + selection of multiplexing function for pin 5 of PF port + 20 + 4 + read-write + + + AFR6 + selection of multiplexing function for pin 6 of PF port + 24 + 4 + read-write + + + AFR7 + selection of multiplexing function for pin 7 of PF port + 28 + 4 + read-write + + + + + + GPIOF_AFHR + GPIOF_AFHR + PF port multiplexing function register + 0x30 + 0x20 + 0x00000000 + + + AFR8 + selection of multiplexing function for pin 8 of PF port + 0 + 4 + read-write + + + AFR9 + selection of multiplexing function for pin 9 of PF port + 4 + 4 + read-write + + + AFR10 + selection of multiplexing function for pin 10 of PF port + 8 + 4 + read-write + + + AFR11 + selection of multiplexing function for pin 11 of PF port + 12 + 4 + read-write + + + AFR12 + selection of multiplexing function for pin 12 of PF port + 16 + 4 + read-write + + + AFR13 + selection of multiplexing function for pin 13 of PF port + 20 + 4 + read-write + + + AFR14 + selection of multiplexing function for pin 14 of PF port + 24 + 4 + read-write + + + AFR15 + selection of multiplexing function for pin 15 of PE port + 28 + 4 + read-write + + + + + + EXTICR1 + EXTICR1 + External interrupt configuration register 1 + 0x3C + 0x20 + 0x00000000 + + + EXTI0 + External interrupt 0 input pin configuration + 0 + 4 + read-write + + + EXTI1 + External interrupt 1 input pin configuration + 4 + 4 + read-write + + + EXTI2 + External interrupt 2 input pin configuration + 8 + 4 + read-write + + + EXTI3 + External interrupt 3 input pin configuration + 12 + 4 + read-write + + + EXTI4 + External interrupt 4 input pin configuration + 16 + 4 + read-write + + + EXTI5 + External interrupt 5 input pin configuration + 20 + 4 + read-write + + + EXTI6 + External interrupt 6 input pin configuration + 24 + 4 + read-write + + + EXTI7 + External interrupt 7 input pin configuration + 28 + 4 + read-write + + + + + + EXTICR2 + EXTICR2 + External interrupt configuration register 2 + 0x40 + 0x20 + 0x00000000 + + + EXTI8 + External interrupt 8 input pin configuration + 0 + 4 + read-write + + + EXTI9 + External interrupt 9 input pin configuration + 4 + 4 + read-write + + + EXTI10 + External interrupt 10 input pin configuration + 8 + 4 + read-write + + + EXTI11 + External interrupt 11 input pin configuration + 12 + 4 + read-write + + + EXTI12 + External interrupt 12 input pin configuration + 16 + 4 + read-write + + + EXTI13 + External interrupt 13 input pin configuration + 20 + 4 + read-write + + + EXTI14 + External interrupt 14 input pin configuration + 24 + 4 + read-write + + + EXTI15 + External interrupt 15 input pin configuration + 28 + 4 + read-write + + + + + + + + DMA1 + DMA1 controller + DMA1 + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CH1 + DMA1 Channel1 global interrupt + 57 + + + DMA1_CH2 + DMA1 Channel2 global interrupt + 38 + + + DMA1_CH3 + DMA1 Channel3 global interrupt + 39 + + + DMA1_CH4 + DMA1 Channel4 global interrupt + 40 + + + DMA1_CH5 + DMA1 Channel5 global interrupt + 41 + + + DMA1_CH6 + DMA1 Channel6 global interrupt + 42 + + + DMA1_CH7 + DMA1 Channel7 global interrupt + 43 + + + DMA1_CH8 + DMA1 Channel8 global interrupt + 44 + + + + INTFR + INTFR + DMA interrupt status register + (DMA_INTFR) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 12 + 1 + + + TCIF4 + Channel 4 Transfer Complete + flag + 13 + 1 + + + HTIF4 + Channel 4 Half Transfer Complete + flag + 14 + 1 + + + TEIF4 + Channel 4 Transfer Error + flag + 15 + 1 + + + GIF5 + Channel 5 Global interrupt + flag + 16 + 1 + + + TCIF5 + Channel 5 Transfer Complete + flag + 17 + 1 + + + HTIF5 + Channel 5 Half Transfer Complete + flag + 18 + 1 + + + TEIF5 + Channel 5 Transfer Error + flag + 19 + 1 + + + GIF6 + Channel 6 Global interrupt + flag + 20 + 1 + + + TCIF6 + Channel 6 Transfer Complete + flag + 21 + 1 + + + HTIF6 + Channel 6 Half Transfer Complete + flag + 22 + 1 + + + TEIF6 + Channel 6 Transfer Error + flag + 23 + 1 + + + GIF7 + Channel 7 Global interrupt + flag + 24 + 1 + + + TCIF7 + Channel 7 Transfer Complete + flag + 25 + 1 + + + HTIF7 + Channel 7 Half Transfer Complete + flag + 26 + 1 + + + TEIF7 + Channel 7 Transfer Error + flag + 27 + 1 + + + GIF8 + Channel 8 Global interrupt + flag + 28 + 1 + + + TCIF8 + Channel 8 Transfer Complete + flag + 29 + 1 + + + HTIF8 + Channel 8 Half Transfer Complete + flag + 30 + 1 + + + TEIF8 + Channel 8 Transfer Error + flag + 31 + 1 + + + + + INTFCR + INTFCR + DMA interrupt flag clear register + (DMA_INTFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CGIF4 + Channel 4 Global interrupt + clear + 12 + 1 + + + CGIF5 + Channel 5 Global interrupt + clear + 16 + 1 + + + CGIF6 + Channel 6 Global interrupt + clear + 20 + 1 + + + CGIF7 + Channel 7 Global interrupt + clear + 24 + 1 + + + CGIF8 + Channel 8 Global interrupt + clear + 28 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CTCIF4 + Channel 4 Transfer Complete + clear + 13 + 1 + + + CTCIF5 + Channel 5 Transfer Complete + clear + 17 + 1 + + + CTCIF6 + Channel 6 Transfer Complete + clear + 21 + 1 + + + CTCIF7 + Channel 7 Transfer Complete + clear + 25 + 1 + + + CTCIF8 + Channel 8 Transfer Complete + clear + 29 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CHTIF4 + Channel 4 Half Transfer + clear + 14 + 1 + + + CHTIF5 + Channel 5 Half Transfer + clear + 18 + 1 + + + CHTIF6 + Channel 6 Half Transfer + clear + 22 + 1 + + + CHTIF7 + Channel 7 Half Transfer + clear + 26 + 1 + + + CHTIF8 + Channel 8 Half Transfer + clear + 30 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CTEIF4 + Channel 4 Transfer Error + clear + 15 + 1 + + + CTEIF5 + Channel 5 Transfer Error + clear + 19 + 1 + + + CTEIF6 + Channel 6 Transfer Error + clear + 23 + 1 + + + CTEIF7 + Channel 7 Transfer Error + clear + 27 + 1 + + + CTEIF8 + Channel 8 Transfer Error + clear + 31 + 1 + + + + + + CFGR1 + CFGR + DMA channel configuration register + (DMA_CFGR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + DOUBLE_MODE + Double buffer mode enable bit + 15 + 1 + + + FLAG_CUR_MEM + Memory address selection setting + 16 + 1 + + + + + + CNTR1 + CNTR + DMA channel 1 number of data + register + 0xC + 0x20 + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + read-write + + + + + + PADDR1 + PADDR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + + MADDR1 + MADDR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + M1ADDR1 + M1ADDR1 + DMA channel 1 memory address1 + register + 0x18 + 0x20 + read-write + 0x00000000 + + + M1A + Memory address + 0 + 32 + + + + + + CFGR2 + CFGR2 + DMA channel configuration register + (DMA_CFGR) + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + + CNTR2 + CNTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + + PADDR2 + PADDR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + + MADDR2 + MADDR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + M1ADDR2 + M1ADDR2 + DMA channel 2 memory address 1 + register + 0x2C + 0x20 + read-write + 0x00000000 + + + M1A + Memory address + 0 + 32 + + + + + + CFGR3 + CFGR3 + DMA channel configuration register + (DMA_CFGR) + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + + CNTR3 + CNTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + + PADDR3 + PADDR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + + MADDR3 + MADDR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + M1ADDR3 + M1ADDR3 + DMA channel 3 memory address 1 + register + 0x40 + 0x20 + read-write + 0x00000000 + + + M1A + Memory address + 0 + 32 + + + + + + CFGR4 + CFGR4 + DMA channel configuration register + (DMA_CFGR) + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + + CNTR4 + CNTR4 + DMA channel 4 number of data + register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + + PADDR4 + PADDR4 + DMA channel 4 peripheral address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + + MADDR4 + MADDR4 + DMA channel 4 memory address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + M1ADDR4 + M1ADDR4 + DMA channel 4 memory address 2 + register + 0x54 + 0x20 + read-write + 0x00000000 + + + M1A + Memory address + 0 + 32 + + + + + + CFGR5 + CFGR5 + DMA channel configuration register + (DMA_CFGR) + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + + CNTR5 + CNTR5 + DMA channel 5 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + + PADDR5 + PADDR5 + DMA channel 5 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + + MADDR5 + MADDR5 + DMA channel 5 memory address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + M1ADDR5 + M1ADDR5 + DMA channel 5 memory address 2 + register + 0x68 + 0x20 + read-write + 0x00000000 + + + M1A + Memory address + 0 + 32 + + + + + + CFGR6 + CFGR6 + DMA channel configuration register + (DMA_CFGR) + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + + CNTR6 + CNTR6 + DMA channel 6 number of data + register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + + PADDR6 + PADDR6 + DMA channel 6 peripheral address + register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + + MADDR6 + MADDR6 + DMA channel 6 memory address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + M1ADDR6 + M1ADDR6 + DMA channel 6 memory address 2 + register + 0x7C + 0x20 + read-write + 0x00000000 + + + M1A + Memory address + 0 + 32 + + + + + + CFGR7 + CFGR7 + DMA channel configuration register + (DMA_CFGR) + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + + CNTR7 + CNTR7 + DMA channel 7 number of data + register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + + PADDR7 + PADDR7 + DMA channel 7 peripheral address + register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + + MADDR7 + MADDR7 + DMA channel 7 memory address + register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + M1ADDR7 + M1ADDR7 + DMA channel 7 memory address 2 + register + 0x90 + 0x20 + read-write + 0x00000000 + + + M1A + Memory address + 0 + 32 + + + + + + CFGR8 + CFGR8 + DMA channel configuration register + (DMA_CFGR) + 0x94 + 0x20 + read-write + 0x00000000 + + + EN + Channel enable + 0 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + CIRC + Circular mode + 5 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + MINC + Memory increment mode + 7 + 1 + + + PSIZE + Peripheral size + 8 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PL + Channel Priority level + 12 + 2 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + + + + CNTR8 + CNTR8 + DMA channel 8 number of data + register + 0x98 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + + PADDR8 + PADDR8 + DMA channel 8 peripheral address + register + 0x9C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + + MADDR8 + MADDR8 + DMA channel 8 memory address + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + M1ADDR8 + M1ADDR8 + DMA channel 8 memory address 2 + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + M1A + Memory address + 0 + 32 + + + + + + + + DMA2 + 0x40020400 + + DMA2_CH1 + DMA2 Channel1 global interrupt + 102 + + + DMA2_CH2 + DMA2 Channel2 global interrupt + 103 + + + DMA2_CH3 + DMA2 Channel3 global interrupt + 104 + + + DMA2_CH4 + DMA2 Channel4 global interrupt + 105 + + + DMA2_CH5 + DMA2 Channel5 global interrupt + 106 + + + DMA2_CH6 + DMA2 Channel6 global interrupt + 107 + + + DMA2_CH7 + DMA2 Channel7 global interrupt + 108 + + + DMA2_CH8 + DMA2 Channel8 global interrupt + 109 + + + + + DMAMUX + DMA request multiplexer + DMAMUX + 0x40020800 + + 0x0 + 0x400 + registers + + + + DMAMUX1_4_CFGR + DMAMUX1_4_CFGR + DMA request multiplexer channels 1 to 4 configuration registers + 0x0 + 0x20 + 0x0000 + + + + CHANNEL1_MUX + DMA request multiplexer channels 1 intput to the volunteer configuration + 0 + 7 + read-write + + + CHANNEL2_MUX + DMA request multiplexer channels 2 intput to the volunteer configuration + 8 + 7 + read-write + + + CHANNEL3_MUX + DMA request multiplexer channels 3 intput to the volunteer configuration + 16 + 7 + read-write + + + CHANNEL4_MUX + DMA request multiplexer channels 4 intput to the volunteer configuration + 24 + 7 + read-write + + + + + + DMAMUX5_8_CFGR + DMAMUX4_7_CFGR + DMA request multiplexer channels 5 to 8 configuration registers + 0x04 + 0x20 + 0x0000 + + + CHANNEL5_MUX + DMA request multiplexer channels 5 intput to the volunteer configuration + 0 + 7 + read-write + + + CHANNEL6_MUX + DMA request multiplexer channels 6 intput to the volunteer configuration + 8 + 7 + read-write + + + CHANNEL7_MUX + DMA request multiplexer channels 7 intput to the volunteer configuration + 16 + 7 + read-write + + + CHANNEL8_MUX + DMA request multiplexer channels 8 intput to the volunteer configuration + 24 + 7 + read-write + + + + + + DMAMUX9_12_CFGR + DMAMUX9_12_CFGR + DMA request multiplexer channels 9 to 12 configuration registers + 0x08 + 0x20 + 0x0000 + + + CHANNEL9_MUX + DMA request multiplexer channels 9 intput to the volunteer configuration + 0 + 7 + read-write + + + CHANNEL10_MUX + DMA request multiplexer channels 10 intput to the volunteer configuration + 8 + 7 + read-write + + + CHANNEL11_MUX + DMA request multiplexer channels 11 intput to the volunteer configuration + 16 + 7 + read-write + + + CHANNEL12_MUX + DMA request multiplexer channels 12 intput to the volunteer configuration + 24 + 7 + read-write + + + + + + DMAMUX13_16_CFGR + DMAMUX13_16_CFGR + DMA request multiplexer channels 13 to 16 configuration registers + 0x0C + 0x20 + 0x0000 + + + CHANNEL13_MUX + DMA request multiplexer channels 13 intput to the volunteer configuration + 0 + 7 + read-write + + + CHANNEL14_MUX + DMA request multiplexer channels 14 intput to the volunteer configuration + 8 + 7 + read-write + + + CHANNEL15_MUX + DMA request multiplexer channels 15 intput to the volunteer configuration + 16 + 7 + read-write + + + CHANNEL16_MUX + DMA request multiplexer channels 16 intput to the volunteer configuration + 24 + 7 + read-write + + + + + + + + ESIG + ESIG configuration + ESIG + 0x1FFFF7E0 + + 0x0 + 0x200 + registers + + + + FLACAP + FLACAP + Flash capecity register + 0x0 + 0x10 + 0x0000 + + + F_SIZE + F_SIZE/kByte + 0 + 16 + read-only + + + + + + UNIID1 + UNIID1 + UID register + 0x8 + 0x20 + 0x00000000 + + + U_ID + U_ID value + 0 + 32 + read-only + + + + + + UNIID2 + UNIID2 + UID register + 0xC + 0x20 + 0x00000000 + + + U_ID + U_ID value + 0 + 32 + read-only + + + + + + UNIID3 + UNIID3 + Div register + 0x10 + 0x20 + 0x00000000 + + + U_ID + U_ID value + 0 + 32 + read-only + + + + + + + + ADC1 + Analog to digital converter + ADC1 + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC + ADC global interrupt + 69 + + + + STATR + STATR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + ADCRSTF + ADC reset flag + 15 + 1 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CTLR1 + CTLR1 + control register 1/TKEY_V_CTLR + 0x4 + 0x20 + read-write + 0x00000000 + + + SW_PRE + Channel pre-handoff is closed + 31 + 1 + + + ANA_RST + simulation module reset enabled + 30 + 1 + + + PGA + ADC_PGA + 27 + 2 + + + BUFEN + TKEY_BUF_Enable + 26 + 1 + + + TKITUNE + TKEY_I enable + 25 + 1 + + + TKENABLE + TKEY enable, including TKEY_F and + TKEY_V + 24 + 1 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DUALMOD + Dual mode selection + 16 + 4 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode enable + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + + CTLR2 + CTLR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + + SWSTART + Start conversion of regular + channels + 22 + 1 + + + JSWSTART + Start conversion of injected + channels + 21 + 1 + + + EXTTRIG + External trigger conversion mode for + regular channels + 20 + 1 + + + EXTSEL + External event select for regular + group + 17 + 3 + + + JEXTTRIG + External trigger conversion mode for + injected channels + 15 + 1 + + + JEXTSEL + External event select for injected + group + 12 + 3 + + + ALIGN + Data alignment + 11 + 1 + + + DMA + Direct memory access mode + 8 + 1 + + + ADC_LP + ADC low power mode control + 7 + 1 + + + CAL_AUTO + the hardware automatic calibration + 6 + 1 + + + CAL_VOL + calibration voltage configuration + 4 + 2 + + + RSTCAL + Reset calibration + 3 + 1 + + + CAL + A/D calibration + 2 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D converter ON / OFF + 0 + 1 + + + + + + SAMPTR1_CHARGE1 + SAMPTR1_CHARGE1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMP10_TKCG10 + Channel 10 sample time + selection + 0 + 3 + + + SMP11_TKCG11 + Channel 11 sample time + selection + 3 + 3 + + + SMP12_TKCG12 + Channel 12 sample time + selection + 6 + 3 + + + SMP13_TKCG13 + Channel 13 sample time + selection + 9 + 3 + + + SMP14_TKCG14 + Channel 14 sample time + selection + 12 + 3 + + + SMP15_TKCG15 + Channel 15 sample time + selection + 15 + 3 + + + SMP16 + Channel 16 sample time + selection + 18 + 3 + + + SMP17 + Channel 17 sample time + selection + 21 + 3 + + + + + SAMPTR2_CHARGE2 + SAMPTR2_CHARGE2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMP0_TKCG0 + Channel 0 sample time + selection + 0 + 3 + + + SMP1_TKCG1 + Channel 1 sample time + selection + 3 + 3 + + + SMP2_TKCG2 + Channel 2 sample time + selection + 6 + 3 + + + SMP3_TKCG3 + Channel 3 sample time + selection + 9 + 3 + + + SMP4_TKCG4 + Channel 4 sample time + selection + 12 + 3 + + + SMP5_TKCG5 + Channel 5 sample time + selection + 15 + 3 + + + SMP6_TKCG6 + Channel 6 sample time + selection + 18 + 3 + + + SMP7_TKCG7 + Channel 7 sample time + selection + 21 + 3 + + + SMP8_TKCG8 + Channel 8 sample time + selection + 24 + 3 + + + SMP9_TKCG9 + Channel 9 sample time + selection + 27 + 3 + + + + + IOFR1 + IOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 12 + + + + + IOFR2 + IOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 12 + + + + + IOFR3 + IOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 12 + + + + + IOFR4 + IOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 12 + + + + + WDHTR + WDHTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + + + WDLTR + WDLTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + RSQR1 + RSQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + RSQR2 + RSQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + + + RSQR3 + RSQR3 + regular sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + SQ1 + 1st conversion in regular + sequence + 0 + 5 + + + + + ISQR + ISQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + + + IDATAR1_CHGOFFSET + IDATAR1_CHGOFFSET + injected data register x_Charge data offset for injected channel x + 0x3C + 0x20 + read-only + 0x00000000 + + + IDATA_TKCGOFFSET + Injected data_Touch key charge data offset for injected channel x + 0 + 16 + + + + + IDATAR2 + IDATAR2 + injected data register x + 0x40 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + IDATAR3 + IDATAR3 + injected data register x + 0x44 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + IDATAR4 + IDATAR4 + injected data register x + 0x48 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + RDATAR_DR + RDATAR_DR + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + DATA0_7 + Regular data + 0 + 8 + + + DATA8_15 + Regular data + 8 + 8 + + + ADC2DATA + converter data + 16 + 16 + + + + + ACT_DCG + ACT_DCG + start and discharge time register + RDATAR_DR + 0x4C + 0x20 + write-only + 0x00000000 + + + TKACT_DCG + Touch key start and discharge time register + 0 + 16 + + + + + AUX + ADCx_AUX + ADC time register + 0x54 + 0x20 + read-write + 0x00000000 + + + ADC_SMP_SEL0 + channel sampling time optional enable bit + 0 + 1 + + + ADC_SMP_SEL1 + channel sampling time optional enable bit + 1 + 1 + + + ADC_SMP_SEL2 + channel sampling time optional enable bit + 2 + 1 + + + ADC_SMP_SEL3 + channel sampling time optional enable bit + 3 + 1 + + + ADC_SMP_SEL4 + channel sampling time optional enable bit + 4 + 1 + + + ADC_SMP_SEL5 + channel sampling time optional enable bit + 5 + 1 + + + ADC_SMP_SEL6 + channel sampling time optional enable bit + 6 + 1 + + + ADC_SMP_SEL7 + channel sampling time optional enable bit + 7 + 1 + + + ADC_SMP_SEL8 + channel sampling time optional enable bit + 8 + 1 + + + ADC_SMP_SEL9 + channel sampling time optional enable bit + 9 + 1 + + + ADC_SMP_SEL10 + channel sampling time optional enable bit + 10 + 1 + + + ADC_SMP_SEL11 + channel sampling time optional enable bit + 11 + 1 + + + ADC_SMP_SEL12 + channel sampling time optional enable bit + 12 + 1 + + + ADC_SMP_SEL13 + channel sampling time optional enable bit + 13 + 1 + + + ADC_SMP_SEL14 + channel sampling time optional enable bit + 14 + 1 + + + ADC_SMP_SEL15 + channel sampling time optional enable bit + 15 + 1 + + + ADC_SMP_SEL16 + channel sampling time optional enable bit + 16 + 1 + + + ADC_SMP_SEL17 + channel sampling time optional enable bit + 17 + 1 + + + ADC_TO_DFSDM + ADC module samples data to DFSDM + 31 + 1 + + + + + + + + ADC2 + 0x40012800 + + 0x0 + 0x400 + registers + + + + ADC2_DRV + ADC2_DRV + ADC TOUCHKEY shielded register + 0x58 + 0x20 + read-write + 0x00000000 + + + TKEY_DRV_OUTEN + TOUCHKEY shielded each channel enable + 0 + 16 + + + TKEY_DRV_EN + TOUCHKEY shielded enable + 16 + 1 + + + + + + + + TIM1 + Advanced timer + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK + TIM1 Break + interrupt + 70 + + + TIM1_UP_ + TIM1 Update + interrupt + 71 + + + TIM1_TRG_COM + TIM1 Trigger and Commutation interrupts + 72 + + + TIM1_CC + TIM1 Capture Compare interrupt + 73 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CAPLVL + Timer capture level indication + enable + 15 + 1 + read-write + + + CAPOV + Timer capture value configuration + enable + 14 + 1 + read-write + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCFGR + SMCFGR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DMAINTENR + DMAINTENR + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + INTFR + INTFR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + SWEVGR + SWEVGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CHCTLR1_Output + CHCTLR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CHCTLR1_Input + CHCTLR1_Input + capture/compare mode register 1 (input + mode) + CHCTLR1_Output + 0x18 + 0x20 + read-write + 0x0000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CHCTLR2_Output + CHCTLR2_Output + capture/compare mode register (output + mode) + 0x1C + 0x20 + read-write + 0x0000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CHCTLR2_Input + CHCTLR2_Input + capture/compare mode register 2 (input + mode) + CHCTLR2_Output + 0x1C + 0x20 + read-write + 0x0000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ATRLR + ATRLR + auto-reload register + 0x2C + 0x20 + read-write + 0xFFFF + + + ATRLR + Auto-reload value + 0 + 16 + + + + + RPTCR + RPTCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + RPTCR + Repetition counter value + 0 + 8 + + + + + CH1CVR + CH1CVR + capture/compare register 1 + 0x34 + 0x20 + 0x0000 + + + CH1CVR + Capture/Compare 1 value + 0 + 16 + read-write + + + LEVEL1 + Level indicating bit + 16 + 1 + read-only + + + + + CH2CVR + CH2CVR + capture/compare register 2 + 0x38 + 0x20 + 0x0000 + + + CH2CVR + Capture/Compare 2 value + 0 + 16 + read-write + + + LEVEL2 + Level indicating bit + 16 + 1 + read-only + + + + + CH3CVR + CH3CVR + capture/compare register 3 + 0x3C + 0x20 + 0x0000 + + + CH3CVR + Capture/Compare value + 0 + 16 + read-write + + + LEVEL3 + Level indicating bit + 16 + 1 + read-only + + + + + CH4CVR + CH4CVR + capture/compare register 4 + 0x40 + 0x20 + 0x0000 + + + CH4CVR + Capture/Compare value + 0 + 16 + read-write + + + LEVEL4 + Level indicating bit + 16 + 1 + read-only + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DMACFGR + DMACFGR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAADR + DMAADR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + AUX + AUX + Double-side egde capture register + 0x50 + 0x10 + read-write + 0x0000 + + + CAP_ED_CH2 + Double-side egde capture is enable for channel2 + 0 + 1 + + + CAP_ED_CH3 + Double-side egde capture is enable for channel3 + 1 + 1 + + + CAP_ED_CH4 + Double-side egde capture is enable for channel4 + 2 + 1 + + + BK_SEL + Break source selection + 3 + 3 + + + DTP_MODE + The dead-time duration of the DT_VLU2 enabled setting occurs + on the rising edge of OCXREF + 6 + 1 + + + DTN_MODE + The dead-time duration of the DT_VLU2 enabled setting occurs + on the falling edge of OCXREF + 7 + 1 + + + DT_VLU2 + set the duration of the dead zone + 8 + 8 + + + + + + + + TIM8 + 0x40013400 + + TIM8_BRK + TIM8 Break + interrupt + 86 + + + TIM8_UP + TIM8 Update + interrupt + 87 + + + TIM8_TRG_COM + TIM8 Trigger and Commutation interrupts + 88 + + + TIM8_CC + TIM8 Capture Compare interrupt + 89 + + + + + TIM2 + General purpose timer + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 74 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CAPLVL + Timer capture level indication + enable + 15 + 1 + + + CAPOV + Timer capture value configuration + enable + 14 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCPC + Compare selection + 0 + 1 + + + + + SMCFGR + SMCFGR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + + DMAINTENR + DMAINTENR + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + INTFR + INTFR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + SWEVGR + SWEVGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CHCTLR1_Output + CHCTLR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x0000 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CHCTLR1_Input + CHCTLR1_Input + capture/compare mode register 1 (input + mode) + CHCTLR1_Output + 0x18 + 0x20 + read-write + 0x0000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CHCTLR2_Output + CHCTLR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x0000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CHCTLR2_Input + CHCTLR2_Input + capture/compare mode register 2 (input + mode) + CHCTLR2_Output + 0x1C + 0x20 + read-write + 0x0000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ATRLR + ATRLR + auto-reload register + 0x2C + 0x20 + read-write + 0xFFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + CH1CVR + CH1CVR + capture/compare register 1 + 0x34 + 0x20 + 0x0000 + + + CH1CVR + Capture/Compare 1 value + 0 + 16 + read-write + + + LEVEL1 + Level indicating bit + 16 + 1 + read-only + + + + + CH2CVR + CH2CVR + capture/compare register 2 + 0x38 + 0x20 + 0x0000 + + + CH2CVR + Capture/Compare 2 value + 0 + 16 + read-write + + + LEVEL2 + Level indicating bit + 16 + 1 + read-only + + + + + CH3CVR + CH3CVR + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x0000 + + + CH3CVR + Capture/Compare 3 value + 0 + 16 + read-write + + + LEVEL3 + Level indicating bit + 16 + 1 + read-only + + + + + CH4CVR + CH4CVR + capture/compare register 4 + 0x40 + 0x20 + 0x0000 + + + CH4CVR + Capture/Compare 4 value + 0 + 16 + read-write + + + LEVEL4 + Level indicating bit + 16 + 1 + read-only + + + + + DMACFGR + DMACFGR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAADR + DMAADR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAADR + DMA register for burst + accesses + 0 + 16 + + + + + AUX + AUX + Double-side egde capture register + 0x50 + 0x10 + read-write + 0x0000 + + + CAP_ED_CH2 + Double-side egde capture is enable for channel2 + 0 + 1 + + + CAP_ED_CH3 + Double-side egde capture is enable for channel3 + 1 + 1 + + + CAP_ED_CH4 + Double-side egde capture is enable for channel4 + 2 + 1 + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 global interrupt + 75 + + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 global interrupt + 76 + + + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 global interrupt + 77 + + + + + TIM9 + General purpose timer + TIM + 0x40014C00 + + 0x0 + 0x400 + registers + + + TIM9 + TIM9 global interrupt + 90 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CAPLVL + Timer capture level indication + enable + 15 + 1 + + + CAPOV + Timer capture value configuration + enable + 14 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCPC + Compare selection + 0 + 1 + + + + + SMCFGR + SMCFGR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + + DMAINTENR + DMAINTENR + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + INTFR + INTFR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + SWEVGR + SWEVGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CHCTLR1_Output + CHCTLR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x0000 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CHCTLR1_Input + CHCTLR1_Input + capture/compare mode register 1 (input + mode) + CHCTLR1_Output + 0x18 + 0x20 + read-write + 0x0000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CHCTLR2_Output + CHCTLR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x0000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CHCTLR2_Input + CHCTLR2_Input + capture/compare mode register 2 (input + mode) + CHCTLR2_Output + 0x1C + 0x20 + read-write + 0x0000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 32 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ATRLR + ATRLR + auto-reload register + 0x2C + 0x20 + read-write + 0xFFFF + + + ARR + Auto-reload value + 0 + 32 + + + + + CH1CVR + CH1CVR + capture/compare register 1 + 0x34 + 0x20 + 0x0000 + + + CH1CVR + Capture/Compare 1 value + 0 + 32 + read-write + + + + + CH2CVR + CH2CVR + capture/compare register 2 + 0x38 + 0x20 + 0x0000 + + + CH2CVR + Capture/Compare 2 value + 0 + 32 + read-write + + + + + CH3CVR + CH3CVR + capture/compare register 3 + 0x3C + 0x20 + 0x0000 + + + CH3CVR + Capture/Compare 3 value + 0 + 32 + read-write + + + + + CH4CVR + CH4CVR + capture/compare register 4 + 0x40 + 0x20 + 0x0000 + + + CH4CVR + Capture/Compare 4 value + 0 + 32 + read-write + + + + + DMACFGR + DMACFGR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAADR + DMAADR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAADR + DMA register for burst + accesses + 0 + 16 + + + + + + + + TIM10 + 0x40015000 + + TIM10 + TIM10 global interrupt + 91 + + + + + TIM11 + 0x40015400 + + TIM11 + TIM11 global interrupt + 92 + + + + + TIM12 + 0x40013C00 + + TIM12 + TIM12 global interrupt + 93 + + + + + TIM6 + Basic timer + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6 + TIM6 global interrupt + 100 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DMAINTENR + DMAINTENR + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + INTFR + INTFR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + SWEVGR + SWEVGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ATRLR + ATRLR + auto-reload register + 0x2C + 0x20 + read-write + 0xFFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 101 + + + + + LPTIM1 + Low-power timer 1 + LPTIM1 + 0x40002400 + + 0x00 + 0x400 + registers + + + LPTIM1WakeUP + LPTIM wake-up interrupt + 141 + + + LPTIM1 + LPTIM global interrupt + 96 + + + + ISR + ISR + interrupt status register + 0x00 + 0x20 + read-only + 0x00000000 + + + DIR_SYNC + direction of count + 7 + 1 + + + DOWN + count down + 6 + 1 + + + UP + count-up + 5 + 1 + + + ARROK + Aoto-reload register data update successfully + 4 + 1 + + + CMPOK + compare register data update successfully + 3 + 1 + + + EXTTRIG + Edge event are triggerd externally + 2 + 1 + + + ARRM + DATA of Aoto-reload register and LPTIM_CNT match + 1 + 1 + + + CMPM + DATA of compare register and LPTIM_CNT match + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x04 + 0x20 + write-only + 0x00000000 + + + DOWNCF + clear down flag + 6 + 1 + + + UPCF + clear up flag + 5 + 1 + + + ARROKCF + clear Aoto-reload register data update flag + 4 + 1 + + + CMPOKCF + clear compare register data update flag + 3 + 1 + + + EXTTRIGCF + clear Edge event are triggerd externally flag + 2 + 1 + + + ARRMCF + clear Aoto-reload register match flag + 1 + 1 + + + CMPMCF + clear compare register match flag + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x08 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Down interrupt enable + 6 + 1 + + + UPIE + UP interrupt enable + 5 + 1 + + + ARROKIE + Aoto-reload register data update successfully interrupts enable + 4 + 1 + + + CMPOKIE + compare register data update successfully interrupts enable + 3 + 1 + + + EXTTRIGIE + Edge event are triggerd externally successfully interrupts enable + 2 + 1 + + + ARRMIE + Aoto-reload register match successfully interrupts enable + 1 + 1 + + + CMPMIE + compare register match successfully interrupts enable + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0x0C + 0x20 + read-write + 0x00000000 + + + FORCE_PWM + Forcing pwm output + 27 + 1 + + + CLKMX_SEL + clock selection + 25 + 2 + + + ENC + coder mode + 24 + 1 + + + COUNTMODE + count clock selection + 23 + 1 + + + PRELOAD + update mode control + 22 + 1 + + + WAVPOL + PWM polarity + 21 + 1 + + + WAVE + PWM + 20 + 1 + + + TIMOUT + TIMEOUT control + 19 + 1 + + + TRIGEN + trigger configuration + 17 + 2 + + + TRIGSEL + trigger source selection + 13 + 1 + + + PRESC + prescaler configuration + 9 + 3 + + + TRGFLT + digital filter for flip-flops + 6 + 2 + + + CKFLT + digital filter for ex-clock + 3 + 2 + + + CKPOL + configure effective edges + 1 + 2 + + + CKSEL + effective edge configuration + 0 + 1 + + + + + CR + CR + control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DIR_EXTEN + externally trigger count direction enable + 4 + 1 + + + OUTEN + pwm output enable + 3 + 1 + + + CNTSTRT + start in continuous mode + 2 + 1 + + + SNGSTRT + start in one trigger mode + 1 + 1 + + + ENABLE + timer enable + 0 + 1 + + + + + CMP + CMP + compare register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + compare value + 0 + 16 + + + + + ARR + ARR + aoto-reload register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + aoto-reload count value + 0 + 16 + + + + + CNT + CNT + COUNT register + 0x1C + 0x20 + read-write + 0x00000000 + + + COUNT + Timer count value + 0 + 16 + + + + + + + + LPTIM2 + 0x40003400 + + LPTIM2WakeUP + LPTIM2 wake-up interrupt + 140 + + + LPTIM2 + LPTIM2 global interrupt + 97 + + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTLR + CTLR + Control register (DAC_CR) + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable + 0 + 1 + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + BOFF2 + DAC channel2 output buffer + disable + 17 + 1 + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + + + SWTR + SWTR + DAC software trigger register + (DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + + + R12BDHR1 + R12BDHR1 + DAC channel1 12-bit right-aligned data + holding register(DAC_DHR12R1) + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + L12BDHR1 + L12BDHR1 + DAC channel1 12-bit left aligned data + holding register (DAC_DHR12L1) + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + R8BDHR1 + R8BDHR1 + DAC channel1 8-bit right aligned data + holding register (DAC_DHR8R1) + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + R12BDHR2 + R12BDHR2 + DAC channel2 12-bit right aligned data + holding register (DAC_DHR12R2) + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + L12BDHR2 + L12BDHR2 + DAC channel2 12-bit left aligned data + holding register (DAC_DHR12L2) + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + R8BDHR2 + R8BDHR2 + DAC channel2 8-bit right-aligned data + holding register (DAC_DHR8R2) + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + RD12BDHR + RD12BDHR + Dual DAC 12-bit right-aligned data holding + register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 + Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + + + LD12BDHR + LD12BDHR + DUAL DAC 12-bit left aligned data holding + register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 + Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 20 + 12 + + + + + RD8BDHR + RD8BDHR + DUAL DAC 8-bit right aligned data holding + register (DAC_DHR8RD), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + + + DOR1 + DOR1 + DAC channel1 data output register + (DAC_DOR1) + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + DAC channel2 data output register + (DAC_DOR2) + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 48 + + + + STATR + STATR + Status register + 0x0 + 0x20 + 0x000000C0 + + + LPWKUP_ACT_FLAG + Low power wake-up indicator flag + 15 + 1 + read-write + + + MS_ERR + MARK or SPACE check error flag + 11 + 1 + read-only + + + RX_BUSY + receive status indication bit + 10 + 1 + read-only + + + CTS + CTS flag + 9 + 1 + read-write + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DATAR + DATAR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CTLR1 + CTLR1 + Control register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + M_EXT + data length extension bit + 14 + 2 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CTLR2 + CTLR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CTLR3 + CTLR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x00000000 + + + LPWKUP_DLY_CFG + Low power wake-up reception delay configuration + 13 + 3 + + + LPWKUP_CK_SRC + Low power wake-up clock source selection + 12 + 1 + + + LPWKUP_EN + Low power wake-up enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + GPR + GPR + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + CTLR4 + CTLR4 + Control register 4 + 0x1C + 0x20 + read-write + 0x00000000 + + + CHECK_SEL + check function selection bit + 2 + 2 + + + MS_ERRIE + SPACE or mark check error enable bit + 1 + 1 + + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 45 + + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 84 + + + + + USART4 + 0x40004C00 + + USART4 + USART4 global interrupt + 85 + + + + + USART5 + 0x40005000 + + USART5 + USART5 global interrupt + 98 + + + + + USART6 + 0x40001800 + + USART6 + USART6 global interrupt + 99 + + + + + USART7 + 0x40001C00 + + USART7 + UART7 global interrupt + 116 + + + + + USART8 + 0x40002000 + + USART8 + USART8 global interrupt + 117 + + + + + I2C1 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1 event interrupt + 46 + + + I2C1_ER + I2C1 error interrupt + 47 + + + + CTLR1 + CTLR1 + Control register 1 + 0x0 + 0x10 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + ALERT + SMBus alert + 13 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + ENARP + ARP enable + 4 + 1 + + + SMBTYPE + SMBus type + 3 + 1 + + + SMBUS + SMBus mode + 1 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CTLR2 + CTLR2 + Control register 2 + 0x4 + 0x10 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x10 + read-write + 0x0000 + + + ADDMODE + Addressing mode (slave + mode) + 15 + 1 + + + ADD9_8 + Interface address + 8 + 2 + + + ADD7_1 + Interface address + 1 + 7 + + + ADD0 + Interface address + 0 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x10 + read-write + 0x0000 + + + ADD2 + Interface address + 1 + 7 + + + ENDUAL + Dual addressing mode + enable + 0 + 1 + + + + + DATAR + DATAR + Data register + 0x10 + 0x10 + read-write + 0x0000 + + + DATAR + 8-bit data register + 0 + 8 + + + + + STAR1 + STAR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + SMBALERT + SMBus alert + 15 + 1 + read-write + + + TIMEOUT + Timeout or Tlow error + 14 + 1 + read-write + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADD10 + 10-bit header sent (Master + mode) + 3 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + STAR2 + STAR2 + Status register 2 + 0x18 + 0x10 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + SMBHOST + SMBus host header (Slave + mode) + 6 + 1 + + + SMBDEFAULT + SMBus device default address (Slave + mode) + 5 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CKCFGR + CKCFGR + Clock control register + 0x1C + 0x10 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + RTR + RTR + Raise time register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 52 + + + I2C2_ER + I2C2 error interrupt + 53 + + + + + I2C3 + 0x40005C00 + + I2C3_EV + I2C3 event interrupt + 78 + + + I2C3_ER + I2C3 error interrupt + 79 + + + + + I2C4 + 0x40014000 + + I2C4_EV + I2C4 event interrupt + 80 + + + I2C4_ER + I2C4 error interrupt + 81 + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 37 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x10 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x10 + read-write + 0x0000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + STATR + STATR + status register + 0x8 + 0x10 + 0x0002 + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + UDR + Underrun flag + 3 + 1 + read-only + + + CHSID + Channel side + 2 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DATAR + DATAR + data register + 0xC + 0x10 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCR + CRCR + CRCR polynomial register + 0x10 + 0x10 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RCRCR + RCRCR + RX CRC register + 0x14 + 0x10 + read-only + 0x0000 + + + RXCRC + Rx CRC register + 0 + 16 + + + + + TCRCR + TCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TXCRC + Tx CRC register + 0 + 16 + + + + + HSCR + HSCR + high speed control register + 0x24 + 0x20 + read-write + 0x0000 + + + HSRXEN + High speed mode read enable + 0 + 1 + + + HSRXEN2 + High speed mode 2 read enable + 2 + 1 + + + + + + + + SPI4 + 0x40004000 + + SPI4 + SPI4 global interrupt + 51 + + + + + SPI3 + Serial peripheral interface + SPI + 0x40003C00 + + 0x0 + 0x400 + registers + + + SPI3 + SPI3 global interrupt + 50 + + + + CTLR1 + CTLR1 + control register 1 + 0x0 + 0x10 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CTLR2 + CTLR2 + control register 2 + 0x4 + 0x10 + read-write + 0x0000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + STATR + STATR + status register + 0x8 + 0x10 + 0x0002 + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + UDR + Underrun flag + 3 + 1 + read-only + + + CHSID + Channel side + 2 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DATAR + DATAR + data register + 0xC + 0x10 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCR + CRCR + CRCR polynomial register + 0x10 + 0x10 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RCRCR + RCRCR + RX CRC register + 0x14 + 0x10 + read-only + 0x0000 + + + RXCRC + Rx CRC register + 0 + 16 + + + + + TCRCR + TCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TXCRC + Tx CRC register + 0 + 16 + + + + + SPI_I2S_CFGR + SPI_I2S_CFGR + SPI_I2S configure register + 0x1C + 0x10 + read-write + 0x0000 + + + CHLEN + Channel length (number of bits per audio channel) + 0 + 1 + + + DATLEN + DATLEN[1:0] bits (Data length to be transferred) + 1 + 2 + + + CKPOL + steady state clock polarity + 3 + 1 + + + I2SSTD + I2SSTD[1:0] bits (I2S standard selection) + 4 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SCFG + I2SCFG[1:0] bits (I2S configuration mode) + 8 + 2 + + + I2SE + I2S Enable + 10 + 1 + + + I2SMOD + I2S mode selection + 11 + 1 + + + + + SPI_I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x10 + read-write + 00000000 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + HSCR + HSCR + high speed control register + 0x24 + 0x20 + read-write + 0x0000 + + + HSRXEN + High speed mode read enable + 0 + 1 + + + HSRXEN2 + High speed mode 2 read enable + 2 + 1 + + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 49 + + + + + USBPD + USBPD configuration + USBPD + 0x40024400 + + 0x0 + 0x400 + registers + + + USBPDWakeUP + USBPD_WKUP global interrupt + 55 + + + USBPD + USBPD global interrupt + 54 + + + + CONFIG + CONFIG + PD interrupt enable register + 0x00 + 0x10 + 0x0002 + + + PD_FILT_EN + control PD pin input filter enable + 0 + 1 + read-write + + + PD_ALL_CLR + PD ITClear + 1 + 1 + read-write + + + CC_SEL + PD Commutation port + 2 + 1 + read-write + + + PD_DMA_EN + PD DMA Enable + 3 + 1 + read-write + + + PD_RST_EN + PD RST Enable + 4 + 1 + read-write + + + WAKE_POLAR + wakeup polarity + 5 + 1 + read-write + + + CC_TR + TR conditioning of the CC LV waveform + 6 + 1 + read-write + + + CC_INC + CC bias current adjustment bit + 7 + 1 + read-write + + + RX_MULTI_0 + Continuously receive several bits of 0 indicator flag + 8 + 1 + read-only + + + IE_PD_IO + IO Enable + 10 + 1 + read-write + + + IE_RX_BIT + bit interrupt Enable + 11 + 1 + read-write + + + IE_RX_BYTE + Receive byte register + 12 + 1 + read-write + + + IE_RX_ACT + Receive complete register + 13 + 1 + read-write + + + IE_RX_RESET + Receive complete rst register + 14 + 1 + read-write + + + IE_TX_END + transfer complete register + 15 + 1 + read-write + + + + + BMC_CLK_CNT + BMC_CLK_CNT + BMC sampling clock counter + 0x02 + 0x10 + 0x0000 + + + BMC_CLK_CNT + R/T counter + 0 + 9 + read-write + + + + + CONTROL + CONTROL + PD Send and receive enable register + 0x4 + 0x08 + 0x00 + + + PD_TX_EN + PD_TX_EN value + 0 + 1 + read-write + + + BMC_START + BMC_START value + 1 + 1 + read-write + + + RX_STATE + PD receive status identification + 2 + 3 + read-write + + + DATA_FLAG + DATA_FLAG value + 5 + 1 + read-only + + + TX_BIT_BACK + TX_BIT_BACK value + 6 + 1 + read-only + + + BMC_BYTE_HI + BMC_BYTE_HI value + 7 + 1 + read-only + + + + + TX_SEL + TX_SEL + SOP port selection register + 0x5 + 0x08 + 0x00 + + + TX_SEL1 + TX_SEL1 value + 0 + 1 + read-write + + + TX_SEL2 + TX_SEL2 value + 2 + 2 + read-write + + + TX_SEL3 + TX_SEL3 value + 4 + 2 + read-write + + + TX_SEL4 + TX_SEL4 value + 6 + 2 + read-write + + + + + BMC_TX_SZ + BMC_TX_SZ + PD send length register + 0x6 + 0x10 + 0x0000 + + + BMC_TX_SZ + BMC_TX_SZ value + 0 + 9 + read-write + + + + + DATA_BUF + DATA_BUF + DMA cache data register + 0x8 + 0x08 + 0x00 + + + DATA_BUF + DATA_BUF value + 0 + 8 + read-only + + + + + STATUS + STATUS + PD interrupt flag register + 0x9 + 0x08 + 0x00 + + + BMC_AUX + BMC_AUX value + 0 + 2 + read-only + + + BUF_ERR + BUF_ERR value + 2 + 1 + read-write + + + IF_RX_BIT + IF_RX_BIT value + 3 + 1 + read-write + + + IF_RX_BYTE + IF_RX_BYTE value + 4 + 1 + read-write + + + IF_RX_ACT + IF_RX_ACT value + 5 + 1 + read-write + + + IF_RX_RESET + IF_RX_RESET value + 6 + 1 + read-write + + + IF_TX_END + IF_TX_END value + 7 + 1 + read-write + + + + + BMC_BYTE_CNT + BMC_BYTE_CNT + Byte counter + 0xA + 0x10 + 0x0000 + + + BMC_BYTE_CNT + BMC_BYTE_CNT value + 0 + 9 + read-only + + + + + PORT_CC1 + PORT_CC1 + CC1 port control register + 0xC + 0x10 + 0x0003 + + + PA_CC1_AI + PA_CC1_AI value + 0 + 1 + read-only + + + CC1_PD + port pull-down resistor enable + 1 + 1 + read-write + + + CC1_PU + CC1_PU value + 2 + 2 + read-write + + + CC1_LVE + CC1_LVE value + 4 + 1 + read-write + + + CC1_CE + CC1_CE value + 5 + 3 + read-write + + + + + PORT_CC2 + PORT_CC2 + CC2 port control register + 0xE + 0x10 + 0x0000 + + + PA_CC2_AI + PA_CC2_AI value + 0 + 1 + read-write + + + CC2_PD + port pull-down resistor enable + 1 + 1 + read-write + + + CC2_PU + CC2_PU value + 2 + 2 + read-write + + + CC2_LVE + CC2_LVE value + 4 + 1 + read-write + + + CC2_CE + CC2_CE value + 5 + 3 + read-write + + + + + DMA + DMA + PD buffer start address register + 0x10 + 0x20 + 0x0000 + + + USBPD_DMA_ADDR + USBPD_DMA_ADDR value + 0 + 21 + read-write + + + + + + + + USB_OTG_FS + USB FS OTG register + USB_OTG_FS + 0x50000000 + + 0x00 + 0x40000 + registers + + + USBFSWakeup + USBFSWakeUP + 68 + + + USBFS + USBFS global interrupt + 67 + + + + R8_USB_CTRL + USB base control + 0x00 + 8 + read-write + + + RB_UC_DMA_EN + DMA enable and DMA interrupt enable for USB + [0:0] + + + RB_UC_CLR_ALL + force clear FIFO and count of USB + [1:1] + + + RB_UC_RST_SIE + force reset USB SIE, need software clear + [2:2] + + + RB_UC_INT_BUSY + enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid + [3:3] + + + MASK_UC_SYS_CTRL_RB_UC_DEV_PU_EN + USB device enable and internal pullup resistance enable + [5:4] + + + RB_UC_LOW_SPEED + enable USB low speed: 0=12Mbps, 1=1.5Mbps + [6:6] + + + RB_UC_HOST_MODE + enable USB host mode: 0=device mode, 1=host mode + [7:7] + + + + + UDEV_CTRL__UHOST_CTRL + USB device/host physical prot control + 0x01 + 8 + read-write + 0x00 + + + RB_UH_PORT_EN__UD_PORT_EN + enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + [0:0] + + + RB_UH_BUS_RESET__UD_GP_BIT + force clear FIFO and count of USB + [1:1] + + + RB_UH_LOW_SPEED__UD_LOW_SPEED + enable USB port low speed: 0=full speed, 1=low speed + [2:2] + + + RB_UH_DM_PIN__UD_DM_PIN + ReadOnly: indicate current UDM pin level + [4:4] + read-only + + + RB_UH_DP_PIN__UD_DP_PIN + USB device enable and internal pullup resistance enable + [5:5] + read-only + + + RB_UH_PD_DIS__UD_PD_DIS + disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable + [7:7] + + + + + R8_USB_INT_EN + USB interrupt enable + 0x02 + 8 + read-write + + + RB_UIE_BUS_RST__UIE_DETECT + enable interrupt for USB bus reset event for USB device mode + [0:0] + + + + RB_UIE_TRANSFER + enable interrupt for USB transfer completion + [1:1] + + + + RB_UIE_SUSPEND + enable interrupt for USB suspend or resume event + [2:2] + + + + RB_UIE_HST_SOF + enable interrupt for host SOF timer action for USB host mode + [3:3] + + + RB_UIE_FIFO_OV + enable interrupt for FIFO overflow + [4:4] + + + RB_UIE_DEV_NAK + enable interrupt for NAK responded for USB device mode + [6:6] + + + RB_UIE_DEV_SOF + enable interrupt for SOF received for USB device mode + [7:7] + + + + + R8_USB_DEV_AD + USB device address + 0x03 + 8 + read-write + + + MASK_USB_ADDR + bit mask for USB device address + [6:0] + read-write + + + RB_UDA_GP_BIT + general purpose bit + [7:7] + + + + + R8_USB_MIS_ST + USB miscellaneous status + 0x05 + 8 + read-only + + + RB_UMS_DEV_ATTACH + RO, indicate device attached status on USB host + [0:0] + + + RB_UMS_DM_LEVEL + RO, indicate UDM level saved at device attached to USB host + [1:1] + + + RB_UMS_SUSPEND + RO, indicate USB suspend status + [2:2] + + + RB_UMS_BUS_RESET + RO, indicate USB bus reset status + [3:3] + + + RB_UMS_R_FIFO_RDY + RO, indicate USB receiving FIFO ready status (not empty) + [4:4] + + + RB_UMS_SIE_FREE + RO, indicate USB SIE free status + [5:5] + + + RB_UMS_SOF_ACT + RO, indicate host SOF timer action status for USB host + [6:6] + + + RB_UMS_SOF_PRES + RO, indicate host SOF timer presage status + [7:7] + + + + + R8_USB_INT_FG + USB interrupt flag + 0x06 + 8 + read-write + + + RB_UIF_BUS_RST__UIF_DETECT + bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear + [0:0] + + + RB_UIF_TRANSFER + USB transfer completion interrupt flag, direct bit address clear or write 1 to clear + [1:1] + + + RB_UIF_SUSPEND + USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear + [2:2] + + + RB_UIF_HST_SOF + host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear + [3:3] + + + RB_UIF_FIFO_OV + FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear + [4:4] + + + RB_U_SIE_FREE + RO, indicate USB SIE free status + [5:5] + read-only + + + RB_U_TOG_OK + RO, indicate current USB transfer toggle is OK + [6:6] + read-only + + + RB_U_IS_NAK + RO, indicate current USB transfer is NAK received + [7:7] + read-only + + + + + R8_USB_INT_ST + USB interrupt status + 0x07 + 8 + read-only + + + MASK_UIS_H_RES__MASK_UIS_ENDP + RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode + [3:0] + + + MASK_UIS_TOKEN + RO, bit mask of current token PID code received for USB device mode + [5:4] + + + RB_UIS_TOG_OK + RO, indicate current USB transfer toggle is OK + [6:6] + + + RB_UIS_IS_NAK + RO, indicate current USB transfer is NAK received for USB device mode + [7:7] + + + + + R16_USB_RX_LEN + USB receiving length + 0x08 + 16 + read-only + + + R8_UEP4_1_MOD + endpoint 4/1 mode + 0x0C + 8 + read-write + + + RB_UEP4_TX_EN + enable USB endpoint 4 transmittal (IN) + [2:2] + + + RB_UEP4_RX_EN + enable USB endpoint 4 receiving (OUT) + [3:3] + + + RB_UEP1_BUF_MOD + buffer mode of USB endpoint 1 + [4:4] + + + RB_UEP1_TX_EN + enable USB endpoint 1 transmittal (IN) + [6:6] + + + RB_UEP1_RX_EN + enable USB endpoint 1 receiving (OUT) + [7:7] + + + + + R8_UEP2_3_MOD__UH_EP_MOD + endpoint 2/3 mode;host endpoint mode + 0x0D + 8 + read-write + + + RB_UEP2_BUF_MOD__UH_EP_RBUF_MOD + buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint + [0:0] + + + RB_UEP2_TX_EN + enable USB endpoint 2 transmittal (IN) + [2:2] + + + RB_UEP2_RX_EN__UH_EP_RX_EN + enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving + [3:3] + + + RB_UEP3_BUF_MOD__UH_EP_TBUF_MOD + buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint + [4:4] + + + RB_UEP3_TX_EN__UH_EP_TX_EN + enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal + [6:6] + + + RB_UEP3_RX_EN + enable USB endpoint 3 receiving (OUT) + [7:7] + + + + + R8_UEP5_6_MOD + endpoint 5/6 mode + 0x0e + 8 + read-write + 0x00 + + + RB_UEP5_BUF_MOD + buffer mode of USB endpoint 5 + [0:0] + + + RB_UEP5_TX_EN + enable USB endpoint 5 transmittal (IN) + [2:2] + + + RB_UEP5_RX_EN + enable USB endpoint 5 receiving (OUT) + [3:3] + + + RB_UEP6_BUF_MOD + buffer mode of USB endpoint 6 + [4:4] + + + RB_UEP6_TX_EN + enable USB endpoint 6 transmittal (IN) + [6:6] + + + RB_UEP3_RX_EN + enable USB endpoint 6 receiving (OUT) + [7:7] + + + + + R8_UEP7_MOD + endpoint 7 mode + 0x0f + 8 + read-write + 0x00 + + + RB_UEP7_BUF_MOD + buffer mode of USB endpoint 7 + [0:0] + + + RB_UEP7_TX_EN + enable USB endpoint 7 transmittal (IN) + [2:2] + + + RB_UEP7_RX_EN + enable USB endpoint 7 receiving (OUT) + [3:3] + + + + + R32_UEP0_DMA + endpoint 0 DMA buffer address + 0x10 + 0x20 + read-write + + + R32_UEP1_DMA + endpoint 1 DMA buffer address + 0x14 + 0x20 + read-write + + + R32_UEP2_DMA__UH_RX_DMA + endpoint 2 DMA buffer address;host rx endpoint buffer high address + 0x18 + 0x20 + read-write + + + R32_UEP3_DMA__UH_TX_DMA + endpoint 3 DMA buffer address;host tx endpoint buffer high address + 0x1C + 0x20 + read-write + + + R32_UEP4_DMA + endpoint 4 DMA buffer address + 0x20 + 0x20 + read-write + + + R32_UEP5_DMA + endpoint 5 DMA buffer address + 0x24 + 0x20 + read-write + + + R32_UEP6_DMA + endpoint 6 DMA buffer address + 0x28 + 0x20 + read-write + + + R32_UEP7_DMA + endpoint 7 DMA buffer address + 0x2c + 0x20 + read-write + + + R8_UEP0_T_LEN + endpoint 0 transmittal length + 0x30 + 8 + read-write + + + R8_UEP0_T_CTRL + endpoint 0 control + 0x32 + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + RB_UEP_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP0_R_CTRL + endpoint 0 control + 0x33 + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + RB_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP1_T_LEN + endpoint 1 transmittal length + 0x34 + 8 + read-write + + + R8_UEP1_T_CTRL___USBHD_UH_SETUP + endpoint 1 control + 0x36 + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + RB_UEP_T_TOG_ + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + RB_UH_SOF_EN + USB host automatic SOF enable + [6:6] + + + RB_UH_PRE_PID_EN + USB host PRE PID enable for low speed device via hub + [7:7] + + + + + R8_UEP1_R_CTRL + endpoint 1 control + 0x37 + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + RB_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP2_T_LEN__USBHD_UH_EP_PID + endpoint 2 transmittal length + 0x38 + 8 + read-write + + + RB_UH_ENDP_MASK + bit mask of endpoint number for USB host transfer + [3:0] + + + RB_UH_TOKEN_MASK + bit mask of token PID for USB host transfer + [7:4] + + + + + R8_UEP2_T_CTRL + endpoint 2 control + 0x3a + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + RB_UEP_T_TOG_ + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP2_R_CTRL__USBHD_UH_RX_CTRL + endpoint 2 control + 0x3b + 8 + read-write + 0x00 + + + MASK_UEP_R_RES___UH_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + RB_UEP_R_TOG___UH_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG___UH_R_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP3_T_LEN__USBHD_UH_TX_LEN + endpoint 3 transmittal length + 0x3c + 8 + read-write + + + R8_UEP3_T_CTRL__USBHD_UH_TX_CTRL + endpoint 3 control + 0x3e + 8 + read-write + 0x00 + + + MASK_UEP_T_RES___UH_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + RB_UEP_T_TOG___UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG__UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP3_R_CTRL_ + endpoint 3 control + 0x3f + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + RB_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + + R8_UEP4_T_LEN + endpoint 4 transmittal length + 0x40 + 8 + read-write + + + R8_UEP4_T_CTRL + endpoint 4 control + 0x42 + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + RB_UEP_T_TOG___UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG__UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP4_R_CTRL_ + endpoint 4 control + 0x43 + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + RB_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + + R8_UEP5_T_LEN + endpoint 5 transmittal length + 0x44 + 8 + read-write + + + R8_UEP5_T_CTRL + endpoint 5 control + 0x46 + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + RB_UEP_T_TOG___UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG__UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP5_R_CTRL_ + endpoint 5 control + 0x47 + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + RB_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + + R8_UEP6_T_LEN + endpoint 6 transmittal length + 0x48 + 8 + read-write + + + R8_UEP6_T_CTRL + endpoint 6 control + 0x4a + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + RB_UEP_T_TOG___UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG__UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP6_R_CTRL_ + endpoint 6 control + 0x4b + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + RB_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP7_T_LEN + endpoint 7 transmittal length + 0x4c + 8 + read-write + + + R8_UEP7_T_CTRL + endpoint 7 control + 0x4e + 8 + read-write + 0x00 + + + MASK_UEP_T_RES + bit mask of handshake response type for USB endpoint X transmittal (IN) + [1:0] + + + RB_UEP_T_TOG___UH_T_TOG + prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG__UH_T_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + R8_UEP7_R_CTRL_ + endpoint 7 control + 0x4f + 8 + read-write + 0x00 + + + MASK_UEP_R_RES + bit mask of handshake response type for USB endpoint X receiving (OUT) + [1:0] + + + RB_UEP_R_TOG + expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 + [2:2] + + + RB_UEP_AUTO_TOG + enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle + [3:3] + + + + + USB_OTG_CR + usb otg control + 0x54 + 0x20 + read-write + 0x00 + + + USB_OTG_CR_DISCHARGEVBUS + usb otg control + [0:0] + + + USB_OTG_CR_CHARGEVBUS + usb otg control + [1:1] + + + USB_OTG_CR_IDPU + usb otg control + [2:2] + + + USB_OTG_CR_OTG_EN + usb otg control + [3:3] + + + USB_OTG_CR_VBUS + usb otg control + [4:4] + + + USB_OTG_CR_SESS + usb otg control + [5:5] + + + + + USB_OTG_SR + usb otg status + 0x58 + 0x20 + read-write + 0x00 + + + USB_OTG_SR_VBUS_VLD + usb otg status + [0:0] + + + USB_OTG_SR_SESS_VLD + usb otg status + [1:1] + + + USB_OTG_SR_SESS_END + usb otg status + [2:2] + + + USB_OTG_SR_ID_DIG + usb otg status + [3:3] + + + + + + + + USBHS + USB register + USBHS + 0x40030000 + + 0x00 + 0x400 + registers + + + USBHS + USBHS global interrupt + 56 + + + USBHSWakeUP + USBHS Wakeup interrupt + 64 + + + + R8_USB_CTRL + USB base control register + 0x00 + 0x08 + read-write + 0x07 + + + RB_UD_RST_LINK + LINK layer reset,highly effective + [0:0] + + + RB_UD_RST_SIE + USB protocol processor reset + [1:1] + + + RB_UD_CLR_ALL + clear all interrupt flags + [2:2] + + + RB_UD_PHY_SUSPENDM + USB PHY suspend + [3:3] + + + RB_UD_DMA_EN + DMA transfer enabled + [4:4] + + + RB_UD_DEV_EN + USB device enabled + [5:5] + + + RB_UD_LPM_EN + LPM enable + [7:7] + + + + + R8_USB_BASE_MODE + USB mode control register + 0x01 + 0x08 + 0x00 + + + RB_UD_SPEED_TYPE + The desired speed mode of the device + [1:0] + read-write + + + + + R8_USB_INT_EN + USB interrupt enable register + 0x02 + 0x08 + read-write + 0x00 + + + RB_UDIE_BUS_RST + USB bus reset interrupt enabled + [0:0] + + + RB_UDIE_SUSPEND + USB bus pause interrupt enabled + [1:1] + + + RB_UDIE_BUS_SLEEP + USB bus sleep interrupt enabled + [2:2] + + + RB_UDIE_LPM_ACT + LMP transfer end interrupt enabled + [3:3] + + + RB_UDIE_TRANSFER + USB transfer end interrupt enabled + [4:4] + + + RB_UDIE_SOF_ACT + Receive SOF packet interrupt enable + [5:5] + + + RB_UDIE_LINK_RDY + USB connection interrupt enable + [6:6] + + + RB_UDIE_FIFO_OVER + USB Overflow interrupt enable + [7:7] + + + + + R8_USB_DEV_AD + USB device address + 0x03 + 0x08 + read-write + 0x00 + + + RB_MASK_USB_ADDR + bit mask for USB device address + [6:0] + + + + + R8_USB_WAKE_CTRL + USB remote wake up register + 0x04 + 0x10 + read-write + 0x0000 + + + RB_UD_REMOTE_WKUP + remote wake up + [0:0] + + + + + R8_USB_TEST_MODE + USB test mode register + 0x05 + 0x08 + read-write + 0x00 + + + RB_UD_TEST_J + test mode,output J + [0:0] + + + RB_UD_TEST_K + test mode,output K + [1:1] + + + RB_UD_TEST_PKT + test mode,output a packet + [2:2] + + + RB_UD_TEST_SE0NAK + test mode,output SEO + [3:3] + + + RB_UD_TEST_EN + test mode enable + [7:7] + + + + + R16_USB_LPM_DATA + USB power management register + 0x06 + 0x10 + 0x8000 + + + RB_UD_LPM_DATA + power management data + [10:0] + read-only + + + RB_UD_LPM_BUSY + power management busy + [15:15] + read-write + + + + + R8_USB_INT_FG + USB interrupt flag register + 0x08 + 0x08 + 0x00 + + + RB_UDIF_BUS_RST + USB bus reset interrupt flag + [0:0] + read-write + + + RB_UDIF_SUSPEND + USB bus suspend interrupt flag + [1:1] + read-write + + + RB_UDIF_BUS_SLEEP + USB bus sleep interrupt flag + [2:2] + read-write + + + RB_UDIF_LPM_ACT + LPM transmission end interrupt flag + [3:3] + read-write + + + RB_UDIF_RTX_ACT + USB transmission end interrupt flag + [4:4] + read-only + + + RB_UDIF_RX_SOF + Receive SOF packet interrupt flag + [5:5] + read-write + + + RB_UDIF_LINK_RDY + USB connection interrupt flag + [6:6] + read-write + + + RB_UDIF_FIFO_OV + USB Overflow interrupt flag + [7:7] + read-write + + + + + R8_USB_INT_ST + USB interrupt status + 0x09 + 0x08 + read-only + 0x00 + + + RB_UDIS_EP_ID_MASK + The endpoint number at which the data transfer occurs + [2:0] + + + RB_UDIS_EP_DIR + Endpoint data transmission direction + [4:4] + + + + + R8_USB_MIS_ST + USB miscellaneous status + 0x0A + 0x08 + read-only + 0x00 + + + RB_UDMS_READY + USB connection status + [0:0] + + + RB_UDMS_SUSPEND + USB suspend status + [1:1] + + + RB_UDMS_SLEEP + USB sleep status + [2:2] + + + RB_UDMS_SIE_FREE + USB free status + [3:3] + + + RB_UDMS_SUSP_REQ + USB suspends the request + [4:4] + + + RB_UDMS_HS_MOD + whether the host is high-speed + [7:7] + + + + + R16_USB_FRAM_NO + USB frame number + 0x0C + 0x10 + read-only + 0x0000 + + + RB_UD_MFRAME_NO + Received micro frame number + [15:13] + + + RB_UD_FRAME_NO + Received frame number + [10:0] + + + + + R16_USB_BUS + USB bus + 0x0E + 0X10 + 0x0000 + + + RB_USB_DM_ST + UDM status + [3:3] + read-only + + + RB_USB_DP_ST + UDP status + [2:2] + read-only + + + RB_USB_WAKEUP + USB wakeup + [0:0] + read-only + + + + + UEP_TX_EN + USB endpoint sends the enable register + 0x10 + 0x10 + 0x0000 + + + RB_UEP_TX_EN + Endpoint 0 to 15 sends enable + [15:0] + read-write + + + + + UEP_RX_EN + USB endpoint receive the enable registers + 0x12 + 0x10 + 0x0000 + + + RB_UEP_RX_EN + Endpoint 0 to 15 receive enable + [15:0] + read-write + + + + + R16_UEP_T_TOG_AUTO + USB endpoint sends the auto-filp enable register + 0x14 + 0X10 + 0x0000 + + + RB_UEP_T_TOG_AUTO + 0 to 7 endpoint synchronization triggers bit auto-filp + enable + [7:0] + read-write + + + + + R16_UEP_R_TOG_AUTO + USB endpoint receive the auto-filp enable register + 0x16 + 0X10 + 0x0000 + + + RB_UEP_R_TOG_AUTO + 0 to 7 endpoint synchronization triggers bit auto-filp + enable + [7:0] + read-write + + + + + R8_UEP_T_BURST + USB endpoint sends a burst register + 0x18 + 0X8 + 0x00 + + + RB_UEP_T_BURST_EN + 0 to 7 endpoint send burst enable + [7:0] + read-write + + + + + R16_UEP_T_BURST_MODE + USB endpoint send the mode register + 0x19 + 0X8 + 0x00 + + + RB_UEP_T_BURST_MODE + 0 to 7 endpoint send the mode enable + [7:0] + read-write + + + + + R8_UEP_R_BURST + USB endpoint receives the burst register + 0x1A + 0X8 + 0x00 + + + RB_UEP_R_BURST_EN + 0 to 7 endpoint receive burst enable + [7:0] + read-write + + + + + R8_UEP_R_RES_MODE + USB endpoint reply mode register + 0x1B + 0X8 + 0x00 + + + RB_UEP_R_RES_MODE + 0 to 7 endpoint reply mode + [7:0] + read-write + + + + + R32_UEP_AF_MODE + USB endpoint muitiplexing register + 0x1C + 0X20 + 0x00000000 + + + RB_UEP_T_AF + 1 to 7 endpoint muitiplexing enables + [7:1] + read-write + + + + + + R32_UEP0_DMA + The start address register of the endpoint 0 buffer + 0x20 + 0x20 + 0x00000000 + + + UEP0_DMA + The start address of the endpoint 0 buffer + [23:0] + read-write + + + + + + R32_UEP1_RX_DMA + endpoint 1 receives the start address register of the buffer + 0x24 + 0x20 + 0x00000000 + + + UEP1_RX_DMA + endpoint receives the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP2_RX_DMA + endpoint 2 receives the start address register of the buffer + 0x28 + 0x20 + 0x00000000 + + + UEP2_RX_DMA + endpoint receives the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP3_RX_DMA + endpoint 3 receives the start address register of the buffer + 0x2C + 0x20 + 0x00000000 + + + UEP3_RX_DMA + endpoint receives the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP4_RX_DMA + endpoint 4 receives the start address register of the buffer + 0x30 + 0x20 + 0x00000000 + + + UEP4_RX_DMA + endpoint receives the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP5_RX_DMA + endpoint 5 receives the start address register of the buffer + 0x34 + 0x20 + 0x00000000 + + + UEP5_RX_DMA + endpoint receives the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP6_RX_DMA + endpoint 6 receives the start address register of the buffer + 0x38 + 0x20 + 0x00000000 + + + UEP6_RX_DMA + endpoint receives the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP7_RX_DMA + endpoint 7 receives the start address register of the buffer + 0x3C + 0x20 + 0x00000000 + + + UEP7_RX_DMA + endpoint receives the start address register of the buffer + [23:0] + read-write + + + + + + R32_UEP1_TX_DMA + endpoint 1 sends the start address register of the buffer + 0x40 + 0x20 + 0x00000000 + + + UEP1_TX_DMA + endpoint sends the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP2_TX_DMA + endpoint 2 sends the start address register of the buffer + 0x44 + 0x20 + 0x00000000 + + + UEP2_TX_DMA + endpoint sends the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP3_TX_DMA + endpoint 3 sends the start address register of the buffer + 0x48 + 0x20 + 0x00000000 + + + UEP3_TX_DMA + endpoint sends the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP4_TX_DMA + endpoint 4 sends the start address register of the buffer + 0x4C + 0x20 + 0x00000000 + + + UEP4_TX_DMA + endpoint sends the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP5_TX_DMA + endpoint 5 sends the start address register of the buffer + 0x50 + 0x20 + 0x00000000 + + + UEP5_TX_DMA + endpoint sends the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP6_TX_DMA + endpoint 6 sends the start address register of the buffer + 0x54 + 0x20 + 0x00000000 + + + UEP6_TX_DMA + endpoint sends the start address register of the buffer + [23:0] + read-write + + + + + R32_UEP7_TX_DMA + endpoint 7 sends the start address register of the buffer + 0x58 + 0x20 + 0x00000000 + + + UEP7_TX_DMA + endpoint sends the start address register of the buffer + [23:0] + read-write + + + + + + R32_UEP0_MAX_LEN + endpoint 0 max length packet register + 0X5C + 0x20 + read-write + 0x00000000 + + + UEP0_MAX_LEN + endpoint 0 max acceptable offset length + [10:0] + + + + + R32_UEP1_MAX_LEN + endpoint 1 max length packet register + 0X60 + 0x20 + read-write + 0x00000000 + + + UEP1_MAX_LEN + endpoint 1 max acceptable offset length + [6:0] + + + + + R32_UEP2_MAX_LEN + endpoint 2 max length packet register + 0X64 + 0x20 + read-write + 0x00000000 + + + UEP2_MAX_LEN + endpoint 2 max acceptable offset length + [6:0] + + + + + R32_UEP3_MAX_LEN + endpoint 3 max length packet register + 0X68 + 0x20 + read-write + 0x00000000 + + + UEP3_MAX_LEN + endpoint 3 max acceptable offset length + [6:0] + + + + + R32_UEP4_MAX_LEN + endpoint 4 max length packet register + 0X6C + 0x20 + read-write + 0x00000000 + + + UEP4_MAX_LEN + endpoint 4 max acceptable offset length + [6:0] + + + + + R32_UEP5_MAX_LEN + endpoint 5 max length packet register + 0X70 + 0x20 + read-write + 0x00000000 + + + UEP5_MAX_LEN + endpoint 5 max acceptable offset length + [6:0] + + + + + R32_UEP6_MAX_LEN + endpoint 6 max length packet register + 0X74 + 0x20 + read-write + 0x00000000 + + + UEP6_MAX_LEN + endpoint 6 max acceptable offset length + [6:0] + + + + + R32_UEP7_MAX_LEN + endpoint 7 max length packet register + 0X78 + 0x20 + read-write + 0x00000000 + + + UEP7_MAX_LEN + endpoint 7 max acceptable offset length + [6:0] + + + + + + R16_UEP0_RX_LEN + endpoint 0 acceptable length + 0X7C + 0x10 + read-write + 0x0000 + + + UEP0_RX_LEN + endpoint 0 acceptable data length + [6:0] + + + + + + R16_UEP1_RX_LEN + endpoint 1 receives the lenth register in a single pass + 0X80 + 0x10 + read-write + 0x0000 + + + UEP1_RX_LEN + the length of data received by endpoint 1 in a single pass + [15:0] + + + + + R16_UEP2_RX_LEN + endpoint 2 receives the lenth register in a single pass + 0X84 + 0x10 + read-write + 0x0000 + + + UEP2_RX_LEN + the length of data received by endpoint 2 in a single pass + [15:0] + + + + + R16_UEP3_RX_LEN + endpoint 3 receives the lenth register in a single pass + 0X88 + 0x10 + read-write + 0x0000 + + + UEP3_RX_LEN + the length of data received by endpoint 3 in a single pass + [15:0] + + + + + R16_UEP4_RX_LEN + endpoint 4 receives the lenth register in a single pass + 0X8c + 0x10 + read-write + 0x0000 + + + UEP4_RX_LEN + the length of data received by endpoint 4 in a single pass + [15:0] + + + + + R16_UEP5_RX_LEN + endpoint 5 receives the lenth register in a single pass + 0X90 + 0x10 + read-write + 0x0000 + + + UEP5_RX_LEN + the length of data received by endpoint 5 in a single pass + [15:0] + + + + + UEP6_RX_LEN + endpoint 6 receives the lenth register in a single pass + 0X94 + 0x10 + read-write + 0x0000 + + + UEP6_RX_LEN + the length of data received by endpoint 6 in a single pass + [15:0] + + + + + R16_UEP7_RX_LEN + endpoint 7 receives the lenth register in a single pass + 0X98 + 0x10 + read-write + 0x0000 + + + UEP7_RX_LEN + the length of data received by endpoint 7 in a single pass + [15:0] + + + + + + R16_UEP1_R_SIZE + the length register of the total received data at endpoint 1 + 0X82 + 0x10 + read-write + 0x0000 + + + UEP1_R_SIZE + the length of the total received data at endpoint 1 + [15:0] + + + + + R16_UEP2_R_SIZE + the length register of the total received data at endpoint 2 + 0X86 + 0x10 + read-write + 0x0000 + + + UEP2_R_SIZE + the length of the total received data at endpoint 2 + [15:0] + + + + + R16_UEP3_R_SIZE + the length register of the total received data at endpoint 3 + 0X8A + 0x10 + read-write + 0x0000 + + + UEP3_R_SIZE + the length of the total received data at endpoint 3 + [15:0] + + + + + R16_UEP4_R_SIZE + the length register of the total received data at endpoint 4 + 0X8E + 0x10 + read-write + 0x0000 + + + UEP4_R_SIZE + the length of the total received data at endpoint 4 + [15:0] + + + + + R16_UEP5_R_SIZE + the length register of the total received data at endpoint 5 + 0X92 + 0x10 + read-write + 0x0000 + + + UEP5_R_SIZE + the length of the total received data at endpoint 5 + [15:0] + + + + + R16_UEP6_R_SIZE + the length register of the total received data at endpoint 6 + 0X96 + 0x10 + read-write + 0x0000 + + + UEP6_R_SIZE + the length of the total received data at endpoint 6 + [15:0] + + + + + R16_UEP7_R_SIZE + the length register of the total received data at endpoint 7 + 0X9A + 0x10 + read-write + 0x0000 + + + UEP7_R_SIZE + the length of the total received data at endpoint 7 + [15:0] + + + + + + R16_UEP0_T_LEN + endpoint 0 send the length + 0x9C + 0x10 + 0x0000 + + + UEP0_T_LEN + endpoint 0 send the length + [6:0] + read-write + + + + + R8_UEP0_TX_CTRL + endpoint 0 send control register + 0x9E + 0x08 + 0x0000 + + + RB_UEP_T_RES_MASK + endpoint 0 control of the send response to IN transactions + [1:0] + read-write + + + RB_UEP_T_TOG_MASK + endpoint 0 synchronous trigger bit for the sender to + prepare + [2:2] + read-write + + + RB_UEP_T_NAK_ACT + endpoint 0 sends the end flag + [6:6] + read-write + + + RB_UEP_T_DONE + endpoint 0 sends the end of NAK flag + [7:7] + read-write + + + + + + R8_UEP0_RX_CTRL + endpoint 0 send control register + 0x9F + 0x08 + 0x00 + + + RB_UEP_R_RES_MASK + endpoint 0 has control over the received response + [1:0] + read-write + + + RB_UEP_R_TOG_MASK + the reception of endpoint 0 expects a synchronous trigger + bit + [2:2] + read-write + + + RB_UEP_R_SETUP_IS + whether endpoint 0 receives a SETUP transaction + [3:3] + read-only + + + RB_UEP_R_TOG_MATCH + received synchronization trigger bit matches the desired + synchronization trigger bit state + [4:4] + read-only + + + RB_UEP_R_NAK_TOG + endpoint 0 for the received return NAK,packet type + [5:5] + read-only + + + RB_UEP_R_NAK_ACT + endpoint 0 receives the end of NAK flag + [6:6] + read-write + + + RB_UEP_R_DONE + endpoint 0 receives the end flag + [7:7] + read-write + + + + + + R16_UEP1_T_LEN + endpoint 1 send the length register + 0xA0 + 0x10 + 0x0000 + + + UEP1_T_LEN + endpoint 1 send the length + [15:0] + read-write + + + + + R8_UEP1_TX_CTRL + endpoint 1 send control register + 0xA2 + 0x08 + 0x00 + + + RB_UEP_T_RES_MASK + endpoint 1 control of the send response to IN transactions + [1:0] + read-write + + + RB_UEP_T_TOG_MASK + endpoint 1 synchronous trigger bit for the sender to + prepare + [3:2] + read-write + + + RB_UEP_T_NAK_ACT + endpoint 1 sends the end flag + [6:6] + read-write + + + RB_UEP_T_DONE + endpoint 1 sends the end of NAK flag + [7:7] + read-write + + + + + R8_UEP1_RX_CTRL + endpoint 1 receive control + 0xA3 + 0x08 + 0x00 + + + RB_UEP_R_RES_MASK + endpoint 1 has control over the received response + [1:0] + read-write + + + RB_UEP_R_TOG_MASK + the reception of endpoint 1 expects a synchronous trigger + bit + [3:2] + read-write + + + RB_UEP_R_TOG_MATCH + received synchronization trigger bit matches the desired + synchronization trigger bit state + [4:4] + read-only + + + RB_UEP_R_NAK_TOG + endpoint 1 for the received return NAK,packet type + [5:5] + read-only + + + RB_UEP_R_NAK_ACT + endpoint 1 receives the end of NAK flag + [6:6] + read-write + + + RB_UEP_R_DONE + endpoint 1 receives the end flag + [7:7] + read-write + + + + + + R16_UEP2_T_LEN + endpoint 2 send the length register + 0xA4 + 0x10 + 0x00 + + + UEP2_T_LEN + endpoint 2 send the length + [15:0] + read-write + + + + + UEP2_TX_CTRL + endpoint 2 send control register + 0xA6 + 0x08 + 0x00 + + + RB_UEP_T_RES_MASK + endpoint 2 control of the send response to IN transactions + [1:0] + read-write + + + RB_UEP_T_TOG_MAS + endpoint 2 synchronous trigger bit for the sender to + prepare + [3:2] + read-write + + + RB_UEP_T_NAK_ACT + endpoint 2 sends the end flag + [6:6] + read-write + + + RB_UEP_T_DONE + endpoint 2 sends the end of NAK flag + [7:7] + read-write + + + + + R8_UEP2_RX_CTRL + endpoint 2 receive control + 0xA7 + 0x08 + 0x00 + + + RB_UEP_R_RES_MASK + endpoint 2 has control over the received response + [1:0] + read-write + + + RB_UEP_R_TOG_MASK + the reception of endpoint 2 expects a synchronous trigger + bit + [3:2] + read-write + + + RB_UEP_R_TOG_MATCH + received synchronization trigger bit matches the desired + synchronization trigger bit state + [4:4] + read-only + + + RB_UEP_R_NAK_TOG + endpoint 2 for the received return NAK,packet type + [5:5] + read-only + + + RB_UEP_R_NAK_ACT + endpoint 2 receives the end of NAK flag + [6:6] + read-write + + + RB_UEP_R_DONE + endpoint 2 receives the end flag + [7:7] + read-write + + + + + + R16_UEP3_T_LEN + endpoint 3 send the length register + 0xA8 + 0x10 + 0x0000 + + + UEP3_T_LEN + endpoint 3 send the length + [15:0] + read-write + + + + + R8_UEP3_TX_CTRL + endpoint 3 send control register + 0xAA + 0x08 + 0x00 + + + RB_UEP_T_RES_MASK + endpoint 3 control of the send response to IN transactions + [1:0] + read-write + + + RB_UEP_T_TOG_MASK + endpoint 3 synchronous trigger bit for the sender to + prepare + [3:2] + read-write + + + RB_UEP_T_NAK_ACT + endpoint 3 sends the end flag + [6:6] + read-write + + + RB_UEP_T_DONE + endpoint 3 sends the end of NAK flag + [7:7] + read-write + + + + + UEP3_RX_CTRL + endpoint 3 receive control + 0xAB + 0x08 + 0x00 + + + RB_UEP_R_RES_MASK + endpoint 3 has control over the received response + [1:0] + read-write + + + RB_UEP_R_TOG_MASK + the reception of endpoint 3 expects a synchronous trigger + bit + [3:2] + read-write + + + RB_UEP_R_TOG_MATCH + received synchronization trigger bit matches the desired + synchronization trigger bit state + [4:4] + read-only + + + RB_UEP_R_NAK_TOG + endpoint 3 for the received return NAK,packet type + [5:5] + read-only + + + RB_UEP_R_NAK_ACT + endpoint 3 receives the end of NAK flag + [6:6] + read-write + + + RB_UEP_R_DONE + endpoint 3 receives the end flag + [7:7] + read-write + + + + + + R16_UEP4_T_LEN + endpoint 4 send the length register + 0xAC + 0x10 + 0x0000 + + + UEP4_T_LEN + endpoint 4 send the length + [15:0] + read-write + + + + + UEP4_TX_CTRL + endpoint 4 send control register + 0xAE + 0x08 + 0x00 + + + RB_UEP_T_RES_MASK + endpoint 4 control of the send response to IN transactions + [1:0] + read-write + + + RB_UEP_T_TOG_MASK + endpoint 4 synchronous trigger bit for the sender to + prepare + [3:2] + read-write + + + RB_UEP_T_NAK_ACT + endpoint 4 sends the end flag + [6:6] + read-write + + + RB_UEP_T_DONE + endpoint 4 sends the end of NAK flag + [7:7] + read-write + + + + + R8_UEP4_RX_CTRL + endpoint 4 receive control + 0xAF + 0x08 + 0x00 + + + RB_UEP_R_RES_MASK + endpoint 4 has control over the received response + [1:0] + read-write + + + RB_UEP_R_TOG_MASK + the reception of endpoint 4 expects a synchronous trigger + bit + [3:2] + read-write + + + RB_UEP_R_TOG_MATCH + received synchronization trigger bit matches the desired + synchronization trigger bit state + [4:4] + read-only + + + RB_UEP_R_NAK_TOG + endpoint 4 for the received return NAK,packet type + [5:5] + read-only + + + RB_UEP_R_NAK_ACT + endpoint 4 receives the end of NAK flag + [6:6] + read-write + + + RB_UEP_R_DONE + endpoint 4 receives the end flag + [7:7] + read-write + + + + + + R16_UEP5_T_LEN + endpoint 5 send the length register + 0xB0 + 0x10 + 0x0000 + + + UEP5_T_LEN + endpoint 5 send the length + [15:0] + read-write + + + + + R8_UEP5_TX_CTRL + endpoint 5 send control register + 0xB2 + 0x08 + 0x00 + + + RB_UEP_T_RES_MASK + endpoint 5 control of the send response to IN transactions + [1:0] + read-write + + + RB_UEP_T_TOG_MASK + endpoint 5 synchronous trigger bit for the sender to + prepare + [3:2] + read-write + + + RB_UEP_T_NAK_ACT + endpoint 5 sends the end flag + [6:6] + read-write + + + RB_UEP_T_DONE + endpoint 5 sends the end of NAK flag + [7:7] + read-write + + + + + R8_UEP5_RX_CTRL + endpoint 5 receive control + 0xB3 + 0x08 + 0x00 + + + RB_UEP_R_RES_MASK + endpoint 5 has control over the received response + [1:0] + read-write + + + RB_UEP_R_TOG_MASK + the reception of endpoint 5 expects a synchronous trigger + bit + [3:2] + read-write + + + RB_UEP_R_TOG_MATCH + received synchronization trigger bit matches the desired + synchronization trigger bit state + [4:4] + read-only + + + RB_UEP_R_NAK_TOG + endpoint 5 for the received return NAK,packet type + [5:5] + read-only + + + RB_UEP_R_NAK_ACT + endpoint 5 receives the end of NAK flag + [6:6] + read-write + + + RB_UEP_R_DONE + endpoint 5 receives the end flag + [7:7] + read-write + + + + + + R16_UEP6_T_LEN + endpoint 6 send the length register + 0xB4 + 0x10 + 0x0000 + + + UEP6_T_LEN + endpoint 6 send the length + [15:0] + read-write + + + + + R8_UEP6_TX_CTRL + endpoint 6 send control register + 0xB6 + 0x08 + 0x00 + + + RB_UEP_T_RES_MASK + endpoint 6 control of the send response to IN transactions + [1:0] + read-write + + + RB_UEP_T_TOG_MASK + endpoint 6 synchronous trigger bit for the sender to + prepare + [3:2] + read-write + + + RB_UEP_T_NAK_ACT + endpoint 6 sends the end flag + [6:6] + read-write + + + RB_UEP_T_DONE + endpoint 6 sends the end of NAK flag + [7:7] + read-write + + + + + R8_UEP6_RX_CTRL + endpoint 6 receive control + 0xB7 + 0x08 + 0x00 + + + RB_UEP_R_RES_MASK + endpoint 6 has control over the received response + [1:0] + read-write + + + RB_UEP_R_TOG_MASK + the reception of endpoint 6 expects a synchronous trigger + bit + [3:2] + read-write + + + RB_UEP_R_TOG_MATCH + received synchronization trigger bit matches the desired + synchronization trigger bit state + [4:4] + read-only + + + RB_UEP_R_NAK_TOG + endpoint 6 for the received return NAK,packet type + [5:5] + read-only + + + RB_UEP_R_NAK_ACT + endpoint 6 receives the end of NAK flag + [6:6] + read-write + + + RB_UEP_R_DONE + endpoint 6 receives the end flag + [7:7] + read-write + + + + + + R16_UEP7_T_LEN + endpoint 7 send the length register + 0xB8 + 0x10 + 0x0000 + + + UEP7_T_LEN + endpoint 7 send the length + [15:0] + read-write + + + + + R8_UEP7_TX_CTRL + endpoint 7 send control register + 0xBA + 0x08 + 0x00 + + + RB_UEP_T_RES_MASK + endpoint 7 control of the send response to IN transactions + [1:0] + read-write + + + RB_UEP_T_TOG_MASK + endpoint 7 synchronous trigger bit for the sender to + prepare + [3:2] + read-write + + + RB_UEP_T_NAK_ACT + endpoint 7 sends the end flag + [6:6] + read-write + + + RB_UEP_T_DONE + endpoint 7 sends the end of NAK flag + [7:7] + read-write + + + + + R8_UEP7_RX_CTRL + endpoint 7 receive control + 0xBB + 0x08 + 0x00 + + + RB_UEP_R_RES_MASK + endpoint 7 has control over the received response + [1:0] + read-write + + + RB_UEP_R_TOG_MASK + the reception of endpoint 7 expects a synchronous trigger + bit + [3:2] + read-write + + + RB_UEP_R_TOG_MATCH + received synchronization trigger bit matches the desired + synchronization trigger bit state + [4:4] + read-only + + + RB_UEP_R_NAK_TOG + endpoint 7 for the received return NAK,packet type + [5:5] + read-only + + + RB_UEP_R_NAK_ACT + endpoint 7 receives the end of NAK flag + [6:6] + read-write + + + RB_UEP_R_DONE + endpoint 7 receives the end flag + [7:7] + read-write + + + + + + R16_UEP_T_ISO + usb endpoint sends a synchronous mode enable register + 0xBC + 0x10 + 0x0000 + + + RB_UEP_T_FIFO_EN + The FIFO mode of the TX of the endpoint is enabled + [15:9] + read-write + + + RB_UEPn_T_ISO_EN + upload endpoint(IN) synchronization mode enabled + [7:1] + read-write + + + + + + R16_UEP_R_ISO + usb endpoint receives a synchronous mode enable register + 0xBE + 0x10 + 0x0000 + + + RB_UEP_R_FIFO_EN + The FIFO mode of the TX of the endpoint is enabled + [15:9] + read-write + + + RB_UEPn_R_ISO_EN + down endpoint(OUT) synchronization mode enabled + [7:1] + read-write + + + + + + R32_UEP1_RX_FIFO + Receive FIFO address of usb endpoint 1 + 0xC0 + 0x20 + 0x00000000 + + + RB_UEP_RX_FIFO_E + The end FIFO address of the receiving endpoint + [31:16] + read-write + + + RB_UEP_RX_FIFO_S + The FIFO start address of the receiving endpoint + [15:0] + read-write + + + + + + R32_UEP2_RX_FIFO + Receive FIFO address of usb endpoint 2 + 0xC4 + 0x20 + 0x00000000 + + + RB_UEP_RX_FIFO_E + The end FIFO address of the receiving endpoint + [31:16] + read-write + + + RB_UEP_RX_FIFO_S + The FIFO start address of the receiving endpoint + [15:0] + read-write + + + + + + R32_UEP3_RX_FIFO + Receive FIFO address of usb endpoint 3 + 0xC8 + 0x20 + 0x00000000 + + + RB_UEP_RX_FIFO_E + The end FIFO address of the receiving endpoint + [31:16] + read-write + + + RB_UEP_RX_FIFO_S + The FIFO start address of the receiving endpoint + [15:0] + read-write + + + + + + R32_UEP4_RX_FIFO + Receive FIFO address of usb endpoint 4 + 0xCC + 0x20 + 0x00000000 + + + RB_UEP_RX_FIFO_E + The end FIFO address of the receiving endpoint + [31:16] + read-write + + + RB_UEP_RX_FIFO_S + The FIFO start address of the receiving endpoint + [15:0] + read-write + + + + + + R32_UEP5_RX_FIFO + Receive FIFO address of usb endpoint 5 + 0xD0 + 0x20 + 0x00000000 + + + RB_UEP_RX_FIFO_E + The end FIFO address of the receiving endpoint + [31:16] + read-write + + + RB_UEP_RX_FIFO_S + The FIFO start address of the receiving endpoint + [15:0] + read-write + + + + + + R32_UEP6_RX_FIFO + Receive FIFO address of usb endpoint 6 + 0xD4 + 0x20 + 0x00000000 + + + RB_UEP_RX_FIFO_E + The end FIFO address of the receiving endpoint + [31:16] + read-write + + + RB_UEP_RX_FIFO_S + The FIFO start address of the receiving endpoint + [15:0] + read-write + + + + + + R32_UEP7_RX_FIFO + Receive FIFO address of usb endpoint 7 + 0xD8 + 0x20 + 0x00000000 + + + RB_UEP_RX_FIFO_E + The end FIFO address of the receiving endpoint + [31:16] + read-write + + + RB_UEP_RX_FIFO_S + The FIFO start address of the receiving endpoint + [15:0] + read-write + + + + + + R32_UEP1_TX_FIFO + The sending FIFO address of usb endpoint 1 + 0xDC + 0x20 + 0x00000000 + + + RB_UEP_TX_FIFO_E + The end FIFO address of the sending endpoint + [31:16] + read-write + + + RB_UEP_TX_FIFO_S + The FIFO start address of the sending endpoint + [15:0] + read-write + + + + + + R32_UEP2_TX_FIFO + The sending FIFO address of usb endpoint 2 + 0xE0 + 0x20 + 0x00000000 + + + RB_UEP_TX_FIFO_E + The end FIFO address of the sending endpoint + [31:16] + read-write + + + RB_UEP_TX_FIFO_S + The FIFO start address of the sending endpoint + [15:0] + read-write + + + + + + R32_UEP3_TX_FIFO + The sending FIFO address of usb endpoint 3 + 0xE4 + 0x20 + 0x00000000 + + + RB_UEP_TX_FIFO_E + The end FIFO address of the sending endpoint + [31:16] + read-write + + + RB_UEP_TX_FIFO_S + The FIFO start address of the sending endpoint + [15:0] + read-write + + + + + + R32_UEP4_TX_FIFO + The sending FIFO address of usb endpoint 4 + 0xE8 + 0x20 + 0x00000000 + + + RB_UEP_TX_FIFO_E + The end FIFO address of the sending endpoint + [31:16] + read-write + + + RB_UEP_TX_FIFO_S + The FIFO start address of the sending endpoint + [15:0] + read-write + + + + + + R32_UEP5_TX_FIFO + The sending FIFO address of usb endpoint 5 + 0xEC + 0x20 + 0x00000000 + + + RB_UEP_TX_FIFO_E + The end FIFO address of the sending endpoint + [31:16] + read-write + + + RB_UEP_TX_FIFO_S + The FIFO start address of the sending endpoint + [15:0] + read-write + + + + + + R32_UEP6_TX_FIFO + The sending FIFO address of usb endpoint 6 + 0xF0 + 0x20 + 0x00000000 + + + RB_UEP_TX_FIFO_E + The end FIFO address of the sending endpoint + [31:16] + read-write + + + RB_UEP_TX_FIFO_S + The FIFO start address of the sending endpoint + [15:0] + read-write + + + + + + R32_UEP7_TX_FIFO + The sending FIFO address of usb endpoint 7 + 0xF4 + 0x20 + 0x00000000 + + + RB_UEP_TX_FIFO_E + The end FIFO address of the sending endpoint + [31:16] + read-write + + + RB_UEP_TX_FIFO_S + The FIFO start address of the sending endpoint + [15:0] + read-write + + + + + + R8_UH_CFG + USB host Configuration register + 0x100 + 0x08 + read-write + 0x07 + + + RB_UH_RST_LINK + USB connection controller module resets + [0:0] + + + RB_UH_RST_SIE + USB protocol processor reset + [1:1] + + + RB_UH_CLR_ALL + clear all interrupt flags + [2:2] + + + RB_UH_PHY_SUSPENDM + PHY suspend,close utmi clock + [3:3] + + + RB_UH_DMA_EN + DMA transfer enabled + [4:4] + + + RB_UH_SOF_EN + sof packet sending function enabled + [5:5] + + + RB_UH_FORCE_FS + forced full speed FS + [6:6] + + + RB_UH_LPM_EN + LPM enable + [7:7] + + + + + R8_UH_INT_EN + USB host interrupt enable register + 0x102 + 0x08 + read-write + 0x00 + + + RB_UHIE_WKUP_ACT + Wakeup interrupt enabled + [2:2] + + + RB_UHIE_RESUME_ACT + bus recovery interrupt was enabled + [3:3] + + + RB_UHIE_TRANSFER + USB transfer end interrupt enabled + [4:4] + + + RB_UHIE_SOF_ACT + sof packet sending interruption is enabled + [5:5] + + + RB_UHIE_TX_HALT + send pause interrupt enable + [6:6] + + + RB_UHIE_FIFO_OVER + FIFO overflow interrupt enable + [7:7] + + + + + R8_UH_DEV_AD + USB host device address register + 0x103 + 0x08 + read-write + 0x00 + + + RB_UH_DEV_ADDR + device address + [6:0] + + + + + R32_UH_CONTROL + USB host control register + 0x104 + 0x20 + read-write + 0x00000000 + + + RB_UH_RX_NO_RES + IN-DATA no answer,used for synchronous transfer or + high-speed SPLIT packets + [23:23] + + + RB_UH_TX_NO_RES + OUT or SETUP DATA no reply is extended and is used for + synchronous transmission or hign-speed SPLIT packets + [22:22] + + + RB_UH_RX_NO_DATA + DATA packets are not expected after IN token packets and + are used for + high-speed SPLIT packets + [21:21] + + + RB_UH_TX_NO_DATA + OUT or SETUP token packet packets are followed by no data + packets for hign-speed SPLIT packets + [20:20] + + + RB_UH_PRE_PID_EN + this bit is enabled when the port is operating at full + speed and needs to send low speed packets(PRE) + [19:19] + + + RB_UH_SPLIT_VALID + valid to send SPLIT packet + [18:18] + + + RB_UH_LPM_VALID + valid to send LMP packet + [17:17] + + + RB_UH_HOST_ACTION + host enables the transaction + [16:16] + + + RB_UH_BUF_MODE + DATA cache control bit + [10:10] + + + RB_UH_T_TOG_MASK + send data PID + [9:8] + + + RB_UH_T_ENDP_MASK + transaction token packet endpoint number + [7:4] + + + RB_UH_T_TOKEN_MASK + transaction token packet PID + [3:0] + + + + + R8_UH_INT_FLAG + USB HOST interrupt flag register + 0x108 + 0x08 + read-write + 0x00 + + + RB_UHIF_WKUP_ACT + Wakeup interrupt flag + [2:2] + + + RB_UHIF_RESUME_ACT_IF + bus recovery interrupt flag + [3:3] + + + RB_UHIF_TRANSFER + USB transaction transfer completion interrupt flag + [4:4] + + + RB_UHIF_SOF_ACT + sof packet delivert completion interrupt flag + [5:5] + + + RB_UHIF_TX_HALT + send pause interrupt flag + [6:6] + + + RB_UHIF_FIFO_OVER + FIFO overflow interrupt flag + [7:7] + + + + + R8_UH_INT_ST + USB host interrupt status + 0x109 + 0x08 + 0x00 + + + RB_UH_R_TOKEN_MASK + received PID + [3:0] + read-only + + + RB_UHIS_PORT_RX_RESUME + A bit of indicates that the port received a wakeup signal + [4:4] + read-write + + + + + R8_UH_MIS_ST + USB host miscellaneous status + 0x10A + 0x08 + 0x00 + + + RB_UHMS_SOF_FREE + port enabled state + [0:0] + read-only + + + RB_UHMS_SOF_PRE + The state of the USB SOF packet is indicated as follows + [1:1] + read-only + + + RB_UHMS_SOF_ACT + USB bus SOF status + [2:2] + read-write + + + RB_UHMS_USB_WAKEUP + USB bus wakes up + [3:3] + read-write + + + RB_UHMS_LINESTATE + USB bus status + [5:4] + read-only + + + RB_UHMS_BUS_J + J on USB bus + [6:6] + read-write + + + RB_UHMS_BUS_SE0 + SE0 on USB bus + [7:7] + read-only + + + + + R32_UH_LPM_DATA + USB host power management data register + 0x10C + 0x20 + read-write + 0x00000000 + + + RB_UH_LPM_DATA + power management data + [10:0] + + + + + R32_UH_SPLIT_DATA + USB host SPLIT register + 0x110 + 0x20 + read-write + 0x00000000 + + + RB_UH_SPLIT_DATA + SPLIT management data + [18:0] + + + + + R32_UH_FRAME + USB host frame register + 0x114 + 0x20 + 0x00000000 + + + RB_UH_FRAME_NO + the frame number + [10:0] + read-write + + + RB_UH_MFRAME_NO + microfame number + [18:16] + read-only + + + RB_UH_SOF_CNT_EN + SOF count enabled + [24:24] + read-write + + + RB_UH_SOF_CNT_CLR + the SOF count is cleared + [25:25] + read-write + + + + + R32_UH_TX_LEN + USB host send length register + 0x118 + 0x20 + read-write + 0x00000000 + + + RB_UH_TX_LEN + send data length + [10:0] + + + + + R32_UH_RX_LEN + USB host receive length register + 0x11C + 0x20 + read-write + 0x00000000 + + + RB_UH_RX_LEN + Received data length + [10:0] + + + + + R32_UH_RX_MAX_LEN + USB host receives the maximum length register + 0x120 + 0x20 + read-write + 0x00000000 + + + RB_UH_RX_MAX_LEN + receives the maximum length + [10:0] + + + + + R32_UH_RX_DMA + DMA receive address register + 0x124 + 0x20 + read-write + 0x00000000 + + + R32_UH_RX_DMA + Received address + [23:0] + + + + + R32_UH_TX_DMA + DMA send address register + 0x128 + 0x20 + read-write + 0x00000000 + + + R32_UH_TX_DMA + Send address + [23:0] + + + + + R32_UH_PORT_CTRL + USB host port control register + 0x12C + 0x20 + 0x00000000 + + + RB_UH_BUS_RST_LONG + BUS reset time selection + [16:16] + read-write + + + RB_UH_PORT_SLEEP_BESL + wake-up time control + [15:12] + read-write + + + RB_UH_CLR_PORT_SLEEP + the PORT exits the sleep state (LPM) + [8:8] + write-only + + + RB_UH_CLR_PORT_CONNECT + bring the PORT into the port state + [5:5] + write-only + + + RB_UH_CLR_PORT_EN + PORT exits the enabled state and enters the DISABLED state + [4:4] + write-only + + + RB_UH_SET_PORT_SLEEP + the PORT goes to sleep(LPM) + [3:3] + write-only + + + RB_UH_CLR_PORT_SUSP + the PORT exits the suspended state + [2:2] + write-only + + + RB_UH_SET_PORT_SUSP + the PORT is in a suspended state + [1:1] + write-only + + + RB_UH_SET_PORT_RESET + PORT send reset + [0:0] + write-only + + + + + R8_UH_PORT_CFG + USB host port Configuration register + 0x130 + 0x08 + 0x00 + + + RB_UH_PD_EN + the 15k resistance drop-down function is enable in host + mode + [7:7] + read-write + + + RB_UH_HOST_EN + USB port mode selection + [0:0] + read-write + + + + + R8_UH_PORT_INT_EN + USB host port interrupt enable register + 0x132 + 0x08 + 0x00 + + + RB_UHIE_PORT_SLP + port sleep state change interrupt enabled + [5:5] + read-write + + + RB_UHIE_PORT_RESET + port reset state change interrupt enabled + [4:4] + read-write + + + RB_UHIE_PORT_SUSP + port pause state change interrupt enabled + [2:2] + read-write + + + RB_UHIE_PORT_EN + port enable state change interrupt enabled + [1:1] + read-write + + + RB_UHIE_PORT_CONNECT + port connection state change interrupt enabled + [0:0] + read-write + + + + + R8_UH_PORT_TEST_CT + USB host port test mode register + 0x133 + 0x08 + 0x00 + + + RB_UH_TEST_SE0_NAK + test SE0 NAK + [4:4] + read-write + + + RB_UH_TEST_PACKET + test packet + [3:3] + read-write + + + RB_UH_TEST_FORCE_EN + test mode was enabled + [2:2] + read-write + + + RB_UH_TEST_K + test output K + [1:1] + read-write + + + RB_UH_TEST_J + test output J + [0:0] + read-write + + + + + R16_UH_PORT_ST + USB host port status register + 0x134 + 0x10 + 0x0010 + + + RB_UHIS_PORT_TEST + whether the port is in test mode + [11:11] + read-only + + + RB_UHIS_PORT_HS + whether the port connection speed is hign + [10:10] + read-only + + + RB_UHIS_PORT_LS + whether the port connection speed is low + [9:9] + read-only + + + RB_UHIS_PORT_SLP + port sleep + [5:5] + read-only + + + RB_UHIS_PORT_RST + port reset status + [4:4] + read-only + + + RB_UHIS_PORT_SUSP + port pause state + [2:2] + read-only + + + RB_UHIS_PORT_EN + port enabled + [1:1] + read-only + + + RB_UHIS_PORT_C0NNECT + port connection state + [0:0] + read-only + + + + + R8_UH_PORT_CHG + USB host port state charge register + 0x136 + 0x10 + 0x0010 + + + RB_UHIF_PORT_SLP + port sleep state charge + [5:5] + read-only + + + RB_UHIF_PORT_RESET + port reset state charge + [4:4] + read-only + + + RB_UHIF_PORT_SUSP + port pause state charge + [2:2] + read-only + + + RB_UHIF_PORT_EN + port enable state charge + [1:1] + read-only + + + RB_UHIF_PORT_CONNECT + port connection state charge + [0:0] + read-only + + + + + + R32_UH_BC_CTRL + USB host BC charging control register + 0x13C + 0x20 + 0x00 + + + RB_UDM_VSRC_ACT + In automatic mode, UDP outputs VBC_SRC ,otherwise it is + controlled by UDM_BC_CMPE + [10:10] + read-only + + + RB_UDM_BC_VSRC + UDM pin BC protocol source voltage enabled + [9:9] + read-write + + + RB_UDP_BC_VSRC + UDP pin BC protocol source voltage enabled + [8:8] + read-write + + + RB_BC_AUTO_MODE + Automatic mode enables + [6:6] + read-write + + + RB_UDM_BC_CMPE + UDM pin BC protocol comparator enables + [5:5] + read-write + + + RB_UDP_BC_CMPE + UDP pin BC protocol comparator enables + [4:4] + read-write + + + RB_UDM_BC_CMPO + UDM pin BC protocol comparator status + [1:1] + read-only + + + RB_UDP_BC_CMPO + UDP pin BC protocol comparator status + [0:0] + read-only + + + + + + + + CAN1 + Controller area network + CAN + 0x40006400 + + 0x00 + 0x200 + registers + + + CAN1_TX + CAN TX interrupts + 59 + + + CAN1_RX0 + CAN RX0 interrupts + 60 + + + CAN1_RX1 + CAN RX0 interrupts + 60 + + + CAN1_SCE + CAN SCE interrupt + 58 + + + + CTLR + CTLR + CAN Master control register + 0x00 + 0x20 + read-write + 0x00010002 + + + CFGCANM + Configure CAN offline recovery time + 17 + 1 + read-write + + + DBF + Debug freeze + 16 + 1 + read-write + + + RST + Software master reset + 15 + 1 + read-write + + + TTCM + Time triggered communication mode + 7 + 1 + read-write + + + ABOM + Automatic bus-off management + 6 + 1 + read-write + + + AWUM + Automatic wakeup mode + 5 + 1 + read-write + + + NART + No automatic retransmission + 4 + 1 + read-write + + + RFLM + Receive FIFO locked mode + 3 + 1 + read-write + + + TXFP + Transmit FIFO priority + 2 + 1 + read-write + + + SLEEP + Sleep mode request bit + 1 + 1 + read-write + + + INRQ + Initialization request + 0 + 1 + read-write + + + + + STATR + STATR + CAN master status register + 0x4 + 0x20 + 0x0000C002 + + + RX + Rx signal + 11 + 1 + read-only + + + SAMP + Last sample point + 10 + 1 + read-only + + + RXM + Receive mode + 9 + 1 + read-only + + + TXM + Transmit mode + 8 + 1 + read-only + + + SLAKI + Sleep acknowledge interrupt + 4 + 1 + read-write + + + WKUI + Wakeup interrupt + 3 + 1 + read-write + + + ERRI + Error interrupt + 2 + 1 + read-write + + + SLAK + Sleep acknowledge + 1 + 1 + read-only + + + INAK + Initialization acknowledge + 0 + 1 + read-only + + + + + TSTATR + TSTATR + CAN transmit status register + 0x8 + 0x20 + 0x1C000000 + + + LOW2 + Lowest priority flag for mailbox2 + 31 + 1 + read-only + + + LOW1 + Lowest priority flag for mailbox1 + 30 + 1 + read-only + + + LOW0 + Lowest priority flag for mailbox0 + 29 + 1 + read-only + + + TME2 + Transmit mailbox 2 empty + 28 + 1 + read-only + + + TME1 + Transmit mailbox 1 empty + 27 + 1 + read-only + + + TME0 + Transmit mailbox 0 empty + 26 + 1 + read-only + + + CODE + Mailbox code + 24 + 2 + read-only + + + ABRQ2 + Abort request for mailbox 2 + 23 + 1 + read-write + + + TERR2 + Transmission error of mailbox 2 + 19 + 1 + read-write + + + ALST2 + Arbitration lost for mailbox 2 + 18 + 1 + read-write + + + TXOK2 + Transmission OK of mailbox 2 + 17 + 1 + read-write + + + RQCP2 + Request completed mailbox2 + 16 + 1 + read-write + + + ABRQ1 + Abort request for mailbox 1 + 15 + 1 + read-write + + + TERR1 + Transmission error of mailbox1 + 11 + 1 + read-write + + + ALST1 + Arbitration lost for mailbox1 + 10 + 1 + read-write + + + TXOK1 + Transmission OK of mailbox1 + 9 + 1 + read-write + + + RQCP1 + Request completed mailbox1 + 8 + 1 + read-write + + + ABRQ0 + Abort request for mailbox0 + 7 + 1 + read-write + + + TERR0 + Transmission error of mailbox0 + 3 + 1 + read-write + + + ALST0 + Arbitration lost for mailbox0 + 2 + 1 + read-write + + + TXOK0 + Transmission OK of mailbox0 + 1 + 1 + read-write + + + RQCP0 + Request completed mailbox0 + 0 + 1 + read-write + + + + + RFIFO0 + RFIFO0 + CAN receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RFOM0 + Release FIFO 0 output mailbox + 5 + 1 + read-write + + + FOVR0 + FIFO 0 overrun + 4 + 1 + read-write + + + FULL0 + FIFO 0 full + 3 + 1 + read-write + + + FMP0 + FIFO 0 message pending + 0 + 2 + read-only + + + + + RFIFO1 + RFIFO1 + CAN receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RFOM1 + Release FIFO 1 output mailbox + 5 + 1 + read-write + + + FOVR1 + FIFO 1 overrun + 4 + 1 + read-write + + + FULL1 + FIFO 1 full + 3 + 1 + read-write + + + FMP1 + FIFO 1 message pending + 0 + 2 + read-only + + + + + INTENR + INTENR + CAN interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLKIE + Sleep interrupt + enable + 17 + 1 + read-write + + + WKUIE + Wakeup interrupt + enable + 16 + 1 + read-write + + + ERRIE + Error interrupt + enable + 15 + 1 + read-write + + + LECIE + Last error code interrupt + enable + 11 + 1 + read-write + + + BOFIE + Bus-off interrupt + enable + 10 + 1 + read-write + + + EPVIE + Error passive interrupt + enable + 9 + 1 + read-write + + + EWGIE + Error warning interrupt + enable + 8 + 1 + read-write + + + FOVIE1 + FIFO overrun interrupt + enable + 6 + 1 + read-write + + + FFIE1 + FIFO full interrupt + enable + 5 + 1 + read-write + + + FMPIE1 + FIFO message pending interrupt + enable + 4 + 1 + read-write + + + FOVIE0 + FIFO overrun interrupt + enable + 3 + 1 + read-write + + + FFIE0 + FIFO full interrupt + enable + 2 + 1 + read-write + + + FMPIE0 + FIFO message pending interrupt + enable + 1 + 1 + read-write + + + TMEIE + Transmit mailbox empty interrupt + enable + 0 + 1 + read-write + + + + + ERRSR + ERRSR + CAN error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Least significant byte of the 9-bit + transmit error counter + 16 + 8 + read-only + + + LEC + Last error code + 4 + 3 + read-write + + + BOFF + Bus-off flag + 2 + 1 + read-only + + + EPVF + Error passive flag + 1 + 1 + read-only + + + EWGF + Error warning + flag + 0 + 1 + read-only + + + + + BTIMR + BTIMR + CAN bit timing register + 0x1C + 0x20 + read-write + 0x01230000 + + + SILM + Silent mode (debug) + 31 + 1 + read-write + + + LBKM + Loop back mode (debug) + 30 + 1 + read-write + + + SJW + Resynchronization jump width + 24 + 4 + read-write + + + TS2 + Time segment 2 + 20 + 4 + read-write + + + TS1 + Time segment 1 + 16 + 4 + read-write + + + BTR_TS1_T + CLAS_LONG_TS1=0;TS1 is TS[3:0](4bit);CLAS_LONG_TS1=1,TS1 is + TS[1:0]+BTR_TS1_T[15:12](6bit) + 12 + 4 + read-write + + + BRP + minimum time unit length setting value + 0 + 10 + read-write + + + + + TTCTLR + TTCTLR + CAN time trigger control register + 0x20 + 0x20 + read-write + 0x0000ffff + + + MODE + Time-triggered mode selection + 17 + 1 + read-write + + + TIMRST + Internal counter reset control + 16 + 1 + write-only + + + TIMCMV + Internal counter count end value + 0 + 16 + read-write + + + + + TTCNT + TTCNT + CAN Time Trigger Count Value Register + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMCNT + time-triggered count value + 0 + 16 + read-write + + + + + TERR_CNT + TERR_CNT + CAN offline recovery error counter + 0x28 + 0x20 + read-write + 0x00000000 + + + TX_ERR_CNT + Offline recovery error count values + 0 + 9 + read-write + + + + + TXMI0R + TXMI0R + CAN TX mailbox identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + STID_EXID + Standard identifier + 21 + 11 + read-write + + + EXID + extended identifier + 3 + 18 + read-write + + + IDE + Identifier extension + 2 + 1 + read-write + + + RTR + Remote transmission request + 1 + 1 + read-write + + + TXRQ + Transmit mailbox request + 0 + 1 + read-write + + + + + TXMDT0R + TXMDT0R + CAN mailbox data length control and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-write + + + TGT + Transmit global time + 8 + 1 + read-write + + + DLC + Data length code + 0 + 4 + read-write + + + + + TXMDL0R + TXMDL0R + CAN mailbox data low register + 0x188 + 0x20 + read-write + 0x00000000 + + + DATA3 + Data byte 3 + 24 + 8 + read-write + + + DATA2 + Data byte 2 + 16 + 8 + read-write + + + DATA1 + Data byte 1 + 8 + 8 + read-write + + + DATA0 + Data byte 0 + 0 + 8 + read-write + + + + + TXMDH0R + TXMDH0R + CAN mailbox data high register + 0x18C + 0x20 + 0x00000000 + + + DATA7 + Data byte 7 + 24 + 8 + read-write + + + DATA6 + Data byte 6 + 16 + 8 + read-write + + + DATA5 + Data byte 5 + 8 + 8 + read-write + + + DATA4 + Data byte 4 + 0 + 8 + read-write + + + + + TXMI1R + TXMI1R + CAN TX mailbox identifier register + 0x190 + 0x20 + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-write + + + EXID + extended identifier + 3 + 18 + read-write + + + IDE + Identifier extension + 2 + 1 + read-write + + + RTR + Remote transmission request + 1 + 1 + read-write + + + TXRQ + Transmit mailbox request + 0 + 1 + read-write + + + + + TXMDT1R + TXMDT1R + CAN mailbox data length control and time stamp register + 0x194 + 0x20 + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-write + + + TGT + Transmit global time + 8 + 1 + read-write + + + DLC + Data length code + 0 + 4 + read-write + + + + + TXMDL1R + TXMDL1R + CAN mailbox data low register + 0x198 + 0x20 + 0x00000000 + + + DATA3 + Data byte 3 + 24 + 8 + read-write + + + DATA2 + Data byte 2 + 16 + 8 + read-write + + + DATA1 + Data byte 1 + 8 + 8 + read-write + + + DATA0 + Data byte 0 + 0 + 8 + read-write + + + + + TXMDH1R + TXMDH1R + CAN mailbox data high register + 0x19C + 0x20 + 0x00000000 + + + DATA7 + Data byte 7 + 24 + 8 + read-write + + + DATA6 + Data byte 6 + 16 + 8 + read-write + + + DATA5 + Data byte 5 + 8 + 8 + read-write + + + DATA4 + Data byte 4 + 0 + 8 + read-write + + + + + TXMI2R + TXMI2R + CAN TX mailbox identifier register + 0x1A0 + 0x20 + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-write + + + EXID + extended identifier + 3 + 18 + read-write + + + IDE + Identifier extension + 2 + 1 + read-write + + + RTR + Remote transmission request + 1 + 1 + read-write + + + TXRQ + Transmit mailbox request + 0 + 1 + read-write + + + + + TXMDT2R + TXMDT2R + CAN mailbox data length control and time stamp register + 0x1A4 + 0x20 + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-write + + + TGT + Transmit global time + 8 + 1 + read-write + + + DLC + Data length code + 0 + 4 + read-write + + + + + TXMDL2R + TXMDL2R + CAN mailbox data low register + 0x1A8 + 0x20 + 0x00000000 + + + DATA3 + Data byte 3 + 24 + 8 + read-write + + + DATA2 + Data byte 2 + 16 + 8 + read-write + + + DATA1 + Data byte 1 + 8 + 8 + read-write + + + DATA0 + Data byte 0 + 0 + 8 + read-write + + + + + TXMDH2R + TXMDH2R + CAN mailbox data high register + 0x1AC + 0x20 + 0x00000000 + + + DATA7 + Data byte 7 + 24 + 8 + read-write + + + DATA6 + Data byte 6 + 16 + 8 + read-write + + + DATA5 + Data byte 5 + 8 + 8 + read-write + + + DATA4 + Data byte 4 + 0 + 8 + read-write + + + + + RXMI0R + RXMI0R + CAN receive FIFO mailbox identifier register + 0x1B0 + 0x20 + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-only + + + EXID + extended identifier + 3 + 18 + read-only + + + IDE + Identifier extension + 2 + 1 + read-only + + + RTR + Remote transmission request + 1 + 1 + read-only + + + + + RXMDT0R + RXMDT0R + CAN receive FIFO mailbox data length control and time stamp + register + 0x1B4 + 0x20 + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-only + + + FMI + Filter match index + 8 + 8 + read-only + + + RES + RES bit of the received frame + 6 + 1 + read-only + + + ESI + ESI bit of the received frame + 5 + 1 + read-only + + + BRS + BRS bit of the received frame + 4 + 1 + read-only + + + DLC + Data length code + 0 + 4 + read-only + + + + + RXMDL0R + RXMDL0R + CAN receive FIFO mailbox data low register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + DATA3 + Data Byte 3 + 24 + 8 + read-only + + + DATA2 + Data Byte 2 + 16 + 8 + read-only + + + DATA1 + Data Byte 1 + 8 + 8 + read-only + + + DATA0 + Data Byte 0 + 0 + 8 + read-only + + + + + RXMDH0R + RXMDH0R + CAN receive FIFO mailbox data high register + 0x1BC + 0x20 + read-only + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + read-only + + + DATA6 + DATA6 + 16 + 8 + read-only + + + DATA5 + DATA5 + 8 + 8 + read-only + + + DATA4 + DATA4 + 0 + 8 + read-only + + + + + + RXMI1R + RXMI1R + CAN receive FIFO mailbox identifier register + 0x1C0 + 0x20 + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-only + + + EXID + extended identifier + 3 + 18 + read-only + + + IDE + Identifier extension + 2 + 1 + read-only + + + RTR + Remote transmission request + 1 + 1 + read-only + + + + + RXMDT1R + RXMDT1R + CAN receive FIFO mailbox data length control and time stamp + register + 0x1C4 + 0x20 + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-only + + + FMI + Filter match index + 8 + 8 + read-only + + + RES + RES bit of the received frame + 6 + 1 + read-only + + + ESI + ESI bit of the received frame + 5 + 1 + read-only + + + BRS + BRS bit of the received frame + 4 + 1 + read-only + + + DLC + Data length code + 0 + 4 + read-only + + + + + RXMDL1R + RXMDL1R + CAN receive FIFO mailbox data low register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + DATA3 + Data Byte 3 + 24 + 8 + read-only + + + DATA2 + Data Byte 2 + 16 + 8 + read-only + + + DATA1 + Data Byte 1 + 8 + 8 + read-only + + + DATA0 + Data Byte 0 + 0 + 8 + read-only + + + + + RXMDH1R + RXMDH1R + CAN receive FIFO mailbox data high register + 0x1CC + 0x20 + read-only + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + read-only + + + DATA6 + DATA6 + 16 + 8 + read-only + + + DATA5 + DATA5 + 8 + 8 + read-only + + + DATA4 + DATA4 + 0 + 8 + read-only + + + + + FCTLR + FCTLR + CAN filter master register + 0x200 + 0x20 + read-write + 0x2A1C0E01 + + + FINIT + Filter init mode + 0 + 1 + read-write + + + CAN2SB + CAN2 start bank + 8 + 5 + read-write + + + CAN3SB + CAN3 start bank + 16 + 6 + read-write + + + + + FMCFGR + FMCFGR + CAN filter mode register + 0x204 + 0x20 + read-write + 0x00000000 + + + FBM0 + Filter mode + 0 + 1 + read-write + + + FBM1 + Filter mode + 1 + 1 + read-write + + + FBM2 + Filter mode + 2 + 1 + read-write + + + FBM3 + Filter mode + 3 + 1 + read-write + + + FBM4 + Filter mode + 4 + 1 + read-write + + + FBM5 + Filter mode + 5 + 1 + read-write + + + FBM6 + Filter mode + 6 + 1 + read-write + + + FBM7 + Filter mode + 7 + 1 + read-write + + + FBM8 + Filter mode + 8 + 1 + read-write + + + FBM9 + Filter mode + 9 + 1 + read-write + + + FBM10 + Filter mode + 10 + 1 + read-write + + + FBM11 + Filter mode + 11 + 1 + read-write + + + FBM12 + Filter mode + 12 + 1 + read-write + + + FBM13 + Filter mode + 13 + 1 + read-write + + + FBM14 + Filter mode + 14 + 1 + read-write + + + FBM15 + Filter mode + 15 + 1 + read-write + + + FBM16 + Filter mode + 16 + 1 + read-write + + + FBM17 + Filter mode + 17 + 1 + read-write + + + FBM18 + Filter mode + 18 + 1 + read-write + + + FBM19 + Filter mode + 19 + 1 + read-write + + + FBM20 + Filter mode + 20 + 1 + read-write + + + FBM21 + Filter mode + 21 + 1 + read-write + + + FBM22 + Filter mode + 22 + 1 + read-write + + + FBM23 + Filter mode + 23 + 1 + read-write + + + FBM24 + Filter mode + 24 + 1 + read-write + + + FBM25 + Filter mode + 25 + 1 + read-write + + + FBM26 + Filter mode + 26 + 1 + read-write + + + FBM27 + Filter mode + 27 + 1 + read-write + + + + + FMCFGR1 + FMCFGR1 + CAN filter mode register 1 + 0x208 + 0x20 + read-write + 0x00000000 + + + FBM28 + Filter mode + 0 + 1 + read-write + + + FBM29 + Filter mode + 1 + 1 + read-write + + + FBM30 + Filter mode + 2 + 1 + read-write + + + FBM31 + Filter mode + 3 + 1 + read-write + + + FBM32 + Filter mode + 4 + 1 + read-write + + + FBM33 + Filter mode + 5 + 1 + read-write + + + FBM34 + Filter mode + 6 + 1 + read-write + + + FBM35 + Filter mode + 7 + 1 + read-write + + + FBM36 + Filter mode + 8 + 1 + read-write + + + FBM37 + Filter mode + 9 + 1 + read-write + + + FBM38 + Filter mode + 10 + 1 + read-write + + + FBM39 + Filter mode + 11 + 1 + read-write + + + FBM40 + Filter mode + 12 + 1 + read-write + + + FBM41 + Filter mode + 13 + 1 + read-write + + + + + FSCFGR + FSCFGR + CAN filter scale register + 0x20C + 0x20 + read-write + 0x00000000 + + + FSC0 + Filter scale configuration + 0 + 1 + read-write + + + FSC1 + Filter scale configuration + 1 + 1 + read-write + + + FSC2 + Filter scale configuration + 2 + 1 + read-write + + + FSC3 + Filter scale configuration + 3 + 1 + read-write + + + FSC4 + Filter scale configuration + 4 + 1 + read-write + + + FSC5 + Filter scale configuration + 5 + 1 + read-write + + + FSC6 + Filter scale configuration + 6 + 1 + read-write + + + FSC7 + Filter scale configuration + 7 + 1 + read-write + + + FSC8 + Filter scale configuration + 8 + 1 + read-write + + + FSC9 + Filter scale configuration + 9 + 1 + read-write + + + FSC10 + Filter scale configuration + 10 + 1 + read-write + + + FSC11 + Filter scale configuration + 11 + 1 + read-write + + + FSC12 + Filter scale configuration + 12 + 1 + read-write + + + FSC13 + Filter scale configuration + 13 + 1 + read-write + + + FSC14 + Filter scale configuration + 14 + 1 + read-write + + + FSC15 + Filter scale configuration + 15 + 1 + read-write + + + FSC16 + Filter scale configuration + 16 + 1 + read-write + + + FSC17 + Filter scale configuration + 17 + 1 + read-write + + + FSC18 + Filter scale configuration + 18 + 1 + read-write + + + FSC19 + Filter scale configuration + 19 + 1 + read-write + + + FSC20 + Filter scale configuration + 20 + 1 + read-write + + + FSC21 + Filter scale configuration + 21 + 1 + read-write + + + FSC22 + Filter scale configuration + 22 + 1 + read-write + + + FSC23 + Filter scale configuration + 23 + 1 + read-write + + + FSC24 + Filter scale configuration + 24 + 1 + read-write + + + FSC25 + Filter scale configuration + 25 + 1 + read-write + + + FSC26 + Filter scale configuration + 26 + 1 + read-write + + + FSC27 + Filter scale configuration + 27 + 1 + read-write + + + + + FSCFGR1 + FSCFGR1 + CAN filter scale register 1 + 0x210 + 0x20 + read-write + 0x00000000 + + + FSC28 + Filter scale configuration + 0 + 1 + read-write + + + FSC29 + Filter scale configuration + 1 + 1 + read-write + + + FSC30 + Filter scale configuration + 2 + 1 + read-write + + + FSC31 + Filter scale configuration + 3 + 1 + read-write + + + FSC32 + Filter scale configuration + 4 + 1 + read-write + + + FSC33 + Filter scale configuration + 5 + 1 + read-write + + + FSC34 + Filter scale configuration + 6 + 1 + read-write + + + FSC35 + Filter scale configuration + 7 + 1 + read-write + + + FSC36 + Filter scale configuration + 8 + 1 + read-write + + + FSC37 + Filter scale configuration + 9 + 1 + read-write + + + FSC38 + Filter scale configuration + 10 + 1 + read-write + + + FSC39 + Filter scale configuration + 11 + 1 + read-write + + + FSC40 + Filter scale configuration + 12 + 1 + read-write + + + FSC41 + Filter scale configuration + 13 + 1 + read-write + + + + + FAFIFOR + FAFIFOR + CAN filter FIFO assignment register + 0x214 + 0x20 + read-write + 0x00000000 + + + FFA0 + Filter FIFO assignment for filter + 0 + 0 + 1 + read-write + + + FFA1 + Filter FIFO assignment for filter + 1 + 1 + 1 + read-write + + + FFA2 + Filter FIFO assignment for filter + 2 + 2 + 1 + read-write + + + FFA3 + Filter FIFO assignment for filter + 3 + 3 + 1 + read-write + + + FFA4 + Filter FIFO assignment for filter + 4 + 4 + 1 + read-write + + + FFA5 + Filter FIFO assignment for filter + 5 + 5 + 1 + read-write + + + FFA6 + Filter FIFO assignment for filter + 6 + 6 + 1 + read-write + + + FFA7 + Filter FIFO assignment for filter + 7 + 7 + 1 + read-write + + + FFA8 + Filter FIFO assignment for filter + 8 + 8 + 1 + read-write + + + FFA9 + Filter FIFO assignment for filter + 9 + 9 + 1 + read-write + + + FFA10 + Filter FIFO assignment for filter + 10 + 10 + 1 + read-write + + + FFA11 + Filter FIFO assignment for filter + 11 + 11 + 1 + read-write + + + FFA12 + Filter FIFO assignment for filter + 12 + 12 + 1 + read-write + + + FFA13 + Filter FIFO assignment for filter + 13 + 13 + 1 + read-write + + + FFA14 + Filter FIFO assignment for filter + 14 + 14 + 1 + read-write + + + FFA15 + Filter FIFO assignment for filter + 15 + 15 + 1 + read-write + + + FFA16 + Filter FIFO assignment for filter + 16 + 16 + 1 + read-write + + + FFA17 + Filter FIFO assignment for filter + 17 + 17 + 1 + read-write + + + FFA18 + Filter FIFO assignment for filter + 18 + 18 + 1 + read-write + + + FFA19 + Filter FIFO assignment for filter + 19 + 19 + 1 + read-write + + + FFA20 + Filter FIFO assignment for filter + 20 + 20 + 1 + read-write + + + FFA21 + Filter FIFO assignment for filter + 21 + 21 + 1 + read-write + + + FFA22 + Filter FIFO assignment for filter + 22 + 22 + 1 + read-write + + + FFA23 + Filter FIFO assignment for filter + 23 + 23 + 1 + read-write + + + + + FAFIFOR1 + FAFIFOR1 + CAN filter FIFO assignment register 1 + 0x218 + 0x20 + read-write + 0x00000000 + + + FFA28 + Filter FIFO assignment for filter + 28 + 0 + 1 + read-write + + + FFA29 + Filter FIFO assignment for filter + 29 + 1 + 1 + read-write + + + FFA30 + Filter FIFO assignment for filter + 30 + 2 + 1 + read-write + + + FFA31 + Filter FIFO assignment for filter + 31 + 3 + 1 + read-write + + + FFA32 + Filter FIFO assignment for filter + 32 + 4 + 1 + read-write + + + FFA33 + Filter FIFO assignment for filter + 33 + 5 + 1 + read-write + + + FFA34 + Filter FIFO assignment for filter + 34 + 6 + 1 + read-write + + + FFA35 + Filter FIFO assignment for filter + 35 + 7 + 1 + read-write + + + FFA36 + Filter FIFO assignment for filter + 36 + 8 + 1 + read-write + + + FFA37 + Filter FIFO assignment for filter + 37 + 9 + 1 + read-write + + + FFA38 + Filter FIFO assignment for filter + 38 + 10 + 1 + read-write + + + FFA39 + Filter FIFO assignment for filter + 39 + 11 + 1 + read-write + + + FFA40 + Filter FIFO assignment for filter + 40 + 12 + 1 + read-write + + + FFA41 + Filter FIFO assignment for filter + 41 + 13 + 1 + read-write + + + + + FWR + FWR + CAN filter activation register + 0x21C + 0x20 + read-write + 0x00000000 + + + FACT0 + Filter active + 0 + 1 + read-write + + + FACT1 + Filter active + 1 + 1 + read-write + + + FACT2 + Filter active + 2 + 1 + read-write + + + FACT3 + Filter active + 3 + 1 + read-write + + + FACT4 + Filter active + 4 + 1 + read-write + + + FACT5 + Filter active + 5 + 1 + read-write + + + FACT6 + Filter active + 6 + 1 + read-write + + + FACT7 + Filter active + 7 + 1 + read-write + + + FACT8 + Filter active + 8 + 1 + read-write + + + FACT9 + Filter active + 9 + 1 + read-write + + + FACT10 + Filter active + 10 + 1 + read-write + + + FACT11 + Filter active + 11 + 1 + read-write + + + FACT12 + Filter active + 12 + 1 + read-write + + + FACT13 + Filter active + 13 + 1 + read-write + + + FACT14 + Filter active + 14 + 1 + read-write + + + FACT15 + Filter active + 15 + 1 + read-write + + + FACT16 + Filter active + 16 + 1 + read-write + + + FACT17 + Filter active + 17 + 1 + read-write + + + FACT18 + Filter active + 18 + 1 + read-write + + + FACT19 + Filter active + 19 + 1 + read-write + + + FACT20 + Filter active + 20 + 1 + read-write + + + FACT21 + Filter active + 21 + 1 + read-write + + + FACT22 + Filter active + 22 + 1 + read-write + + + FACT23 + Filter active + 23 + 1 + read-write + + + FACT24 + Filter active + 24 + 1 + read-write + + + FACT25 + Filter active + 25 + 1 + read-write + + + FACT26 + Filter active + 26 + 1 + read-write + + + FACT27 + Filter active + 27 + 1 + read-write + + + + + + FWR1 + FWR1 + CAN filter activation register 1 + 0x220 + 0x20 + read-write + 0x00000000 + + + FACT28 + Filter active + 0 + 1 + read-write + + + FACT29 + Filter active + 1 + 1 + read-write + + + FACT30 + Filter active + 2 + 1 + read-write + + + FACT31 + Filter active + 3 + 1 + read-write + + + FACT32 + Filter active + 4 + 1 + read-write + + + FACT33 + Filter active + 5 + 1 + read-write + + + FACT34 + Filter active + 6 + 1 + read-write + + + FACT35 + Filter active + 7 + 1 + read-write + + + FACT36 + Filter active + 8 + 1 + read-write + + + FACT37 + Filter active + 9 + 1 + read-write + + + FACT38 + Filter active + 10 + 1 + read-write + + + FACT39 + Filter active + 11 + 1 + read-write + + + FACT40 + Filter active + 12 + 1 + read-write + + + FACT41 + Filter active + 13 + 1 + read-write + + + + + F0R1 + F0R1 + Filter bank 0 register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F0R2 + F0R2 + Filter bank 0 register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F1R1 + F1R1 + Filter bank 1 register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F1R2 + F1R2 + Filter bank 1 register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F2R1 + F2R1 + Filter bank 2 register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F2R2 + F2R2 + Filter bank 2 register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F3R1 + F3R1 + Filter bank 3 register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F3R2 + F3R2 + Filter bank 3 register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F4R1 + F4R1 + Filter bank 4 register 1 + 0x260 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F4R2 + F4R2 + Filter bank 4 register 2 + 0x264 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F5R1 + F5R1 + Filter bank 5 register 1 + 0x268 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F5R2 + F5R2 + Filter bank 5 register 2 + 0x26C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F6R1 + F6R1 + Filter bank 6 register 1 + 0x270 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F6R2 + F6R2 + Filter bank 6 register 2 + 0x274 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F7R1 + F7R1 + Filter bank 7 register 1 + 0x278 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F7R2 + F7R2 + Filter bank 7 register 2 + 0x27C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F8R1 + F8R1 + Filter bank 8 register 1 + 0x280 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F8R2 + F8R2 + Filter bank 8 register 2 + 0x284 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F9R1 + F9R1 + Filter bank 9 register 1 + 0x288 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F9R2 + F9R2 + Filter bank 9 register 2 + 0x28C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F10R1 + F10R1 + Filter bank 10 register 1 + 0x290 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F10R2 + F10R2 + Filter bank 10 register 2 + 0x294 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F11R1 + F11R1 + Filter bank 11 register 1 + 0x298 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F11R2 + F11R2 + Filter bank 11 register 2 + 0x29C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F12R1 + F12R1 + Filter bank 4 register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F12R2 + F12R2 + Filter bank 12 register 2 + 0x2A4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F13R1 + F13R1 + Filter bank 13 register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F13R2 + F13R2 + Filter bank 13 register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F14R1 + F14R1 + Filter bank 14 register 1 + 0x2B0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F14R2 + F14R2 + Filter bank 14 register 2 + 0x2B4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F15R1 + F15R1 + Filter bank 15 register 1 + 0x2B8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F15R2 + F15R2 + Filter bank 15 register 2 + 0x2BC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F16R1 + F16R1 + Filter bank 16 register 1 + 0x2C0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F16R2 + F16R2 + Filter bank 16 register 2 + 0x2C4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F17R1 + F17R1 + Filter bank 17 register 1 + 0x2C8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F17R2 + F17R2 + Filter bank 17 register 2 + 0x2CC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F18R1 + F18R1 + Filter bank 18 register 1 + 0x2D0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F18R2 + F18R2 + Filter bank 18 register 2 + 0x2D4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F19R1 + F19R1 + Filter bank 19 register 1 + 0x2D8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F19R2 + F19R2 + Filter bank 19 register 2 + 0x2DC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F20R1 + F20R1 + Filter bank 20 register 1 + 0x2E0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F20R2 + F20R2 + Filter bank 20 register 2 + 0x2E4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F21R1 + F21R1 + Filter bank 21 register 1 + 0x2E8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F21R2 + F21R2 + Filter bank 21 register 2 + 0x2EC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F22R1 + F22R1 + Filter bank 22 register 1 + 0x2F0 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F22R2 + F22R2 + Filter bank 22 register 2 + 0x2F4 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F23R1 + F23R1 + Filter bank 23 register 1 + 0x2F8 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F23R2 + F23R2 + Filter bank 23 register 2 + 0x2FC + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F24R1 + F24R1 + Filter bank 24 register 1 + 0x300 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F24R2 + F24R2 + Filter bank 24 register 2 + 0x304 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F25R1 + F25R1 + Filter bank 25 register 1 + 0x308 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F25R2 + F25R2 + Filter bank 25 register 2 + 0x30C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F26R1 + F26R1 + Filter bank 26 register 1 + 0x310 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F26R2 + F26R2 + Filter bank 26 register 2 + 0x314 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F27R1 + F27R1 + Filter bank 27 register 1 + 0x318 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F27R2 + F27R2 + Filter bank 27 register 2 + 0x31C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + + F28R1 + F28R1 + Filter bank 28 register 1 + 0x720 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F28R2 + F0R2 + Filter bank 28 register 2 + 0x724 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F29R1 + F29R1 + Filter bank 29 register 1 + 0x728 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F29R2 + F29R2 + Filter bank 29 register 2 + 0x72C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F30R1 + F30R1 + Filter bank 30 register 1 + 0x730 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F30R2 + F30R2 + Filter bank 30 register 2 + 0x734 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F31R1 + F31R1 + Filter bank 31 register 1 + 0x738 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F31R2 + F31R2 + Filter bank 31 register 2 + 0x73C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F32R1 + F32R1 + Filter bank 32 register 1 + 0x740 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F32R2 + F32R2 + Filter bank 32 register 2 + 0x744 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F33R1 + F33R1 + Filter bank 33 register 1 + 0x748 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F33R2 + F33R2 + Filter bank 33 register 2 + 0x74C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F34R1 + F34R1 + Filter bank 34 register 1 + 0x750 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F34R2 + F34R2 + Filter bank 34 register 2 + 0x754 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F35R1 + F35R1 + Filter bank 35 register 1 + 0x758 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F35R2 + F35R2 + Filter bank 35 register 2 + 0x75C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F36R1 + F36R1 + Filter bank 36 register 1 + 0x760 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F36R2 + F36R2 + Filter bank 36 register 2 + 0x764 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F37R1 + F37R1 + Filter bank 37 register 1 + 0x768 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F37R2 + F37R2 + Filter bank 37 register 2 + 0x76C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F38R1 + F38R1 + Filter bank 38 register 1 + 0x770 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F38R2 + F38R2 + Filter bank 38 register 2 + 0x774 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F39R1 + F39R1 + Filter bank 39 register 1 + 0x778 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F39R2 + F39R2 + Filter bank 39 register 2 + 0x77C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F40R1 + F40R1 + Filter bank 40 register 1 + 0x780 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F40R2 + F40R2 + Filter bank 40 register 2 + 0x784 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F41R1 + F41R1 + Filter bank 41 register 1 + 0x788 + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F41R2 + F41R2 + Filter bank 41 register 2 + 0x78C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN TX interrupts + 113 + + + CAN2_RX0 + CAN RX0 interrupts + 114 + + + CAN2_RX1 + CAN RX1 interrupts + 115 + + + CAN2_SCE + CAN SCE interrupt + 112 + + + + CTLR + CTLR + CAN Master control register + 0x00 + 0x20 + read-write + 0x00010002 + + + CFGCANM + Configure CAN offline recovery time + 17 + 1 + read-write + + + DBF + Debug freeze + 16 + 1 + read-write + + + RST + Software master reset + 15 + 1 + read-write + + + TTCM + Time triggered communication mode + 7 + 1 + read-write + + + ABOM + Automatic bus-off management + 6 + 1 + read-write + + + AWUM + Automatic wakeup mode + 5 + 1 + read-write + + + NART + No automatic retransmission + 4 + 1 + read-write + + + RFLM + Receive FIFO locked mode + 3 + 1 + read-write + + + TXFP + Transmit FIFO priority + 2 + 1 + read-write + + + SLEEP + Sleep mode request bit + 1 + 1 + read-write + + + INRQ + Initialization request + 0 + 1 + read-write + + + + + STATR + STATR + CAN master status register + 0x4 + 0x20 + 0x0000C002 + + + RX + Rx signal + 11 + 1 + read-only + + + SAMP + Last sample point + 10 + 1 + read-only + + + RXM + Receive mode + 9 + 1 + read-only + + + TXM + Transmit mode + 8 + 1 + read-only + + + SLAKI + Sleep acknowledge interrupt + 4 + 1 + read-write + + + WKUI + Wakeup interrupt + 3 + 1 + read-write + + + ERRI + Error interrupt + 2 + 1 + read-write + + + SLAK + Sleep acknowledge + 1 + 1 + read-only + + + INAK + Initialization acknowledge + 0 + 1 + read-only + + + + + TSTATR + TSTATR + CAN transmit status register + 0x8 + 0x20 + 0x1C000000 + + + LOW2 + Lowest priority flag for mailbox2 + 31 + 1 + read-only + + + LOW1 + Lowest priority flag for mailbox1 + 30 + 1 + read-only + + + LOW0 + Lowest priority flag for mailbox0 + 29 + 1 + read-only + + + TME2 + Transmit mailbox 2 empty + 28 + 1 + read-only + + + TME1 + Transmit mailbox 1 empty + 27 + 1 + read-only + + + TME0 + Transmit mailbox 0 empty + 26 + 1 + read-only + + + CODE + Mailbox code + 24 + 2 + read-only + + + ABRQ2 + Abort request for mailbox 2 + 23 + 1 + read-write + + + TERR2 + Transmission error of mailbox 2 + 19 + 1 + read-write + + + ALST2 + Arbitration lost for mailbox 2 + 18 + 1 + read-write + + + TXOK2 + Transmission OK of mailbox 2 + 17 + 1 + read-write + + + RQCP2 + Request completed mailbox2 + 16 + 1 + read-write + + + ABRQ1 + Abort request for mailbox 1 + 15 + 1 + read-write + + + TERR1 + Transmission error of mailbox1 + 11 + 1 + read-write + + + ALST1 + Arbitration lost for mailbox1 + 10 + 1 + read-write + + + TXOK1 + Transmission OK of mailbox1 + 9 + 1 + read-write + + + RQCP1 + Request completed mailbox1 + 8 + 1 + read-write + + + ABRQ0 + Abort request for mailbox0 + 7 + 1 + read-write + + + TERR0 + Transmission error of mailbox0 + 3 + 1 + read-write + + + ALST0 + Arbitration lost for mailbox0 + 2 + 1 + read-write + + + TXOK0 + Transmission OK of mailbox0 + 1 + 1 + read-write + + + RQCP0 + Request completed mailbox0 + 0 + 1 + read-write + + + + + RFIFO0 + RFIFO0 + CAN receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RFOM0 + Release FIFO 0 output mailbox + 5 + 1 + read-write + + + FOVR0 + FIFO 0 overrun + 4 + 1 + read-write + + + FULL0 + FIFO 0 full + 3 + 1 + read-write + + + FMP0 + FIFO 0 message pending + 0 + 2 + read-only + + + + + RFIFO1 + RFIFO1 + CAN receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RFOM1 + Release FIFO 1 output mailbox + 5 + 1 + read-write + + + FOVR1 + FIFO 1 overrun + 4 + 1 + read-write + + + FULL1 + FIFO 1 full + 3 + 1 + read-write + + + FMP1 + FIFO 1 message pending + 0 + 2 + read-only + + + + + INTENR + INTENR + CAN interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLKIE + Sleep interrupt + enable + 17 + 1 + read-write + + + WKUIE + Wakeup interrupt + enable + 16 + 1 + read-write + + + ERRIE + Error interrupt + enable + 15 + 1 + read-write + + + LECIE + Last error code interrupt + enable + 11 + 1 + read-write + + + BOFIE + Bus-off interrupt + enable + 10 + 1 + read-write + + + EPVIE + Error passive interrupt + enable + 9 + 1 + read-write + + + EWGIE + Error warning interrupt + enable + 8 + 1 + read-write + + + FOVIE1 + FIFO overrun interrupt + enable + 6 + 1 + read-write + + + FFIE1 + FIFO full interrupt + enable + 5 + 1 + read-write + + + FMPIE1 + FIFO message pending interrupt + enable + 4 + 1 + read-write + + + FOVIE0 + FIFO overrun interrupt + enable + 3 + 1 + read-write + + + FFIE0 + FIFO full interrupt + enable + 2 + 1 + read-write + + + FMPIE0 + FIFO message pending interrupt + enable + 1 + 1 + read-write + + + TMEIE + Transmit mailbox empty interrupt + enable + 0 + 1 + read-write + + + + + ERRSR + ERRSR + CAN error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Least significant byte of the 9-bit + transmit error counter + 16 + 8 + read-only + + + LEC + Last error code + 4 + 3 + read-write + + + BOFF + Bus-off flag + 2 + 1 + read-only + + + EPVF + Error passive flag + 1 + 1 + read-only + + + EWGF + Error warning + flag + 0 + 1 + read-only + + + + + BTIMR + BTIMR + CAN bit timing register + 0x1C + 0x20 + read-write + 0x01230000 + + + SILM + Silent mode (debug) + 31 + 1 + read-write + + + LBKM + Loop back mode (debug) + 30 + 1 + read-write + + + SJW + Resynchronization jump width + 24 + 4 + read-write + + + TS2 + Time segment 2 + 20 + 4 + read-write + + + TS1 + Time segment 1 + 16 + 4 + read-write + + + BTR_TS1_T + CLAS_LONG_TS1=0;TS1 is TS[3:0](4bit);CLAS_LONG_TS1=1,TS1 is + TS[1:0]+BTR_TS1_T[15:12](6bit) + 12 + 4 + read-write + + + BRP + minimum time unit length setting value + 0 + 10 + read-write + + + + + TTCTLR + TTCTLR + CAN time trigger control register + 0x20 + 0x20 + read-write + 0x0000ffff + + + MODE + Time-triggered mode selection + 17 + 1 + read-write + + + TIMRST + Internal counter reset control + 16 + 1 + write-only + + + TIMCMV + Internal counter count end value + 0 + 16 + read-write + + + + + TTCNT + TTCNT + CAN Time Trigger Count Value Register + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMCNT + time-triggered count value + 0 + 16 + read-write + + + + + TERR_CNT + TERR_CNT + CAN offline recovery error counter + 0x28 + 0x20 + read-write + 0x00000000 + + + TX_ERR_CNT + Offline recovery error count values + 0 + 9 + read-write + + + + + TXMI0R + TXMI0R + CAN TX mailbox identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + STID_EXID + Standard identifier + 21 + 11 + read-write + + + EXID + extended identifier + 3 + 18 + read-write + + + IDE + Identifier extension + 2 + 1 + read-write + + + RTR + Remote transmission request + 1 + 1 + read-write + + + TXRQ + Transmit mailbox request + 0 + 1 + read-write + + + + + TXMDT0R + TXMDT0R + CAN mailbox data length control and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-write + + + TGT + Transmit global time + 8 + 1 + read-write + + + DLC + Data length code + 0 + 4 + read-write + + + + + TXMDL0R + TXMDL0R + CAN mailbox data low register + 0x188 + 0x20 + read-write + 0x00000000 + + + DATA3 + Data byte 3 + 24 + 8 + read-write + + + DATA2 + Data byte 2 + 16 + 8 + read-write + + + DATA1 + Data byte 1 + 8 + 8 + read-write + + + DATA0 + Data byte 0 + 0 + 8 + read-write + + + + + TXMDH0R + TXMDH0R + CAN mailbox data high register + 0x18C + 0x20 + 0x00000000 + + + DATA7 + Data byte 7 + 24 + 8 + read-write + + + DATA6 + Data byte 6 + 16 + 8 + read-write + + + DATA5 + Data byte 5 + 8 + 8 + read-write + + + DATA4 + Data byte 4 + 0 + 8 + read-write + + + + + TXMI1R + TXMI1R + CAN TX mailbox identifier register + 0x190 + 0x20 + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-write + + + EXID + extended identifier + 3 + 18 + read-write + + + IDE + Identifier extension + 2 + 1 + read-write + + + RTR + Remote transmission request + 1 + 1 + read-write + + + TXRQ + Transmit mailbox request + 0 + 1 + read-write + + + + + TXMDT1R + TXMDT1R + CAN mailbox data length control and time stamp register + 0x194 + 0x20 + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-write + + + TGT + Transmit global time + 8 + 1 + read-write + + + DLC + Data length code + 0 + 4 + read-write + + + + + TXMDL1R + TXMDL1R + CAN mailbox data low register + 0x198 + 0x20 + 0x00000000 + + + DATA3 + Data byte 3 + 24 + 8 + read-write + + + DATA2 + Data byte 2 + 16 + 8 + read-write + + + DATA1 + Data byte 1 + 8 + 8 + read-write + + + DATA0 + Data byte 0 + 0 + 8 + read-write + + + + + TXMDH1R + TXMDH1R + CAN mailbox data high register + 0x19C + 0x20 + 0x00000000 + + + DATA7 + Data byte 7 + 24 + 8 + read-write + + + DATA6 + Data byte 6 + 16 + 8 + read-write + + + DATA5 + Data byte 5 + 8 + 8 + read-write + + + DATA4 + Data byte 4 + 0 + 8 + read-write + + + + + TXMI2R + TXMI2R + CAN TX mailbox identifier register + 0x1A0 + 0x20 + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-write + + + EXID + extended identifier + 3 + 18 + read-write + + + IDE + Identifier extension + 2 + 1 + read-write + + + RTR + Remote transmission request + 1 + 1 + read-write + + + TXRQ + Transmit mailbox request + 0 + 1 + read-write + + + + + TXMDT2R + TXMDT2R + CAN mailbox data length control and time stamp register + 0x1A4 + 0x20 + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-write + + + TGT + Transmit global time + 8 + 1 + read-write + + + DLC + Data length code + 0 + 4 + read-write + + + + + TXMDL2R + TXMDL2R + CAN mailbox data low register + 0x1A8 + 0x20 + 0x00000000 + + + DATA3 + Data byte 3 + 24 + 8 + read-write + + + DATA2 + Data byte 2 + 16 + 8 + read-write + + + DATA1 + Data byte 1 + 8 + 8 + read-write + + + DATA0 + Data byte 0 + 0 + 8 + read-write + + + + + TXMDH2R + TXMDH2R + CAN mailbox data high register + 0x1AC + 0x20 + 0x00000000 + + + DATA7 + Data byte 7 + 24 + 8 + read-write + + + DATA6 + Data byte 6 + 16 + 8 + read-write + + + DATA5 + Data byte 5 + 8 + 8 + read-write + + + DATA4 + Data byte 4 + 0 + 8 + read-write + + + + + RXMI0R + RXMI0R + CAN receive FIFO mailbox identifier register + 0x1B0 + 0x20 + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-only + + + EXID + extended identifier + 3 + 18 + read-only + + + IDE + Identifier extension + 2 + 1 + read-only + + + RTR + Remote transmission request + 1 + 1 + read-only + + + + + RXMDT0R + RXMDT0R + CAN receive FIFO mailbox data length control and time stamp + register + 0x1B4 + 0x20 + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-only + + + FMI + Filter match index + 8 + 8 + read-only + + + RES + RES bit of the received frame + 6 + 1 + read-only + + + ESI + ESI bit of the received frame + 5 + 1 + read-only + + + BRS + BRS bit of the received frame + 4 + 1 + read-only + + + DLC + Data length code + 0 + 4 + read-only + + + + + RXMDL0R + RXMDL0R + CAN receive FIFO mailbox data low register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + DATA3 + Data Byte 3 + 24 + 8 + read-only + + + DATA2 + Data Byte 2 + 16 + 8 + read-only + + + DATA1 + Data Byte 1 + 8 + 8 + read-only + + + DATA0 + Data Byte 0 + 0 + 8 + read-only + + + + + RXMDH0R + RXMDH0R + CAN receive FIFO mailbox data high register + 0x1BC + 0x20 + read-only + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + read-only + + + DATA6 + DATA6 + 16 + 8 + read-only + + + DATA5 + DATA5 + 8 + 8 + read-only + + + DATA4 + DATA4 + 0 + 8 + read-only + + + + + + RXMI1R + RXMI1R + CAN receive FIFO mailbox identifier register + 0x1C0 + 0x20 + 0x00000000 + + + STID + Standard identifier + 21 + 11 + read-only + + + EXID + extended identifier + 3 + 18 + read-only + + + IDE + Identifier extension + 2 + 1 + read-only + + + RTR + Remote transmission request + 1 + 1 + read-only + + + + + RXMDT1R + RXMDT1R + CAN receive FIFO mailbox data length control and time stamp + register + 0x1C4 + 0x20 + 0x00000000 + + + TIME + Message time stamp + 16 + 16 + read-only + + + FMI + Filter match index + 8 + 8 + read-only + + + RES + RES bit of the received frame + 6 + 1 + read-only + + + ESI + ESI bit of the received frame + 5 + 1 + read-only + + + BRS + BRS bit of the received frame + 4 + 1 + read-only + + + DLC + Data length code + 0 + 4 + read-only + + + + + RXMDL1R + RXMDL1R + CAN receive FIFO mailbox data low register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + DATA3 + Data Byte 3 + 24 + 8 + read-only + + + DATA2 + Data Byte 2 + 16 + 8 + read-only + + + DATA1 + Data Byte 1 + 8 + 8 + read-only + + + DATA0 + Data Byte 0 + 0 + 8 + read-only + + + + + RXMDH1R + RXMDH1R + CAN receive FIFO mailbox data high register + 0x1CC + 0x20 + read-only + 0x00000000 + + + DATA7 + DATA7 + 24 + 8 + read-only + + + DATA6 + DATA6 + 16 + 8 + read-only + + + DATA5 + DATA5 + 8 + 8 + read-only + + + DATA4 + DATA4 + 0 + 8 + read-only + + + + + + + + CAN3 + 0x40007800 + + CAN3_TX + CAN TX interrupts + 137 + + + CAN3_RX0 + CAN RX0 interrupts + 138 + + + CAN3_RX1 + CAN RX1 interrupts + 139 + + + CAN3_SCE + CAN SCE interrupt + 136 + + + + + DVP + Digital Video Port + DVP + 0x40025800 + + 0x0 + 0x400 + registers + + + DVP + DVP global Interrupt + interrupt + 120 + + + + CR0 + CR0 + Digital Video control register + (DVP_CR0) + 0x00 + 0x08 + read-write + 0x00 + + + RB_DVP_ENABLE + DVP enable + 0 + 1 + read-write + + + RB_DVP_V_POLAR + DVP VSYNC polarity control + 1 + 1 + read-write + + + RB_DVP_H_POLAR + DVP HSYNC polarity control + 2 + 1 + read-write + + + RB_DVP_P_POLAR + DVP PCLK polarity control + 3 + 1 + read-write + + + RB_DVP_MSK_DAT_MOD + DVP data mode + 4 + 2 + + + RB_DVP_JPEG + DVP JPEG mode + 6 + 1 + read-write + + + + + CR1 + CR1 + Digital Video control register + (DVP_CR1) + 0x01 + 0x08 + read-write + 0x06 + + + RB_DVP_DMA_ENABLE + DVP dma enable + 0 + 1 + read-write + + + RB_DVP_ALL_CLR + DVP all clear + 1 + 1 + read-write + + + RB_DVP_RCV_CLR + DVP receive logic clear + 2 + 1 + read-write + + + RB_DVP_BUF_TOG + DVP bug toggle by software + 3 + 1 + read-write + + + RB_DVP_CM + DVP capture mode + 4 + 1 + read-write + + + RB_DVP_CROP + DVP Crop feature enable + 5 + 1 + read-write + + + RB_DVP_FCRC + DVP frame capture rate control + 6 + 2 + read-write + + + + + IER + IER + Digital Video Interrupt register + (DVP_IER) + 0x02 + 0x08 + read-write + 0x00 + + + RB_DVP_IE_STR_FRM + DVP frame start interrupt enable + 0 + 1 + read-write + + + RB_DVP_IE_ROW_DONE + DVP row received done interrupt enable + 1 + 1 + read-write + + + RB_DVP_IE_FRM_DONE + DVP frame received done interrupt enable + 2 + 1 + read-write + + + RB_DVP_IE_FIFO_OV + DVP receive fifo overflow interrupt enable + 3 + 1 + read-write + + + RB_DVP_IE_STP_FRM + DVP frame stop interrupt enable + 4 + 1 + read-write + + + + + ROW_NUM + ROW_NUM + Image line count configuration register + (DVP_ROW_NUM) + 0x04 + 0x10 + read-write + 0x0000 + + + RB_DVP_ROW_NUM + The number of rows of frame image data + 0 + 16 + read-write + + + + + COL_NUM + COL_NUM + Image column number configuration register + (DVP_COL_NUM) + 0x06 + 0x10 + read-write + 0x0000 + + + RB_DVP_COL_NUM + Number of PCLK cycles for row data + 0 + 16 + read-write + + + + + DMA_BUF0 + DMA_BUF0 + Digital Video DMA address register + (DVP_DMA_BUF0) + 0x08 + 0x20 + read-write + 0x00000000 + + + RB_DVP_DMA_BUF0 + DMA receive address 0 + 0 + 32 + read-write + + + + + DMA_BUF1 + DMA_BUF1 + Digital Video DMA address register + (DVP_DMA_BUF1) + 0x0C + 0x20 + read-write + 0x00000000 + + + RB_DVP_DMA_BUF1 + DMA receive address 1 + 0 + 32 + read-write + + + + + IFR + IFR + Digital Video Flag register + (DVP_IFR) + 0x10 + 0x08 + read-write + 0x00 + + + RB_DVP_IF_STR_FRM + DVP frame start interrupt enable + 0 + 1 + read-write + + + RB_DVP_IF_ROW_DONE + DVP row received done interrupt enable + 1 + 1 + read-write + + + RB_DVP_IF_FRM_DONE + DVP frame received done interrupt enable + 2 + 1 + read-write + + + RB_DVP_IF_FIFO_OV + DVP receive fifo overflow interrupt enable + 3 + 1 + read-write + + + RB_DVP_IF_STP_FRM + DVP frame stop interrupt enable + 4 + 1 + read-write + + + + + STATUS + STATUS + Digital Video STATUS register + (DVP_STATUS) + 0x11 + 0x08 + read-only + 0x00 + + + RB_DVP_FIFO_RDY + DVP frame start interrupt enable + 0 + 1 + read-only + + + RB_DVP_FIFO_FULL + DVP row received done interrupt enable + 1 + 1 + read-only + + + RB_DVP_FIFO_OV + DVP frame received done interrupt enable + 2 + 1 + read-only + + + RB_DVP_MSK_FIFO_CNT + DVP receive fifo overflow interrupt enable + 4 + 3 + read-only + + + + + ROW_CNT + ROW_CNT + Digital Video line counter register + (DVP_ROW_CNT) + 0x14 + 0x10 + read-only + 0x0000 + + + RB_DVP_ROW_CNT + The number of rows of frame image data + 0 + 16 + read-only + + + + + HOFFCNT + HOFFCNT + Digital Video horizontal displacement register + (DVP_HOFFCNT) + 0x18 + 0x10 + read-write + 0x0000 + + + RB_DVP_HOFFCNT + Number of PCLK cycles for row data + 0 + 16 + read-write + + + + + VST + VST + Digital Video line number register + (DVP_VST) + 0x1A + 0x10 + read-write + 0x0000 + + + RB_DVP_VST + The number of lines captured by the image + 0 + 16 + read-write + + + + + CAPCNT + CAPCNT + Digital Video Capture count register + (DVP_CAPCNT) + 0x1C + 0x10 + read-write + 0x0000 + + + RB_DVP_CAPCNT + Number of PCLK cycles captured by clipping window + 0 + 16 + read-write + + + + + VLINE + VLINE + Digital Video Vertical line count register + (DVP_VLINE) + 0x1E + 0x10 + read-write + 0x0000 + + + RB_DVP_VLINE + Crop the number of rows captured by window + 0 + 16 + read-write + + + + + DR + DR + Digital Video Data register + (DVP_DR) + 0x20 + 0x20 + read-only + 0x00000000 + + + RB_DVP_DR + Prevent DMA overflow + 0 + 32 + + + + + + + + RNG + Random number generator + RNG + 0x40023C00 + + 0x0 + 0x400 + registers + + + RNG + RNG interrupt + 146 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt + status + 6 + 1 + read-write + + + CEIS + Clock error interrupt + status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + + SERDES + Serial-parallel interconversion controller and transceiver + SERDES + 0x40027C00 + + 0x0 + 0x400 + registers + + + SERDES + SERDES global interrupt + 83 + + + + SERDES1_CTRL + SERDES1_CTRL + SERDESx Control Register + 0x00 + 0x20 + read-write + 0x00041207 + + + ALIGN_EN + A ALIGN signal is inserted at the time of transmission, + and it is highly effective to solve the frequency offset + 18 + 1 + + + CONT_EN + Replace the SYNC at idle with CONT and scrambling data to reduce EMI + 17 + 1 + + + TX_PWR_UP + Power-on enable bit of transmit module + 15 + 1 + + + RX_PWR_UP + Receiver module power-up enable bit + 14 + 1 + + + DMA_EN + DMA enables + 7 + 1 + + + TX_EN + Send Enable + 6 + 1 + + + RX_EN + Receiver Enable + 5 + 1 + + + RX_POLARITY + RXN/RXP signal exchange + 4 + 1 + + + INT_BUSY_EN + The SERDES transmission is complete, and the interruption flag is not cleared + 3 + 1 + + + RESET_PHY + SERDES Physical Layer Software Reset Control Bits + 2 + 1 + + + RESET_LINK + SERDES Link Layer Software Reset Control Bits + 1 + 1 + + + CLR_ALL + Clear the SERDES interrupt flag and FIFO + 0 + 1 + + + + + SERDES1_INT_EN + SERDES1_INT_EN + SERDESx interrupt enable register + 0x04 + 0x20 + read-write + 0x00000000 + + + COMINIT_IE + COMIT RECEIVE INTERRUPT ENABLES + 5 + 1 + + + FIFO_OV_IE + FIFO overflow interrupt enabled + 3 + 1 + + + RECV_DONE_IE + Receive Completion Interrupt Enables + 2 + 1 + + + TRAN_DONE_IE_RECV_ERR_IE + Transmission Mode: Interrupt Enabled for Transmission Completion; + Receive Mode: Receive CRC Error Interrupt Enabled + 1 + 1 + + + PHYRDY_IE + PHYS-LAYER READY INTERRUPT ENABLES + 0 + 1 + + + + + SERDES1_INT_FS + SERDES1_INT_FS + SERDESx Interrupt Flag/Status Register + 0x08 + 0x20 + 0x00000000 + + + TX_SEQ_NUM + LINK_INIT automatically clears when it is valid + 28 + 4 + read-only + + + RX_SEQ_NUM + In the receive mode, the received COMINT is automatically cleared + 24 + 4 + read-only + + + R_FIFO_RDY + SERDES receives FIFO data readiness status + 21 + 1 + read-only + + + LINK_FREE + The SERDES link layer sends the idle status bits + 20 + 1 + read-only + + + PLL_LOCK + The PLL locks the status bit + 19 + 1 + read-only + + + RECV_CRC_OK + The receive dataframe checks the status bit, detects it after RECV_DONE interrupt, + and updates it after the packet is received + 18 + 1 + read-only + + + RX_SEQ_MATCH + Receive SEQ_NUM match status bits + 17 + 1 + read-only + + + PHYRDY + The physical layer READY status bit + 16 + 1 + read-only + + + COMINIT_IF + COMIT receives the interrupt flag + 5 + 1 + read-write + + + FIFO_OV_IF + FIFO overflows the interrupt flag + 3 + 1 + read-write + + + RECV_DONE_IF + Receive the Interrupt Completion flag + 2 + 1 + read-write + + + TRAN_DONE_IF_RECV_ERR_IF + Sending Mode: The signal of the interrupt is completed. + Receive Mode: Receives the CRC error interrupt flag. + 1 + 1 + read-write + + + PHYRDY_IF + The physical layer READY interrupt flag + 0 + 1 + read-write + + + + + SERDES1_RTX_CTRL + SERDES1_RTX_CTRL + SERDESx Transceiver Controller + 0x0C + 0x20 + read-write + 0x00000000 + + + BUF_MODE + Double-buffered control bit + 18 + 1 + + + TX_VLD + The sent packet is valid, zeroed by the software, and the bit is returned and synchronized with the PHY_CLK + 17 + 1 + + + LINK_INIT + This bit is 1 and sends a LINK initialization packet + 16 + 1 + + + SERDES_TX_LEN + Number of data bytes sent, the lower 2 bits are fixed at 0 (4-byte aligned) + 0 + 16 + + + + + SERDES1_RX_LEN0 + SERDES1_RX_LEN0 + SERDESx Receive Length 0 Register + 0x10 + 0x20 + read-only + 0x00000000 + + + SERDES_RX_LEN0 + The packet length of the last received data, with the lowest 2 digits fixed at 0 + 0 + 16 + + + + + SERDES1_DATA0 + SERDES1_DATA0 + SERDESx Data 0 Buffer Register + 0x14 + 0x20 + read-write + 0x00000000 + + + SERDES_DATA0 + SERDES data buffer 0 + 0 + 32 + + + + + SERDES1_DMA0 + SERDES1_DMA0 + Start address register + 0x18 + 0x20 + read-write + 0x00000000 + + + SERDES_DMA0 + Buffer 0 start address, in receive mode, + the software needs to align the lower 4 fixed bits 0 (16 bytes), + and in send mode, it does not need to align 16 bytes + 0 + 32 + + + + + SERDES1_RX_LEN1 + SERDES1_RX_LEN1 + SERDESx Receive Length 1 Register + 0x1C + 0x20 + read-only + 0x00000000 + + + SERDES_RX_LEN1 + The packet length of the last received data, with the lowest 2 digits fixed at 1 + 0 + 16 + + + + + SERDES1_DATA1 + SERDES1_DATA1 + SERDESx Data 1 Buffer Register + 0x20 + 0x20 + read-write + 0x00000000 + + + SERDES_DATA1 + SERDES data buffer 1 + 0 + 32 + + + + + SERDES1_DMA1 + SERDES1_DMA1 + Start address register + 0x24 + 0x20 + read-write + 0x00000000 + + + SERDES_DMA1 + Buffer 0 start address, in receive mode, + the software needs to align the lower 4 fixed bits 0 (16 bytes), + and in send mode, it does not need to align 16 bytes + 0 + 32 + + + + + + SERDES2_CTRL + SERDES2_CTRL + SERDESx Control Register + 0x40 + 0x20 + read-write + 0x00041207 + + + ALIGN_EN + A ALIGN signal is inserted at the time of transmission, + and it is highly effective to solve the frequency offset + 18 + 1 + + + CONT_EN + Replace the SYNC at idle with CONT and scrambling data to reduce EMI + 17 + 1 + + + PHY_PWR_UP + Enable bits on the physical layer + 16 + 1 + + + TX_PWR_UP + Power-on enable bit of transmit module + 15 + 1 + + + RX_PWR_UP + Receiver module power-up enable bit + 14 + 1 + + + PLL_FACTOR + PLL Clock Control Coefficient + 8 + 5 + + + DMA_EN + DMA enables + 7 + 1 + + + TX_EN + Send Enable + 6 + 1 + + + RX_EN + Receiver Enable + 5 + 1 + + + RX_POLARITY + RXN/RXP signal exchange + 4 + 1 + + + INT_BUSY_EN + The SERDES transmission is complete, and the interruption flag is not cleared + 3 + 1 + + + RESET_PHY + SERDES Physical Layer Software Reset Control Bits + 2 + 1 + + + RESET_LINK + SERDES Link Layer Software Reset Control Bits + 1 + 1 + + + CLR_ALL + Clear the SERDES interrupt flag and FIFO + 0 + 1 + + + + + SERDES2_INT_EN + SERDES2_INT_EN + SERDESx interrupt enable register + 0x44 + 0x20 + read-write + 0x00000000 + + + COMINIT_IE + COMIT RECEIVE INTERRUPT ENABLES + 5 + 1 + + + FIFO_OV_IE + FIFO overflow interrupt enabled + 3 + 1 + + + RECV_DONE_IE + Receive Completion Interrupt Enables + 2 + 1 + + + TRAN_DONE_IE_RECV_ERR_IE + Transmission Mode: Interrupt Enabled for Transmission Completion; + Receive Mode: Receive CRC Error Interrupt Enabled + 1 + 1 + + + PHYRDY_IE + PHYS-LAYER READY INTERRUPT ENABLES + 0 + 1 + + + + + SERDES2_INT_FS + SERDES1_INT_FS + SERDESx Interrupt Flag/Status Register + 0x48 + 0x20 + 0x00000000 + + + TX_SEQ_NUM + LINK_INIT automatically clears when it is valid + 28 + 4 + read-only + + + RX_SEQ_NUM + In the receive mode, the received COMINT is automatically cleared + 24 + 4 + read-only + + + R_FIFO_RDY + SERDES receives FIFO data readiness status + 21 + 1 + read-only + + + LINK_FREE + The SERDES link layer sends the idle status bits + 20 + 1 + read-only + + + PLL_LOCK + The PLL locks the status bit + 19 + 1 + read-only + + + RECV_CRC_OK + The receive dataframe checks the status bit, detects it after RECV_DONE interrupt, + and updates it after the packet is received + 18 + 1 + read-only + + + RX_SEQ_MATCH + Receive SEQ_NUM match status bits + 17 + 1 + read-only + + + PHYRDY + The physical layer READY status bit + 16 + 1 + read-only + + + COMINIT_IF + COMIT receives the interrupt flag + 5 + 1 + read-write + + + FIFO_OV_IF + FIFO overflows the interrupt flag + 3 + 1 + read-write + + + RECV_DONE_IF + Receive the Interrupt Completion flag + 2 + 1 + read-write + + + TRAN_DONE_IF_RECV_ERR_IF + Sending Mode: The signal of the interrupt is completed. + Receive Mode: Receives the CRC error interrupt flag. + 1 + 1 + read-write + + + PHYRDY_IF + The physical layer READY interrupt flag + 0 + 1 + read-write + + + + + SERDES2_RTX_CTRL + SERDES2_RTX_CTRL + SERDESx Transceiver Controller + 0x4C + 0x20 + read-write + 0x00000000 + + + BUF_MODE + Double-buffered control bit + 18 + 1 + + + TX_VLD + The sent packet is valid, zeroed by the software, and the bit is returned and synchronized with the PHY_CLK + 17 + 1 + + + LINK_INIT + This bit is 1 and sends a LINK initialization packet + 16 + 1 + + + SERDES_TX_LEN + Number of data bytes sent, the lower 2 bits are fixed at 0 (4-byte aligned) + 0 + 16 + + + + + SERDES2_RX_LEN0 + SERDES2_RX_LEN0 + SERDESx Receive Length 0 Register + 0x50 + 0x20 + read-only + 0x00000000 + + + SERDES_RX_LEN0 + The packet length of the last received data, with the lowest 2 digits fixed at 0 + 0 + 16 + + + + + SERDES2_DATA0 + SERDES2_DATA0 + SERDESx Data 0 Buffer Register + 0x54 + 0x20 + read-write + 0x00000000 + + + SERDES_DATA0 + SERDES data buffer 0 + 0 + 32 + + + + + SERDES2_DMA0 + SERDES1_DMA0 + Start address register + 0x58 + 0x20 + read-write + 0x00000000 + + + SERDES_DMA0 + Buffer 0 start address, in receive mode, + the software needs to align the lower 4 fixed bits 0 (16 bytes), + and in send mode, it does not need to align 16 bytes + 0 + 32 + + + + + SERDES2_RX_LEN1 + SERDES2_RX_LEN1 + SERDESx Receive Length 1 Register + 0x5C + 0x20 + read-only + 0x00000000 + + + SERDES_RX_LEN1 + The packet length of the last received data, with the lowest 2 digits fixed at 1 + 0 + 16 + + + + + SERDES2_DATA1 + SERDES2_DATA1 + SERDESx Data 1 Buffer Register + 0x60 + 0x20 + read-write + 0x00000000 + + + SERDES_DATA1 + SERDES data buffer 1 + 0 + 32 + + + + + SERDES2_DMA1 + SERDES1_DMA1 + Start address register + 0x64 + 0x20 + read-write + 0x00000000 + + + SERDES_DMA1 + Buffer 0 start address, in receive mode, + the software needs to align the lower 4 fixed bits 0 (16 bytes), + and in send mode, it does not need to align 16 bytes + 0 + 32 + + + + + + + + USBSS + USB3.0 ultra-high speed host /device controller + USBSS + 0x40034000 + + 0x0 + 0x400 + registers + + + USBSS + USBSS global interrupt + 62 + + + USBSS_LINK + USBSS LINK interrupt + 63 + + + USBSSWakeUP + USBSS wake-up interrupt + 65 + + + + R32_USBSS_CTRL + USBSS Control Register + 0x70 + 0x20 + 0x00000006 + + + RB_DEV_ADDR + Host Mode + [30:24] + read-write + + + RB_UIE_FIFO_RXOV + Receive FIFO overflow interrupt enabled + [23:23] + read-write + + + RB_UIE_FIFO_TXOV + Sending FIFO overflow interrupt enables + [22:22] + read-write + + + RB_UIE_ITP + Send ITP to complete interrupt enable + [20:20] + read-write + + + RB_UIE_RX_PING + Interrupt Enabled for Receiving PING-TP + [19:19] + read-write + + + RB_UDIE_STATUS__UHIE_NOTIF + Device mode: Receiving STATUS transaction completion interrupt enabled; + Host mode: Interrupt enabled for receiving DEV_NOTIF-TP + [18:18] + read-write + + + RB_UDIE_SETUP__UHIE_ERDY + Device Mode: Receive SETUP Transaction Completion Interrupt Enabled; + Host mode:Receive SETUP Transaction Completion Interrupt Enabled + [17:17] + read-write + + + RB_UIE_TRANSFER + USB Transaction Completion Interrupt Enabled + [16:16] + read-write + + + RB_TX_ERDY_MODE + Use in device mode + [14:14] + read-write + + + RB_REG_HP_PEND + Packet Pending control bit for sending TP/DP packets + [9:8] + read-write + + + RB_HOST_MODE + USB Operating Mode Selection Bits + [7:7] + read-write + + + RB_ITP_EN + In host mode, send ITP enabled + [6:6] + read-write + + + RB_SETUP_FLOW + SETUP transaction throttling + [5:5] + read-write + + + RB_DMA_MODE + When DPH is transmitted in bursts, the next packet of data status + [3:3] + read-write + + + RB_FORCE_RST + The protocol layer and FIFO module are reset and need to be cleared by software. + [2:2] + read-write + + + RB_USB_CLR_ALL + Reset all software configuration registers, high validity, software clearance required + [1:1] + read-write + + + RB_DMA_EN + Enable DMA + [0:0] + read-write + + + + + STATUS + USBSS Status Register + 0x74 + 0x20 + 0x00000000 + + + RB_HRX_RES + A reply TP is received from the device back + [31:30] + read-write + + + RB_HTX_RES + Received a reply TP from the device returning + [23:22] + read-write + + + RB_HOST_ACK_NUMP + This bit is invalid for synchronous transmission, and is defined as follows in Control Transfer, + Block Transfer, and Interrupt Transfer + [20:16] + read-write + + + RB_EP_DIR + The direction of the endpoint that currently has an interrupt flag for transmission completion, + [12:12] + read-write + + + RB_EP_ID + If multiple endpoints have interrupt flags at the same time, the order of endpoint priority is as follows + [10:8] + read-write + + + RB_UIF_FIFO_RXOV + Receive FIFO overflow interrupt flag + [7:7] + read-write + + + RB_UIF_FIFO_TXOV + Send FIFO overflow interrupt flag + [6:6] + read-write + + + RB_UIF_ITP + Send the ITP Complete Interrupt flag + [4:4] + read-write + + + RB_UIF_RX_PING + Receive PING-TP Complete Interrupt Flag + [3:3] + read-write + + + RB_UHIF_NOTIF__UDIF_STATUS + Host Mode: Receive DEV_NOTIF-TP Complete Interrupt Flag; + Device Mode: Receive STATUS Transaction Completion Interrupt Flag + [2:2] + read-write + + + RB_UHIF_ERDY__UDIF_SETUP + Host Mode: Receive ERDY-TP Complete Interrupt Flag; + Device Mode: Receive SETUP Transaction Completion Interrupt Flag + [1:1] + read-write + + + RB_UIF_TRANSFER + USB Transaction Completion Interrupt Flag + [0:0] + read-write + + + + + UH_TX_DMA_U3EP0_TX_DMA + Send buffer address registers + 0x8C + 0x20 + 0x00000000 + + + U3EP0_TX_DMA + Host Mode:The start address of the host sending buffer. + Device Mode:Endpoint 0 sends the start of the buffer. + [31:0] + read-write + + + + + UH_RX_DMA_U3EP0_RX_DMA + Receive buffer address registers + 0x90 + 0x20 + 0x00000000 + + + U3EP0_RX_DMA + Host Mode:The start address of the host receiving buffer. + Device Mode:Endpoint 0 receives the start of the buffer. + [31:0] + read-write + + + + + + ITP + Interval Registers for ITP packets in USB + 0x78 + 0x20 + 0x00000000 + + + REG_ITP_INTERVAL + Bus interval Counter field in the received ITP. + [13:0] + read-only + + + + + ITP_ADJ + Interval Adaptive Registers for ITP packets in USB + 0x7C + 0x20 + 0x00000000 + + + ITP_DELTA + The higher 13-bit delta of the ITS in + the ITP received in device mode indicates the time difference from the start of the current + ITP packet to the previous bus interval boundary. + [20:8] + read-only + + + ITP_DELAYED + In device mode, the Delayed bit of Link Control Word in the received ITP is 1 when the ITP is delayed. + [7:7] + read-only + + + ITP_ADJ_CR + In device mode, the Bus Interval Adjustment Control field in the received ITP should be 0 after power-on reset or device disconnection. + [6:0] + read-only + + + + + UEP_TX_EN + Endpoint Sends Enable Register + 0x80 + 0x10 + 0x00000001 + + + RB_EP_TX_EN + Endpoints 1~15 upload enabled + [15:1] + read-write + + + + + UEP_RX_EN + Endpoint Receive Enable Register + 0x82 + 0x10 + 0x00000001 + + + RB_EP_RX_EN + Endpoints 1~15 downpass enabled + [15:1] + read-write + + + + + UEP0_TX_CTRL + Endpoint 0 sends control registers + 0x84 + 0x20 + 0x00000000 + + + RB_UIF_EP0_TX_ACT + The upload transaction is interrupted, the software writes 0 to zero, and the hardware sets 1. + [31:31] + read-write + + + RB_EP0_TX_FLOW + A sign that completes the NRDY-TP send (answer) + [25:25] + read-only + + + RB_EP0_TX_PP + The PP bit in the received ACK-TP + [24:24] + read-only + + + RB_EP0_TX_ERDY + ERDY received + [23:23] + read-write + + + RB_EP0_TX_RES + Response to ACK-TP + [22:21] + read-write + + + RB_EP0_TX_SEQ + The current sequence number of the endpoint, + which is aotomatically reset after receiving the SETUP transaction + [20:16] + read-write + + + RB_EP0_TX_LEN + Endpoint transmits length registers with a maximum value of 512B + [10:0] + read-write + + + + + UEP0_RX_CTRL + Endpoint 0 receives control registers + 0x88 + 0x20 + 0x00000000 + + + RB_UIF_EP0_RX_ACT + Upload the transaction completion interrupt flag, the software writes 0 to zero, and the hardware sets 1 + [31:31] + read-write + + + RB_EP0_RX_PP + PP bits in the received DPH + [24:24] + read-only + + + RB_EP0_RX_ERDY + ERDY received + [23:23] + read-write + + + RB_EP0_RX_RES + Response to DPH + [22:21] + read-write + + + RB_EP0_RX_SEQ + The sequence number of the endpoint expects to accept + [20:16] + read-write + + + RB_EP0_RX_LEN + The endpoint receives the length register + [10:0] + read-only + + + + + + UEP1_TX_CFG + Endpoint 1 Configuration Register + 0xC0 + 0x8 + 0x86 + + + RB_EP_TX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_TX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_TX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_TX_EOB_MODE + If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP + [3:3] + read-write + + + RB_EP_TX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_TX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_TX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP1_TX_CR + Endpoint 1 control register + 0xC1 + 0x8 + 0x10 + + + RB_EP_TX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_TX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_TX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_TX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP1_TX_SEQ + Endpoint 1 Serial Number Register + 0xC2 + 0x8 + 0x00 + + + RB_TX_EP_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP1_TX_ST + Endpoint 1 status register + 0xC3 + 0x8 + 0x00 + + + RB_TX_EP_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_TX_EP_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_TX_EP_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_TX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_TX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP1_TX_CHAIN_CR + Endpoint 1 CHAIN control register + 0xC4 + 0x8 + 0x00 + + + RB_TX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_TX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_TX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_TX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP1_TX_CHAIN_ST + Endpoint 1 CHAIN state register + 0xC5 + 0x8 + 0x00 + + + RB_TX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_TX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_TX_EOB_LPF + EOB/LPF bits in the last packet of DPH in the current CHAIN + [5:5] + read-write + + + RB_TX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_TX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_TX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP1_TX_CHAIN_LEN + Endpoint 1 CHAIN sends the last packet length + 0xC6 + 0x10 + 0x00 + + + CHAIN_TX_LEN + The length of the last packet sent by the CHAIN + [10:0] + read-only + + + + + UEP1_TX_CHAIN_EXP_NUMP + Number of NUMPs expected to be sent by endpoint 1 + 0xC8 + 0x10 + 0x00 + + + TX_CHAIN_EXP_NUMP + The number of DPP packets that can be sent by the currently completed CHAIN + [7:0] + read-write + + + + + UEP1_TX_CHAIN_NUMP + Number of NUMPs has been sent by endpoint n + 0xC9 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that have been transmitted + [7:0] + read-write + + + + + UEP1_TX_DMA_OFS + DMA offset length for endpoint 1 + 0xCA + 0x10 + 0x0000 + + + CHAIN_TX_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-write + + + + + UEP1_TX_DMA + DMA start address for endpoint 1 + 0xCC + 0x20 + 0x00000000 + + + CHAIN_TX_DMA + Normal mode:The DMA start address of the CHAIN to send data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP2_TX_CFG + Endpoint 2 Configuration Register + 0xE0 + 0x8 + 0x86 + + + RB_EP_TX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_TX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_TX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_TX_EOB_MODE + If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP + [3:3] + read-write + + + RB_EP_TX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_TX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_TX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP2_TX_CR + Endpoint 2 control register + 0xE1 + 0x8 + 0x10 + + + RB_EP_TX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_TX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_TX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_TX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP2_TX_SEQ + Endpoint 2 Serial Number Register + 0xE2 + 0x8 + 0x00 + + + RB_TX_EP_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP2_TX_ST + Endpoint 2 status register + 0xE3 + 0x8 + 0x00 + + + RB_TX_EP_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_TX_EP_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_TX_EP_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_TX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_TX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP2_TX_CHAIN_CR + Endpoint 2 CHAIN control register + 0xE4 + 0x8 + 0x00 + + + RB_TX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_TX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_TX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_TX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP2_TX_CHAIN_ST + Endpoint 2 CHAIN state register + 0xE5 + 0x8 + 0x00 + + + RB_TX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_TX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_TX_EOB_LPF + EOB/LPF bits in the last packet of DPH in the current CHAIN + [5:5] + read-write + + + RB_TX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_TX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_TX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP2_TX_CHAIN_LEN + Endpoint 2 CHAIN sends the last packet length + 0xE6 + 0x10 + 0x00 + + + CHAIN_TX_LEN + The length of the last packet sent by the CHAIN + [10:0] + read-only + + + + + UEP2_TX_CHAIN_EXP_NUMP + Number of NUMPs expected to be sent by endpoint 2 + 0xE8 + 0x10 + 0x00 + + + TX_CHAIN_EXP_NUMP + The number of DPP packets that can be sent by the currently completed CHAIN + [7:0] + read-write + + + + + UEP2_TX_CHAIN_NUMP + Number of NUMPs has been sent by endpoint 2 + 0xE9 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that have been transmitted + [7:0] + read-write + + + + + UEP2_TX_DMA_OFS + DMA offset length for endpoint 2 + 0xEA + 0x10 + 0x0000 + + + CHAIN_TX_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-write + + + + + UEP2_TX_DMA + DMA start address for endpoint 2 + 0xEC + 0x20 + 0x00000000 + + + CHAIN_TX_DMA + Normal mode:The DMA start address of the CHAIN to send data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP3_TX_CFG + Endpoint 3 Configuration Register + 0x100 + 0x8 + 0x86 + + + RB_EP_TX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_TX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_TX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_TX_EOB_MODE + If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP + [3:3] + read-write + + + RB_EP_TX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_TX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_TX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP3_TX_CR + Endpoint 3 control register + 0x101 + 0x8 + 0x10 + + + RB_EP_TX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_TX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_TX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_TX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP3_TX_SEQ + Endpoint 3 Serial Number Register + 0x102 + 0x8 + 0x00 + + + RB_TX_EP_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP3_TX_ST + Endpoint 3 status register + 0x103 + 0x8 + 0x00 + + + RB_TX_EP_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_TX_EP_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_TX_EP_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_TX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_TX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP3_TX_CHAIN_CR + Endpoint 3 CHAIN control register + 0x104 + 0x8 + 0x00 + + + RB_TX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_TX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_TX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_TX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP3_TX_CHAIN_ST + Endpoint 3 CHAIN state register + 0x105 + 0x8 + 0x00 + + + RB_TX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_TX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_TX_EOB_LPF + EOB/LPF bits in the last packet of DPH in the current CHAIN + [5:5] + read-write + + + RB_TX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_TX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_TX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP3_TX_CHAIN_LEN + Endpoint 3 CHAIN sends the last packet length + 0x106 + 0x10 + 0x00 + + + CHAIN_TX_LEN + The length of the last packet sent by the CHAIN + [10:0] + read-only + + + + + UEP3_TX_CHAIN_EXP_NUMP + Number of NUMPs expected to be sent by endpoint 3 + 0x108 + 0x10 + 0x00 + + + TX_CHAIN_EXP_NUMP + The number of DPP packets that can be sent by the currently completed CHAIN + [7:0] + read-write + + + + + UEP3_TX_CHAIN_NUMP + Number of NUMPs has been sent by endpoint 3 + 0x109 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that have been transmitted + [7:0] + read-write + + + + + UEP3_TX_DMA_OFS + DMA offset length for endpoint 3 + 0x10A + 0x10 + 0x0000 + + + CHAIN_TX_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-write + + + + + UEP3_TX_DMA + DMA start address for endpoint 3 + 0x10C + 0x20 + 0x00000000 + + + CHAIN_TX_DMA + Normal mode:The DMA start address of the CHAIN to send data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP4_TX_CFG + Endpoint 4 Configuration Register + 0x120 + 0x8 + 0x86 + + + RB_EP_TX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_TX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_TX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_TX_EOB_MODE + If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP + [3:3] + read-write + + + RB_EP_TX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_TX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_TX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP4_TX_CR + Endpoint 4 control register + 0x121 + 0x8 + 0x10 + + + RB_EP_TX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_TX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_TX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_TX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP4_TX_SEQ + Endpoint 4 Serial Number Register + 0x122 + 0x8 + 0x00 + + + RB_TX_EP_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP4_TX_ST + Endpoint 4 status register + 0x123 + 0x8 + 0x00 + + + RB_TX_EP_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_TX_EP_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_TX_EP_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_TX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_TX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP4_TX_CHAIN_CR + Endpoint 4 CHAIN control register + 0x124 + 0x8 + 0x00 + + + RB_TX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_TX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_TX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_TX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP4_TX_CHAIN_ST + Endpoint 4 CHAIN state register + 0x125 + 0x8 + 0x00 + + + RB_TX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_TX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_TX_EOB_LPF + EOB/LPF bits in the last packet of DPH in the current CHAIN + [5:5] + read-write + + + RB_TX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_TX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_TX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP4_TX_CHAIN_LEN + Endpoint 4 CHAIN sends the last packet length + 0x126 + 0x10 + 0x00 + + + CHAIN_TX_LEN + The length of the last packet sent by the CHAIN + [10:0] + read-only + + + + + UEP4_TX_CHAIN_EXP_NUMP + Number of NUMPs expected to be sent by Endpoint 4 + 0x128 + 0x10 + 0x00 + + + TX_CHAIN_EXP_NUMP + The number of DPP packets that can be sent by the currently completed CHAIN + [7:0] + read-write + + + + + UEP4_TX_CHAIN_NUMP + Number of NUMPs has been sent by Endpoint 4 + 0x129 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that have been transmitted + [7:0] + read-write + + + + + UEP4_TX_DMA_OFS + DMA offset length for Endpoint 4 + 0x12A + 0x10 + 0x0000 + + + CHAIN_TX_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-write + + + + + UEP4_TX_DMA + DMA start address for Endpoint 4 + 0x12C + 0x20 + 0x00000000 + + + CHAIN_TX_DMA + Normal mode:The DMA start address of the CHAIN to send data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP5_TX_CFG + Endpoint 5 Configuration Register + 0x140 + 0x8 + 0x86 + + + RB_EP_TX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_TX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_TX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_TX_EOB_MODE + If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP + [3:3] + read-write + + + RB_EP_TX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_TX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_TX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP5_TX_CR + Endpoint 5 control register + 0x141 + 0x8 + 0x10 + + + RB_EP_TX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_TX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_TX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_TX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP5_TX_SEQ + Endpoint 5 Serial Number Register + 0x142 + 0x8 + 0x00 + + + RB_TX_EP_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP5_TX_ST + Endpoint 5 status register + 0x143 + 0x8 + 0x00 + + + RB_TX_EP_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_TX_EP_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_TX_EP_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_TX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_TX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP5_TX_CHAIN_CR + Endpoint 5 CHAIN control register + 0x144 + 0x8 + 0x00 + + + RB_TX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_TX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_TX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_TX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP5_TX_CHAIN_ST + Endpoint 5 CHAIN state register + 0x145 + 0x8 + 0x00 + + + RB_TX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_TX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_TX_EOB_LPF + EOB/LPF bits in the last packet of DPH in the current CHAIN + [5:5] + read-write + + + RB_TX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_TX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_TX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP5_TX_CHAIN_LEN + Endpoint 5 CHAIN sends the last packet length + 0x146 + 0x10 + 0x00 + + + CHAIN_TX_LEN + The length of the last packet sent by the CHAIN + [10:0] + read-only + + + + + UEP5_TX_CHAIN_EXP_NUMP + Number of NUMPs expected to be sent by Endpoint 5 + 0x148 + 0x10 + 0x00 + + + TX_CHAIN_EXP_NUMP + The number of DPP packets that can be sent by the currently completed CHAIN + [7:0] + read-write + + + + + UEP5_TX_CHAIN_NUMP + Number of NUMPs has been sent by Endpoint 5 + 0x149 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that have been transmitted + [7:0] + read-write + + + + + UEP5_TX_DMA_OFS + DMA offset length for Endpoint 5 + 0x14A + 0x10 + 0x0000 + + + CHAIN_TX_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-write + + + + + UEP5_TX_DMA + DMA start address for Endpoint 5 + 0x14C + 0x20 + 0x00000000 + + + CHAIN_TX_DMA + Normal mode:The DMA start address of the CHAIN to send data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP6_TX_CFG + Endpoint 6 Configuration Register + 0x160 + 0x8 + 0x86 + + + RB_EP_TX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_TX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_TX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_TX_EOB_MODE + If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP + [3:3] + read-write + + + RB_EP_TX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_TX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_TX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP6_TX_CR + Endpoint 6 control register + 0x161 + 0x8 + 0x10 + + + RB_EP_TX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_TX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_TX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_TX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP6_TX_SEQ + Endpoint 6 Serial Number Register + 0x162 + 0x8 + 0x00 + + + RB_TX_EP_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP6_TX_ST + Endpoint 6 status register + 0x163 + 0x8 + 0x00 + + + RB_TX_EP_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_TX_EP_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_TX_EP_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_TX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_TX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP6_TX_CHAIN_CR + Endpoint 6 CHAIN control register + 0x164 + 0x8 + 0x00 + + + RB_TX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_TX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_TX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_TX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP6_TX_CHAIN_ST + Endpoint 6 CHAIN state register + 0x165 + 0x8 + 0x00 + + + RB_TX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_TX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_TX_EOB_LPF + EOB/LPF bits in the last packet of DPH in the current CHAIN + [5:5] + read-write + + + RB_TX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_TX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_TX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP6_TX_CHAIN_LEN + Endpoint 6 CHAIN sends the last packet length + 0x166 + 0x10 + 0x00 + + + CHAIN_TX_LEN + The length of the last packet sent by the CHAIN + [10:0] + read-only + + + + + UEP6_TX_CHAIN_EXP_NUMP + Number of NUMPs expected to be sent by Endpoint 6 + 0x168 + 0x10 + 0x00 + + + TX_CHAIN_EXP_NUMP + The number of DPP packets that can be sent by the currently completed CHAIN + [7:0] + read-write + + + + + UEP6_TX_CHAIN_NUMP + Number of NUMPs has been sent by Endpoint 6 + 0x169 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that have been transmitted + [7:0] + read-write + + + + + UEP6_TX_DMA_OFS + DMA offset length for Endpoint 6 + 0x16A + 0x10 + 0x0000 + + + CHAIN_TX_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-write + + + + + UEP6_TX_DMA + DMA start address for Endpoint 6 + 0x16C + 0x20 + 0x00000000 + + + CHAIN_TX_DMA + Normal mode:The DMA start address of the CHAIN to send data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP7_TX_CFG + Endpoint 7 Configuration Register + 0x180 + 0x8 + 0x86 + + + RB_EP_TX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_TX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_TX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_TX_EOB_MODE + If a short packet is sent, EOB/LPF=0 in ACK-TP;If a short packet is sent, EOB/LPF=1 in ACK-TP + [3:3] + read-write + + + RB_EP_TX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_TX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_TX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP7_TX_CR + Endpoint 7 control register + 0x181 + 0x8 + 0x10 + + + RB_EP_TX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_TX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_TX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_TX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP7_TX_SEQ + Endpoint 7 Serial Number Register + 0x182 + 0x8 + 0x00 + + + RB_TX_EP_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP7_TX_ST + Endpoint 7 status register + 0x183 + 0x8 + 0x00 + + + RB_TX_EP_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_TX_EP_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_TX_EP_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_TX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_TX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP7_TX_CHAIN_CR + Endpoint 7 CHAIN control register + 0x184 + 0x8 + 0x00 + + + RB_TX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_TX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_TX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_TX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP7_TX_CHAIN_ST + Endpoint 7 CHAIN state register + 0x185 + 0x8 + 0x00 + + + RB_TX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_TX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_TX_EOB_LPF + EOB/LPF bits in the last packet of DPH in the current CHAIN + [5:5] + read-write + + + RB_TX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_TX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_TX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP7_TX_CHAIN_LEN + Endpoint 7 CHAIN sends the last packet length + 0x186 + 0x10 + 0x00 + + + CHAIN_TX_LEN + The length of the last packet sent by the CHAIN + [10:0] + read-only + + + + + UEP7_TX_CHAIN_EXP_NUMP + Number of NUMPs expected to be sent by Endpoint 7 + 0x188 + 0x10 + 0x00 + + + TX_CHAIN_EXP_NUMP + The number of DPP packets that can be sent by the currently completed CHAIN + [7:0] + read-write + + + + + UEP7_TX_CHAIN_NUMP + Number of NUMPs has been sent by Endpoint 7 + 0x189 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that have been transmitted + [7:0] + read-write + + + + + UEP7_TX_DMA_OFS + DMA offset length for Endpoint 7 + 0x18A + 0x10 + 0x0000 + + + CHAIN_TX_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-write + + + + + UEP7_TX_DMA + DMA start address for Endpoint 7 + 0x18C + 0x20 + 0x00000000 + + + CHAIN_TX_DMA + Normal mode:The DMA start address of the CHAIN to send data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + + + + + + + UEP1_RX_CFG + Endpoint 1 Configuration Register + 0xD0 + 0x8 + 0x86 + + + RB_EP_RX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_RX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_RX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_RX_TOUT_MODE + This bit is 1, and when a continuous burst packet is received, + PP=1 and not a short packet is not received, and DPH is not received after the timeout, resulting in TOUT_IF interrupt + [4:4] + read-write + + + RB_EP_RX_EOB_MODE + This bit is 1, and when a short packet or DP(PP=0) is received, + clearing all CHAIN_EN will result in an NRDY response to the subsequent DPH; + Software reconfiguration required. + [3:3] + read-write + + + RB_EP_RX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_RX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_RX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP1_RX_CR + Endpoint 1 control register + 0xD1 + 0x8 + 0x10 + + + RB_EP_RX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_RX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_RX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_RX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP1_RX_SEQ + Endpoint 1 Serial Number Register + 0xD2 + 0x8 + 0x00 + + + RB_EP_RX_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP1_RX_ST + Endpoint 1 status register + 0xD3 + 0x8 + 0x00 + + + RB_EP_RX_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_EP_RX_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_EP_RX_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_EP_RX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_ER_RX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP1_RX_CHAIN_CR + Endpoint 1 CHAIN control register + 0xD4 + 0x8 + 0x00 + + + RB_EP_RX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_EP_RX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_EP_RX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_EP_RX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP1_RX_CHAIN_ST + Endpoint 1 CHAIN state register + 0xD5 + 0x8 + 0x00 + + + RB_EP_RX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_EP_RX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_EP_RX_LPF_FLAG + Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH. + [5:5] + read-write + + + RB_EP_RX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_EP_RX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_EP_RX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP1_RX_CHAIN_LEN + Endpoint 1 CHAIN sends the last packet length + 0xD6 + 0x10 + 0x00 + + + RB_EP_RX_CHAIN_RX_LEN + The length of the currently completed CHAIN to the last packet. + [10:0] + read-only + + + + + UEP1_RX_CHAIN_MAX_NUMP + Number of NUMPs that Endpoint 1 can receive + 0xD8 + 0x8 + 0x00 + + + RX_CHAIN_MAX_NUMP + The number of DPP packets that can be received by the CHAIN + [7:0] + read-only + + + + + UEP1_RX_CHAIN_NUMP + Number of NUMPs has been received by endpoint 1 + 0xD9 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that has received + [7:0] + read-only + + + + + UEP1_RX_DMA_OFS + DMA offset length for endpoint 1 + 0xDA + 0x10 + 0x0000 + + + CHAIN_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-only + + + + + UEP1_RX_DMA + DMA start address for endpoint 1 + 0xDC + 0x20 + 0x00000000 + + + CHAIN_RX_DMA + Normal mode:The DMA start address of the CHAIN to receive data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP2_RX_CFG + Endpoint 2 Configuration Register + 0xF0 + 0x8 + 0x86 + + + RB_EP_RX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_RX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_RX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_RX_TOUT_MODE + This bit is 1, and when a continuous burst packet is received, + PP=1 and not a short packet is not received, and DPH is not received after the timeout, resulting in TOUT_IF interrupt + [4:4] + read-write + + + RB_EP_RX_EOB_MODE + This bit is 1, and when a short packet or DP(PP=0) is received, + clearing all CHAIN_EN will result in an NRDY response to the subsequent DPH; + Software reconfiguration required. + [3:3] + read-write + + + RB_EP_RX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_RX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_RX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP2_RX_CR + Endpoint 2 control register + 0xF1 + 0x8 + 0x10 + + + RB_EP_RX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_RX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_RX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_RX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP2_RX_SEQ + Endpoint 2 Serial Number Register + 0xF2 + 0x8 + 0x00 + + + RB_EP_RX_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP2_RX_ST + Endpoint 2 status register + 0xF3 + 0x8 + 0x00 + + + RB_EP_RX_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_EP_RX_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_EP_RX_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_EP_RX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_ER_RX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP2_RX_CHAIN_CR + Endpoint 2 CHAIN control register + 0xF4 + 0x8 + 0x00 + + + RB_EP_RX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_EP_RX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_EP_RX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_EP_RX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP2_RX_CHAIN_ST + Endpoint 2 CHAIN state register + 0xF5 + 0x8 + 0x00 + + + RB_EP_RX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_EP_RX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_EP_RX_LPF_FLAG + Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH. + [5:5] + read-write + + + RB_EP_RX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_EP_RX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_EP_RX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP2_RX_CHAIN_LEN + Endpoint 2 CHAIN sends the last packet length + 0xF6 + 0x10 + 0x00 + + + RB_EP_RX_CHAIN_RX_LEN + The length of the currently completed CHAIN to the last packet. + [10:0] + read-only + + + + + UEP2_RX_CHAIN_MAX_NUMP + Number of NUMPs that Endpoint 2 can receive + 0xF8 + 0x8 + 0x00 + + + RX_CHAIN_MAX_NUMP + The number of DPP packets that can be received by the CHAIN + [7:0] + read-only + + + + + UEP2_RX_CHAIN_NUMP + Number of NUMPs has been received by endpoint 2 + 0xF9 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that has received + [7:0] + read-only + + + + + UEP2_RX_DMA_OFS + DMA offset length for Endpoint 2 + 0xFA + 0x10 + 0x0000 + + + CHAIN_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-only + + + + + UEP2_RX_DMA + DMA start address for Endpoint 2 + 0xFC + 0x20 + 0x00000000 + + + CHAIN_RX_DMA + Normal mode:The DMA start address of the CHAIN to receive data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP3_RX_CFG + Endpoint 3 Configuration Register + 0x110 + 0x8 + 0x86 + + + RB_EP_RX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_RX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_RX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_RX_TOUT_MODE + This bit is 1, and when a continuous burst packet is received, + PP=1 and not a short packet is not received, and DPH is not received after the timeout, resulting in TOUT_IF interrupt + [4:4] + read-write + + + RB_EP_RX_EOB_MODE + This bit is 1, and when a short packet or DP(PP=0) is received, + clearing all CHAIN_EN will result in an NRDY response to the subsequent DPH; + Software reconfiguration required. + [3:3] + read-write + + + RB_EP_RX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_RX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_RX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP3_RX_CR + Endpoint 3 control register + 0x111 + 0x8 + 0x10 + + + RB_EP_RX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_RX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_RX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_RX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP3_RX_SEQ + Endpoint 3 Serial Number Register + 0x112 + 0x8 + 0x00 + + + RB_EP_RX_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP3_RX_ST + Endpoint 3 status register + 0x113 + 0x8 + 0x00 + + + RB_EP_RX_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_EP_RX_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_EP_RX_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_EP_RX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_ER_RX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP3_RX_CHAIN_CR + Endpoint 3 CHAIN control register + 0x114 + 0x8 + 0x00 + + + RB_EP_RX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_EP_RX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_EP_RX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_EP_RX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP3_RX_CHAIN_ST + Endpoint 3 CHAIN state register + 0x115 + 0x8 + 0x00 + + + RB_EP_RX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_EP_RX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_EP_RX_LPF_FLAG + Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH. + [5:5] + read-write + + + RB_EP_RX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_EP_RX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_EP_RX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP3_RX_CHAIN_LEN + Endpoint 3 CHAIN sends the last packet length + 0x116 + 0x10 + 0x00 + + + RB_EP_RX_CHAIN_RX_LEN + The length of the currently completed CHAIN to the last packet. + [10:0] + read-only + + + + + UEP3_RX_CHAIN_MAX_NUMP + Number of NUMPs that Endpoint 3 can receive + 0x118 + 0x8 + 0x00 + + + RX_CHAIN_MAX_NUMP + The number of DPP packets that can be received by the CHAIN + [7:0] + read-only + + + + + UEP3_RX_CHAIN_NUMP + Number of NUMPs has been received by Endpoint 3 + 0x119 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that has received + [7:0] + read-only + + + + + UEP3_RX_DMA_OFS + DMA offset length for Endpoint 3 + 0x11A + 0x10 + 0x0000 + + + CHAIN_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-only + + + + + UEP3_RX_DMA + DMA start address for Endpoint 3 + 0x11C + 0x20 + 0x00000000 + + + CHAIN_RX_DMA + Normal mode:The DMA start address of the CHAIN to receive data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP4_RX_CFG + Endpoint 4 Configuration Register + 0x130 + 0x8 + 0x86 + + + RB_EP_RX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_RX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_RX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_RX_TOUT_MODE + This bit is 1, and when a continuous burst packet is received, + PP=1 and not a short packet is not received, and DPH is not received after the timeout, resulting in TOUT_IF interrupt + [4:4] + read-write + + + RB_EP_RX_EOB_MODE + This bit is 1, and when a short packet or DP(PP=0) is received, + clearing all CHAIN_EN will result in an NRDY response to the subsequent DPH; + Software reconfiguration required. + [3:3] + read-write + + + RB_EP_RX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_RX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_RX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP4_RX_CR + Endpoint 4 control register + 0x131 + 0x8 + 0x10 + + + RB_EP_RX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_RX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_RX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_RX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP4_RX_SEQ + Endpoint 4 Serial Number Register + 0x132 + 0x8 + 0x00 + + + RB_EP_RX_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP4_RX_ST + Endpoint 4 status register + 0x133 + 0x8 + 0x00 + + + RB_EP_RX_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_EP_RX_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_EP_RX_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_EP_RX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_ER_RX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP4_RX_CHAIN_CR + Endpoint 4 CHAIN control register + 0x134 + 0x8 + 0x00 + + + RB_EP_RX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_EP_RX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_EP_RX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_EP_RX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP4_RX_CHAIN_ST + Endpoint 4 CHAIN state register + 0x135 + 0x8 + 0x00 + + + RB_EP_RX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_EP_RX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_EP_RX_LPF_FLAG + Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH. + [5:5] + read-write + + + RB_EP_RX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_EP_RX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_EP_RX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP4_RX_CHAIN_LEN + Endpoint 4 CHAIN sends the last packet length + 0x136 + 0x10 + 0x00 + + + RB_EP_RX_CHAIN_RX_LEN + The length of the currently completed CHAIN to the last packet. + [10:0] + read-only + + + + + UEP4_RX_CHAIN_MAX_NUMP + Number of NUMPs that Endpoint 4 can receive + 0x138 + 0x8 + 0x00 + + + RX_CHAIN_MAX_NUMP + The number of DPP packets that can be received by the CHAIN + [7:0] + read-only + + + + + UEP4_RX_CHAIN_NUMP + Number of NUMPs has been received by Endpoint 4 + 0x139 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that has received + [7:0] + read-only + + + + + UEP4_RX_DMA_OFS + DMA offset length for Endpoint 4 + 0x13A + 0x10 + 0x0000 + + + CHAIN_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-only + + + + + UEP4_RX_DMA + DMA start address for Endpoint 4 + 0x13C + 0x20 + 0x00000000 + + + CHAIN_RX_DMA + Normal mode:The DMA start address of the CHAIN to receive data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP5_RX_CFG + Endpoint 5 Configuration Register + 0x150 + 0x8 + 0x86 + + + RB_EP_RX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_RX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_RX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_RX_TOUT_MODE + This bit is 1, and when a continuous burst packet is received, + PP=1 and not a short packet is not received, and DPH is not received after the timeout, resulting in TOUT_IF interrupt + [4:4] + read-write + + + RB_EP_RX_EOB_MODE + This bit is 1, and when a short packet or DP(PP=0) is received, + clearing all CHAIN_EN will result in an NRDY response to the subsequent DPH; + Software reconfiguration required. + [3:3] + read-write + + + RB_EP_RX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_RX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_RX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP5_RX_CR + Endpoint 5 control register + 0x151 + 0x8 + 0x10 + + + RB_EP_RX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_RX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_RX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_RX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP5_RX_SEQ + Endpoint 5 Serial Number Register + 0x152 + 0x8 + 0x00 + + + RB_EP_RX_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP5_RX_ST + Endpoint 5 status register + 0x153 + 0x8 + 0x00 + + + RB_EP_RX_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_EP_RX_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_EP_RX_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_EP_RX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_ER_RX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP5_RX_CHAIN_CR + Endpoint 5 CHAIN control register + 0x154 + 0x8 + 0x00 + + + RB_EP_RX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_EP_RX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_EP_RX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_EP_RX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP5_RX_CHAIN_ST + Endpoint 5 CHAIN state register + 0x155 + 0x8 + 0x00 + + + RB_EP_RX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_EP_RX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_EP_RX_LPF_FLAG + Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH. + [5:5] + read-write + + + RB_EP_RX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_EP_RX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_EP_RX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP5_RX_CHAIN_LEN + Endpoint 5 CHAIN sends the last packet length + 0x156 + 0x10 + 0x00 + + + RB_EP_RX_CHAIN_RX_LEN + The length of the currently completed CHAIN to the last packet. + [10:0] + read-only + + + + + UEP5_RX_CHAIN_MAX_NUMP + Number of NUMPs that Endpoint 5 can receive + 0x158 + 0x8 + 0x00 + + + RX_CHAIN_MAX_NUMP + The number of DPP packets that can be received by the CHAIN + [7:0] + read-only + + + + + UEP5_RX_CHAIN_NUMP + Number of NUMPs has been received by Endpoint 5 + 0x159 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that has received + [7:0] + read-only + + + + + UEP5_RX_DMA_OFS + DMA offset length for Endpoint 5 + 0x15A + 0x10 + 0x0000 + + + CHAIN_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-only + + + + + UEP5_RX_DMA + DMA start address for Endpoint 5 + 0x15C + 0x20 + 0x00000000 + + + CHAIN_RX_DMA + Normal mode:The DMA start address of the CHAIN to receive data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP6_RX_CFG + Endpoint 6 Configuration Register + 0x170 + 0x8 + 0x86 + + + RB_EP_RX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_RX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_RX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_RX_TOUT_MODE + This bit is 1, and when a continuous burst packet is received, + PP=1 and not a short packet is not received, and DPH is not received after the timeout, resulting in TOUT_IF interrupt + [4:4] + read-write + + + RB_EP_RX_EOB_MODE + This bit is 1, and when a short packet or DP(PP=0) is received, + clearing all CHAIN_EN will result in an NRDY response to the subsequent DPH; + Software reconfiguration required. + [3:3] + read-write + + + RB_EP_RX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_RX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_RX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP6_RX_CR + Endpoint 6 control register + 0x171 + 0x8 + 0x10 + + + RB_EP_RX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_RX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_RX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_RX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP6_RX_SEQ + Endpoint 6 Serial Number Register + 0x172 + 0x8 + 0x00 + + + RB_EP_RX_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP6_RX_ST + Endpoint 6 status register + 0x173 + 0x8 + 0x00 + + + RB_EP_RX_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_EP_RX_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_EP_RX_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_EP_RX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_ER_RX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP6_RX_CHAIN_CR + Endpoint 6 CHAIN control register + 0x174 + 0x8 + 0x00 + + + RB_EP_RX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_EP_RX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_EP_RX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_EP_RX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP6_RX_CHAIN_ST + Endpoint 6 CHAIN state register + 0x175 + 0x8 + 0x00 + + + RB_EP_RX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_EP_RX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_EP_RX_LPF_FLAG + Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH. + [5:5] + read-write + + + RB_EP_RX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_EP_RX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_EP_RX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP6_RX_CHAIN_LEN + Endpoint 6 CHAIN sends the last packet length + 0x176 + 0x10 + 0x00 + + + RB_EP_RX_CHAIN_RX_LEN + The length of the currently completed CHAIN to the last packet. + [10:0] + read-only + + + + + UEP6_RX_CHAIN_MAX_NUMP + Number of NUMPs that Endpoint 6 can receive + 0x178 + 0x8 + 0x00 + + + RX_CHAIN_MAX_NUMP + The number of DPP packets that can be received by the CHAIN + [7:0] + read-only + + + + + UEP6_RX_CHAIN_NUMP + Number of NUMPs has been received by Endpoint 6 + 0x179 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that has received + [7:0] + read-only + + + + + UEP6_RX_DMA_OFS + DMA offset length for Endpoint 6 + 0x17A + 0x10 + 0x0000 + + + CHAIN_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-only + + + + + UEP6_RX_DMA + DMA start address for Endpoint 6 + 0x17C + 0x20 + 0x00000000 + + + CHAIN_RX_DMA + Normal mode:The DMA start address of the CHAIN to receive data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + UEP7_RX_CFG + Endpoint 7 Configuration Register + 0x190 + 0x8 + 0x86 + + + RB_EP_RX_CHAIN_AUTO + CHAIN automatically switches modes, and this mode is recommended + [7:7] + read-write + + + RB_EP_RX_FIFO_MODE + If the bit is 1, the current endpoint uses FIFO mode, + and the start and end addresses of the FIFO should be configured before the bit is 1. + [6:6] + read-write + + + RB_EP_RX_FIFO_CFG + Access offset address 0xC~0xF, and the operation object + [5:5] + read-write + + + RB_EP_RX_TOUT_MODE + This bit is 1, and when a continuous burst packet is received, + PP=1 and not a short packet is not received, and DPH is not received after the timeout, resulting in TOUT_IF interrupt + [4:4] + read-write + + + RB_EP_RX_EOB_MODE + This bit is 1, and when a short packet or DP(PP=0) is received, + clearing all CHAIN_EN will result in an NRDY response to the subsequent DPH; + Software reconfiguration required. + [3:3] + read-write + + + RB_EP_RX_ERDY_AUTO + ERDY automatic mode, the hardware will send ERDY, + no software control required; It is recommended that the synchronization endpoint zero out this bit. + [2:2] + read-write + + + RB_EP_RX_SEQ_AUTO + 1: It is forbidden to write R16_EPn_ST->EP_SEQ_NUM software; + 0: allows the software to write R16_EPn_ST->EP_SEQ_NUM. + [1:1] + read-write + + + RB_EP_RX_ISO_MODE + A value of 1 indicates that the current endpoint is a synchronous endpoint + [0:0] + read-write + + + + + UEP7_RX_CR + Endpoint 7 control register + 0x191 + 0x8 + 0x10 + + + RB_EP_RX_HALT + Endpoint Stop, High Validity, Endpoint Stop Answering STALL to DPH. + [7:7] + read-write + + + RB_EP_RX_CLR + Write 1 clears all configuration values and status of the endpoint, except for UEP_CFG. + [6:6] + read-write + + + RB_EP_RX_CHAIN_CLR + Write 1 clears all CHAIN configuration values and statuses + [5:5] + read-write + + + RB_EP_RX_ERDY_NUMP + The nump field of ERDY-TP is sent by the hardware, + and the value is generally set to the number of supported bursts. + For example, if you support 16 bursts, the value of this field is 16. + [4:0] + read-write + + + + + UEP7_RX_SEQ + Endpoint 7 Serial Number Register + 0x192 + 0x8 + 0x00 + + + RB_EP_RX_SEQ_NUM + The current serial number of the endpoint, + writable in non-SEQ_AUTO mode, + read-only in SEQ_AUTO mode + [4:0] + read-write + + + + + UEP7_RX_ST + Endpoint 7 status register + 0x193 + 0x8 + 0x00 + + + RB_EP_RX_INT_FLAG + The current break flag for the endpoint, the bit is read-only, + and all CHAIN_IF are 0 if the bit is 0, otherwise it is 1. + [7:7] + read-only + + + RB_EP_RX_FC_ST + The endpoint is in the current throttling state, and write 1 is cleared to zero. + [6:6] + read-write + + + RB_EP_RX_ERDY_REQ + Indicates that the ERDY is currently being sent; + Writing 1 to that bit will send ERDY, which is used in non-ERDY_AUTO mode. + [5:5] + read-write + + + RB_EP_RX_CHAIN_RES + CHAIN response state, corresponding to 4 separate CHAINS + [4:4] + read-only + + + RB_ER_RX_CHAIN_EN + The CHAIN enabled state, which corresponds to 4 independent CHAINS. + [3:0] + read-only + + + + + UEP7_RX_CHAIN_CR + Endpoint 7 CHAIN control register + 0x194 + 0x8 + 0x00 + + + RB_EP_RX_CUR_USE + The CHAIN serial number currently in use + [7:6] + read-only + + + RB_EP_RX_CUR_CFG + The chain serial number of the current configuration. + [5:4] + read-only + + + RB_EP_RX_FORCE_RET + This bit effectively forces the return of the selected CHAIN state machine configuration + [2:2] + read-write + + + RB_EP_RX_RET_SEL + When the FORCE_RET is valid, this bit indicates the returned CHAIN status and configuration + [1:0] + read-write + + + + + UEP7_RX_CHAIN_ST + Endpoint 7 CHAIN state register + 0x195 + 0x8 + 0x00 + + + RB_EP_RX_CHAIN_EN + The currently used CHAIN enables the automatic hardware setting of 1 after the UEP_CHAIN_NUMP register is configured, + and the CHAIN is automatically cleared to zero after the transmission is completed + [7:7] + read-only + + + RB_EP_RX_CHAIN_IF + This bit is only written, and 1 is written to release the current CHAIN_IF + [6:6] + read-write + + + RB_EP_RX_LPF_FLAG + Only the synchronous downhaul endpoint is used to currently receive the LPF status in the DPH. + [5:5] + read-write + + + RB_EP_RX_NUMP_EMPTY + IF THE NUMP IN THE CHAIN IS 0, THE POSITION IS 1 + [3:3] + read-only + + + RB_EP_RX_DPH_PP + The status of the PP bits in the currently received DPH + [2:2] + read-write + + + RB_EP_RX_CHAIN_NO + The serial number of the CHAIN that is currently interrupting + [1:0] + read-write + + + + + UEP7_RX_CHAIN_LEN + Endpoint 7 CHAIN sends the last packet length + 0x196 + 0x10 + 0x00 + + + RB_EP_RX_CHAIN_RX_LEN + The length of the currently completed CHAIN to the last packet. + [10:0] + read-only + + + + + UEP7_RX_CHAIN_MAX_NUMP + Number of NUMPs that Endpoint 7 can receive + 0x198 + 0x8 + 0x00 + + + RX_CHAIN_MAX_NUMP + The number of DPP packets that can be received by the CHAIN + [7:0] + read-only + + + + + UEP7_RX_CHAIN_NUMP + Number of NUMPs has been received by Endpoint 7 + 0x199 + 0x8 + 0x00 + + + TX_CHAIN_NUMP + The number of DPP packets that has received + [7:0] + read-only + + + + + UEP7_RX_DMA_OFS + DMA offset length for Endpoint 7 + 0x19A + 0x10 + 0x0000 + + + CHAIN_DMA_OFS + The offset address of the DPP in that CHAIN + [15:0] + read-only + + + + + UEP7_RX_DMA + DMA start address for Endpoint 7 + 0x19C + 0x20 + 0x00000000 + + + CHAIN_RX_DMA + Normal mode:The DMA start address of the CHAIN to receive data. + FIFO mode:16~23 bits of the FIFO start address in SRAM;The FIFO end address is 16~23 bits of the mapped address in SRAM. + [31:0] + read-write + + + + + + UH_TX_CTRL + Host Transmit Control Registers + UEP0_TX_CTRL + 0x84 + 0x20 + 0x00000000 + + + RB_UH_TX_ACT + The IN transaction completes the interrupt flag, the software writes 0 to zero, and the hardware sets 1. + [31:31] + read-write + + + RB_UH_TX_ISO + The host prepares to send ISO packets. + [30:30] + read-write + + + RB_UH_TX_SETUP + Indicates that the packet sent by the host is a Setup packet, and the setup flag is set. + [29:29] + read-write + + + RB_UH_TX_STATUS + Indicates that the packet sent by the host is STATUS TP. + [28:28] + read-write + + + RB_UH_TX_LPF + For burst transmissions, this bit simply represents the LPF/EOB of the last packet, + and the LPF/EOB of the preceding packet uses a fixed value of 0. + [23:23] + read-write + + + RB_UH_TX_RES + Response to DPH+DPP + [22:21] + read-write + + + RB_UH_TX_SEQ + The SEQ _NUM for which the endpoint receives the packet, the hardware automatically adds 1, except for endpoint 0 + [20:16] + read-write + + + RB_UH_TX_EP + Indicates the destination of the packet sent in host mode (the target endpoint number of the device) + [15:12] + read-write + + + RB_UH_TX_LEN + The endpoint receives the length register, + which for burst transmissions indicates the packet length of the last packet of the burst transmission, + and the other packets must be 1024B as specified in the protocol. + [10:0] + read-write + + + + + UH_RX_CTRL + Host receives control registers + UEP0_RX_CTRL + 0x88 + 0x20 + 0x00000000 + + + RB_UH_RX_ACT + The OUT transaction completes the interrupt flag, the software writes 0 to zero, and the hardware sets 1 + [31:31] + read-write + + + RB_UH_RX_ISO + Received Packets (DPP) are transmitted synchronously + [30:30] + read-only + + + RB_UH_RX_NUMP + The number of packets (DPP) that the endpoint is capable of receiving (burst transmission) + [28:24] + read-write + + + RB_UH_RX_RES + Response to DPH+DPP or STATUS-TP + [22:21] + read-only + + + RB_UH_RX_SEQ + The SEQ _NUM that the endpoint expects to receive, the hardware automatically adds 1, except for endpoint 0 + [20:16] + read-write + + + RB_UH_RX_EP + Indicates the source (device endpoint number) from which the packet was received in host mode + [15:12] + read-write + + + RB_UH_RX_LEN + The endpoint receives the length register, + which for burst transmissions indicates the packet length of the last packet of the burst transmission, + and the other packets must be 1024B as specified in the protocol + [10:0] + read-only + + + + + UH_TX_DMA_OFS + Host Transmit Address Offset Register + 0x94 + 0x20 + 0x00000400 + + + RB_UH_TX_DMA_OFS + After the host sends the DMA, the size of the DMA address offset + [31:0] + read-write + + + + + UH_RX_DMA_OFS + Host Receive Address Offset Register + 0x98 + 0x20 + 0x00000400 + + + RB_UH_RX_DMA_OFS + After the host receives it, the DMA's address is offset by a large amount. + [31:0] + read-write + + + + + HOST_RX_NUMP + The host receives the NUMP register + 0x9E + 0x10 + 0x00000000 + + + RB_UH_RX_DPP_NUM + The number of DPPs that have been accepted by the host. + [15:8] + read-write + + + RB_UH_RX_NUMP + The number of packets that the host expects to receive, + if it is a synchronous transmission, will automatically subtract 1 from the hardware for each packet it receives. + [7:0] + read-write + + + + + HOST_STATUS + Host Status Registers + 0xA0 + 0x20 + 0x00000100 + + + RB_UH_ITP_PRESAGE + In host mode, this bit indicates the time when the ITP packet was sent + [19:18] + read-only + + + RB_UH_RX_ISO_PKT_ERR + A CRC error was received for the packet (DPP) during synchronous transmission + [17:17] + read-only + + + RB_UH_RX_EOB_LPF + This bit represents the EOB/LPF status in the received packet + [16:16] + read-only + + + RB_UH_RX_ERDY_DIR + ERDY is received from the device, and the segment represents the direction of the endpoint + [15:15] + read-only + + + RB_UH_RX_ERDY_NUMP + ERDY received from the device, + which indicates the number of packets that can be sent/received by the device's corresponding endpoint + [12:8] + read-only + + + RB_UH_RX_ERDY_EP + ERDY is received from the device, and the segment represents the endpoint number of the device ERDY + [7:4] + read-only + + + + + HOST_TX_FC_STATUS + The host endpoint sends flow control register + 0xA4 + 0x10 + 0x0000 + + + EPx_TX_FC + The flow control status of the host to send endpoints 1-15. + [15:1] + read-write + + + + + HOST_RX_FC_STATUS + The host endpoint receives the flow control register + 0xA6 + 0x10 + 0x0000 + + + EPx_RX_FC + The flow control status of the host to receiving endpoints 1-15 + [15:1] + read-write + + + + + TP_RX_DATA0 + DEV_NOTIF-TP Data 0 Register + 0xA8 + 0x20 + 0x00000000 + + + USB3_NOTIF_DATA0 + After the DEV_NOTIF-TP is received, the HP data is stored in this register + [31:0] + read-only + + + + + TP_RX_DATA1 + DEV_NOTIF-TP Data 1 Register + 0xAC + 0x20 + 0x00000000 + + + USB3_NOTIF_DATA1 + After the DEV_NOTIF-TP is received, the HP data is stored in this register + [31:0] + read-only + + + + + TP_RX_DATA2 + DEV_NOTIF-TP Data 2 Register + 0xB0 + 0x20 + 0x00000000 + + + USB3_NOTIF_DATA2 + After the DEV_NOTIF-TP is received, the HP data is stored in this register + [31:0] + read-only + + + + + + LINK_CFG + LINK Configuration Register + 0x00 + 0x20 + 0xC0000128 + + + RB_LINK_RESET + LINK reset, including the reset state machine and all interrupt flags, is highly effective + [31:31] + read-write + + + RB_LINK_TOUT_MODE + SPEC configure + [21:21] + read-write + + + RB_LINK_U1_PING_EN + Send PING_FPFS under U1 to enable + [20:20] + read-write + + + RB_LINK_U2_ALLOW + High validity, after receiving the LGO_U2, the response LXU allows to enter the U2 state, + otherwise after receiving the LGO_U2, the response LXU refuses to enter the U2 state. + [17:17] + read-write + + + RB_LINK_U1_ALLOW + High validity, after receiving the LGO_U1, the response LAU allows to enter the U1 state, + otherwise, after receiving the LGO_U1, the response LXU refuses to enter the U1 state + [16:16] + read-write + + + RB_LINK_LTSSM_MODE + The link state machine enters DISABLE mode + [15:15] + read-write + + + RB_LINK_LOOKBACK_ACT + It is used in LOOPBACK mode for the LOOPBACK master to control the pattern transmission (the LOOPBACK slave keeps 0), + and the ACT is a high-level signal that lasts for a period of time. + [14:14] + read-write + + + RB_LINK_LOOPBACK_EN + The LOOPBACK enable bit is allowed, which is highly active, and can be used with the LOOKBACK enable in TX/RX_TS_CFG [3], + both of which are valid before LINK can enter the LOOKBACK mode + (used to enable the data loopback and error counting of the LOOPBACK slave, + and the LOOPBACK master remains 0). + [13:13] + read-write + + + RB_LINK_U2_DET_EN + Detection mode of connected devices in U2 state + [12:12] + read-write + + + RB_LINK_CP78_SEL + In Compliance Pattern 7/8, send a length of consecutive 0 or consecutive 1 + [11:10] + read-write + + + RB_LINK_TX_DEEMPH + Transmitter de-emphasis control + [9:8] + read-write + + + RB_LINK_TX_SWING + The transmitter signal swing control, low swing power consumption, but affect the transmission distance + [7:7] + read-write + + + RB_LINK_RX_EQ_EN + Receiver equalization enable control, optional protocol specifications + [6:6] + read-write + + + RB_LINK_LFPS_RX_PD + LFPS receive control, this bit is 1 to disable LFPS reception + [5:5] + read-write + + + RB_LINK_COMPLIANCE_EN + POLLING_LFPS timeout is in COMPLIANCE mode + [4:4] + read-write + + + RB_LINK_PHY_RESET + The PIPE interface is reset + [3:3] + read-write + + + RB_LINK_SS_PLR_SWAP + Exchange SSTX and SSRX polarities as follows + [2:2] + read-write + + + RB_LINK_RX_TERM_EN + Receiver Termination Resistance Control + [1:1] + read-write + + + RB_LINK_DOWN_MODE + Peripheral Type + [0:0] + read-write + + + + + + LINK_CTRL + LINK control registers + 0x04 + 0x20 + 0x00000013 + + + LINK_RX_TS_CFG + Received Link Control + [31:24] + read-only + + + LINK_TX_TS_CFG + Send the link configuration of the TS1/TS2 training sequence + [23:16] + read-write + + + LINK_TX_LGO_U3 + After the bit is valid, the LGO_U3 is transmitted, and the hardware is automatically cleared + [15:15] + read-write + + + LINK_TX_LGO_U2 + After the bit is valid, the LGO_U2 is sent, the high is active, and the hardware is automatically cleared + [14:14] + read-write + + + LINK_TX_LGO_U1 + After the bit is valid, the LGO_U1 is sent, the high is active, and the hardware is automatically cleared + [13:13] + read-write + + + LINK_POLLING_EN + If the TERM is detected by the SS.RX_DETECT, + a POLLING handshake will be performed after the software sets the bit to be valid + [12:12] + read-write + + + LINK_REG_ROUT_EN + Enable the routing function of the HUB, which is highly effective, with registers and no interfaces + [11:11] + read-write + + + LINK_LUP_LDN_EN + In the U0 state, if there is no data, whether to send LUP and LDN packets every 10us + [10:10] + read-write + + + LINK_TX_UX_EXIT + High validity, hardware automatic zeroing + [9:9] + read-write + + + LINK_TX_WARM_RST + High validity, cleared by software. A valid bit will send a warm-reset + [8:8] + read-write + + + LINK_GO_RX_DET + Before setting this bit, the PD_MODE should be set to P2 mode, + and the LINK should be set to enter the SS.RX_DETECT, + and the software will query TERM_PRESENT to know whether there is a connection or whether the connection is disconnected. + High effectiveness, automatic clearing. + [7:7] + read-write + + + LINK_GO_RECOVERY + SET THE LINK TO ENTER SS.RECOVERY, + WHICH IS HIGHLY EFFECTIVE, AND THE HARDWARE IS AUTOMATICALLY CLEARED. + [6:6] + read-write + + + LINK_GO_INACTIVE + SET THE LINK TO ENTER SS.INACTIVE, + WHICH IS HIGHLY VALID, AND THE HARDWARE IS AUTOMATICALLY CLEARED + [5:5] + read-write + + + LINK_GO_DISABLED + SET LINK TO ENTER SS.DISABLED, WHICH IS HIGHLY VALID, + AND REQUIRES SOFTWARE TO CLEAR + [4:4] + read-write + + + LINK_PD_MODE + Configure the current power mode of the PHY, corresponding to PO/P1/P2/P3 in the PIPE + [1:0] + read-write + + + + + LINK_INT_CTRL + LINK interrupt enable register + 0x08 + 0x20 + 0x00000000 + + + LINK_IE_STATE_CHG + Link State Machine Change Flag Interrupt Enabled + [31:31] + read-write + + + LINK_IE_U1_TOUT + U1 Timeout Interrupt Enabled + [30:30] + read-write + + + LINK_IE_U2_TOUT + U2 Timeout Interrupt Enabled + [29:29] + read-write + + + LINK_IE_UX_FAIL + UX Conversion Failure Interrupt Enabled + [28:28] + read-write + + + LINK_IE_TX_WARMRST + Send warm_reset end interrupt enabled + [27:27] + read-write + + + LINK_IE_UX_EXIT_FAIL + Exit UX failed to interrupt enabled + [26:26] + read-write + + + LINK_IE_RX_LMP_TOUT + Receive LMP Timeout Interrupt Enabled + [23:23] + read-write + + + LINK_IE_TX_LMP + If you successfully enter U0, you can send an HP packet to interrupt enable + [22:22] + read-write + + + LINK_IE_RX_LMP + Received Link Command Flag Interrupt Enabled + [21:21] + read-write + + + LINK_IE_RX_DET + The link enters the Rx.Detect state and is interrupted + [20:20] + read-write + + + LINK_IE_LOOPBACK + The link goes into loopback mode for testing and error isolation interrupt enablement + [19:19] + read-write + + + LINK_IE_COMPLIANCE + The link enters the compliance test, + and the interrupt is enabled by the compatibility test or the physical layer conformance test + [18:18] + read-write + + + LINK_IE_HPBUF_FULL + BUF sends FIFO full interrupt enable + [17:17] + read-write + + + LINK_IE_HPBUF_EMPTY + BUF sends FIFO null interrupt enable + [16:16] + read-write + + + LINK_IE_HOT_RST + hot reset, which uses the reset interrupt enable of the TS1/TS2 ordered set + [15:15] + read-write + + + LINK_IE_U3_WAKEUP + In the U3 state, the Low Frequency Periodic Signal (LFPS) is received to wake up interrupt enabled + [14:14] + read-write + + + LINK_IE_WARM_RST + Warm reset (not connected) interrupt enabled with LPFS + [13:13] + read-write + + + LINK_IE_UX_EXIT + Request to exit UX is received Interrupt Enable + [12:12] + read-write + + + LINK_IE_TXEQ + LINK enters the POLLING_RXEQ for receiver equalization training interrupt enable + [11:11] + read-write + + + LINK_IE_TERM_PRES + LINK enters the RX_DETECT to detect the impedance of the remote receiver trace segment and detect the interrupt enabled + [10:10] + read-write + + + LINK_IE_UX_REJ + Transmit LGO_ Ux, receive LXU interrupt enabled that refuses to enter the Ux + [9:9] + read-write + + + LINK_IE_U3_WK_TOUT + Interrupt the U3 command when requesting to exit U3 command timeout + [8:8] + read-write + + + LINK_IE_GO_U0 + LINK is interrupted at U0 to enable the following + [7:7] + read-write + + + LINK_IE_GO_U1 + LINK is interrupted at U1 to enable the following + [6:6] + read-write + + + LINK_IE_GO_U2 + LINK is interrupted at U2 and enabled + [5:5] + read-write + + + LINK_IE_GO_U3 + LINK is enabled when the U3 interrupt is enabled + [4:4] + read-write + + + LINK_IE_DISABLE + LINK is disabled, interrupt enabled + [3:3] + read-write + + + LINK_IE_INACTIVE + LINK is enabled on INACTIVE interrupt + [2:2] + read-write + + + LINK_IE_RECOVERY + DUE TO ERROR LINK IN RECOVERY INTERRUPTED ENABLED + [1:1] + read-write + + + LINK_IE_READY + LINK is initialized, including two ports before (Header Sequence Number Advertisement) + and (RX Headr Buffer Credit Advertisement) interrupt enabled + [0:0] + read-write + + + + + LINK_INT_FLAG + LINK Interrupt Flag Register + 0x0C + 0x20 + 0x00000000 + + + LINK_IF_STATE_CHG + link_reset reset to 0 + [31:31] + read-write + + + LINK_IF_U1_TOUT + U1 timeout interrupted + [30:30] + read-write + + + LINK_IF_U2_TOUT + U2 timeout interrupted + [29:29] + read-write + + + LINK_IF_UX_FAIL + Enter the Ux failed to interrupt + [28:28] + read-write + + + LINK_IF_TX_WARMRST + send warm_reset to end interrupt + [27:27] + read-write + + + LINK_IF_UX_EXIT_FAIL + Exit UX fails to interrupt + [26:26] + read-write + + + LINK_IF_RX_LMP_TOUT + After the LINK initialization is complete, + the Port Capabilities/Configuration LMPs timeout (20us) interrupt flag is exchanged. + [23:23] + read-write + + + LINK_IF_TX_LMP + After the LINK initialization is completed, + the software is configured to send Port Capabilities LMP for port capability switching + [22:22] + read-write + + + LINK_IF_RX_LMP + Receive LMP Interrupt Flag + [21:21] + read-write + + + LINK_IF_RX_DET + After entering the RX_DETECT state interrupt flag, this position 1, + the software sets the PWR_MODE to P2, ready for RX_DETECT + [20:20] + read-write + + + LINK_IF_LOOPBACK + LINK enters the LOOPBACK state and the LINK is interrupted. + [19:19] + read-write + + + LINK_IF_COMPLIANCE + LINK enters the COMPLIANCE state with an outage flag. + [18:18] + read-write + + + LINK_IF_HPBUF_FULL + Header Packet buffer full interrupt flag. + [17:17] + read-write + + + LINK_IF_HPBUF_EMPTY + he device receives the HOT RESET interrupt flag + [16:16] + read-write + + + LINK_IF_HOT_RST + The device receives the HOT RESET interrupt flag + [15:15] + read-write + + + LINK_IF_WAKEUP + The power supply is in P3 mode and the LFPS signal interrupt flag is detected. + [14:14] + read-write + + + LINK_IF_WARM_RST + The WARM RESET status change (active-> inactive, + or invalid->active) interrupt flag received by the device. + [13:13] + read-write + + + LINK_IF_UX_EXIT + LINK receives the LFPS ready to exit U1/U2/U3 request interrupt flag + [12:12] + read-write + + + LINK_IF_TXEQ + LINK enters TXEQ state interrupt flag: + INDICATE THAT THE POLLING HANDSHAKE IS COMPLETE, + AND WAIT FOR THE SOFTWARE TO SET THE PWR_MODE TO P0 IN ORDER TO ENTER THE TXEQ PHASE. + [11:11] + read-write + + + LINK_IF_TERM_PRES + The TERM disconnected or disconnected flag was detected + [10:10] + read-write + + + LINK_IF_UX_REJ + LINK refuses to enter the low-power mode (U1/U2) interrupt flag. + [9:9] + read-write + + + LINK_IF_U3_WK_TOUT + Wake up from U3 to timeout interrupt flag (10ms). + [8:8] + read-write + + + LINK_IF_GO_U0 + LINK enters the U0 state interrupt flag. + [7:7] + read-write + + + LINK_IF_GO_U1 + LINK enters the U1 state interrupt flag. + [6:6] + read-write + + + LINK_IF_GO_U2 + LINK enters the U2 state interrupt flag. + [5:5] + read-write + + + LINK_IF_GO_U3 + LINK enters the U3 state interrupt flag. + [4:4] + read-write + + + LINK_IF_DISABLE + LINK INTO SS.DISABLE STATE INTERRUPT FLAG + [3:3] + read-write + + + LINK_IF_INACTIVE + LINK ENTERS THE SS.ACTIVE STATE INTERRUPT FLAG + [2:2] + read-write + + + LINK_IF_RECOVERY + LINK INTO THE SS.RECOVERY STATE INTERRUPT FLAG + [1:1] + read-write + + + LINK_IF_READY + LINK enters the U0 state and completes LINK initialization of the interrupt flag. + [0:0] + read-write + + + + + LINK_STATUS + LINK Status Register + 0x10 + 0x20 + 0x00000000 + + + LINK_HPBUF_EMPTY + The HP buffer is empty. + [31:31] + read-only + + + LINK_HPBUF_FULL + The HP buffer is full. + [30:30] + read-only + + + LINK_HPBUF_IDLE + BUF sends the status of the FIFO IDLE + [29:29] + read-only + + + LINK_U3_SLEEP_ALLOW + The link is in the U3 state and sleep is allowed + [22:22] + read-only + + + LINK_U2_SLEEP_ALLOW + The link is in the U2 state and sleep is allowed. + [21:21] + read-only + + + LINK_RXDET_SLEEP_ALLOW + The link is in the RXDET state, allowing sleep. + [20:20] + read-only + + + LINK_WAKUP + A link wake-up signal is received. + [19:19] + read-only + + + LINK_RX_LFPS + The link receives an LFPS signal. + [18:18] + read-only + + + LINK_RX_DETECT + The link is at P2 and is in rx_detect. + [17:17] + read-only + + + LINK_RX_UX_EXIT_REQ + Received a request to exit Ux + [16:16] + read-only + + + LINK_STATE + Link Status + [11:8] + read-only + + + LINK_TXEQ + The link is in POLLING_RXEQ. + [6:6] + read-only + + + LINK_PD_MODE_MASK + Link Power Status + [5:4] + read-only + + + LINK_READY + When the LINK enters the U0 state, the position 1 exits the U0 state after the initialization + (broadcast) is completed, and the bit is automatically cleared. + [3:3] + read-only + + + LINK_BUSY + When the LINK is busy, the bit is 1 when the switchover is PD_MODE, + and the hardware will automatically clear the link after the switchover is completed. + [2:2] + read-only + + + LINK_RX_WARM_RST + A valid warm-reset signal is received from the host + (the hardware automatically pulls up after receiving the host's warm_reset 18ms). + [1:1] + read-only + + + LINK_RX_TERM_PRES + After RX_DETECT, if a receive termination resistor is present, the bit is 1 + [0:0] + read-only + + + + + LINK_ITP_PRE + LINK ITP Timeout Mode Register + 0x17 + 0x8 + 0x80 + + + ITP_PRE + ITP Timeout Mode + [7:0] + read-only + + + + + LINK_U2_INACT_TIMER + LINK U2 Inactivity Timeout Counter Threshold Register + 0x1D + 0x8 + 0X00 + + + U2_INACTIVE_TIMER + The value of the inactivity timeout counter threshold for U2 + [7:0] + read-write + + + + + LINK_U1_WKUP_FILTER + U1 wakes up the LFPS Duration Register + 0x28 + 0x8 + 0x4A + + + U1_WKUP_FILTER + The duration of the LFPS received by U1 when exiting. + When the receiving LFPS reaches this time, the received U1 EXIT is considered valid, + and the handshake is successful when the transmitting LFPS_last is raised, which is 600ns by default + U1_WKUP_FILTER [7]: the unit of time that controls the U1_WKUP_FILTER [6:0] + [7:0] + read-write + + + + + LINK_U2_WKUP_FILTER + U2 wakes up the LFPS Duration Register + 0x2C + 0x8 + 0X02 + + + U2_WKUP_FILTER + When the receiving LFPS reaches this time, the sending LFPS_last is pulled up and the handshake is successful, + and the received U2 EXIT can be considered valid with the duration of (n)us, the default is 2us. + [7:0] + read-write + + + + + LINK_U3_WKUP_FILTER + U3 wakes up the LFPS validity duration register + 0x30 + 0x8 + 0X64 + + + U3_WKUP_FILTER + When the receiving LFPS reaches this time, the LFPS_last is raised, and the handshake is successful, + and the received U3 EXIT is considered valid for (n)us, with a default of 100us. + [7:0] + read-write + + + + + LINK_ISO_DLY + LINK Synchronous Delay Register + 0x40 + 0x10 + 0x0028 + + + LINK_ISOCH_DLY + The delay time for the serial bitstream to parse to the parallel data is 40ns by default, + and the SET ISOCH DELAY host sends this information to the device when enumerated, + and writes the delay information to the register as the device, and the lower 3 bits of the register are invalid + (because the clock frequency is 125MHz, the delay time needs to be set to 8*n). + [15:0] + read-write + + + + + LINK_LPM_CR + Link Power Management Registers + 0x50 + 0x10 + 0x0180 + + + PHY_CHSEL_AUTO + Automatic selection of the PHY layer transceiver channel type + [13:13] + read-write + + + LPM_RXDET_EN + When the lpm count reaches the expected value RXDET_EXP it is confirmed that + a device is connected to the PHY, this bit is raised. + [12:12] + read-write + + + LPM_TERM_PRESENT + The PHY layer detects a device connection. + [11:11] + read-write + + + LPM_TERM_CHG + The connected device changes, plugs in the device or unplugs the device. + [10:10] + read-write + + + LPM_EN + LPM Enable + [9:9] + read-write + + + LPM_RST + Reset signal for LPM related register + [8:8] + read-write + + + RXDET_EXP + Detects external device counter registers. + [7:0] + read-write + + + + + LINK_LMP_PORT_CAP + PORT_CAP Registers + 0x54 + 0x20 + 0x00000000 + + + LINK_LMP_RX_CAP_VLD + A valid PORT_CAP-LMP is received, and the protocol stipulates that + the two LINK parties exchange PORT_CAP-LMP within 20 years after entering the U0 state. + [31:31] + read-only + + + LINK_LMP_TX_CAP_VLD + PORT Capability configuration completion flag + [30:30] + read-only + + + LINK_SPEED + [24] Position 1, indicating that the supported device supports USB3.2 Gen1 (5Gbps). + [29:24] + read-only + + + LINK_REG_PORT_CAP + link port configure + [23:0] + read-only + + + + + LINK_LMP_RX_DATA0 + LMP receives data 0 register + 0x58 + 0x20 + 0x00000000 + + + LINK_LMP_RX_DATA0 + Once the LMP is received, the HP data is stored in this register [31:0] + [31:0] + read-only + + + + + LINK_LMP_RX_DATA1 + LMP receives data 1 register + 0x5C + 0x20 + 0x00000000 + + + LINK_LMP_RX_DATA1 + Once the LMP is received, the HP data is stored in this register [63:32] + [31:0] + read-only + + + + + LINK_LMP_RX_DATA2 + LMP receives data 2 register + 0x60 + 0x20 + 0x00000000 + + + LINK_LMP_RX_DATA1 + Once the LMP is received, the HP data is stored in this register [95:64] + [31:0] + read-only + + + + + LINK_LMP_TX_DATA0 + USB Custom HP Data 0 Register + 0x64 + 0x20 + 0x00000000 + + + LINK_LMP_TX_DATA0 + The data of the user-defined HP is sent [31:0] + [31:0] + read-write + + + + + LINK_LMP_TX_DATA1 + USB Custom HP Data 1 Register + 0x68 + 0x20 + 0x00000000 + + + LINK_LMP_TX_DATA1 + The data of the user-defined HP is sent [63:32] + [31:0] + read-write + + + + + LINK_LMP_TX_DATA2 + USB Custom HP Data 2 Register + 0x6c + 0x20 + 0x00000000 + + + LINK_LMP_TX_DATA2 + The data of the user-defined HP is sent [95:64] + [31:0] + read-write + + + + + + + + PIOC + Programmable protocol I/O microcontroller + PIOC + 0x40025C00 + + 0x0 + 0x400 + registers + + + PIOC + PIOC global interrupt + 122 + + + + SFR_INDIR_PORT + SFR_INDIR_PORT + Indirectly addressed data read/write ports + 0x00 + 0x08 + 0x00 + + + + RSFR_INDIR_PORT2 + SFR_INDIR_PORT2 + Indirectly addresses the data read/write port of 2 + 0x01 + 0x08 + 0x00 + + + + SFR_PRG_COUNT + SFR_PRG_COUNT + Program counters for the low bytes of the PC + 0x02 + 0x08 + 0x00 + + + + SFR_STATUS_REG + R8_SFR_STATUS_REG + Status registers + 0x03 + 0x08 + 0x00 + + + SB_STACK_USED + Current stack usage flags + 5 + 1 + + + SB_EN_TOUT_RST + Timer Timeout Reset Enabled + 4 + 1 + + + SB_GP_BIT_Y + a generic bit variable Y, defined and used by the application + 3 + 1 + + + SB_FLAG_Z + ALU zero flag, whether the result is 00H + 2 + 1 + + + SB_GP_BIT_X + A generic bit variable X, defined and used by the application + 1 + 1 + + + SB_FLAG_C + ALU carry flag, whether the result is carried or produced by displacement + 0 + 1 + + + + + + SFR_INDIR_ADDR + SFR_INDIR_ADDR + Indirectly addressed address registers + 0x04 + 0x08 + read-only + 0x00 + + + + SFR_TMR0_COUNT + SFR_TMR0_COUNT + The counter register of timer 0 + 0x05 + 0x08 + read-only + 0x00 + + + + SFR_TIMER_CTRL + SFR_TIMER_CTRL + The control register of the timer + 0x06 + 0x08 + read-only + 0x00 + + + + SFR_TMR0_INIT + SFR_TMR0_INIT + The initial register of timer 0 + 0x07 + 0x08 + read-only + 0x00 + + + + SFR_BIT_CYCLE + SFR_BIT_CYCLE + Periodic registers for coded bits + 0x08 + 0x08 + read-write + 0x00 + + + SB_BIT_TX_O0 + The raw bit data of the encoded bit to be sent, which is a double-buffered structure + 7 + 1 + + + SB_BIT_CYCLE + Sets the width of the encoded bits in clock cycles, which is the actual number of bits minus 1 + 0 + 7 + + + + + + SFR_INDIR_ADDR2 + SFR_INDIR_ADDR2 + Address registers for indirect address 2 + 0x09 + 0x08 + read-only + 0x00 + + + + SFR_PORT_DIR + SFR_PORT_DIR + The port direction sets the register + 0x0A + 0x08 + read-only + 0x00 + + + SB_PORT_MOD3 + Pin mode control, host side defines the purpose + 7 + 1 + + + SB_PORT_MOD2 + Pin mode control, host side defines the purpose + 6 + 1 + + + SB_PORT_MOD1 + Pin mode control, host side defines the purpose + 5 + 1 + + + SB_PORT_MOD0 + Pin mode control, host side defines the purpose + 4 + 1 + + + SB_PORT_PU1 + IO1 Pin Pull-Up Enables + 3 + 1 + + + SB_PORT_PU0 + IO0 Pin Pull-Up Enables + 2 + 1 + + + SB_PORT_DIR1 + IO1 Pin Direction Control + 1 + 1 + + + SB_PORT_DIR0 + IO0 Pin Direction Control + 0 + 1 + + + + + + SFR_PORT_IO + SFR_PORT_IO + Port input and output registers + 0x0B + 0x08 + read-only + 0x00 + + + + SFR_BIT_CONFIG + SFR_BIT_CONFIG + Coded bit configuration registers + 0x0C + 0x08 + read-only + 0x00 + + + SB_BIT_TX_EN + The transmission of the coded bits is enabled + 7 + 1 + + + SB_BIT_CODE_MOD + How the coded bits are modulated + 6 + 1 + + + SB_PORT_IN_EDGE + Pin input level sampling point selection + 5 + 1 + + + SB_BIT_CYC_TAIL + Periodic state of the encoded bits + 4 + 1 + + + SB_BIT_CYC_CNT6 + The periodic timing state of the encoded bits + 3 + 1 + + + SB_BIT_CYC_CNT5 + The periodic timing state of the encoded bits + 2 + 1 + + + SB_BIT_CYC_CNT4 + The periodic timing state of the encoded bits + 1 + 1 + + + SB_BIT_CYC_CNT3 + The periodic timing state of the encoded bits + 0 + 1 + + + + + + SFR_SYS_CFG + SFR_SYS_CFG + System configuration registers + 0x1C + 0x08 + 0x00 + + + SB_INT_REQ + Interrupt Request Activation Bits + 7 + 1 + read-only + + + SB_DATA_SW_MR + SFR_CTRL_RD wait to read the status bit + 6 + 1 + read-only + + + SB_DATA_MW_SR + SFR_CTRL_WR waiting to read the status bit + 5 + 1 + read-only + + + SB_MST_CFG_B4 + Configure information bits, software-defined uses + 4 + 1 + write-only + + + SB_MST_IO_EN1 + Mode and output control switches for IO1 pins + 3 + 1 + write-only + + + SB_MST_IO_EN0 + Mode and output control switches for IO0 pins + 2 + 1 + write-only + + + SB_MST_RESET + Force eMCU Reset + 1 + 1 + write-only + + + SB_MST_CLK_GATE + Global Clock Control for eMCUs + 0 + 1 + write-only + + + + + + SFR_CTRL_RD + SFR_CTRL_RD + The eMCU reads and writes and the host reads only the registers + 0x1D + 0x08 + read-only + 0x00 + + + + SFR_CTRL_WR + SFR_CTRL_WR + The host reads and writes and the eMCU reads only registers + 0x1E + 0x08 + read-write + 0x00 + + + + SFR_DATA_EXCH + SFR_DATA_EXCH + Data exchange registers + 0x1F + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG0 + SFR_DATA_REG0 + Data register 0 + 0x20 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG1 + SFR_DATA_REG1 + Data register 1 + 0x21 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG2 + SFR_DATA_REG2 + Data register 2 + 0x22 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG3 + SFR_DATA_REG3 + Data register 3 + 0x23 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG4 + SFR_DATA_REG4 + Data register 4 + 0x24 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG5 + SFR_DATA_REG5 + Data register 5 + 0x25 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG6 + SFR_DATA_REG6 + Data register 6 + 0x26 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG7 + SFR_DATA_REG7 + Data register 7 + 0x27 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG8 + SFR_DATA_REG8 + Data register 8 + 0x28 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG9 + SFR_DATA_REG9 + Data register 9 + 0x29 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG10 + SFR_DATA_REG10 + Data register 10 + 0x2A + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG11 + SFR_DATA_REG11 + Data register 11 + 0x2B + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG12 + SFR_DATA_REG12 + Data register 12 + 0x2C + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG13 + SFR_DATA_REG13 + Data register 13 + 0x2D + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG14 + SFR_DATA_REG14 + Data register 14 + 0x2E + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG15 + SFR_DATA_REG15 + Data register 15 + 0x2F + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG16 + SFR_DATA_REG16 + Data register 16 + 0x30 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG17 + SFR_DATA_REG17 + Data register 17 + 0x31 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG18 + SFR_DATA_REG18 + Data register 18 + 0x32 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG19 + SFR_DATA_REG19 + Data register 19 + 0x33 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG20 + SFR_DATA_REG20 + Data register 20 + 0x34 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG21 + SFR_DATA_REG21 + Data register 21 + 0x35 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG22 + SFR_DATA_REG22 + Data register 22 + 0x36 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG23 + SFR_DATA_REG23 + Data register 23 + 0x37 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG24 + SFR_DATA_REG24 + Data register 24 + 0x38 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG25 + SFR_DATA_REG25 + Data register 25 + 0x39 + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG26 + SFR_DATA_REG26 + Data register 26 + 0x3A + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG27 + SFR_DATA_REG27 + Data register 27 + 0x3B + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG28 + SFR_DATA_REG28 + Data register 28 + 0x3C + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG29 + SFR_DATA_REG29 + Data register 29 + 0x3D + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG30 + SFR_DATA_REG30 + Data register 30 + 0x3E + 0x08 + read-write + 0x00 + + + + SFR_DATA_REG31 + SFR_DATA_REG31 + Data register 31 + 0x3F + 0x08 + read-write + 0x00 + + + + + + + UHSIF + Universal high speed interface + UHSIF + 0x40038000 + + 0x0 + 0x400 + registers + + + UHSIF + UHSIF global interrupt + 145 + + + + + SDIO + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 147 + + + + POWER + POWER + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + Power supply control bits + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + (SDIO_CLKCR) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock divide factor + 0 + 8 + + + CLKEN + Clock enable bit + 8 + 1 + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + + + ARG + ARG + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + SDIO command register + (SDIO_CMD) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDINDEX + Command index + 0 + 6 + + + WAITRESP + Wait for response bits + 6 + 2 + + + WAITINT + CPSM waits for interrupt request + 8 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer (CmdPend internal signal) + 9 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable bit + 10 + 1 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + + NIEN + not Interrupt Enable + 13 + 1 + + + ATACMD + CE-ATA command + 14 + 1 + + + + + RESPCMD + RESPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + Bits 127:96 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + Card status 1 + 0 + 32 + + + + + RESP2 + RESP2 + Bits 95:64 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + Card status 2 + 0 + 32 + + + + + RESP3 + RESP3 + Bits 63:32 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + Card status 3 + 0 + 32 + + + + + RESP4 + RESP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + Card status 4 + 0 + 32 + + + + + DTIMER + DTIMER + Bits 31:0 = DATATIME: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + DTEN + Data transfer enabled bit + 0 + 1 + + + DTDIR + Data transfer direction selection + 1 + 1 + + + DTMODE + Data transfer mode selection 1: Stream or + SDIO multibyte data transfer + 2 + 1 + + + DMAEN + DMA enable bit + 3 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + PWSTART + Read wait start + 8 + 1 + + + PWSTOP + Read wait stop + 9 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + + + DCOUNT + DCOUNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CCRCFAIL + Command response received (CRC check failed) + 0 + 1 + + + DCRCFAIL + Data block sent/received (CRC check failed) + 1 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + TXUNDERR + Transmit FIFO underrun error + 4 + 1 + + + RXOVERR + Received FIFO overrun error + 5 + 1 + + + CMDREND + Command response received (CRC check passed) + 6 + 1 + + + CMDSENT + Command sent (no response required) + 7 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is zero) + 8 + 1 + + + STBITERR + Start bit not detected on all data signals in wide bus mode + 9 + 1 + + + DBCKEND + Data block sent/received (CRC check passed) + 10 + 1 + + + CMDACT + Command transfer in progress + 11 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 words can be written into the + FIFO + 14 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at least 8 words in the + FIFO + 15 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXDAVL + Data available in transmit FIFO + 20 + 1 + + + RXDAVL + Data available in receive FIFO + 21 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + CEATAEND + CE-ATA command completion signal received for CMD61 + 23 + 1 + + + + + ICR + ICR + SDIO interrupt clear register + (SDIO_ICR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + + + MASK + MASK + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CCRCFAILIE + Command CRC fail interrupt + enable + 0 + 1 + + + DCRCFAILIE + Data CRC fail interrupt + enable + 1 + 1 + + + CTIMEOUTIE + Command timeout interrupt + enable + 2 + 1 + + + DTIMEOUTIE + Data timeout interrupt + enable + 3 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt + enable + 4 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt + enable + 5 + 1 + + + CMDRENDIE + Command response received interrupt + enable + 6 + 1 + + + CMDSENTIE + Command sent interrupt + enable + 7 + 1 + + + DATAENDIE + Data end interrupt + enable + 8 + 1 + + + STBITERRIE + Start bit error interrupt + enable + 9 + 1 + + + DBACKENDIE + Data block end interrupt + enable + 10 + 1 + + + CMDACTIE + Command acting interrupt + enable + 11 + 1 + + + TXACTIE + Data transmit acting interrupt + enable + 12 + 1 + + + RXACTIE + Data receive acting interrupt + enable + 13 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt + enable + 14 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt + enable + 15 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt + enable + 16 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt + enable + 17 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt + enable + 18 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt + enable + 19 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt + enable + 20 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt + enable + 21 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable + 22 + 1 + + + CEATENDIE + CE-ATA command completion signal received interrupt + enable + 23 + 1 + + + + + FIFOCNT + FIFOCNT + Bits 23:0 = FIFOCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + FIF0COUNT + Remaining number of words to be written to or read from the + FIFO + 0 + 32 + + + + + DCTRL2 + SDIO_DCTRL2 + Data control register 2 + 0x60 + 0x20 + read-only + 0x00000000 + + + SLV_CK_PHASE + phase selection bit when DATA is output from the mode + 26 + 1 + + + SLV_FORCE_ERR + in slave mode software forces data block CRC errors + 25 + 1 + + + SLV_MODE + slave mode enable bit + 24 + 1 + + + RANDOM_LEN_EN + data block arbirary byte length enable bit + 16 + 1 + + + DBLOCKSIZE2 + data block length field of arbirary byte length pattern + 0 + 12 + + + + + FIFO + FIFO + bits 31:0 = FIFOData: Receive and transmit + FIFO data + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFODATA + Receive and transmit FIFO data + 0 + 32 + + + + + + + + EMMC + EMMC register + EMMC + 0x40024000 + + 0x00 + 0x400 + registers + + + SDMMC + SDMMC global interrupt + 95 + + + + + R32_EMMC_ARGUMENT + SD 32bits command argument register + 0x00 + 32 + read-write + 0x00000000 + + + EMMC_ARGUMENT + 32 bit command parameter register + [31:0] + + + + + R16_EMMC_CMD_SET + SD 16bits cmd setting register + 0x04 + 16 + read-write + 0x0000 + + + RB_EMMC_CMDIDX_MASK + the index number of the currently sent command + [5:0] + + + RB_EMMC_RPTY_MASK + current respone type + [9:8] + + + RB_EMMC_CKCRC + check the response CRC + [10:10] + + + RB_EMMC_CKIDX + check the response command index + [11:11] + + + + + R32_EMMC_RESPONSE0 + SD 128bits response register, [31:0] 32bits + 0x08 + 32 + read-only + 0x00000000 + + + R32_EMMC_RESPONSE0 + response parameter register + [31:0] + + + + + R32_EMMC_RESPONSE1 + SD 128bits response register, [63:32] 32bits + 0x0C + 32 + read-only + 0x00000000 + + + R32_EMMC_RESPONSE1 + response parameter register + [31:0] + + + + + R32_EMMC_RESPONSE2 + SD 128bits response register, [95:64] 32bits + 0x10 + 32 + read-only + 0x00000000 + + + R32_EMMC_RESPONSE2 + response parameter register + [31:0] + + + + + R32_EMMC_RESPONSE3 + SD 128bits response register, [127:96] 32bits + 0x14 + 32 + read-only + 0x00000000 + + + R32_EMMC_RESPONSE3 + response parameter register + [31:0] + + + + + R32_EMMC_WRITE_CONT + Multiplexing register of the EMMC_RESPONSE3,[127:96] 32bits + R32_EMMC_RESPONSE3 + 0x14 + 32 + write-only + 0x00000000 + + + R32_EMMC_WRITE_CONT + response parameter register + [31:0] + + + + + R16_EMMC_CONTROL + SD 8 bits control register + 0x18 + 0x10 + read-write + 0x15 + + + RB_EMMC_LW_MASK + effctive data width for sending or receiving data + [1:0] + + + RB_EMMC_ALL_CLR + reset all the inner logic, default is valid + [2:2] + + + RB_EMMC_DMAEN + enable the dma + [3:3] + + + RB_EMMC_RST_LGC + reset the data tran/recv logic + [4:4] + + + RB_EMMC_NEGSMP + controller use nagedge sample cmd + [5:5] + + + RB_SLV_MODE + enable Slave mode + [8:8] + + + RB_SLV_FORCE_ERR + Software forced data block CRC error in slave mode + [9:9] + + + + + R8_EMMC_TIMEOUT + SD 8 bits data timeout value + 0x1C + 8 + read-write + 0x0C + + + RB_EMMC_TOCNT_MASK + response data timeout configuration + [3:0] + + + + + R32_EMMC_STATUS + SD status + 0x20 + 32 + read-only + 0x00000000 + + + MASK_BLOCK_NUM + the number of blocks successfully transmitted in the current multi-block transmission + [15:0] + + + RB_EMMC_CMDSTA + indicate cmd line is high level now + [16:16] + + + RB_EMMC_DAT0STA + indicate dat[0] line is high level now + [17:17] + + + + + R16_EMMC_INT_FG + SD 16bits interrupt flag register + 0x24 + 16 + read-write + 0x0000 + + + RB_EMMC_IF_RE_TMOUT + indicate when expect the response, timeout + [0:0] + + + RB_EMMC_IF_RECRC_WR + indicate CRC error of the response + [1:1] + + + RB_EMMC_IF_REIDX_ER + indicate INDEX error of the response + [2:2] + + + RB_EMMC_IF_CMDDONE + when cmd hasn't response, indicate cmd has been sent, when cmd has a response, indicate cmd has bee sent and has received the response + [3:3] + + + RB_EMMC_IF_DATTMO + data line busy timeout + [4:4] + + + RB_EMMC_IF_TRANERR + last block have encountered a CRC error + [5:5] + + + RB_EMMC_IF_TRANDONE + all the blocks have been tran/recv successfully + [6:6] + + + RB_EMMC_IF_BKGAP + every block gap interrupt when multiple read/write, allow drive change the DMA address at this moment + [7:7] + + + RB_EMMC_IF_FIFO_OV + fifo overflow, when write sd, indicate empty overflow, when read sd, indicate full overflow + [8:8] + + + RB_EMMC_IF_SDIOINT + interrupt from SDIO card inside + [9:9] + + + RB_SIF_SLV_BUF_RELEASE + In slave double buffer mode,BUF releases the flag bit + [10:10] + + + + + R16_EMMC_INT_EN + SD 16bits interrupt enable register + 0x28 + 16 + read-write + 0x0000 + + + RB_EMMC_IE_RE_TMOUT + command response timeout interrupt enable + [0:0] + + + RB_EMMC_IE_RECRC_WR + response CRC check error interrupt enable + [1:1] + + + RB_EMMC_IE_REIDX_ER + response index check error interrupt enable + [2:2] + + + RB_EMMC_IE_CMDDONE + command completion interrupt enable + [3:3] + + + RB_EMMC_IE_DATTMO + data timeout interrupt enable + [4:4] + + + RB_EMMC_IE_TRANERR + blocks transfer CRC error interrupt enable + [5:5] + + + RB_EMMC_IE_TRANDONE + all blocks transfer complete interrupt enable + [6:6] + + + RB_EMMC_IE_BKGAP + single block transmission completion interrupt enable + [7:7] + + + RB_EMMC_IE_FIFO_OV + FIFO overflow interrupt enable + [8:8] + + + RB_EMMC_IE_SDIOINT + SDIO card interrupt enable + [9:9] + + + + + R32_EMMC_DMA_BEG1 + SD 32 bits DMA start address register when to operate + 0x2C + 32 + read-write + 0x00000000 + + + RB_EMMC_DMAAD1_MASK + start address of read-write data buffer,the lower 4 bits are fixed to 0 + [31:0] + + + + + R32_EMMC_BLOCK_CFG + SD 32bits data counter, [15:0] number of blocks this time will tran/recv, [27:16] block sise(byte number) of every block in this time tran/recv + 0x30 + 32 + read-write + 0x00000000 + + + RB_EMMC_BKNUM_MASK + the number of blocks to be transferred + [15:0] + + + RB_EMMC_BKSIZE_MASK + single block transfer size + [27:16] + + + + + R32_EMMC_TRAN_MODE + SD TRANSFER MODE register + 0x34 + 32 + read-write + 0x00000000 + + + RB_EMMC_DMA_DIR + set DMA direction is controller to emmc card + [0:0] + + + RB_EMMC_GAP_STOP + clock stop mode after block completion + [1:1] + + + RB_EMMC_MODE_BOOT + enable emmc boot mode + [2:2] + + + RB_EMMC_AUTOGAPSTOP + enable auto set bTM_GAP_STOP when tran start + [4:4] + + + RB_EMMC_DMATN_CNT + in double buffer mode,set the block count value of buffer switch + [14:8] + + + RB_EMMC_DULEDMA_EN + enable double buffer dma + [16:16] + + + RB_DDR_MODE + enable DDR mode + [17:17] + + + RB_CARE_NEG + In DDR mode,check the falling edge of the clock + [18:18] + + + RB_SW + In DDR mode,the clock is switched + [20:19] + + + + + R16_EMMC_CLK_DIV + SD clock divider register + 0x38 + 16 + read-write + 0x0213 + + + RB_EMMC_DIV_MASK + clk div + [4:0] + + + RB_EMMC_CLKOE + chip output sdclk oe + [8:8] + + + RB_EMMC_CLKMode + EMMC clock frequency mode selection bit + [9:9] + + + RB_EMMC_PHASEINV + invert chip output sdclk phase + [10:10] + + + + + R32_EMMC_DMA_BEG2 + SD 32bits DMA start address register when to operate + 0x3C + 32 + read-write + 0x00000000 + + + RB_EMMC_DMAAD2_MASK + start address of read-write data buffer,the lower 4 bits are fixed to 0 + [31:0] + + + + + R32_EMMC_TUNE_DATO + data output delay register + 0x40 + 32 + read-write + 0x00000000 + + + RB_TUNNE_DAT0_O + the delay of data 0 output + [3:0] + + + RB_TUNNE_DAT1_O + the delay of data 1 output + [7:4] + + + RB_TUNNE_DAT2_O + the delay of data 2 output + [11:8] + + + RB_TUNNE_DAT3_O + the delay of data 3 output + [15:12] + + + RB_TUNNE_DAT4_O + the delay of data 4 output + [19:16] + + + RB_TUNNE_DAT5_O + the delay of data 5 output + [23:20] + + + RB_TUNNE_DAT6_O + the delay of data 6 output + [27:24] + + + RB_TUNNE_DAT7_O + the delay of data 7 output + [31:28] + + + + + R32_EMMC_TUNE_DATI + data input delay register + 0x44 + 32 + read-write + 0x00000000 + + + RB_TUNNE_DAT0_I + In DDR mode,the delay of data 0 input + [3:0] + + + RB_TUNNE_DAT1_I + In DDR mode,the delay of data 1 input + [7:4] + + + RB_TUNNE_DAT2_I + In DDR mode,the delay of data 2 input + [11:8] + + + RB_TUNNE_DAT3_I + In DDR mode,the delay of data 3 input + [15:12] + + + RB_TUNNE_DAT4_I + In DDR mode,the delay of data 4 input + [19:16] + + + RB_TUNNE_DAT5_I + In DDR mode,the delay of data 5 input + [23:20] + + + RB_TUNNE_DAT6_I + In DDR mode,the delay of data 6 input + [27:24] + + + RB_TUNNE_DAT7_I + In DDR mode,the delay of data 7 input + [31:28] + + + + + R32_EMMC_TUNE_CLK_CMD + clock and command delay registers + 0x48 + 32 + read-write + 0x00000000 + + + RB_TUNNE_CLK_O + In DDR mode,delay in command input + [3:0] + + + RB_TUNNE_CLK_I + In DDR mode,delay in command output + [7:4] + + + RB_TUNNE_CMD_O + In DDR mode,the delay of the clock input + [19:16] + + + RB_TUNNE_CMD_I + In DDR mode,the delay of the clock output + [23:20] + + + + + + + + ECDC + ECDC register + ECDC + 0x40016C00 + + 0x00 + 0x400 + registers + + + ECDC + ECDC global Interrupt + interrupt + 121 + + + + R32_ECEC_CTRL + ECED AES/SM4 register + 0x00 + 32 + 0x00000020 + + + RB_ECDC_KEYEX_EN + enable key expansion + [0:0] + read-write + + + RB_ECDC_NORMAL_EN + Enable the encryption and + decryption to work in the normal encryption and decryption mode + [1:1] + read-write + + + RB_ECDC_MODE_SEL + ECDC mode select + [3:3] + read-write + + + RB_ECDC_CLKDIV_MASK + Clock divide factor + [6:4] + read-write + + + RB_ECDC_WRSRAM_EN + module dma enable + [7:7] + read-write + + + RB_ECDC_ALGRM_MOD + Encryption and decryption algorithm mode selection + [8:8] + read-write + + + RB_ECDC_CIPHER_MOD + Block cipher mode selection + [9:9] + read-write + + + RB_ECDC_KLEN_MASK + Key length setting + [11:10] + read-write + + + RB_ECDC_DAT_MOD + source data and result data is bit endian + [13:13] + write-only + + + RB_ECDC_IE_SINGLE + Single encryption and decryption completion interrupt enable + [17:17] + read-write + + + RB_ECDC_IE_WRSRAM + Memory to memory encryption and decryption completion interrupt enable + [18:18] + write-only + + + RB_ECDC_CLOCK_SELECT + ECED AES/SM4 clock selection + [24:24] + read-write + + + RB_ECDC_AES_SM4_CLOCK_EN + ECED AES/SM4 clock enabled + [25:25] + read-write + + + + + R32_ECDC_INT_FG + Interupt flag register + 0x04 + 32 + read-write + 0x00 + + + RB_ECDC_IF_SINGLE + Single encryption and decryption completion interrupt flag + [17:17] + + + RB_ECDC_IF_WRSRAM + Memory to memory encryption and decryption completion interrupt flag + [18:18] + + + + + R32_ECDC_KEY_255T224 + User key 224-255 register + 0x08 + 32 + read-write + 0x00000000 + + + RB_ECDC_KEY_255T224 + User key 224-255 register + [31:0] + + + + + R32_ECDC_KEY_223T192 + User key 192-223 register + 0x0C + 32 + read-write + 0x00000000 + + + RB_ECDC_KEY_223T192 + User key 192-223 register + [31:0] + + + + + R32_ECDC_KEY_191T160 + User key 160-191 register + 0x10 + 32 + read-write + 0x00000000 + + + RB_ECDC_KEY_191T160 + User key 160-191 register + [31:0] + + + + + R32_ECDC_KEY_159T128 + User key 128-159 register + 0x14 + 32 + read-write + 0x00000000 + + + RB_ECDC_KEY_159T128 + User key 128-159 register + [31:0] + + + + + R32_ECDC_KEY_127T96 + User key 96-127 register + 0x18 + 32 + read-write + 0x00000000 + + + RB_ECDC_KEY_127T96 + User key 96-127 register + [31:0] + + + + + R32_ECDC_KEY_95T64 + User key 64-95 register + 0x1C + 32 + read-write + 0x00000000 + + + RB_ECDC_KEY_95T64 + User key 64-95 register + [31:0] + + + + + R32_ECDC_KEY_63T32 + User key 32-63 register + 0x20 + 32 + read-write + 0x00000000 + + + RB_ECDC_KEY_63T32 + User key 32-63 register + [31:0] + + + + + R32_ECDC_KEY_31T0 + User key 0-31 register + 0x24 + 32 + read-write + 0x00000000 + + + RB_ECDC_KEY_31T0 + User key 0-31 register + [31:0] + + + + + R32_ECDC_IV_127T96 + CTR mode count 96-127 register + 0x28 + 32 + read-write + 0x00000000 + + + RB_ECDC_IV_127T96 + CTR mode count 96-127 register + [31:0] + + + + + R32_ECDC_IV_95T64 + CTR mode count 64-95 register + 0x2C + 32 + read-write + 0x00000000 + + + RB_ECDC_IV_95T64 + CTR mode count 64-95 register + [31:0] + + + + + R32_ECDC_IV_63T32 + CTR mode count 32-63 register + 0x30 + 32 + read-write + 0x00000000 + + + RB_ECDC_IV_63T32 + CTR mode count 32-63 register + [31:0] + + + + + R32_ECDC_IV_31T0 + CTR mode count 0-31 register + 0x34 + 32 + read-write + 0x00000000 + + + RB_ECDC_IV_31T0 + CTR mode count 0-31 register + [31:0] + + + + + R32_ECDC_SGSD_127T96 + Single encryption and decryption of original data 96-127 register + 0x40 + 32 + read-write + 0x00000000 + + + RB_ECDC_SGSD_127T96 + Single encryption and decryption of original data 96-127 register + [31:0] + + + + + R32_ECDC_SGSD_95T64 + Single encryption and decryption of original data 64-95 register + 0x44 + 32 + read-write + 0x00000000 + + + RB_ECDC_SGSD_95T64 + Single encryption and decryption of original data 64-95 register + [31:0] + + + + + R32_ECDC_SGSD_63T32 + Single encryption and decryption of original data 32-63 register + 0x48 + 32 + read-write + 0x00000000 + + + RB_ECDC_SGSD_63T32 + Single encryption and decryption of original data 32-63 register + [31:0] + + + + + R32_ECDC_SGSD_31T0 + Single encryption and decryption of original data 0-31 register + 0x4C + 32 + read-write + 0x00000000 + + + RB_ECDC_SGSD_31T0 + Single encryption and decryption of original data 0-31 register + [31:0] + + + + + R32_ECDC_SGRT_127T96 + Single encryption and decryption result 96-127 register + 0x50 + 32 + read-write + 0x00000000 + + + RB_ECDC_SGRT_127T96 + Single encryption and decryption result 96-127 register + [31:0] + + + + + R32_ECDC_SGRT_95T64 + Single encryption and decryption result 64-95 register + 0x54 + 32 + read-write + 0x00000000 + + + RB_ECDC_SGRT_95T64 + Single encryption and decryption result 64-95 register + [31:0] + + + + + R32_ECDC_SGRT_63T32 + Single encryption and decryption result 0-31 register + 0x58 + 32 + read-write + 0x00000000 + + + RB_ECDC_SGRT_63T32 + Single encryption and decryption result 0-31 register + [31:0] + + + + + RB_ECDC_SGRT_31T0 + Single encryption and decryption result 0-31 register + 0x5C + 32 + read-write + 0x00000000 + + + RB_ECDC_SGRT_31T0 + Single encryption and decryption result 0-31 register + [31:0] + + + + + R32_ECDC_SRC_ADDR + encryption and decryption sram start address register + 0x60 + 32 + read-write + 0x00000000 + + + RB_ECDC_SRC_ADDR + encryption and decryption sram start address register + [31:0] + + + + + R32_ECDC_DST_ADDR + encryption and decryption sram destination address register + 0x64 + 32 + read-write + 0x00000000 + + + RB_ECDC_DST_ADDR + encryption and decryption sram destination address register + [31:0] + + + + + R32_ECDC_SRAM_LEN + encryption and decryption sram size register + 0x68 + 32 + read-write + 0x00000000 + + + RB_ECDC_SRAM_LEN + encryption and decryption sram size register + [12:0] + + + + + + + + I3C + Improved inter-integrated circuit + I3C + 0x40014400 + + 0x0 + 0x400 + registers + + + I3C_EV + I3C event interrupt + 118 + + + I3C_ER + I3C error interrupt + 119 + + + I3CWakeUP + I3C wakeup interrupt + 142 + + + + I3C_CTLR + I3C_CTLR + I3C control register + 0x0 + 0x20 + 0x00000000 + + + DCNT + count of data to transfer during a read or write message, + in bytes (whatever I3C is acting as master/slave) + Linear encoding up to 64 Kbytes -1 + 0 + 16 + write-only + + + RNW + read / non-write message (when I3C is acting as master) + 16 + 1 + write-only + + + ADD + 7-bit I3C dynamic / I2C static slave address (when I3C is acting as master) + 17 + 7 + write-only + + + MTYPE + message type + 27 + 4 + write-only + + + MEND + message end type (when the I3C is acting as master) + 31 + 1 + write-only + + + + + I3C_CR_ALTERNATE + I3C_CR_ALTERNATE + I3C message control register alternate + I3C_CTLR + 0x0 + 0x20 + 0x00000000 + + + DCNT + count of data to transfer during a read or write message, in bytes (when I3C is acting as master) + Linear encoding up to 64 Kbytes -1.... + 0 + 16 + write-only + + + CCC + 8-bit CCC code (when I3C is acting as master) + 16 + 8 + write-only + + + MTYPE + message type (when I3C is acting as master) + 27 + 4 + write-only + + + MEND + message end type (when I3C is acting as master) + 31 + 1 + write-only + + + + + I3C_CFGR + I3C_CFGR + I3C configuration register + 0x4 + 0x20 + 0x00000000 + + + EN + I3C enable (whatever I3C is acting as master/slave) + 0 + 1 + read-write + + + CRINIT + initial master/slave role + 1 + 1 + read-write + + + NOARBH + no arbitrable header after a START (when I3C is acting as a master) + 2 + 1 + read-write + + + RSTPTRN + HDR reset pattern enable (when I3C is acting as a master) + 3 + 1 + read-write + + + EXITPTRN + HDR Exit Pattern enable (when I3C is acting as a master) + 4 + 1 + read-write + + + HJACK + Hot Join request acknowledge (when I3C is acting as a master) + 7 + 1 + read-write + + + RXDMAEN + RX-FIFO DMA request enable (whatever I3C is acting as master/slave) + 8 + 1 + read-write + + + RXFLUSH + RX-FIFO flush (whatever I3C is acting as master/slave)This bit can only be written. + 9 + 1 + write-only + + + RXTHRES + RX-FIFO threshold (whatever I3C is acting as master/slave) + 10 + 1 + read-write + + + TXDMAEN + TX-FIFO DMA request enable (whatever I3C is acting as master/slave) + 12 + 1 + read-write + + + TXFLUSH + TX-FIFO flush (whatever I3C is acting as master/slave) + 13 + 1 + write-only + + + TXTHRES + TX-FIFO threshold (whatever I3C is acting as master/slave) + 14 + 1 + read-write + + + SDMAEN + S-FIFO DMA request enable (when I3C is acting as master) + 16 + 1 + read-write + + + SFLUSH + S-FIFO flush (when I3C is acting as master) + 17 + 1 + write-only + + + RMODE + S-FIFO enable / status receive mode (when I3C is acting as master) + 18 + 1 + read-write + + + TMODE + transmit mode (when I3C is acting as master) + 19 + 1 + read-write + + + CDMAEN + C-FIFO DMA request enable (when I3C is acting as master) + 20 + 1 + read-write + + + B_0x0 + DMA mode is disabled for C-FIFO + 0x0 + + + B_0x1 + DMA mode is enabled for C-FIFO + 0x1 + + + + + CFLUSH + C-FIFO flush (when I3C is acting as master) + 21 + 1 + write-only + + + TSFSET + frame transfer set (a.k.a. software trigger) (when I3C is acting as master) + 30 + 1 + write-only + + + + + I3C_RDR + I3C_RDR + I3C receive data byte register + 0x10 + 0x20 + 0x00000000 + + + RDB0 + 8-bit received data on I3C bus. + 0 + 8 + read-only + + + + + I3C_RDWR + I3C_RDWR + I3C receive data word register + 0x14 + 0x20 + 0x00000000 + + + RDB0 + 8-bit received data (earliest byte on I3C bus). + 0 + 8 + read-only + + + RDB1 + 8-bit received data (next byte after RDB0 on I3C bus). + 8 + 8 + read-only + + + RDB2 + 8-bit received data (next byte after RDB1 on I3C bus). + 16 + 8 + read-only + + + RDB3 + 8-bit received data (latest byte on I3C bus). + 24 + 8 + read-only + + + + + I3C_TDR + I3C_TDR + I3C transmit data byte register + 0x18 + 0x20 + 0x00000000 + + + TDB0 + 8-bit data to transmit on I3C bus. + 0 + 8 + write-only + + + + + I3C_TDWR + I3C_TDWR + I3C transmit data word register + 0x1c + 0x20 + 0x00000000 + + + TDB0 + 8-bit transmit data (earliest byte on I3C bus) + 0 + 8 + write-only + + + TDB1 + 8-bit transmit data (next byte after TDB0[7:0] on I3C bus). + 8 + 8 + write-only + + + TDB2 + 8-bit transmit data (next byte after TDB1[7:0] on I3C bus). + 16 + 8 + write-only + + + TDB3 + 8-bit transmit data (latest byte on I3C bus). + 24 + 8 + write-only + + + + + I3C_IBIDR + I3C_IBIDR + I3C IBI payload data register + 0x20 + 0x20 + 0x00000000 + + + IBIDB0 + 8-bit IBI payload data (earliest byte on I3C bus, i.e. MDB[7:0] mandatory data byte). + 0 + 8 + read-write + + + IBIDB1 + 8-bit IBI payload data (next byte on I3C bus after IBIDB0[7:0]). + 8 + 8 + read-write + + + IBIDB2 + 8-bit IBI payload data (next byte on I3C bus after IBIDB1[7:0]). + 16 + 8 + read-write + + + IBIDB3 + 8-bit IBI payload data (latest byte on I3C bus). + 24 + 8 + read-write + + + + + I3C_TGTTDR + I3C_TGTTDR + I3C slave transmit configuration register + 0x24 + 0x20 + 0x00000000 + + + TGTTDCNT + transmit data counter, in bytes (when I3C is configured as slave) + 0 + 16 + read-write + + + PRELOAD + preload of the TX-FIFO (when I3C is configured as slave) + 16 + 1 + read-write + + + + + I3C_RESET + I3C_RESET + I3C reset register + 0x2C + 0x20 + 0x03000000 + + + HST_SIE_RST + Reset Register of the Master + 24 + 1 + read-write + + + TGT_SIE_RST + Reset Register of the slave + 25 + 1 + read-write + + + + + I3C_STATR + I3C_STATR + I3C status register + 0x30 + 0x20 + 0x00000000 + + + XDCNT + data counter + 0 + 16 + read-only + + + ABT + a private read message is completed/aborted prematurely by the slave (when the I3C is acting as master) + 17 + 1 + read-only + + + DIR + message direction(whatever I3C is acting as master/slave) + 18 + 1 + read-only + + + MID + message identifier/counter of a given frame (when the I3C is acting as master) + 24 + 8 + read-only + + + + + I3C_STATER + I3C_STATER + I3C status error register + 0x34 + 0x20 + 0x00000000 + + + CODERR + protocol error code/type + 0 + 4 + read-only + + + PERR + protocol error + 4 + 1 + read-only + + + STALL + SCL stall error (when the I3C is acting as slave) + 5 + 1 + read-only + + + DOVR + RX-FIFO overrun or TX-FIFO underrun + 6 + 1 + read-only + + + COVR + C-FIFO underrun or S-FIFO overrun (when the I3C is acting as master) + 7 + 1 + read-only + + + ANACK + address not acknowledged (when the I3C is configured as master) + 8 + 1 + read-only + + + DNACK + data not acknowledged (when the I3C is acting as master) + 9 + 1 + read-only + + + DERR + data error (when the I3C is acting as master) + 10 + 1 + read-only + + + + + I3C_RMR + I3C_RMR + I3C received message register + 0x40 + 0x20 + 0x00000000 + + + IBIRDCNT + IBI received payload data count (when the I3C is configured as master) + 0 + 3 + read-only + + + RCODE + received CCC code (when the I3C is configured as slave) + 8 + 8 + read-only + + + RADD + received slave address (when the I3C is configured as master) + 17 + 7 + read-only + + + + + I3C_EVR + I3C_EVR + I3C event register + 0x50 + 0x20 + 0x00000003 + + + CFEF + C-FIFO empty flag (whatever the I3C is acting as master/slave) + 0 + 1 + read-only + + + TXFEF + TX-FIFO empty flag (whatever the I3C is acting as master/slave) + 1 + 1 + read-only + + + CFNFF + C-FIFO not full flag (when the I3C is acting as master) + 2 + 1 + read-only + + + SFNEF + S-FIFO not empty flag (when the I3C is acting as master) + 3 + 1 + read-only + + + TXFNFF + TX-FIFO not full flag (whatever the I3C is acting as master/slave) + 4 + 1 + read-only + + + RXFNEF + RX-FIFO not empty flag (whatever the I3C is acting as master/slave) + 5 + 1 + read-only + + + TXLASTF + last written data byte/word flag (whatever the I3C is acting as master/slave) + 6 + 1 + read-only + + + RXLASTF + last read data byte/word flag (whatever the I3C is acting as master/slave) + 7 + 1 + read-only + + + FCF + frame complete flag (whatever the I3C is acting as master/slave) + 9 + 1 + read-only + + + RXTGTENDF + slave-initiated read end flag (when the I3C is acting as master) + 10 + 1 + read-only + + + ERRF + flag (whatever the I3C is acting as master/slave) + 11 + 1 + read-only + + + IBIF + IBI flag (when the I3C is acting as master) + 15 + 1 + read-only + + + IBIENDF + IBI end flag (when the I3C is acting as slave) + 16 + 1 + read-only + + + CRF + master-role request flag (when the I3C is acting as master) + 17 + 1 + read-only + + + CRUPDF + master-role update flag (when the I3C is acting as slave) + 18 + 1 + read-only + + + HJF + hot-join flag (when the I3C is acting as master) + 19 + 1 + read-only + + + WKPF + wakeup/missed start flag (when the I3C is acting as slave) + 21 + 1 + read-only + + + GETF + get flag (when the I3C is acting as slave) + 22 + 1 + read-only + + + STAF + get status flag (when the I3C is acting as slave) + 23 + 1 + read-only + + + DAUPDF + dynamic address update flag (when the I3C is acting as slave) + 24 + 1 + read-only + + + MWLUPDF + maximum write length update flag (when the I3C is acting as slave) + 25 + 1 + read-only + + + MRLUPDF + maximum read length update flag (when the I3C is acting as slave) + 26 + 1 + read-only + + + RSTF + reset pattern flag (when the I3C is acting as slave) + 27 + 1 + read-only + + + ASUPDF + activity state update flag (when the I3C is acting as slave) + 28 + 1 + read-only + + + INTUPDF + interrupt/master-role/hot-join update flag (when the I3C is acting as slave) + 29 + 1 + read-only + + + DEFF + DEFTGTS flag (when the I3C is acting as slave) + 30 + 1 + read-only + + + GRPF + group addressing flag (when the I3C is acting as slave) + 31 + 1 + read-only + + + + + I3C_INTENR + I3C_INTENR + I3C interrupt enable register + 0x54 + 0x20 + 0x00000000 + + + CFNFIE + C-FIFO not full interrupt enable (whatever the I3C is acting as master/slave) + 2 + 1 + read-only + + + SFNEIE + S-FIFO not empty interrupt enable (whatever the I3C is acting as master/slave) + 3 + 1 + read-only + + + TXFNFIE + TX-FIFO not full interrupt enable (whatever the I3C is acting as master/slave) + 4 + 1 + read-only + + + RXFNEIE + RX-FIFO not empty interrupt enable (whatever the I3C is acting as master/slave) + 5 + 1 + read-only + + + FCIE + frame complete interrupt enable (whatever the I3C is acting as master/slave) + 9 + 1 + read-only + + + RXTGTENDIE + slave-initiated read end interrupt enable (when the I3C is acting as master) + 10 + 1 + read-only + + + ERRIE + error interrupt enable (whatever the I3C is acting as master/slave) + 11 + 1 + read-only + + + IBIIE + IBI request interrupt enable (when the I3C is acting as master) + 15 + 1 + read-only + + + IBIENDIE + IBI end interrupt enable (when the I3C is acting as slave) + 16 + 1 + read-only + + + CRIE + master-role request interrupt enable (when the I3C is acting as master) + 17 + 1 + read-only + + + CRUPDIE + master-role update interrupt enable (when the I3C is acting as slave) + 18 + 1 + read-only + + + HJIE + hot-join interrupt enable (when the I3C is acting as master) + 19 + 1 + read-only + + + WKPIE + wakeup interrupt enable (when the I3C is acting as slave) + 21 + 1 + read-only + + + GETIE + GETxxx CCC interrupt enable (when the I3C is acting as slave) + 22 + 1 + read-only + + + STAIE + GETSTATUS CCC interrupt enable (when the I3C is acting as slave) + 23 + 1 + read-only + + + DAUPDIE + ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable (when the I3C is acting as slave) + 24 + 1 + read-only + + + MWLUPDIE + SETMWL CCC interrupt enable (when the I3C is acting as slave) + 25 + 1 + read-only + + + MRLUPDIE + SETMRL CCC interrupt enable (when the I3C is acting as slave) + 26 + 1 + read-only + + + RSTIE + reset pattern interrupt enable (when the I3C is acting as slave) + 27 + 1 + read-only + + + ASUPDIE + ENTASx CCC interrupt enable (when the I3C is acting as slave) + 28 + 1 + read-only + + + INTUPDIE + ENEC/DISEC CCC interrupt enable (when the I3C is acting as slave) + 29 + 1 + read-only + + + DEFIE + DEFTGTS CCC interrupt enable (when the I3C is acting as slave) + 30 + 1 + read-only + + + GRPIE + DEFGRPA CCC interrupt enable (when the I3C is acting as slave) + 31 + 1 + read-only + + + + + I3C_CEVR + I3C_CEVR + I3C clear event register + 0x58 + 0x20 + 0x00000000 + + + CFCF + clear frame complete flag (whatever the I3C is acting as master/slave) + 9 + 1 + write-only + + + CRXTGTENDF + clear slave-initiated read end flag (when the I3C is acting as master) + 10 + 1 + write-only + + + CERRF + clear error flag (whatever the I3C is acting as master/slave) + 11 + 1 + write-only + + + CIBIF + clear IBI request flag (when the I3C is acting as master) + 15 + 1 + write-only + + + CIBIENDF + clear IBI end flag (when the I3C is acting as slave) + 16 + 1 + write-only + + + CCRF + clear master-role request flag (when the I3C is acting as master) + 17 + 1 + write-only + + + CCRUPDF + clear master-role update flag (when the I3C is acting as slave) + 18 + 1 + write-only + + + CHJF + clear hot-join flag (when the I3C is acting as master) + 19 + 1 + write-only + + + CWKPF + clear wakeup flag (when the I3C is acting as slave) + 21 + 1 + write-only + + + CGETF + clear GETxxx CCC flag (when the I3C is acting as slave) + 22 + 1 + write-only + + + CSTAF + clear GETSTATUS CCC flag (when the I3C is acting as slave) + 23 + 1 + write-only + + + CDAUPDF + clear ENTDAA/RSTDAA/SETNEWDA CCC flag (when the I3C is acting as slave) + 24 + 1 + write-only + + + CMWLUPDF + clear SETMWL CCC flag (when the I3C is acting as slave) + 25 + 1 + write-only + + + CMRLUPDF + clear SETMRL CCC flag (when the I3C is acting as slave) + 26 + 1 + write-only + + + CRSTF + clear reset pattern flag (when the I3C is acting as slave) + 27 + 1 + write-only + + + CASUPDF + clear ENTASx CCC flag (when the I3C is acting as slave) + 28 + 1 + write-only + + + CINTUPDF + clear ENEC/DISEC CCC flag (when the I3C is acting as slave) + 29 + 1 + write-only + + + CDEFF + clear DEFTGTS CCC flag (when the I3C is acting as slave) + 30 + 1 + write-only + + + CGRPF + clear DEFGRPA CCC flag (when the I3C is acting as slave) + 31 + 1 + write-only + + + + + I3C_DEVR0 + I3C_DEVR0 + I3C own device characteristics register + 0x60 + 0x20 + 0x00000000 + + + DAVAL + dynamic address is valid (when the I3C is acting as slave) + 0 + 1 + read-write + + + DA + 7-bit dynamic address + 1 + 7 + read-write + + + IBIEN + IBI request enable (when the I3C is acting as slave) + 16 + 1 + read-write + + + CREN + master-role request enable (when the I3C is acting as slave) + 17 + 1 + read-write + + + HJEN + hot-join request enable (when the I3C is acting as slave) + 19 + 1 + read-write + + + AS + activity state (when the I3C is acting as slave) + 20 + 2 + read-only + + + RSTACT + reset action/level on received reset pattern (when the I3C is acting as slave) + 22 + 2 + read-only + + + RSTVAL + reset action is valid (when the I3C is acting as slave) + 24 + 1 + read-only + + + + + I3C_DEVR1 + I3C_DEVR1 + I3C device 1 characteristics register + 0x64 + 0x20 + 0x00000000 + + + DA + assigned I3C dynamic address to slave x (when the I3C is acting as master) + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C is acting as master) + 16 + 1 + read-write + + + CRACK + master-role request acknowledge (when the I3C is acting as master) + 17 + 1 + read-write + + + IBIDEN + IBI data enable (when the I3C is acting as master) + 18 + 1 + read-write + + + SUSP + suspend/stop I3C transfer on received IBI (when the I3C is acting as master) + 19 + 1 + read-write + + + DIS + DA[6:0] write disabled (when the I3C is acting as master) + 31 + 1 + read-only + + + + + I3C_DEVR2 + I3C_DEVR2 + I3C device 2 characteristics register + 0x68 + 0x20 + 0x00000000 + + + DA + assigned I3C dynamic address to slave x (when the I3C is acting as master) + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C is acting as master) + 16 + 1 + read-write + + + CRACK + master-role request acknowledge (when the I3C is acting as master) + 17 + 1 + read-write + + + IBIDEN + IBI data enable (when the I3C is acting as master) + 18 + 1 + read-write + + + SUSP + suspend/stop I3C transfer on received IBI (when the I3C is acting as master) + 19 + 1 + read-write + + + DIS + DA[6:0] write disabled (when the I3C is acting as master) + 31 + 1 + read-only + + + + + I3C_DEVR3 + I3C_DEVR3 + I3C device 3 characteristics register + 0x6c + 0x20 + 0x00000000 + + + DA + assigned I3C dynamic address to slave x (when the I3C is acting as master) + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C is acting as master) + 16 + 1 + read-write + + + CRACK + master-role request acknowledge (when the I3C is acting as master) + 17 + 1 + read-write + + + IBIDEN + IBI data enable (when the I3C is acting as master) + 18 + 1 + read-write + + + SUSP + suspend/stop I3C transfer on received IBI (when the I3C is acting as master) + 19 + 1 + read-write + + + DIS + DA[6:0] write disabled (when the I3C is acting as master) + 31 + 1 + read-only + + + + + I3C_DEVR4 + I3C_DEVR4 + I3C device 4 characteristics register + 0x70 + 0x20 + 0x00000000 + + + DA + assigned I3C dynamic address to slave x (when the I3C is acting as master) + 1 + 7 + read-write + + + IBIACK + IBI request acknowledge (when the I3C is acting as master) + 16 + 1 + read-write + + + CRACK + master-role request acknowledge (when the I3C is acting as master) + 17 + 1 + read-write + + + IBIDEN + IBI data enable (when the I3C is acting as master) + 18 + 1 + read-write + + + SUSP + suspend/stop I3C transfer on received IBI (when the I3C is acting as master) + 19 + 1 + read-write + + + DIS + DA[6:0] write disabled (when the I3C is acting as master) + 31 + 1 + read-only + + + + + I3C_MAXRLR + I3C_MAXRLR + I3C maximum read length register + 0x90 + 0x20 + 0x00000000 + + + MRL + maximum data read length (when I3C is acting as slave) + 0 + 16 + read-write + + + IBIP + IBI payload data size, in bytes (when I3C is acting as slave) + 16 + 3 + read-write + + + + + I3C_MAXWLR + I3C_MAXWLR + I3C maximum write length register + 0x94 + 0x20 + 0x00000000 + + + MWL + maximum data write length (when I3C is acting as slave) + 0 + 16 + read-write + + + + + I3C_TIMINGR0 + I3C_TIMINGR0 + I3C timing register 0 + 0xA0 + 0x20 + 0x00000000 + + + SCLL_PP + SCL low duration in I3C push-pull phases, in number of kernel clocks cycles + 0 + 8 + read-write + + + SCLH_I3C + SCL high duration, used for I3C messages (both in push-pull and open-drain phases), in number of kernel clocks cycles + 8 + 8 + read-write + + + SCLL_OD + SCL low duration in open-drain phases, used for legacy I2C commands and for I3C open-drain phases (address header phase following a START, not a Repeated START), in number of kernel clocks cycles + 16 + 8 + read-write + + + SCLH_I2C + SCL high duration, used for legacy I2C commands, in number of kernel clocks cycles + 24 + 8 + read-write + + + + + I3C_TIMINGR1 + I3C_TIMINGR1 + I3C timing register 1 + 0xA4 + 0x20 + 0x00000000 + + + AVAL + number of kernel clock cycles, that is used whatever I3C is acting as controller or slave, to set the following MIPI I3C timings, like bus available condition time: +When the I3C is acting as slave + 0 + 8 + read-write + + + ASNCR + activity state of the new master (when I3C is acting as active- master) + 8 + 2 + read-write + + + FREE + number of kernel clocks cycles that is used to set some MIPI timings like bus free condition time (when the I3C is acting as master) + 16 + 7 + read-write + + + SDA_HD + SDA hold time (when the I3C is acting as master), in number of kernel clocks cycles (refer to MIPI timing SDA hold time in push-pull tHD_PP): + 28 + 1 + read-write + + + + + I3C_TIMINGR2 + I3C_TIMINGR2 + I3C timing register 2 + 0xa8 + 0x20 + 0x00000000 + + + STALLT + master clock stall on T-bit phase of Data enable + 0 + 1 + read-write + + + STALLD + master clock stall on PAR phase of Data enable + 1 + 1 + read-write + + + STALLC + master clock stall on PAR phase of CCC enable + 2 + 1 + read-write + + + STALLA + master clock stall enable on ACK phase + 3 + 1 + read-write + + + STALL + master clock stall time, in number of kernel clock cycles + 8 + 8 + read-write + + + + + I3C_BCR + I3C_BCR + I3C bus characteristics register + 0xc0 + 0x20 + 0x00000000 + + + BCR0 + max data speed limitation + 0 + 1 + read-write + + + BCR2 + in-band interrupt (IBI) payload + 2 + 1 + read-write + + + BCR6 + master capable + 6 + 1 + read-write + + + + + I3C_DCR + I3C_DCR + I3C device characteristics register + 0xc4 + 0x20 + 0x00000000 + + + DCR + device characteristics ID + 0 + 8 + read-write + + + + + I3C_GETCAPR + I3C_GETCAPR + I3C get capability register + 0xc8 + 0x20 + 0x00000000 + + + CAPPEND + IBI MDB support for pending read notification + 14 + 1 + read-write + + + + + I3C_CRCAPR + I3C_CRCAPR + I3C master-role capability register + 0xcc + 0x20 + 0x00000000 + + + CAPDHOFF + delayed master-role hand-off + 3 + 1 + read-write + + + CAPGRP + group management support (when acting as master) + 9 + 1 + read-write + + + + + I3C_GETMDSR + I3C_GETMDSR + I3C get capability register + 0xD0 + 0x20 + 0x00000000 + + + HOFFAS + master hand-off activity state + 0 + 2 + read-write + + + FMT + GETMXDS CCC format + 8 + 2 + read-write + + + RDTURN + programmed byte of the 3-byte MaxRdTurn (maximum read turnaround byte) + 16 + 8 + read-write + + + TSCO + clock-to-data turnaround time (tSCO) + 24 + 1 + read-write + + + + + I3C_EPIDR + I3C_EPIDR + I3C extended provisioned ID register + 0xd4 + 0x20 + 0x02080000 + + + MIPIID + 4-bit MIPI Instance ID + 12 + 4 + read-write + + + IDTSEL + provisioned ID type selector + 16 + 1 + read-only + + + MIPIMID + 15-bit MIPI manufacturer ID + 17 + 15 + read-only + + + + + + + + HSADC + High speed ADC + HSADC + 0x40017400 + + 0x00 + 0x400 + registers + + + HSADC + HSADC global interrupt + 144 + + + + CFGR + CFGR + High-speed ADC configuration register + 0x00 + 0x20 + 0x00002400 + + + EN + High-speed ADC enable + 0 + 1 + read-write + + + DMAEN + Direct Storage Access (DMA) mode enable + 2 + 3 + read-write + + + SETUP + First Transition Establishment Time Configuration Bit + 8 + 6 + read-write + + + PPMODE + Ping Pong storage mode enable + 14 + 1 + read-write + + + BURST_EN + DMA transmission length configuration bit + 15 + 1 + read-write + + + DMA_LEN + DMA transmission length configuration bit + 16 + 16 + read-write + + + + + CTLR1 + CTLR1 + HSADC Control Register 1 + 0x04 + 0x20 + 0x00000000 + + + START + Initiating High-Speed ADC Conversion + 0 + 1 + write-only + + + BURST_END + Abort a burst transmission + 1 + 1 + read-write + + + EOCIE + Transition Completion Interrupt Enables + 8 + 1 + read-write + + + DMAIE + Transition Completion Interrupt Enables + 9 + 1 + read-write + + + BURSTIE + Interrupt enables when the burst transmission is complete + 10 + 1 + read-write + + + + + CTLR2 + CTLR2 + HSADC Control Register 2 + 0x08 + 0x20 + 0x00000000 + + + BURST_LEN + Burst transmission length configuration + 16 + 16 + read-write + + + BURST_DMA_LEN + The final DMA transmission length configuration bit for burst transmission. + If the number of data transmitted in the final burst is not aligned with the DMA transmission length, + the DMA transmission length is configured + 0 + 16 + read-write + + + + + STATR + STATR + HSADC Status Register + 0x0C + 0x20 + 0x00000100 + + + EOCIF + Transition Complete Interrupt flag + 0 + 1 + read-write + + + DMAIF + DMA Transmission Complete Interrupt flag + 1 + 1 + read-write + + + BURSTIF + Burst transfer completed interrupt flag + 2 + 1 + read-write + + + RXNE + The data register is not empty flag, that is, the conversion is completed + and the data is stored in the data register, which is the position bit; + A read operation on the data register clears the bit + 3 + 1 + read-only + + + PP_ADDR + Ping-pong storage mode cache address indicator bit + 4 + 1 + read-only + + + FIFO_RDY + Receives a FIFO non-null status flag + 8 + 1 + read-only + + + FIFO_FULL + Receive FIFO full status flags + 9 + 1 + read-only + + + FIFO_OV + Receives the FIFO overflow status flag + 10 + 1 + read-only + + + FIFO_CNT + Receives the FIFO current count value + 11 + 3 + read-only + + + + + DATAR + DATAR + HSADC Data Register + 0x10 + 0x20 + 0x00000000 + + + DR + Convert data register + 0 + 10 + read-write + + + + + ADDR0 + ADDR0 + HSADC DMA Receive Address Register 0 + 0x14 + 0x20 + 0x00000000 + + + DMA_ADDR0 + The DMA transmission address is configured with the 0 configuration bit + 0 + 32 + read-write + + + + + ADDR1 + ADDR1 + HSADC DMA Receive Address Register 1 + 0x18 + 0x20 + 0x00000000 + + + DMA_ADDR1 + DMA transport address 1 configuration bit + 0 + 32 + read-write + + + + + + + + EXTI + EXTI + EXTI + 0x40010400 + + 0x00 + 0x400 + registers + + + EXTI7_0 + EXTI Line[7:0] interrupt + 36 + + + EXTI15_8 + EXTI Line[15:8] interrupts + 33 + + + + INTENR + INTENR + Interrupt mask register + (EXTI_INTENR) + 0x00 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + MR20 + Interrupt Mask on line 20 + 20 + 1 + + + MR21 + Interrupt Mask on line 21 + 21 + 1 + + + MR22 + Interrupt Mask on line 22 + 22 + 1 + + + MR23 + Interrupt Mask on line 23 + 23 + 1 + + + MR24 + Interrupt Mask on line 24 + 24 + 1 + + + MR25 + Interrupt Mask on line 25 + 25 + 1 + + + MR26 + Interrupt Mask on line 26 + 26 + 1 + + + + + EVENR + EVENR + Event mask register (EXTI_EVENR) + 0x04 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR19 + Event Mask on line 19 + 19 + 1 + + + MR20 + Event Mask on line 20 + 20 + 1 + + + MR21 + Event Mask on line 21 + 21 + 1 + + + MR22 + Event Mask on line 22 + 22 + 1 + + + MR23 + Event Mask on line 23 + 23 + 1 + + + MR24 + Event Mask on line 24 + 24 + 1 + + + MR25 + Event Mask on line 25 + 25 + 1 + + + MR26 + Event Mask on line 26 + 26 + 1 + + + + + RTENR + RTENR + Rising Trigger selection register + (EXTI_RTENR) + 0x08 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + TR19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + TR20 + Rising trigger event configuration of + line 20 + 20 + 1 + + + TR21 + Rising trigger event configuration of + line 21 + 21 + 1 + + + TR22 + Rising trigger event configuration of + line 22 + 22 + 1 + + + TR23 + Rising trigger event configuration of + line 23 + 23 + 1 + + + TR24 + Rising trigger event configuration of + line 24 + 24 + 1 + + + TR25 + Rising trigger event configuration of + line 25 + 25 + 1 + + + TR26 + Rising trigger event configuration of + line 26 + 26 + 1 + + + + + FTENR + FTENR + Falling Trigger selection register + (EXTI_FTENR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + TR19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + TR20 + Falling trigger event configuration of + line 20 + 20 + 1 + + + TR21 + Falling trigger event configuration of + line 21 + 21 + 1 + + + TR22 + Falling trigger event configuration of + line 22 + 22 + 1 + + + TR23 + Falling trigger event configuration of + line 23 + 23 + 1 + + + TR24 + Falling trigger event configuration of + line 24 + 24 + 1 + + + TR25 + Falling trigger event configuration of + line 25 + 25 + 1 + + + TR26 + Falling trigger event configuration of + line 26 + 26 + 1 + + + + + SWIEVR + SWIEVR + Software interrupt event register + (EXTI_SWIEVR) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIER19 + Software Interrupt on line + 19 + 19 + 1 + + + SWIER20 + Software Interrupt on line + 20 + 20 + 1 + + + SWIER21 + Software Interrupt on line + 21 + 21 + 1 + + + SWIER22 + Software Interrupt on line + 22 + 22 + 1 + + + SWIER23 + Software Interrupt on line + 23 + 23 + 1 + + + SWIER24 + Software Interrupt on line + 24 + 24 + 1 + + + SWIER25 + Software Interrupt on line + 25 + 25 + 1 + + + SWIER26 + Software Interrupt on line + 26 + 26 + 1 + + + + + INTFR + INTFR + interrupt flag register (EXTI_INTFR) + 0x14 + 0x20 + read-write + 0x00000000 + + + IF0 + interrupt flag bit 0 + 0 + 1 + + + IF1 + interrupt flag bit 1 + 1 + 1 + + + IF2 + interrupt flag bit 2 + 2 + 1 + + + IF3 + interrupt flag bit 3 + 3 + 1 + + + IF4 + interrupt flag bit 4 + 4 + 1 + + + IF5 + interrupt flag bit 5 + 5 + 1 + + + IF6 + interrupt flag bit 6 + 6 + 1 + + + IF7 + interrupt flag bit 7 + 7 + 1 + + + IF8 + interrupt flag bit 8 + 8 + 1 + + + IF9 + interrupt flag bit 9 + 9 + 1 + + + IF10 + interrupt flag bit 10 + 10 + 1 + + + IF11 + interrupt flag bit 11 + 11 + 1 + + + IF12 + interrupt flag bit 12 + 12 + 1 + + + IF13 + interrupt flag bit 13 + 13 + 1 + + + IF14 + interrupt flag bit 14 + 14 + 1 + + + IF15 + interrupt flag bit 15 + 15 + 1 + + + IF16 + interrupt flag bit 16 + 16 + 1 + + + IF17 + interrupt flag bit 17 + 17 + 1 + + + IF19 + interrupt flag bit 19 + 19 + 1 + + + IF20 + interrupt flag bit 20 + 20 + 1 + + + IF21 + interrupt flag bit 21 + 21 + 1 + + + IF22 + interrupt flag bit 22 + 22 + 1 + + + IF23 + interrupt flag bit 23 + 23 + 1 + + + IF24 + interrupt flag bit 24 + 24 + 1 + + + IF25 + interrupt flag bit 25 + 25 + 1 + + + IF26 + interrupt flag bit 26 + 26 + 1 + + + + + + + + OPA + OPA configuration + OPA + 0x40017800 + + 0x00 + 0x400 + registers + + + + OPA_CTLR1 + CTLR1 + OPA Control Register 1 + 0x00 + 0x20 + 0x00000076 + + + EN1 + OPA1 enable + 0 + 1 + read-write + + + MODE1 + OPA1 Output Channel Selection + 1 + 2 + read-write + + + PSEL1 + OPA1 Positive Channel Selection + 3 + 1 + read-write + + + NSEL1 + OPA1 Negative Channel Selection vs. PGA Gain Selection + 4 + 3 + read-write + + + FB_EN1 + OPA1's PGA mode feedback enable + 8 + 1 + read-write + + + PGADIF1 + OPA1 is used with NSEL1 as PGA and the N-terminal is connected to OPA1_CHN1 (PA7) + 9 + 1 + read-write + + + HS1 + OPA1 high-speed mode enables + 10 + 1 + read-write + + + + + OPA_CTLR2 + CTLR2 + OPA Control Register 2 + 0x04 + 0x20 + 0x00000070 + + + EN2 + OPA2 enable + 0 + 1 + read-write + + + MODE2 + OPA2 Output Channel Selection + 1 + 2 + read-write + + + PSEL2 + OPA2 Positive Channel Selection + 3 + 1 + read-write + + + NSEL2 + OPA2 Negative Channel Selection vs. PGA Gain Selection + 4 + 3 + read-write + + + FB_EN2 + OPA2's PGA mode feedback enable + 8 + 1 + read-write + + + PGADIF1 + OPA2 is used with NSEL1 as PGA and the N-terminal is connected to OPA2_CHN1 (PA7) + 9 + 1 + read-write + + + HS2 + OPA2 high-speed mode enables + 10 + 1 + read-write + + + + + OPA_CTLR3 + CTLR3 + OPA Control Register 3 + 0x08 + 0x20 + 0x00000070 + + + EN3 + OPA3 enable + 0 + 1 + read-write + + + MODE3 + OPA3 Output Channel Selection + 1 + 2 + read-write + + + PSEL3 + OPA3 Positive Channel Selection + 3 + 1 + read-write + + + NSEL3 + OPA3 Negative Channel Selection vs. PGA Gain Selection + 4 + 3 + read-write + + + FB_EN3 + OPA3's PGA mode feedback enable + 8 + 1 + read-write + + + PGADIF3 + OPA3 is used with NSEL1 as PGA and the N-terminal is connected to OPA3_CHN1 (PA7) + 9 + 1 + read-write + + + HS3 + OPA3 high-speed mode enables + 10 + 1 + read-write + + + + + CMP_CTLR + CMP_CTLR + CMP Control Registers + 0x0C + 0x20 + 0x000000FF + + + PSEL + CMP Positive Channel Selection Bits + 0 + 2 + read-write + + + NSEL + CMP Negative End Channel Selection Bits + 2 + 2 + read-write + + + MODE + CMP Output Channel Selection + 4 + 4 + read-write + + + EN + CMP enables + 8 + 1 + read-write + + + HYPSEL + CMP hysteresis voltage selector + 9 + 2 + read-write + + + VREF + CMP Internal Bias Voltage Selector + 11 + 2 + read-write + + + FILT_EN + CMP Digital Filtering Enable + 13 + 1 + read-write + + + FILT_CFG + CMP filter sampling interval configuration + 16 + 9 + read-write + + + FILT_BASE + CMP filtering sampling time base configuration + 28 + 3 + read-write + + + + + CMP_STATR + CMP_STATR + CMP Status Registers + 0x10 + 0x20 + 0x00000000 + + + OUT_FILT + CMP Output + 0 + 1 + read-only + + + + + + + + LTDC + LCD-TFT Controller + LTDC + 0x40014800 + + 0x0 + 0x400 + registers + + + LTDC + LCD-TFT global interrupt + 124 + + + + SSCR + SSCR + Synchronization Size Configuration + Register + 0x0 + 0x20 + read-write + 0x00000000 + + + HSW + Horizontal Synchronization Width (in + units of pixel clock period) + 16 + 12 + + + VSH + Vertical Synchronization Height (in + units of horizontal scan line) + 0 + 11 + + + + + BPCR + BPCR + Back Porch Configuration + Register + 0x4 + 0x20 + read-write + 0x00000000 + + + AHBP + Accumulated Horizontal back porch (in + units of pixel clock period) + 16 + 12 + + + AVBP + Accumulated Vertical back porch (in + units of horizontal scan line) + 0 + 11 + + + + + AWCR + AWCR + Active Width Configuration + Register + 0x8 + 0x20 + read-write + 0x00000000 + + + AAW + Accumulated Active Width (in + units of pixel clock period) + 16 + 12 + + + AAH + Accumulated Active Height (in units of + horizontal scan line) + 0 + 11 + + + + + TWCR + TWCR + Total Width Configuration + Register + 0x0C + 0x20 + read-write + 0x00000000 + + + TOTALW + Total Width (in units of pixel clock + period) + 16 + 12 + + + TOTALH + Total Height (in units of horizontal + scan line) + 0 + 11 + + + + + GCR + GCR + Global Control Register + 0x10 + 0x20 + 0x00002220 + + + HSPOL + Horizontal Synchronization + Polarity + 31 + 1 + read-write + + + VSPOL + Vertical Synchronization + Polarity + 30 + 1 + read-write + + + DEPOL + Data Enable Polarity + 29 + 1 + read-write + + + PCPOL + Pixel Clock Polarity + 28 + 1 + read-write + + + DEN + Dither Enable + 16 + 1 + read-write + + + DRW + Dither Red Width + 12 + 3 + read-only + + + DGW + Dither Green Width + 8 + 3 + read-only + + + DBW + Dither Blue Width + 4 + 3 + read-only + + + LTDCEN + LCD-TFT controller enable + bit + 0 + 1 + read-write + + + + + SRCR + SRCR + Shadow Reload Configuration + Register + 0x14 + 0x20 + read-write + 0x00000000 + + + VBR + Vertical Blanking Reload + 1 + 1 + + + IMR + Immediate Reload + 0 + 1 + + + + + BCCR + BCCR + Background Color Configuration + Register + 0x18 + 0x20 + read-write + 0x00000000 + + + BCBLUE + Background Color Blue + value + 0 + 8 + + + BCGREEN + Background Color Green + value + 8 + 8 + + + BCRED + Background Color Red value + 16 + 8 + + + + + IER + IER + Interrupt Enable Register + 0x1C + 0x20 + read-write + 0x00000000 + + + RRIE + Register Reload interrupt + enable + 3 + 1 + + + FUIE + FIFO Underrun Interrupt + Enable + 1 + 1 + + + LIE + Line Interrupt Enable + 0 + 1 + + + + + ISR + ISR + Interrupt Status Register + 0x20 + 0x20 + read-only + 0x00000000 + + + RRIF + Register Reload Interrupt + Flag + 3 + 1 + + + FUIF + FIFO Underrun Interrupt + flag + 1 + 1 + + + LIF + Line Interrupt flag + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x24 + 0x20 + write-only + 0x00000000 + + + CRRIF + Clears Register Reload Interrupt + Flag + 3 + 1 + + + CFUIF + Clears the FIFO Underrun Interrupt + flag + 1 + 1 + + + CLIF + Clears the Line Interrupt + Flag + 0 + 1 + + + + + LIPCR + LIPCR + Line Interrupt Position Configuration + Register + 0x28 + 0x20 + read-write + 0x00000000 + + + LIPOS + Line Interrupt Position + 0 + 11 + + + + + CPSR + CPSR + Current Position Status + Register + 0x2C + 0x20 + read-write + 0x00000000 + + + CXPOS + Current X Position + 16 + 16 + + + CYPOS + Current Y Position + 0 + 16 + + + + + CDSR + CDSR + Current Display Status + Register + 0x30 + 0x20 + read-only + 0x0000000F + + + HSYNCS + Horizontal Synchronization display + Status + 3 + 1 + + + VSYNCS + Vertical Synchronization display + Status + 2 + 1 + + + HDES + Horizontal Data Enable display + Status + 1 + 1 + + + VDES + Vertical Data Enable display + Status + 0 + 1 + + + + + L1CR + L1CR + Layerx Control Register + 0x34 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + + COLKEN + Color Keying Enable + 1 + 1 + + + LEN + Layer Enable + 0 + 1 + + + + + L1WHPCR + L1WHPCR + Layerx Window Horizontal Position + Configuration Register + 0x38 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop + Position + 16 + 12 + + + WHSTPOS + Window Horizontal Start + Position + 0 + 12 + + + + + L1WVPCR + L1WVPCR + Layerx Window Vertical Position + Configuration Register + 0x3C + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop + Position + 16 + 11 + + + WVSTPOS + Window Vertical Start + Position + 0 + 11 + + + + + L1CKCR + L1CKCR + Layerx Color Keying Configuration + Register + 0x40 + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + CKGREEN + Color Key Green value + 8 + 8 + + + CKBLUE + Color Key Blue value + 0 + 8 + + + + + L1PFCR + L1PFCR + Layerx Pixel Format Configuration + Register + 0x44 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + + + + L1CACR + L1CACR + Layerx Constant Alpha Configuration + Register + 0x48 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + + + L1DCCR + L1DCCR + Layerx Default Color Configuration + Register + 0x4C + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + DCRED + Default Color Red + 16 + 8 + + + DCGREEN + Default Color Green + 8 + 8 + + + DCBLUE + Default Color Blue + 0 + 8 + + + + + L1BFCR + L1BFCR + Layerx Blending Factors Configuration + Register + 0x50 + 0x20 + read-write + 0x00000600 + + + BF1 + Blending Factor 1 + 8 + 3 + + + BF2 + Blending Factor 2 + 0 + 3 + + + + + L1CFBAR + L1CFBAR + Layerx Color Frame Buffer Address + Register + 0x54 + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start + Address + 0 + 32 + + + + + L1CFBLR + L1CFBLR + Layerx Color Frame Buffer Length + Register + 0x58 + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in + bytes + 16 + 13 + + + CFBLL + Color Frame Buffer Line + Length + 0 + 13 + + + + + L1CFBLNR + L1CFBLNR + Layerx ColorFrame Buffer Line Number + Register + 0x5C + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + + + L1CLUTWR + L1CLUTWR + Layerx CLUT Write Register + 0x60 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + RED + Red value + 16 + 8 + + + GREEN + Green value + 8 + 8 + + + BLUE + Blue value + 0 + 8 + + + + + L2CR + L2CR + Layerx Control Register + 0x64 + 0x20 + read-write + 0x00000000 + + + CLUTEN + Color Look-Up Table Enable + 4 + 1 + + + COLKEN + Color Keying Enable + 1 + 1 + + + LEN + Layer Enable + 0 + 1 + + + + + L2WHPCR + L2WHPCR + Layerx Window Horizontal Position + Configuration Register + 0x68 + 0x20 + read-write + 0x00000000 + + + WHSPPOS + Window Horizontal Stop + Position + 16 + 12 + + + WHSTPOS + Window Horizontal Start + Position + 0 + 12 + + + + + L2WVPCR + L2WVPCR + Layerx Window Vertical Position + Configuration Register + 0x6C + 0x20 + read-write + 0x00000000 + + + WVSPPOS + Window Vertical Stop + Position + 16 + 11 + + + WVSTPOS + Window Vertical Start + Position + 0 + 11 + + + + + L2CKCR + L2CKCR + Layerx Color Keying Configuration + Register + 0x70 + 0x20 + read-write + 0x00000000 + + + CKRED + Color Key Red value + 16 + 8 + + + CKGREEN + Color Key Green value + 8 + 8 + + + CKBLUE + Color Key Blue value + 0 + 8 + + + + + L2PFCR + L2PFCR + Layerx Pixel Format Configuration + Register + 0x74 + 0x20 + read-write + 0x00000000 + + + PF + Pixel Format + 0 + 3 + + + + + L2CACR + L2CACR + Layerx Constant Alpha Configuration + Register + 0x78 + 0x20 + read-write + 0x00000000 + + + CONSTA + Constant Alpha + 0 + 8 + + + + + L2DCCR + L2DCCR + Layerx Default Color Configuration + Register + 0x7C + 0x20 + read-write + 0x00000000 + + + DCALPHA + Default Color Alpha + 24 + 8 + + + DCRED + Default Color Red + 16 + 8 + + + DCGREEN + Default Color Green + 8 + 8 + + + DCBLUE + Default Color Blue + 0 + 8 + + + + + L2BFCR + L2BFCR + Layerx Blending Factors Configuration + Register + 0x80 + 0x20 + read-write + 0x00000600 + + + BF1 + Blending Factor 1 + 8 + 3 + + + BF2 + Blending Factor 2 + 0 + 3 + + + + + L2CFBAR + L2CFBAR + Layerx Color Frame Buffer Address + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CFBADD + Color Frame Buffer Start + Address + 0 + 32 + + + + + L2CFBLR + L2CFBLR + Layerx Color Frame Buffer Length + Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CFBP + Color Frame Buffer Pitch in + bytes + 16 + 13 + + + CFBLL + Color Frame Buffer Line + Length + 0 + 13 + + + + + L2CFBLNR + L2CFBLNR + Layerx ColorFrame Buffer Line Number + Register + 0x8C + 0x20 + read-write + 0x00000000 + + + CFBLNBR + Frame Buffer Line Number + 0 + 11 + + + + + L2CLUTWR + L2CLUTWR + Layerx CLUT Write Register + 0x90 + 0x20 + write-only + 0x00000000 + + + CLUTADD + CLUT Address + 24 + 8 + + + RED + Red value + 16 + 8 + + + GREEN + Green value + 8 + 8 + + + BLUE + Blue value + 0 + 8 + + + + + + + + GPHA + GPHA + GPHA + 0x40016800 + + 0x0 + 0x400 + registers + + + GPHA + GPHA global interrupt + 125 + + + + CTLR + CTLR + GPHA control register + 0x0 + 0x20 + read-write + 0x00000000 + + + START + Start This bit can be used to launch the + GPHA according to the parameters loaded in the + various configuration registers + 0 + 1 + + + SUSP + Suspend This bit can be used to suspend + the current transfer. + 1 + 1 + + + ABORT + Abort This bit can be used to abort the + current transfer. + 2 + 1 + + + TCIE + Transfer complete interrupt enable + 9 + 1 + + + TWIE + Transfer watermark interrupt enable + 10 + 1 + + + CAEIE + CLUT access error interrupt enable + 11 + 1 + + + CTCIE + CLUT transfer complete interrupt enable + 12 + 1 + + + CEIE + Configuration Error Interrupt Enable + 13 + 1 + + + MODE + GPHA mode + 16 + 2 + + + + + ISR + ISR + GPHA Interrupt Status + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + TCIF + Transfer complete interrupt flag + 1 + 1 + + + TWIF + Transfer watermark interrupt flag + 2 + 1 + + + CAEIF + CLUT access error interrupt flag + 3 + 1 + + + CTCIF + CLUT transfer complete interrupt flag + 4 + 1 + + + CEIF + Configuration error interrupt flag + 5 + 1 + + + + + IFCR + IFCR + GPHA interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTCIF + Clear transfer complete interrupt flag + Programming + 1 + 1 + + + CTWIF + Clear transfer watermark interrupt flag + Programming + 2 + 1 + + + CAECIF + Clear CLUT access error interrupt flag + Programming + 3 + 1 + + + CCTCIF + Clear CLUT transfer complete interrupt + flag Programming + 4 + 1 + + + CCEIF + Clear configuration error interrupt flag + Programming + 5 + 1 + + + + + FGMAR + FGMAR + GPHA foreground memory address + register + 0xC + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the foreground image. + 0 + 32 + + + + + FGOR + FGOR + GPHA foreground offset + register + 0x10 + 0x20 + read-write + 0x00000000 + + + LO + Line offset Line offset used for the + foreground expressed in pixel + 0 + 14 + + + + + BGMAR + BGMAR + GPHA background memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the background image + 0 + 32 + + + + + BGOR + BGOR + GPHA background offset + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LO + Line offset Line offset used for the + background image (expressed in pixel) + 0 + 14 + + + + + FGPFCCR + FGPFCCR + GPHA foreground PFC control + register + 0x1C + 0x20 + read-write + 0x00000000 + + + CM + Color mode + 0 + 4 + + + CCM + CLUT color mode + 4 + 1 + + + START + Start This bit can be set to start the + automatic loading of the CLUT + 5 + 1 + + + CS + CLUT size + 8 + 8 + + + AM + Alpha mode + 16 + 2 + + + AI + Alpha Inverted + 20 + 1 + + + RBS + Red Blue Swap + 21 + 1 + + + ALPHA + Alpha value + 24 + 8 + + + + + FGCOLR + FGCOLR + GPHA foreground color + register + 0x20 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits defines the blue + value for the A4 or A8 mode of the foreground image + 0 + 8 + + + GREEN + Green Value These bits defines the green + value for the A4 or A8 mode of the foreground image + 8 + 8 + + + RED + Red Value These bits defines the red + value for the A4 or A8 mode of the foreground image + 16 + 8 + + + + + BGPFCCR + BGPFCCR + GPHA background PFC control + register + 0x24 + 0x20 + read-write + 0x00000000 + + + CM + Color mode + 0 + 4 + + + CCM + CLUT Color mode These bits define the + color format of the CLUT + 4 + 1 + + + START + Start This bit is set to start the + automatic loading of the CLUT + 5 + 1 + + + CS + CLUT size + 8 + 8 + + + AM + Alpha mode + 16 + 2 + + + AI + Alpha Inverted + 20 + 1 + + + RBS + Red Blue Swap + 21 + 1 + + + ALPHA + Alpha value + 24 + 8 + + + + + BGCOLR + BGCOLR + GPHA background color + register + 0x28 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits define the blue + value for the A4 or A8 mode of the background + 0 + 8 + + + GREEN + Green Value These bits define the green + value for the A4 or A8 mode of the background + 8 + 8 + + + RED + Red Value These bits define the red + value for the A4 or A8 mode of the background + 16 + 8 + + + + + FGCMAR + FGCMAR + GPHA foreground CLUT memory address + register + 0x2C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address Address of the data used + for the CLUT address dedicated to the foreground + image + 0 + 32 + + + + + BGCMAR + BGCMAR + GPHA background CLUT memory address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + MA + Memory address Address of the data used + for the CLUT address dedicated to the background + image + 0 + 32 + + + + + OPFCCR + OPFCCR + GPHA output PFC control + register + 0x34 + 0x20 + read-write + 0x00000000 + + + CM + Color mode These bits define the color + format of the output image + 0 + 3 + + + AI + Alpha Inverted This bit inverts the + alpha value + 20 + 1 + + + RBS + Red Blue Swap + 21 + 1 + + + + + OCOLR + OCOLR + GPHA output color register + 0x38 + 0x20 + read-write + 0x00000000 + + + BLUE + Blue Value These bits define the blue + value of the output image + 0 + 8 + + + GREEN + Green Value These bits define the green + value of the output image + 8 + 8 + + + RED + Red Value These bits define the red + value of the output image + 16 + 8 + + + ALPHA + Alpha Channel Value These bits define + the alpha channel of the output color + 24 + 8 + + + + + OMAR + OMAR + GPHA output memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory Address Address of the data used + for the output FIFO + 0 + 32 + + + + + OOR + OOR + GPHA output offset register + 0x40 + 0x20 + read-write + 0x00000000 + + + LO + Line Offset Line offset used for the + output (expressed in pixels) + 0 + 14 + + + + + NLR + NLR + GPHA number of line register + 0x44 + 0x20 + read-write + 0x00000000 + + + NL + Number of lines Number of lines of the + area to be transferred + 0 + 16 + + + PL + Pixel per lines Number of pixels per + lines of the area to be transferred + 16 + 14 + + + + + LWR + LWR + GPHA line watermark register + 0x48 + 0x20 + read-write + 0x00000000 + + + LW + Line watermark These bits allow to + configure the line watermark for interrupt + generation + 0 + 16 + + + + + AMTCR + AMTCR + GPHA HB master timer configuration + register + 0x4C + 0x20 + read-write + 0x00000000 + + + EN + Enable Enables the dead time + functionality. + 0 + 1 + + + DT + Dead Time Dead time value in the HB + clock cycle inserted between two consecutive accesses + on the HB master port. These bits represent the + minimum guaranteed number of cycles between two + consecutive HB accesses. + 8 + 8 + + + + + FGCWRS + FGCWRS + GPHA foreground layer CLUT read/write setting + register + 0x50 + 0x20 + 0x00000000 + + + FG_CLUT_INDEX + set the address of the lookup table + 0 + 8 + read-write + + + FG_CLUT_EN + enable CPU read/write lookup table + 8 + 1 + read-write + + + + + FGCDAT + FGCDAT + GPHA foreground layer CLUT read/write data + register + 0x54 + 0x20 + 0x00000000 + + + FG_CLUT_DATA + read data or write SRAM data for lookup table + 0 + 32 + read-write + + + + + BGCWRS + BGCWRS + GPHA background layer CLUT read/write setting + register + 0x58 + 0x20 + 0x00000000 + + + BG_CLUT_INDEX + set the address of the lookup table + 0 + 8 + read-write + + + BG_CLUT_EN + enable CPU read/write lookup table + 8 + 1 + read-write + + + + + BGCDAT + BGCDAT + GPHA background layer CLUT read/write data + register + 0x5C + 0x20 + 0x00000000 + + + BG_CLUT_DATA + read data or write SRAM data for lookup table + 0 + 32 + read-write + + + + + + + + DFSDM + Digital filter for sigma delta + modulators + DFSDM + 0x40017000 + + 0x0 + 0x400 + registers + + + DFSDM0 + DFSDM0 global interrupt + 127 + + + DFSDM1 + DFSDM1 global interrupt + 128 + + + + CH0CFGR1 + CH0CFGR1 + channel configuration 0 + register + 0x0 + 0x20 + read-write + 0x0 + + + DFSDMEN + The DFSDM interface is globally enabled + 31 + 1 + + + CKOUTSRC + Output Serial Clock Source Selection + 30 + 1 + + + CKOUTDIV + Output Serial Clock Divider + 16 + 8 + + + DATPACK + R32_DFSDM_CHyDATINR register data encapsulation mode + 14 + 2 + + + DATMPX + Channel 0 Input Data Multiplexer + 12 + 2 + + + CHINSEL + Channel Input Selection + 8 + 1 + + + CHEN + Channel 0 enables + 7 + 1 + + + CKABEN + Channel 0 Clock Missing Detector Enables + 6 + 1 + + + SCDEN + Channel 0 Short Circuit Detector Enables + 5 + 1 + + + SPICKSEL + Channel 0 SPI Clock Selection + 2 + 2 + + + SITP + Channel 0 Serial Interface Type + 0 + 1 + + + + + CH1CFGR1 + CH1CFGR1 + channel configuration 1 + register + 0x04 + 0x20 + read-write + 0x0 + + + DFSDMEN + The DFSDM interface is globally enabled + 31 + 1 + + + CKOUTSRC + Output Serial Clock Source Selection + 30 + 1 + + + CKOUTDIV + Output Serial Clock Divider + 16 + 8 + + + DATPACK + R32_DFSDM_CHyDATINR register data encapsulation mode + 14 + 2 + + + DATMPX + Channel 1 Input Data Multiplexer + 12 + 2 + + + CHINSEL + Channel Input Selection + 8 + 1 + + + CHEN + Channel 1 enables + 7 + 1 + + + CKABEN + Channel 1 Clock Missing Detector Enables + 6 + 1 + + + SCDEN + Channel 1 Short Circuit Detector Enables + 5 + 1 + + + SPICKSEL + Channel 1 SPI Clock Selection + 2 + 2 + + + SITP + Channel 1 Serial Interface Type + 0 + 2 + + + + + CH0CFGR2 + CH0CFGR2 + channel configuration 0 + register + 0x8 + 0x20 + read-write + 0x0 + + + OFFSET + Channel 0 24-bit calibration offset + 8 + 24 + + + DTRBS + Channel 0 data right shift + 3 + 5 + + + + + CH1CFGR2 + CH1CFGR2 + channel configuration 1 + register + 0x0C + 0x20 + read-write + 0x0 + + + OFFSET + Channel 1 24-bit calibration offset + 8 + 24 + + + DTRBS + Channel 1 data right shift + 3 + 5 + + + + + CH0AWSCDR + CH0AWSCDR + analog watchdog and short-circuit detector + register + 0x10 + 0x20 + read-write + 0x0 + + + AWFORD + Channel 0 analog watchdog Sinc filter order + 22 + 2 + + + AWFOSR + Channel 0 analog watchdog filter oversampling rate + 16 + 5 + + + BKSCD + Channel 0 Short Circuit Detector Open Signal Distribution + 12 + 4 + + + SCDT + Short Circuit Detector Threshold for Channel 0 + 0 + 8 + + + + + CH1AWSCDR + CH1AWSCDR + analog watchdog and short-circuit detector + register + 0x14 + 0x20 + read-write + 0x0 + + + AWFORD + Channel 1 analog watchdog Sinc filter order + 22 + 2 + + + AWFOSR + Channel 1 analog watchdog filter oversampling rate + 16 + 5 + + + BKSCD + Channel 1 Short Circuit Detector Open Signal Distribution + 12 + 4 + + + SCDT + Short Circuit Detector Threshold for Channel 1 + 0 + 8 + + + + + + CH0WDATR + CH0WDATR + channel watchdog filter data + register + 0x18 + 0x20 + read-write + 0x0 + + + WDATA + Enter channel 0 watchdog data + 0 + 16 + + + + + CH1WDATR + CH1WDATR + channel watchdog filter data + register + 0x1C + 0x20 + read-write + 0x0 + + + WDATA + Enter channel 1 watchdog data + 0 + 16 + + + + + + CH0DATINR + CH0DATINR + channel data input register + 0x20 + 0x20 + read-write + 0x0 + + + INDAT1 + Input data for channel y or channel y+1 + 16 + 16 + + + INDAT0 + Channel Y Input Data + 0 + 16 + + + + + CH1DATINR + CH1DATINR + channel data input register + 0x24 + 0x20 + read-write + 0x0 + + + INDAT1 + Input data for channel 1 or channel 2 + 16 + 16 + + + INDAT0 + Channel 1 Input Data + 0 + 16 + + + + + DFSDM_FLT0CR1 + DFSDM_FLT0CR1 + control register 1 + 0x28 + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 4 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT0CR2 + DFSDM_FLT0CR2 + control register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT0ISR + DFSDM_FLT0ISR + interrupt and status register + 0x38 + 0x20 + read-only + 0x00000000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT0ICR + DFSDM_FLT0ICR + interrupt flag clear register + 0x40 + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT0JCHGR + DFSDM_FLT0JCHGR + injected channel group selection + register + 0x48 + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 2 + + + + + DFSDM_FLT0FCR3 + FLT0FCR3 + control register 3 + 0x50 + 0x20 + 0x00000000 + + + FORD + Sinc Filter Order + 29 + 3 + read-only + + + FOSR + Sinc filter oversampling rate + 16 + 10 + read-write + + + IOSR + The integrator oversampling rate is 2 to the power of IOSR + 0 + 4 + read-write + + + + + DFSDM_FLT0JDATAR + DFSDM_FLT0JDATAR + data register for injected + group + 0x58 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 1 + + + + + DFSDM_FLT0RDATAR + DFSDM_FLT0RDATAR + data register for the regular + channel + 0x60 + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 1 + + + + + DFSDM_FLT0AWHTR + DFSDM_FLT0AWHTR + analog watchdog high threshold + register + 0x68 + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT0AWLTR + DFSDM_FLT0AWLTR + analog watchdog low threshold + register + 0x70 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 2 + + + + + DFSDM_FLT0AWSR + DFSDM_FLT0AWSR + analog watchdog status + register + 0x78 + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT0AWCFR + DFSDM_FLT0AWCFR + analog watchdog clear flag + register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 2 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 2 + + + + + DFSDM_FLT0EXMAX + DFSDM_FLT0EXMAX + Extremes detector maximum + register + 0x88 + 0x20 + read-only + 0x00000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 1 + + + + + DFSDM_FLT0EXMIN + DFSDM_FLT0EXMIN + Extremes detector minimum + register + 0x90 + 0x20 + read-only + 0x00000000 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 1 + + + + + DFSDM_FLT0CNVTIMR + DFSDM_FLT0CNVTIMR + conversion timer register + 0x98 + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + DFSDM_FLT1CR1 + DFSDM_FLT1CR1 + control register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + AWFSEL + Analog watchdog fast mode + select + 30 + 1 + + + FAST + Fast conversion mode selection for + regular conversions + 29 + 1 + + + RCH + Regular channel selection + 24 + 3 + + + RDMAEN + DMA channel enabled to read data for the + regular conversion + 21 + 1 + + + RSYNC + Launch regular conversion synchronously + with DFSDM0 + 19 + 1 + + + RCONT + Continuous mode selection for regular + conversions + 18 + 1 + + + RSWSTART + Software start of a conversion on the + regular channel + 17 + 1 + + + JEXTEN + Trigger enable and trigger edge + selection for injected conversions + 13 + 2 + + + JEXTSEL + Trigger signal selection for launching + injected conversions + 8 + 4 + + + JDMAEN + DMA channel enabled to read data for the + injected channel group + 5 + 1 + + + JSCAN + Scanning conversion mode for injected + conversions + 4 + 1 + + + JSYNC + Launch an injected conversion + synchronously with the DFSDM0 JSWSTART + trigger + 3 + 1 + + + JSWSTART + Start a conversion of the injected group + of channels + 1 + 1 + + + DFEN + DFSDM enable + 0 + 1 + + + + + DFSDM_FLT1CR2 + DFSDM_FLT1CR2 + control register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + AWDCH + Analog watchdog channel + selection + 16 + 8 + + + EXCH + Extremes detector channel + selection + 8 + 8 + + + CKABIE + Clock absence interrupt + enable + 6 + 1 + + + SCDIE + Short-circuit detector interrupt + enable + 5 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 4 + 1 + + + ROVRIE + Regular data overrun interrupt + enable + 3 + 1 + + + JOVRIE + Injected data overrun interrupt + enable + 2 + 1 + + + REOCIE + Regular end of conversion interrupt + enable + 1 + 1 + + + JEOCIE + Injected end of conversion interrupt + enable + 0 + 1 + + + + + DFSDM_FLT1ISR + DFSDM_FLT1ISR + interrupt and status register + 0x3C + 0x20 + read-only + 0x00000000 + + + SCDF + short-circuit detector + flag + 24 + 8 + + + CKABF + Clock absence flag + 16 + 8 + + + RCIP + Regular conversion in progress + status + 14 + 1 + + + JCIP + Injected conversion in progress + status + 13 + 1 + + + AWDF + Analog watchdog + 4 + 1 + + + ROVRF + Regular conversion overrun + flag + 3 + 1 + + + JOVRF + Injected conversion overrun + flag + 2 + 1 + + + REOCF + End of regular conversion + flag + 1 + 1 + + + JEOCF + End of injected conversion + flag + 0 + 1 + + + + + DFSDM_FLT1ICR + DFSDM_FLT1ICR + interrupt flag clear register + 0x44 + 0x20 + read-write + 0x00000000 + + + CLRSCDF + Clear the short-circuit detector + flag + 24 + 8 + + + CLRCKABF + Clear the clock absence + flag + 16 + 8 + + + CLRROVRF + Clear the regular conversion overrun + flag + 3 + 1 + + + CLRJOVRF + Clear the injected conversion overrun + flag + 2 + 1 + + + + + DFSDM_FLT1JCHGR + DFSDM_FLT1JCHGR + injected channel group selection + register + 0x4C + 0x20 + read-write + 0x00000001 + + + JCHG + Injected channel group + selection + 0 + 2 + + + + + DFSDM_FLT1FCR3 + FLT1FCR3 + control register 3 + 0x54 + 0x20 + 0x00000000 + + + FORD + Sinc Filter Order + 29 + 3 + read-only + + + FOSR + Sinc filter oversampling rate + 16 + 10 + read-write + + + IOSR + The integrator oversampling rate is 2 to the power of IOSR + 0 + 4 + read-write + + + + + DFSDM_FLT1JDATAR + DFSDM_FLT1JDATAR + data register for injected + group + 0x5C + 0x20 + read-only + 0x00000000 + + + JDATA + Injected group conversion + data + 8 + 24 + + + JDATACH + Injected channel most recently + converted + 0 + 1 + + + + + DFSDM_FLT1RDATAR + DFSDM_FLT1RDATAR + data register for the regular + channel + 0x64 + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel conversion + data + 8 + 24 + + + RPEND + Regular channel pending + data + 4 + 1 + + + RDATACH + Regular channel most recently + converted + 0 + 1 + + + + + DFSDM_FLT1AWHTR + DFSDM_FLT1AWHTR + analog watchdog high threshold + register + 0x6C + 0x20 + read-write + 0x00000000 + + + AWHT + Analog watchdog high + threshold + 8 + 24 + + + BKAWH + Break signal assignment to analog + watchdog high threshold event + 0 + 4 + + + + + DFSDM_FLT1AWLTR + DFSDM_FLT1AWLTR + analog watchdog low threshold + register + 0x74 + 0x20 + read-write + 0x00000000 + + + AWLT + Analog watchdog low + threshold + 8 + 24 + + + BKAWL + Break signal assignment to analog + watchdog low threshold event + 0 + 2 + + + + + DFSDM_FLT1AWSR + DFSDM_FLT1AWSR + analog watchdog status + register + 0x7C + 0x20 + read-only + 0x00000000 + + + AWHTF + Analog watchdog high threshold + flag + 8 + 8 + + + AWLTF + Analog watchdog low threshold + flag + 0 + 8 + + + + + DFSDM_FLT1AWCFR + DFSDM_FLT1AWCFR + analog watchdog clear flag + register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRAWHTF + Clear the analog watchdog high threshold + flag + 8 + 2 + + + CLRAWLTF + Clear the analog watchdog low threshold + flag + 0 + 2 + + + + + DFSDM_FLT1EXMAX + DFSDM_FLT1EXMAX + Extremes detector maximum + register + 0x8C + 0x20 + read-only + 0x00000000 + + + EXMAX + Extremes detector maximum + value + 8 + 24 + + + EXMAXCH + Extremes detector maximum data + channel + 0 + 1 + + + + + DFSDM_FLT1EXMIN + DFSDM_FLT1EXMIN + Extremes detector minimum + register + 0x94 + 0x20 + read-only + 0x00000000 + + + EXMIN + EXMIN + 8 + 24 + + + EXMINCH + Extremes detector minimum data + channel + 0 + 1 + + + + + DFSDM_FLT1CNVTIMR + DFSDM_FLT1CNVTIMR + conversion timer register + 0x9C + 0x20 + read-only + 0x00000000 + + + CNVCNT + 28-bit timer counting conversion time t + = CNVCNT[27:0] / fDFSDM_CKIN + 4 + 28 + + + + + + + + QSPI1 + QSPI1 + QSPI1 + 0x40024C00 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 82 + + + + CR + CR + QSPI control register + 0x0 + 0x20 + 0x00000000 + + + EN + Enable Enable the QSPI + 0 + 1 + read-write + + + ABORT + Abort request This bit aborts the + on-going command sequence + 1 + 1 + read-write + + + DMAEN + DMA mode enabled + 2 + 1 + read-write + + + TCEN + Timeout counter enable + 3 + 1 + read-write + + + START + start the FLASH command sequence + 5 + 1 + write-only + + + DFM + Dual-flash mode This bit activates + dual-flash mode + 6 + 1 + read-write + + + FSEL + Flash memory selection + 7 + 1 + read-write + + + FTHRES + FIFO threshold level Defines + 8 + 5 + read-write + + + SIOXEN + SIOX enable + 13 + 1 + read-write + + + TEIE + Transfer error interrupt enable This bit + enables the transfer error interrupt. + 16 + 1 + read-write + + + TCIE + Transfer complete interrupt enable This + bit enables the transfer complete + interrupt. + 17 + 1 + read-write + + + FTIE + FIFO threshold interrupt enable This bit + enables the FIFO threshold interrupt. + 18 + 1 + read-write + + + SMIE + Status match interrupt enable This bit + enables the status match interrupt. + 19 + 1 + read-write + + + TOIE + TimeOut interrupt enable This bit + enables the TimeOut interrupt. + 20 + 1 + read-write + + + APMS + Automatic poll mode stop + 22 + 1 + read-write + + + PMM + Polling match mode + 23 + 1 + read-write + + + PRESCALER + clock prescaler + 24 + 8 + read-write + + + + + DCR + DCR + QSPI device configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + CKMODE + indicates the level that clk takes + between command + 0 + 1 + + + CSHT + Chip select high time + 8 + 3 + + + FSIZE + Flash memory size + 16 + 5 + + + + + SR + SR + QSPI status register + 0x8 + 0x20 + read-only + 0x00000000 + + + TEF + Transfer error flag + 0 + 1 + + + TCF + Transfer complete flag + 1 + 1 + + + FTF + FIFO threshold flag + 2 + 1 + + + SMF + Status match flag + 3 + 1 + + + TOF + Timeout flag This bit is set when + timeout occurs + 4 + 1 + + + BUSY + Busy This bit is set when an operation + is on going + 5 + 1 + + + FLEVEL + FIFO level + 8 + 6 + + + IDLEF + IDLE flag + 16 + 1 + + + + + FCR + FCR + QSPI flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTEF + Clear transfer error flag Writing 1 + clears the TEF flag in the QSPI_SR + register + 0 + 1 + + + CTCF + Clear transfer complete flag Writing 1 + clears the TCF flag in the QSPI_SR + register + 1 + 1 + + + CSMF + Clear status match flag Writing 1 clears + the SMF flag in the QSPI_SR register + 3 + 1 + + + CTOF + Clear timeout flag Writing 1 clears the + TOF flag in the QSPI_SR register + 4 + 1 + + + + + DLR + DLR + QSPI data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length + 0 + 32 + + + + + CCR + CCR + QSPI communication configuration + register + 0x14 + 0x20 + read-write + 0x00000000 + + + INSTRUCTION + Instruction + 0 + 8 + + + IMODE + Instruction mode + 8 + 2 + + + ADMODE + Address mode + 10 + 2 + + + ADSIZE + Address size + 12 + 2 + + + ABMODE + Alternate bytes mode + 14 + 2 + + + ABSIZE + Alternate bytes size + 16 + 2 + + + DCYC + Number of dummy cycles + 18 + 5 + + + DMODE + Data mode + 24 + 2 + + + FMODE + Functional mode + 26 + 2 + + + SIOO + Send instruction only once mode + 28 + 1 + + + + + AR + AR + QSPI address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + QSPI Address + 0 + 32 + + + + + ABR + ABR + QSPI alternate bytes + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + Alternate Bytes Optional data to be send + to the external SPI device right after the address. + + 0 + 32 + + + + + DR + DR + QSPI data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PSMKR + PSMKR + QSPI polling status mask + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask Mask to be applied to the + status bytes received in polling mode + 0 + 32 + + + + + PSMAR + PSMAR + QSPI polling status match + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match Value to be compared with + the masked status register to get a match. This field + can be written only when BUSY = 0. + 0 + 32 + + + + + PIR + PIR + QSPI polling interval + register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval Number of CLK cycles + between to read during automatic polling phases. This + field can be written only when BUSY = + 0. + 0 + 16 + + + + + LPTR + LPTR + QSPI low-power timeout + register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout + 0 + 16 + + + + + + + + QSPI2 + 0x40025000 + + 0x0 + 0x400 + registers + + + QSPI2 + QSPI2 global interrupt + 134 + + + + + SWPMI + Single Wire Protocol Master + Interface + SWPMI + 0x40008400 + + 0x0 + 0x400 + registers + + + SWPMI + SWPMI global interrupt + 131 + + + SWPMIWakeUP + SWPMI wake-up interrupt + 135 + + + + CR + CR + SWPMI Configuration/Control + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RXDMA + Reception DMA enable + 0 + 1 + + + TXDMA + Transmission DMA enable + 1 + 1 + + + RXMODE + Reception buffering mode + 2 + 1 + + + TXMODE + Transmission buffering + mode + 3 + 1 + + + LPBK + Loopback mode enable + 4 + 1 + + + SWPACT + Single wire protocol master interface + activate + 5 + 1 + + + DEACT + Single wire protocol master interface + deactivate + 10 + 1 + + + SWPTEN + Single wire protocol master transceiver + enable + 11 + 1 + + + + + BRR + BRR + SWPMI Bitrate register + 0x4 + 0x20 + read-write + 0x00000001 + + + BR + Bitrate prescaler + 0 + 8 + + + + + ISR + ISR + SWPMI Interrupt and Status + register + 0xC + 0x20 + read-only + 0x000002C2 + + + RXBFF + Receive buffer full flag + 0 + 1 + + + TXBEF + Transmit buffer empty flag + 1 + 1 + + + RXBERF + Receive CRC error flag + 2 + 1 + + + RXOVRF + Receive overrun error flag + 3 + 1 + + + TXUNRF + Transmit underrun error + flag + 4 + 1 + + + RXNE + Receive data register not + empty + 5 + 1 + + + TXE + Transmit data register + empty + 6 + 1 + + + TCF + Transfer complete flag + 7 + 1 + + + SRF + Slave resume flag + 8 + 1 + + + SUSP + SUSPEND flag + 9 + 1 + + + DEACTF + DEACTIVATED flag + 10 + 1 + + + RDYF + transceiver ready flag + 11 + 1 + + + + + ICR + ICR + SWPMI Interrupt Flag Clear + register + 0x10 + 0x20 + read-write + 0x00000000 + + + CRXBFF + Clear receive buffer full + flag + 0 + 1 + + + CTXBEF + Clear transmit buffer empty + flag + 1 + 1 + + + CRXBERF + Clear receive CRC error + flag + 2 + 1 + + + CRXOVRF + Clear receive overrun error + flag + 3 + 1 + + + CTXUNRF + Clear transmit underrun error + flag + 4 + 1 + + + CTCF + Clear transfer complete + flag + 7 + 1 + + + CSRF + Clear slave resume flag + 8 + 1 + + + CRDYF + Clear transceiver ready + flag + 11 + 1 + + + + + IER + IER + SWPMI Interrupt Enable + register + 0x14 + 0x20 + read-write + 0x00000000 + + + RXBFIE + Receive buffer full interrupt + enable + 0 + 1 + + + TXBEIE + Transmit buffer empty interrupt + enable + 1 + 1 + + + RXBERIE + Receive CRC error interrupt + enable + 2 + 1 + + + RXOVRIE + Receive overrun error interrupt + enable + 3 + 1 + + + TXUNRIE + Transmit underrun error interrupt + enable + 4 + 1 + + + RIE + Receive interrupt enable + 5 + 1 + + + TIE + Transmit interrupt enable + 6 + 1 + + + TCIE + Transmit complete interrupt + enable + 7 + 1 + + + SRIE + Slave resume interrupt + enable + 8 + 1 + + + RDYIE + Transceiver ready interrupt + enable + 11 + 1 + + + + + RFL + RFL + SWPMI Receive Frame Length + register + 0x18 + 0x20 + read-only + 0x00000000 + + + RFL + Receive frame length + 0 + 5 + + + + + TDR + TDR + SWPMI Transmit data register + 0x1C + 0x20 + write-only + 0x00000000 + + + TD + Transmit data + 0 + 32 + + + + + RDR + RDR + SWPMI Receive data register + 0x20 + 0x20 + read-only + 0x00000000 + + + RD + received data + 0 + 32 + + + + + OR + OR + SWPMI Option register + 0x24 + 0x20 + read-write + 0x00000000 + + + SWP_TBYP + SWP transceiver bypass + 0 + 1 + + + SWP_ISEL + SWP current selection + 2 + 2 + + + + + + + + SAI + SAI + SAI + 0x40015800 + + 0x0 + 0x400 + registers + + + SAI + SAI global interrupt + 123 + + + + SAI_ACFGR1 + SAI_ACFGR1 + Configuration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MODE + SAIx audio block mode + immediately + 0 + 2 + + + PRTCFG + Protocol configuration + 2 + 2 + + + DS + Data size + 5 + 3 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + CKSTR + Clock strobing edge + 9 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + MONO + Mono mode + 12 + 1 + + + SAIXEN + Audio block enable + 16 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + NOMCK + No divider + 19 + 1 + + + MCKDIV + Master clock divider + 20 + 6 + + + OSR + Oversampling ratio for master + clock + 26 + 1 + + + + + SAI_ACFGR2 + SAI_ACFGR2 + Configuration register 2 + 0x8 + 0x20 + 0x00000000 + + + FTH + FIFO threshold + 0 + 3 + read-write + + + FFLUSH + FIFO flush + 3 + 1 + read-write + + + TRIS + Tristate management on data line + 4 + 1 + read-write + + + MUTE + Mute mode enable + 5 + 1 + read-write + + + MUTEVAL + Mute value + 6 + 1 + read-write + + + MUTECNT + Mute counter + 7 + 6 + read-write + + + CPL + Complement bit + 13 + 1 + read-write + + + COMP + Companding mode + 14 + 2 + read-write + + + + + SAI_AFRCR + SAI_AFRCR + This register has no meaning in AC97 and + SPDIF audio protocol + 0xC + 0x20 + 0x00000007 + + + FRL + Frame length + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length + 8 + 7 + read-write + + + FSDEF + Frame synchronization definition + 16 + 1 + read-only + + + FSPOL + Frame synchronization polarity + 17 + 1 + read-write + + + FSOFF + Frame synchronization offset + 18 + 1 + read-write + + + + + SAI_ASLOTR + SAI_ASLOTR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x10 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset + 0 + 5 + + + SLOTSZ + Slot size + 6 + 2 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTEN + Slot enable + 16 + 16 + + + + + SAI_AINTENR + SAI_AINTENR + Interrupt mask register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + MUTEDETIE + Mute detection interrupt enable + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable + 2 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + CNRDYIE + Codec not ready interrupt enable (AC97). + + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable + 6 + 1 + + + + + SAI_ASR + SAI_ASR + Status register + 0x18 + 0x20 + 0x00000008 + + + OVRUDR + Overrun/underrun error flag + 0 + 1 + read-write + + + MUTEDET + Mute detection flag + 1 + 1 + read-write + + + WCKCFG + Wrong clock configuration error flag + 2 + 1 + read-write + + + FREQ + FIFO request flag + 3 + 1 + read-write + + + CNRDY + Codec not ready + 4 + 1 + read-write + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + read-write + + + LFSDET + Late frame synchronization detection + 6 + 1 + read-write + + + FLVL + FIFO level threshold + 16 + 3 + read-only + + + + + SAI_ADATAR + SAI_ADATAR + Data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + SAI_BCFGR1 + SAI_BCFGR1 + Configuration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MODE + SAIx audio block mode + immediately + 0 + 2 + + + PRTCFG + Protocol configuration + 2 + 2 + + + DS + Data size + 5 + 3 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + CKSTR + Clock strobing edge + 9 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + MONO + Mono mode + 12 + 1 + + + OUTDRIV + Output drive + 13 + 1 + + + SAIXEN + Audio block enable + 16 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + NOMCK + No divider + 19 + 1 + + + MCKDIV + Master clock divider + 20 + 6 + + + OSR + Oversampling ratio for master + clock + 26 + 1 + + + + + SAI_BCFGR2 + SAI_BCFGR2 + Configuration register 2 + 0x28 + 0x20 + 0x00000000 + + + FTH + FIFO threshold + 0 + 3 + read-write + + + FFLUSH + FIFO flush + 3 + 1 + read-write + + + TRIS + Tristate management on data line + 4 + 1 + read-write + + + MUTE + Mute mode enable + 5 + 1 + read-write + + + MUTEVAL + Mute value + 6 + 1 + read-write + + + MUTECNT + Mute counter + 7 + 6 + read-write + + + CPL + Complement bit + 13 + 1 + read-write + + + COMP + Companding mode + 14 + 2 + read-write + + + + + SAI_BFRCR + SAI_BFRCR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x2C + 0x20 + 0x00000007 + + + FRL + Frame length + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length + 8 + 7 + read-write + + + FSDEF + Frame synchronization definition + 16 + 1 + read-only + + + FSPOL + Frame synchronization polarity + 17 + 1 + read-write + + + FSOFF + Frame synchronization offset + 18 + 1 + read-write + + + + + SAI_BSLOTR + SAI_BSLOTR + This register has no meaning in AC97 and + SPDIF audio protocol + 0x30 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset + 0 + 5 + + + SLOTSZ + Slot size + 6 + 2 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTEN + Slot enable + 16 + 16 + + + + + SAI_BINTENR + SAI_BINTENR + Interrupt mask register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + MUTEDETIE + Mute detection interrupt enable + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable + 2 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + CNRDYIE + Codec not ready interrupt enable (AC97). + + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable + 6 + 1 + + + + + SAI_BSR + SAI_BSR + Status register + 0x38 + 0x20 + 0x00000008 + + + OVRUDR + Overrun/underrun error flag + 0 + 1 + read-write + + + MUTEDET + Mute detection flag + 1 + 1 + read-write + + + WCKCFG + Wrong clock configuration error flag + 2 + 1 + read-write + + + FREQ + FIFO request flag + 3 + 1 + read-write + + + CNRDY + Codec not ready + 4 + 1 + read-write + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + read-write + + + LFSDET + Late frame synchronization detection + 6 + 1 + read-write + + + FLVL + FIFO level threshold + 16 + 3 + read-only + + + + + SAI_BDATAR + SAI_BDATAR + Data register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + + + + FMC + FMC + FMC + 0x40025400 + + 0x0 + 0x400 + registers + + + FMC + FMC global interrupt + 94 + + + + BCR1 + BCR1 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x0 + 0x20 + read-write + 0x00003052 + + + MBKEN + Memory bank enable + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + 1 + 1 + + + MTYP + Memory type + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable + 6 + 1 + + + BURSTEN + Burst enable bit + 8 + 1 + + + WAITPOL + Wait signal polarity bit + 9 + 1 + + + WAITCFG + Wait timing configuration + 11 + 1 + + + WREN + Write enable bit + 12 + 1 + + + WAITEN + Wait enable bit + 13 + 1 + + + EXTMOD + Extended mode enable + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers + 15 + 1 + + + CPSIZE + CRAM Page Size + 16 + 3 + + + CBURSTRW + Write burst enable + 19 + 1 + + + BMP + FMC bank mapping + 24 + 2 + + + FMC_EN + FMC controller Enable + 31 + 1 + + + + + BTR1 + BTR1 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + 24 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + + + BCR2 + BCR2 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x8 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + 1 + 1 + + + MTYP + Memory type + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable + 6 + 1 + + + BURSTEN + Burst enable bit + 8 + 1 + + + WAITPOL + Wait signal polarity bit + 9 + 1 + + + WAITCFG + Wait timing configuration + 11 + 1 + + + WREN + Write enable bit + 12 + 1 + + + WAITEN + Wait enable bit + 13 + 1 + + + EXTMOD + Extended mode enable + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers + 15 + 1 + + + CPSIZE + CRAM Page Size + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode + 19 + 1 + + + BMP + FMC bank mapping + 24 + 2 + + + FMC_EN + FMC controller Enable + 31 + 1 + + + + + BTR2 + BTR2 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + 24 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + + + BCR3 + BCR3 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x10 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + 1 + 1 + + + MTYP + Memory type + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable + 6 + 1 + + + BURSTEN + Burst enable bit + 8 + 1 + + + WAITPOL + Wait signal polarity bit + 9 + 1 + + + WAITCFG + Wait timing configuration + 11 + 1 + + + WREN + Write enable bit + 12 + 1 + + + WAITEN + Wait enable bit + 13 + 1 + + + EXTMOD + Extended mode enable + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers + 15 + 1 + + + CPSIZE + CRAM Page Size + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode + 19 + 1 + + + BMP + FMC bank mapping + 24 + 2 + + + FMC_EN + FMC controller Enable + 31 + 1 + + + + + BTR3 + BTR3 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + 24 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + + + BCR4 + BCR4 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories. + 0x18 + 0x20 + read-write + 0x000030D2 + + + MBKEN + Memory bank enable bit + 0 + 1 + + + MUXEN + Address/data multiplexing enable bit + 1 + 1 + + + MTYP + Memory type + 2 + 2 + + + MWID + Memory data bus width Defines the + external memory device width, valid for all type of + memories. + 4 + 2 + + + FACCEN + Flash access enable + 6 + 1 + + + BURSTEN + Burst enable bit + 8 + 1 + + + WAITPOL + Wait signal polarity bit + 9 + 1 + + + WAITCFG + Wait timing configuration + 11 + 1 + + + WREN + Write enable bit + 12 + 1 + + + WAITEN + Wait enable bit + 13 + 1 + + + EXTMOD + Extended mode enable + 14 + 1 + + + ASYNCWAIT + Wait signal during asynchronous + transfers + 15 + 1 + + + CPSIZE + CRAM Page Size + 16 + 3 + + + CBURSTRW + Write burst enable For PSRAM (CRAM) + operating in Burst mode + 19 + 1 + + + BMP + FMC bank mapping + 24 + 2 + + + FMC_EN + FMC controller Enable + 31 + 1 + + + + + BTR4 + BTR4 + This register contains the control + information of each memory bank, used for SRAMs, PSRAM + and NOR Flash memories + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + CLKDIV + Clock divide ratio (for FMC_CLK signal) + 20 + 4 + + + DATLAT + Data latency for synchronous memory For + synchronous access with read write burst mode enabled + 24 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + + + + PCR + PCR + NAND Flash control registers + 0x80 + 0x20 + read-write + 0x00000018 + + + PWAITEN + Wait feature enable bit + 1 + 1 + + + PBKEN + NAND Flash memory bank enable bit + 2 + 1 + + + PTYP + memory type + 3 + 1 + + + PWID + Data bus width + 4 + 2 + + + ECCEN + ECC computation logic enable + bit + 6 + 1 + + + TCLR + CLE to RE delay + 9 + 4 + + + TAR + ALE to RE delay + 13 + 4 + + + ECCPS + ECC page size + 17 + 3 + + + + + SR + SR + This register contains information about the + FIFO status and interrupt + 0x84 + 0x20 + 0x00000040 + + + IRS + Interrupt rising edge status + 0 + 1 + read-write + + + ILS + Interrupt high-level status + 1 + 1 + read-write + + + IFS + Interrupt falling edge status + 2 + 1 + read-write + + + IREN + Interrupt rising edge detection enable + bit + 3 + 1 + read-write + + + ILEN + Interrupt high-level detection enable + bit + 4 + 1 + read-write + + + IFEN + Interrupt falling edge detection enable + bit + 5 + 1 + read-write + + + FEMPT + FIFO empty + 6 + 1 + read-only + + + + + PMEM + PMEM + The FMC_PMEM read/write register contains + the timing information for NAND Flash memory bank + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMSET + Common memory x setup time + 0 + 8 + + + MEMWAIT + Common memory wait time + 8 + 8 + + + MEMHOLD + Common memory hold time + 16 + 8 + + + MEMHIZ + Common memory x data bus Hi-Z time + 24 + 8 + + + + + PATT + PATT + The FMC_PATT read/write register contains + the timing information for NAND Flash memory bank + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTSET + Attribute memory setup time + 0 + 8 + + + ATTWAIT + Attribute memory wait time + 8 + 8 + + + ATTHOLD + Attribute memory hold time + 16 + 8 + + + ATTHIZ + Attribute memory data bus Hi-Z time + 24 + 8 + + + + + ECCR + ECCR + This register contain the current error + correction code value computed by the ECC computation + modules of the FMC NAND controller + 0x94 + 0x20 + read-only + 0x00000000 + + + ECC + ECC result This field contains the value + computed by the ECC computation logic. Table167 + describes the contents of these bit + fields. + 0 + 32 + + + + + BWTR1 + BWTR1 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + + + BWTR2 + BWTR2 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + + + BWTR3 + BWTR3 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + + + BWTR4 + BWTR4 + This register contains the control + information of each memory bank. It is used for SRAMs, + PSRAMs and NOR Flash memories. + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ADDSET + Address setup phase duration + 0 + 4 + + + ADDHLD + Address-hold phase duration + 4 + 4 + + + DATAST + Data-phase duration + 8 + 8 + + + BUSTURN + Bus turnaround phase duration + 16 + 4 + + + ACCMOD + Access mode + 28 + 2 + + + + + SDCR1 + SDCR1 + This register contains the control + parameters for each SDRAM memory bank + 0x140 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address bits These bits + define the number of bits of a column + address. + 0 + 2 + + + NR + Number of row address bits These bits + define the number of bits of a row + address. + 2 + 2 + + + MWID + Memory data bus width. These bits define + the memory device width. + 4 + 2 + + + NB + Number of internal banks This bit sets + the number of internal banks. + 6 + 1 + + + CAS + CAS Latency This bits sets the SDRAM CAS + latency in number of memory clock + cycles + 7 + 2 + + + WP + Write protection This bit enables write + mode access to the SDRAM bank. + 9 + 1 + + + SDCLK + SDRAM clock configuration + 10 + 2 + + + RBURST + Burst read + 12 + 1 + + + RPIPE + Read pipe + 13 + 2 + + + + + SDCR2 + SDCR2 + This register contains the control + parameters for each SDRAM memory bank + 0x144 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address bits These bits + define the number of bits of a column + address. + 0 + 2 + + + NR + Number of row address bits These bits + define the number of bits of a row + address. + 2 + 2 + + + MWID + Memory data bus width. These bits define + the memory device width. + 4 + 2 + + + NB + Number of internal banks This bit sets + the number of internal banks. + 6 + 1 + + + CAS + CAS Latency This bits sets the SDRAM CAS + latency in number of memory clock + cycles + 7 + 2 + + + WP + Write protection This bit enables write + mode access to the SDRAM bank. + 9 + 1 + + + SDCLK + SDRAM clock configuration + 10 + 2 + + + RBURST + Burst read + 12 + 1 + + + RPIPE + Read pipe + 13 + 2 + + + + + SDTR1 + SDTR1 + This register contains the timing parameters + of each SDRAM bank + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to Active + 0 + 4 + + + TXSR + Exit Self-refresh delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Row cycle delay + 12 + 4 + + + TWR + Recovery delay + 16 + 4 + + + TRP + Row precharge delay + 20 + 4 + + + TRCD + Row to column delay + 24 + 4 + + + + + SDTR2 + SDTR2 + This register contains the timing parameters + of each SDRAM bank + 0x14C + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to Active + 0 + 4 + + + TXSR + Exit Self-refresh delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Row cycle delay + 12 + 4 + + + TWR + Recovery delay + 16 + 4 + + + TRP + Row precharge delay + 20 + 4 + + + TRCD + Row to column delay + 24 + 4 + + + + + SDCMR + SDCMR + This register contains the command issued + when the SDRAM device is accessed + 0x150 + 0x20 + read-write + 0x00000000 + + + MODE + Command mode These bits define the + command issued to the SDRAM device. + 0 + 3 + + + CTB2 + Command Target Bank 2 This bit indicates + whether the command will be issued to SDRAM Bank 2 or + not. + 3 + 1 + + + CTB1 + Command Target Bank 1 This bit indicates + whether the command will be issued to SDRAM Bank 1 or + not. + 4 + 1 + + + NRFS + Number of Auto-refresh + 5 + 4 + + + MRD + Mode Register definition + 9 + 14 + + + + + SDRTR + SDRTR + This register sets the refresh rate in + number of SDCLK clock cycles between the refresh cycles + by configuring the Refresh Timer Count value + 0x154 + 0x20 + 0x00000000 + + + CRE + Clear Refresh error flag + 0 + 1 + write-only + + + COUNT + Refresh Timer Count + 1 + 13 + read-write + + + REIE + RES Interrupt Enable + 14 + 1 + read-write + + + + + SDSR + SDSR + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + RE + Refresh error flag An interrupt is + generated if REIE = 1 and RE = 1 + 0 + 1 + + + MODES1 + Status Mode for Bank 1 These bits define + the Status Mode of SDRAM Bank 1. + 1 + 2 + + + MODES2 + Status Mode for Bank 2 These bits define + the Status Mode of SDRAM Bank 2. + 3 + 2 + + + BUSY + BUSY + 5 + 1 + + + + + MISC + MISC + SDRAM custom registers + 0x180 + 0x20 + 0x00000000 + + + NRFS_CNT + Define the number of times the controller self-refreshes each time + 0 + 4 + read-write + + + Phase_Sel + Phase offset of the output SDR_CLK + 4 + 4 + read-write + + + Enhance_read_mode + Read enhancement/prefetch mode + 15 + 1 + read-write + + + En_Bank1 + Enable SDRAM1 + 16 + 1 + read-write + + + En_Bank2 + Enable SDRAM2 + 17 + 1 + read-write + + + + + + + + ETHERNET_MAC + Ethernet: media access control + ETHERNET + 0x40028000 + + 0x0 + 0x100 + registers + + + ETH + Ethernet global interrupt + 110 + + + ETHWakeUP + Ethernet Wakeup interrupt + 111 + + + + MACCR + MACCR + Ethernet MAC configuration register + (ETH_MACCR) + 0x0 + 0x20 + read-write + 0x00000000 + + + TCF + Send clock reversal + 1 + 1 + + + RE + Receiver enable + 2 + 1 + + + TE + Transmitter enable + 3 + 1 + + + APCS + Automatic pad/CRC + stripping + 7 + 1 + + + IPCO + IPv4 checksum offload + 10 + 1 + + + DM + Duplex mode + 11 + 1 + + + LM + Loopback mode + 12 + 1 + + + FES + Fast Ethernet speed + 14 + 2 + + + IFG + Interframe gap + 17 + 3 + + + JD + Jabber disable + 22 + 1 + + + WD + Watchdog disable + 23 + 1 + + + TCD + SEND clock delay + 29 + 3 + + + + + MACFFR + MACFFR + Ethernet MAC frame filter register + (ETH_MACCFFR) + 0x4 + 0x20 + read-write + 0x00000000 + + + PM + Promiscuous mode + 0 + 1 + + + HU + Hash unicast + 1 + 1 + + + HM + Hash multicast + 2 + 1 + + + DAIF + Destination address inverse + filtering + 3 + 1 + + + PAM + Pass all multicast + 4 + 1 + + + BFD + Broadcast frames disable + 5 + 1 + + + PCF + Pass control frames + 6 + 2 + + + SAIF + Source address inverse + filtering + 8 + 1 + + + SAF + Source address filter + 9 + 1 + + + HPF + Hash or perfect filter + 10 + 1 + + + RA + Receive all + 31 + 1 + + + + + MACHTHR + MACHTHR + Ethernet MAC hash table high + register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + Hash table high + 0 + 32 + + + + + MACHTLR + MACHTLR + Ethernet MAC hash table low + register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + Hash table low + 0 + 32 + + + + + MACMIIAR + MACMIIAR + Ethernet MAC MII address register + (ETH_MACMIIAR) + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MII busy + 0 + 1 + + + MW + MII write + 1 + 1 + + + CR + Clock range + 2 + 3 + + + MR + MII register + 6 + 5 + + + PA + PHY address + 11 + 5 + + + + + MACMIIDR + MACMIIDR + Ethernet MAC MII data register + (ETH_MACMIIDR) + 0x14 + 0x20 + read-write + 0x00000000 + + + MD + MII data + 0 + 16 + + + + + MACFCR + MACFCR + Ethernet MAC flow control register + (ETH_MACFCR) + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB + Flow control busy + 0 + 1 + + + TFCE + Transmit flow control + enable + 1 + 1 + + + RFCE + Receive flow control + enable + 2 + 1 + + + UPFD + Unicast pause frame detect + 3 + 1 + + + PT + Pass control frames + 16 + 16 + + + + + MACVLAN + MACVLAN + Ethernet MAC VLAN tag register + (ETH_MACVLAN) + 0x1C + 0x20 + read-write + 0x00000000 + + + VLANTI + VLAN tag identifier (for receive + frames) + 0 + 16 + + + VLANT + VLAN tag comparison + 16 + 1 + + + + + MACRWUFFR + MACRWUFFR + Ethernet MAC remote wakeup frame filter + register (ETH_MACRWUFFR) + 0x28 + 0x20 + read-write + 0x00000000 + + + RWUFFR + wakeup frame filter + 0 + 32 + + + + + MACPMTCSR + MACPMTCSR + Ethernet MAC PMT control and status register + (ETH_MACPMTCSR) + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + Power down + 0 + 1 + + + MPE + Magic Packet enable + 1 + 1 + + + WFE + Wakeup frame enable + 2 + 1 + + + PHY_PMEB_EN + PHY_PMEB enable + 3 + 1 + + + MPR + Magic packet received + 5 + 1 + + + WFR + Wakeup frame received + 6 + 1 + + + PHY_PMEBR + PHY_PMEB reset + 7 + 1 + + + GU + Global unicast + 9 + 1 + + + WFFRPR + Wakeup frame filter register pointer + reset + 31 + 1 + + + + + MACSR + MACSR + Ethernet MAC interrupt status register + (ETH_MACSR) + 0x38 + 0x20 + read-write + 0x00000000 + + + PMTS + PMT status + 3 + 1 + + + MMCS + MMC status + 4 + 1 + + + MMCRS + MMC receive status + 5 + 1 + + + MMCTS + MMC transmit status + 6 + 1 + + + TSTS + Time stamp trigger status + 9 + 1 + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask register + (ETH_MACIMR) + 0x3C + 0x20 + read-write + 0x00000000 + + + PMTIM + PMT interrupt mask + 3 + 1 + + + TSTIM + Time stamp trigger interrupt + mask + 9 + 1 + + + + + MACA0HR + MACA0HR + Ethernet MAC address 0 high register + (ETH_MACA0HR) + 0x40 + 0x20 + 0x8000FFFF + + + MACA0H + MAC address0 high + 0 + 16 + read-write + + + MO + Always 1 + 31 + 1 + read-only + + + + + MACA0LR + MACA0LR + Ethernet MAC address 0 low + register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MACA0L + MAC address0 low + 0 + 32 + + + + + MACA1HR + MACA1HR + Ethernet MAC address 1 high register + (ETH_MACA1HR) + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MACA1H + MAC address1 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA1LR + MACA1LR + Ethernet MAC address1 low + register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MACA1L + MAC address1 low + 0 + 32 + + + + + MACA2HR + MACA2HR + Ethernet MAC address 2 high register + (ETH_MACA2HR) + 0x50 + 0x20 + read-write + 0x0000FFFF + + + ETH_MACA2HR + Ethernet MAC address 2 high + register + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA2LR + MACA2LR + Ethernet MAC address 2 low + register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MACA2L + MAC address2 low + 0 + 32 + + + + + MACA3HR + MACA3HR + Ethernet MAC address 3 high register + (ETH_MACA3HR) + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MACA3H + MAC address3 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA3LR + MACA3LR + Ethernet MAC address 3 low + register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MBCA3L + MAC address3 low + 0 + 32 + + + + + ETH_PHY_CFGR + ETH_PHY_CFGR + ETH PHY configure register + 0x80 + 0x20 + 0x00000000 + + + PHY_RSTN + ETH PHY global reset control + 31 + 1 + read-write + + + PHY_PD + PHY power-down mode + 30 + 1 + read-write + + + DUPlEX + connected mode + 10 + 1 + read-only + + + SPEED + speed selection + 9 + 1 + read-only + + + LINK_STATUS + LINK status + 8 + 1 + read-only + + + PHYADDR_EN + reconfigure the PHY address + 7 + 1 + read-write + + + REPHYADDR + when the bit7 set 1,bit4:0 as PHY address + 0 + 5 + read-write + + + + + + + ETHERNET_MMC + Ethernet: MAC management counters + ETHERNET + 0x40028100 + + 0x0 + 0x400 + registers + + + + MMCCR + MMCCR + Ethernet MMC control register + (ETH_MMCCR) + 0x0 + 0x20 + read-write + 0x00000000 + + + CR + Counter reset + 0 + 1 + + + CSR + Counter stop rollover + 1 + 1 + + + ROR + Reset on read + 2 + 1 + + + MCF + MMC counter freeze + 31 + 1 + + + + + MMCRIR + MMCRIR + Ethernet MMC receive interrupt register + (ETH_MMCRIR) + 0x4 + 0x20 + read-only + 0x00000000 + + + RFCES + Received frames CRC error + status + 5 + 1 + + + RGUFS + Received Good Unicast Frames + Status + 17 + 1 + + + + + MMCTIR + MMCTIR + Ethernet MMC transmit interrupt register + (ETH_MMCTIR) + 0x8 + 0x20 + read-only + 0x00000000 + + + TGFS + Transmitted good frames + status + 21 + 1 + + + + + MMCRIMR + MMCRIMR + Ethernet MMC receive interrupt mask register + (ETH_MMCRIMR) + 0xC + 0x20 + read-write + 0x00000000 + + + RFCEM + Received frame CRC error + mask + 5 + 1 + + + RGUFM + Received good unicast frames + mask + 17 + 1 + + + + + MMCTIMR + MMCTIMR + Ethernet MMC transmit interrupt mask + register (ETH_MMCTIMR) + 0x10 + 0x20 + read-write + 0x00000000 + + + TGFM + Transmitted good frames + mask + 21 + 1 + + + + + MMCTGFSCCR + MMCTGFSCCR + Ethernet MMC transmitted good frames after a + single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + Transmitted good frames after a single + collision counter + 0 + 32 + + + + + MMCTGFMSCCR + MMCTGFMSCCR + Ethernet MMC transmitted good frames after + more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + Transmitted good frames after more than + a single collision counter + 0 + 32 + + + + + MMCTGFCR + MMCTGFCR + Ethernet MMC transmitted good frames counter + register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + Transmitted good frames + counter + 0 + 32 + + + + + MMCRFCECR + MMCRFCECR + Ethernet MMC received frames with CRC error + counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCFC + Received frames with CRC error + counter + 0 + 32 + + + + + MMCRFAECR + MMCRFAECR + Ethernet MMC received frames with alignment + error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + Received frames with alignment error + counter + 0 + 32 + + + + + MMCRAFCR + MMCRAFCR + MMC received all frames counter + register + 0x9C + 0x20 + read-only + 0x00000000 + + + RAFCR + Received all frames + counter + 0 + 32 + + + + + MMCRGUFCR + MMCRGUFCR + MMC received good unicast frames counter + register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + Received good unicast frames + counter + 0 + 32 + + + + + + + ETHERNET_PTP + Ethernet: Precision time protocol + ETHERNET + 0x40028700 + + 0x0 + 0x400 + registers + + + + PTPTSCR + PTPTSCR + Ethernet PTP time stamp control register + (ETH_PTPTSCR) + 0x0 + 0x20 + read-write + 0x00000000 + + + TSE + Time stamp enable + 0 + 1 + + + TSFCU + Time stamp fine or coarse + update + 1 + 1 + + + TSSTI + Time stamp system time + initialize + 2 + 1 + + + TSSTU + Time stamp system time + update + 3 + 1 + + + TSITE + Time stamp interrupt trigger + enable + 4 + 1 + + + TSARU + Time stamp addend register + update + 5 + 1 + + + + + PTPSSIR + PTPSSIR + Ethernet PTP subsecond increment + register + 0x4 + 0x20 + read-write + 0x00000000 + + + STSSI + System time subsecond + increment + 0 + 8 + + + + + PTPTSHR + PTPTSHR + Ethernet PTP time stamp high + register + 0x8 + 0x20 + read-only + 0x00000000 + + + STS + System time second + 0 + 32 + + + + + PTPTSLR + PTPTSLR + Ethernet PTP time stamp low register + (ETH_PTPTSLR) + 0xC + 0x20 + read-only + 0x00000000 + + + STSS + System time subseconds + 0 + 31 + + + STPNS + System time positive or negative + sign + 31 + 1 + + + + + PTPTSHUR + PTPTSHUR + Ethernet PTP time stamp high update + register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSUS + Time stamp update second + 0 + 32 + + + + + PTPTSLUR + PTPTSLUR + Ethernet PTP time stamp low update register + (ETH_PTPTSLUR) + 0x14 + 0x20 + read-write + 0x00000000 + + + TSUSS + Time stamp update + subseconds + 0 + 31 + + + TSUPNS + Time stamp update positive or negative + sign + 31 + 1 + + + + + PTPTSAR + PTPTSAR + Ethernet PTP time stamp addend + register + 0x18 + 0x20 + read-write + 0x00000000 + + + TSA + Time stamp addend + 0 + 32 + + + + + PTPTTHR + PTPTTHR + Ethernet PTP target time high + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSH + Target time stamp high + 0 + 32 + + + + + PTPTTLR + PTPTTLR + Ethernet PTP target time low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTSL + Target time stamp low + 0 + 32 + + + + + + + ETHERNET_DMA + Ethernet: DMA controller operation + ETHERNET + 0x40029000 + + 0x0 + 0x400 + registers + + + + DMABMR + DMABMR + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x00000001 + + + SR + Software reset + 0 + 1 + + + DSL + Descriptor skip length + 2 + 5 + + + DFM + Descriptor mode + 7 + 1 + + + ERX_RST + MAC receive reset control + 31 + 1 + + + ETX_RST + MAC sent reset control + 30 + 1 + + + DMARX_RST + DMA receive reset control + 29 + 1 + + + DMATX_RST + DMA sent reset control + 28 + 1 + + + + + DMATPDR + DMATPDR + Ethernet DMA transmit poll demand + register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + Transmit poll demand + 0 + 32 + + + + + DMARPDR + DMARPDR + EHERNET DMA receive poll demand + register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + Receive poll demand + 0 + 32 + + + + + DMARDLAR + DMARDLAR + Ethernet DMA receive descriptor list address + register + 0xC + 0x20 + read-write + 0x00000000 + + + RDLAR + Start of receive list + 0 + 32 + + + + + DMATDLAR + DMATDLAR + Ethernet DMA transmit descriptor list + address register + 0x10 + 0x20 + read-write + 0x00000000 + + + TDLAR + Start of transmit list + 0 + 32 + + + + + DMASR + DMASR + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TS + Transmit status + 0 + 1 + read-write + + + TPSS + Transmit process stopped + status + 1 + 1 + read-write + + + TBUS + Transmit buffer unavailable + status + 2 + 1 + read-write + + + TJTS + Transmit jabber timeout + status + 3 + 1 + read-write + + + ROS + Receive overflow status + 4 + 1 + read-write + + + TUS + Transmit underflow status + 5 + 1 + read-write + + + RS + Receive status + 6 + 1 + read-write + + + RBUS + Receive buffer unavailable + status + 7 + 1 + read-write + + + RPSS + Receive process stopped + status + 8 + 1 + read-write + + + PWTS + Receive watchdog timeout + status + 9 + 1 + read-write + + + ETS + Early transmit status + 10 + 1 + read-write + + + PLS + 10MPHY Physical layer variation + 11 + 1 + read-only + + + ERS + Early receive status + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RPS + Receive process state + 17 + 3 + read-only + + + TPS + Transmit process state + 20 + 3 + read-only + + + EBS + Error bits status + 23 + 3 + read-only + + + MMCS + MMC status + 27 + 1 + read-only + + + PMTS + PMT status + 28 + 1 + read-only + + + TSTS + Time stamp trigger status + 29 + 1 + read-only + + + + + DMAOMR + DMAOMR + Ethernet DMA operation mode + register + 0x18 + 0x20 + read-write + 0x00000000 + + + SR + SR + 1 + 1 + + + FUGF + FUGF + 6 + 1 + + + FEF + FEF + 7 + 1 + + + ST + ST + 13 + 1 + + + FTF + FTF + 20 + 1 + + + TSF + TSF + 21 + 1 + + + DTCEFD + DTCEFD + 26 + 1 + + + + + DMAIER + DMAIER + Ethernet DMA interrupt enable + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TPSIE + Transmit process stopped interrupt + enable + 1 + 1 + + + TBUIE + Transmit buffer unavailable interrupt + enable + 2 + 1 + + + TJTIE + Transmit jabber timeout interrupt + enable + 3 + 1 + + + ROIE + Overflow interrupt enable + 4 + 1 + + + TUIE + Underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUIE + Receive buffer unavailable interrupt + enable + 7 + 1 + + + RPSIE + Receive process stopped interrupt + enable + 8 + 1 + + + RWTIE + receive watchdog timeout interrupt + enable + 9 + 1 + + + ETIE + Early transmit interrupt + enable + 10 + 1 + + + PLE + 10M Physical layer connection + 11 + 1 + + + ERS + Early receive interrupt + enable + 14 + 1 + + + AISE + Abnormal interrupt summary + enable + 15 + 1 + + + NISE + Normal interrupt summary + enable + 16 + 1 + + + + + DMAMFBOCR + DMAMFBOCR + Ethernet DMA missed frame and buffer + overflow counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + MFC + Missed frames by the + controller + 0 + 16 + + + OMFC + Overflow bit for missed frame + counter + 16 + 1 + + + MFA + Missed frames by the + application + 17 + 11 + + + OFOC + Overflow bit for FIFO overflow + counter + 28 + 1 + + + + + DMACHTDR + DMACHTDR + Ethernet DMA current host transmit + descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address + pointer + 0 + 32 + + + + + DMACHRDR + DMACHRDR + Ethernet DMA current host receive descriptor + register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address + pointer + 0 + 32 + + + + + DMACHTBAR + DMACHTBAR + Ethernet DMA current host transmit buffer + address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address + pointer + 0 + 32 + + + + + DMACHRBAR + DMACHRBAR + Ethernet DMA current host receive buffer + address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address + pointer + 0 + 32 + + + + + + + + FLASH + FLASH + FLASH + 0x40022000 + + 0x00 + 0x400 + registers + + + FLASH + Flash global interrupt + 34 + + + + ACTLR + ACTLR + Access control register + 0x00 + 0x20 + 0x00000000 + + + SCK_CFG + Waiting Status + 0 + 2 + read-write + + + ENHANCE_STATUS + Enhanced Status + 6 + 1 + read-only + + + EHMOD + flash enhanced read mode control bit + 7 + 1 + read-write + + + FLASH_LP + FLASH Low Power Mode Control Bit + 8 + 1 + read-write + + + FLASH_READY + flash ready indicator + 14 + 1 + read-only + + + FLASH_ST + FLASH Low Power Status Indicator Bits + 15 + 1 + read-only + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEYR + FPEC key + 0 + 32 + + + + + OBKEYR + OBKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OBTKEY + Option byte key + 0 + 32 + + + + + STATR + STATR + Status register + 0xC + 0x20 + 0x00008000 + + + BOOT_LOCK + BOOT_LOCK + 15 + 1 + read-write + + + BOOT_MODE + BOOT_MODE + 14 + 1 + read-write + + + BOOT_STATUS + BOOT_STATUS + 13 + 1 + read-only + + + BOOT_AVA + BOOT_AVA + 12 + 1 + read-only + + + EOP + End of operation + 5 + 1 + read-write + + + WRPRTERR + Write protection error + 4 + 1 + read-write + + + WRBSY + Quick page programming + 1 + 1 + read-only + + + BSY + Busy + 0 + 1 + read-only + + + + + CTLR + CTLR + Control register + 0x10 + 0x20 + read-write + 0x00008080 + + + PG + Programming + 0 + 1 + + + PER + Page Erase + 1 + 1 + + + OBPG + Option byte programming + 4 + 1 + + + OBER + Option byte erase + 5 + 1 + + + STRT + Start + 6 + 1 + + + LOCK + Lock + 7 + 1 + + + OBWRE + Option bytes write enable + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + EOPIE + End of operation interrupt + enable + 12 + 1 + + + FLOCK + Fast programmable lock + 15 + 1 + + + FTPG + Fast programming + 16 + 1 + + + BER + Block Erase + 18 + 1 + + + PGSTRT + Page Programming Start + 21 + 1 + + + RSENACT + Reset Flash Enhance read mode + 22 + 1 + + + + + ADDR + ADDR + Flash address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FAR + Flash Address + 0 + 32 + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + OBERR + Option byte error + 0 + 1 + + + RDPRT + Read protection + 1 + 1 + + + IWDG_SW + IWDG_SW + 2 + 1 + + + FIX_11 + Fixed to 11 + 8 + 2 + + + DATA0 + Data byte 0 + 10 + 8 + + + DATA1 + Data byte 1 + 18 + 8 + + + + + WPR + WPR + Write protection register + 0x20 + 0x20 + read-only + 0x00000000 + + + WRP + Write protect + 0 + 32 + + + + + MODEKEYR + MODEKEYR + Mode select register + 0x24 + 0x20 + write-only + 0x00000000 + + + MODEKEYR + Mode select + 0 + 32 + + + + + CFGR0 + CFGR0 + FLASH configuration register + 0x2C + 0x20 + read-only + 0x00000000 + + + DBMODE + FLASH Mode status + 28 + 1 + + + + + + + + IPC + Inter-cpre communication + IPC + 0xE000D000 + + 0x0 + 0x1000 + registers + + + IPC_CH0 + IPC global interrupt 0 + 16 + + + IPC_CH1 + IPC global interrupt 1 + 17 + + + IPC_CH2 + IPC global interrupt 2 + 18 + + + IPC_CH3 + IPC global interrupt 3 + 19 + + + + CTLR + CTLR + IPC control register + 0x00 + 0x20 + 0x00000000 + + + TX_CID0 + The ID of the sender kernel to specify the kernel that responds to the sending interrupt + 0 + 1 + read-write + + + RX_CID0 + The ID of the kernel on the receiver side, which is configured to respond to the receive interrupt + 2 + 1 + read-write + + + TX_IER0 + Channel 0 transmitter interrupt is enabled, and channel 0 can generate transmit interrupt when set to 1 + 4 + 1 + read-write + + + RX_IER0 + Channel 0 receiver interrupt is enabled, and channel 0 can generate a receive interrupt when 1 is set + 5 + 1 + read-write + + + AUTOEN0 + The channel 0 status bit enables automatic updates + 6 + 1 + read-write + + + LOCK0 + Channel 0 is configured locked + 7 + 1 + read-write + + + TX_CID1 + The ID of the sender kernel to specify the kernel that responds to the sending interrupt + 8 + 1 + read-write + + + RX_CID1 + The ID of the kernel on the receiver side, which is configured to respond to the receive interrupt + 10 + 1 + read-write + + + TX_IER1 + Channel 1 transmitter interrupt is enabled, and channel 1 can generate a transmit interrupt when 1 is set + 12 + 1 + read-write + + + RX_IER1 + Channel 1 receiver interrupt is enabled, and channel 1 can generate receive interrupt when 1 is set + 13 + 1 + read-write + + + AUTOEN1 + Channel 1 status bits enable automatic updates + 14 + 1 + read-write + + + LOCK1 + Channel 1 configuration locks + 15 + 1 + read-write + + + TX_CID2 + The ID of the sender kernel to specify the kernel that responds to the sending interrupt + 16 + 1 + read-write + + + RX_CID2 + The ID of the kernel on the receiver side, which is configured to respond to the receive interrupt + 18 + 1 + read-write + + + TX_IER2 + Channel 2 transmitter interrupt is enabled, and channel 2 can generate a transmit interrupt when 1 is set + 20 + 1 + read-write + + + RX_IER2 + Channel 2 receiver interrupt is enabled, and channel 2 can generate a receive interrupt when 1 is set + 21 + 1 + read-write + + + AUTOEN2 + Channel 2 status bits are enabled to be updated automatically + 22 + 1 + read-write + + + LOCK2 + Channel 2 configuration locking + 23 + 1 + read-write + + + TX_CID3 + The ID of the sender kernel and the kernel that responds to the send interrupt + 24 + 1 + read-write + + + RX_CID3 + Receiver kernel ID, configure the kernel that responds to receive interrupts + 26 + 1 + read-write + + + TX_IER3 + Channel 3 transmitter interrupt is enabled, and channel 3 can generate a transmit interrupt when 1 is set + 28 + 1 + read-write + + + RX_IER3 + Channel 3 receiver interrupt is enabled, and channel 3 can generate receive interrupt when set to 1 + 29 + 1 + read-write + + + AUTOEN3 + The status bit of channel 3 is automatically updated, when the receiver writes IPC _STS when 1, + the IPC_ENA is automatically updated to the same value, and when the receiver writes IPC_SET to the IPC_STS, + the corresponding position bit is IPC_ENA when the receiver writes to the IPC_STS + 30 + 1 + read-write + + + LOCK3 + Channel 3 is locked, and only reset can be cleared after write 1, + and other control registers of channel 3 cannot be overridden after locking + 31 + 1 + read-write + + + + + ISR + ISR + IPC interrupt status register + 0x4 + 0x20 + 0x00000000 + + + IPC_ISR0 + IPC channel 0 interrupt status register + 0 + 8 + read-only + + + IPC_ISR1 + IPC channel 1 interrupt status register + 8 + 8 + read-only + + + IPC_ISR2 + IPC channel 2 interrupt status register + 16 + 8 + read-only + + + IPC_ISR3 + IPC channel 3 interrupt status register + 24 + 8 + read-only + + + + + ISM + ISM + IPC ISM channel interrupt mask register + 0x8 + 0x20 + 0x00000000 + + + IPC_ISM0 + IPC channel 0 interrupts the mask register + 0 + 8 + read-only + + + IPC_ISM1 + IPC channel 1 interrupts the mask register + 8 + 8 + read-only + + + IPC_ISM2 + IPC channel 2 interrupts the mask register + 16 + 8 + read-only + + + IPC_ISM3 + IPC channel 3 interrupts the mask register + 24 + 8 + read-only + + + + + ENA + ENA + IPC status bit interrupt enable register + 0x10 + 0x20 + 0x00000000 + + + IPC_ENA0 + IPC channel 0 flag interrupt enable register + 0 + 8 + read-write + + + IPC_ENA1 + IPC channel 1 flag interrupt enable register + 8 + 8 + read-write + + + IPC_ENA2 + IPC channel 2 flag interrupt enable register + 16 + 8 + read-write + + + IPC_ENA3 + IPC channel 3 flag interrupt enable register + 24 + 8 + read-write + + + + + STS + STS + IPC channel status registers + 0x14 + 0x20 + 0x00000000 + + + IPC_STS0 + IPC channel 0 status register + 0 + 8 + read-write + + + IPC_STS1 + IPC channel 1 status register + 8 + 8 + read-write + + + IPC_STS2 + IPC channel 2 status register + 16 + 8 + read-write + + + IPC_STS3 + IPC channel 3 status register + 24 + 8 + read-write + + + + + SET + SET + IPC Status Flag Position Bit Register + 0x18 + 0x20 + 0x00000000 + + + IPC_SET0 + IPC channel 0 status flag position bit register + 0 + 8 + write-only + + + IPC_SET1 + IPC channel 1 status flag position bit register + 8 + 8 + write-only + + + IPC_SET2 + IPC channel 2 status flag position bit register + 16 + 8 + write-only + + + IPC_SET3 + IPC channel 3 status flag position bit register + 24 + 8 + write-only + + + + + CLR + CLR + IPC Status Flag Bit Reset Register + 0x1C + 0x20 + 0x00000000 + + + IPC_CLR0 + The status flag of IPC channel 0 clears the register, + and the corresponding bit of the IPC _STS register is reset after writing 1 + 0 + 8 + write-only + + + IPC_CLR1 + The status flag of IPC channel 1 clears the register, + and the corresponding bit of the IPC _STS register is reset after writing 1 + 8 + 8 + write-only + + + IPC_CLR2 + The status flag of IPC channel 2 clears the register, + and the corresponding bit of the IPC _STS register is reset after writing 1 + 16 + 8 + write-only + + + IPC_CLR3 + The status flag of IPC channel 3 clears the register, + and the corresponding bit of the IPC _STS register is reset after writing 1 + 24 + 8 + write-only + + + + + MSG0 + MSG0 + IPC information register + 0x20 + 0x20 + 0x00000000 + + + IPC_MSG0 + IPC information registers are used to store + and transmit information that needs to be passed on for inter-core communication + 0 + 32 + read-write + + + + + MSG1 + MSG1 + IPC information register + 0x24 + 0x20 + 0x00000000 + + + IPC_MSG1 + IPC information registers are used to store + and transmit information that needs to be passed on for inter-core communication + 0 + 32 + read-write + + + + + MSG2 + MSG2 + IPC information register + 0x28 + 0x20 + 0x00000000 + + + IPC_MSG2 + IPC information registers are used to store + and transmit information that needs to be passed on for inter-core communication + 0 + 32 + read-write + + + + + MSG3 + MSG3 + IPC information register + 0x2C + 0x20 + 0x00000000 + + + IPC_MSG3 + IPC information registers are used to store + and transmit information that needs to be passed on for inter-core communication + 0 + 32 + read-write + + + + + + + + STK + SysTick + STK + 0xE000F000 + + 0x00 + 0xFFF + registers + + + + STK_CTLR_0 + STK_CTLR_0 + System count control register 0 + 0x00 + 0x20 + 0x00000000 + + + EN_0 + System counter 0 enable control bit + 0 + 1 + read-write + + + IE_0 + Counter 0 interrupt enable control bit + 1 + 1 + read-write + + + NO_RTC_0 + Counter Clock Source Selection Bit + 2 + 1 + read-write + + + AUTO_RELOAD_0 + Auto Reload Count Enable Bit + 3 + 1 + read-write + + + DOWN_MODE_0 + Counting Mode + 4 + 1 + read-write + + + CID_0 + Counter 0 allocates a kernel register + 6 + 1 + read-write + + + + + STK_ISR + STK_ISR + System counter interrupt status register + 0x04 + 0x20 + 0x00000000 + + + STK_ISR0 + Systick0 Interrupt Flag + 0 + 1 + read-write + + + STK_ISR1 + Systick1 Interrupt Flag + 1 + 1 + read-write + + + + + STK_CNT_0 + STK_CNT_0 + System counter 0 count register + 0x08 + 0x20 + 0x00000000 + + + CNT_0 + Systick0 counter register, counts are enabled and accumulate/subtract and + automatically reload according to configuration + 0 + 32 + read-write + + + + + STK_CMP_0 + STK_CMP_0 + System counter 0 comparison register + 0x10 + 0x20 + 0x00000000 + + + CMP_0 + Systick0 comparison register for automatic reloading + when counting up and comparing when counting down + 0 + 32 + read-write + + + + + STK_CTLR_1 + STK_CTLR_1 + System count control register 1 + 0x80 + 0x20 + 0x00000000 + + + EN_1 + System counter 1 enable control bit + 0 + 1 + read-write + + + IE_1 + Counter 1 interrupt enable control bit + 1 + 1 + read-write + + + NO_RTC_1 + Counter Clock Source Selection Bit + 2 + 1 + read-write + + + AUTO_RELOAD_1 + Auto Reload Count Enable Bit + 3 + 1 + read-write + + + DOWN_MODE_1 + Counting Mode + 4 + 1 + read-write + + + CID_1 + Counter 1 allocates a kernel register + 6 + 1 + read-write + + + + + STK_CNT_1 + STK_CNT_1 + System counter 1 count register + 0x88 + 0x20 + 0x00000000 + + + CNT_1 + Systick1 counter register, counts are enabled and accumulate/subtract and + automatically reload according to configuration + 0 + 32 + read-write + + + + + STK_CMP_1 + STK_CMP_1 + System counter 1 comparison register + 0x90 + 0x20 + 0x00000000 + + + CMP_1 + Systick1 comparison register for automatic reloading + when counting up and comparing when counting down + 0 + 32 + read-write + + + + + + + + HSEM + HSEM + HSEM + 0xE00C000 + + 0x0 + 0x1000 + registers + + + HSEM + HSEM global interrupt + 28 + + + + HSEM_RX0 + HSEM_RX0 + HSEM register HSEM_RX0 HSEM_RX31 + 0x0 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX1 + HSEM_RX1 + HSEM register HSEM_RX0 HSEM_RX31 + 0x4 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX2 + HSEM_RX2 + HSEM register HSEM_RX0 HSEM_RX31 + 0x8 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX3 + HSEM_RX3 + HSEM register HSEM_RX0 HSEM_RX31 + 0xC + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX4 + HSEM_RX4 + HSEM register HSEM_RX0 HSEM_RX31 + 0x10 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX5 + HSEM_RX5 + HSEM register HSEM_RX0 HSEM_RX31 + 0x14 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX6 + HSEM_RX6 + HSEM register HSEM_RX0 HSEM_RX31 + 0x18 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX7 + HSEM_RX7 + HSEM register HSEM_RX0 HSEM_RX31 + 0x1C + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX8 + HSEM_RX8 + HSEM register HSEM_RX0 HSEM_RX31 + 0x20 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX9 + HSEM_RX9 + HSEM register HSEM_RX0 HSEM_RX31 + 0x24 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX10 + HSEM_RX10 + HSEM register HSEM_RX0 HSEM_RX31 + 0x28 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX11 + HSEM_RX11 + HSEM register HSEM_RX0 HSEM_RX31 + 0x2C + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX12 + HSEM_RX12 + HSEM register HSEM_RX0 HSEM_RX31 + 0x30 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX13 + HSEM_RX13 + HSEM register HSEM_RX0 HSEM_RX31 + 0x34 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX14 + HSEM_RX14 + HSEM register HSEM_RX0 HSEM_RX31 + 0x38 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX15 + HSEM_RX15 + HSEM register HSEM_RX0 HSEM_RX31 + 0x3C + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX16 + HSEM_RX16 + HSEM register HSEM_RX0 HSEM_RX31 + 0x40 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX17 + HSEM_RX17 + HSEM register HSEM_RX0 HSEM_RX31 + 0x44 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX18 + HSEM_RX18 + HSEM register HSEM_RX0 HSEM_RX31 + 0x48 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX19 + HSEM_RX19 + HSEM register HSEM_RX0 HSEM_RX31 + 0x4C + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX20 + HSEM_RX20 + HSEM register HSEM_RX0 HSEM_RX31 + 0x50 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX21 + HSEM_RX21 + HSEM register HSEM_RX0 HSEM_RX31 + 0x54 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX22 + HSEM_RX22 + HSEM register HSEM_RX0 HSEM_RX31 + 0x58 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX23 + HSEM_RX23 + HSEM register HSEM_RX0 HSEM_RX31 + 0x5C + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX24 + HSEM_RX24 + HSEM register HSEM_RX0 HSEM_RX31 + 0x60 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX25 + HSEM_RX25 + HSEM register HSEM_RX0 HSEM_RX31 + 0x64 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX26 + HSEM_RX26 + HSEM register HSEM_RX0 HSEM_RX31 + 0x68 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX27 + HSEM_RX27 + HSEM register HSEM_RX0 HSEM_RX31 + 0x6C + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX28 + HSEM_RX28 + HSEM register HSEM_RX0 HSEM_RX31 + 0x70 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX29 + HSEM_RX29 + HSEM register HSEM_RX0 HSEM_RX31 + 0x74 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX30 + HSEM_RX30 + HSEM register HSEM_RX0 HSEM_RX31 + 0x78 + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RX31 + HSEM_RX31 + HSEM register HSEM_RX0 HSEM_RX31 + 0x7C + 0x20 + read-write + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX0 + HSEM_RLRX0 + HSEM Read lock register + 0x100 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX1 + HSEM_RLRX1 + HSEM Read lock register + 0x104 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX2 + HSEM_RLRX2 + HSEM Read lock register + 0x108 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX3 + HSEM_RLRX3 + HSEM Read lock register + 0x10C + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX4 + HSEM_RLRX4 + HSEM Read lock register + 0x110 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX5 + HSEM_RLRX5 + HSEM Read lock register + 0x114 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX6 + HSEM_RLRX6 + HSEM Read lock register + 0x118 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX7 + HSEM_RLRX7 + HSEM Read lock register + 0x11C + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX8 + HSEM_RLRX8 + HSEM Read lock register + 0x120 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX9 + HSEM_RLRX9 + HSEM Read lock register + 0x124 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX10 + HSEM_RLRX10 + HSEM Read lock register + 0x128 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX11 + HSEM_RLRX11 + HSEM Read lock register + 0x12C + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX12 + HSEM_RLRX12 + HSEM Read lock register + 0x130 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX13 + HSEM_RLRX13 + HSEM Read lock register + 0x134 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX14 + HSEM_RLRX14 + HSEM Read lock register + 0x138 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX15 + HSEM_RLRX15 + HSEM Read lock register + 0x13C + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX16 + HSEM_RLRX16 + HSEM Read lock register + 0x140 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX17 + HSEM_RLRX17 + HSEM Read lock register + 0x144 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX18 + HSEM_RLRX18 + HSEM Read lock register + 0x148 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX19 + HSEM_RLRX19 + HSEM Read lock register + 0x14C + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX20 + HSEM_RLRX20 + HSEM Read lock register + 0x150 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX21 + HSEM_RLRX21 + HSEM Read lock register + 0x154 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX22 + HSEM_RLRX22 + HSEM Read lock register + 0x158 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX23 + HSEM_RLRX23 + HSEM Read lock register + 0x15C + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX24 + HSEM_RLRX24 + HSEM Read lock register + 0x160 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX25 + HSEM_RLRX25 + HSEM Read lock register + 0x164 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX26 + HSEM_RLRX26 + HSEM Read lock register + 0x168 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX27 + HSEM_RLRX27 + HSEM Read lock register + 0x16C + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX28 + HSEM_RLRX28 + HSEM Read lock register + 0x170 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX29 + HSEM_RLRX29 + HSEM Read lock register + 0x174 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX30 + HSEM_RLRX30 + HSEM Read lock register + 0x178 + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_RLRX31 + HSEM_RLRX31 + HSEM Read lock register + 0x17C + 0x20 + read-only + 0x00000000 + + + PID + Semaphore ProcessID + 0 + 8 + + + CID + Semaphore CID + 8 + 4 + + + LOCK + Lock indication + 31 + 1 + + + + + HSEM_IER + HSEM_IER + HSEM interrupt enable register + 0x300 + 0x20 + 0x00000000 + + + HSEM_IER + HSEM channel interrupt enable register, kernel private register, + set to 1 when the corresponding channel is unlocked by other cores to allow interrupts. + Interaction with HSEM_ISR registers can produce interrupts + 0 + 32 + read-write + + + + + HSEM_ISR + HSEM_ISR + HSEM interrupt status register + 0x308 + 0x20 + 0x00000000 + + + HSEM_IER + HSEM channel interrupt enable register, kernel private register, + set to 1 when the corresponding channel is unlocked by other cores to allow interrupts. + Interaction with HSEM_ISR registers can produce interrupts + 0 + 32 + read-write + + + + + HSEM_ISM + HSEM_ISM + HSEM interrupt mask register + 0x310 + 0x20 + 0x00000000 + + + HSEM_ISM + HSEM channel lock status registers to obtain the lock status of 32 channels + 0 + 32 + read-only + + + + + HSEM_LSE + HSEM_LSE + HSEM lock status register + 0x200 + 0x20 + 0x00000000 + + + HSEM_LSE + HSEM channel lock status registers to obtain the lock status of 32 channels + 0 + 32 + read-only + + + + + HSEM_LSM + HSEM_LSM + HSEM Lock Status Mask Register + 0x318 + 0x20 + 0x00000000 + + + HSEM_LSE + HSEM channel lock status registers to obtain the lock status of 32 channels + 0 + 32 + read-only + + + + + HSEM_CLR + HSEM_CLR + HSEM Unlock Register + 0x208 + 0x20 + 0x00000000 + + + match_PID + It is used to match the unlocked PID value and compare it with the PID value of each locked channel + 0 + 8 + write-only + + + match_CID + It is used to match the unlocked CID value and compare it with the CID value of each locked channel + 8 + 2 + write-only + + + PID_MASK + PID Matching Shielding + 12 + 1 + write-only + + + CID_MASK + CID Matching Shielding + 13 + 1 + write-only + + + CLR_KEY + Unlock keywords, the operation is valid + when the write data is equal to the matching keyword, + otherwise it is invalid. The key value is 0x5AA5 + 16 + 16 + write-only + + + + + HSEM_KEY + HSEM_KEY + HSEM unlocks the keyword register + 0x20C + 0x20 + 0x00000000 + + + auto_1step_clr + When the channel is locked in 1step mode, + the corresponding channel interrupt status bit is automatically cleared. + 0 + 1 + read-write + + + auto_2step_clr + When the channel is locked in 2step mode, + the corresponding channel interrupt status bit is automatically cleared. + 1 + 1 + read-write + + + KEY_VALUE + Unlock keywords, which are used to match unlock method keyword comparisons. + 16 + 16 + read-only + + + + + + + + PFIC + Programmable Fast Interrupt + Controller + PFIC + 0xE000E000 + + 0x00 + 0x1000 + registers + + + + ISR1 + ISR1 + Interrupt Status + Register + 0x00 + 0x20 + read-only + 0x0000000C + + + INTENSTA2_3 + Interrupt ID Status + 2 + 2 + + + INTENSTA5 + Interrupt ID Status + 5 + 1 + + + INTENSTA8_9 + Interrupt ID Status + 8 + 2 + + + INTENSTA12_31 + Interrupt ID Status + 12 + 20 + + + + + ISR2 + ISR2 + Interrupt Status + Register + 0x04 + 0x20 + read-only + 0x00000000 + + + INTENSTA + Interrupt ID Status + 0 + 32 + + + + + ISR3 + ISR3 + Interrupt Status + Register + 0x08 + 0x20 + read-only + 0x00000000 + + + INTENSTA + Interrupt ID Status + 0 + 32 + + + + + ISR4 + ISR4 + Interrupt Status + Register + 0x0C + 0x20 + read-only + 0x00000000 + + + INTENSTA + Interrupt ID Status + 0 + 32 + + + + + ISR5 + ISR5 + Interrupt Status + Register + 0x10 + 0x20 + read-only + 0x00000000 + + + INTENSTA + Interrupt ID Status + 0 + 20 + + + + + IPR1 + IPR1 + Interrupt Pending Register + 0x20 + 0x20 + read-only + 0x00000000 + + + PENDSTA2_3 + PENDSTA + 2 + 2 + + + PENDSTA5 + PENDSTA + 5 + 1 + + + INTENSTA8_9 + PENDSTA + 8 + 2 + + + INTENSTA12_31 + PENDSTA + 12 + 20 + + + + + IPR2 + IPR2 + Interrupt Pending Register + 0x24 + 0x20 + read-only + 0x00000000 + + + PENDSTA + PENDSTA + 0 + 32 + + + + + IPR3 + IPR3 + Interrupt Pending Register + 0x28 + 0x20 + read-only + 0x00000000 + + + PENDSTA + PENDSTA + 0 + 32 + + + + + IPR4 + IPR4 + Interrupt Pending Register + 0x2C + 0x20 + read-only + 0x00000000 + + + PENDSTA + PENDSTA + 0 + 32 + + + + + IPR5 + IPR5 + Interrupt Pending Register + 0x30 + 0x20 + read-only + 0x00000000 + + + PENDSTA + PENDSTA + 0 + 20 + + + + + ITHRESDR + ITHRESDR + Interrupt Priority + Register + 0x40 + 0x20 + read-write + 0x00000000 + + + THRESHOLD + THRESHOLD + 0 + 8 + + + + + CFGR + CFGR + Interrupt configuration register + 0x48 + 0x20 + 0x00000000 + + + SYSRST + System reset register + 7 + 1 + write-only + + + KEYCODE + KEYCODE + 16 + 16 + write-only + + + + + GISR + GISR + Interrupt Global Register + 0x4C + 0x20 + read-only + 0x00000000 + + + NESTSTA + interrupt nesting + 0 + 8 + + + GACTSTA + interrupt execution + 8 + 1 + + + GPENDSTA + interrupt pending + 9 + 1 + + + GLOBL_IE + global interrupt enable + 11 + 1 + + + DBG_MODE + debug mode + 12 + 1 + + + LOCK_UP + lock-out state + 13 + 1 + + + EX_STATE + The kernel status register, which is used to obtain the running state of the kernel + 14 + 2 + + + + + VTFIDR + VTFIDR + ID Config Register + 0x50 + 0x20 + read-write + 0x00000000 + + + VTFID0 + VTFID0 + 0 + 8 + + + VTFID1 + VTFID1 + 8 + 8 + + + VTFID2 + VTFID2 + 16 + 8 + + + VTFID3 + VTFID3 + 24 + 8 + + + + + VTFADDRR0 + VTFADDRR0 + Interrupt 0 address + Register + 0x60 + 0x20 + read-write + 0x00000000 + + + VTF0EN + VTF0EN + 0 + 1 + + + ADDR0 + ADDR0 + 1 + 31 + + + + + VTFADDRR1 + VTFADDRR1 + Interrupt 1 address + Register + 0x64 + 0x20 + read-write + 0x00000000 + + + VTF1EN + VTF1EN + 0 + 1 + + + ADDR1 + ADDR1 + 1 + 31 + + + + + VTFADDRR2 + VTFADDRR2 + Interrupt 2 address + Register + 0x68 + 0x20 + read-write + 0x00000000 + + + VTF2EN + VTF2EN + 0 + 1 + + + ADDR2 + ADDR2 + 1 + 31 + + + + + VTFADDRR3 + VTFADDRR3 + Interrupt 3 address + Register + 0x6C + 0x20 + read-write + 0x00000000 + + + VTF3EN + VTF3EN + 0 + 1 + + + ADDR3 + ADDR3 + 1 + 31 + + + + + IENR1 + IENR1 + Interrupt Setting Register + 0x100 + 0x20 + write-only + 0x00000000 + + + INTEN12_31 + INTEN12_31 + 12 + 20 + + + + + IENR2 + IENR2 + Interrupt Setting Register + 0x104 + 0x20 + write-only + 0x00000000 + + + INTEN + INTEN + 0 + 32 + + + + + IENR3 + IENR3 + Interrupt Setting Register + 0x108 + 0x20 + write-only + 0x00000000 + + + INTEN + INTEN + 0 + 32 + + + + + IENR4 + IENR4 + Interrupt Setting Register + 0x10C + 0x20 + write-only + 0x00000000 + + + INTEN + INTEN + 0 + 32 + + + + + IENR5 + IENR5 + Interrupt Setting Register + 0x110 + 0x20 + write-only + 0x00000000 + + + INTEN + INTEN + 0 + 20 + + + + + IRER1 + IRER1 + Interrupt Clear Register + 0x180 + 0x20 + write-only + 0x00000000 + + + INTRSET12_31 + INTRSET12_31 + 12 + 20 + + + + + IRER2 + IRER2 + Interrupt Clear Register + 0x184 + 0x20 + write-only + 0x00000000 + + + INTRSET + INTRSET + 0 + 32 + + + + + IRER3 + IRER3 + Interrupt Clear Register + 0x188 + 0x20 + write-only + 0x00000000 + + + INTRSET + INTRSET + 0 + 32 + + + + + IRER4 + IRER4 + Interrupt Clear Register + 0x18C + 0x20 + write-only + 0x00000000 + + + INTRSET + INTRSET + 0 + 32 + + + + + IRER5 + IRER5 + Interrupt Clear Register + 0x190 + 0x20 + write-only + 0x00000000 + + + INTRSET + INTRSET + 0 + 20 + + + + + IPSR1 + IPSR1 + Interrupt Pending Register + 0x200 + 0x20 + write-only + 0x00000000 + + + PENDSET2_3 + PENDSET + 2 + 2 + + + PENDSET5 + PENDSET + 5 + 1 + + + PENDSET8_9 + PENDSET + 8 + 2 + + + PENDSET12_31 + PENDSET + 12 + 20 + + + + + IPSR2 + IPSR2 + Interrupt Pending Register + 0x204 + 0x20 + write-only + 0x00000000 + + + PENDSET + PENDSET + 0 + 32 + + + + + IPSR3 + IPSR3 + Interrupt Pending Register + 0x208 + 0x20 + write-only + 0x00000000 + + + PENDSET + PENDSET + 0 + 32 + + + + + IPSR4 + IPSR4 + Interrupt Pending Register + 0x20C + 0x20 + write-only + 0x00000000 + + + PENDSET + PENDSET + 0 + 32 + + + + + IPSR5 + IPSR5 + Interrupt Pending Register + 0x210 + 0x20 + write-only + 0x00000000 + + + PENDSET + PENDSET + 0 + 20 + + + + + IPRR1 + IPRR1 + Interrupt Pending Clear Register + 0x280 + 0x20 + write-only + 0x00000000 + + + PENDRST2_3 + PENDRESET + 2 + 2 + + + PENDRST5 + PENDRESET + 5 + 1 + + + PENDRST8 + PENDRESET + 8 + 2 + + + PENDRST12_31 + PENDRESET + 12 + 20 + + + + + IPRR2 + IPRR2 + Interrupt Pending Clear Register + 0x284 + 0x20 + write-only + 0x00000000 + + + PENDRST + PENDRESET + 0 + 32 + + + + + IPRR3 + IPRR3 + Interrupt Pending Clear Register + 0x288 + 0x20 + write-only + 0x00000000 + + + PENDRST + PENDRESET + 0 + 32 + + + + + IPRR4 + IPRR4 + Interrupt Pending Clear Register + 0x28C + 0x20 + write-only + 0x00000000 + + + PENDRST + PENDRESET + 0 + 32 + + + + + IPRR5 + IPRR5 + Interrupt Pending Clear Register + 0x290 + 0x20 + write-only + 0x00000000 + + + PENDRST + PENDRESET + 0 + 20 + + + + + IACTR1 + IACTR1 + Interrupt ACTIVE Register + 0x300 + 0x20 + write-only + 0x00000000 + + + IACTS2_3 + IACTS + 2 + 2 + + + IACTS5 + IACTS + 5 + 1 + + + IACTS8_9 + IACTS + 8 + 2 + + + IACTS12_31 + IACTS + 12 + 20 + + + + + IACTR2 + IACTR2 + Interrupt ACTIVE Register + 0x304 + 0x20 + write-only + 0x00000000 + + + IACTS + IACTS + 0 + 32 + + + + + IACTR3 + IACTR3 + Interrupt ACTIVE Register + 0x308 + 0x20 + write-only + 0x00000000 + + + IACTS + IACTS + 0 + 32 + + + + + IACTR4 + IACTR4 + Interrupt ACTIVE Register + 0x30C + 0x20 + write-only + 0x00000000 + + + IACTS + IACTS + 0 + 32 + + + + + IACTR5 + IACTR5 + Interrupt ACTIVE Register + 0x310 + 0x20 + write-only + 0x00000000 + + + IACTS + IACTS + 0 + 20 + + + + + IPRIOR0 + IPRIOR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPRIOR1 + IPRIOR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPRIOR2 + IPRIOR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPRIOR3 + IPRIOR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPRIOR4 + IPRIOR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPRIOR5 + IPRIOR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPRIOR6 + IPRIOR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPRIOR7 + IPRIOR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPRIOR8 + IPRIOR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPRIOR9 + IPRIOR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPRIOR10 + IPRIOR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + + IPRIOR11 + IPRIOR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPRIOR12 + IPRIOR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPRIOR13 + IPRIOR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPRIOR14 + IPRIOR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPRIOR15 + IPRIOR15 + Interrupt Priority Register + 0x43C + 0x20 + read-write + 0x00000000 + + + IPRIOR16 + IPRIOR6 + Interrupt Priority Register + 0x440 + 0x20 + read-write + 0x00000000 + + + IPRIOR17 + IPRIOR7 + Interrupt Priority Register + 0x444 + 0x20 + read-write + 0x00000000 + + + IPRIOR18 + IPRIOR8 + Interrupt Priority Register + 0x448 + 0x20 + read-write + 0x00000000 + + + IPRIOR19 + IPRIOR9 + Interrupt Priority Register + 0x44C + 0x20 + read-write + 0x00000000 + + + IPRIOR20 + IPRIOR20 + Interrupt Priority Register + 0x450 + 0x20 + read-write + 0x00000000 + + + + IPRIOR21 + IPRIOR21 + Interrupt Priority Register + 0x454 + 0x20 + read-write + 0x00000000 + + + IPRIOR22 + IPRIOR22 + Interrupt Priority Register + 0x458 + 0x20 + read-write + 0x00000000 + + + IPRIOR23 + IPRIOR23 + Interrupt Priority Register + 0x45C + 0x20 + read-write + 0x00000000 + + + IPRIOR24 + IPRIOR24 + Interrupt Priority Register + 0x460 + 0x20 + read-write + 0x00000000 + + + IPRIOR25 + IPRIOR25 + Interrupt Priority Register + 0x464 + 0x20 + read-write + 0x00000000 + + + IPRIOR26 + IPRIOR26 + Interrupt Priority Register + 0x468 + 0x20 + read-write + 0x00000000 + + + IPRIOR27 + IPRIOR27 + Interrupt Priority Register + 0x46C + 0x20 + read-write + 0x00000000 + + + IPRIOR28 + IPRIOR28 + Interrupt Priority Register + 0x470 + 0x20 + read-write + 0x00000000 + + + IPRIOR29 + IPRIOR29 + Interrupt Priority Register + 0x474 + 0x20 + read-write + 0x00000000 + + + + IPRIOR30 + IPRIOR30 + Interrupt Priority Register + 0x478 + 0x20 + read-write + 0x00000000 + + + IPRIOR31 + IPRIOR31 + Interrupt Priority Register + 0x47C + 0x20 + read-write + 0x00000000 + + + IPRIOR32 + IPRIOR32 + Interrupt Priority Register + 0x480 + 0x20 + read-write + 0x00000000 + + + IPRIOR33 + IPRIOR33 + Interrupt Priority Register + 0x484 + 0x20 + read-write + 0x00000000 + + + IPRIOR34 + IPRIOR34 + Interrupt Priority Register + 0x488 + 0x20 + read-write + 0x00000000 + + + IPRIOR35 + IPRIOR35 + Interrupt Priority Register + 0x48C + 0x20 + read-write + 0x00000000 + + + IPRIOR36 + IPRIOR36 + Interrupt Priority Register + 0x490 + 0x20 + read-write + 0x00000000 + + + IPRIOR37 + IPRIOR37 + Interrupt Priority Register + 0x494 + 0x20 + read-write + 0x00000000 + + + IPRIOR38 + IPRIOR38 + Interrupt Priority Register + 0x498 + 0x20 + read-write + 0x00000000 + + + IPRIOR39 + IPRIOR39 + Interrupt Priority Register + 0x49C + 0x20 + read-write + 0x00000000 + + + + IPRIOR40 + IPRIOR40 + Interrupt Priority Register + 0x4A0 + 0x20 + read-write + 0x00000000 + + + IPRIOR41 + IPRIOR41 + Interrupt Priority Register + 0x4A4 + 0x20 + read-write + 0x00000000 + + + IPRIOR42 + IPRIOR42 + Interrupt Priority Register + 0x4A8 + 0x20 + read-write + 0x00000000 + + + IPRIOR43 + IPRIOR43 + Interrupt Priority Register + 0x4AC + 0x20 + read-write + 0x00000000 + + + IPRIOR44 + IPRIOR44 + Interrupt Priority Register + 0x4B0 + 0x20 + read-write + 0x00000000 + + + IPRIOR45 + IPRIOR45 + Interrupt Priority Register + 0x4B4 + 0x20 + read-write + 0x00000000 + + + IPRIOR46 + IPRIOR46 + Interrupt Priority Register + 0x4B8 + 0x20 + read-write + 0x00000000 + + + IPRIOR47 + IPRIOR47 + Interrupt Priority Register + 0x4BC + 0x20 + read-write + 0x00000000 + + + IPRIOR48 + IPRIOR48 + Interrupt Priority Register + 0x4C0 + 0x20 + read-write + 0x00000000 + + + IPRIOR49 + IPRIOR49 + Interrupt Priority Register + 0x4C4 + 0x20 + read-write + 0x00000000 + + + + IPRIOR50 + IPRIOR50 + Interrupt Priority Register + 0x4C8 + 0x20 + read-write + 0x00000000 + + + IPRIOR51 + IPRIOR51 + Interrupt Priority Register + 0x4CC + 0x20 + read-write + 0x00000000 + + + IPRIOR52 + IPRIOR52 + Interrupt Priority Register + 0x4D0 + 0x20 + read-write + 0x00000000 + + + IPRIOR53 + IPRIOR53 + Interrupt Priority Register + 0x4D4 + 0x20 + read-write + 0x00000000 + + + IPRIOR54 + IPRIOR54 + Interrupt Priority Register + 0x4D8 + 0x20 + read-write + 0x00000000 + + + IPRIOR55 + IPRIOR55 + Interrupt Priority Register + 0x4DC + 0x20 + read-write + 0x00000000 + + + IPRIOR56 + IPRIOR56 + Interrupt Priority Register + 0x4E0 + 0x20 + read-write + 0x00000000 + + + IPRIOR57 + IPRIOR57 + Interrupt Priority Register + 0x4E4 + 0x20 + read-write + 0x00000000 + + + IPRIOR58 + IPRIOR58 + Interrupt Priority Register + 0x4E8 + 0x20 + read-write + 0x00000000 + + + IPRIOR59 + IPRIOR59 + Interrupt Priority Register + 0x4EC + 0x20 + read-write + 0x00000000 + + + + IPRIOR60 + IPRIOR60 + Interrupt Priority Register + 0x4F0 + 0x20 + read-write + 0x00000000 + + + IPRIOR61 + IPRIOR61 + Interrupt Priority Register + 0x4F4 + 0x20 + read-write + 0x00000000 + + + IPRIOR62 + IPRIOR62 + Interrupt Priority Register + 0x4F8 + 0x20 + read-write + 0x00000000 + + + IPRIOR63 + IPRIOR63 + Interrupt Priority Register + 0x4FC + 0x20 + read-write + 0x00000000 + + + + IALLOCR0 + IALLOCR0 + Interrupt Allocation Register + 0x600 + 0x20 + read-only + 0x00000000 + + + IALLOCR1 + IALLOCR1 + Interrupt Allocation Register + 0x604 + 0x20 + read-only + 0x00000000 + + + IALLOCR2 + IALLOCR2 + Interrupt Allocation Register + 0x608 + 0x20 + read-only + 0x00000000 + + + IALLOCR3 + IALLOCR3 + Interrupt Allocation Register + 0x60C + 0x20 + read-only + 0x00000000 + + + IALLOCR4 + IALLOCR4 + Interrupt Allocation Register + 0x610 + 0x20 + read-only + 0x00000000 + + + IALLOCR5 + IALLOCR5 + Interrupt Allocation Register + 0x614 + 0x20 + read-only + 0x00000000 + + + IALLOCR6 + IALLOCR6 + Interrupt Allocation Register + 0x618 + 0x20 + read-only + 0x00000000 + + + IALLOCR7 + IALLOCR7 + Interrupt Allocation Register + 0x61C + 0x20 + read-only + 0x00000000 + + + IALLOCR8 + IALLOCR8 + Interrupt Allocation Register + 0x620 + 0x20 + read-only + 0x00000000 + + + IALLOCR9 + IALLOCR9 + Interrupt Allocation Register + 0x624 + 0x20 + read-only + 0x00000000 + + + IALLOCR10 + IALLOCR10 + Interrupt Allocation Register + 0x628 + 0x20 + read-only + 0x00000000 + + + + IALLOCR11 + IALLOCR11 + Interrupt Allocation Register + 0x62C + 0x20 + read-only + 0x00000000 + + + IALLOCR12 + IALLOCR12 + Interrupt Allocation Register + 0x630 + 0x20 + read-only + 0x00000000 + + + IALLOCR13 + IALLOCR13 + Interrupt Allocation Register + 0x634 + 0x20 + read-only + 0x00000000 + + + IALLOCR14 + IALLOCR14 + Interrupt Allocation Register + 0x638 + 0x20 + read-only + 0x00000000 + + + IALLOCR15 + IALLOCR15 + Interrupt Allocation Register + 0x63C + 0x20 + read-only + 0x00000000 + + + IALLOCR16 + IALLOCR6 + Interrupt Allocation Register + 0x640 + 0x20 + read-only + 0x00000000 + + + IALLOCR17 + IALLOCR7 + Interrupt Allocation Register + 0x644 + 0x20 + read-only + 0x00000000 + + + IALLOCR18 + IALLOCR8 + Interrupt Allocation Register + 0x648 + 0x20 + read-only + 0x00000000 + + + IALLOCR19 + IALLOCR9 + Interrupt Allocation Register + 0x64C + 0x20 + read-only + 0x00000000 + + + IALLOCR20 + IALLOCR20 + Interrupt Allocation Register + 0x650 + 0x20 + read-only + 0x00000000 + + + + IALLOCR21 + IALLOCR21 + Interrupt Allocation Register + 0x654 + 0x20 + read-only + 0x00000000 + + + IALLOCR22 + IALLOCR22 + Interrupt Allocation Register + 0x658 + 0x20 + read-only + 0x00000000 + + + IALLOCR23 + IALLOCR23 + Interrupt Allocation Register + 0x65C + 0x20 + read-only + 0x00000000 + + + IALLOCR24 + IALLOCR24 + Interrupt Allocation Register + 0x660 + 0x20 + read-only + 0x00000000 + + + IALLOCR25 + IALLOCR25 + Interrupt Allocation Register + 0x664 + 0x20 + read-only + 0x00000000 + + + IALLOCR26 + IALLOCR26 + Interrupt Allocation Register + 0x668 + 0x20 + read-only + 0x00000000 + + + IALLOCR27 + IALLOCR27 + Interrupt Allocation Register + 0x66C + 0x20 + read-only + 0x00000000 + + + IALLOCR28 + IALLOCR28 + Interrupt Allocation Register + 0x670 + 0x20 + read-only + 0x00000000 + + + IALLOCR29 + IALLOCR29 + Interrupt Allocation Register + 0x674 + 0x20 + read-only + 0x00000000 + + + + IALLOCR30 + IALLOCR30 + Interrupt Allocation Register + 0x678 + 0x20 + read-only + 0x00000000 + + + IALLOCR31 + IALLOCR31 + Interrupt Allocation Register + 0x67C + 0x20 + read-only + 0x00000000 + + + IALLOCR32 + IALLOCR32 + Interrupt Allocation Register + 0x680 + 0x20 + read-write + 0x00000000 + + + IALLOCR33 + IALLOCR33 + Interrupt Allocation Register + 0x684 + 0x20 + read-write + 0x00000000 + + + IALLOCR34 + IALLOCR34 + Interrupt Allocation Register + 0x688 + 0x20 + read-write + 0x00000000 + + + IALLOCR35 + IALLOCR35 + Interrupt Allocation Register + 0x68C + 0x20 + read-write + 0x00000000 + + + IALLOCR36 + IALLOCR36 + Interrupt Allocation Register + 0x690 + 0x20 + read-write + 0x00000000 + + + IALLOCR37 + IALLOCR37 + Interrupt Allocation Register + 0x694 + 0x20 + read-write + 0x00000000 + + + IALLOCR38 + IALLOCR38 + Interrupt Allocation Register + 0x698 + 0x20 + read-write + 0x00000000 + + + IALLOCR39 + IALLOCR39 + Interrupt Allocation Register + 0x69C + 0x20 + read-write + 0x00000000 + + + + IALLOCR40 + IALLOCR40 + Interrupt Allocation Register + 0x6A0 + 0x20 + read-write + 0x00000000 + + + IALLOCR41 + IALLOCR41 + Interrupt Allocation Register + 0x6A4 + 0x20 + read-write + 0x00000000 + + + IALLOCR42 + IALLOCR42 + Interrupt Allocation Register + 0x6A8 + 0x20 + read-write + 0x00000000 + + + IALLOCR43 + IALLOCR43 + Interrupt Allocation Register + 0x6AC + 0x20 + read-write + 0x00000000 + + + IALLOCR44 + IALLOCR44 + Interrupt Allocation Register + 0x6B0 + 0x20 + read-write + 0x00000000 + + + IALLOCR45 + IALLOCR45 + Interrupt Allocation Register + 0x6B4 + 0x20 + read-write + 0x00000000 + + + IALLOCR46 + IALLOCR46 + Interrupt Allocation Register + 0x6B8 + 0x20 + read-write + 0x00000000 + + + IALLOCR47 + IALLOCR47 + Interrupt Allocation Register + 0x6BC + 0x20 + read-write + 0x00000000 + + + IALLOCR48 + IALLOCR48 + Interrupt Allocation Register + 0x6C0 + 0x20 + read-write + 0x00000000 + + + IALLOCR49 + IALLOCR49 + Interrupt Allocation Register + 0x6C4 + 0x20 + read-write + 0x00000000 + + + + IALLOCR50 + IALLOCR50 + Interrupt Allocation Register + 0x6C8 + 0x20 + read-write + 0x00000000 + + + IALLOCR51 + IALLOCR51 + Interrupt Allocation Register + 0x6CC + 0x20 + read-write + 0x00000000 + + + IALLOCR52 + IALLOCR52 + Interrupt Allocation Register + 0x6D0 + 0x20 + read-write + 0x00000000 + + + IALLOCR53 + IALLOCR53 + Interrupt Allocation Register + 0x6D4 + 0x20 + read-write + 0x00000000 + + + IALLOCR54 + IALLOCR54 + Interrupt Allocation Register + 0x6D8 + 0x20 + read-write + 0x00000000 + + + IALLOCR55 + IALLOCR55 + Interrupt Allocation Register + 0x6DC + 0x20 + read-write + 0x00000000 + + + IALLOCR56 + IALLOCR56 + Interrupt Allocation Register + 0x6E0 + 0x20 + read-write + 0x00000000 + + + IALLOCR57 + IALLOCR57 + Interrupt Allocation Register + 0x6E4 + 0x20 + read-write + 0x00000000 + + + IALLOCR58 + IALLOCR58 + Interrupt Allocation Register + 0x6E8 + 0x20 + read-write + 0x00000000 + + + IALLOCR59 + IALLOCR59 + Interrupt Allocation Register + 0x6EC + 0x20 + read-write + 0x00000000 + + + + IALLOCR60 + IALLOCR60 + Interrupt Allocation Register + 0x6F0 + 0x20 + read-write + 0x00000000 + + + IALLOCR61 + IALLOCR61 + Interrupt Allocation Register + 0x6F4 + 0x20 + read-write + 0x00000000 + + + IALLOCR62 + IALLOCR62 + Interrupt Allocation Register + 0x6F8 + 0x20 + read-write + 0x00000000 + + + IALLOCR63 + IALLOCR63 + Interrupt Allocation Register + 0x6FC + 0x20 + read-write + 0x00000000 + + + IAUTR1 + IAUTR1 + interrupts authority register 1 + 0x700 + 0x20 + 0x00000000 + + + IAUT + interrupt allocates all registers + and is used to query whether the interrupt responds to each kernel allocation + 0 + 32 + read-only + + + + + IAUTR2 + IAUTR2 + interrupts authority register 2 + 0x704 + 0x20 + 0x00000000 + + + IAUT + interrupt allocates all registers + and is used to query whether the interrupt responds to each kernel allocation + 0 + 32 + read-only + + + + + IAUTR3 + IAUTR3 + interrupts authority register 3 + 0x708 + 0x20 + 0x00000000 + + + IAUT + interrupt allocates all registers + and is used to query whether the interrupt responds to each kernel allocation + 0 + 32 + read-only + + + + + IAUTR4 + IAUTR4 + interrupts authority register 4 + 0x70C + 0x20 + 0x00000000 + + + IAUT + interrupt allocates all registers + and is used to query whether the interrupt responds to each kernel allocation + 0 + 32 + read-only + + + + + IAUTR5 + IAUTR5 + interrupts authority register 5 + 0x710 + 0x20 + 0x00000000 + + + IAUT + interrupt allocates all registers + and is used to query whether the interrupt responds to each kernel allocation + 0 + 32 + read-only + + + + + WAKEIP0 + WAKEIP0 + PFIC wake-up instruction pointer register 0 + 0x720 + 0x20 + 0x00000000 + + + IP_RELOAD0 + The PC address register on kernel C0 wake-up, + which is used to reload the PC value after power-on wake-up and reset wake-up + 1 + 31 + read-write + + + SHUTDOWN0 + Kernel C0 Deep Sleep (Locked) Cancellation Register + 0 + 1 + read-write + + + + + WAKEIP1 + WAKEIP1 + PFIC wake-up instruction pointer register 1 + 0x724 + 0x20 + 0x00000000 + + + IP_RELOAD1 + The PC address register on kernel C1 wake-up, + which is used to reload the PC value after power-on wake-up and reset wake-up + 1 + 31 + read-write + + + SHUTDOWN1 + Kernel C1 Deep Sleep (Locked) Cancellation Register + 0 + 1 + read-write + + + + + CSTAR0 + CSTAR0 + PFIC kernel status register 0 + 0x780 + 0x20 + 0x00000000 + + + CPU_nest_sta_0 + The nested status register of kernel C0 interrupts is used to + query the nested state of kernel C0 interrupts. nest_sta bits from the INEST_CTLR register of the CSR register + 0 + 8 + read-only + + + CPU_irq_active_0 + Kernel C0 interrupt active flag register, + which is used to query whether kernel C0 is processing interrupts + 8 + 1 + read-only + + + CPU_irq_pend_0 + Kernel C0 interrupt pending flag register, which is used to query kernel C1 for unhandled interrupts + 9 + 1 + read-only + + + CPU_globl_ie_0 + The kernel C0 global interrupt enable register is used to + query whether the kernel C0 global interrupt is enabled + 11 + 1 + read-only + + + CPU_dbg_mode_0 + Kernel C0 debug mode register, which is used to query whether kernel C0 is in debug mode + 12 + 1 + read-only + + + CPU_lock_up_0 + The kernel C0 lock status register is used to query whether kernel C0 is in the locked state + 13 + 1 + read-only + + + CPU_ex_state_0 + The kernel C0 status register is used to obtain the running state of kernel C0 + 14 + 2 + read-only + + + + + CSTAR1 + CSTAR1 + PFIC kernel status register 1 + 0x784 + 0x20 + 0x00000000 + + + CPU_nest_sta_1 + The nested status register of kernel C1 interrupts is used to + query the nested state of kernel C1 interrupts. nest_sta bits from the INEST_CTLR register of the CSR register + 0 + 8 + read-only + + + CPU_irq_active_1 + Kernel C1 interrupt active flag register, + which is used to query whether kernel C1 is processing interrupts + 8 + 1 + read-only + + + CPU_irq_pend_1 + Kernel C1 interrupt pending flag register, which is used to query kernel C1 for unhandled interrupts + 9 + 1 + read-only + + + CPU_globl_ie_1 + The kernel C1 global interrupt enable register is used to + query whether the kernel C1 global interrupt is enabled + 11 + 1 + read-only + + + CPU_dbg_mode_1 + Kernel C1 debug mode register, which is used to query whether kernel C1 is in debug mode + 12 + 1 + read-only + + + CPU_lock_up_1 + The kernel C1 lock status register is used to query whether kernel C1 is in the locked state + 13 + 1 + read-only + + + CPU_ex_state_1 + The kernel C1 status register is used to obtain the running state of kernel C1 + 14 + 2 + read-only + + + + + EENR + EENR + PFIC Event Enable Register + 0xC80 + 0x20 + 0xFFFFFFFF + + + EVENTEN + 31-0 Event wake-up enabled + 0 + 31 + read-write + + + + + EPR + EPR + PFIC Event Suspend Register + 0xC84 + 0x20 + 0x00000000 + + + EVENT_PEND31_8 + 31-8 event is suspended, write 1 to clear zero + 8 + 24 + read-write + + + EVENT_PEND7_0 + 7-0 Event Pending Status, Not Clearable + 0 + 8 + read-only + + + + + EWUPR + EWUPR + PFIC Event Wake Register + 0xC88 + 0x20 + 0x00000000 + + + EVENT_WUP + 31-0 Event Wake Register + 0 + 32 + read-only + + + + + SCTLR + SCTLR + System Control Register + 0xD10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + system leaves the state after an interruption + 1 + 1 + + + SLEEPDEEP + low power mode selection + 2 + 1 + + + WFITOWFE + ues WFI as WFE + 3 + 1 + + + SEVONPEND + SEVONPEND + 4 + 1 + + + SETEVENT + set event + 5 + 1 + + + HART_ID + Kernel ID register, + which is used to obtain the kernel ID of the reader register + 16 + 8 + + + SYSRST + System reset + 31 + 1 + + + + + + + + \ No newline at end of file diff --git a/port/wch/ch32h/src/cpus/main.zig b/port/wch/ch32h/src/cpus/main.zig new file mode 100644 index 000000000..52f8befff --- /dev/null +++ b/port/wch/ch32h/src/cpus/main.zig @@ -0,0 +1,542 @@ +const std = @import("std"); +const microzig = @import("microzig"); + +const riscv32_common = @import("riscv32-common"); +const cpu_impl = @import("cpu_impl"); + +const peripherals = microzig.chip.peripherals; +const PFIC = peripherals.PFIC; + +pub const cpu_frequency = cpu_impl.cpu_frequency; + +pub const CpuName = enum { + /// CH32H417 CORE0 (control-oriented, up to 150 MHz) + qingkev3f, + /// CH32H417 CORE1 (out-of-order superscalar, up to 400 MHz) + qingkev5f, +}; +pub const cpu_name: CpuName = std.meta.stringToEnum(CpuName, microzig.config.cpu_name) orelse @compileError("Unknown CPU name: " ++ microzig.config.cpu_name); + +// Interrupt + +pub const Interrupt = cpu_impl.Interrupt; +pub const riscv_calling_convention: std.builtin.CallingConvention = .{ .riscv32_interrupt = .{ .mode = .machine } }; +pub const Exception = enum(u32) { + InstructionMisaligned = 0x0, + InstructionFault = 0x1, + IllegalInstruction = 0x2, + Breakpoint = 0x3, + LoadMisaligned = 0x4, + LoadFault = 0x5, + StoreMisaligned = 0x6, + StoreFault = 0x7, + UserEnvCall = 0x8, + MachineEnvCall = 0xb, +}; +pub const InterruptHandler = *const fn () callconv(riscv_calling_convention) void; +pub const InterruptOptions = microzig.utilities.GenerateInterruptOptions(&.{ + .{ .InterruptEnum = enum { Exception }, .HandlerFn = InterruptHandler }, + .{ .InterruptEnum = Interrupt, .HandlerFn = InterruptHandler }, +}); +const VectorTable = [vector_table_size()]InterruptHandler; + +pub const interrupt = struct { + pub inline fn globally_enabled() bool { + return csr.mstatus.read().mie == 1; + } + + pub inline fn enable_interrupts() void { + csr.mstatus.set(.{ .mie = 1 }); + } + + pub inline fn disable_interrupts() void { + csr.mstatus.clear(.{ .mie = 1 }); + } + + pub inline fn is_enabled(irq: Interrupt) bool { + const irq_num = @backingInt(irq); + const num = irq_num >> 5; + const pos = irq_num & 0x1F; + const v = switch (num) { + 0 => get_bit(PFIC.ISR1, pos), + 1 => get_bit(PFIC.ISR2, pos), + 2 => get_bit(PFIC.ISR3, pos), + 3 => get_bit(PFIC.ISR4, pos), + else => @compileError("Invalid interrupt number!"), + }; + return v != 0; + } + + pub inline fn enable(irq: Interrupt) void { + comptime { + const irq_name = @tagName(irq); + const app_has = @field(microzig.options.interrupts, irq_name) != null; + const hal_has = if (microzig.config.has_hal and @hasDecl(microzig.hal, "default_interrupts")) + @field(microzig.hal.default_interrupts, irq_name) != null + else + false; + if (!app_has and !hal_has) { + @compileError( + irq_name ++ " interrupt handler should be defined.\n" ++ + "Add to your main file:\n" ++ + " pub const microzig_options: microzig.Options = .{\n" ++ + " .interrupts = .{\n" ++ + " ." ++ irq_name ++ " = your_handler_for_" ++ irq_name ++ ",\n" ++ + " },\n" ++ + " };\n", + ); + } + } + + const irq_num = @backingInt(irq); + const num = irq_num >> 5; + const pos = irq_num & 0x1F; + switch (num) { + 0 => PFIC.IENR1.raw |= @as(u32, 1) << pos, + 1 => PFIC.IENR2.raw |= @as(u32, 1) << pos, + 2 => PFIC.IENR3.raw |= @as(u32, 1) << pos, + 3 => PFIC.IENR4.raw |= @as(u32, 1) << pos, + else => @compileError("Invalid interrupt number!"), + } + } + + pub inline fn disable(irq: Interrupt) void { + const irq_num = @backingInt(irq); + const num = irq_num >> 5; + const pos = irq_num & 0x1F; + switch (num) { + 0 => PFIC.IRER1.raw |= @as(u32, 1) << pos, + 1 => PFIC.IRER2.raw |= @as(u32, 1) << pos, + 2 => PFIC.IRER3.raw |= @as(u32, 1) << pos, + 3 => PFIC.IRER4.raw |= @as(u32, 1) << pos, + else => @compileError("Invalid interrupt number!"), + } + } + + pub inline fn is_pending(irq: Interrupt) bool { + const irq_num = @backingInt(irq); + const num = irq_num >> 5; + const pos = irq_num & 0x1F; + const v = switch (num) { + 0 => get_bit(PFIC.IPR1, pos), + 1 => get_bit(PFIC.IPR2, pos), + 2 => get_bit(PFIC.IPR3, pos), + 3 => get_bit(PFIC.IPR4, pos), + else => @compileError("Invalid interrupt number!"), + }; + return v != 0; + } + + pub inline fn set_pending(irq: Interrupt) void { + const irq_num = @backingInt(irq); + const num = irq_num >> 5; + const pos = irq_num & 0x1F; + switch (num) { + 0 => PFIC.IPSR1.raw |= @as(u32, 1) << pos, + 1 => PFIC.IPSR2.raw |= @as(u32, 1) << pos, + 2 => PFIC.IPSR3.raw |= @as(u32, 1) << pos, + 3 => PFIC.IPSR4.raw |= @as(u32, 1) << pos, + else => @compileError("Invalid interrupt number!"), + } + } + + pub inline fn clear_pending(irq: Interrupt) void { + const irq_num = @backingInt(irq); + const num = irq_num >> 5; + const pos = irq_num & 0x1F; + switch (num) { + 0 => PFIC.IPRR1.raw |= @as(u32, 1) << pos, + 1 => PFIC.IPRR2.raw |= @as(u32, 1) << pos, + 2 => PFIC.IPRR3.raw |= @as(u32, 1) << pos, + 3 => PFIC.IPRR4.raw |= @as(u32, 1) << pos, + else => @compileError("Invalid interrupt number!"), + } + } + + pub inline fn is_active(irq: Interrupt) void { + const irq_num = @backingInt(irq); + const num = irq_num >> 5; + const pos = irq_num & 0x1F; + const v = switch (num) { + 0 => get_bit(PFIC.IACTR1, pos), + 1 => get_bit(PFIC.IACTR2, pos), + 2 => get_bit(PFIC.IACTR3, pos), + 3 => get_bit(PFIC.IACTR4, pos), + else => @compileError("Invalid interrupt number!"), + }; + return v != 0; + } + + /// Interrupt priority configuration. + /// priority: + /// bit7 - pre-emption priority + /// bit6~bit4 - subpriority + /// bit3~bit0 - reserved (must be 0) + pub inline fn set_priority(comptime irq: Interrupt, priority: u8) void { + const irq_num = @backingInt(irq); + const irq_num_str = std.fmt.comptimePrint("{}", .{irq_num}); + @field(PFIC, "IPRIOR" ++ irq_num_str) = @backingInt(priority) & 0b1111_0000; + } + + pub inline fn get_priority(comptime irq: Interrupt) u8 { + const irq_num = @backingInt(irq); + const irq_num_str = std.fmt.comptimePrint("{}", .{irq_num}); + return @field(PFIC, "IPRIOR" ++ irq_num_str); + } + + inline fn get_bit(self: anytype, pos: u5) u1 { + return @truncate(self.raw >> pos); + } +}; + +pub inline fn wfi() void { + cpu_impl.wfi(microzig.chip); +} + +pub inline fn wfe() void { + cpu_impl.wfe(microzig.chip); +} + +pub fn unhandled() callconv(riscv_calling_convention) void { + const mcause = csr.mcause.read(); + + if (mcause.is_interrupt != 0) { + std.log.err("unhandled interrupt {} occurred!", .{mcause.code}); + } else { + std.log.err("exception 0x{x} occurred!", .{mcause.code}); + } + + @panic("unhandled interrupt"); +} + +// Startup + +pub const startup_logic = struct { + extern fn microzig_main() noreturn; + + pub fn _start() callconv(.naked) void { + asm volatile ( + \\ + // Set global pointer. + \\.option push + \\.option norelax + \\la gp, __global_pointer$ + \\.option pop + \\ + // Set stack pointer. + \\mv sp, %[eos] + + // Initialize the system. + \\j _system_init + : + : [eos] "r" (comptime microzig.utilities.get_end_of_stack()), + ); + } + + export fn _system_init() callconv(.c) noreturn { + // NOTE: this can only be called once. Otherwise, we get a linker error for duplicate symbols + startup_logic.initialize_system_memories(); + + // Configure the CPU. + switch (cpu_name) { + .qingkev3f, .qingkev5f => { + // Configure pipelining and instruction prediction. + csr.corecfgr.write_raw(0x1f); + // Enable interrupt nesting and hardware stack. + // TODO: V5F supports 8-level nesting, V3F 2-level; need to verify pmtcfg + // values against the CH32H417 reference manual. + csr.intsyscr.write(.{ .hwstken = 1, .inesten = 1, .pmtcfg = 0b10 }); + }, + } + + // Set mtvec.base to (vector_table_address - 4) >> 2 so that interrupt N + // jumps to the correct handler regardless of any padding between _reset_vector + // and vector_table. + const vtable_addr = @intFromPtr(&vector_table); + csr.mtvec.write(.{ + .mode0 = 1, // Interrupt entry for each interrupt + .mode1 = 1, // Use absolute addresses + .base = @intCast((vtable_addr - 4) >> 2), + }); + + // mstatus.mpp determines the privilege level restored by mret. + // Set to 0x3 (Machine) so mret returns to Machine mode, allowing the + // firmware to manage interrupts and change privilege as needed. + // To change execution to User mode set mpp to 0x0 and execute mret. + // Enable machine-level interrupts (mie) and set floating-point status (fs) if applicable. + csr.mstatus.write(.{ + .mie = 1, + .mpie = 1, + // Both V3F and V5F implement the F extension (RV32IMAFBC-X). + .fs = .dirty, + .mpp = 0x3, + }); + + cpu_impl.system_init(microzig.chip); + + // Load the address of the `microzig_main` function into the `mepc` register + // and transfer control to it using the `mret` instruction. + // This is necessary to ensure proper MCU startup after a power-off. + // Directly calling the function from an interrupt would prevent the MCU from starting correctly. + csr.mepc.write(@intFromPtr(µzig_main)); + + // Return from the interrupt. + // This changes the privilege level to mstatus.mpp, set above. In this case we are in + // machine mode and we are switching to machine mode, but normally this could switch us to + // user mode. + asm volatile ("mret"); + unreachable; + } + + inline fn initialize_system_memories() void { + // Clear .bss section. + asm volatile ( + \\ li a0, 0 + \\ la a1, microzig_bss_start + \\ la a2, microzig_bss_end + \\ beq a1, a2, clear_bss_done + \\clear_bss_loop: + \\ sw a0, 0(a1) + \\ addi a1, a1, 4 + \\ blt a1, a2, clear_bss_loop + \\clear_bss_done: + ::: .{ .x10 = true, .x11 = true, .x12 = true }); + + // Copy .data from FLASH to RAM. + asm volatile ( + \\ la a0, microzig_data_load_start + \\ la a1, microzig_data_start + \\ la a2, microzig_data_end + \\copy_data_loop: + \\ beq a1, a2, copy_done + \\ lw a3, 0(a0) + \\ sw a3, 0(a1) + \\ addi a0, a0, 4 + \\ addi a1, a1, 4 + \\ bne a1, a2, copy_data_loop + \\copy_done: + ::: .{ .x10 = true, .x11 = true, .x12 = true, .x13 = true }); + } + + export fn _reset_vector() linksection("microzig_flash_start") callconv(.naked) void { + asm volatile ("j _start"); + } +}; + +// Vector table + +const vector_table_offset = 1; // First entry is reserved for the _reset_vector. + +fn vector_table_size() usize { + const type_info = @typeInfo(Interrupt); + + const interrupts_list = type_info.@"enum".field_values; + const last_interrupt = interrupts_list[interrupts_list.len - 1]; + const last_interrupt_idx = last_interrupt; + + return last_interrupt_idx + 1 - vector_table_offset; +} + +pub fn generate_vector_table() VectorTable { + @setEvalBranchQuota(100_000); + var tmp: VectorTable = @splat(microzig.options.interrupts.Exception orelse unhandled); + + const type_info = @typeInfo(Interrupt); + const interrupt_names = type_info.@"enum".field_names; + const interrupt_values = type_info.@"enum".field_values; + + // Apply interrupts + for (&tmp, vector_table_offset..) |_, idx| { + // Find name of the interrupt by its number. + var name: ?[:0]const u8 = null; + for (interrupt_names, interrupt_values) |interrupt_name, interrupt_value| { + if (interrupt_value == idx) { + name = interrupt_name; + break; + } + } + + if (name) |n| { + const maybe_handler = @field(microzig.options.interrupts, n); + const maybe_default = get_hal_default_handler(n); + + tmp[idx - vector_table_offset] = blk: { + if (maybe_handler) |handler| { + if (!microzig.options.overwrite_hal_interrupts and maybe_default != null) + @compileError(std.fmt.comptimePrint( + \\Interrupt {s} is used internally by the HAL; overriding it may cause malfunction. + \\If you are sure of what you are doing, set "overwrite_hal_interrupts" to true in: "microzig_options". + \\ + , .{n})); + break :blk handler; + } else break :blk maybe_default orelse unhandled; + }; + } + } + + return tmp; +} + +fn get_hal_default_handler(comptime handler_name: []const u8) ?InterruptHandler { + if (microzig.config.has_hal) { + if (@hasDecl(microzig.hal, "default_interrupts")) { + return @field(microzig.hal.default_interrupts, handler_name); + } + } + return null; +} + +const vector_table: VectorTable = generate_vector_table(); + +pub fn export_startup_logic() void { + @export(&startup_logic._start, .{ .name = "_start" }); + @export(&vector_table, .{ + .name = "vector_table", + .section = "microzig_flash_start", + }); +} + +// CSR + +pub const csr = struct { + pub const Csr = riscv32_common.csr.Csr; + + /// Architecture Number Register + /// Fields correspond to individual letters. 1=A, 2=B, etc. + /// Examples: + /// - 0xDC68D841 - WCH-V2A + /// - 0xDC68D886 - WCH-V4F + pub const marchid = Csr(0xF12, packed struct(u32) { + version: u4 = 0, + serial: u5 = 0, + arch: u5 = 0, + reserved15: u1 = 0, + vendor2: u5 = 0, // 'H' + vendor1: u5 = 0, // 'C' + vendor0: u5 = 0, // 'W' + reserved: u1 = 0, + }); + pub const mimpid = Csr(0xF13, packed struct(u32) { + reserved0: u16 = 0, + vendor2: u5 = 0, // 'H' + vendor1: u5 = 0, // 'C' + vendor0: u5 = 0, // 'W' + reserved31: u1 = 0, + }); + + /// Machine Mode Status Register + pub const mstatus = Csr(0x300, packed struct(u32) { + pub const FS = enum(u2) { + /// Floating-point unit status + off = 0b00, + initial = 0b01, + clean = 0b10, + dirty = 0b11, + }; + + /// [2:0] Reserved + reserved0: u3 = 0, + /// [3] Machine mode interrupt enable + mie: u1 = 0, + /// [6:4] Reserved + reserved4: u3 = 0, + /// [7] Interrupt enable state before entering interrupt + mpie: u1 = 0, + /// [10:8] Reserved + reserved8: u3 = 0, + /// [12:11] Privileged mode before entering break + mpp: u2 = 0, + /// [14:13] Floating-point unit status + /// Valid only for WCH-V4F + /// NOTE: reserved on other chips + fs: FS = .off, + /// [31:15] Reserved + reserved15: u17 = 0, + }); + pub const misa = Csr(0x301, packed struct(u32) { + extensions: u26 = 0, + reserved26: u4 = 0, + // Machine work length. 1 => 32 bit + mxl: u2 = 1, + }); + /// Machine Mode Exception Base Address Register + pub const mtvec = Csr(0x305, packed struct(u32) { + /// [0] Mode 0 + /// Interrupt or exception entry address mode selection. + /// 0: Use of the uniform entry address. + /// 1: Address offset based on interrupt number *4. + mode0: u1 = 0, + /// [1] Mode 1 + /// Interrupt vector table identifies patterns. + /// 0: Identification by jump instruction, + /// limited range, support for non-jump 0 instructions. + /// 1: Identify by absolute address, support + /// full range, but must jump. + mode1: u1 = 0, + /// [31:2] Base address of the interrupt vector table + base: u30 = 0, + }); + + pub const mscratch = riscv32_common.csr.mscratch; + // PC where to `mret` returns to after an interrupt or exception handler runs. + // - For interrupts, it's set to the next unexecuted instruction. + // - For exceptions, it's set to the instruction that was executing when the exception occured. + // That means that `mepc` might need to be modified if we want to 'recover' from an exception. + pub const mepc = riscv32_common.csr.mepc; + // Cause of the interrupt/exception. + pub const mcause = riscv32_common.csr.mcause; + // 'Value' of an exception, e.g. the address of where a memory access exception occurred. + pub const mtval = riscv32_common.csr.mtval; + + // Physical memory protection + pub const pmpcfg0 = riscv32_common.csr.pmpcfg0; + pub const pmpaddr0 = riscv32_common.csr.pmpaddr0; + pub const pmpaddr1 = riscv32_common.csr.pmpaddr1; + pub const pmpaddr2 = riscv32_common.csr.pmpaddr2; + pub const pmpaddr3 = riscv32_common.csr.pmpaddr3; + + // Hardware floating point registers + // NOTE: QingKeV4F only + pub const fflags = riscv32_common.csr.fflags; + pub const frm = riscv32_common.csr.frm; + pub const fcsr = Csr(0x003, packed struct(u32) { + nx: u1 = 0, + uf: u1 = 0, + of: u1 = 0, + dz: u1 = 0, + nv: u1 = 0, + frm: u3 = 0, + reserved8: u24 = 0, + }); + + // Debug registers + pub const dcsr = riscv32_common.csr.dcsr; + pub const dpc = riscv32_common.csr.dpc; + pub const dscratch0 = riscv32_common.csr.dscratch0; + pub const dscratch1 = riscv32_common.csr.dscratch1; + + pub const gintenr = Csr(0x800, u32); + pub const intsyscr = Csr(0x804, cpu_impl.csr_types.intsyscr); + pub const corecfgr = Csr(0xBC0, u32); + pub const cstrcr = Csr(0xBC2, packed struct(u32) { + reserved0: u1 = 0, + icddisable: u1 = 0, + reserved2: u22 = 0, + iccodestren: u1 = 0, + icsramstren: u1 = 0, + reserved26: u6 = 0, + }); + pub const cpmpocr = Csr(0xBC3, u32); + pub const cmcr = Csr(0xBD0, packed struct(u32) { + opcode: u2 = 0, + idxmode: u1 = 0, + reserved3: u2 = 0, + vaddr: u27 = 0, + }); + pub const cinfor = Csr(0xFC0, packed struct(u32) { + iclinesize: u2 = 0, + icszie: u3 = 0, + icway: u2 = 0, + reserved7: u25 = 0, + }); +}; diff --git a/port/wch/ch32h/src/cpus/qingkev3f.zig b/port/wch/ch32h/src/cpus/qingkev3f.zig new file mode 100644 index 000000000..c65b27dc2 --- /dev/null +++ b/port/wch/ch32h/src/cpus/qingkev3f.zig @@ -0,0 +1,179 @@ +/// +/// Processor-specific configuration for WCH QingKe V3F processor (CH32H417 CORE0). +/// Interrupt vector table extracted from openwch/ch32h417 EVT startup_ch32h417_v3f.S. +/// +pub const cpu_frequency = 150_000_000; // 150 MHz + +pub const Interrupt = enum(u8) { + NMI = 2, + HardFault = 3, + Ecall_M_Mode = 5, + Ecall_U_Mode = 8, + Break_Point = 9, + SysTick0 = 12, + SysTick1 = 13, + SW = 14, + IPC_CH0 = 16, + IPC_CH1 = 17, + IPC_CH2 = 18, + IPC_CH3 = 19, + HSEM = 28, + WWDG = 32, + EXTI15_8 = 33, + FLASH = 34, + RCC = 35, + EXTI7_0 = 36, + SPI1 = 37, + DMA1_Channel2 = 38, + DMA1_Channel3 = 39, + DMA1_Channel4 = 40, + DMA1_Channel5 = 41, + DMA1_Channel6 = 42, + DMA1_Channel7 = 43, + DMA1_Channel8 = 44, + USART2 = 45, + I2C1_EV = 46, + I2C1_ER = 47, + USART1 = 48, + SPI2 = 49, + SPI3 = 50, + SPI4 = 51, + I2C2_EV = 52, + I2C2_ER = 53, + USBPD = 54, + USBPDWakeUp = 55, + USBHS = 56, + DMA1_Channel1 = 57, + CAN1_SCE = 58, + CAN1_TX = 59, + CAN1_RX0 = 60, + CAN1_RX1 = 61, + USBSS = 62, + USBSS_LINK = 63, + USBHSWakeup = 64, + USBSSWakeup = 65, + RTCAlarm = 66, + USBFS = 67, + USBFSWakeup = 68, + ADC1_2 = 69, + TIM1_BRK = 70, + TIM1_UP = 71, + TIM1_TRG_COM = 72, + TIM1_CC = 73, + TIM2 = 74, + TIM3 = 75, + TIM4 = 76, + TIM5 = 77, + I2C3_EV = 78, + I2C3_ER = 79, + I2C4_EV = 80, + I2C4_ER = 81, + QSPI1 = 82, + SERDES = 83, + USART3 = 84, + USART4 = 85, + TIM8_BRK = 86, + TIM8_UP = 87, + TIM8_TRG_COM = 88, + TIM8_CC = 89, + TIM9 = 90, + TIM10 = 91, + TIM11 = 92, + TIM12 = 93, + FMC = 94, + SDMMC = 95, + LPTIM1 = 96, + LPTIM2 = 97, + USART5 = 98, + USART6 = 99, + TIM6 = 100, + TIM7 = 101, + DMA2_Channel1 = 102, + DMA2_Channel2 = 103, + DMA2_Channel3 = 104, + DMA2_Channel4 = 105, + DMA2_Channel5 = 106, + DMA2_Channel6 = 107, + DMA2_Channel7 = 108, + DMA2_Channel8 = 109, + ETH = 110, + ETH_WKUP = 111, + CAN2_SCE = 112, + CAN2_TX = 113, + CAN2_RX0 = 114, + CAN2_RX1 = 115, + USART7 = 116, + USART8 = 117, + I3C_EV = 118, + I3C_ER = 119, + DVP = 120, + ECDC = 121, + PIOC = 122, + SAI = 123, + LTDC = 124, + GPHA = 125, + DFSDM0 = 127, + DFSDM1 = 128, + SWPMI = 131, + QSPI2 = 134, + SWPMI_WKUP = 135, + CAN3_SCE = 136, + CAN3_TX = 137, + CAN3_RX0 = 138, + CAN3_RX1 = 139, + LPTIM2_WKUP = 140, + LPTIM1_WKUP = 141, + I3C_WKUP = 142, + RTC = 143, + HSADC = 144, + UHSIF = 145, + RNG = 146, + SDIO = 147, + USART_WKUP = 148, +}; + +/// System initialization. The stock EVT startup code configures the PLL here +/// (RCC @ 0x40021000); the chip boots from the internal 25 MHz HSI, so this is +/// left as a no-op for now. TODO: port the PLL bring-up from the EVT. +pub inline fn system_init(comptime chip: anytype) void { + _ = chip; +} + +/// Wait for interrupt. Clears WFITOWFE so the wfi instruction behaves as +/// a true wait-for-interrupt. +pub inline fn wfi(comptime chip: anytype) void { + const PFIC = chip.peripherals.PFIC; + PFIC.SCTLR.modify(.{ .WFITOWFE = 0 }); + asm volatile ("wfi"); +} + +/// Wait for event. Sets SETEVENT to clear any stale event latch, enables +/// WFITOWFE so the wfi instruction acts as wfe, then executes wfi twice: +/// the first clears the just-set event, the second sleeps until a real event. +pub inline fn wfe(comptime chip: anytype) void { + const PFIC = chip.peripherals.PFIC; + PFIC.SCTLR.modify(.{ .SETEVENT = 1, .WFITOWFE = 1 }); + asm volatile ("wfi"); + asm volatile ("wfi"); +} + +pub const csr_types = struct { + pub const intsyscr = packed struct(u32) { + /// [0] Hardware Prologue/Epilogue (HPE) enable + hwstken: u1, + /// [1] Interrupt nesting enable + inesten: u1, + /// [3:2] Interrupt nesting depth configuration + pmtcfg: u2, + /// [4] Interrupt enable after HPE overflow + hwstkoven: u1 = 0, + /// [5] Global interrupt and HPE off enable + gihwstknen: u1 = 0, + /// [7:6] Reserved + reserved1: u2 = 0, + /// [15:8] Preemption status indication + pmtsta: u8 = 0, + /// [31:16] Reserved + reserved0: u16 = 0, + }; +}; diff --git a/port/wch/ch32h/src/cpus/qingkev5f.zig b/port/wch/ch32h/src/cpus/qingkev5f.zig new file mode 100644 index 000000000..73f3b0efc --- /dev/null +++ b/port/wch/ch32h/src/cpus/qingkev5f.zig @@ -0,0 +1,181 @@ +/// +/// Processor-specific configuration for WCH QingKe V5F processor (CH32H417 CORE1). +/// Interrupt vector table extracted from openwch/ch32h417 EVT startup_ch32h417_v5f.S. +/// +pub const cpu_frequency = 400_000_000; // 400 MHz + +pub const Interrupt = enum(u8) { + NMI = 2, + HardFault = 3, + Ecall_M_Mode = 5, + Ecall_U_Mode = 8, + Break_Point = 9, + SysTick0 = 12, + SysTick1 = 13, + SW = 14, + IPC_CH0 = 16, + IPC_CH1 = 17, + IPC_CH2 = 18, + IPC_CH3 = 19, + HSEM = 28, + WWDG = 32, + EXTI15_8 = 33, + FLASH = 34, + RCC = 35, + EXTI7_0 = 36, + SPI1 = 37, + DMA1_Channel2 = 38, + DMA1_Channel3 = 39, + DMA1_Channel4 = 40, + DMA1_Channel5 = 41, + DMA1_Channel6 = 42, + DMA1_Channel7 = 43, + DMA1_Channel8 = 44, + USART2 = 45, + I2C1_EV = 46, + I2C1_ER = 47, + USART1 = 48, + SPI2 = 49, + SPI3 = 50, + SPI4 = 51, + I2C2_EV = 52, + I2C2_ER = 53, + USBPD = 54, + USBPDWakeUp = 55, + USBHS = 56, + DMA1_Channel1 = 57, + CAN1_SCE = 58, + CAN1_TX = 59, + CAN1_RX0 = 60, + CAN1_RX1 = 61, + USBSS = 62, + USBSS_LINK = 63, + USBHSWakeup = 64, + USBSSWakeup = 65, + RTCAlarm = 66, + USBFS = 67, + USBFSWakeup = 68, + ADC1_2 = 69, + TIM1_BRK = 70, + TIM1_UP = 71, + TIM1_TRG_COM = 72, + TIM1_CC = 73, + TIM2 = 74, + TIM3 = 75, + TIM4 = 76, + TIM5 = 77, + I2C3_EV = 78, + I2C3_ER = 79, + I2C4_EV = 80, + I2C4_ER = 81, + QSPI1 = 82, + SERDES = 83, + USART3 = 84, + USART4 = 85, + TIM8_BRK = 86, + TIM8_UP = 87, + TIM8_TRG_COM = 88, + TIM8_CC = 89, + TIM9 = 90, + TIM10 = 91, + TIM11 = 92, + TIM12 = 93, + FMC = 94, + SDMMC = 95, + LPTIM1 = 96, + LPTIM2 = 97, + USART5 = 98, + USART6 = 99, + TIM6 = 100, + TIM7 = 101, + DMA2_Channel1 = 102, + DMA2_Channel2 = 103, + DMA2_Channel3 = 104, + DMA2_Channel4 = 105, + DMA2_Channel5 = 106, + DMA2_Channel6 = 107, + DMA2_Channel7 = 108, + DMA2_Channel8 = 109, + ETH = 110, + ETH_WKUP = 111, + CAN2_SCE = 112, + CAN2_TX = 113, + CAN2_RX0 = 114, + CAN2_RX1 = 115, + USART7 = 116, + USART8 = 117, + I3C_EV = 118, + I3C_ER = 119, + DVP = 120, + ECDC = 121, + PIOC = 122, + SAI = 123, + LTDC = 124, + GPHA = 125, + DFSDM0 = 127, + DFSDM1 = 128, + SWPMI = 131, + QSPI2 = 134, + SWPMI_WKUP = 135, + CAN3_SCE = 136, + CAN3_TX = 137, + CAN3_RX0 = 138, + CAN3_RX1 = 139, + LPTIM2_WKUP = 140, + LPTIM1_WKUP = 141, + I3C_WKUP = 142, + RTC = 143, + HSADC = 144, + UHSIF = 145, + RNG = 146, + SDIO = 147, + USART_WKUP = 148, +}; + +/// System initialization. The stock EVT startup code configures the PLL here +/// (RCC @ 0x40021000); the chip boots from the internal 25 MHz HSI, so this is +/// left as a no-op for now. TODO: port the PLL bring-up from the EVT. +pub inline fn system_init(comptime chip: anytype) void { + _ = chip; +} + +/// Wait for interrupt. Clears WFITOWFE so the wfi instruction behaves as +/// a true wait-for-interrupt. +pub inline fn wfi(comptime chip: anytype) void { + const PFIC = chip.peripherals.PFIC; + PFIC.SCTLR.modify(.{ .WFITOWFE = 0 }); + asm volatile ("wfi"); +} + +/// Wait for event. Sets SETEVENT to clear any stale event latch, enables +/// WFITOWFE so the wfi instruction acts as wfe, then executes wfi twice: +/// the first clears the just-set event, the second sleeps until a real event. +pub inline fn wfe(comptime chip: anytype) void { + const PFIC = chip.peripherals.PFIC; + PFIC.SCTLR.modify(.{ .SETEVENT = 1, .WFITOWFE = 1 }); + asm volatile ("wfi"); + asm volatile ("wfi"); +} + +pub const csr_types = struct { + pub const intsyscr = packed struct(u32) { + /// [0] Hardware Prologue/Epilogue (HPE) enable + /// NOTE: Probably not supported by the Zig compiler. Would require + /// __attribute__((interrupt("WCH-Interrupt-fast"))). + hwstken: u1, + /// [1] Interrupt nesting enable + inesten: u1, + /// [3:2] Interrupt nesting depth configuration + pmtcfg: u2, + /// [4] Interrupt enable after HPE overflow + hwstkoven: u1 = 0, + /// [5] Global interrupt and HPE off enable + gihwstknen: u1 = 0, + /// [7:6] Reserved + reserved1: u2 = 0, + /// [15:8] Preemption status indication + pmtsta: u8 = 0, + /// [31:16] Reserved + reserved0: u16 = 0, + }; +}; diff --git a/port/wch/ch32h/src/hals/ch32h417.zig b/port/wch/ch32h/src/hals/ch32h417.zig new file mode 100644 index 000000000..874dca319 --- /dev/null +++ b/port/wch/ch32h/src/hals/ch32h417.zig @@ -0,0 +1,17 @@ +const microzig = @import("microzig"); + +pub const peripherals = microzig.chip.peripherals; + +pub const drivers = struct {}; + +pub fn init() void {} + +pub const gpio = struct { + pub inline fn write(port: anytype, pin: u4, level: u1) void { + if (level == 1) { + port.BSHR.raw = @as(u32, 1) << pin; + } else { + port.BCR.raw = @as(u32, 1) << pin; + } + } +}; diff --git a/port/wch/ch32h/tools/merge_dual_core_image.zig b/port/wch/ch32h/tools/merge_dual_core_image.zig new file mode 100644 index 000000000..5b109eb1a --- /dev/null +++ b/port/wch/ch32h/tools/merge_dual_core_image.zig @@ -0,0 +1,108 @@ +//! merge_dual_core_image - merges the V3F and V5F firmwares of the CH32H417 +//! into one flash image. +//! +//! Usage: merge_dual_core_image +//! +//! For each ELF, all PT_LOAD segments whose physical (load) address lies in +//! the CodeFlash window (0x0000_0000 .. 0x0010_0000) are extracted and placed +//! at their absolute flash address (V3F is linked at 0x0, V5F at ). +//! Any gap is padded with 0xFF and overlapping segments are rejected. +//! +//! Reading the ELFs directly (instead of objcopy'd flat binaries) sidesteps +//! the LLVM objcopy NOLOAD-segment issue, which otherwise inflates binaries +//! by the flash-to-RAM address gap (~512 MB). + +const std = @import("std"); + +/// CodeFlash of the CH32H417 (960 KB at 0x0000_0000). +const flash_base: u64 = 0x0000_0000; +const flash_size: u64 = 960 * 1024; + +const Segment = struct { + paddr: u64, + data: []const u8, +}; + +fn extract_flash_segments(allocator: std.mem.Allocator, elf_data: []const u8) ![]Segment { + var reader: std.Io.Reader = .fixed(elf_data); + const elf_header = try std.elf.Header.read(&reader); + if (elf_header.machine != .RISCV) return error.NotARiscvElf; + + var segments: std.ArrayList(Segment) = .empty; + var it = elf_header.iterateProgramHeadersBuffer(elf_data); + while (try it.next()) |phdr| { + if (phdr.type != .LOAD) continue; + if (phdr.filesz == 0) continue; + if (phdr.paddr < flash_base or phdr.paddr + phdr.filesz > flash_base + flash_size) continue; + try segments.append(allocator, .{ + .paddr = phdr.paddr, + .data = elf_data[@intCast(phdr.offset)..][0..@intCast(phdr.filesz)], + }); + } + if (segments.items.len == 0) return error.NoFlashSegments; + return segments.items; +} + +/// Writes all segments of one core into the image buffer at +/// `(paddr - flash_base) + image_offset`, extending the buffer as needed. +fn place_segments( + allocator: std.mem.Allocator, + image: *std.ArrayList(u8), + segments: []const Segment, + image_offset: u64, +) !void { + for (segments) |seg| { + const start = (seg.paddr - flash_base) + image_offset; + const end = start + seg.data.len; + if (end > image.items.len) { + const old_len = image.items.len; + try image.resize(allocator, @intCast(end)); + @memset(image.items[old_len..], 0xFF); // erased flash pattern + } + // Overlaps would indicate a broken memory layout; refuse to silently + // produce a corrupt image. + for (image.items[@intCast(start)..@intCast(end)]) |byte| { + if (byte != 0xFF) return error.OverlappingSegments; + } + @memcpy(image.items[@intCast(start)..@intCast(end)], seg.data); + } +} + +pub fn main(init: std.process.Init) !void { + const io = init.io; + const allocator = init.arena.allocator(); + const args = try init.minimal.args.toSlice(allocator); + + if (args.len != 5) { + std.log.err("usage: {s} ", .{args[0]}); + return error.InvalidArguments; + } + + const v3f_elf = try std.Io.Dir.cwd().readFileAlloc(io, args[1], allocator, .limited(64 * 1024 * 1024)); + const v5f_elf = try std.Io.Dir.cwd().readFileAlloc(io, args[2], allocator, .limited(64 * 1024 * 1024)); + const v5f_offset = try std.fmt.parseInt(u64, args[3], 0); + + const v3f_segments = try extract_flash_segments(allocator, v3f_elf); + const v5f_segments = try extract_flash_segments(allocator, v5f_elf); + + // Sanity check. + for (v5f_segments) |seg| { + if (seg.paddr - flash_base < v5f_offset) { + std.log.err( + "v5f segment at flash offset 0x{x} lies before the expected v5f image offset 0x{x}", + .{ seg.paddr - flash_base, v5f_offset }, + ); + return error.UnexpectedV5fOffset; + } + } + + var image: std.ArrayList(u8) = .empty; + try place_segments(allocator, &image, v3f_segments, 0); + try place_segments(allocator, &image, v5f_segments, 0); + + std.log.info("merged image: {d} bytes ({d} v3f segments at 0x0, {d} v5f segments at 0x{x})", .{ + image.items.len, v3f_segments.len, v5f_segments.len, v5f_offset, + }); + + try std.Io.Dir.cwd().writeFile(io, .{ .sub_path = args[4], .data = image.items }); +} From 697ecfab1b82d5bfec0da760b2ae9f0fcbd6737e Mon Sep 17 00:00:00 2001 From: So1aric Date: Sun, 6 Sep 2026 23:10:44 +0800 Subject: [PATCH 2/2] wch(ch32h): add dual-core example for CH32H417. --- examples/wch/ch32h/build.zig | 4 ---- examples/wch/ch32h/src/v3f.zig | 11 +++++++---- examples/wch/ch32h/src/v5f.zig | 18 ++++++++---------- port/wch/ch32h/build.zig | 6 ++---- port/wch/ch32h/src/cpus/qingkev3f.zig | 5 ++--- port/wch/ch32h/src/cpus/qingkev5f.zig | 5 ++--- port/wch/ch32h/tools/merge_dual_core_image.zig | 17 ++++------------- 7 files changed, 25 insertions(+), 41 deletions(-) diff --git a/examples/wch/ch32h/build.zig b/examples/wch/ch32h/build.zig index e0b550f45..0b5b28395 100644 --- a/examples/wch/ch32h/build.zig +++ b/examples/wch/ch32h/build.zig @@ -19,8 +19,4 @@ pub fn build(b: *std.Build) void { }); mb.ports.ch32h.installFirmware(mb, fw); - - // // Also install the individual per-core ELFs for debugging. - // mb.install_firmware(fw.v3f, .{ .format = .elf }); - // mb.install_firmware(fw.v5f, .{ .format = .elf }); } diff --git a/examples/wch/ch32h/src/v3f.zig b/examples/wch/ch32h/src/v3f.zig index 621631a2b..ebbe70d39 100644 --- a/examples/wch/ch32h/src/v3f.zig +++ b/examples/wch/ch32h/src/v3f.zig @@ -1,4 +1,5 @@ const microzig = @import("microzig"); +const std = @import("std"); pub const panic = microzig.panic; @@ -9,6 +10,7 @@ comptime { } const RCC = microzig.chip.peripherals.RCC; +const PFIC = microzig.chip.peripherals.PFIC; const GPIOC = microzig.chip.peripherals.GPIOC; const pin: u4 = 2; @@ -20,16 +22,17 @@ fn delay(cycles: u32) void { } pub fn main() !void { - // Enable the GPIOA peripheral clock (IOPAEN = RCC_HB2PCENR bit 2). RCC.HB2PCENR.modify(.{ .IOPCEN = 1 }); - // PC2: general purpose open-drain output, 50 MHz. GPIOC.CFGLR.modify(.{ .MODE2 = 0b11, .CNF2 = 0b01 }); + PFIC.WAKEIP1.raw = 0x10000 & ~@as(u32, 0x3FF); + PFIC.SCTLR.raw |= (1 << 5); + while (true) { microzig.hal.gpio.write(GPIOC, pin, 1); - delay(100_000); + delay(10_000); microzig.hal.gpio.write(GPIOC, pin, 0); - delay(100_000); + delay(10_000); } } diff --git a/examples/wch/ch32h/src/v5f.zig b/examples/wch/ch32h/src/v5f.zig index e906e4463..92defdc18 100644 --- a/examples/wch/ch32h/src/v5f.zig +++ b/examples/wch/ch32h/src/v5f.zig @@ -9,9 +9,9 @@ comptime { } const RCC = microzig.chip.peripherals.RCC; -const GPIOA = microzig.chip.peripherals.GPIOA; +const GPIOC = microzig.chip.peripherals.GPIOC; -const pin: u4 = 1; +const pin: u4 = 3; fn delay(cycles: u32) void { for (0..cycles) |_| { @@ -20,16 +20,14 @@ fn delay(cycles: u32) void { } pub fn main() !void { - // Enable the GPIOA peripheral clock (IOPAEN = RCC_HB2PCENR bit 2). - RCC.HB2PCENR.modify(.{ .IOPAEN = 1 }); + RCC.HB2PCENR.modify(.{ .IOPCEN = 1 }); - // PA1: general purpose push-pull output, 50 MHz (MODE=0b11, CNF=0b00). - GPIOA.CFGLR.modify(.{ .MODE1 = 0b11, .CNF1 = 0b00 }); + GPIOC.CFGLR.modify(.{ .MODE3 = 0b11, .CNF3 = 0b01 }); while (true) { - microzig.hal.gpio.write(GPIOA, pin, 1); - delay(250_000); - microzig.hal.gpio.write(GPIOA, pin, 0); - delay(250_000); + microzig.hal.gpio.write(GPIOC, pin, 1); + delay(20_000); + microzig.hal.gpio.write(GPIOC, pin, 0); + delay(20_000); } } diff --git a/port/wch/ch32h/build.zig b/port/wch/ch32h/build.zig index 68845d474..5d6e7736f 100644 --- a/port/wch/ch32h/build.zig +++ b/port/wch/ch32h/build.zig @@ -73,8 +73,6 @@ const cpu_common_features = std.Target.riscv.featureSet(&.{ }); pub fn init(dep: *std.Build.Dependency) ?Self { - // const b = dep.builder; - const chip_v3f = create_core(dep, "qingkev3f", dep.path("src/cpus/qingkev3f.zig"), &.{ .{ .name = "FLASH", .tag = .flash, .offset = 0x0000_0000, .length = default_v5f_image_offset, .access = .rx }, .{ .name = "SRAM", .tag = .ram, .offset = 0x2010_0000, .length = 512 * KiB, .access = .rwx }, @@ -130,7 +128,7 @@ pub fn DualCoreFirmware(comptime mb_type: type) type { } /// Builds the V3F and V5F applications as two independent firmwares and merges -/// both flat binaries into one flash image, gap padded with 0xFF. +/// both ELF images into one flash image, gap padded with 0xFF. pub fn addDualCoreFirmware( self: Self, mb: anytype, @@ -152,7 +150,7 @@ pub fn addDualCoreFirmware( .optimize = options.optimize, }); - // Host tool that concatenates the two flat binaries at the given offset. + // Host tool that merges the per-core ELF images into one flash image. const merge_exe = b.addExecutable(.{ .name = "merge_dual_core_image", .root_module = b.createModule(.{ diff --git a/port/wch/ch32h/src/cpus/qingkev3f.zig b/port/wch/ch32h/src/cpus/qingkev3f.zig index c65b27dc2..413532a1b 100644 --- a/port/wch/ch32h/src/cpus/qingkev3f.zig +++ b/port/wch/ch32h/src/cpus/qingkev3f.zig @@ -132,9 +132,8 @@ pub const Interrupt = enum(u8) { USART_WKUP = 148, }; -/// System initialization. The stock EVT startup code configures the PLL here -/// (RCC @ 0x40021000); the chip boots from the internal 25 MHz HSI, so this is -/// left as a no-op for now. TODO: port the PLL bring-up from the EVT. +/// System initialization: no-op for now (both cores boot from the 25 MHz HSI). +// TODO: port the PLL/clock bring-up from the EVT startup code. pub inline fn system_init(comptime chip: anytype) void { _ = chip; } diff --git a/port/wch/ch32h/src/cpus/qingkev5f.zig b/port/wch/ch32h/src/cpus/qingkev5f.zig index 73f3b0efc..e40e13906 100644 --- a/port/wch/ch32h/src/cpus/qingkev5f.zig +++ b/port/wch/ch32h/src/cpus/qingkev5f.zig @@ -132,9 +132,8 @@ pub const Interrupt = enum(u8) { USART_WKUP = 148, }; -/// System initialization. The stock EVT startup code configures the PLL here -/// (RCC @ 0x40021000); the chip boots from the internal 25 MHz HSI, so this is -/// left as a no-op for now. TODO: port the PLL bring-up from the EVT. +/// System initialization: no-op for now (both cores boot from the 25 MHz HSI). +// TODO: port the PLL/clock bring-up from the EVT startup code. pub inline fn system_init(comptime chip: anytype) void { _ = chip; } diff --git a/port/wch/ch32h/tools/merge_dual_core_image.zig b/port/wch/ch32h/tools/merge_dual_core_image.zig index 5b109eb1a..5f1135316 100644 --- a/port/wch/ch32h/tools/merge_dual_core_image.zig +++ b/port/wch/ch32h/tools/merge_dual_core_image.zig @@ -1,16 +1,8 @@ -//! merge_dual_core_image - merges the V3F and V5F firmwares of the CH32H417 -//! into one flash image. +//! merge_dual_core_image - merge the CH32H417 V3F and V5F firmware ELFs into +//! one flash image. PT_LOAD segments inside the CodeFlash window are placed at +//! their load address (V3F @ 0x0, V5F @ ), gaps 0xFF-padded. //! //! Usage: merge_dual_core_image -//! -//! For each ELF, all PT_LOAD segments whose physical (load) address lies in -//! the CodeFlash window (0x0000_0000 .. 0x0010_0000) are extracted and placed -//! at their absolute flash address (V3F is linked at 0x0, V5F at ). -//! Any gap is padded with 0xFF and overlapping segments are rejected. -//! -//! Reading the ELFs directly (instead of objcopy'd flat binaries) sidesteps -//! the LLVM objcopy NOLOAD-segment issue, which otherwise inflates binaries -//! by the flash-to-RAM address gap (~512 MB). const std = @import("std"); @@ -59,8 +51,7 @@ fn place_segments( try image.resize(allocator, @intCast(end)); @memset(image.items[old_len..], 0xFF); // erased flash pattern } - // Overlaps would indicate a broken memory layout; refuse to silently - // produce a corrupt image. + // Reject overlaps: they indicate a broken memory layout. for (image.items[@intCast(start)..@intCast(end)]) |byte| { if (byte != 0xFF) return error.OverlappingSegments; }