From 009865138af9c83c679b5a6354a70864e5aeef4e Mon Sep 17 00:00:00 2001
From: Jaehyun Kim <jhkim@precisioninno.com>
Date: Wed, 16 Sep 2026 10:02:28 +0900
Subject: [PATCH] flow: Add public benchmark designs

Add six public benchmark designs, three RTL sources each implemented on
asap7 and nangate45:

- xiangshan_coupledl2: the CoupledL2 subsystem of OpenXiangShan
  (MinimalConfig, one core) generated with Chisel 7.3.0 / firtool 1.135.0,
  with the SRAM arrays as bsg_fakeram macros.
- picorv32: the LogikBench PicoRV32 benchmark.
- tpu: the LogikBench TPU benchmark at its N=8 default.

Each design directory carries a self-contained config.mk, constraint.sdc
and rules-base.json, plus the fakeram.cfg that records how its SRAM views
were generated. The SRAM macro views themselves are shared platform
collateral under platforms/<pdk>/{lef,lib,verilog}/, following the existing
fakeram convention. Each source directory carries the RTL, a SOURCE.md that
records the upstream repositories, commits and local transformations, and
the upstream license texts under LICENSES/.

All design-specific settings are plain variables in the design config.mk
files; no flow hook, dont-use override, ORFS flow script or platform file
is used or modified. asap7 xiangshan_coupledl2 sets SKIP_DETAILED_ROUTE=1
because FlexDR reports DRT-0206 on this design, so its Final report uses
global-route parasitics. nangate45 xiangshan_coupledl2 sets
OPT_POST_GRT_WNS=1 because the nangate45 platform default of 0 wraps
recover_power in an incremental global_route pair that does not receive
-allow_congestion and fails with GRT-0116 on this congested design. The
new designs are listed in the commented DESIGN_CONFIG examples of
flow/Makefile.

All six SDCs use set_max_fanout 16. A full-flow comparison against
set_max_fanout 32 and no fanout constraint kept 16 as the best overall
setup WNS/TNS.

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
---
 flow/Makefile                                 |     6 +
 flow/designs/asap7/picorv32/config.mk         |    21 +
 flow/designs/asap7/picorv32/constraint.sdc    |    10 +
 flow/designs/asap7/picorv32/rules-base.json   |   112 +
 flow/designs/asap7/tpu/config.mk              |    21 +
 flow/designs/asap7/tpu/constraint.sdc         |    10 +
 flow/designs/asap7/tpu/rules-base.json        |   112 +
 .../asap7/xiangshan_coupledl2/config.mk       |    63 +
 .../asap7/xiangshan_coupledl2/constraint.sdc  |    15 +
 .../asap7/xiangshan_coupledl2/fakeram.cfg     |    26 +
 .../asap7/xiangshan_coupledl2/rules-base.json |    44 +
 flow/designs/nangate45/picorv32/config.mk     |    18 +
 .../designs/nangate45/picorv32/constraint.sdc |    10 +
 .../nangate45/picorv32/rules-base.json        |   112 +
 flow/designs/nangate45/tpu/config.mk          |    17 +
 flow/designs/nangate45/tpu/constraint.sdc     |    10 +
 flow/designs/nangate45/tpu/rules-base.json    |   112 +
 .../nangate45/xiangshan_coupledl2/config.mk   |    68 +
 .../xiangshan_coupledl2/constraint.sdc        |    15 +
 .../nangate45/xiangshan_coupledl2/fakeram.cfg |    22 +
 .../xiangshan_coupledl2/rules-base.json       |    60 +
 .../src/picorv32/LICENSES/LogikBench-MIT.txt  |    21 +
 .../src/picorv32/LICENSES/PicoRV32-ISC.txt    |    13 +
 flow/designs/src/picorv32/SOURCE.md           |    16 +
 flow/designs/src/picorv32/picorv32.sv         |  3049 ++++
 .../src/tpu/LICENSES/LogikBench-MIT.txt       |    21 +
 flow/designs/src/tpu/SOURCE.md                |    11 +
 flow/designs/src/tpu/tpu.sv                   |   140 +
 flow/designs/src/tpu/tpu_array.sv             |    76 +
 flow/designs/src/tpu/tpu_pe.sv                |    66 +
 .../src/xiangshan_coupledl2/CoupledL2.sv      |  2265 +++
 .../LICENSES/Chisel-Apache-2.0.txt            |   183 +
 .../OpenXiangShan-XSCache-MulanPSL-2.0.txt    |   132 +
 ...penXiangShan-XSCache-SiFive-Apache-2.0.txt |   202 +
 .../OpenXiangShan-XiangShan-MulanPSL-2.0.txt  |   127 +
 .../xiangshan_coupledl2/LICENSES/README.md    |    16 +
 .../VLSIDA-bsg_fakeram-BSD-3-Clause.txt       |    29 +
 .../PROVENANCE/selected-rtl.tsv               |   139 +
 .../designs/src/xiangshan_coupledl2/SOURCE.md |    51 +
 .../deps/Arbiter16_CHIDAT.sv                  |   560 +
 .../deps/Arbiter16_TLBundleD.sv               |   364 +
 .../deps/Arbiter1_L2CacheErrorInfo.sv         |    14 +
 .../deps/Arbiter3_CHIREQ.sv                   |   119 +
 .../deps/Arbiter3_HintQueueEntry.sv           |    48 +
 .../deps/Arbiter3_TaskBundle.sv               |    95 +
 .../deps/Arbiter3_TaskWithData.sv             |   846 +
 .../src/xiangshan_coupledl2/deps/ClockGate.sv |    14 +
 .../src/xiangshan_coupledl2/deps/ClockMux.sv  |    10 +
 .../xiangshan_coupledl2/deps/CustomL1Hint.sv  |   230 +
 .../xiangshan_coupledl2/deps/DataStorage.sv   |   511 +
 .../deps/Decoupled2LCredit.sv                 |   185 +
 .../deps/Decoupled2LCredit_1.sv               |   147 +
 .../deps/Decoupled2LCredit_2.sv               |   179 +
 .../xiangshan_coupledl2/deps/DelayQueue.sv    |   478 +
 .../xiangshan_coupledl2/deps/DelayQueue_1.sv  |   478 +
 .../src/xiangshan_coupledl2/deps/Directory.sv |  2718 +++
 .../deps/FastArbiter_10.sv                    |   625 +
 .../deps/FastArbiter_12.sv                    |   207 +
 .../deps/FastArbiter_16.sv                    |   251 +
 .../deps/FastArbiter_18.sv                    |   128 +
 .../xiangshan_coupledl2/deps/FastArbiter_2.sv |   435 +
 .../deps/FastArbiter_20.sv                    |   257 +
 .../deps/FastArbiter_22.sv                    |  1430 ++
 .../deps/FastArbiter_24.sv                    |    98 +
 .../deps/FastArbiter_26.sv                    |    50 +
 .../deps/FastArbiter_27.sv                    |   225 +
 .../deps/FastArbiter_28.sv                    |   444 +
 .../xiangshan_coupledl2/deps/FastArbiter_4.sv |   214 +
 .../xiangshan_coupledl2/deps/FastArbiter_6.sv |   274 +
 .../xiangshan_coupledl2/deps/FastArbiter_8.sv |    29 +
 .../xiangshan_coupledl2/deps/FastArbiter_9.sv |     9 +
 .../deps/GatedSplittedSRAM.sv                 |   283 +
 .../xiangshan_coupledl2/deps/GrantBuffer.sv   |  1131 ++
 .../src/xiangshan_coupledl2/deps/L2Cache.sv   |   213 +
 .../xiangshan_coupledl2/deps/L2DataStorage.sv |   247 +
 .../xiangshan_coupledl2/deps/L2Directory.sv   |   266 +
 .../src/xiangshan_coupledl2/deps/L2Slice.sv   |   212 +
 .../deps/LCredit2Decoupled.sv                 |   166 +
 .../deps/LCredit2Decoupled_1.sv               |   139 +
 .../deps/LCredit2Decoupled_2.sv               |   157 +
 .../xiangshan_coupledl2/deps/LinkMonitor.sv   |   493 +
 .../xiangshan_coupledl2/deps/MMIOBridge.sv    |  2607 +++
 .../deps/MMIOBridgeEntry.sv                   |   436 +
 .../deps/MMIOBridgeEntry_2.sv                 |   436 +
 .../deps/MMIOBridgeEntry_4.sv                 |   436 +
 .../deps/MMIOBridgeEntry_8.sv                 |   436 +
 .../src/xiangshan_coupledl2/deps/MSHR.sv      |  1781 ++
 .../xiangshan_coupledl2/deps/MSHRBuffer.sv    |   607 +
 .../xiangshan_coupledl2/deps/MSHRBuffer_1.sv  |   625 +
 .../src/xiangshan_coupledl2/deps/MSHRCtl.sv   | 13739 ++++++++++++++++
 .../xiangshan_coupledl2/deps/MSHRSelector.sv  |    39 +
 .../xiangshan_coupledl2/deps/MainPipe_1.sv    |  4148 +++++
 .../deps/MbistClockGateCell_186.sv            |    28 +
 .../xiangshan_coupledl2/deps/MbistIntfL2.sv   |    38 +
 .../deps/MbistPipeL2Prefetcher.sv             |   185 +
 .../deps/OffsetScoreTable.sv                  |   724 +
 .../deps/OffsetScoreTable_1.sv                |  1636 ++
 .../deps/OverwriteQueue.sv                    |   739 +
 .../deps/PBestOffsetPrefetch.sv               |   216 +
 .../xiangshan_coupledl2/deps/Pipeline_10.sv   |    71 +
 .../xiangshan_coupledl2/deps/Pipeline_5.sv    |    43 +
 .../xiangshan_coupledl2/deps/Pipeline_6.sv    |    33 +
 .../xiangshan_coupledl2/deps/Pipeline_7.sv    |    47 +
 .../xiangshan_coupledl2/deps/Pipeline_8.sv    |    19 +
 .../xiangshan_coupledl2/deps/Pipeline_9.sv    |   107 +
 .../deps/PrefetchReqBuffer.sv                 |  1506 ++
 .../xiangshan_coupledl2/deps/Prefetcher.sv    |   327 +
 .../deps/Queue10_GrantBuffer_Anon.sv          |   109 +
 .../deps/Queue16_CHIREQ.sv                    |   208 +
 .../deps/Queue16_CHIRSP.sv                    |   167 +
 .../deps/Queue16_DSBeat.sv                    |   115 +
 .../deps/Queue16_GrantQueueData.sv            |   113 +
 .../deps/Queue16_GrantQueueTask.sv            |   234 +
 .../deps/Queue16_HintQueueEntry.sv            |   128 +
 .../deps/Queue16_TaskBundle.sv                |   246 +
 .../xiangshan_coupledl2/deps/Queue1_CHIDAT.sv |   197 +
 .../xiangshan_coupledl2/deps/Queue1_CHIRSP.sv |   147 +
 .../deps/Queue1_ChosenQBundle.sv              |   341 +
 .../deps/Queue1_HintQueueEntry.sv             |   107 +
 .../deps/Queue1_PrefetchReq.sv                |   119 +
 .../deps/Queue1_PrefetchResp.sv               |    86 +
 .../deps/Queue1_PrefetchTrain.sv              |   123 +
 .../xiangshan_coupledl2/deps/Queue2_CHISNP.sv |   154 +
 .../deps/Queue2_PCrdGranted.sv                |   122 +
 .../deps/Queue30_PCrdGranted.sv               |   121 +
 .../xiangshan_coupledl2/deps/Queue4_CHISNP.sv |   174 +
 .../src/xiangshan_coupledl2/deps/RXDAT.sv     |    81 +
 .../src/xiangshan_coupledl2/deps/RXRSP.sv     |    32 +
 .../src/xiangshan_coupledl2/deps/RXSNP.sv     |  1262 ++
 .../deps/RecentRequestTable.sv                |   172 +
 .../deps/RecentRequestTable_1.sv              |   172 +
 .../xiangshan_coupledl2/deps/RequestArb.sv    |  3443 ++++
 .../xiangshan_coupledl2/deps/RequestBuffer.sv |  3372 ++++
 .../deps/SRAMTemplate_239.sv                  |   166 +
 .../deps/SRAMTemplate_241.sv                  |   165 +
 .../deps/SRAMTemplate_243.sv                  |   436 +
 .../deps/SRAMTemplate_244.sv                  |   161 +
 .../deps/SRAMTemplate_245.sv                  |   198 +
 .../deps/SRAMTemplate_246.sv                  |   168 +
 .../deps/SRAMTemplate_247.sv                  |   168 +
 .../src/xiangshan_coupledl2/deps/SinkA.sv     |    67 +
 .../src/xiangshan_coupledl2/deps/SinkC.sv     |  3256 ++++
 .../src/xiangshan_coupledl2/deps/Slice.sv     | 10069 +++++++++++
 .../src/xiangshan_coupledl2/deps/SourceB.sv   |   491 +
 .../deps/SplittedSRAM_3.sv                    |   137 +
 .../src/xiangshan_coupledl2/deps/TXDAT.sv     |   530 +
 .../src/xiangshan_coupledl2/deps/TXREQ.sv     |   175 +
 .../src/xiangshan_coupledl2/deps/TXRSP.sv     |   120 +
 .../deps/TwoLevelRRArbiter_1.sv               |   761 +
 .../deps/TwoLevelRRArbiter_10.sv              |  3310 ++++
 .../deps/TwoLevelRRArbiter_11.sv              |   424 +
 .../deps/TwoLevelRRArbiter_12.sv              |   226 +
 .../deps/TwoLevelRRArbiter_2.sv               |   201 +
 .../deps/TwoLevelRRArbiter_3.sv               |   358 +
 .../deps/TwoLevelRRArbiter_4.sv               |  1648 ++
 .../deps/TwoLevelRRArbiter_5.sv               |   405 +
 .../deps/TwoLevelRRArbiter_7.sv               |   287 +
 .../deps/TwoLevelRRArbiter_8.sv               |   190 +
 .../deps/TwoLevelRRArbiter_9.sv               |   326 +
 .../deps/VBestOffsetPrefetch.sv               |   244 +
 .../deps/array_2048x137_wrap.sv               |    86 +
 .../xiangshan_coupledl2/deps/ram_16x148.sv    |    91 +
 .../src/xiangshan_coupledl2/deps/ram_16x25.sv |    89 +
 .../src/xiangshan_coupledl2/deps/ram_16x73.sv |    91 +
 .../src/xiangshan_coupledl2/deps/ram_16x78.sv |    91 +
 .../src/xiangshan_coupledl2/deps/ram_16x9.sv  |    89 +
 .../src/xiangshan_coupledl2/deps/ram_2x15.sv  |    89 +
 .../src/xiangshan_coupledl2/deps/ram_2x98.sv  |    91 +
 .../src/xiangshan_coupledl2/deps/ram_30x15.sv |    89 +
 .../src/xiangshan_coupledl2/deps/ram_4x115.sv |    91 +
 .../deps/ram_data_16x256.sv                   |    91 +
 ...sram_array_1p2048x137m137s1h1l2b_l2_dat.sv |    21 +
 .../sram_array_1p256x104m13s1h0l1b_l2_meta.sv |    47 +
 ...m_array_1p256x13m13s1h0l1b_l2_pftch_rrt.sv |    21 +
 .../sram_array_1p256x164m41s1h0l1b_l2_tag.sv  |    35 +
 .../sram_array_1p256x16m16s1h0l1b_l2_repl.sv  |    21 +
 .../sram_array_1p256x8m1s1h0l1b_l2_orgb.sv    |    47 +
 .../platforms/asap7/lef/array_2048x137_bk.lef |  2670 +++
 flow/platforms/asap7/lef/array_256x104.lef    |  2147 +++
 flow/platforms/asap7/lef/array_256x13.lef     |   425 +
 flow/platforms/asap7/lef/array_256x16.lef     |   479 +
 flow/platforms/asap7/lef/array_256x164.lef    |  3198 ++++
 flow/platforms/asap7/lef/array_256x8_0.lef    |   409 +
 .../asap7/lib/NLDM/array_2048x137_bk.lib      |   395 +
 .../asap7/lib/NLDM/array_256x104.lib          |   474 +
 .../platforms/asap7/lib/NLDM/array_256x13.lib |   395 +
 .../platforms/asap7/lib/NLDM/array_256x16.lib |   395 +
 .../asap7/lib/NLDM/array_256x164.lib          |   474 +
 .../asap7/lib/NLDM/array_256x8_0.lib          |   474 +
 .../asap7/verilog/array_2048x137_bk_bb.sv     |    10 +
 .../asap7/verilog/array_256x104_bb.sv         |    11 +
 .../asap7/verilog/array_256x13_bb.sv          |    10 +
 .../asap7/verilog/array_256x164_bb.sv         |    11 +
 .../asap7/verilog/array_256x16_bb.sv          |    10 +
 .../asap7/verilog/array_256x8_0_bb.sv         |    11 +
 .../nangate45/lef/array_2048x137_bk.lef       |  2714 +++
 .../platforms/nangate45/lef/array_256x104.lef |  2182 +++
 flow/platforms/nangate45/lef/array_256x13.lef |   418 +
 flow/platforms/nangate45/lef/array_256x16.lef |   472 +
 .../platforms/nangate45/lef/array_256x164.lef |  3241 ++++
 .../platforms/nangate45/lef/array_256x8_0.lef |   437 +
 .../nangate45/lib/array_2048x137_bk.lib       |   395 +
 .../platforms/nangate45/lib/array_256x104.lib |   474 +
 flow/platforms/nangate45/lib/array_256x13.lib |   395 +
 flow/platforms/nangate45/lib/array_256x16.lib |   395 +
 .../platforms/nangate45/lib/array_256x164.lib |   474 +
 .../platforms/nangate45/lib/array_256x8_0.lib |   474 +
 .../nangate45/verilog/array_2048x137_bk_bb.sv |    10 +
 .../nangate45/verilog/array_256x104_bb.sv     |    11 +
 .../nangate45/verilog/array_256x13_bb.sv      |    10 +
 .../nangate45/verilog/array_256x164_bb.sv     |    11 +
 .../nangate45/verilog/array_256x16_bb.sv      |    10 +
 .../nangate45/verilog/array_256x8_0_bb.sv     |    11 +
 213 files changed, 114973 insertions(+)
 create mode 100644 flow/designs/asap7/picorv32/config.mk
 create mode 100644 flow/designs/asap7/picorv32/constraint.sdc
 create mode 100644 flow/designs/asap7/picorv32/rules-base.json
 create mode 100644 flow/designs/asap7/tpu/config.mk
 create mode 100644 flow/designs/asap7/tpu/constraint.sdc
 create mode 100644 flow/designs/asap7/tpu/rules-base.json
 create mode 100644 flow/designs/asap7/xiangshan_coupledl2/config.mk
 create mode 100644 flow/designs/asap7/xiangshan_coupledl2/constraint.sdc
 create mode 100644 flow/designs/asap7/xiangshan_coupledl2/fakeram.cfg
 create mode 100644 flow/designs/asap7/xiangshan_coupledl2/rules-base.json
 create mode 100644 flow/designs/nangate45/picorv32/config.mk
 create mode 100644 flow/designs/nangate45/picorv32/constraint.sdc
 create mode 100644 flow/designs/nangate45/picorv32/rules-base.json
 create mode 100644 flow/designs/nangate45/tpu/config.mk
 create mode 100644 flow/designs/nangate45/tpu/constraint.sdc
 create mode 100644 flow/designs/nangate45/tpu/rules-base.json
 create mode 100644 flow/designs/nangate45/xiangshan_coupledl2/config.mk
 create mode 100644 flow/designs/nangate45/xiangshan_coupledl2/constraint.sdc
 create mode 100644 flow/designs/nangate45/xiangshan_coupledl2/fakeram.cfg
 create mode 100644 flow/designs/nangate45/xiangshan_coupledl2/rules-base.json
 create mode 100644 flow/designs/src/picorv32/LICENSES/LogikBench-MIT.txt
 create mode 100644 flow/designs/src/picorv32/LICENSES/PicoRV32-ISC.txt
 create mode 100644 flow/designs/src/picorv32/SOURCE.md
 create mode 100644 flow/designs/src/picorv32/picorv32.sv
 create mode 100644 flow/designs/src/tpu/LICENSES/LogikBench-MIT.txt
 create mode 100644 flow/designs/src/tpu/SOURCE.md
 create mode 100644 flow/designs/src/tpu/tpu.sv
 create mode 100644 flow/designs/src/tpu/tpu_array.sv
 create mode 100644 flow/designs/src/tpu/tpu_pe.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/CoupledL2.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/LICENSES/Chisel-Apache-2.0.txt
 create mode 100644 flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XSCache-MulanPSL-2.0.txt
 create mode 100644 flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XSCache-SiFive-Apache-2.0.txt
 create mode 100644 flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XiangShan-MulanPSL-2.0.txt
 create mode 100644 flow/designs/src/xiangshan_coupledl2/LICENSES/README.md
 create mode 100644 flow/designs/src/xiangshan_coupledl2/LICENSES/VLSIDA-bsg_fakeram-BSD-3-Clause.txt
 create mode 100644 flow/designs/src/xiangshan_coupledl2/PROVENANCE/selected-rtl.tsv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/SOURCE.md
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Arbiter16_CHIDAT.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Arbiter16_TLBundleD.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Arbiter1_L2CacheErrorInfo.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_CHIREQ.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_HintQueueEntry.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_TaskBundle.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_TaskWithData.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ClockGate.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ClockMux.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/CustomL1Hint.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/DataStorage.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit_1.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit_2.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/DelayQueue.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/DelayQueue_1.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Directory.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_10.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_12.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_16.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_18.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_2.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_20.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_22.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_24.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_26.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_27.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_28.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_4.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_6.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_8.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_9.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/GatedSplittedSRAM.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/GrantBuffer.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/L2Cache.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/L2DataStorage.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/L2Directory.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/L2Slice.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled_1.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled_2.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/LinkMonitor.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MMIOBridge.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_2.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_4.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_8.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MSHR.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MSHRBuffer.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MSHRBuffer_1.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MSHRCtl.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MSHRSelector.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MainPipe_1.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MbistClockGateCell_186.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MbistIntfL2.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/MbistPipeL2Prefetcher.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/OffsetScoreTable.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/OffsetScoreTable_1.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/OverwriteQueue.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/PBestOffsetPrefetch.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Pipeline_10.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Pipeline_5.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Pipeline_6.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Pipeline_7.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Pipeline_8.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Pipeline_9.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/PrefetchReqBuffer.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Prefetcher.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue10_GrantBuffer_Anon.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue16_CHIREQ.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue16_CHIRSP.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue16_DSBeat.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue16_GrantQueueData.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue16_GrantQueueTask.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue16_HintQueueEntry.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue16_TaskBundle.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue1_CHIDAT.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue1_CHIRSP.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue1_ChosenQBundle.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue1_HintQueueEntry.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchReq.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchResp.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchTrain.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue2_CHISNP.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue2_PCrdGranted.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue30_PCrdGranted.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Queue4_CHISNP.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/RXDAT.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/RXRSP.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/RXSNP.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/RecentRequestTable.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/RecentRequestTable_1.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/RequestArb.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/RequestBuffer.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_239.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_241.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_243.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_244.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_245.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_246.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_247.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SinkA.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SinkC.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/Slice.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SourceB.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/SplittedSRAM_3.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TXDAT.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TXREQ.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TXRSP.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_1.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_10.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_11.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_12.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_2.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_3.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_4.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_5.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_7.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_8.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_9.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/VBestOffsetPrefetch.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/array_2048x137_wrap.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_16x148.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_16x25.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_16x73.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_16x78.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_16x9.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_2x15.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_2x98.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_30x15.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_4x115.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/ram_data_16x256.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p2048x137m137s1h1l2b_l2_dat.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x104m13s1h0l1b_l2_meta.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x13m13s1h0l1b_l2_pftch_rrt.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x164m41s1h0l1b_l2_tag.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x16m16s1h0l1b_l2_repl.sv
 create mode 100644 flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x8m1s1h0l1b_l2_orgb.sv
 create mode 100644 flow/platforms/asap7/lef/array_2048x137_bk.lef
 create mode 100644 flow/platforms/asap7/lef/array_256x104.lef
 create mode 100644 flow/platforms/asap7/lef/array_256x13.lef
 create mode 100644 flow/platforms/asap7/lef/array_256x16.lef
 create mode 100644 flow/platforms/asap7/lef/array_256x164.lef
 create mode 100644 flow/platforms/asap7/lef/array_256x8_0.lef
 create mode 100644 flow/platforms/asap7/lib/NLDM/array_2048x137_bk.lib
 create mode 100644 flow/platforms/asap7/lib/NLDM/array_256x104.lib
 create mode 100644 flow/platforms/asap7/lib/NLDM/array_256x13.lib
 create mode 100644 flow/platforms/asap7/lib/NLDM/array_256x16.lib
 create mode 100644 flow/platforms/asap7/lib/NLDM/array_256x164.lib
 create mode 100644 flow/platforms/asap7/lib/NLDM/array_256x8_0.lib
 create mode 100644 flow/platforms/asap7/verilog/array_2048x137_bk_bb.sv
 create mode 100644 flow/platforms/asap7/verilog/array_256x104_bb.sv
 create mode 100644 flow/platforms/asap7/verilog/array_256x13_bb.sv
 create mode 100644 flow/platforms/asap7/verilog/array_256x164_bb.sv
 create mode 100644 flow/platforms/asap7/verilog/array_256x16_bb.sv
 create mode 100644 flow/platforms/asap7/verilog/array_256x8_0_bb.sv
 create mode 100644 flow/platforms/nangate45/lef/array_2048x137_bk.lef
 create mode 100644 flow/platforms/nangate45/lef/array_256x104.lef
 create mode 100644 flow/platforms/nangate45/lef/array_256x13.lef
 create mode 100644 flow/platforms/nangate45/lef/array_256x16.lef
 create mode 100644 flow/platforms/nangate45/lef/array_256x164.lef
 create mode 100644 flow/platforms/nangate45/lef/array_256x8_0.lef
 create mode 100644 flow/platforms/nangate45/lib/array_2048x137_bk.lib
 create mode 100644 flow/platforms/nangate45/lib/array_256x104.lib
 create mode 100644 flow/platforms/nangate45/lib/array_256x13.lib
 create mode 100644 flow/platforms/nangate45/lib/array_256x16.lib
 create mode 100644 flow/platforms/nangate45/lib/array_256x164.lib
 create mode 100644 flow/platforms/nangate45/lib/array_256x8_0.lib
 create mode 100644 flow/platforms/nangate45/verilog/array_2048x137_bk_bb.sv
 create mode 100644 flow/platforms/nangate45/verilog/array_256x104_bb.sv
 create mode 100644 flow/platforms/nangate45/verilog/array_256x13_bb.sv
 create mode 100644 flow/platforms/nangate45/verilog/array_256x164_bb.sv
 create mode 100644 flow/platforms/nangate45/verilog/array_256x16_bb.sv
 create mode 100644 flow/platforms/nangate45/verilog/array_256x8_0_bb.sv

diff --git a/flow/Makefile b/flow/Makefile
index b331a691cd..9e849b0f2f 100644
--- a/flow/Makefile
+++ b/flow/Makefile
@@ -21,9 +21,12 @@
 # DESIGN_CONFIG=./designs/nangate45/ibex/config.mk
 # DESIGN_CONFIG=./designs/nangate45/jpeg/config.mk
 # DESIGN_CONFIG=./designs/nangate45/mempool_group/config.mk
+# DESIGN_CONFIG=./designs/nangate45/picorv32/config.mk
 # DESIGN_CONFIG=./designs/nangate45/swerv/config.mk
 # DESIGN_CONFIG=./designs/nangate45/swerv_wrapper/config.mk
 # DESIGN_CONFIG=./designs/nangate45/tinyRocket/config.mk
+# DESIGN_CONFIG=./designs/nangate45/tpu/config.mk
+# DESIGN_CONFIG=./designs/nangate45/xiangshan_coupledl2/config.mk
 
 # DESIGN_CONFIG=./designs/gf12/aes/config.mk
 # DESIGN_CONFIG=./designs/gf12/ariane/config.mk
@@ -60,9 +63,12 @@
 # DESIGN_CONFIG=./designs/asap7/ibex/config.mk
 # DESIGN_CONFIG=./designs/asap7/jpeg/config.mk
 # DESIGN_CONFIG=./designs/asap7/megaboom/config.mk
+# DESIGN_CONFIG=./designs/asap7/picorv32/config.mk
 # DESIGN_CONFIG=./designs/asap7/riscv32i/config.mk
 # DESIGN_CONFIG=./designs/asap7/swerv_wrapper/config.mk
+# DESIGN_CONFIG=./designs/asap7/tpu/config.mk
 # DESIGN_CONFIG=./designs/asap7/uart/config.mk
+# DESIGN_CONFIG=./designs/asap7/xiangshan_coupledl2/config.mk
 
 # DESIGN_CONFIG=./designs/intel16/aes/config.mk
 # DESIGN_CONFIG=./designs/intel16/gcd/config.mk
diff --git a/flow/designs/asap7/picorv32/config.mk b/flow/designs/asap7/picorv32/config.mk
new file mode 100644
index 0000000000..68d0a0b281
--- /dev/null
+++ b/flow/designs/asap7/picorv32/config.mk
@@ -0,0 +1,21 @@
+export PLATFORM = asap7
+export DESIGN_NAME = picorv32
+
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/picorv32/*.sv))
+export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export ASAP7_USE_VT = RVT LVT SLVT
+
+# Synthesis
+export SYNTH_OPERATIONS_ARGS = -booth
+export REMOVE_ABC_BUFFERS = 1
+export SYNTH_RETIME_MODULES = $(DESIGN_NAME)
+export SYNTH_HDL_FRONTEND = slang
+export LEC_CHECK = 0
+
+# Floorplan
+export CORE_UTILIZATION = 60
+export CORE_ASPECT_RATIO = 1
+export CORE_MARGIN = 2
+
+export TNS_END_PERCENT = 100
diff --git a/flow/designs/asap7/picorv32/constraint.sdc b/flow/designs/asap7/picorv32/constraint.sdc
new file mode 100644
index 0000000000..56023be662
--- /dev/null
+++ b/flow/designs/asap7/picorv32/constraint.sdc
@@ -0,0 +1,10 @@
+set_units -time ps -capacitance fF -resistance kOhm -voltage V -current mA -power pW
+current_design picorv32
+
+set clk_period 300
+set io_delay [expr 0.20 * $clk_period]
+create_clock -name core_clock -period $clk_period [get_ports clk]
+create_clock -name vclk_core -period $clk_period
+set_max_fanout 16 [current_design]
+set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks]
+set_output_delay $io_delay -clock vclk_core [all_outputs]
diff --git a/flow/designs/asap7/picorv32/rules-base.json b/flow/designs/asap7/picorv32/rules-base.json
new file mode 100644
index 0000000000..7ce66606a5
--- /dev/null
+++ b/flow/designs/asap7/picorv32/rules-base.json
@@ -0,0 +1,112 @@
+{
+    "synth__canonical_netlist__hash": {
+        "value": "e4ff1176ec5b0f3d0fe6b92a6a8dfd6c2f841d84",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__netlist__hash": {
+        "value": "f224cc0c978bde0570734d1aff0a28360b477a40",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__design__instance__area__stdcell": {
+        "value": 2620.0,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 2,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 2762,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 24496,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 2130,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 2130,
+        "compare": "<="
+    },
+    "cts__timing__setup__ws": {
+        "value": -429.0,
+        "compare": ">="
+    },
+    "cts__timing__setup__tns": {
+        "value": -18000.0,
+        "compare": ">="
+    },
+    "cts__timing__hold__ws": {
+        "value": -20.0,
+        "compare": ">="
+    },
+    "cts__timing__hold__tns": {
+        "value": -80.0,
+        "compare": ">="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "globalroute__timing__setup__ws": {
+        "value": -461.0,
+        "compare": ">="
+    },
+    "globalroute__timing__setup__tns": {
+        "value": -22000.0,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__ws": {
+        "value": -20.0,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__tns": {
+        "value": -80.0,
+        "compare": ">="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 87408,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -417.0,
+        "compare": ">="
+    },
+    "finish__timing__setup__tns": {
+        "value": -18600.0,
+        "compare": ">="
+    },
+    "finish__timing__hold__ws": {
+        "value": -20.0,
+        "compare": ">="
+    },
+    "finish__timing__hold__tns": {
+        "value": -80.0,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 2885,
+        "compare": "<="
+    }
+}
diff --git a/flow/designs/asap7/tpu/config.mk b/flow/designs/asap7/tpu/config.mk
new file mode 100644
index 0000000000..c349601544
--- /dev/null
+++ b/flow/designs/asap7/tpu/config.mk
@@ -0,0 +1,21 @@
+export PLATFORM = asap7
+export DESIGN_NAME = tpu
+
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/tpu/*.sv))
+export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+export ASAP7_USE_VT = RVT LVT SLVT
+
+# Synthesis
+export SYNTH_HDL_FRONTEND = slang
+export LEC_CHECK = 0
+
+# Floorplan
+export CORE_UTILIZATION = 60
+export CORE_ASPECT_RATIO = 1
+export CORE_MARGIN = 2
+
+export TNS_END_PERCENT = 100
+
+# Routing
+export MAX_ROUTING_LAYER = M9
diff --git a/flow/designs/asap7/tpu/constraint.sdc b/flow/designs/asap7/tpu/constraint.sdc
new file mode 100644
index 0000000000..a447a41f8c
--- /dev/null
+++ b/flow/designs/asap7/tpu/constraint.sdc
@@ -0,0 +1,10 @@
+set_units -time ps -capacitance fF -resistance kOhm -voltage V -current mA -power pW
+current_design tpu
+
+set clk_period 200
+set io_delay [expr 0.20 * $clk_period]
+create_clock -name core_clock -period $clk_period [get_ports clk]
+create_clock -name vclk_core -period $clk_period
+set_max_fanout 16 [current_design]
+set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks]
+set_output_delay $io_delay -clock vclk_core [all_outputs]
diff --git a/flow/designs/asap7/tpu/rules-base.json b/flow/designs/asap7/tpu/rules-base.json
new file mode 100644
index 0000000000..0a422b4549
--- /dev/null
+++ b/flow/designs/asap7/tpu/rules-base.json
@@ -0,0 +1,112 @@
+{
+    "synth__canonical_netlist__hash": {
+        "value": "d93c1a668eaa8748f4ddbc8ed4ce3334d5b0ec1b",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__netlist__hash": {
+        "value": "b76c679a52aa60fd98a6195d467f06e647c75ad6",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__design__instance__area__stdcell": {
+        "value": 6020.0,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 2,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 5926,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 52923,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 4602,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 4602,
+        "compare": "<="
+    },
+    "cts__timing__setup__ws": {
+        "value": -50.0,
+        "compare": ">="
+    },
+    "cts__timing__setup__tns": {
+        "value": -200.0,
+        "compare": ">="
+    },
+    "cts__timing__hold__ws": {
+        "value": -50.0,
+        "compare": ">="
+    },
+    "cts__timing__hold__tns": {
+        "value": -200.0,
+        "compare": ">="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "globalroute__timing__setup__ws": {
+        "value": -50.0,
+        "compare": ">="
+    },
+    "globalroute__timing__setup__tns": {
+        "value": -200.0,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__ws": {
+        "value": -50.0,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__tns": {
+        "value": -200.0,
+        "compare": ">="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 119542,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -50.0,
+        "compare": ">="
+    },
+    "finish__timing__setup__tns": {
+        "value": -200.0,
+        "compare": ">="
+    },
+    "finish__timing__hold__ws": {
+        "value": -50.0,
+        "compare": ">="
+    },
+    "finish__timing__hold__tns": {
+        "value": -200.0,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 6092,
+        "compare": "<="
+    }
+}
diff --git a/flow/designs/asap7/xiangshan_coupledl2/config.mk b/flow/designs/asap7/xiangshan_coupledl2/config.mk
new file mode 100644
index 0000000000..aa70fe9b41
--- /dev/null
+++ b/flow/designs/asap7/xiangshan_coupledl2/config.mk
@@ -0,0 +1,63 @@
+export PLATFORM = asap7
+export DESIGN_NAME = CoupledL2
+export DESIGN_NICKNAME = xiangshan_coupledl2
+
+export VERILOG_FILES = $(sort \
+  $(wildcard $(DESIGN_HOME)/src/xiangshan_coupledl2/*.sv) \
+  $(wildcard $(DESIGN_HOME)/src/xiangshan_coupledl2/deps/*.sv)) \
+  $(PLATFORM_DIR)/verilog/array_2048x137_bk_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x104_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x13_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x164_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x16_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x8_0_bb.sv
+export VERILOG_DEFINES += -D SYNTHESIS
+export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+# Fakeram macros for the SRAM arrays; fakeram.cfg in this directory records how
+# the platform views were generated.
+export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/array_2048x137_bk.lef \
+                         $(PLATFORM_DIR)/lef/array_256x104.lef \
+                         $(PLATFORM_DIR)/lef/array_256x13.lef \
+                         $(PLATFORM_DIR)/lef/array_256x164.lef \
+                         $(PLATFORM_DIR)/lef/array_256x16.lef \
+                         $(PLATFORM_DIR)/lef/array_256x8_0.lef
+export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/NLDM/array_2048x137_bk.lib \
+                         $(PLATFORM_DIR)/lib/NLDM/array_256x104.lib \
+                         $(PLATFORM_DIR)/lib/NLDM/array_256x13.lib \
+                         $(PLATFORM_DIR)/lib/NLDM/array_256x164.lib \
+                         $(PLATFORM_DIR)/lib/NLDM/array_256x16.lib \
+                         $(PLATFORM_DIR)/lib/NLDM/array_256x8_0.lib
+export GDS_ALLOW_EMPTY = (fakeram.*|DFFHQN[VH][24].*|array_.*)
+
+export ASAP7_USE_VT = RVT LVT SLVT
+
+# Synthesis
+export SYNTH_HIERARCHICAL = 1
+export SYNTH_MINIMUM_KEEP_SIZE ?= 10000
+export SYNTH_HDL_FRONTEND = slang
+export LEC_CHECK = 0
+
+# Floorplan
+export CORE_UTILIZATION = 50
+export CORE_ASPECT_RATIO = 1
+export CORE_MARGIN = 2
+export MACRO_PLACE_HALO = 5 5
+
+# Placement and timing repair
+export GPL_TIMING_DRIVEN = 0
+export GPL_ROUTABILITY_DRIVEN = 0
+export TNS_END_PERCENT = 5
+export SKIP_CTS_REPAIR_TIMING = 1
+export SKIP_INCREMENTAL_REPAIR = 1
+export ENABLE_RESISTANCE_AWARE = 0
+
+# Routing
+export GLOBAL_ROUTE_ARGS = -congestion_iterations 5 -congestion_report_iter_step 5 -verbose -allow_congestion
+# FlexDR on current master reports DRT-0206 terminal-connectivity errors for
+# this design, so detailed routing is skipped and the Final report uses
+# global-route estimated parasitics.
+export SKIP_DETAILED_ROUTE = 1
+export DETAILED_ROUTE_END_ITERATION = 32
+export SKIP_ANTENNA_REPAIR = 1
+export SKIP_ANTENNA_REPAIR_POST_DRT = 1
diff --git a/flow/designs/asap7/xiangshan_coupledl2/constraint.sdc b/flow/designs/asap7/xiangshan_coupledl2/constraint.sdc
new file mode 100644
index 0000000000..8b062f0315
--- /dev/null
+++ b/flow/designs/asap7/xiangshan_coupledl2/constraint.sdc
@@ -0,0 +1,15 @@
+set_units -time ps -capacitance fF -resistance kOhm -voltage V -current mA -power pW
+current_design CoupledL2
+
+# The 1400 ps target keeps the public CI runtime bounded while leaving setup
+# violations for optimization experiments; it is not a measured Fmax of this
+# 128 KiB MinimalConfig L2.
+set clk_period 1400
+set io_delay [expr 0.20 * $clk_period]
+create_clock -name core_clock -period $clk_period [get_ports clock]
+create_clock -name vclk_core -period $clk_period
+set_max_fanout 16 [current_design]
+# Exclude the asynchronous reset from data-path timing optimization.
+set_false_path -from [get_ports reset]
+set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks]
+set_output_delay $io_delay -clock vclk_core [all_outputs]
diff --git a/flow/designs/asap7/xiangshan_coupledl2/fakeram.cfg b/flow/designs/asap7/xiangshan_coupledl2/fakeram.cfg
new file mode 100644
index 0000000000..4edc71f350
--- /dev/null
+++ b/flow/designs/asap7/xiangshan_coupledl2/fakeram.cfg
@@ -0,0 +1,26 @@
+# Generated with VLSIDA/bsg_fakeram commit c83ecb47f5a90d2e92d589b4f63a2e38c25c1afd.
+# Generated rw0_* physical pins are renamed to the RTL's RW0_* interface.
+{
+  "tech_nm": 7,
+  "voltage": 0.7,
+  "metalPrefix": "M",
+  "LRpinWidth_nm": 24,
+  "LRpinPitch_nm": 48,
+  "TBpinWidth_nm": 18,
+  "TBpinPitch_nm": 36,
+  "manufacturing_grid_nm": 1,
+  "contacted_poly_pitch_nm": 54,
+  "column_mux_factor": 3,
+  "fin_pitch_nm": 27,
+  "flipPins": false,
+  "snap_width_nm": 190,
+  "snap_height_nm": 1400,
+  "srams": [
+    {"name": "array_2048x137_bk", "width": 137, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x104", "width": 104, "depth": 256, "banks": 1, "no_wmask": "false", "write_granularity": 13, "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x13", "width": 13, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x164", "width": 164, "depth": 256, "banks": 1, "no_wmask": "false", "write_granularity": 41, "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x16", "width": 16, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x8_0", "width": 8, "depth": 256, "banks": 1, "no_wmask": "false", "write_granularity": 1, "ports": {"r": 0, "w": 0, "rw": 1}}
+  ]
+}
diff --git a/flow/designs/asap7/xiangshan_coupledl2/rules-base.json b/flow/designs/asap7/xiangshan_coupledl2/rules-base.json
new file mode 100644
index 0000000000..54d11cc226
--- /dev/null
+++ b/flow/designs/asap7/xiangshan_coupledl2/rules-base.json
@@ -0,0 +1,44 @@
+{
+    "synth__canonical_netlist__hash": {
+        "value": "33f2b4072fe999569e74883744b385a9f53929b4",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__netlist__hash": {
+        "value": "5d6fc356ed0cb276bac47e41fd223bb5c1363b78",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__design__instance__area__stdcell": {
+        "value": 68900.0,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 2,
+        "compare": "=="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "finish__timing__setup__ws": {
+        "value": -284.0,
+        "compare": ">="
+    },
+    "finish__timing__setup__tns": {
+        "value": -60900.0,
+        "compare": ">="
+    },
+    "finish__timing__hold__ws": {
+        "value": -795.0,
+        "compare": ">="
+    },
+    "finish__timing__hold__tns": {
+        "value": -4150000.0,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 113945,
+        "compare": "<="
+    }
+}
diff --git a/flow/designs/nangate45/picorv32/config.mk b/flow/designs/nangate45/picorv32/config.mk
new file mode 100644
index 0000000000..45a6a3833b
--- /dev/null
+++ b/flow/designs/nangate45/picorv32/config.mk
@@ -0,0 +1,18 @@
+export PLATFORM = nangate45
+export DESIGN_NAME = picorv32
+
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/picorv32/*.sv))
+export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+# Synthesis
+export ABC_CLOCK_PERIOD_IN_PS = 900
+export SYNTH_RETIME_MODULES = $(DESIGN_NAME)
+export SYNTH_HDL_FRONTEND = slang
+export LEC_CHECK = 0
+
+# Floorplan
+export CORE_UTILIZATION = 60
+export CORE_ASPECT_RATIO = 1
+export CORE_MARGIN = 2
+
+export TNS_END_PERCENT = 100
diff --git a/flow/designs/nangate45/picorv32/constraint.sdc b/flow/designs/nangate45/picorv32/constraint.sdc
new file mode 100644
index 0000000000..f86d3463ba
--- /dev/null
+++ b/flow/designs/nangate45/picorv32/constraint.sdc
@@ -0,0 +1,10 @@
+set_units -time ns -capacitance fF -resistance kOhm -voltage V -current mA -power nW
+current_design picorv32
+
+set clk_period 0.9
+set io_delay [expr 0.20 * $clk_period]
+create_clock -name core_clock -period $clk_period [get_ports clk]
+create_clock -name vclk_core -period $clk_period
+set_max_fanout 16 [current_design]
+set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks]
+set_output_delay $io_delay -clock vclk_core [all_outputs]
diff --git a/flow/designs/nangate45/picorv32/rules-base.json b/flow/designs/nangate45/picorv32/rules-base.json
new file mode 100644
index 0000000000..900218b443
--- /dev/null
+++ b/flow/designs/nangate45/picorv32/rules-base.json
@@ -0,0 +1,112 @@
+{
+    "synth__canonical_netlist__hash": {
+        "value": "ce44c7d6fdabc48b0b0e48dc5b36466e29468972",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__netlist__hash": {
+        "value": "447814994a423936e4234218bf85334f3e7137fc",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__design__instance__area__stdcell": {
+        "value": 34100.0,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 2,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 35016,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 18533,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 1612,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 1612,
+        "compare": "<="
+    },
+    "cts__timing__setup__ws": {
+        "value": -0.784,
+        "compare": ">="
+    },
+    "cts__timing__setup__tns": {
+        "value": -34.5,
+        "compare": ">="
+    },
+    "cts__timing__hold__ws": {
+        "value": -0.045,
+        "compare": ">="
+    },
+    "cts__timing__hold__tns": {
+        "value": -0.18,
+        "compare": ">="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "globalroute__timing__setup__ws": {
+        "value": -0.791,
+        "compare": ">="
+    },
+    "globalroute__timing__setup__tns": {
+        "value": -35.5,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__ws": {
+        "value": -0.045,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__tns": {
+        "value": -0.18,
+        "compare": ">="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 310653,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -0.776,
+        "compare": ">="
+    },
+    "finish__timing__setup__tns": {
+        "value": -34.6,
+        "compare": ">="
+    },
+    "finish__timing__hold__ws": {
+        "value": -0.045,
+        "compare": ">="
+    },
+    "finish__timing__hold__tns": {
+        "value": -0.18,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 36101,
+        "compare": "<="
+    }
+}
diff --git a/flow/designs/nangate45/tpu/config.mk b/flow/designs/nangate45/tpu/config.mk
new file mode 100644
index 0000000000..fbed3b98b9
--- /dev/null
+++ b/flow/designs/nangate45/tpu/config.mk
@@ -0,0 +1,17 @@
+export PLATFORM = nangate45
+export DESIGN_NAME = tpu
+
+export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/tpu/*.sv))
+export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+# Synthesis
+export ABC_CLOCK_PERIOD_IN_PS = 1000
+export SYNTH_HDL_FRONTEND = slang
+export LEC_CHECK = 0
+
+# Floorplan
+export CORE_UTILIZATION = 60
+export CORE_ASPECT_RATIO = 1
+export CORE_MARGIN = 2
+
+export TNS_END_PERCENT = 100
diff --git a/flow/designs/nangate45/tpu/constraint.sdc b/flow/designs/nangate45/tpu/constraint.sdc
new file mode 100644
index 0000000000..0383176ded
--- /dev/null
+++ b/flow/designs/nangate45/tpu/constraint.sdc
@@ -0,0 +1,10 @@
+set_units -time ns -capacitance fF -resistance kOhm -voltage V -current mA -power nW
+current_design tpu
+
+set clk_period 1.0
+set io_delay [expr 0.20 * $clk_period]
+create_clock -name core_clock -period $clk_period [get_ports clk]
+create_clock -name vclk_core -period $clk_period
+set_max_fanout 16 [current_design]
+set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks]
+set_output_delay $io_delay -clock vclk_core [all_outputs]
diff --git a/flow/designs/nangate45/tpu/rules-base.json b/flow/designs/nangate45/tpu/rules-base.json
new file mode 100644
index 0000000000..034d3f18cc
--- /dev/null
+++ b/flow/designs/nangate45/tpu/rules-base.json
@@ -0,0 +1,112 @@
+{
+    "synth__canonical_netlist__hash": {
+        "value": "e2c3bdd070c83cd5e711c7c98ae0b21a88983835",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__netlist__hash": {
+        "value": "cebf5d2af70e9cb34cf758972ab48da7d29fec46",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__design__instance__area__stdcell": {
+        "value": 83600.0,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 2,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 84841,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 47778,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 4155,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 4155,
+        "compare": "<="
+    },
+    "cts__timing__setup__ws": {
+        "value": -0.0772,
+        "compare": ">="
+    },
+    "cts__timing__setup__tns": {
+        "value": -0.305,
+        "compare": ">="
+    },
+    "cts__timing__hold__ws": {
+        "value": -0.0716,
+        "compare": ">="
+    },
+    "cts__timing__hold__tns": {
+        "value": -0.286,
+        "compare": ">="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "globalroute__timing__setup__ws": {
+        "value": -0.0958,
+        "compare": ">="
+    },
+    "globalroute__timing__setup__tns": {
+        "value": -0.694,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__ws": {
+        "value": -0.0716,
+        "compare": ">="
+    },
+    "globalroute__timing__hold__tns": {
+        "value": -0.286,
+        "compare": ">="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 489354,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -0.0732,
+        "compare": ">="
+    },
+    "finish__timing__setup__tns": {
+        "value": -0.288,
+        "compare": ">="
+    },
+    "finish__timing__hold__ws": {
+        "value": -0.0716,
+        "compare": ">="
+    },
+    "finish__timing__hold__tns": {
+        "value": -0.286,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 87096,
+        "compare": "<="
+    }
+}
diff --git a/flow/designs/nangate45/xiangshan_coupledl2/config.mk b/flow/designs/nangate45/xiangshan_coupledl2/config.mk
new file mode 100644
index 0000000000..0348632392
--- /dev/null
+++ b/flow/designs/nangate45/xiangshan_coupledl2/config.mk
@@ -0,0 +1,68 @@
+export PLATFORM = nangate45
+export DESIGN_NAME = CoupledL2
+export DESIGN_NICKNAME = xiangshan_coupledl2
+
+export VERILOG_FILES = $(sort \
+  $(wildcard $(DESIGN_HOME)/src/xiangshan_coupledl2/*.sv) \
+  $(wildcard $(DESIGN_HOME)/src/xiangshan_coupledl2/deps/*.sv)) \
+  $(PLATFORM_DIR)/verilog/array_2048x137_bk_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x104_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x13_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x164_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x16_bb.sv \
+  $(PLATFORM_DIR)/verilog/array_256x8_0_bb.sv
+export VERILOG_DEFINES += -D SYNTHESIS
+export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+# Fakeram macros for the SRAM arrays; fakeram.cfg in this directory records how
+# the platform views were generated.
+export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/array_2048x137_bk.lef \
+                         $(PLATFORM_DIR)/lef/array_256x104.lef \
+                         $(PLATFORM_DIR)/lef/array_256x13.lef \
+                         $(PLATFORM_DIR)/lef/array_256x164.lef \
+                         $(PLATFORM_DIR)/lef/array_256x16.lef \
+                         $(PLATFORM_DIR)/lef/array_256x8_0.lef
+export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/array_2048x137_bk.lib \
+                         $(PLATFORM_DIR)/lib/array_256x104.lib \
+                         $(PLATFORM_DIR)/lib/array_256x13.lib \
+                         $(PLATFORM_DIR)/lib/array_256x164.lib \
+                         $(PLATFORM_DIR)/lib/array_256x16.lib \
+                         $(PLATFORM_DIR)/lib/array_256x8_0.lib
+export GDS_ALLOW_EMPTY = (fakeram.*|DFFHQN[VH][24].*|array_.*)
+
+# Synthesis
+export ABC_CLOCK_PERIOD_IN_PS = 3800
+export SYNTH_HIERARCHICAL = 1
+export SYNTH_MINIMUM_KEEP_SIZE ?= 10000
+export SYNTH_RETIME_MODULES = $(DESIGN_NAME)
+export SYNTH_HDL_FRONTEND = slang
+export LEC_CHECK = 0
+
+# Floorplan
+export CORE_UTILIZATION = 70
+export CORE_ASPECT_RATIO = 1
+export CORE_MARGIN = 2
+export MACRO_PLACE_HALO = 10 10
+
+# Placement and timing repair
+export GPL_TIMING_DRIVEN = 0
+export GPL_ROUTABILITY_DRIVEN = 0
+export TNS_END_PERCENT = 5
+export SKIP_CTS_REPAIR_TIMING = 1
+export SKIP_INCREMENTAL_REPAIR = 1
+export ENABLE_RESISTANCE_AWARE = 0
+
+# Routing
+export GLOBAL_ROUTE_ARGS = -congestion_iterations 5 -congestion_report_iter_step 5 -verbose -allow_congestion
+# The nangate45 platform defaults OPT_POST_GRT_WNS to 0, which wraps recover_power in an
+# incremental global_route pair even with RECOVER_POWER=0. That reroute does not receive
+# -allow_congestion and fails with GRT-0116 on this congested design, so skip it. The
+# post-GRT WNS repair it would enable is already disabled by SKIP_INCREMENTAL_REPAIR.
+export OPT_POST_GRT_WNS = 1
+export DETAILED_ROUTE_END_ITERATION = 16
+export SKIP_ANTENNA_REPAIR = 1
+export SKIP_ANTENNA_REPAIR_POST_DRT = 1
+
+# PDNSim cannot connect short row-end filler stubs next to the macro halos.
+export PWR_NETS_VOLTAGES =
+export GND_NETS_VOLTAGES =
diff --git a/flow/designs/nangate45/xiangshan_coupledl2/constraint.sdc b/flow/designs/nangate45/xiangshan_coupledl2/constraint.sdc
new file mode 100644
index 0000000000..13f69f514c
--- /dev/null
+++ b/flow/designs/nangate45/xiangshan_coupledl2/constraint.sdc
@@ -0,0 +1,15 @@
+set_units -time ns -capacitance fF -resistance kOhm -voltage V -current mA -power nW
+current_design CoupledL2
+
+# The 3.8 ns target keeps the public CI runtime bounded while leaving setup
+# violations for optimization experiments; it is not a measured Fmax of this
+# 128 KiB MinimalConfig L2.
+set clk_period 3.8
+set io_delay [expr 0.20 * $clk_period]
+create_clock -name core_clock -period $clk_period [get_ports clock]
+create_clock -name vclk_core -period $clk_period
+set_max_fanout 16 [current_design]
+# Exclude the asynchronous reset from data-path timing optimization.
+set_false_path -from [get_ports reset]
+set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks]
+set_output_delay $io_delay -clock vclk_core [all_outputs]
diff --git a/flow/designs/nangate45/xiangshan_coupledl2/fakeram.cfg b/flow/designs/nangate45/xiangshan_coupledl2/fakeram.cfg
new file mode 100644
index 0000000000..d1067abd41
--- /dev/null
+++ b/flow/designs/nangate45/xiangshan_coupledl2/fakeram.cfg
@@ -0,0 +1,22 @@
+# Generated with VLSIDA/bsg_fakeram commit c83ecb47f5a90d2e92d589b4f63a2e38c25c1afd.
+# Generated rw0_* physical pins are renamed to the RTL's RW0_* interface.
+{
+  "tech_nm": 45,
+  "voltage": 1.1,
+  "metalPrefix": "metal",
+  "LRpinWidth_nm": 70,
+  "LRpinPitch_nm": 140,
+  "TBpinWidth_nm": 70,
+  "TBpinPitch_nm": 190,
+  "snapWidth_nm": 190,
+  "snapHeight_nm": 1400,
+  "flipPins": true,
+  "srams": [
+    {"name": "array_2048x137_bk", "width": 137, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x104", "width": 104, "depth": 256, "banks": 1, "no_wmask": "false", "write_granularity": 13, "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x13", "width": 13, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x164", "width": 164, "depth": 256, "banks": 1, "no_wmask": "false", "write_granularity": 41, "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x16", "width": 16, "depth": 256, "banks": 1, "no_wmask": "true", "ports": {"r": 0, "w": 0, "rw": 1}},
+    {"name": "array_256x8_0", "width": 8, "depth": 256, "banks": 1, "no_wmask": "false", "write_granularity": 1, "ports": {"r": 0, "w": 0, "rw": 1}}
+  ]
+}
diff --git a/flow/designs/nangate45/xiangshan_coupledl2/rules-base.json b/flow/designs/nangate45/xiangshan_coupledl2/rules-base.json
new file mode 100644
index 0000000000..2c598c10ce
--- /dev/null
+++ b/flow/designs/nangate45/xiangshan_coupledl2/rules-base.json
@@ -0,0 +1,60 @@
+{
+    "synth__canonical_netlist__hash": {
+        "value": "0151110e1e1994b2b76ba059cb16f1c3e159498b",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__netlist__hash": {
+        "value": "a7aed3fde7d1f078356e0518b13d1714438e7810",
+        "compare": "==",
+        "level": "warning"
+    },
+    "synth__design__instance__area__stdcell": {
+        "value": 863000.0,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 2,
+        "compare": "=="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 18294289,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 2,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 463,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -0.867,
+        "compare": ">="
+    },
+    "finish__timing__setup__tns": {
+        "value": -6.89,
+        "compare": ">="
+    },
+    "finish__timing__hold__ws": {
+        "value": -0.723,
+        "compare": ">="
+    },
+    "finish__timing__hold__tns": {
+        "value": -3700.0,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 2285004,
+        "compare": "<="
+    }
+}
diff --git a/flow/designs/src/picorv32/LICENSES/LogikBench-MIT.txt b/flow/designs/src/picorv32/LICENSES/LogikBench-MIT.txt
new file mode 100644
index 0000000000..238c66dc4b
--- /dev/null
+++ b/flow/designs/src/picorv32/LICENSES/LogikBench-MIT.txt
@@ -0,0 +1,21 @@
+The MIT License (MIT)
+
+Copyright (c) 2025 Zero ASIC Corporation
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/flow/designs/src/picorv32/LICENSES/PicoRV32-ISC.txt b/flow/designs/src/picorv32/LICENSES/PicoRV32-ISC.txt
new file mode 100644
index 0000000000..b660be29b7
--- /dev/null
+++ b/flow/designs/src/picorv32/LICENSES/PicoRV32-ISC.txt
@@ -0,0 +1,13 @@
+Copyright (C) 2015 Claire Xenia Wolf <claire@yosyshq.com>
+
+Permission to use, copy, modify, and/or distribute this software for any
+purpose with or without fee is hereby granted, provided that the above
+copyright notice and this permission notice appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
+REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
+AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
+INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
+LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
+OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+PERFORMANCE OF THIS SOFTWARE.
diff --git a/flow/designs/src/picorv32/SOURCE.md b/flow/designs/src/picorv32/SOURCE.md
new file mode 100644
index 0000000000..3ef3d68d9e
--- /dev/null
+++ b/flow/designs/src/picorv32/SOURCE.md
@@ -0,0 +1,16 @@
+# PicoRV32 source
+
+- Top: `picorv32`
+- Benchmark source: `zeroasiccorp/LogikBench`, commit
+  `62fc37ec58451c7d8813d7d3e3e1d7a1377c9082`
+- Upstream source: `YosysHQ/picorv32`, commit
+  `87c89acc18994c8cf9a2311e871818e87d304568`
+
+The packaged RTL is byte-identical to the LogikBench benchmark. LogikBench's
+intentional parameter-default changes relative to upstream are part of the
+benchmark definition. Only the file suffix was changed from `.v` to `.sv`;
+the contents are unchanged.
+
+`LICENSES/LogikBench-MIT.txt` records the immediate benchmark grant and
+`LICENSES/PicoRV32-ISC.txt` records the authored RTL grant preserved in the
+source header.
diff --git a/flow/designs/src/picorv32/picorv32.sv b/flow/designs/src/picorv32/picorv32.sv
new file mode 100644
index 0000000000..9d1c9bc7a1
--- /dev/null
+++ b/flow/designs/src/picorv32/picorv32.sv
@@ -0,0 +1,3049 @@
+/*
+ *  PicoRV32 -- A Small RISC-V (RV32I) Processor Core
+ *
+ *  Copyright (C) 2015  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+/* verilator lint_off WIDTH */
+/* verilator lint_off PINMISSING */
+/* verilator lint_off CASEOVERLAP */
+/* verilator lint_off CASEINCOMPLETE */
+
+`timescale 1 ns / 1 ps
+// `default_nettype none
+// `define DEBUGNETS
+// `define DEBUGREGS
+// `define DEBUGASM
+// `define DEBUG
+
+`ifdef DEBUG
+  `define debug(debug_command) debug_command
+`else
+  `define debug(debug_command)
+`endif
+
+`ifdef FORMAL
+  `define FORMAL_KEEP (* keep *)
+  `define assert(assert_expr) assert(assert_expr)
+`else
+  `ifdef DEBUGNETS
+    `define FORMAL_KEEP (* keep *)
+  `else
+    `define FORMAL_KEEP
+  `endif
+  `define assert(assert_expr) empty_statement
+`endif
+
+// uncomment this for register file in extra module
+// `define PICORV32_REGS picorv32_regs
+
+// this macro can be used to check if the verilog files in your
+// design are read in the correct order.
+`define PICORV32_V
+
+
+/***************************************************************
+ * picorv32
+ ***************************************************************/
+
+module picorv32 #(
+	parameter [ 0:0] ENABLE_COUNTERS = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 0,
+	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+	parameter [ 0:0] ENABLE_REGS_DUALPORT = 0,
+	parameter [ 0:0] LATCHED_MEM_RDATA = 1,
+	parameter [ 0:0] TWO_STAGE_SHIFT = 0,
+	parameter [ 0:0] BARREL_SHIFTER = 1,
+	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 1,
+	parameter [ 0:0] CATCH_MISALIGN = 0,
+	parameter [ 0:0] CATCH_ILLINSN = 0,
+	parameter [ 0:0] ENABLE_PCPI = 1,
+	parameter [ 0:0] ENABLE_MUL = 1,
+	parameter [ 0:0] ENABLE_FAST_MUL = 1,
+	parameter [ 0:0] ENABLE_DIV = 1,
+	parameter [ 0:0] ENABLE_IRQ = 1,
+	parameter [ 0:0] ENABLE_IRQ_QREGS = 0,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 0,
+	parameter [ 0:0] ENABLE_TRACE = 0,
+	parameter [ 0:0] REGS_INIT_ZERO = 0,
+	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+	input clk, resetn,
+	output reg trap,
+
+	output reg        mem_valid,
+	output reg        mem_instr,
+	input             mem_ready,
+
+	output reg [31:0] mem_addr,
+	output reg [31:0] mem_wdata,
+	output reg [ 3:0] mem_wstrb,
+	input      [31:0] mem_rdata,
+
+	// Look-Ahead Interface
+	output            mem_la_read,
+	output            mem_la_write,
+	output     [31:0] mem_la_addr,
+	output reg [31:0] mem_la_wdata,
+	output reg [ 3:0] mem_la_wstrb,
+
+	// Pico Co-Processor Interface (PCPI)
+	output reg        pcpi_valid,
+	output reg [31:0] pcpi_insn,
+	output     [31:0] pcpi_rs1,
+	output     [31:0] pcpi_rs2,
+	input             pcpi_wr,
+	input      [31:0] pcpi_rd,
+	input             pcpi_wait,
+	input             pcpi_ready,
+
+	// IRQ Interface
+	input      [31:0] irq,
+	output reg [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+	output reg        rvfi_valid,
+	output reg [63:0] rvfi_order,
+	output reg [31:0] rvfi_insn,
+	output reg        rvfi_trap,
+	output reg        rvfi_halt,
+	output reg        rvfi_intr,
+	output reg [ 1:0] rvfi_mode,
+	output reg [ 1:0] rvfi_ixl,
+	output reg [ 4:0] rvfi_rs1_addr,
+	output reg [ 4:0] rvfi_rs2_addr,
+	output reg [31:0] rvfi_rs1_rdata,
+	output reg [31:0] rvfi_rs2_rdata,
+	output reg [ 4:0] rvfi_rd_addr,
+	output reg [31:0] rvfi_rd_wdata,
+	output reg [31:0] rvfi_pc_rdata,
+	output reg [31:0] rvfi_pc_wdata,
+	output reg [31:0] rvfi_mem_addr,
+	output reg [ 3:0] rvfi_mem_rmask,
+	output reg [ 3:0] rvfi_mem_wmask,
+	output reg [31:0] rvfi_mem_rdata,
+	output reg [31:0] rvfi_mem_wdata,
+
+	output reg [63:0] rvfi_csr_mcycle_rmask,
+	output reg [63:0] rvfi_csr_mcycle_wmask,
+	output reg [63:0] rvfi_csr_mcycle_rdata,
+	output reg [63:0] rvfi_csr_mcycle_wdata,
+
+	output reg [63:0] rvfi_csr_minstret_rmask,
+	output reg [63:0] rvfi_csr_minstret_wmask,
+	output reg [63:0] rvfi_csr_minstret_rdata,
+	output reg [63:0] rvfi_csr_minstret_wdata,
+`endif
+
+	// Trace Interface
+	output reg        trace_valid,
+	output reg [35:0] trace_data
+);
+	localparam integer irq_timer = 0;
+	localparam integer irq_ebreak = 1;
+	localparam integer irq_buserror = 2;
+
+	localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16;
+	localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS;
+	localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS;
+
+	localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV;
+
+	localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0};
+	localparam [35:0] TRACE_ADDR   = {4'b 0010, 32'b 0};
+	localparam [35:0] TRACE_IRQ    = {4'b 1000, 32'b 0};
+
+	reg [63:0] count_cycle, count_instr;
+	reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out;
+	reg [4:0] reg_sh;
+
+	reg [31:0] next_insn_opcode;
+	reg [31:0] dbg_insn_opcode;
+	reg [31:0] dbg_insn_addr;
+
+	wire dbg_mem_valid = mem_valid;
+	wire dbg_mem_instr = mem_instr;
+	wire dbg_mem_ready = mem_ready;
+	wire [31:0] dbg_mem_addr  = mem_addr;
+	wire [31:0] dbg_mem_wdata = mem_wdata;
+	wire [ 3:0] dbg_mem_wstrb = mem_wstrb;
+	wire [31:0] dbg_mem_rdata = mem_rdata;
+
+	assign pcpi_rs1 = reg_op1;
+	assign pcpi_rs2 = reg_op2;
+
+	wire [31:0] next_pc;
+
+	reg irq_delay;
+	reg irq_active;
+	reg [31:0] irq_mask;
+	reg [31:0] irq_pending;
+	reg [31:0] timer;
+
+`ifndef PICORV32_REGS
+	reg [31:0] cpuregs [0:regfile_size-1];
+
+	integer i;
+	initial begin
+		if (REGS_INIT_ZERO) begin
+			for (i = 0; i < regfile_size; i = i+1)
+				cpuregs[i] = 0;
+		end
+	end
+`endif
+
+	task empty_statement;
+		// This task is used by the `assert directive in non-formal mode to
+		// avoid empty statement (which are unsupported by plain Verilog syntax).
+		begin end
+	endtask
+
+`ifdef DEBUGREGS
+	wire [31:0] dbg_reg_x0  = 0;
+	wire [31:0] dbg_reg_x1  = cpuregs[1];
+	wire [31:0] dbg_reg_x2  = cpuregs[2];
+	wire [31:0] dbg_reg_x3  = cpuregs[3];
+	wire [31:0] dbg_reg_x4  = cpuregs[4];
+	wire [31:0] dbg_reg_x5  = cpuregs[5];
+	wire [31:0] dbg_reg_x6  = cpuregs[6];
+	wire [31:0] dbg_reg_x7  = cpuregs[7];
+	wire [31:0] dbg_reg_x8  = cpuregs[8];
+	wire [31:0] dbg_reg_x9  = cpuregs[9];
+	wire [31:0] dbg_reg_x10 = cpuregs[10];
+	wire [31:0] dbg_reg_x11 = cpuregs[11];
+	wire [31:0] dbg_reg_x12 = cpuregs[12];
+	wire [31:0] dbg_reg_x13 = cpuregs[13];
+	wire [31:0] dbg_reg_x14 = cpuregs[14];
+	wire [31:0] dbg_reg_x15 = cpuregs[15];
+	wire [31:0] dbg_reg_x16 = cpuregs[16];
+	wire [31:0] dbg_reg_x17 = cpuregs[17];
+	wire [31:0] dbg_reg_x18 = cpuregs[18];
+	wire [31:0] dbg_reg_x19 = cpuregs[19];
+	wire [31:0] dbg_reg_x20 = cpuregs[20];
+	wire [31:0] dbg_reg_x21 = cpuregs[21];
+	wire [31:0] dbg_reg_x22 = cpuregs[22];
+	wire [31:0] dbg_reg_x23 = cpuregs[23];
+	wire [31:0] dbg_reg_x24 = cpuregs[24];
+	wire [31:0] dbg_reg_x25 = cpuregs[25];
+	wire [31:0] dbg_reg_x26 = cpuregs[26];
+	wire [31:0] dbg_reg_x27 = cpuregs[27];
+	wire [31:0] dbg_reg_x28 = cpuregs[28];
+	wire [31:0] dbg_reg_x29 = cpuregs[29];
+	wire [31:0] dbg_reg_x30 = cpuregs[30];
+	wire [31:0] dbg_reg_x31 = cpuregs[31];
+`endif
+
+	// Internal PCPI Cores
+
+	wire        pcpi_mul_wr;
+	wire [31:0] pcpi_mul_rd;
+	wire        pcpi_mul_wait;
+	wire        pcpi_mul_ready;
+
+	wire        pcpi_div_wr;
+	wire [31:0] pcpi_div_rd;
+	wire        pcpi_div_wait;
+	wire        pcpi_div_ready;
+
+	reg        pcpi_int_wr;
+	reg [31:0] pcpi_int_rd;
+	reg        pcpi_int_wait;
+	reg        pcpi_int_ready;
+
+	generate if (ENABLE_FAST_MUL) begin
+		picorv32_pcpi_fast_mul pcpi_mul (
+			.clk       (clk            ),
+			.resetn    (resetn         ),
+			.pcpi_valid(pcpi_valid     ),
+			.pcpi_insn (pcpi_insn      ),
+			.pcpi_rs1  (pcpi_rs1       ),
+			.pcpi_rs2  (pcpi_rs2       ),
+			.pcpi_wr   (pcpi_mul_wr    ),
+			.pcpi_rd   (pcpi_mul_rd    ),
+			.pcpi_wait (pcpi_mul_wait  ),
+			.pcpi_ready(pcpi_mul_ready )
+		);
+	end else if (ENABLE_MUL) begin
+		picorv32_pcpi_mul pcpi_mul (
+			.clk       (clk            ),
+			.resetn    (resetn         ),
+			.pcpi_valid(pcpi_valid     ),
+			.pcpi_insn (pcpi_insn      ),
+			.pcpi_rs1  (pcpi_rs1       ),
+			.pcpi_rs2  (pcpi_rs2       ),
+			.pcpi_wr   (pcpi_mul_wr    ),
+			.pcpi_rd   (pcpi_mul_rd    ),
+			.pcpi_wait (pcpi_mul_wait  ),
+			.pcpi_ready(pcpi_mul_ready )
+		);
+	end else begin
+		assign pcpi_mul_wr = 0;
+		assign pcpi_mul_rd = 32'bx;
+		assign pcpi_mul_wait = 0;
+		assign pcpi_mul_ready = 0;
+	end endgenerate
+
+	generate if (ENABLE_DIV) begin
+		picorv32_pcpi_div pcpi_div (
+			.clk       (clk            ),
+			.resetn    (resetn         ),
+			.pcpi_valid(pcpi_valid     ),
+			.pcpi_insn (pcpi_insn      ),
+			.pcpi_rs1  (pcpi_rs1       ),
+			.pcpi_rs2  (pcpi_rs2       ),
+			.pcpi_wr   (pcpi_div_wr    ),
+			.pcpi_rd   (pcpi_div_rd    ),
+			.pcpi_wait (pcpi_div_wait  ),
+			.pcpi_ready(pcpi_div_ready )
+		);
+	end else begin
+		assign pcpi_div_wr = 0;
+		assign pcpi_div_rd = 32'bx;
+		assign pcpi_div_wait = 0;
+		assign pcpi_div_ready = 0;
+	end endgenerate
+
+	always @* begin
+		pcpi_int_wr = 0;
+		pcpi_int_rd = 32'bx;
+		pcpi_int_wait  = |{ENABLE_PCPI && pcpi_wait,  (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait,  ENABLE_DIV && pcpi_div_wait};
+		pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready};
+
+		(* parallel_case *)
+		case (1'b1)
+			ENABLE_PCPI && pcpi_ready: begin
+				pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0;
+				pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0;
+			end
+			(ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin
+				pcpi_int_wr = pcpi_mul_wr;
+				pcpi_int_rd = pcpi_mul_rd;
+			end
+			ENABLE_DIV && pcpi_div_ready: begin
+				pcpi_int_wr = pcpi_div_wr;
+				pcpi_int_rd = pcpi_div_rd;
+			end
+		endcase
+	end
+
+
+	// Memory Interface
+
+	reg [1:0] mem_state;
+	reg [1:0] mem_wordsize;
+	reg [31:0] mem_rdata_word;
+	reg [31:0] mem_rdata_q;
+	reg mem_do_prefetch;
+	reg mem_do_rinst;
+	reg mem_do_rdata;
+	reg mem_do_wdata;
+
+	wire mem_xfer;
+	reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid;
+	wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword;
+	wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg);
+
+	reg prefetched_high_word;
+	reg clear_prefetched_high_word;
+	reg [15:0] mem_16bit_buffer;
+
+	wire [31:0] mem_rdata_latched_noshuffle;
+	wire [31:0] mem_rdata_latched;
+
+	wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word;
+	assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst);
+
+	wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata};
+	wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) &&
+			(!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer));
+
+	assign mem_la_write = resetn && !mem_state && mem_do_wdata;
+	assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) ||
+			(COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0]));
+	assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00};
+
+	assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q;
+
+	assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} :
+			COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} :
+			COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle;
+
+	always @(posedge clk) begin
+		if (!resetn) begin
+			mem_la_firstword_reg <= 0;
+			last_mem_valid <= 0;
+		end else begin
+			if (!last_mem_valid)
+				mem_la_firstword_reg <= mem_la_firstword;
+			last_mem_valid <= mem_valid && !mem_ready;
+		end
+	end
+
+	always @* begin
+		(* full_case *)
+		case (mem_wordsize)
+			0: begin
+				mem_la_wdata = reg_op2;
+				mem_la_wstrb = 4'b1111;
+				mem_rdata_word = mem_rdata;
+			end
+			1: begin
+				mem_la_wdata = {2{reg_op2[15:0]}};
+				mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011;
+				case (reg_op1[1])
+					1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]};
+					1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]};
+				endcase
+			end
+			2: begin
+				mem_la_wdata = {4{reg_op2[7:0]}};
+				mem_la_wstrb = 4'b0001 << reg_op1[1:0];
+				case (reg_op1[1:0])
+					2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]};
+					2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]};
+					2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]};
+					2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]};
+				endcase
+			end
+		endcase
+	end
+
+	always @(posedge clk) begin
+		if (mem_xfer) begin
+			mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+			next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata;
+		end
+
+		if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin
+			case (mem_rdata_latched[1:0])
+				2'b00: begin // Quadrant 0
+					case (mem_rdata_latched[15:13])
+						3'b000: begin // C.ADDI4SPN
+							mem_rdata_q[14:12] <= 3'b000;
+							mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00};
+						end
+						3'b010: begin // C.LW
+							mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+						3'b 110: begin // C.SW
+							{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+					endcase
+				end
+				2'b01: begin // Quadrant 1
+					case (mem_rdata_latched[15:13])
+						3'b 000: begin // C.ADDI
+							mem_rdata_q[14:12] <= 3'b000;
+							mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+						end
+						3'b 010: begin // C.LI
+							mem_rdata_q[14:12] <= 3'b000;
+							mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+						end
+						3'b 011: begin
+							if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3],
+										mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000});
+							end else begin // C.LUI
+								mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+							end
+						end
+						3'b100: begin
+							if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI
+								mem_rdata_q[31:25] <= 7'b0000000;
+								mem_rdata_q[14:12] <= 3'b 101;
+							end
+							if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI
+								mem_rdata_q[31:25] <= 7'b0100000;
+								mem_rdata_q[14:12] <= 3'b 101;
+							end
+							if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+								mem_rdata_q[14:12] <= 3'b111;
+								mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]});
+							end
+							if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+								if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000;
+								if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100;
+								if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110;
+								if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111;
+								mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000;
+							end
+						end
+						3'b 110: begin // C.BEQZ
+							mem_rdata_q[14:12] <= 3'b000;
+							{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+									$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+											mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+						end
+						3'b 111: begin // C.BNEZ
+							mem_rdata_q[14:12] <= 3'b001;
+							{ mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <=
+									$signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2],
+											mem_rdata_latched[11:10], mem_rdata_latched[4:3]});
+						end
+					endcase
+				end
+				2'b10: begin // Quadrant 2
+					case (mem_rdata_latched[15:13])
+						3'b000: begin // C.SLLI
+							mem_rdata_q[31:25] <= 7'b0000000;
+							mem_rdata_q[14:12] <= 3'b 001;
+						end
+						3'b010: begin // C.LWSP
+							mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+						3'b100: begin
+							if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:20] <= 12'b0;
+							end
+							if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:25] <= 7'b0000000;
+							end
+							if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:20] <= 12'b0;
+							end
+							if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+								mem_rdata_q[14:12] <= 3'b000;
+								mem_rdata_q[31:25] <= 7'b0000000;
+							end
+						end
+						3'b110: begin // C.SWSP
+							{mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00};
+							mem_rdata_q[14:12] <= 3'b 010;
+						end
+					endcase
+				end
+			endcase
+		end
+	end
+
+	always @(posedge clk) begin
+		if (resetn && !trap) begin
+			if (mem_do_prefetch || mem_do_rinst || mem_do_rdata)
+				`assert(!mem_do_wdata);
+
+			if (mem_do_prefetch || mem_do_rinst)
+				`assert(!mem_do_rdata);
+
+			if (mem_do_rdata)
+				`assert(!mem_do_prefetch && !mem_do_rinst);
+
+			if (mem_do_wdata)
+				`assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata));
+
+			if (mem_state == 2 || mem_state == 3)
+				`assert(mem_valid || mem_do_prefetch);
+		end
+	end
+
+	always @(posedge clk) begin
+		if (!resetn || trap) begin
+			if (!resetn)
+				mem_state <= 0;
+			if (!resetn || mem_ready)
+				mem_valid <= 0;
+			mem_la_secondword <= 0;
+			prefetched_high_word <= 0;
+		end else begin
+			if (mem_la_read || mem_la_write) begin
+				mem_addr <= mem_la_addr;
+				mem_wstrb <= mem_la_wstrb & {4{mem_la_write}};
+			end
+			if (mem_la_write) begin
+				mem_wdata <= mem_la_wdata;
+			end
+			case (mem_state)
+				0: begin
+					if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin
+						mem_valid <= !mem_la_use_prefetched_high_word;
+						mem_instr <= mem_do_prefetch || mem_do_rinst;
+						mem_wstrb <= 0;
+						mem_state <= 1;
+					end
+					if (mem_do_wdata) begin
+						mem_valid <= 1;
+						mem_instr <= 0;
+						mem_state <= 2;
+					end
+				end
+				1: begin
+					`assert(mem_wstrb == 0);
+					`assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata);
+					`assert(mem_valid == !mem_la_use_prefetched_high_word);
+					`assert(mem_instr == (mem_do_prefetch || mem_do_rinst));
+					if (mem_xfer) begin
+						if (COMPRESSED_ISA && mem_la_read) begin
+							mem_valid <= 1;
+							mem_la_secondword <= 1;
+							if (!mem_la_use_prefetched_high_word)
+								mem_16bit_buffer <= mem_rdata[31:16];
+						end else begin
+							mem_valid <= 0;
+							mem_la_secondword <= 0;
+							if (COMPRESSED_ISA && !mem_do_rdata) begin
+								if (~&mem_rdata[1:0] || mem_la_secondword) begin
+									mem_16bit_buffer <= mem_rdata[31:16];
+									prefetched_high_word <= 1;
+								end else begin
+									prefetched_high_word <= 0;
+								end
+							end
+							mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3;
+						end
+					end
+				end
+				2: begin
+					`assert(mem_wstrb != 0);
+					`assert(mem_do_wdata);
+					if (mem_xfer) begin
+						mem_valid <= 0;
+						mem_state <= 0;
+					end
+				end
+				3: begin
+					`assert(mem_wstrb == 0);
+					`assert(mem_do_prefetch);
+					if (mem_do_rinst) begin
+						mem_state <= 0;
+					end
+				end
+			endcase
+		end
+
+		if (clear_prefetched_high_word)
+			prefetched_high_word <= 0;
+	end
+
+
+	// Instruction Decoder
+
+	reg instr_lui, instr_auipc, instr_jal, instr_jalr;
+	reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu;
+	reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw;
+	reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai;
+	reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and;
+	reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak, instr_fence;
+	reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer;
+	wire instr_trap;
+
+	reg [regindex_bits-1:0] decoded_rd, decoded_rs1;
+	reg [4:0] decoded_rs2;
+	reg [31:0] decoded_imm, decoded_imm_j;
+	reg decoder_trigger;
+	reg decoder_trigger_q;
+	reg decoder_pseudo_trigger;
+	reg decoder_pseudo_trigger_q;
+	reg compressed_instr;
+
+	reg is_lui_auipc_jal;
+	reg is_lb_lh_lw_lbu_lhu;
+	reg is_slli_srli_srai;
+	reg is_jalr_addi_slti_sltiu_xori_ori_andi;
+	reg is_sb_sh_sw;
+	reg is_sll_srl_sra;
+	reg is_lui_auipc_jal_jalr_addi_add_sub;
+	reg is_slti_blt_slt;
+	reg is_sltiu_bltu_sltu;
+	reg is_beq_bne_blt_bge_bltu_bgeu;
+	reg is_lbu_lhu_lw;
+	reg is_alu_reg_imm;
+	reg is_alu_reg_reg;
+	reg is_compare;
+
+	assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr,
+			instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu,
+			instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw,
+			instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai,
+			instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and,
+			instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_fence,
+			instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer};
+
+	wire is_rdcycle_rdcycleh_rdinstr_rdinstrh;
+	assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh};
+
+	reg [63:0] new_ascii_instr;
+	`FORMAL_KEEP reg [63:0] dbg_ascii_instr;
+	`FORMAL_KEEP reg [31:0] dbg_insn_imm;
+	`FORMAL_KEEP reg [4:0] dbg_insn_rs1;
+	`FORMAL_KEEP reg [4:0] dbg_insn_rs2;
+	`FORMAL_KEEP reg [4:0] dbg_insn_rd;
+	`FORMAL_KEEP reg [31:0] dbg_rs1val;
+	`FORMAL_KEEP reg [31:0] dbg_rs2val;
+	`FORMAL_KEEP reg dbg_rs1val_valid;
+	`FORMAL_KEEP reg dbg_rs2val_valid;
+
+	always @* begin
+		new_ascii_instr = "";
+
+		if (instr_lui)      new_ascii_instr = "lui";
+		if (instr_auipc)    new_ascii_instr = "auipc";
+		if (instr_jal)      new_ascii_instr = "jal";
+		if (instr_jalr)     new_ascii_instr = "jalr";
+
+		if (instr_beq)      new_ascii_instr = "beq";
+		if (instr_bne)      new_ascii_instr = "bne";
+		if (instr_blt)      new_ascii_instr = "blt";
+		if (instr_bge)      new_ascii_instr = "bge";
+		if (instr_bltu)     new_ascii_instr = "bltu";
+		if (instr_bgeu)     new_ascii_instr = "bgeu";
+
+		if (instr_lb)       new_ascii_instr = "lb";
+		if (instr_lh)       new_ascii_instr = "lh";
+		if (instr_lw)       new_ascii_instr = "lw";
+		if (instr_lbu)      new_ascii_instr = "lbu";
+		if (instr_lhu)      new_ascii_instr = "lhu";
+		if (instr_sb)       new_ascii_instr = "sb";
+		if (instr_sh)       new_ascii_instr = "sh";
+		if (instr_sw)       new_ascii_instr = "sw";
+
+		if (instr_addi)     new_ascii_instr = "addi";
+		if (instr_slti)     new_ascii_instr = "slti";
+		if (instr_sltiu)    new_ascii_instr = "sltiu";
+		if (instr_xori)     new_ascii_instr = "xori";
+		if (instr_ori)      new_ascii_instr = "ori";
+		if (instr_andi)     new_ascii_instr = "andi";
+		if (instr_slli)     new_ascii_instr = "slli";
+		if (instr_srli)     new_ascii_instr = "srli";
+		if (instr_srai)     new_ascii_instr = "srai";
+
+		if (instr_add)      new_ascii_instr = "add";
+		if (instr_sub)      new_ascii_instr = "sub";
+		if (instr_sll)      new_ascii_instr = "sll";
+		if (instr_slt)      new_ascii_instr = "slt";
+		if (instr_sltu)     new_ascii_instr = "sltu";
+		if (instr_xor)      new_ascii_instr = "xor";
+		if (instr_srl)      new_ascii_instr = "srl";
+		if (instr_sra)      new_ascii_instr = "sra";
+		if (instr_or)       new_ascii_instr = "or";
+		if (instr_and)      new_ascii_instr = "and";
+
+		if (instr_rdcycle)  new_ascii_instr = "rdcycle";
+		if (instr_rdcycleh) new_ascii_instr = "rdcycleh";
+		if (instr_rdinstr)  new_ascii_instr = "rdinstr";
+		if (instr_rdinstrh) new_ascii_instr = "rdinstrh";
+		if (instr_fence)    new_ascii_instr = "fence";
+
+		if (instr_getq)     new_ascii_instr = "getq";
+		if (instr_setq)     new_ascii_instr = "setq";
+		if (instr_retirq)   new_ascii_instr = "retirq";
+		if (instr_maskirq)  new_ascii_instr = "maskirq";
+		if (instr_waitirq)  new_ascii_instr = "waitirq";
+		if (instr_timer)    new_ascii_instr = "timer";
+	end
+
+	reg [63:0] q_ascii_instr;
+	reg [31:0] q_insn_imm;
+	reg [31:0] q_insn_opcode;
+	reg [4:0] q_insn_rs1;
+	reg [4:0] q_insn_rs2;
+	reg [4:0] q_insn_rd;
+	reg dbg_next;
+
+	wire launch_next_insn;
+	reg dbg_valid_insn;
+
+	reg [63:0] cached_ascii_instr;
+	reg [31:0] cached_insn_imm;
+	reg [31:0] cached_insn_opcode;
+	reg [4:0] cached_insn_rs1;
+	reg [4:0] cached_insn_rs2;
+	reg [4:0] cached_insn_rd;
+
+	always @(posedge clk) begin
+		q_ascii_instr <= dbg_ascii_instr;
+		q_insn_imm <= dbg_insn_imm;
+		q_insn_opcode <= dbg_insn_opcode;
+		q_insn_rs1 <= dbg_insn_rs1;
+		q_insn_rs2 <= dbg_insn_rs2;
+		q_insn_rd <= dbg_insn_rd;
+		dbg_next <= launch_next_insn;
+
+		if (!resetn || trap)
+			dbg_valid_insn <= 0;
+		else if (launch_next_insn)
+			dbg_valid_insn <= 1;
+
+		if (decoder_trigger_q) begin
+			cached_ascii_instr <= new_ascii_instr;
+			cached_insn_imm <= decoded_imm;
+			if (&next_insn_opcode[1:0])
+				cached_insn_opcode <= next_insn_opcode;
+			else
+				cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]};
+			cached_insn_rs1 <= decoded_rs1;
+			cached_insn_rs2 <= decoded_rs2;
+			cached_insn_rd <= decoded_rd;
+		end
+
+		if (launch_next_insn) begin
+			dbg_insn_addr <= next_pc;
+		end
+	end
+
+	always @* begin
+		dbg_ascii_instr = q_ascii_instr;
+		dbg_insn_imm = q_insn_imm;
+		dbg_insn_opcode = q_insn_opcode;
+		dbg_insn_rs1 = q_insn_rs1;
+		dbg_insn_rs2 = q_insn_rs2;
+		dbg_insn_rd = q_insn_rd;
+
+		if (dbg_next) begin
+			if (decoder_pseudo_trigger_q) begin
+				dbg_ascii_instr = cached_ascii_instr;
+				dbg_insn_imm = cached_insn_imm;
+				dbg_insn_opcode = cached_insn_opcode;
+				dbg_insn_rs1 = cached_insn_rs1;
+				dbg_insn_rs2 = cached_insn_rs2;
+				dbg_insn_rd = cached_insn_rd;
+			end else begin
+				dbg_ascii_instr = new_ascii_instr;
+				if (&next_insn_opcode[1:0])
+					dbg_insn_opcode = next_insn_opcode;
+				else
+					dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]};
+				dbg_insn_imm = decoded_imm;
+				dbg_insn_rs1 = decoded_rs1;
+				dbg_insn_rs2 = decoded_rs2;
+				dbg_insn_rd = decoded_rd;
+			end
+		end
+	end
+
+`ifdef DEBUGASM
+	always @(posedge clk) begin
+		if (dbg_next) begin
+			$display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*");
+		end
+	end
+`endif
+
+`ifdef DEBUG
+	always @(posedge clk) begin
+		if (dbg_next) begin
+			if (&dbg_insn_opcode[1:0])
+				$display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+			else
+				$display("DECODE: 0x%08x     0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN");
+		end
+	end
+`endif
+
+	always @(posedge clk) begin
+		is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal};
+		is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub};
+		is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt};
+		is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu};
+		is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw};
+		is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu};
+
+		if (mem_do_rinst && mem_done) begin
+			instr_lui     <= mem_rdata_latched[6:0] == 7'b0110111;
+			instr_auipc   <= mem_rdata_latched[6:0] == 7'b0010111;
+			instr_jal     <= mem_rdata_latched[6:0] == 7'b1101111;
+			instr_jalr    <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000;
+			instr_retirq  <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ;
+			instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ;
+
+			is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011;
+			is_lb_lh_lw_lbu_lhu          <= mem_rdata_latched[6:0] == 7'b0000011;
+			is_sb_sh_sw                  <= mem_rdata_latched[6:0] == 7'b0100011;
+			is_alu_reg_imm               <= mem_rdata_latched[6:0] == 7'b0010011;
+			is_alu_reg_reg               <= mem_rdata_latched[6:0] == 7'b0110011;
+
+			{ decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0});
+
+			decoded_rd <= mem_rdata_latched[11:7];
+			decoded_rs1 <= mem_rdata_latched[19:15];
+			decoded_rs2 <= mem_rdata_latched[24:20];
+
+			if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS)
+				decoded_rs1[regindex_bits-1] <= 1; // instr_getq
+
+			if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ)
+				decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq
+
+			compressed_instr <= 0;
+			if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin
+				compressed_instr <= 1;
+				decoded_rd <= 0;
+				decoded_rs1 <= 0;
+				decoded_rs2 <= 0;
+
+				{ decoded_imm_j[31:11], decoded_imm_j[4], decoded_imm_j[9:8], decoded_imm_j[10], decoded_imm_j[6],
+				  decoded_imm_j[7], decoded_imm_j[3:1], decoded_imm_j[5], decoded_imm_j[0] } <= $signed({mem_rdata_latched[12:2], 1'b0});
+
+				case (mem_rdata_latched[1:0])
+					2'b00: begin // Quadrant 0
+						case (mem_rdata_latched[15:13])
+							3'b000: begin // C.ADDI4SPN
+								is_alu_reg_imm <= |mem_rdata_latched[12:5];
+								decoded_rs1 <= 2;
+								decoded_rd <= 8 + mem_rdata_latched[4:2];
+							end
+							3'b010: begin // C.LW
+								is_lb_lh_lw_lbu_lhu <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rd <= 8 + mem_rdata_latched[4:2];
+							end
+							3'b110: begin // C.SW
+								is_sb_sh_sw <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+							end
+						endcase
+					end
+					2'b01: begin // Quadrant 1
+						case (mem_rdata_latched[15:13])
+							3'b000: begin // C.NOP / C.ADDI
+								is_alu_reg_imm <= 1;
+								decoded_rd <= mem_rdata_latched[11:7];
+								decoded_rs1 <= mem_rdata_latched[11:7];
+							end
+							3'b001: begin // C.JAL
+								instr_jal <= 1;
+								decoded_rd <= 1;
+							end
+							3'b 010: begin // C.LI
+								is_alu_reg_imm <= 1;
+								decoded_rd <= mem_rdata_latched[11:7];
+								decoded_rs1 <= 0;
+							end
+							3'b 011: begin
+								if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin
+									if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP
+										is_alu_reg_imm <= 1;
+										decoded_rd <= mem_rdata_latched[11:7];
+										decoded_rs1 <= mem_rdata_latched[11:7];
+									end else begin // C.LUI
+										instr_lui <= 1;
+										decoded_rd <= mem_rdata_latched[11:7];
+										decoded_rs1 <= 0;
+									end
+								end
+							end
+							3'b100: begin
+								if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI
+									is_alu_reg_imm <= 1;
+									decoded_rd <= 8 + mem_rdata_latched[9:7];
+									decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+									decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+								end
+								if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI
+									is_alu_reg_imm <= 1;
+									decoded_rd <= 8 + mem_rdata_latched[9:7];
+									decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								end
+								if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND
+									is_alu_reg_reg <= 1;
+									decoded_rd <= 8 + mem_rdata_latched[9:7];
+									decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+									decoded_rs2 <= 8 + mem_rdata_latched[4:2];
+								end
+							end
+							3'b101: begin // C.J
+								instr_jal <= 1;
+							end
+							3'b110: begin // C.BEQZ
+								is_beq_bne_blt_bge_bltu_bgeu <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rs2 <= 0;
+							end
+							3'b111: begin // C.BNEZ
+								is_beq_bne_blt_bge_bltu_bgeu <= 1;
+								decoded_rs1 <= 8 + mem_rdata_latched[9:7];
+								decoded_rs2 <= 0;
+							end
+						endcase
+					end
+					2'b10: begin // Quadrant 2
+						case (mem_rdata_latched[15:13])
+							3'b000: begin // C.SLLI
+								if (!mem_rdata_latched[12]) begin
+									is_alu_reg_imm <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= mem_rdata_latched[11:7];
+									decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]};
+								end
+							end
+							3'b010: begin // C.LWSP
+								if (mem_rdata_latched[11:7]) begin
+									is_lb_lh_lw_lbu_lhu <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= 2;
+								end
+							end
+							3'b100: begin
+								if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR
+									instr_jalr <= 1;
+									decoded_rd <= 0;
+									decoded_rs1 <= mem_rdata_latched[11:7];
+								end
+								if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV
+									is_alu_reg_reg <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= 0;
+									decoded_rs2 <= mem_rdata_latched[6:2];
+								end
+								if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR
+									instr_jalr <= 1;
+									decoded_rd <= 1;
+									decoded_rs1 <= mem_rdata_latched[11:7];
+								end
+								if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD
+									is_alu_reg_reg <= 1;
+									decoded_rd <= mem_rdata_latched[11:7];
+									decoded_rs1 <= mem_rdata_latched[11:7];
+									decoded_rs2 <= mem_rdata_latched[6:2];
+								end
+							end
+							3'b110: begin // C.SWSP
+								is_sb_sh_sw <= 1;
+								decoded_rs1 <= 2;
+								decoded_rs2 <= mem_rdata_latched[6:2];
+							end
+						endcase
+					end
+				endcase
+			end
+		end
+
+		if (decoder_trigger && !decoder_pseudo_trigger) begin
+			pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx;
+
+			instr_beq   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000;
+			instr_bne   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001;
+			instr_blt   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100;
+			instr_bge   <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101;
+			instr_bltu  <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110;
+			instr_bgeu  <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111;
+
+			instr_lb    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000;
+			instr_lh    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001;
+			instr_lw    <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010;
+			instr_lbu   <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100;
+			instr_lhu   <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101;
+
+			instr_sb    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000;
+			instr_sh    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001;
+			instr_sw    <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010;
+
+			instr_addi  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000;
+			instr_slti  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010;
+			instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011;
+			instr_xori  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100;
+			instr_ori   <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110;
+			instr_andi  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111;
+
+			instr_slli  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_srli  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_srai  <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+
+			instr_add   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_sub   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000;
+			instr_sll   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_slt   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_sltu  <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_xor   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_srl   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_sra   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000;
+			instr_or    <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000;
+			instr_and   <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000;
+
+			instr_rdcycle  <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) ||
+			                   (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS;
+			instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) ||
+			                   (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+			instr_rdinstr  <=  (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS;
+			instr_rdinstrh <=  (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64;
+
+			instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) ||
+					(COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002));
+			instr_fence <= (mem_rdata_q[6:0] == 7'b0001111 && !mem_rdata_q[14:12]);
+
+			instr_getq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+			instr_setq    <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS;
+			instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ;
+			instr_timer   <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER;
+
+			is_slli_srli_srai <= is_alu_reg_imm && |{
+				mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+			};
+
+			is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{
+				mem_rdata_q[14:12] == 3'b000,
+				mem_rdata_q[14:12] == 3'b010,
+				mem_rdata_q[14:12] == 3'b011,
+				mem_rdata_q[14:12] == 3'b100,
+				mem_rdata_q[14:12] == 3'b110,
+				mem_rdata_q[14:12] == 3'b111
+			};
+
+			is_sll_srl_sra <= is_alu_reg_reg && |{
+				mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000,
+				mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000
+			};
+
+			is_lui_auipc_jal_jalr_addi_add_sub <= 0;
+			is_compare <= 0;
+
+			(* parallel_case *)
+			case (1'b1)
+				instr_jal:
+					decoded_imm <= decoded_imm_j;
+				|{instr_lui, instr_auipc}:
+					decoded_imm <= mem_rdata_q[31:12] << 12;
+				|{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}:
+					decoded_imm <= $signed(mem_rdata_q[31:20]);
+				is_beq_bne_blt_bge_bltu_bgeu:
+					decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0});
+				is_sb_sh_sw:
+					decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]});
+				default:
+					decoded_imm <= 1'bx;
+			endcase
+		end
+
+		if (!resetn) begin
+			is_beq_bne_blt_bge_bltu_bgeu <= 0;
+			is_compare <= 0;
+
+			instr_beq   <= 0;
+			instr_bne   <= 0;
+			instr_blt   <= 0;
+			instr_bge   <= 0;
+			instr_bltu  <= 0;
+			instr_bgeu  <= 0;
+
+			instr_addi  <= 0;
+			instr_slti  <= 0;
+			instr_sltiu <= 0;
+			instr_xori  <= 0;
+			instr_ori   <= 0;
+			instr_andi  <= 0;
+
+			instr_add   <= 0;
+			instr_sub   <= 0;
+			instr_sll   <= 0;
+			instr_slt   <= 0;
+			instr_sltu  <= 0;
+			instr_xor   <= 0;
+			instr_srl   <= 0;
+			instr_sra   <= 0;
+			instr_or    <= 0;
+			instr_and   <= 0;
+
+			instr_fence <= 0;
+		end
+	end
+
+
+	// Main State Machine
+
+	localparam cpu_state_trap   = 8'b10000000;
+	localparam cpu_state_fetch  = 8'b01000000;
+	localparam cpu_state_ld_rs1 = 8'b00100000;
+	localparam cpu_state_ld_rs2 = 8'b00010000;
+	localparam cpu_state_exec   = 8'b00001000;
+	localparam cpu_state_shift  = 8'b00000100;
+	localparam cpu_state_stmem  = 8'b00000010;
+	localparam cpu_state_ldmem  = 8'b00000001;
+
+	reg [7:0] cpu_state;
+	reg [1:0] irq_state;
+
+	`FORMAL_KEEP reg [127:0] dbg_ascii_state;
+
+	always @* begin
+		dbg_ascii_state = "";
+		if (cpu_state == cpu_state_trap)   dbg_ascii_state = "trap";
+		if (cpu_state == cpu_state_fetch)  dbg_ascii_state = "fetch";
+		if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1";
+		if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2";
+		if (cpu_state == cpu_state_exec)   dbg_ascii_state = "exec";
+		if (cpu_state == cpu_state_shift)  dbg_ascii_state = "shift";
+		if (cpu_state == cpu_state_stmem)  dbg_ascii_state = "stmem";
+		if (cpu_state == cpu_state_ldmem)  dbg_ascii_state = "ldmem";
+	end
+
+	reg set_mem_do_rinst;
+	reg set_mem_do_rdata;
+	reg set_mem_do_wdata;
+
+	reg latched_store;
+	reg latched_stalu;
+	reg latched_branch;
+	reg latched_compr;
+	reg latched_trace;
+	reg latched_is_lu;
+	reg latched_is_lh;
+	reg latched_is_lb;
+	reg [regindex_bits-1:0] latched_rd;
+
+	reg [31:0] current_pc;
+	assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc;
+
+	reg [3:0] pcpi_timeout_counter;
+	reg pcpi_timeout;
+
+	reg [31:0] next_irq_pending;
+	reg do_waitirq;
+
+	reg [31:0] alu_out, alu_out_q;
+	reg alu_out_0, alu_out_0_q;
+	reg alu_wait, alu_wait_2;
+
+	reg [31:0] alu_add_sub;
+	reg [31:0] alu_shl, alu_shr;
+	reg alu_eq, alu_ltu, alu_lts;
+
+	generate if (TWO_CYCLE_ALU) begin
+		always @(posedge clk) begin
+			alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+			alu_eq <= reg_op1 == reg_op2;
+			alu_lts <= $signed(reg_op1) < $signed(reg_op2);
+			alu_ltu <= reg_op1 < reg_op2;
+			alu_shl <= reg_op1 << reg_op2[4:0];
+			alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+		end
+	end else begin
+		always @* begin
+			alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2;
+			alu_eq = reg_op1 == reg_op2;
+			alu_lts = $signed(reg_op1) < $signed(reg_op2);
+			alu_ltu = reg_op1 < reg_op2;
+			alu_shl = reg_op1 << reg_op2[4:0];
+			alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0];
+		end
+	end endgenerate
+
+	always @* begin
+		alu_out_0 = 'bx;
+		(* parallel_case, full_case *)
+		case (1'b1)
+			instr_beq:
+				alu_out_0 = alu_eq;
+			instr_bne:
+				alu_out_0 = !alu_eq;
+			instr_bge:
+				alu_out_0 = !alu_lts;
+			instr_bgeu:
+				alu_out_0 = !alu_ltu;
+			is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+				alu_out_0 = alu_lts;
+			is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}):
+				alu_out_0 = alu_ltu;
+		endcase
+
+		alu_out = 'bx;
+		(* parallel_case, full_case *)
+		case (1'b1)
+			is_lui_auipc_jal_jalr_addi_add_sub:
+				alu_out = alu_add_sub;
+			is_compare:
+				alu_out = alu_out_0;
+			instr_xori || instr_xor:
+				alu_out = reg_op1 ^ reg_op2;
+			instr_ori || instr_or:
+				alu_out = reg_op1 | reg_op2;
+			instr_andi || instr_and:
+				alu_out = reg_op1 & reg_op2;
+			BARREL_SHIFTER && (instr_sll || instr_slli):
+				alu_out = alu_shl;
+			BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai):
+				alu_out = alu_shr;
+		endcase
+
+`ifdef RISCV_FORMAL_BLACKBOX_ALU
+		alu_out_0 = $anyseq;
+		alu_out = $anyseq;
+`endif
+	end
+
+	reg clear_prefetched_high_word_q;
+	always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word;
+
+	always @* begin
+		clear_prefetched_high_word = clear_prefetched_high_word_q;
+		if (!prefetched_high_word)
+			clear_prefetched_high_word = 0;
+		if (latched_branch || irq_state || !resetn)
+			clear_prefetched_high_word = COMPRESSED_ISA;
+	end
+
+	reg cpuregs_write;
+	reg [31:0] cpuregs_wrdata;
+	reg [31:0] cpuregs_rs1;
+	reg [31:0] cpuregs_rs2;
+	reg [regindex_bits-1:0] decoded_rs;
+
+	always @* begin
+		cpuregs_write = 0;
+		cpuregs_wrdata = 'bx;
+
+		if (cpu_state == cpu_state_fetch) begin
+			(* parallel_case *)
+			case (1'b1)
+				latched_branch: begin
+					cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4);
+					cpuregs_write = 1;
+				end
+				latched_store && !latched_branch: begin
+					cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out;
+					cpuregs_write = 1;
+				end
+				ENABLE_IRQ && irq_state[0]: begin
+					cpuregs_wrdata = reg_next_pc | latched_compr;
+					cpuregs_write = 1;
+				end
+				ENABLE_IRQ && irq_state[1]: begin
+					cpuregs_wrdata = irq_pending & ~irq_mask;
+					cpuregs_write = 1;
+				end
+			endcase
+		end
+	end
+
+`ifndef PICORV32_REGS
+	always @(posedge clk) begin
+		if (resetn && cpuregs_write && latched_rd)
+`ifdef PICORV32_TESTBUG_001
+			cpuregs[latched_rd ^ 1] <= cpuregs_wrdata;
+`elsif PICORV32_TESTBUG_002
+			cpuregs[latched_rd] <= cpuregs_wrdata ^ 1;
+`else
+			cpuregs[latched_rd] <= cpuregs_wrdata;
+`endif
+	end
+
+	always @* begin
+		decoded_rs = 'bx;
+		if (ENABLE_REGS_DUALPORT) begin
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+			cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0;
+			cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0;
+`else
+			cpuregs_rs1 = decoded_rs1 ? $anyseq : 0;
+			cpuregs_rs2 = decoded_rs2 ? $anyseq : 0;
+`endif
+		end else begin
+			decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+`ifndef RISCV_FORMAL_BLACKBOX_REGS
+			cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0;
+`else
+			cpuregs_rs1 = decoded_rs ? $anyseq : 0;
+`endif
+			cpuregs_rs2 = cpuregs_rs1;
+		end
+	end
+`else
+	wire[31:0] cpuregs_rdata1;
+	wire[31:0] cpuregs_rdata2;
+
+	wire [5:0] cpuregs_waddr = latched_rd;
+	wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs;
+	wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0;
+
+	`PICORV32_REGS cpuregs (
+		.clk(clk),
+		.wen(resetn && cpuregs_write && latched_rd),
+		.waddr(cpuregs_waddr),
+		.raddr1(cpuregs_raddr1),
+		.raddr2(cpuregs_raddr2),
+		.wdata(cpuregs_wrdata),
+		.rdata1(cpuregs_rdata1),
+		.rdata2(cpuregs_rdata2)
+	);
+
+	always @* begin
+		decoded_rs = 'bx;
+		if (ENABLE_REGS_DUALPORT) begin
+			cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0;
+			cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0;
+		end else begin
+			decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1;
+			cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0;
+			cpuregs_rs2 = cpuregs_rs1;
+		end
+	end
+`endif
+
+	assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask));
+
+	always @(posedge clk) begin
+		trap <= 0;
+		reg_sh <= 'bx;
+		reg_out <= 'bx;
+		set_mem_do_rinst = 0;
+		set_mem_do_rdata = 0;
+		set_mem_do_wdata = 0;
+
+		alu_out_0_q <= alu_out_0;
+		alu_out_q <= alu_out;
+
+		alu_wait <= 0;
+		alu_wait_2 <= 0;
+
+		if (launch_next_insn) begin
+			dbg_rs1val <= 'bx;
+			dbg_rs2val <= 'bx;
+			dbg_rs1val_valid <= 0;
+			dbg_rs2val_valid <= 0;
+		end
+
+		if (WITH_PCPI && CATCH_ILLINSN) begin
+			if (resetn && pcpi_valid && !pcpi_int_wait) begin
+				if (pcpi_timeout_counter)
+					pcpi_timeout_counter <= pcpi_timeout_counter - 1;
+			end else
+				pcpi_timeout_counter <= ~0;
+			pcpi_timeout <= !pcpi_timeout_counter;
+		end
+
+		if (ENABLE_COUNTERS) begin
+			count_cycle <= resetn ? count_cycle + 1 : 0;
+			if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0;
+		end else begin
+			count_cycle <= 'bx;
+			count_instr <= 'bx;
+		end
+
+		next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx;
+
+		if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin
+			timer <= timer - 1;
+		end
+
+		decoder_trigger <= mem_do_rinst && mem_done;
+		decoder_trigger_q <= decoder_trigger;
+		decoder_pseudo_trigger <= 0;
+		decoder_pseudo_trigger_q <= decoder_pseudo_trigger;
+		do_waitirq <= 0;
+
+		trace_valid <= 0;
+
+		if (!ENABLE_TRACE)
+			trace_data <= 'bx;
+
+		if (!resetn) begin
+			reg_pc <= PROGADDR_RESET;
+			reg_next_pc <= PROGADDR_RESET;
+			if (ENABLE_COUNTERS)
+				count_instr <= 0;
+			latched_store <= 0;
+			latched_stalu <= 0;
+			latched_branch <= 0;
+			latched_trace <= 0;
+			latched_is_lu <= 0;
+			latched_is_lh <= 0;
+			latched_is_lb <= 0;
+			pcpi_valid <= 0;
+			pcpi_timeout <= 0;
+			irq_active <= 0;
+			irq_delay <= 0;
+			irq_mask <= ~0;
+			next_irq_pending = 0;
+			irq_state <= 0;
+			eoi <= 0;
+			timer <= 0;
+			if (~STACKADDR) begin
+				latched_store <= 1;
+				latched_rd <= 2;
+				reg_out <= STACKADDR;
+			end
+			cpu_state <= cpu_state_fetch;
+		end else
+		(* parallel_case, full_case *)
+		case (cpu_state)
+			cpu_state_trap: begin
+				trap <= 1;
+			end
+
+			cpu_state_fetch: begin
+				mem_do_rinst <= !decoder_trigger && !do_waitirq;
+				mem_wordsize <= 0;
+
+				current_pc = reg_next_pc;
+
+				(* parallel_case *)
+				case (1'b1)
+					latched_branch: begin
+						current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc;
+						`debug($display("ST_RD:  %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);)
+					end
+					latched_store && !latched_branch: begin
+						`debug($display("ST_RD:  %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);)
+					end
+					ENABLE_IRQ && irq_state[0]: begin
+						current_pc = PROGADDR_IRQ;
+						irq_active <= 1;
+						mem_do_rinst <= 1;
+					end
+					ENABLE_IRQ && irq_state[1]: begin
+						eoi <= irq_pending & ~irq_mask;
+						next_irq_pending = next_irq_pending & irq_mask;
+					end
+				endcase
+
+				if (ENABLE_TRACE && latched_trace) begin
+					latched_trace <= 0;
+					trace_valid <= 1;
+					if (latched_branch)
+						trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe);
+					else
+						trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out);
+				end
+
+				reg_pc <= current_pc;
+				reg_next_pc <= current_pc;
+
+				latched_store <= 0;
+				latched_stalu <= 0;
+				latched_branch <= 0;
+				latched_is_lu <= 0;
+				latched_is_lh <= 0;
+				latched_is_lb <= 0;
+				latched_rd <= decoded_rd;
+				latched_compr <= compressed_instr;
+
+				if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin
+					irq_state <=
+						irq_state == 2'b00 ? 2'b01 :
+						irq_state == 2'b01 ? 2'b10 : 2'b00;
+					latched_compr <= latched_compr;
+					if (ENABLE_IRQ_QREGS)
+						latched_rd <= irqregs_offset | irq_state[0];
+					else
+						latched_rd <= irq_state[0] ? 4 : 3;
+				end else
+				if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin
+					if (irq_pending) begin
+						latched_store <= 1;
+						reg_out <= irq_pending;
+						reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+						mem_do_rinst <= 1;
+					end else
+						do_waitirq <= 1;
+				end else
+				if (decoder_trigger) begin
+					`debug($display("-- %-0t", $time);)
+					irq_delay <= irq_active;
+					reg_next_pc <= current_pc + (compressed_instr ? 2 : 4);
+					if (ENABLE_TRACE)
+						latched_trace <= 1;
+					if (ENABLE_COUNTERS) begin
+						count_instr <= count_instr + 1;
+						if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0;
+					end
+					if (instr_jal) begin
+						mem_do_rinst <= 1;
+						reg_next_pc <= current_pc + decoded_imm_j;
+						latched_branch <= 1;
+					end else begin
+						mem_do_rinst <= 0;
+						mem_do_prefetch <= !instr_jalr && !instr_retirq;
+						cpu_state <= cpu_state_ld_rs1;
+					end
+				end
+			end
+
+			cpu_state_ld_rs1: begin
+				reg_op1 <= 'bx;
+				reg_op2 <= 'bx;
+
+				(* parallel_case *)
+				case (1'b1)
+					(CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin
+						if (WITH_PCPI) begin
+							`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+							reg_op1 <= cpuregs_rs1;
+							dbg_rs1val <= cpuregs_rs1;
+							dbg_rs1val_valid <= 1;
+							if (ENABLE_REGS_DUALPORT) begin
+								pcpi_valid <= 1;
+								`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+								reg_sh <= cpuregs_rs2;
+								reg_op2 <= cpuregs_rs2;
+								dbg_rs2val <= cpuregs_rs2;
+								dbg_rs2val_valid <= 1;
+								if (pcpi_int_ready) begin
+									mem_do_rinst <= 1;
+									pcpi_valid <= 0;
+									reg_out <= pcpi_int_rd;
+									latched_store <= pcpi_int_wr;
+									cpu_state <= cpu_state_fetch;
+								end else
+								if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+									pcpi_valid <= 0;
+									`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+									if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+										next_irq_pending[irq_ebreak] = 1;
+										cpu_state <= cpu_state_fetch;
+									end else
+										cpu_state <= cpu_state_trap;
+								end
+							end else begin
+								cpu_state <= cpu_state_ld_rs2;
+							end
+						end else begin
+							`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+							if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+								next_irq_pending[irq_ebreak] = 1;
+								cpu_state <= cpu_state_fetch;
+							end else
+								cpu_state <= cpu_state_trap;
+						end
+					end
+					ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							instr_rdcycle:
+								reg_out <= count_cycle[31:0];
+							instr_rdcycleh && ENABLE_COUNTERS64:
+								reg_out <= count_cycle[63:32];
+							instr_rdinstr:
+								reg_out <= count_instr[31:0];
+							instr_rdinstrh && ENABLE_COUNTERS64:
+								reg_out <= count_instr[63:32];
+						endcase
+						latched_store <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					is_lui_auipc_jal: begin
+						reg_op1 <= instr_lui ? 0 : reg_pc;
+						reg_op2 <= decoded_imm;
+						if (TWO_CYCLE_ALU)
+							alu_wait <= 1;
+						else
+							mem_do_rinst <= mem_do_prefetch;
+						cpu_state <= cpu_state_exec;
+					end
+					ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_out <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						latched_store <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_out <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						latched_rd <= latched_rd | irqregs_offset;
+						latched_store <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && instr_retirq: begin
+						eoi <= 0;
+						irq_active <= 0;
+						latched_branch <= 1;
+						latched_store <= 1;
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && instr_maskirq: begin
+						latched_store <= 1;
+						reg_out <= irq_mask;
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						irq_mask <= cpuregs_rs1 | MASKED_IRQ;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin
+						latched_store <= 1;
+						reg_out <= timer;
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						timer <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+					is_lb_lh_lw_lbu_lhu && !instr_trap: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						cpu_state <= cpu_state_ldmem;
+						mem_do_rinst <= 1;
+					end
+					is_slli_srli_srai && !BARREL_SHIFTER: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						reg_sh <= decoded_rs2;
+						cpu_state <= cpu_state_shift;
+					end
+					is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm;
+						if (TWO_CYCLE_ALU)
+							alu_wait <= 1;
+						else
+							mem_do_rinst <= mem_do_prefetch;
+						cpu_state <= cpu_state_exec;
+					end
+					default: begin
+						`debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);)
+						reg_op1 <= cpuregs_rs1;
+						dbg_rs1val <= cpuregs_rs1;
+						dbg_rs1val_valid <= 1;
+						if (ENABLE_REGS_DUALPORT) begin
+							`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+							reg_sh <= cpuregs_rs2;
+							reg_op2 <= cpuregs_rs2;
+							dbg_rs2val <= cpuregs_rs2;
+							dbg_rs2val_valid <= 1;
+							(* parallel_case *)
+							case (1'b1)
+								is_sb_sh_sw: begin
+									cpu_state <= cpu_state_stmem;
+									mem_do_rinst <= 1;
+								end
+								is_sll_srl_sra && !BARREL_SHIFTER: begin
+									cpu_state <= cpu_state_shift;
+								end
+								default: begin
+									if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+										alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+										alu_wait <= 1;
+									end else
+										mem_do_rinst <= mem_do_prefetch;
+									cpu_state <= cpu_state_exec;
+								end
+							endcase
+						end else
+							cpu_state <= cpu_state_ld_rs2;
+					end
+				endcase
+			end
+
+			cpu_state_ld_rs2: begin
+				`debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);)
+				reg_sh <= cpuregs_rs2;
+				reg_op2 <= cpuregs_rs2;
+				dbg_rs2val <= cpuregs_rs2;
+				dbg_rs2val_valid <= 1;
+
+				(* parallel_case *)
+				case (1'b1)
+					WITH_PCPI && instr_trap: begin
+						pcpi_valid <= 1;
+						if (pcpi_int_ready) begin
+							mem_do_rinst <= 1;
+							pcpi_valid <= 0;
+							reg_out <= pcpi_int_rd;
+							latched_store <= pcpi_int_wr;
+							cpu_state <= cpu_state_fetch;
+						end else
+						if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin
+							pcpi_valid <= 0;
+							`debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);)
+							if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin
+								next_irq_pending[irq_ebreak] = 1;
+								cpu_state <= cpu_state_fetch;
+							end else
+								cpu_state <= cpu_state_trap;
+						end
+					end
+					is_sb_sh_sw: begin
+						cpu_state <= cpu_state_stmem;
+						mem_do_rinst <= 1;
+					end
+					is_sll_srl_sra && !BARREL_SHIFTER: begin
+						cpu_state <= cpu_state_shift;
+					end
+					default: begin
+						if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin
+							alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu);
+							alu_wait <= 1;
+						end else
+							mem_do_rinst <= mem_do_prefetch;
+						cpu_state <= cpu_state_exec;
+					end
+				endcase
+			end
+
+			cpu_state_exec: begin
+				reg_out <= reg_pc + decoded_imm;
+				if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin
+					mem_do_rinst <= mem_do_prefetch && !alu_wait_2;
+					alu_wait <= alu_wait_2;
+				end else
+				if (is_beq_bne_blt_bge_bltu_bgeu) begin
+					latched_rd <= 0;
+					latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+					latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0;
+					if (mem_done)
+						cpu_state <= cpu_state_fetch;
+					if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin
+						decoder_trigger <= 0;
+						set_mem_do_rinst = 1;
+					end
+				end else begin
+					latched_branch <= instr_jalr;
+					latched_store <= 1;
+					latched_stalu <= 1;
+					cpu_state <= cpu_state_fetch;
+				end
+			end
+
+			cpu_state_shift: begin
+				latched_store <= 1;
+				if (reg_sh == 0) begin
+					reg_out <= reg_op1;
+					mem_do_rinst <= mem_do_prefetch;
+					cpu_state <= cpu_state_fetch;
+				end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin
+					(* parallel_case, full_case *)
+					case (1'b1)
+						instr_slli || instr_sll: reg_op1 <= reg_op1 << 4;
+						instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4;
+						instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4;
+					endcase
+					reg_sh <= reg_sh - 4;
+				end else begin
+					(* parallel_case, full_case *)
+					case (1'b1)
+						instr_slli || instr_sll: reg_op1 <= reg_op1 << 1;
+						instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1;
+						instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1;
+					endcase
+					reg_sh <= reg_sh - 1;
+				end
+			end
+
+			cpu_state_stmem: begin
+				if (ENABLE_TRACE)
+					reg_out <= reg_op2;
+				if (!mem_do_prefetch || mem_done) begin
+					if (!mem_do_wdata) begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							instr_sb: mem_wordsize <= 2;
+							instr_sh: mem_wordsize <= 1;
+							instr_sw: mem_wordsize <= 0;
+						endcase
+						if (ENABLE_TRACE) begin
+							trace_valid <= 1;
+							trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+						end
+						reg_op1 <= reg_op1 + decoded_imm;
+						set_mem_do_wdata = 1;
+					end
+					if (!mem_do_prefetch && mem_done) begin
+						cpu_state <= cpu_state_fetch;
+						decoder_trigger <= 1;
+						decoder_pseudo_trigger <= 1;
+					end
+				end
+			end
+
+			cpu_state_ldmem: begin
+				latched_store <= 1;
+				if (!mem_do_prefetch || mem_done) begin
+					if (!mem_do_rdata) begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							instr_lb || instr_lbu: mem_wordsize <= 2;
+							instr_lh || instr_lhu: mem_wordsize <= 1;
+							instr_lw: mem_wordsize <= 0;
+						endcase
+						latched_is_lu <= is_lbu_lhu_lw;
+						latched_is_lh <= instr_lh;
+						latched_is_lb <= instr_lb;
+						if (ENABLE_TRACE) begin
+							trace_valid <= 1;
+							trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff);
+						end
+						reg_op1 <= reg_op1 + decoded_imm;
+						set_mem_do_rdata = 1;
+					end
+					if (!mem_do_prefetch && mem_done) begin
+						(* parallel_case, full_case *)
+						case (1'b1)
+							latched_is_lu: reg_out <= mem_rdata_word;
+							latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]);
+							latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]);
+						endcase
+						decoder_trigger <= 1;
+						decoder_pseudo_trigger <= 1;
+						cpu_state <= cpu_state_fetch;
+					end
+				end
+			end
+		endcase
+
+		if (ENABLE_IRQ) begin
+			next_irq_pending = next_irq_pending | irq;
+			if(ENABLE_IRQ_TIMER && timer)
+				if (timer - 1 == 0)
+					next_irq_pending[irq_timer] = 1;
+		end
+
+		if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin
+			if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin
+				`debug($display("MISALIGNED WORD: 0x%08x", reg_op1);)
+				if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+					next_irq_pending[irq_buserror] = 1;
+				end else
+					cpu_state <= cpu_state_trap;
+			end
+			if (mem_wordsize == 1 && reg_op1[0] != 0) begin
+				`debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);)
+				if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+					next_irq_pending[irq_buserror] = 1;
+				end else
+					cpu_state <= cpu_state_trap;
+			end
+		end
+		if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin
+			`debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);)
+			if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin
+				next_irq_pending[irq_buserror] = 1;
+			end else
+				cpu_state <= cpu_state_trap;
+		end
+		if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin
+			cpu_state <= cpu_state_trap;
+		end
+
+		if (!resetn || mem_done) begin
+			mem_do_prefetch <= 0;
+			mem_do_rinst <= 0;
+			mem_do_rdata <= 0;
+			mem_do_wdata <= 0;
+		end
+
+		if (set_mem_do_rinst)
+			mem_do_rinst <= 1;
+		if (set_mem_do_rdata)
+			mem_do_rdata <= 1;
+		if (set_mem_do_wdata)
+			mem_do_wdata <= 1;
+
+		irq_pending <= next_irq_pending & ~MASKED_IRQ;
+
+		if (!CATCH_MISALIGN) begin
+			if (COMPRESSED_ISA) begin
+				reg_pc[0] <= 0;
+				reg_next_pc[0] <= 0;
+			end else begin
+				reg_pc[1:0] <= 0;
+				reg_next_pc[1:0] <= 0;
+			end
+		end
+		current_pc = 'bx;
+	end
+
+`ifdef RISCV_FORMAL
+	reg dbg_irq_call;
+	reg dbg_irq_enter;
+	reg [31:0] dbg_irq_ret;
+	always @(posedge clk) begin
+		rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn;
+		rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0;
+
+		rvfi_insn <= dbg_insn_opcode;
+		rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0;
+		rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0;
+		rvfi_pc_rdata <= dbg_insn_addr;
+		rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0;
+		rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0;
+		rvfi_trap <= trap;
+		rvfi_halt <= trap;
+		rvfi_intr <= dbg_irq_enter;
+		rvfi_mode <= 3;
+		rvfi_ixl <= 1;
+
+		if (!resetn) begin
+			dbg_irq_call <= 0;
+			dbg_irq_enter <= 0;
+		end else
+		if (rvfi_valid) begin
+			dbg_irq_call <= 0;
+			dbg_irq_enter <= dbg_irq_call;
+		end else
+		if (irq_state == 1) begin
+			dbg_irq_call <= 1;
+			dbg_irq_ret <= next_pc;
+		end
+
+		if (!resetn) begin
+			rvfi_rd_addr <= 0;
+			rvfi_rd_wdata <= 0;
+		end else
+		if (cpuregs_write && !irq_state) begin
+`ifdef PICORV32_TESTBUG_003
+			rvfi_rd_addr <= latched_rd ^ 1;
+`else
+			rvfi_rd_addr <= latched_rd;
+`endif
+`ifdef PICORV32_TESTBUG_004
+			rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata ^ 1 : 0;
+`else
+			rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0;
+`endif
+		end else
+		if (rvfi_valid) begin
+			rvfi_rd_addr <= 0;
+			rvfi_rd_wdata <= 0;
+		end
+
+		casez (dbg_insn_opcode)
+			32'b 0000000_?????_000??_???_?????_0001011: begin // getq
+				rvfi_rs1_addr <= 0;
+				rvfi_rs1_rdata <= 0;
+			end
+			32'b 0000001_?????_?????_???_000??_0001011: begin // setq
+				rvfi_rd_addr <= 0;
+				rvfi_rd_wdata <= 0;
+			end
+			32'b 0000010_?????_00000_???_00000_0001011: begin // retirq
+				rvfi_rs1_addr <= 0;
+				rvfi_rs1_rdata <= 0;
+			end
+		endcase
+
+		if (!dbg_irq_call) begin
+			if (dbg_mem_instr) begin
+				rvfi_mem_addr <= 0;
+				rvfi_mem_rmask <= 0;
+				rvfi_mem_wmask <= 0;
+				rvfi_mem_rdata <= 0;
+				rvfi_mem_wdata <= 0;
+			end else
+			if (dbg_mem_valid && dbg_mem_ready) begin
+				rvfi_mem_addr <= dbg_mem_addr;
+				rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0;
+				rvfi_mem_wmask <= dbg_mem_wstrb;
+				rvfi_mem_rdata <= dbg_mem_rdata;
+				rvfi_mem_wdata <= dbg_mem_wdata;
+			end
+		end
+	end
+
+	always @* begin
+`ifdef PICORV32_TESTBUG_005
+		rvfi_pc_wdata = (dbg_irq_call ? dbg_irq_ret : dbg_insn_addr) ^ 4;
+`else
+		rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr;
+`endif
+
+		rvfi_csr_mcycle_rmask = 0;
+		rvfi_csr_mcycle_wmask = 0;
+		rvfi_csr_mcycle_rdata = 0;
+		rvfi_csr_mcycle_wdata = 0;
+
+		rvfi_csr_minstret_rmask = 0;
+		rvfi_csr_minstret_wmask = 0;
+		rvfi_csr_minstret_rdata = 0;
+		rvfi_csr_minstret_wdata = 0;
+
+		if (rvfi_valid && rvfi_insn[6:0] == 7'b 1110011 && rvfi_insn[13:12] == 3'b010) begin
+			if (rvfi_insn[31:20] == 12'h C00) begin
+				rvfi_csr_mcycle_rmask = 64'h 0000_0000_FFFF_FFFF;
+				rvfi_csr_mcycle_rdata = {32'h 0000_0000, rvfi_rd_wdata};
+			end
+			if (rvfi_insn[31:20] == 12'h C80) begin
+				rvfi_csr_mcycle_rmask = 64'h FFFF_FFFF_0000_0000;
+				rvfi_csr_mcycle_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
+			end
+			if (rvfi_insn[31:20] == 12'h C02) begin
+				rvfi_csr_minstret_rmask = 64'h 0000_0000_FFFF_FFFF;
+				rvfi_csr_minstret_rdata = {32'h 0000_0000, rvfi_rd_wdata};
+			end
+			if (rvfi_insn[31:20] == 12'h C82) begin
+				rvfi_csr_minstret_rmask = 64'h FFFF_FFFF_0000_0000;
+				rvfi_csr_minstret_rdata = {rvfi_rd_wdata, 32'h 0000_0000};
+			end
+		end
+	end
+`endif
+
+	// Formal Verification
+`ifdef FORMAL
+	reg [3:0] last_mem_nowait;
+	always @(posedge clk)
+		last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid};
+
+	// stall the memory interface for max 4 cycles
+	restrict property (|last_mem_nowait || mem_ready || !mem_valid);
+
+	// resetn low in first cycle, after that resetn high
+	restrict property (resetn != $initstate);
+
+	// this just makes it much easier to read traces. uncomment as needed.
+	// assume property (mem_valid || !mem_ready);
+
+	reg ok;
+	always @* begin
+		if (resetn) begin
+			// instruction fetches are read-only
+			if (mem_valid && mem_instr)
+				assert (mem_wstrb == 0);
+
+			// cpu_state must be valid
+			ok = 0;
+			if (cpu_state == cpu_state_trap)   ok = 1;
+			if (cpu_state == cpu_state_fetch)  ok = 1;
+			if (cpu_state == cpu_state_ld_rs1) ok = 1;
+			if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT;
+			if (cpu_state == cpu_state_exec)   ok = 1;
+			if (cpu_state == cpu_state_shift)  ok = 1;
+			if (cpu_state == cpu_state_stmem)  ok = 1;
+			if (cpu_state == cpu_state_ldmem)  ok = 1;
+			assert (ok);
+		end
+	end
+
+	reg last_mem_la_read = 0;
+	reg last_mem_la_write = 0;
+	reg [31:0] last_mem_la_addr;
+	reg [31:0] last_mem_la_wdata;
+	reg [3:0] last_mem_la_wstrb = 0;
+
+	always @(posedge clk) begin
+		last_mem_la_read <= mem_la_read;
+		last_mem_la_write <= mem_la_write;
+		last_mem_la_addr <= mem_la_addr;
+		last_mem_la_wdata <= mem_la_wdata;
+		last_mem_la_wstrb <= mem_la_wstrb;
+
+		if (last_mem_la_read) begin
+			assert(mem_valid);
+			assert(mem_addr == last_mem_la_addr);
+			assert(mem_wstrb == 0);
+		end
+		if (last_mem_la_write) begin
+			assert(mem_valid);
+			assert(mem_addr == last_mem_la_addr);
+			assert(mem_wdata == last_mem_la_wdata);
+			assert(mem_wstrb == last_mem_la_wstrb);
+		end
+		if (mem_la_read || mem_la_write) begin
+			assert(!mem_valid || mem_ready);
+		end
+	end
+`endif
+endmodule
+
+// This is a simple example implementation of PICORV32_REGS.
+// Use the PICORV32_REGS mechanism if you want to use custom
+// memory resources to implement the processor register file.
+// Note that your implementation must match the requirements of
+// the PicoRV32 configuration. (e.g. QREGS, etc)
+module picorv32_regs (
+	input clk, wen,
+	input [5:0] waddr,
+	input [5:0] raddr1,
+	input [5:0] raddr2,
+	input [31:0] wdata,
+	output [31:0] rdata1,
+	output [31:0] rdata2
+);
+	reg [31:0] regs [0:30];
+
+	always @(posedge clk)
+		if (wen) regs[~waddr[4:0]] <= wdata;
+
+	assign rdata1 = regs[~raddr1[4:0]];
+	assign rdata2 = regs[~raddr2[4:0]];
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_mul
+ ***************************************************************/
+
+module picorv32_pcpi_mul #(
+	parameter STEPS_AT_ONCE = 1,
+	parameter CARRY_CHAIN = 4
+) (
+	input clk, resetn,
+
+	input             pcpi_valid,
+	input      [31:0] pcpi_insn,
+	input      [31:0] pcpi_rs1,
+	input      [31:0] pcpi_rs2,
+	output reg        pcpi_wr,
+	output reg [31:0] pcpi_rd,
+	output reg        pcpi_wait,
+	output reg        pcpi_ready
+);
+	reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+	wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+	wire instr_rs2_signed = |{instr_mulh};
+
+	reg pcpi_wait_q;
+	wire mul_start = pcpi_wait && !pcpi_wait_q;
+
+	always @(posedge clk) begin
+		instr_mul <= 0;
+		instr_mulh <= 0;
+		instr_mulhsu <= 0;
+		instr_mulhu <= 0;
+
+		if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+			case (pcpi_insn[14:12])
+				3'b000: instr_mul <= 1;
+				3'b001: instr_mulh <= 1;
+				3'b010: instr_mulhsu <= 1;
+				3'b011: instr_mulhu <= 1;
+			endcase
+		end
+
+		pcpi_wait <= instr_any_mul;
+		pcpi_wait_q <= pcpi_wait;
+	end
+
+	reg [63:0] rs1, rs2, rd, rdx;
+	reg [63:0] next_rs1, next_rs2, this_rs2;
+	reg [63:0] next_rd, next_rdx, next_rdt;
+	reg [6:0] mul_counter;
+	reg mul_waiting;
+	reg mul_finish;
+	integer i, j;
+
+	// carry save accumulator
+	always @* begin
+		next_rd = rd;
+		next_rdx = rdx;
+		next_rs1 = rs1;
+		next_rs2 = rs2;
+
+		for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin
+			this_rs2 = next_rs1[0] ? next_rs2 : 0;
+			if (CARRY_CHAIN == 0) begin
+				next_rdt = next_rd ^ next_rdx ^ this_rs2;
+				next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1;
+				next_rd = next_rdt;
+			end else begin
+				next_rdt = 0;
+				for (j = 0; j < 64; j = j + CARRY_CHAIN)
+					{next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} =
+							next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN];
+				next_rdx = next_rdt << 1;
+			end
+			next_rs1 = next_rs1 >> 1;
+			next_rs2 = next_rs2 << 1;
+		end
+	end
+
+	always @(posedge clk) begin
+		mul_finish <= 0;
+		if (!resetn) begin
+			mul_waiting <= 1;
+		end else
+		if (mul_waiting) begin
+			if (instr_rs1_signed)
+				rs1 <= $signed(pcpi_rs1);
+			else
+				rs1 <= $unsigned(pcpi_rs1);
+
+			if (instr_rs2_signed)
+				rs2 <= $signed(pcpi_rs2);
+			else
+				rs2 <= $unsigned(pcpi_rs2);
+
+			rd <= 0;
+			rdx <= 0;
+			mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE);
+			mul_waiting <= !mul_start;
+		end else begin
+			rd <= next_rd;
+			rdx <= next_rdx;
+			rs1 <= next_rs1;
+			rs2 <= next_rs2;
+
+			mul_counter <= mul_counter - STEPS_AT_ONCE;
+			if (mul_counter[6]) begin
+				mul_finish <= 1;
+				mul_waiting <= 1;
+			end
+		end
+	end
+
+	always @(posedge clk) begin
+		pcpi_wr <= 0;
+		pcpi_ready <= 0;
+		if (mul_finish && resetn) begin
+			pcpi_wr <= 1;
+			pcpi_ready <= 1;
+			pcpi_rd <= instr_any_mulh ? rd >> 32 : rd;
+		end
+	end
+endmodule
+
+module picorv32_pcpi_fast_mul #(
+	parameter EXTRA_MUL_FFS = 0,
+	parameter EXTRA_INSN_FFS = 0,
+	parameter MUL_CLKGATE = 0
+) (
+	input clk, resetn,
+
+	input             pcpi_valid,
+	input      [31:0] pcpi_insn,
+	input      [31:0] pcpi_rs1,
+	input      [31:0] pcpi_rs2,
+	output            pcpi_wr,
+	output     [31:0] pcpi_rd,
+	output            pcpi_wait,
+	output            pcpi_ready
+);
+	reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu;
+	wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu};
+	wire instr_rs1_signed = |{instr_mulh, instr_mulhsu};
+	wire instr_rs2_signed = |{instr_mulh};
+
+	reg shift_out;
+	reg [3:0] active;
+	reg [32:0] rs1, rs2, rs1_q, rs2_q;
+	reg [63:0] rd, rd_q;
+
+	wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001;
+	reg pcpi_insn_valid_q;
+
+	always @* begin
+		instr_mul = 0;
+		instr_mulh = 0;
+		instr_mulhsu = 0;
+		instr_mulhu = 0;
+
+		if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin
+			case (pcpi_insn[14:12])
+				3'b000: instr_mul = 1;
+				3'b001: instr_mulh = 1;
+				3'b010: instr_mulhsu = 1;
+				3'b011: instr_mulhu = 1;
+			endcase
+		end
+	end
+
+	always @(posedge clk) begin
+		pcpi_insn_valid_q <= pcpi_insn_valid;
+		if (!MUL_CLKGATE || active[0]) begin
+			rs1_q <= rs1;
+			rs2_q <= rs2;
+		end
+		if (!MUL_CLKGATE || active[1]) begin
+			rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2);
+		end
+		if (!MUL_CLKGATE || active[2]) begin
+			rd_q <= rd;
+		end
+	end
+
+	always @(posedge clk) begin
+		if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin
+			if (instr_rs1_signed)
+				rs1 <= $signed(pcpi_rs1);
+			else
+				rs1 <= $unsigned(pcpi_rs1);
+
+			if (instr_rs2_signed)
+				rs2 <= $signed(pcpi_rs2);
+			else
+				rs2 <= $unsigned(pcpi_rs2);
+			active[0] <= 1;
+		end else begin
+			active[0] <= 0;
+		end
+
+		active[3:1] <= active;
+		shift_out <= instr_any_mulh;
+
+		if (!resetn)
+			active <= 0;
+	end
+
+	assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1];
+	assign pcpi_wait = 0;
+	assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1];
+`ifdef RISCV_FORMAL_ALTOPS
+	assign pcpi_rd =
+			instr_mul    ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e :
+			instr_mulh   ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 :
+			instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 :
+			instr_mulhu  ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx;
+`else
+	assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd);
+`endif
+endmodule
+
+
+/***************************************************************
+ * picorv32_pcpi_div
+ ***************************************************************/
+
+module picorv32_pcpi_div (
+	input clk, resetn,
+
+	input             pcpi_valid,
+	input      [31:0] pcpi_insn,
+	input      [31:0] pcpi_rs1,
+	input      [31:0] pcpi_rs2,
+	output reg        pcpi_wr,
+	output reg [31:0] pcpi_rd,
+	output reg        pcpi_wait,
+	output reg        pcpi_ready
+);
+	reg instr_div, instr_divu, instr_rem, instr_remu;
+	wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu};
+
+	reg pcpi_wait_q;
+	wire start = pcpi_wait && !pcpi_wait_q;
+
+	always @(posedge clk) begin
+		instr_div <= 0;
+		instr_divu <= 0;
+		instr_rem <= 0;
+		instr_remu <= 0;
+
+		if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin
+			case (pcpi_insn[14:12])
+				3'b100: instr_div <= 1;
+				3'b101: instr_divu <= 1;
+				3'b110: instr_rem <= 1;
+				3'b111: instr_remu <= 1;
+			endcase
+		end
+
+		pcpi_wait <= instr_any_div_rem && resetn;
+		pcpi_wait_q <= pcpi_wait && resetn;
+	end
+
+	reg [31:0] dividend;
+	reg [62:0] divisor;
+	reg [31:0] quotient;
+	reg [31:0] quotient_msk;
+	reg running;
+	reg outsign;
+
+	always @(posedge clk) begin
+		pcpi_ready <= 0;
+		pcpi_wr <= 0;
+		pcpi_rd <= 'bx;
+
+		if (!resetn) begin
+			running <= 0;
+		end else
+		if (start) begin
+			running <= 1;
+			dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1;
+			divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31;
+			outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]);
+			quotient <= 0;
+			quotient_msk <= 1 << 31;
+		end else
+		if (!quotient_msk && running) begin
+			running <= 0;
+			pcpi_ready <= 1;
+			pcpi_wr <= 1;
+`ifdef RISCV_FORMAL_ALTOPS
+			case (1)
+				instr_div:  pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec;
+				instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70;
+				instr_rem:  pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5;
+				instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1;
+			endcase
+`else
+			if (instr_div || instr_divu)
+				pcpi_rd <= outsign ? -quotient : quotient;
+			else
+				pcpi_rd <= outsign ? -dividend : dividend;
+`endif
+		end else begin
+			if (divisor <= dividend) begin
+				dividend <= dividend - divisor;
+				quotient <= quotient | quotient_msk;
+			end
+			divisor <= divisor >> 1;
+`ifdef RISCV_FORMAL_ALTOPS
+			quotient_msk <= quotient_msk >> 5;
+`else
+			quotient_msk <= quotient_msk >> 1;
+`endif
+		end
+	end
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi
+ ***************************************************************/
+
+module picorv32_axi #(
+	parameter [ 0:0] ENABLE_COUNTERS = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+	parameter [ 0:0] BARREL_SHIFTER = 0,
+	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 0,
+	parameter [ 0:0] CATCH_MISALIGN = 1,
+	parameter [ 0:0] CATCH_ILLINSN = 1,
+	parameter [ 0:0] ENABLE_PCPI = 0,
+	parameter [ 0:0] ENABLE_MUL = 0,
+	parameter [ 0:0] ENABLE_FAST_MUL = 0,
+	parameter [ 0:0] ENABLE_DIV = 0,
+	parameter [ 0:0] ENABLE_IRQ = 0,
+	parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+	parameter [ 0:0] ENABLE_TRACE = 0,
+	parameter [ 0:0] REGS_INIT_ZERO = 0,
+	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+	input clk, resetn,
+	output trap,
+
+	// AXI4-lite master memory interface
+
+	output        mem_axi_awvalid,
+	input         mem_axi_awready,
+	output [31:0] mem_axi_awaddr,
+	output [ 2:0] mem_axi_awprot,
+
+	output        mem_axi_wvalid,
+	input         mem_axi_wready,
+	output [31:0] mem_axi_wdata,
+	output [ 3:0] mem_axi_wstrb,
+
+	input         mem_axi_bvalid,
+	output        mem_axi_bready,
+
+	output        mem_axi_arvalid,
+	input         mem_axi_arready,
+	output [31:0] mem_axi_araddr,
+	output [ 2:0] mem_axi_arprot,
+
+	input         mem_axi_rvalid,
+	output        mem_axi_rready,
+	input  [31:0] mem_axi_rdata,
+
+	// Pico Co-Processor Interface (PCPI)
+	output        pcpi_valid,
+	output [31:0] pcpi_insn,
+	output [31:0] pcpi_rs1,
+	output [31:0] pcpi_rs2,
+	input         pcpi_wr,
+	input  [31:0] pcpi_rd,
+	input         pcpi_wait,
+	input         pcpi_ready,
+
+	// IRQ interface
+	input  [31:0] irq,
+	output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+	output        rvfi_valid,
+	output [63:0] rvfi_order,
+	output [31:0] rvfi_insn,
+	output        rvfi_trap,
+	output        rvfi_halt,
+	output        rvfi_intr,
+	output [ 4:0] rvfi_rs1_addr,
+	output [ 4:0] rvfi_rs2_addr,
+	output [31:0] rvfi_rs1_rdata,
+	output [31:0] rvfi_rs2_rdata,
+	output [ 4:0] rvfi_rd_addr,
+	output [31:0] rvfi_rd_wdata,
+	output [31:0] rvfi_pc_rdata,
+	output [31:0] rvfi_pc_wdata,
+	output [31:0] rvfi_mem_addr,
+	output [ 3:0] rvfi_mem_rmask,
+	output [ 3:0] rvfi_mem_wmask,
+	output [31:0] rvfi_mem_rdata,
+	output [31:0] rvfi_mem_wdata,
+`endif
+
+	// Trace Interface
+	output        trace_valid,
+	output [35:0] trace_data
+);
+	wire        mem_valid;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [ 3:0] mem_wstrb;
+	wire        mem_instr;
+	wire        mem_ready;
+	wire [31:0] mem_rdata;
+
+	picorv32_axi_adapter axi_adapter (
+		.clk            (clk            ),
+		.resetn         (resetn         ),
+		.mem_axi_awvalid(mem_axi_awvalid),
+		.mem_axi_awready(mem_axi_awready),
+		.mem_axi_awaddr (mem_axi_awaddr ),
+		.mem_axi_awprot (mem_axi_awprot ),
+		.mem_axi_wvalid (mem_axi_wvalid ),
+		.mem_axi_wready (mem_axi_wready ),
+		.mem_axi_wdata  (mem_axi_wdata  ),
+		.mem_axi_wstrb  (mem_axi_wstrb  ),
+		.mem_axi_bvalid (mem_axi_bvalid ),
+		.mem_axi_bready (mem_axi_bready ),
+		.mem_axi_arvalid(mem_axi_arvalid),
+		.mem_axi_arready(mem_axi_arready),
+		.mem_axi_araddr (mem_axi_araddr ),
+		.mem_axi_arprot (mem_axi_arprot ),
+		.mem_axi_rvalid (mem_axi_rvalid ),
+		.mem_axi_rready (mem_axi_rready ),
+		.mem_axi_rdata  (mem_axi_rdata  ),
+		.mem_valid      (mem_valid      ),
+		.mem_instr      (mem_instr      ),
+		.mem_ready      (mem_ready      ),
+		.mem_addr       (mem_addr       ),
+		.mem_wdata      (mem_wdata      ),
+		.mem_wstrb      (mem_wstrb      ),
+		.mem_rdata      (mem_rdata      )
+	);
+
+	picorv32 #(
+		.ENABLE_COUNTERS     (ENABLE_COUNTERS     ),
+		.ENABLE_COUNTERS64   (ENABLE_COUNTERS64   ),
+		.ENABLE_REGS_16_31   (ENABLE_REGS_16_31   ),
+		.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+		.TWO_STAGE_SHIFT     (TWO_STAGE_SHIFT     ),
+		.BARREL_SHIFTER      (BARREL_SHIFTER      ),
+		.TWO_CYCLE_COMPARE   (TWO_CYCLE_COMPARE   ),
+		.TWO_CYCLE_ALU       (TWO_CYCLE_ALU       ),
+		.COMPRESSED_ISA      (COMPRESSED_ISA      ),
+		.CATCH_MISALIGN      (CATCH_MISALIGN      ),
+		.CATCH_ILLINSN       (CATCH_ILLINSN       ),
+		.ENABLE_PCPI         (ENABLE_PCPI         ),
+		.ENABLE_MUL          (ENABLE_MUL          ),
+		.ENABLE_FAST_MUL     (ENABLE_FAST_MUL     ),
+		.ENABLE_DIV          (ENABLE_DIV          ),
+		.ENABLE_IRQ          (ENABLE_IRQ          ),
+		.ENABLE_IRQ_QREGS    (ENABLE_IRQ_QREGS    ),
+		.ENABLE_IRQ_TIMER    (ENABLE_IRQ_TIMER    ),
+		.ENABLE_TRACE        (ENABLE_TRACE        ),
+		.REGS_INIT_ZERO      (REGS_INIT_ZERO      ),
+		.MASKED_IRQ          (MASKED_IRQ          ),
+		.LATCHED_IRQ         (LATCHED_IRQ         ),
+		.PROGADDR_RESET      (PROGADDR_RESET      ),
+		.PROGADDR_IRQ        (PROGADDR_IRQ        ),
+		.STACKADDR           (STACKADDR           )
+	) picorv32_core (
+		.clk      (clk   ),
+		.resetn   (resetn),
+		.trap     (trap  ),
+
+		.mem_valid(mem_valid),
+		.mem_addr (mem_addr ),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_instr(mem_instr),
+		.mem_ready(mem_ready),
+		.mem_rdata(mem_rdata),
+
+		.pcpi_valid(pcpi_valid),
+		.pcpi_insn (pcpi_insn ),
+		.pcpi_rs1  (pcpi_rs1  ),
+		.pcpi_rs2  (pcpi_rs2  ),
+		.pcpi_wr   (pcpi_wr   ),
+		.pcpi_rd   (pcpi_rd   ),
+		.pcpi_wait (pcpi_wait ),
+		.pcpi_ready(pcpi_ready),
+
+		.irq(irq),
+		.eoi(eoi),
+
+`ifdef RISCV_FORMAL
+		.rvfi_valid    (rvfi_valid    ),
+		.rvfi_order    (rvfi_order    ),
+		.rvfi_insn     (rvfi_insn     ),
+		.rvfi_trap     (rvfi_trap     ),
+		.rvfi_halt     (rvfi_halt     ),
+		.rvfi_intr     (rvfi_intr     ),
+		.rvfi_rs1_addr (rvfi_rs1_addr ),
+		.rvfi_rs2_addr (rvfi_rs2_addr ),
+		.rvfi_rs1_rdata(rvfi_rs1_rdata),
+		.rvfi_rs2_rdata(rvfi_rs2_rdata),
+		.rvfi_rd_addr  (rvfi_rd_addr  ),
+		.rvfi_rd_wdata (rvfi_rd_wdata ),
+		.rvfi_pc_rdata (rvfi_pc_rdata ),
+		.rvfi_pc_wdata (rvfi_pc_wdata ),
+		.rvfi_mem_addr (rvfi_mem_addr ),
+		.rvfi_mem_rmask(rvfi_mem_rmask),
+		.rvfi_mem_wmask(rvfi_mem_wmask),
+		.rvfi_mem_rdata(rvfi_mem_rdata),
+		.rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+		.trace_valid(trace_valid),
+		.trace_data (trace_data)
+	);
+endmodule
+
+
+/***************************************************************
+ * picorv32_axi_adapter
+ ***************************************************************/
+
+module picorv32_axi_adapter (
+	input clk, resetn,
+
+	// AXI4-lite master memory interface
+
+	output        mem_axi_awvalid,
+	input         mem_axi_awready,
+	output [31:0] mem_axi_awaddr,
+	output [ 2:0] mem_axi_awprot,
+
+	output        mem_axi_wvalid,
+	input         mem_axi_wready,
+	output [31:0] mem_axi_wdata,
+	output [ 3:0] mem_axi_wstrb,
+
+	input         mem_axi_bvalid,
+	output        mem_axi_bready,
+
+	output        mem_axi_arvalid,
+	input         mem_axi_arready,
+	output [31:0] mem_axi_araddr,
+	output [ 2:0] mem_axi_arprot,
+
+	input         mem_axi_rvalid,
+	output        mem_axi_rready,
+	input  [31:0] mem_axi_rdata,
+
+	// Native PicoRV32 memory interface
+
+	input         mem_valid,
+	input         mem_instr,
+	output        mem_ready,
+	input  [31:0] mem_addr,
+	input  [31:0] mem_wdata,
+	input  [ 3:0] mem_wstrb,
+	output [31:0] mem_rdata
+);
+	reg ack_awvalid;
+	reg ack_arvalid;
+	reg ack_wvalid;
+	reg xfer_done;
+
+	assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid;
+	assign mem_axi_awaddr = mem_addr;
+	assign mem_axi_awprot = 0;
+
+	assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid;
+	assign mem_axi_araddr = mem_addr;
+	assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000;
+
+	assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid;
+	assign mem_axi_wdata = mem_wdata;
+	assign mem_axi_wstrb = mem_wstrb;
+
+	assign mem_ready = mem_axi_bvalid || mem_axi_rvalid;
+	assign mem_axi_bready = mem_valid && |mem_wstrb;
+	assign mem_axi_rready = mem_valid && !mem_wstrb;
+	assign mem_rdata = mem_axi_rdata;
+
+	always @(posedge clk) begin
+		if (!resetn) begin
+			ack_awvalid <= 0;
+		end else begin
+			xfer_done <= mem_valid && mem_ready;
+			if (mem_axi_awready && mem_axi_awvalid)
+				ack_awvalid <= 1;
+			if (mem_axi_arready && mem_axi_arvalid)
+				ack_arvalid <= 1;
+			if (mem_axi_wready && mem_axi_wvalid)
+				ack_wvalid <= 1;
+			if (xfer_done || !mem_valid) begin
+				ack_awvalid <= 0;
+				ack_arvalid <= 0;
+				ack_wvalid <= 0;
+			end
+		end
+	end
+endmodule
+
+
+/***************************************************************
+ * picorv32_wb
+ ***************************************************************/
+
+module picorv32_wb #(
+	parameter [ 0:0] ENABLE_COUNTERS = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
+	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
+	parameter [ 0:0] TWO_STAGE_SHIFT = 1,
+	parameter [ 0:0] BARREL_SHIFTER = 0,
+	parameter [ 0:0] TWO_CYCLE_COMPARE = 0,
+	parameter [ 0:0] TWO_CYCLE_ALU = 0,
+	parameter [ 0:0] COMPRESSED_ISA = 0,
+	parameter [ 0:0] CATCH_MISALIGN = 1,
+	parameter [ 0:0] CATCH_ILLINSN = 1,
+	parameter [ 0:0] ENABLE_PCPI = 0,
+	parameter [ 0:0] ENABLE_MUL = 0,
+	parameter [ 0:0] ENABLE_FAST_MUL = 0,
+	parameter [ 0:0] ENABLE_DIV = 0,
+	parameter [ 0:0] ENABLE_IRQ = 0,
+	parameter [ 0:0] ENABLE_IRQ_QREGS = 1,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+	parameter [ 0:0] ENABLE_TRACE = 0,
+	parameter [ 0:0] REGS_INIT_ZERO = 0,
+	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
+	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
+	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010,
+	parameter [31:0] STACKADDR = 32'h ffff_ffff
+) (
+	output trap,
+
+	// Wishbone interfaces
+	input wb_rst_i,
+	input wb_clk_i,
+
+	output reg [31:0] wbm_adr_o,
+	output reg [31:0] wbm_dat_o,
+	input [31:0] wbm_dat_i,
+	output reg wbm_we_o,
+	output reg [3:0] wbm_sel_o,
+	output reg wbm_stb_o,
+	input wbm_ack_i,
+	output reg wbm_cyc_o,
+
+	// Pico Co-Processor Interface (PCPI)
+	output        pcpi_valid,
+	output [31:0] pcpi_insn,
+	output [31:0] pcpi_rs1,
+	output [31:0] pcpi_rs2,
+	input         pcpi_wr,
+	input  [31:0] pcpi_rd,
+	input         pcpi_wait,
+	input         pcpi_ready,
+
+	// IRQ interface
+	input  [31:0] irq,
+	output [31:0] eoi,
+
+`ifdef RISCV_FORMAL
+	output        rvfi_valid,
+	output [63:0] rvfi_order,
+	output [31:0] rvfi_insn,
+	output        rvfi_trap,
+	output        rvfi_halt,
+	output        rvfi_intr,
+	output [ 4:0] rvfi_rs1_addr,
+	output [ 4:0] rvfi_rs2_addr,
+	output [31:0] rvfi_rs1_rdata,
+	output [31:0] rvfi_rs2_rdata,
+	output [ 4:0] rvfi_rd_addr,
+	output [31:0] rvfi_rd_wdata,
+	output [31:0] rvfi_pc_rdata,
+	output [31:0] rvfi_pc_wdata,
+	output [31:0] rvfi_mem_addr,
+	output [ 3:0] rvfi_mem_rmask,
+	output [ 3:0] rvfi_mem_wmask,
+	output [31:0] rvfi_mem_rdata,
+	output [31:0] rvfi_mem_wdata,
+`endif
+
+	// Trace Interface
+	output        trace_valid,
+	output [35:0] trace_data,
+
+	output mem_instr
+);
+	wire        mem_valid;
+	wire [31:0] mem_addr;
+	wire [31:0] mem_wdata;
+	wire [ 3:0] mem_wstrb;
+	reg         mem_ready;
+	reg [31:0] mem_rdata;
+
+	wire clk;
+	wire resetn;
+
+	assign clk = wb_clk_i;
+	assign resetn = ~wb_rst_i;
+
+	picorv32 #(
+		.ENABLE_COUNTERS     (ENABLE_COUNTERS     ),
+		.ENABLE_COUNTERS64   (ENABLE_COUNTERS64   ),
+		.ENABLE_REGS_16_31   (ENABLE_REGS_16_31   ),
+		.ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT),
+		.TWO_STAGE_SHIFT     (TWO_STAGE_SHIFT     ),
+		.BARREL_SHIFTER      (BARREL_SHIFTER      ),
+		.TWO_CYCLE_COMPARE   (TWO_CYCLE_COMPARE   ),
+		.TWO_CYCLE_ALU       (TWO_CYCLE_ALU       ),
+		.COMPRESSED_ISA      (COMPRESSED_ISA      ),
+		.CATCH_MISALIGN      (CATCH_MISALIGN      ),
+		.CATCH_ILLINSN       (CATCH_ILLINSN       ),
+		.ENABLE_PCPI         (ENABLE_PCPI         ),
+		.ENABLE_MUL          (ENABLE_MUL          ),
+		.ENABLE_FAST_MUL     (ENABLE_FAST_MUL     ),
+		.ENABLE_DIV          (ENABLE_DIV          ),
+		.ENABLE_IRQ          (ENABLE_IRQ          ),
+		.ENABLE_IRQ_QREGS    (ENABLE_IRQ_QREGS    ),
+		.ENABLE_IRQ_TIMER    (ENABLE_IRQ_TIMER    ),
+		.ENABLE_TRACE        (ENABLE_TRACE        ),
+		.REGS_INIT_ZERO      (REGS_INIT_ZERO      ),
+		.MASKED_IRQ          (MASKED_IRQ          ),
+		.LATCHED_IRQ         (LATCHED_IRQ         ),
+		.PROGADDR_RESET      (PROGADDR_RESET      ),
+		.PROGADDR_IRQ        (PROGADDR_IRQ        ),
+		.STACKADDR           (STACKADDR           )
+	) picorv32_core (
+		.clk      (clk   ),
+		.resetn   (resetn),
+		.trap     (trap  ),
+
+		.mem_valid(mem_valid),
+		.mem_addr (mem_addr ),
+		.mem_wdata(mem_wdata),
+		.mem_wstrb(mem_wstrb),
+		.mem_instr(mem_instr),
+		.mem_ready(mem_ready),
+		.mem_rdata(mem_rdata),
+
+		.pcpi_valid(pcpi_valid),
+		.pcpi_insn (pcpi_insn ),
+		.pcpi_rs1  (pcpi_rs1  ),
+		.pcpi_rs2  (pcpi_rs2  ),
+		.pcpi_wr   (pcpi_wr   ),
+		.pcpi_rd   (pcpi_rd   ),
+		.pcpi_wait (pcpi_wait ),
+		.pcpi_ready(pcpi_ready),
+
+		.irq(irq),
+		.eoi(eoi),
+
+`ifdef RISCV_FORMAL
+		.rvfi_valid    (rvfi_valid    ),
+		.rvfi_order    (rvfi_order    ),
+		.rvfi_insn     (rvfi_insn     ),
+		.rvfi_trap     (rvfi_trap     ),
+		.rvfi_halt     (rvfi_halt     ),
+		.rvfi_intr     (rvfi_intr     ),
+		.rvfi_rs1_addr (rvfi_rs1_addr ),
+		.rvfi_rs2_addr (rvfi_rs2_addr ),
+		.rvfi_rs1_rdata(rvfi_rs1_rdata),
+		.rvfi_rs2_rdata(rvfi_rs2_rdata),
+		.rvfi_rd_addr  (rvfi_rd_addr  ),
+		.rvfi_rd_wdata (rvfi_rd_wdata ),
+		.rvfi_pc_rdata (rvfi_pc_rdata ),
+		.rvfi_pc_wdata (rvfi_pc_wdata ),
+		.rvfi_mem_addr (rvfi_mem_addr ),
+		.rvfi_mem_rmask(rvfi_mem_rmask),
+		.rvfi_mem_wmask(rvfi_mem_wmask),
+		.rvfi_mem_rdata(rvfi_mem_rdata),
+		.rvfi_mem_wdata(rvfi_mem_wdata),
+`endif
+
+		.trace_valid(trace_valid),
+		.trace_data (trace_data)
+	);
+
+	localparam IDLE = 2'b00;
+	localparam WBSTART = 2'b01;
+	localparam WBEND = 2'b10;
+
+	reg [1:0] state;
+
+	wire we;
+	assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]);
+
+	always @(posedge wb_clk_i) begin
+		if (wb_rst_i) begin
+			wbm_adr_o <= 0;
+			wbm_dat_o <= 0;
+			wbm_we_o <= 0;
+			wbm_sel_o <= 0;
+			wbm_stb_o <= 0;
+			wbm_cyc_o <= 0;
+			state <= IDLE;
+		end else begin
+			case (state)
+				IDLE: begin
+					if (mem_valid) begin
+						wbm_adr_o <= mem_addr;
+						wbm_dat_o <= mem_wdata;
+						wbm_we_o <= we;
+						wbm_sel_o <= mem_wstrb;
+
+						wbm_stb_o <= 1'b1;
+						wbm_cyc_o <= 1'b1;
+						state <= WBSTART;
+					end else begin
+						mem_ready <= 1'b0;
+
+						wbm_stb_o <= 1'b0;
+						wbm_cyc_o <= 1'b0;
+						wbm_we_o <= 1'b0;
+					end
+				end
+				WBSTART:begin
+					if (wbm_ack_i) begin
+						mem_rdata <= wbm_dat_i;
+						mem_ready <= 1'b1;
+
+						state <= WBEND;
+
+						wbm_stb_o <= 1'b0;
+						wbm_cyc_o <= 1'b0;
+						wbm_we_o <= 1'b0;
+					end
+				end
+				WBEND: begin
+					mem_ready <= 1'b0;
+
+					state <= IDLE;
+				end
+				default:
+					state <= IDLE;
+			endcase
+		end
+	end
+endmodule
diff --git a/flow/designs/src/tpu/LICENSES/LogikBench-MIT.txt b/flow/designs/src/tpu/LICENSES/LogikBench-MIT.txt
new file mode 100644
index 0000000000..238c66dc4b
--- /dev/null
+++ b/flow/designs/src/tpu/LICENSES/LogikBench-MIT.txt
@@ -0,0 +1,21 @@
+The MIT License (MIT)
+
+Copyright (c) 2025 Zero ASIC Corporation
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/flow/designs/src/tpu/SOURCE.md b/flow/designs/src/tpu/SOURCE.md
new file mode 100644
index 0000000000..cdf89e64f0
--- /dev/null
+++ b/flow/designs/src/tpu/SOURCE.md
@@ -0,0 +1,11 @@
+# TPU source
+
+The TPU RTL comes from LogikBench commit
+`62fc37ec58451c7d8813d7d3e3e1d7a1377c9082` and is distributed under the MIT
+license in `LICENSES/LogikBench-MIT.txt`. The RTL files are byte-identical to
+the benchmark; only the file suffix was changed from `.v` to `.sv`.
+
+ORFS uses the RTL defaults `N=8`, `DW=8`, and `ACCW=32`. The implemented design
+is therefore an 8x8 processing-element array. The larger LogikBench `N=128`
+configuration is intentionally not used because its ABC technology-mapping
+runtime is unsuitable for a regularly exercised public flow.
diff --git a/flow/designs/src/tpu/tpu.sv b/flow/designs/src/tpu/tpu.sv
new file mode 100644
index 0000000000..7a61b1043a
--- /dev/null
+++ b/flow/designs/src/tpu/tpu.sv
@@ -0,0 +1,140 @@
+//#############################################################################
+// Copyright: Zero ASIC. All rights Reserved.
+// Author: Andreas Olofsson
+// License:  MIT (see LICENSE file in LogikBench repository)
+//#############################################################################
+//
+// Weight-stationary systolic matrix-multiply tile (a Google-TPU-style MXU).
+//
+// Computes one tile product C = A * B, where A and B are N x N signed operands
+// (DW bits) and C is N x N signed (ACCW bits). B is the "weight" matrix, loaded
+// into and held by the array; A is the "activation" matrix, streamed through; C
+// drains out the bottom. Built from a tpu_array of N x N tpu_pe cells.
+//
+// Operation has two phases the host drives via valids:
+//
+//   1. Weight load: assert w_valid for N cycles. w_data carries one weight row
+//      per cycle, N signed weights packed { col N-1 ... col 0 }. Because the
+//      array loads top-down (shift south), push the BOTTOM matrix row first:
+//      cycle k carries B[N-1-k][*]. After N cycles PE(i,j) holds B[i][j].
+//
+//   2. Compute: assert a_valid while streaming A one row per cycle, a_data
+//      packed { col N-1 ... col 0 } = A[m][N-1..0]. Row m of the result, C[m][*]
+//      (packed the same way), appears on c_data with c_valid high, 2*N-1 cycles
+//      after its A row was accepted.
+//
+// Time alignment: row i of A is delayed i cycles entering the array (input
+// skew) so partial sums chain correctly down each column; column j of the
+// result is delayed N-1-j cycles (output de-skew) so a full result row leaves
+// together. Both skew networks and the valid pipeline advance only with the
+// array (compute enable), so the 2*N-1 latency is exact. Per CLAUDE.md the skew
+// chains are generated per-row/column shift registers, not a procedural unroll.
+//
+//#############################################################################
+
+module tpu
+  #(parameter N = 8,	 // array dimension (N x N)
+    parameter DW = 8,	 // operand width (signed)
+    parameter ACCW = 32) // result / accumulator width (signed)
+   (
+    input		clk,
+    input		rst,	 // synchronous, active high
+    input		w_valid, // weight-row valid (load phase)
+    input [N*DW-1:0]	w_data,	 // weight row, packed { col N-1 ... col 0 }
+    input		a_valid, // activation-row valid (compute phase)
+    input [N*DW-1:0]	a_data,	 // activation row, packed { col N-1 ... col 0 }
+    output		c_valid, // result-row valid
+    output [N*ACCW-1:0]	c_data	 // result row, packed { col N-1 ... col 0 }
+    );
+
+   // total injection-to-output latency, in compute cycles
+   localparam LAT = 2*N - 1;
+
+   // load weights while w_valid; otherwise the array computes (and drains)
+   wire	      ld = w_valid;
+   wire	      en = ~w_valid;
+
+   //##########################################################################
+   // Input skew: row i of the activation is delayed i cycles. Zero is injected
+   // when a_valid is low so idle/drain cycles add nothing to the accumulators.
+   //##########################################################################
+   wire [N*DW-1:0] a_left;
+   genvar	   i;
+   generate
+      for (i = 0; i < N; i = i + 1) begin : g_skew
+         wire [DW-1:0] din =
+		       a_valid ? a_data[i*DW +: DW] : {DW{1'b0}};
+         if (i == 0) begin : g_skew0
+            assign a_left[i*DW +: DW] = din;
+         end
+         else begin : g_skewn
+            reg [DW-1:0] sr [0:i-1];
+            integer k;
+            always @(posedge clk) begin
+               if (rst) begin
+                  for (k = 0; k < i; k = k + 1)
+                    sr[k] <= {DW{1'b0}};
+               end
+               else if (en) begin
+                  sr[0] <= din;
+                  for (k = 1; k < i; k = k + 1)
+                    sr[k] <= sr[k-1];
+               end
+            end
+            assign a_left[i*DW +: DW] = sr[i-1];
+         end
+      end
+   endgenerate
+
+   //##########################################################################
+   // The systolic array.
+   //##########################################################################
+   wire [N*ACCW-1:0] c_bot;
+   tpu_array #(.N(N), .DW(DW), .ACCW(ACCW)) u_array
+     (.clk(clk), .rst(rst), .ld(ld), .en(en),
+      .w_top(w_data), .a_left(a_left), .c_bot(c_bot));
+
+   //##########################################################################
+   // Output de-skew: column j is delayed N-1-j cycles so all columns of a
+   // result row line up. Column N-1 (longest path) needs no delay.
+   //##########################################################################
+   genvar j;
+   generate
+      for (j = 0; j < N; j = j + 1) begin : g_deskew
+         localparam D = N - 1 - j;
+         wire [ACCW-1:0] cin = c_bot[j*ACCW +: ACCW];
+         if (D == 0) begin : g_deskew0
+            assign c_data[j*ACCW +: ACCW] = cin;
+         end
+         else begin : g_deskewn
+            reg [ACCW-1:0] dr [0:D-1];
+            integer k;
+            always @(posedge clk) begin
+               if (rst) begin
+                  for (k = 0; k < D; k = k + 1)
+                    dr[k] <= {ACCW{1'b0}};
+               end
+               else if (en) begin
+                  dr[0] <= cin;
+                  for (k = 1; k < D; k = k + 1)
+                    dr[k] <= dr[k-1];
+               end
+            end
+            assign c_data[j*ACCW +: ACCW] = dr[D-1];
+         end
+      end
+   endgenerate
+
+   //##########################################################################
+   // Valid pipeline: c_valid is a_valid delayed LAT compute cycles.
+   //##########################################################################
+   reg [LAT-1:0] vpipe;
+   always @(posedge clk) begin
+      if (rst)
+        vpipe <= {LAT{1'b0}};
+      else if (en)
+        vpipe <= {vpipe[LAT-2:0], a_valid};
+   end
+   assign c_valid = vpipe[LAT-1];
+
+endmodule
diff --git a/flow/designs/src/tpu/tpu_array.sv b/flow/designs/src/tpu/tpu_array.sv
new file mode 100644
index 0000000000..c053af110e
--- /dev/null
+++ b/flow/designs/src/tpu/tpu_array.sv
@@ -0,0 +1,76 @@
+//#############################################################################
+// Copyright: Zero ASIC. All rights Reserved.
+// Author: Andreas Olofsson
+// License:  MIT (see LICENSE file in LogikBench repository)
+//#############################################################################
+//
+// N x N weight-stationary systolic array (the TPU MXU core).
+//
+// One tpu_pe per grid element, wired as a 2D mesh (per CLAUDE.md: replicated
+// hardware via generate, never a procedural unroll):
+//
+//   - weights load from the top: w_top[j] feeds column j; each column is a
+//     vertical shift register (w_south of PE(i,j) -> w_north of PE(i+1,j)).
+//   - activations flow west to east: a_left[i] enters row i; a_east of PE(i,j)
+//     feeds a_west of PE(i,j+1).
+//   - partial sums flow north to south and accumulate; the top row's psum_north
+//     is tied to zero (fresh accumulation), and c_bot[j] is the column-j result
+//     leaving the bottom row.
+//
+// With weight B[i][j] held at PE(i,j) and activation A[m][i] entering row i,
+// column j computes C[m][j] = sum_i A[m][i] * B[i][j]. Input/output skew (which
+// time-aligns rows and columns) lives in the tpu top, not here.
+//
+//#############################################################################
+
+module tpu_array
+  #(parameter N = 8,	 // array dimension (N x N PEs)
+    parameter DW = 8,	 // operand width (signed)
+    parameter ACCW = 32) // accumulator width (signed)
+   (
+    input		clk,
+    input		rst,	// synchronous, active high
+    input		ld,	// weight-load shift enable
+    input		en,	// compute enable
+    input [N*DW-1:0]	w_top,	// weight inputs, one per column (load)
+    input [N*DW-1:0]	a_left,	// activation inputs, one per row
+    output [N*ACCW-1:0]	c_bot	// column results, one per column
+    );
+
+   // mesh nets: a_h carries activations east, psum_v carries sums south,
+   // w_v carries weights south during load.
+   wire [DW-1:0]   a_h    [0:N-1][0:N];
+   wire [ACCW-1:0] psum_v [0:N][0:N-1];
+   wire [DW-1:0]   w_v    [0:N][0:N-1];
+
+   genvar	   i, j;
+   generate
+      // west edge: activation inputs into column 0 of each row
+      for (i = 0; i < N; i = i + 1) begin : g_west
+         assign a_h[i][0] = a_left[i*DW +: DW];
+      end
+      // top edge: zero partial sums, weight inputs; bottom edge: results out
+      for (j = 0; j < N; j = j + 1) begin : g_edge
+         assign psum_v[0][j] = {ACCW{1'b0}};
+         assign w_v[0][j]    = w_top[j*DW +: DW];
+         assign c_bot[j*ACCW +: ACCW] = psum_v[N][j];
+      end
+      // the PE mesh
+      for (i = 0; i < N; i = i + 1) begin : g_pe_row
+         for (j = 0; j < N; j = j + 1) begin : g_pe_col
+            tpu_pe #(.DW(DW), .ACCW(ACCW)) u_pe
+              (.clk        (clk),
+               .rst        (rst),
+               .ld         (ld),
+               .en         (en),
+               .w_north    (w_v[i][j]),
+               .a_west     (a_h[i][j]),
+               .psum_north (psum_v[i][j]),
+               .w_south    (w_v[i+1][j]),
+               .a_east     (a_h[i][j+1]),
+               .psum_south (psum_v[i+1][j]));
+         end
+      end
+   endgenerate
+
+endmodule
diff --git a/flow/designs/src/tpu/tpu_pe.sv b/flow/designs/src/tpu/tpu_pe.sv
new file mode 100644
index 0000000000..9d9e2fc8b3
--- /dev/null
+++ b/flow/designs/src/tpu/tpu_pe.sv
@@ -0,0 +1,66 @@
+//#############################################################################
+// Copyright: Zero ASIC. All rights Reserved.
+// Author: Andreas Olofsson
+// License:  MIT (see LICENSE file in LogikBench repository)
+//#############################################################################
+//
+// Processing element (PE) for the weight-stationary systolic array (TPU MXU).
+//
+// Each PE holds one stationary signed weight 'w'. Two independent datapaths
+// share the cell:
+//
+//   Weight load (ld): the weights form a per-column shift register that loads
+//   from the top. On each ld cycle the PE captures the weight from the PE above
+//   (w_north) and presents its stored weight downward (w_south). After N load
+//   cycles every PE in a column holds its final stationary weight.
+//
+//   Compute (en): the activation flows west to east (registered, one hop per
+//   cycle) and the partial sum flows north to south, accumulating the local
+//   product a_west * w. This is the only arithmetic cell in the array: one
+//   signed DW x DW multiply plus an ACCW-bit add.
+//
+//#############################################################################
+
+module tpu_pe
+  #(parameter DW = 8,	 // operand width (signed)
+    parameter ACCW = 32) // accumulator / partial-sum width (signed)
+   (
+    input		  clk,
+    input		  rst,	      // synchronous, active high
+    input		  ld,	      // weight-load shift enable
+    input		  en,	      // compute enable
+    input [DW-1:0]	  w_north,    // weight in from PE above
+    input [DW-1:0]	  a_west,     // activation in from west
+    input [ACCW-1:0]	  psum_north, // partial sum in from above
+    output [DW-1:0]	  w_south,    // stored weight out to PE below
+    output reg [DW-1:0]	  a_east,     // activation out to east
+    output reg [ACCW-1:0] psum_south  // partial sum out to below
+    );
+
+   // stationary weight register; presented downward for the load shift chain
+   reg [DW-1:0] w;
+   assign w_south = w;
+
+   // local product: the ONLY signed operation. Operands are interpreted as
+   // signed here via $signed; the 2*DW-bit result holds the two's-complement
+   // product, which is then sign-extended to the accumulator width below.
+   wire [2*DW-1:0] prod = $signed(a_west) * $signed(w);
+
+   always @(posedge clk) begin
+      if (rst) begin
+         w          <= {DW{1'b0}};
+         a_east     <= {DW{1'b0}};
+         psum_south <= {ACCW{1'b0}};
+      end
+      else begin
+         if (ld)
+           w <= w_north;
+         if (en) begin
+            a_east     <= a_west;
+            psum_south <= psum_north +
+                          {{(ACCW-2*DW){prod[2*DW-1]}}, prod};
+         end
+      end
+   end
+
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/CoupledL2.sv b/flow/designs/src/xiangshan_coupledl2/CoupledL2.sv
new file mode 100644
index 0000000000..b9cae73897
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/CoupledL2.sv
@@ -0,0 +1,2265 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module CoupledL2(
+  input          clock,
+  input          reset,
+  output         auto_mmioBridge_mmio_in_a_ready,
+  input          auto_mmioBridge_mmio_in_a_valid,
+  input  [3:0]   auto_mmioBridge_mmio_in_a_bits_opcode,
+  input  [2:0]   auto_mmioBridge_mmio_in_a_bits_param,
+  input  [1:0]   auto_mmioBridge_mmio_in_a_bits_size,
+  input  [4:0]   auto_mmioBridge_mmio_in_a_bits_source,
+  input  [47:0]  auto_mmioBridge_mmio_in_a_bits_address,
+  input          auto_mmioBridge_mmio_in_a_bits_user_memBackType_MM,
+  input          auto_mmioBridge_mmio_in_a_bits_user_memPageType_NC,
+  input  [7:0]   auto_mmioBridge_mmio_in_a_bits_mask,
+  input  [63:0]  auto_mmioBridge_mmio_in_a_bits_data,
+  input          auto_mmioBridge_mmio_in_a_bits_corrupt,
+  input          auto_mmioBridge_mmio_in_d_ready,
+  output         auto_mmioBridge_mmio_in_d_valid,
+  output [3:0]   auto_mmioBridge_mmio_in_d_bits_opcode,
+  output [1:0]   auto_mmioBridge_mmio_in_d_bits_param,
+  output [1:0]   auto_mmioBridge_mmio_in_d_bits_size,
+  output [4:0]   auto_mmioBridge_mmio_in_d_bits_source,
+  output         auto_mmioBridge_mmio_in_d_bits_sink,
+  output         auto_mmioBridge_mmio_in_d_bits_denied,
+  output [63:0]  auto_mmioBridge_mmio_in_d_bits_data,
+  output         auto_mmioBridge_mmio_in_d_bits_corrupt,
+  output         auto_in_a_ready,
+  input          auto_in_a_valid,
+  input  [3:0]   auto_in_a_bits_opcode,
+  input  [2:0]   auto_in_a_bits_param,
+  input  [2:0]   auto_in_a_bits_size,
+  input  [6:0]   auto_in_a_bits_source,
+  input  [47:0]  auto_in_a_bits_address,
+  input  [4:0]   auto_in_a_bits_user_reqSource,
+  input          auto_in_a_bits_user_alias,
+  input  [43:0]  auto_in_a_bits_user_vaddr,
+  input          auto_in_a_bits_user_needHint,
+  input          auto_in_a_bits_echo_isKeyword,
+  input          auto_in_a_bits_corrupt,
+  input          auto_in_b_ready,
+  output         auto_in_b_valid,
+  output [2:0]   auto_in_b_bits_opcode,
+  output [1:0]   auto_in_b_bits_param,
+  output [47:0]  auto_in_b_bits_address,
+  output [255:0] auto_in_b_bits_data,
+  output         auto_in_c_ready,
+  input          auto_in_c_valid,
+  input  [2:0]   auto_in_c_bits_opcode,
+  input  [2:0]   auto_in_c_bits_param,
+  input  [2:0]   auto_in_c_bits_size,
+  input  [6:0]   auto_in_c_bits_source,
+  input  [47:0]  auto_in_c_bits_address,
+  input  [255:0] auto_in_c_bits_data,
+  input          auto_in_c_bits_corrupt,
+  input          auto_in_d_ready,
+  output         auto_in_d_valid,
+  output [3:0]   auto_in_d_bits_opcode,
+  output [1:0]   auto_in_d_bits_param,
+  output [6:0]   auto_in_d_bits_source,
+  output [7:0]   auto_in_d_bits_sink,
+  output         auto_in_d_bits_denied,
+  output         auto_in_d_bits_echo_isKeyword,
+  output [255:0] auto_in_d_bits_data,
+  output         auto_in_d_bits_corrupt,
+  input          auto_in_e_valid,
+  input  [7:0]   auto_in_e_bits_sink,
+  input          io_pfCtrlFromCore_l2_pf_master_en,
+  input          io_pfCtrlFromCore_l2_pbop_en,
+  input          io_pfCtrlFromCore_l2_vbop_en,
+  input  [9:0]   io_pfCtrlFromCore_l2_pf_delay_latency,
+  output         io_l2_hint_valid,
+  output [6:0]   io_l2_hint_bits_sourceId,
+  output         io_l2_hint_bits_isKeyword,
+  output         io_l2_tlb_req_req_valid,
+  output [49:0]  io_l2_tlb_req_req_bits_vaddr,
+  input          io_l2_tlb_req_resp_valid,
+  input  [47:0]  io_l2_tlb_req_resp_bits_paddr_0,
+  input  [1:0]   io_l2_tlb_req_resp_bits_pbmt,
+  input          io_l2_tlb_req_resp_bits_miss,
+  input          io_l2_tlb_req_resp_bits_excp_0_gpf_ld,
+  input          io_l2_tlb_req_resp_bits_excp_0_pf_ld,
+  input          io_l2_tlb_req_resp_bits_excp_0_af_ld,
+  input          io_l2_tlb_req_pmp_resp_ld,
+  input          io_l2_tlb_req_pmp_resp_mmio,
+  output         io_l2Miss,
+  output         io_error_valid,
+  output [47:0]  io_error_address,
+  input          io_dft_ram_hold,
+  input          io_dft_ram_bypass,
+  input          io_dft_ram_bp_clken,
+  input          io_dft_ram_aux_clk,
+  input          io_dft_ram_aux_ckbp,
+  input          io_dft_ram_mcp_hold,
+  input          io_dft_cgen,
+  output         io_chi_txsactive,
+  input          io_chi_rxsactive,
+  output         io_chi_syscoreq,
+  input          io_chi_syscoack,
+  output         io_chi_tx_linkactivereq,
+  input          io_chi_tx_linkactiveack,
+  output         io_chi_tx_req_flitpend,
+  output         io_chi_tx_req_flitv,
+  output [161:0] io_chi_tx_req_flit,
+  input          io_chi_tx_req_lcrdv,
+  output         io_chi_tx_rsp_flitpend,
+  output         io_chi_tx_rsp_flitv,
+  output [72:0]  io_chi_tx_rsp_flit,
+  input          io_chi_tx_rsp_lcrdv,
+  output         io_chi_tx_dat_flitpend,
+  output         io_chi_tx_dat_flitv,
+  output [421:0] io_chi_tx_dat_flit,
+  input          io_chi_tx_dat_lcrdv,
+  input          io_chi_rx_linkactivereq,
+  output         io_chi_rx_linkactiveack,
+  input          io_chi_rx_rsp_flitpend,
+  input          io_chi_rx_rsp_flitv,
+  input  [72:0]  io_chi_rx_rsp_flit,
+  output         io_chi_rx_rsp_lcrdv,
+  input          io_chi_rx_dat_flitpend,
+  input          io_chi_rx_dat_flitv,
+  input  [421:0] io_chi_rx_dat_flit,
+  output         io_chi_rx_dat_lcrdv,
+  input          io_chi_rx_snp_flitpend,
+  input          io_chi_rx_snp_flitv,
+  input  [114:0] io_chi_rx_snp_flit,
+  output         io_chi_rx_snp_lcrdv,
+  input  [10:0]  io_nodeID,
+  output [5:0]   io_perf_1_value,
+  output [5:0]   io_perf_2_value,
+  output [5:0]   io_perf_4_value,
+  output [5:0]   io_perf_5_value,
+  output [5:0]   io_perf_6_value,
+  output [5:0]   io_perf_7_value,
+  output [5:0]   io_perf_8_value,
+  output [5:0]   io_perf_9_value,
+  output [5:0]   io_perf_10_value,
+  output [5:0]   io_perf_11_value,
+  output [5:0]   io_perf_12_value,
+  output [5:0]   io_perf_13_value,
+  output [5:0]   io_perf_14_value,
+  output [5:0]   io_perf_15_value,
+  output [5:0]   io_perf_16_value,
+  output [5:0]   io_perf_17_value
+);
+
+  wire [163:0] childBd_1_outdata;
+  wire         childBd_1_ack;
+  wire [12:0]  childBd_outdata;
+  wire         childBd_ack;
+  reg          master_ready_REG_2;
+  reg          master_ready_REG_1;
+  reg          master_ready_REG;
+  wire [3:0]   _l2MbistIntf_toPipeline_0_array;
+  wire         _l2MbistIntf_toPipeline_0_all;
+  wire         _l2MbistIntf_toPipeline_0_req;
+  wire         _l2MbistIntf_toPipeline_0_writeen;
+  wire [7:0]   _l2MbistIntf_toPipeline_0_be;
+  wire [11:0]  _l2MbistIntf_toPipeline_0_addr;
+  wire [163:0] _l2MbistIntf_toPipeline_0_indata;
+  wire         _l2MbistIntf_toPipeline_0_readen;
+  wire [11:0]  _l2MbistIntf_toPipeline_0_addr_rd;
+  wire         _mbistPl_mbist_ack;
+  wire [163:0] _mbistPl_mbist_outdata;
+  wire         _l2ECCArb_io_out_valid;
+  wire         _l2ECCArb_io_out_bits_valid;
+  wire         _rxrspPipe_pipeline_io_in_ready;
+  wire         _rxrspPipe_pipeline_io_out_valid;
+  wire [3:0]   _rxrspPipe_pipeline_io_out_bits_qos;
+  wire [10:0]  _rxrspPipe_pipeline_io_out_bits_tgtID;
+  wire [10:0]  _rxrspPipe_pipeline_io_out_bits_srcID;
+  wire [11:0]  _rxrspPipe_pipeline_io_out_bits_txnID;
+  wire [4:0]   _rxrspPipe_pipeline_io_out_bits_opcode;
+  wire [1:0]   _rxrspPipe_pipeline_io_out_bits_respErr;
+  wire [2:0]   _rxrspPipe_pipeline_io_out_bits_resp;
+  wire [2:0]   _rxrspPipe_pipeline_io_out_bits_fwdState;
+  wire [2:0]   _rxrspPipe_pipeline_io_out_bits_cBusy;
+  wire [11:0]  _rxrspPipe_pipeline_io_out_bits_dbID;
+  wire [3:0]   _rxrspPipe_pipeline_io_out_bits_pCrdType;
+  wire [1:0]   _rxrspPipe_pipeline_io_out_bits_tagOp;
+  wire         _rxrspPipe_pipeline_io_out_bits_traceTag;
+  wire         _rxdatPipe_pipeline_io_in_ready;
+  wire         _rxdatPipe_pipeline_io_out_valid;
+  wire [3:0]   _rxdatPipe_pipeline_io_out_bits_qos;
+  wire [10:0]  _rxdatPipe_pipeline_io_out_bits_tgtID;
+  wire [10:0]  _rxdatPipe_pipeline_io_out_bits_srcID;
+  wire [11:0]  _rxdatPipe_pipeline_io_out_bits_txnID;
+  wire [10:0]  _rxdatPipe_pipeline_io_out_bits_homeNID;
+  wire [3:0]   _rxdatPipe_pipeline_io_out_bits_opcode;
+  wire [1:0]   _rxdatPipe_pipeline_io_out_bits_respErr;
+  wire [2:0]   _rxdatPipe_pipeline_io_out_bits_resp;
+  wire [3:0]   _rxdatPipe_pipeline_io_out_bits_dataSource;
+  wire [2:0]   _rxdatPipe_pipeline_io_out_bits_cBusy;
+  wire [11:0]  _rxdatPipe_pipeline_io_out_bits_dbID;
+  wire [1:0]   _rxdatPipe_pipeline_io_out_bits_ccID;
+  wire [1:0]   _rxdatPipe_pipeline_io_out_bits_dataID;
+  wire [1:0]   _rxdatPipe_pipeline_io_out_bits_tagOp;
+  wire [7:0]   _rxdatPipe_pipeline_io_out_bits_tag;
+  wire [1:0]   _rxdatPipe_pipeline_io_out_bits_tu;
+  wire         _rxdatPipe_pipeline_io_out_bits_traceTag;
+  wire [3:0]   _rxdatPipe_pipeline_io_out_bits_rsvdc;
+  wire [31:0]  _rxdatPipe_pipeline_io_out_bits_be;
+  wire [255:0] _rxdatPipe_pipeline_io_out_bits_data;
+  wire [31:0]  _rxdatPipe_pipeline_io_out_bits_dataCheck;
+  wire [3:0]   _rxdatPipe_pipeline_io_out_bits_poison;
+  wire         _linkMonitor_io_in_tx_req_ready;
+  wire         _linkMonitor_io_in_tx_rsp_ready;
+  wire         _linkMonitor_io_in_tx_dat_ready;
+  wire         _linkMonitor_io_in_rx_rsp_valid;
+  wire [3:0]   _linkMonitor_io_in_rx_rsp_bits_qos;
+  wire [10:0]  _linkMonitor_io_in_rx_rsp_bits_tgtID;
+  wire [10:0]  _linkMonitor_io_in_rx_rsp_bits_srcID;
+  wire [11:0]  _linkMonitor_io_in_rx_rsp_bits_txnID;
+  wire [4:0]   _linkMonitor_io_in_rx_rsp_bits_opcode;
+  wire [1:0]   _linkMonitor_io_in_rx_rsp_bits_respErr;
+  wire [2:0]   _linkMonitor_io_in_rx_rsp_bits_resp;
+  wire [2:0]   _linkMonitor_io_in_rx_rsp_bits_fwdState;
+  wire [2:0]   _linkMonitor_io_in_rx_rsp_bits_cBusy;
+  wire [11:0]  _linkMonitor_io_in_rx_rsp_bits_dbID;
+  wire [3:0]   _linkMonitor_io_in_rx_rsp_bits_pCrdType;
+  wire [1:0]   _linkMonitor_io_in_rx_rsp_bits_tagOp;
+  wire         _linkMonitor_io_in_rx_rsp_bits_traceTag;
+  wire         _linkMonitor_io_in_rx_dat_valid;
+  wire [3:0]   _linkMonitor_io_in_rx_dat_bits_qos;
+  wire [10:0]  _linkMonitor_io_in_rx_dat_bits_tgtID;
+  wire [10:0]  _linkMonitor_io_in_rx_dat_bits_srcID;
+  wire [11:0]  _linkMonitor_io_in_rx_dat_bits_txnID;
+  wire [10:0]  _linkMonitor_io_in_rx_dat_bits_homeNID;
+  wire [3:0]   _linkMonitor_io_in_rx_dat_bits_opcode;
+  wire [1:0]   _linkMonitor_io_in_rx_dat_bits_respErr;
+  wire [2:0]   _linkMonitor_io_in_rx_dat_bits_resp;
+  wire [3:0]   _linkMonitor_io_in_rx_dat_bits_dataSource;
+  wire [2:0]   _linkMonitor_io_in_rx_dat_bits_cBusy;
+  wire [11:0]  _linkMonitor_io_in_rx_dat_bits_dbID;
+  wire [1:0]   _linkMonitor_io_in_rx_dat_bits_ccID;
+  wire [1:0]   _linkMonitor_io_in_rx_dat_bits_dataID;
+  wire [1:0]   _linkMonitor_io_in_rx_dat_bits_tagOp;
+  wire [7:0]   _linkMonitor_io_in_rx_dat_bits_tag;
+  wire [1:0]   _linkMonitor_io_in_rx_dat_bits_tu;
+  wire         _linkMonitor_io_in_rx_dat_bits_traceTag;
+  wire [3:0]   _linkMonitor_io_in_rx_dat_bits_rsvdc;
+  wire [31:0]  _linkMonitor_io_in_rx_dat_bits_be;
+  wire [255:0] _linkMonitor_io_in_rx_dat_bits_data;
+  wire [31:0]  _linkMonitor_io_in_rx_dat_bits_dataCheck;
+  wire [3:0]   _linkMonitor_io_in_rx_dat_bits_poison;
+  wire         _linkMonitor_io_in_rx_snp_valid;
+  wire [3:0]   _linkMonitor_io_in_rx_snp_bits_qos;
+  wire [10:0]  _linkMonitor_io_in_rx_snp_bits_srcID;
+  wire [11:0]  _linkMonitor_io_in_rx_snp_bits_txnID;
+  wire [10:0]  _linkMonitor_io_in_rx_snp_bits_fwdNID;
+  wire [11:0]  _linkMonitor_io_in_rx_snp_bits_fwdTxnID;
+  wire [4:0]   _linkMonitor_io_in_rx_snp_bits_opcode;
+  wire [44:0]  _linkMonitor_io_in_rx_snp_bits_addr;
+  wire         _linkMonitor_io_in_rx_snp_bits_ns;
+  wire         _linkMonitor_io_in_rx_snp_bits_doNotGoToSD;
+  wire         _linkMonitor_io_in_rx_snp_bits_retToSrc;
+  wire         _linkMonitor_io_in_rx_snp_bits_traceTag;
+  wire         _linkMonitor_io_in_rx_snp_bits_mpam_perfMonGroup;
+  wire [8:0]   _linkMonitor_io_in_rx_snp_bits_mpam_partID;
+  wire         _linkMonitor_io_in_rx_snp_bits_mpam_mpamNS;
+  wire         _pcrdgrant_arb_io_in_0_ready;
+  wire         _pcrdgrant_arb_io_in_1_ready;
+  wire         _pcrdgrant_arb_io_in_2_ready;
+  wire         _pcrdgrant_arb_io_in_3_ready;
+  wire         _pcrdgrant_arb_io_in_4_ready;
+  wire         _pcrdgrant_arb_io_in_5_ready;
+  wire         _pcrdgrant_arb_io_in_6_ready;
+  wire         _pcrdgrant_arb_io_in_7_ready;
+  wire         _pcrdgrant_arb_io_in_8_ready;
+  wire         _pcrdgrant_arb_io_in_9_ready;
+  wire         _pcrdgrant_arb_io_in_10_ready;
+  wire         _pcrdgrant_arb_io_in_11_ready;
+  wire         _pcrdgrant_arb_io_in_12_ready;
+  wire         _pcrdgrant_arb_io_in_13_ready;
+  wire         _pcrdgrant_arb_io_in_14_ready;
+  wire         _pcrdgrant_arb_io_in_15_ready;
+  wire         _pcrdgrant_arb_io_in_16_ready;
+  wire         _pcrdgrant_arb_io_in_17_ready;
+  wire         _pcrdgrant_arb_io_in_18_ready;
+  wire         _pcrdgrant_arb_io_in_19_ready;
+  wire         _pcrdgrant_arb_io_in_20_ready;
+  wire         _pcrdgrant_arb_io_in_21_ready;
+  wire         _pcrdgrant_arb_io_in_22_ready;
+  wire         _pcrdgrant_arb_io_in_23_ready;
+  wire         _pcrdgrant_arb_io_in_24_ready;
+  wire         _pcrdgrant_arb_io_in_25_ready;
+  wire         _pcrdgrant_arb_io_in_26_ready;
+  wire         _pcrdgrant_arb_io_in_27_ready;
+  wire         _pcrdgrant_arb_io_in_28_ready;
+  wire         _pcrdgrant_arb_io_in_29_ready;
+  wire         _pcrdgrant_arb_io_in_30_ready;
+  wire         _pcrdgrant_arb_io_in_31_ready;
+  wire         _pcrdgrant_arb_io_out_valid;
+  wire         _pCrdQueue_s3_io_enq_ready;
+  wire         _pCrdQueue_s3_io_deq_valid;
+  wire [3:0]   _pCrdQueue_s3_io_deq_bits_pCrdType;
+  wire [10:0]  _pCrdQueue_s3_io_deq_bits_srcID;
+  wire         _pCrdQueue_s2_io_deq_valid;
+  wire [3:0]   _pCrdQueue_s2_io_deq_bits_pCrdType;
+  wire [10:0]  _pCrdQueue_s2_io_deq_bits_srcID;
+  wire         _txdat_arb_io_in_0_ready;
+  wire         _txdat_arb_io_in_1_ready;
+  wire         _txdat_arb_io_out_valid;
+  wire [3:0]   _txdat_arb_io_out_bits_qos;
+  wire [10:0]  _txdat_arb_io_out_bits_tgtID;
+  wire [11:0]  _txdat_arb_io_out_bits_txnID;
+  wire [10:0]  _txdat_arb_io_out_bits_homeNID;
+  wire [3:0]   _txdat_arb_io_out_bits_opcode;
+  wire [1:0]   _txdat_arb_io_out_bits_respErr;
+  wire [2:0]   _txdat_arb_io_out_bits_resp;
+  wire [3:0]   _txdat_arb_io_out_bits_dataSource;
+  wire [2:0]   _txdat_arb_io_out_bits_cBusy;
+  wire [11:0]  _txdat_arb_io_out_bits_dbID;
+  wire [1:0]   _txdat_arb_io_out_bits_ccID;
+  wire [1:0]   _txdat_arb_io_out_bits_dataID;
+  wire [1:0]   _txdat_arb_io_out_bits_tagOp;
+  wire [7:0]   _txdat_arb_io_out_bits_tag;
+  wire [1:0]   _txdat_arb_io_out_bits_tu;
+  wire         _txdat_arb_io_out_bits_traceTag;
+  wire [3:0]   _txdat_arb_io_out_bits_rsvdc;
+  wire [31:0]  _txdat_arb_io_out_bits_be;
+  wire [255:0] _txdat_arb_io_out_bits_data;
+  wire [31:0]  _txdat_arb_io_out_bits_dataCheck;
+  wire [3:0]   _txdat_arb_io_out_bits_poison;
+  wire         _txrsp_arb_io_in_0_ready;
+  wire         _txrsp_arb_io_out_valid;
+  wire [3:0]   _txrsp_arb_io_out_bits_qos;
+  wire [10:0]  _txrsp_arb_io_out_bits_tgtID;
+  wire [11:0]  _txrsp_arb_io_out_bits_txnID;
+  wire [4:0]   _txrsp_arb_io_out_bits_opcode;
+  wire [1:0]   _txrsp_arb_io_out_bits_respErr;
+  wire [2:0]   _txrsp_arb_io_out_bits_resp;
+  wire [2:0]   _txrsp_arb_io_out_bits_fwdState;
+  wire [2:0]   _txrsp_arb_io_out_bits_cBusy;
+  wire [11:0]  _txrsp_arb_io_out_bits_dbID;
+  wire [3:0]   _txrsp_arb_io_out_bits_pCrdType;
+  wire [1:0]   _txrsp_arb_io_out_bits_tagOp;
+  wire         _txrsp_arb_io_out_bits_traceTag;
+  wire         _txreq_arb_io_in_0_ready;
+  wire         _txreq_arb_io_in_1_ready;
+  wire         _txreq_arb_io_out_valid;
+  wire [3:0]   _txreq_arb_io_out_bits_qos;
+  wire [10:0]  _txreq_arb_io_out_bits_tgtID;
+  wire [11:0]  _txreq_arb_io_out_bits_txnID;
+  wire [10:0]  _txreq_arb_io_out_bits_returnNID;
+  wire         _txreq_arb_io_out_bits_stashNIDValid;
+  wire [11:0]  _txreq_arb_io_out_bits_returnTxnID;
+  wire [6:0]   _txreq_arb_io_out_bits_opcode;
+  wire [2:0]   _txreq_arb_io_out_bits_size;
+  wire [47:0]  _txreq_arb_io_out_bits_addr;
+  wire         _txreq_arb_io_out_bits_ns;
+  wire         _txreq_arb_io_out_bits_likelyshared;
+  wire         _txreq_arb_io_out_bits_allowRetry;
+  wire [1:0]   _txreq_arb_io_out_bits_order;
+  wire [3:0]   _txreq_arb_io_out_bits_pCrdType;
+  wire         _txreq_arb_io_out_bits_memAttr_allocate;
+  wire         _txreq_arb_io_out_bits_memAttr_cacheable;
+  wire         _txreq_arb_io_out_bits_memAttr_device;
+  wire         _txreq_arb_io_out_bits_memAttr_ewa;
+  wire         _txreq_arb_io_out_bits_snpAttr;
+  wire [7:0]   _txreq_arb_io_out_bits_lpIDWithPadding;
+  wire         _txreq_arb_io_out_bits_snoopMe;
+  wire         _txreq_arb_io_out_bits_expCompAck;
+  wire [1:0]   _txreq_arb_io_out_bits_tagOp;
+  wire         _txreq_arb_io_out_bits_traceTag;
+  wire         _txreq_arb_io_out_bits_mpam_perfMonGroup;
+  wire [8:0]   _txreq_arb_io_out_bits_mpam_partID;
+  wire         _txreq_arb_io_out_bits_mpam_mpamNS;
+  wire [3:0]   _txreq_arb_io_out_bits_rsvdc;
+  wire         _resp_pipeline_io_in_ready;
+  wire         _resp_pipeline_io_out_valid;
+  wire         _train_pipeline_io_out_valid;
+  wire [33:0]  _train_pipeline_io_out_bits_tag;
+  wire [7:0]   _train_pipeline_io_out_bits_set;
+  wire         _train_pipeline_io_out_bits_needT;
+  wire [6:0]   _train_pipeline_io_out_bits_source;
+  wire [43:0]  _train_pipeline_io_out_bits_vaddr;
+  wire [4:0]   _train_pipeline_io_out_bits_reqsource;
+  wire         _slices_0_io_in_d_valid;
+  wire         _slices_0_io_l1Hint_valid;
+  wire [6:0]   _slices_0_io_l1Hint_bits_sourceId;
+  wire         _slices_0_io_l1Hint_bits_hasData;
+  wire         _slices_0_io_prefetch_train_valid;
+  wire [33:0]  _slices_0_io_prefetch_train_bits_tag;
+  wire [7:0]   _slices_0_io_prefetch_train_bits_set;
+  wire         _slices_0_io_prefetch_train_bits_needT;
+  wire [6:0]   _slices_0_io_prefetch_train_bits_source;
+  wire [43:0]  _slices_0_io_prefetch_train_bits_vaddr;
+  wire         _slices_0_io_prefetch_train_bits_hit;
+  wire         _slices_0_io_prefetch_train_bits_prefetched;
+  wire [3:0]   _slices_0_io_prefetch_train_bits_pfsource;
+  wire [4:0]   _slices_0_io_prefetch_train_bits_reqsource;
+  wire         _slices_0_io_prefetch_req_ready;
+  wire         _slices_0_io_prefetch_resp_valid;
+  wire         _slices_0_io_error_valid;
+  wire         _slices_0_io_error_bits_valid;
+  wire [47:0]  _slices_0_io_error_bits_address;
+  wire         _slices_0_io_l2Miss;
+  wire         _slices_0_io_out_tx_req_valid;
+  wire [3:0]   _slices_0_io_out_tx_req_bits_qos;
+  wire [10:0]  _slices_0_io_out_tx_req_bits_srcID;
+  wire [11:0]  _slices_0_io_out_tx_req_bits_txnID;
+  wire [10:0]  _slices_0_io_out_tx_req_bits_returnNID;
+  wire         _slices_0_io_out_tx_req_bits_stashNIDValid;
+  wire [11:0]  _slices_0_io_out_tx_req_bits_returnTxnID;
+  wire [6:0]   _slices_0_io_out_tx_req_bits_opcode;
+  wire [47:0]  _slices_0_io_out_tx_req_bits_addr;
+  wire         _slices_0_io_out_tx_req_bits_ns;
+  wire         _slices_0_io_out_tx_req_bits_likelyshared;
+  wire         _slices_0_io_out_tx_req_bits_allowRetry;
+  wire [1:0]   _slices_0_io_out_tx_req_bits_order;
+  wire [3:0]   _slices_0_io_out_tx_req_bits_pCrdType;
+  wire         _slices_0_io_out_tx_req_bits_memAttr_allocate;
+  wire         _slices_0_io_out_tx_req_bits_memAttr_cacheable;
+  wire         _slices_0_io_out_tx_req_bits_memAttr_device;
+  wire         _slices_0_io_out_tx_req_bits_memAttr_ewa;
+  wire         _slices_0_io_out_tx_req_bits_snpAttr;
+  wire [7:0]   _slices_0_io_out_tx_req_bits_lpIDWithPadding;
+  wire         _slices_0_io_out_tx_req_bits_snoopMe;
+  wire         _slices_0_io_out_tx_req_bits_expCompAck;
+  wire [1:0]   _slices_0_io_out_tx_req_bits_tagOp;
+  wire         _slices_0_io_out_tx_req_bits_traceTag;
+  wire         _slices_0_io_out_tx_req_bits_mpam_perfMonGroup;
+  wire [8:0]   _slices_0_io_out_tx_req_bits_mpam_partID;
+  wire         _slices_0_io_out_tx_req_bits_mpam_mpamNS;
+  wire [3:0]   _slices_0_io_out_tx_req_bits_rsvdc;
+  wire         _slices_0_io_out_tx_rsp_valid;
+  wire [3:0]   _slices_0_io_out_tx_rsp_bits_qos;
+  wire [10:0]  _slices_0_io_out_tx_rsp_bits_tgtID;
+  wire [10:0]  _slices_0_io_out_tx_rsp_bits_srcID;
+  wire [11:0]  _slices_0_io_out_tx_rsp_bits_txnID;
+  wire [4:0]   _slices_0_io_out_tx_rsp_bits_opcode;
+  wire [1:0]   _slices_0_io_out_tx_rsp_bits_respErr;
+  wire [2:0]   _slices_0_io_out_tx_rsp_bits_resp;
+  wire [2:0]   _slices_0_io_out_tx_rsp_bits_fwdState;
+  wire [2:0]   _slices_0_io_out_tx_rsp_bits_cBusy;
+  wire [11:0]  _slices_0_io_out_tx_rsp_bits_dbID;
+  wire [3:0]   _slices_0_io_out_tx_rsp_bits_pCrdType;
+  wire [1:0]   _slices_0_io_out_tx_rsp_bits_tagOp;
+  wire         _slices_0_io_out_tx_rsp_bits_traceTag;
+  wire         _slices_0_io_out_tx_dat_valid;
+  wire [10:0]  _slices_0_io_out_tx_dat_bits_tgtID;
+  wire [10:0]  _slices_0_io_out_tx_dat_bits_srcID;
+  wire [11:0]  _slices_0_io_out_tx_dat_bits_txnID;
+  wire [10:0]  _slices_0_io_out_tx_dat_bits_homeNID;
+  wire [3:0]   _slices_0_io_out_tx_dat_bits_opcode;
+  wire [1:0]   _slices_0_io_out_tx_dat_bits_respErr;
+  wire [2:0]   _slices_0_io_out_tx_dat_bits_resp;
+  wire [3:0]   _slices_0_io_out_tx_dat_bits_dataSource;
+  wire [11:0]  _slices_0_io_out_tx_dat_bits_dbID;
+  wire [1:0]   _slices_0_io_out_tx_dat_bits_ccID;
+  wire [1:0]   _slices_0_io_out_tx_dat_bits_dataID;
+  wire         _slices_0_io_out_tx_dat_bits_traceTag;
+  wire [31:0]  _slices_0_io_out_tx_dat_bits_be;
+  wire [255:0] _slices_0_io_out_tx_dat_bits_data;
+  wire [31:0]  _slices_0_io_out_tx_dat_bits_dataCheck;
+  wire [3:0]   _slices_0_io_out_tx_dat_bits_poison;
+  wire         _slices_0_io_out_rx_snp_ready;
+  wire         _slices_0_io_pCrd_0_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_0_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_0_query_bits_srcID;
+  wire         _slices_0_io_pCrd_1_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_1_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_1_query_bits_srcID;
+  wire         _slices_0_io_pCrd_2_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_2_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_2_query_bits_srcID;
+  wire         _slices_0_io_pCrd_3_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_3_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_3_query_bits_srcID;
+  wire         _slices_0_io_pCrd_4_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_4_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_4_query_bits_srcID;
+  wire         _slices_0_io_pCrd_5_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_5_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_5_query_bits_srcID;
+  wire         _slices_0_io_pCrd_6_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_6_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_6_query_bits_srcID;
+  wire         _slices_0_io_pCrd_7_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_7_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_7_query_bits_srcID;
+  wire         _slices_0_io_pCrd_8_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_8_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_8_query_bits_srcID;
+  wire         _slices_0_io_pCrd_9_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_9_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_9_query_bits_srcID;
+  wire         _slices_0_io_pCrd_10_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_10_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_10_query_bits_srcID;
+  wire         _slices_0_io_pCrd_11_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_11_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_11_query_bits_srcID;
+  wire         _slices_0_io_pCrd_12_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_12_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_12_query_bits_srcID;
+  wire         _slices_0_io_pCrd_13_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_13_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_13_query_bits_srcID;
+  wire         _slices_0_io_pCrd_14_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_14_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_14_query_bits_srcID;
+  wire         _slices_0_io_pCrd_15_query_valid;
+  wire [3:0]   _slices_0_io_pCrd_15_query_bits_pCrdType;
+  wire [10:0]  _slices_0_io_pCrd_15_query_bits_srcID;
+  wire [5:0]   _slices_0_io_perf_0_value;
+  wire [5:0]   _slices_0_io_perf_1_value;
+  wire [5:0]   _slices_0_io_perf_3_value;
+  wire [5:0]   _slices_0_io_perf_4_value;
+  wire [5:0]   _slices_0_io_perf_5_value;
+  wire [5:0]   _slices_0_io_perf_6_value;
+  wire [5:0]   _slices_0_io_perf_7_value;
+  wire [5:0]   _slices_0_io_perf_8_value;
+  wire [5:0]   _slices_0_io_perf_9_value;
+  wire [5:0]   _slices_0_io_perf_10_value;
+  wire [5:0]   _slices_0_io_perf_11_value;
+  wire [5:0]   _slices_0_io_perf_12_value;
+  wire [5:0]   _slices_0_io_perf_13_value;
+  wire [5:0]   _slices_0_io_perf_14_value;
+  wire [5:0]   _slices_0_io_perf_15_value;
+  wire [5:0]   _slices_0_io_perf_16_value;
+  wire         _prefetcher_io_train_0_ready;
+  wire         _prefetcher_io_req_0_valid;
+  wire [33:0]  _prefetcher_io_req_0_bits_tag;
+  wire [7:0]   _prefetcher_io_req_0_bits_set;
+  wire [43:0]  _prefetcher_io_req_0_bits_vaddr;
+  wire         _prefetcher_io_req_0_bits_needT;
+  wire [6:0]   _prefetcher_io_req_0_bits_source;
+  wire [4:0]   _prefetcher_io_req_0_bits_pfSource;
+  wire         _prefetcher_io_resp_0_ready;
+  wire         _mmioBridge_io_tx_req_valid;
+  wire [3:0]   _mmioBridge_io_tx_req_bits_qos;
+  wire [10:0]  _mmioBridge_io_tx_req_bits_tgtID;
+  wire [10:0]  _mmioBridge_io_tx_req_bits_srcID;
+  wire [11:0]  _mmioBridge_io_tx_req_bits_txnID;
+  wire [10:0]  _mmioBridge_io_tx_req_bits_returnNID;
+  wire         _mmioBridge_io_tx_req_bits_stashNIDValid;
+  wire [11:0]  _mmioBridge_io_tx_req_bits_returnTxnID;
+  wire [6:0]   _mmioBridge_io_tx_req_bits_opcode;
+  wire [2:0]   _mmioBridge_io_tx_req_bits_size;
+  wire [47:0]  _mmioBridge_io_tx_req_bits_addr;
+  wire         _mmioBridge_io_tx_req_bits_ns;
+  wire         _mmioBridge_io_tx_req_bits_likelyshared;
+  wire         _mmioBridge_io_tx_req_bits_allowRetry;
+  wire [1:0]   _mmioBridge_io_tx_req_bits_order;
+  wire [3:0]   _mmioBridge_io_tx_req_bits_pCrdType;
+  wire         _mmioBridge_io_tx_req_bits_memAttr_allocate;
+  wire         _mmioBridge_io_tx_req_bits_memAttr_cacheable;
+  wire         _mmioBridge_io_tx_req_bits_memAttr_device;
+  wire         _mmioBridge_io_tx_req_bits_memAttr_ewa;
+  wire         _mmioBridge_io_tx_req_bits_snpAttr;
+  wire [7:0]   _mmioBridge_io_tx_req_bits_lpIDWithPadding;
+  wire         _mmioBridge_io_tx_req_bits_snoopMe;
+  wire         _mmioBridge_io_tx_req_bits_expCompAck;
+  wire [1:0]   _mmioBridge_io_tx_req_bits_tagOp;
+  wire         _mmioBridge_io_tx_req_bits_traceTag;
+  wire         _mmioBridge_io_tx_req_bits_mpam_perfMonGroup;
+  wire [8:0]   _mmioBridge_io_tx_req_bits_mpam_partID;
+  wire         _mmioBridge_io_tx_req_bits_mpam_mpamNS;
+  wire [3:0]   _mmioBridge_io_tx_req_bits_rsvdc;
+  wire         _mmioBridge_io_tx_dat_valid;
+  wire [3:0]   _mmioBridge_io_tx_dat_bits_qos;
+  wire [10:0]  _mmioBridge_io_tx_dat_bits_tgtID;
+  wire [10:0]  _mmioBridge_io_tx_dat_bits_srcID;
+  wire [11:0]  _mmioBridge_io_tx_dat_bits_txnID;
+  wire [10:0]  _mmioBridge_io_tx_dat_bits_homeNID;
+  wire [3:0]   _mmioBridge_io_tx_dat_bits_opcode;
+  wire [1:0]   _mmioBridge_io_tx_dat_bits_respErr;
+  wire [2:0]   _mmioBridge_io_tx_dat_bits_resp;
+  wire [3:0]   _mmioBridge_io_tx_dat_bits_dataSource;
+  wire [2:0]   _mmioBridge_io_tx_dat_bits_cBusy;
+  wire [11:0]  _mmioBridge_io_tx_dat_bits_dbID;
+  wire [1:0]   _mmioBridge_io_tx_dat_bits_ccID;
+  wire [1:0]   _mmioBridge_io_tx_dat_bits_dataID;
+  wire [1:0]   _mmioBridge_io_tx_dat_bits_tagOp;
+  wire [7:0]   _mmioBridge_io_tx_dat_bits_tag;
+  wire [1:0]   _mmioBridge_io_tx_dat_bits_tu;
+  wire         _mmioBridge_io_tx_dat_bits_traceTag;
+  wire [3:0]   _mmioBridge_io_tx_dat_bits_rsvdc;
+  wire [31:0]  _mmioBridge_io_tx_dat_bits_be;
+  wire [255:0] _mmioBridge_io_tx_dat_bits_data;
+  wire [31:0]  _mmioBridge_io_tx_dat_bits_dataCheck;
+  wire [3:0]   _mmioBridge_io_tx_dat_bits_poison;
+  wire         _mmioBridge_io_rx_rsp_ready;
+  wire         _mmioBridge_io_rx_dat_ready;
+  wire         _mmioBridge_io_pCrd_0_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_0_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_0_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_1_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_1_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_1_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_2_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_2_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_2_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_3_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_3_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_3_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_4_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_4_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_4_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_5_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_5_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_5_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_6_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_6_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_6_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_7_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_7_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_7_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_8_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_8_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_8_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_9_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_9_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_9_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_10_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_10_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_10_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_11_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_11_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_11_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_12_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_12_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_12_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_13_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_13_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_13_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_14_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_14_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_14_query_bits_srcID;
+  wire         _mmioBridge_io_pCrd_15_query_valid;
+  wire [3:0]   _mmioBridge_io_pCrd_15_query_bits_pCrdType;
+  wire [10:0]  _mmioBridge_io_pCrd_15_query_bits_srcID;
+  wire [163:0] bd_indata = 164'h0;
+  wire [11:0]  bd_addr_rd = 12'h0;
+  wire [11:0]  bd_addr = 12'h0;
+  wire [7:0]   bd_be = 8'h0;
+  wire [3:0]   bd_array = 4'h0;
+  wire         bd_readen = 1'h0;
+  wire         bd_writeen = 1'h0;
+  wire         bd_req = 1'h0;
+  wire         bd_all = 1'h0;
+  reg          allCanFire_REG;
+  reg          allCanFire_REG_1;
+  reg          allCanFire_REG_2;
+  reg          allCanFire_REG_3;
+  reg          allCanFire_REG_4;
+  reg          sliceCanFire_REG;
+  reg          sliceCanFire_REG_1;
+  reg          sliceCanFire_REG_2;
+  reg          sliceCanFire_REG_3;
+  reg          sliceCanFire_REG_4;
+  wire         sliceCanFire = sliceCanFire_REG_1 | sliceCanFire_REG_4;
+  wire         _slice_io_in_d_ready_T =
+    sliceCanFire | allCanFire_REG_1 & allCanFire_REG_4 | sliceCanFire
+    & ~_slices_0_io_in_d_valid;
+  wire         _rxrsp_ready_T = _rxrspPipe_pipeline_io_out_bits_opcode == 5'h7;
+  wire         isPCrdGrant = _rxrspPipe_pipeline_io_out_valid & _rxrsp_ready_T;
+  reg          pCrdGrantValid_s1;
+  reg  [3:0]   pCrdGrantType_s1;
+  reg  [10:0]  pCrdGrantSrcID_s1;
+  reg  [63:0]  grantCnt;
+  reg  [5:0]   io_perf_1_value_REG;
+  reg  [5:0]   io_perf_1_value_REG_1;
+  reg  [5:0]   io_perf_2_value_REG;
+  reg  [5:0]   io_perf_2_value_REG_1;
+  reg  [5:0]   io_perf_4_value_REG;
+  reg  [5:0]   io_perf_4_value_REG_1;
+  reg  [5:0]   io_perf_5_value_REG;
+  reg  [5:0]   io_perf_5_value_REG_1;
+  reg  [5:0]   io_perf_6_value_REG;
+  reg  [5:0]   io_perf_6_value_REG_1;
+  reg  [5:0]   io_perf_7_value_REG;
+  reg  [5:0]   io_perf_7_value_REG_1;
+  reg  [5:0]   io_perf_8_value_REG;
+  reg  [5:0]   io_perf_8_value_REG_1;
+  reg  [5:0]   io_perf_9_value_REG;
+  reg  [5:0]   io_perf_9_value_REG_1;
+  reg  [5:0]   io_perf_10_value_REG;
+  reg  [5:0]   io_perf_10_value_REG_1;
+  reg  [5:0]   io_perf_11_value_REG;
+  reg  [5:0]   io_perf_11_value_REG_1;
+  reg  [5:0]   io_perf_12_value_REG;
+  reg  [5:0]   io_perf_12_value_REG_1;
+  reg  [5:0]   io_perf_13_value_REG;
+  reg  [5:0]   io_perf_13_value_REG_1;
+  reg  [5:0]   io_perf_14_value_REG;
+  reg  [5:0]   io_perf_14_value_REG_1;
+  reg  [5:0]   io_perf_15_value_REG;
+  reg  [5:0]   io_perf_15_value_REG_1;
+  reg  [5:0]   io_perf_16_value_REG;
+  reg  [5:0]   io_perf_16_value_REG_1;
+  reg  [5:0]   io_perf_17_value_REG;
+  reg  [5:0]   io_perf_17_value_REG_1;
+  wire         contains =
+    ~(_slices_0_io_l1Hint_bits_sourceId[6])
+    & _slices_0_io_l1Hint_bits_sourceId[5:0] < 6'h24;
+  wire         hintChosenVec_0_valid =
+    ~master_ready_REG & _slices_0_io_l1Hint_valid & contains;
+  wire         contains_1 =
+    _slices_0_io_l1Hint_bits_sourceId[6:4] == 3'h5
+    & _slices_0_io_l1Hint_bits_sourceId[3:0] != 4'hF;
+  wire         hintChosenVec_1_valid =
+    ~master_ready_REG_1 & _slices_0_io_l1Hint_valid & contains_1;
+  wire         contains_2 = _slices_0_io_l1Hint_bits_sourceId[6:4] == 3'h4;
+  wire         hintChosenVec_2_valid =
+    ~master_ready_REG_2 & _slices_0_io_l1Hint_valid & contains_2;
+  reg          io_l2Miss_REG;
+  always @(posedge clock) begin
+    allCanFire_REG <=
+      ~(hintChosenVec_0_valid | hintChosenVec_1_valid | hintChosenVec_2_valid);
+    allCanFire_REG_1 <= allCanFire_REG;
+    allCanFire_REG_2 <=
+      ~(hintChosenVec_0_valid & _slices_0_io_l1Hint_bits_hasData | hintChosenVec_1_valid
+        & _slices_0_io_l1Hint_bits_hasData | hintChosenVec_2_valid
+        & _slices_0_io_l1Hint_bits_hasData);
+    allCanFire_REG_3 <= allCanFire_REG_2;
+    allCanFire_REG_4 <= allCanFire_REG_3;
+    sliceCanFire_REG <=
+      hintChosenVec_0_valid | hintChosenVec_1_valid | hintChosenVec_2_valid;
+    sliceCanFire_REG_1 <= sliceCanFire_REG;
+    sliceCanFire_REG_2 <=
+      hintChosenVec_0_valid & _slices_0_io_l1Hint_bits_hasData | hintChosenVec_1_valid
+      & _slices_0_io_l1Hint_bits_hasData | hintChosenVec_2_valid
+      & _slices_0_io_l1Hint_bits_hasData;
+    sliceCanFire_REG_3 <= sliceCanFire_REG_2;
+    sliceCanFire_REG_4 <= sliceCanFire_REG_3;
+    pCrdGrantValid_s1 <= isPCrdGrant;
+    pCrdGrantType_s1 <= _rxrspPipe_pipeline_io_out_bits_pCrdType;
+    pCrdGrantSrcID_s1 <= _rxrspPipe_pipeline_io_out_bits_srcID;
+    io_perf_1_value_REG <= _slices_0_io_perf_0_value;
+    io_perf_1_value_REG_1 <= io_perf_1_value_REG;
+    io_perf_2_value_REG <= _slices_0_io_perf_1_value;
+    io_perf_2_value_REG_1 <= io_perf_2_value_REG;
+    io_perf_4_value_REG <= _slices_0_io_perf_3_value;
+    io_perf_4_value_REG_1 <= io_perf_4_value_REG;
+    io_perf_5_value_REG <= _slices_0_io_perf_4_value;
+    io_perf_5_value_REG_1 <= io_perf_5_value_REG;
+    io_perf_6_value_REG <= _slices_0_io_perf_5_value;
+    io_perf_6_value_REG_1 <= io_perf_6_value_REG;
+    io_perf_7_value_REG <= _slices_0_io_perf_6_value;
+    io_perf_7_value_REG_1 <= io_perf_7_value_REG;
+    io_perf_8_value_REG <= _slices_0_io_perf_7_value;
+    io_perf_8_value_REG_1 <= io_perf_8_value_REG;
+    io_perf_9_value_REG <= _slices_0_io_perf_8_value;
+    io_perf_9_value_REG_1 <= io_perf_9_value_REG;
+    io_perf_10_value_REG <= _slices_0_io_perf_9_value;
+    io_perf_10_value_REG_1 <= io_perf_10_value_REG;
+    io_perf_11_value_REG <= _slices_0_io_perf_10_value;
+    io_perf_11_value_REG_1 <= io_perf_11_value_REG;
+    io_perf_12_value_REG <= _slices_0_io_perf_11_value;
+    io_perf_12_value_REG_1 <= io_perf_12_value_REG;
+    io_perf_13_value_REG <= _slices_0_io_perf_12_value;
+    io_perf_13_value_REG_1 <= io_perf_13_value_REG;
+    io_perf_14_value_REG <= _slices_0_io_perf_13_value;
+    io_perf_14_value_REG_1 <= io_perf_14_value_REG;
+    io_perf_15_value_REG <= _slices_0_io_perf_14_value;
+    io_perf_15_value_REG_1 <= io_perf_15_value_REG;
+    io_perf_16_value_REG <= _slices_0_io_perf_15_value;
+    io_perf_16_value_REG_1 <= io_perf_16_value_REG;
+    io_perf_17_value_REG <= _slices_0_io_perf_16_value;
+    io_perf_17_value_REG_1 <= io_perf_17_value_REG;
+    master_ready_REG <= hintChosenVec_0_valid & _slices_0_io_l1Hint_bits_hasData;
+    master_ready_REG_1 <= hintChosenVec_1_valid & _slices_0_io_l1Hint_bits_hasData;
+    master_ready_REG_2 <= hintChosenVec_2_valid & _slices_0_io_l1Hint_bits_hasData;
+    io_l2Miss_REG <= _slices_0_io_l2Miss;
+  end // always @(posedge)
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      grantCnt <= 64'h0;
+    else if (_pcrdgrant_arb_io_out_valid)
+      grantCnt <= 64'(grantCnt + 64'h1);
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:77];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [6:0] i = 7'h0; i < 7'h4E; i += 7'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        allCanFire_REG = _RANDOM[7'h0][0];
+        allCanFire_REG_1 = _RANDOM[7'h0][1];
+        allCanFire_REG_2 = _RANDOM[7'h0][2];
+        allCanFire_REG_3 = _RANDOM[7'h0][3];
+        allCanFire_REG_4 = _RANDOM[7'h0][4];
+        sliceCanFire_REG = _RANDOM[7'h0][5];
+        sliceCanFire_REG_1 = _RANDOM[7'h0][6];
+        sliceCanFire_REG_2 = _RANDOM[7'h0][7];
+        sliceCanFire_REG_3 = _RANDOM[7'h0][8];
+        sliceCanFire_REG_4 = _RANDOM[7'h0][9];
+        pCrdGrantValid_s1 = _RANDOM[7'h44][10];
+        pCrdGrantType_s1 = _RANDOM[7'h44][14:11];
+        pCrdGrantSrcID_s1 = _RANDOM[7'h44][25:15];
+        grantCnt = {_RANDOM[7'h44][31:26], _RANDOM[7'h45], _RANDOM[7'h46][25:0]};
+        io_perf_1_value_REG = {_RANDOM[7'h46][31:28], _RANDOM[7'h47][1:0]};
+        io_perf_1_value_REG_1 = _RANDOM[7'h47][7:2];
+        io_perf_2_value_REG = _RANDOM[7'h47][13:8];
+        io_perf_2_value_REG_1 = _RANDOM[7'h47][19:14];
+        io_perf_4_value_REG = _RANDOM[7'h48][5:0];
+        io_perf_4_value_REG_1 = _RANDOM[7'h48][11:6];
+        io_perf_5_value_REG = _RANDOM[7'h48][17:12];
+        io_perf_5_value_REG_1 = _RANDOM[7'h48][23:18];
+        io_perf_6_value_REG = _RANDOM[7'h48][29:24];
+        io_perf_6_value_REG_1 = {_RANDOM[7'h48][31:30], _RANDOM[7'h49][3:0]};
+        io_perf_7_value_REG = _RANDOM[7'h49][9:4];
+        io_perf_7_value_REG_1 = _RANDOM[7'h49][15:10];
+        io_perf_8_value_REG = _RANDOM[7'h49][21:16];
+        io_perf_8_value_REG_1 = _RANDOM[7'h49][27:22];
+        io_perf_9_value_REG = {_RANDOM[7'h49][31:28], _RANDOM[7'h4A][1:0]};
+        io_perf_9_value_REG_1 = _RANDOM[7'h4A][7:2];
+        io_perf_10_value_REG = _RANDOM[7'h4A][13:8];
+        io_perf_10_value_REG_1 = _RANDOM[7'h4A][19:14];
+        io_perf_11_value_REG = _RANDOM[7'h4A][25:20];
+        io_perf_11_value_REG_1 = _RANDOM[7'h4A][31:26];
+        io_perf_12_value_REG = _RANDOM[7'h4B][5:0];
+        io_perf_12_value_REG_1 = _RANDOM[7'h4B][11:6];
+        io_perf_13_value_REG = _RANDOM[7'h4B][17:12];
+        io_perf_13_value_REG_1 = _RANDOM[7'h4B][23:18];
+        io_perf_14_value_REG = _RANDOM[7'h4B][29:24];
+        io_perf_14_value_REG_1 = {_RANDOM[7'h4B][31:30], _RANDOM[7'h4C][3:0]};
+        io_perf_15_value_REG = _RANDOM[7'h4C][9:4];
+        io_perf_15_value_REG_1 = _RANDOM[7'h4C][15:10];
+        io_perf_16_value_REG = _RANDOM[7'h4C][21:16];
+        io_perf_16_value_REG_1 = _RANDOM[7'h4C][27:22];
+        io_perf_17_value_REG = {_RANDOM[7'h4C][31:28], _RANDOM[7'h4D][1:0]};
+        io_perf_17_value_REG_1 = _RANDOM[7'h4D][7:2];
+        master_ready_REG = _RANDOM[7'h4D][8];
+        master_ready_REG_1 = _RANDOM[7'h4D][9];
+        master_ready_REG_2 = _RANDOM[7'h4D][10];
+        io_l2Miss_REG = _RANDOM[7'h4D][11];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        grantCnt = 64'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  MMIOBridge mmioBridge (
+    .clock                                   (clock),
+    .reset                                   (reset),
+    .auto_mmio_in_a_ready                    (auto_mmioBridge_mmio_in_a_ready),
+    .auto_mmio_in_a_valid                    (auto_mmioBridge_mmio_in_a_valid),
+    .auto_mmio_in_a_bits_opcode              (auto_mmioBridge_mmio_in_a_bits_opcode),
+    .auto_mmio_in_a_bits_param               (auto_mmioBridge_mmio_in_a_bits_param),
+    .auto_mmio_in_a_bits_size                (auto_mmioBridge_mmio_in_a_bits_size),
+    .auto_mmio_in_a_bits_source              (auto_mmioBridge_mmio_in_a_bits_source),
+    .auto_mmio_in_a_bits_address             (auto_mmioBridge_mmio_in_a_bits_address),
+    .auto_mmio_in_a_bits_user_memBackType_MM
+      (auto_mmioBridge_mmio_in_a_bits_user_memBackType_MM),
+    .auto_mmio_in_a_bits_user_memPageType_NC
+      (auto_mmioBridge_mmio_in_a_bits_user_memPageType_NC),
+    .auto_mmio_in_a_bits_mask                (auto_mmioBridge_mmio_in_a_bits_mask),
+    .auto_mmio_in_a_bits_data                (auto_mmioBridge_mmio_in_a_bits_data),
+    .auto_mmio_in_a_bits_corrupt             (auto_mmioBridge_mmio_in_a_bits_corrupt),
+    .auto_mmio_in_d_ready                    (auto_mmioBridge_mmio_in_d_ready),
+    .auto_mmio_in_d_valid                    (auto_mmioBridge_mmio_in_d_valid),
+    .auto_mmio_in_d_bits_opcode              (auto_mmioBridge_mmio_in_d_bits_opcode),
+    .auto_mmio_in_d_bits_param               (auto_mmioBridge_mmio_in_d_bits_param),
+    .auto_mmio_in_d_bits_size                (auto_mmioBridge_mmio_in_d_bits_size),
+    .auto_mmio_in_d_bits_source              (auto_mmioBridge_mmio_in_d_bits_source),
+    .auto_mmio_in_d_bits_sink                (auto_mmioBridge_mmio_in_d_bits_sink),
+    .auto_mmio_in_d_bits_denied              (auto_mmioBridge_mmio_in_d_bits_denied),
+    .auto_mmio_in_d_bits_data                (auto_mmioBridge_mmio_in_d_bits_data),
+    .auto_mmio_in_d_bits_corrupt             (auto_mmioBridge_mmio_in_d_bits_corrupt),
+    .io_tx_req_ready                         (_txreq_arb_io_in_1_ready),
+    .io_tx_req_valid                         (_mmioBridge_io_tx_req_valid),
+    .io_tx_req_bits_qos                      (_mmioBridge_io_tx_req_bits_qos),
+    .io_tx_req_bits_tgtID                    (_mmioBridge_io_tx_req_bits_tgtID),
+    .io_tx_req_bits_srcID                    (_mmioBridge_io_tx_req_bits_srcID),
+    .io_tx_req_bits_txnID                    (_mmioBridge_io_tx_req_bits_txnID),
+    .io_tx_req_bits_returnNID                (_mmioBridge_io_tx_req_bits_returnNID),
+    .io_tx_req_bits_stashNIDValid            (_mmioBridge_io_tx_req_bits_stashNIDValid),
+    .io_tx_req_bits_returnTxnID              (_mmioBridge_io_tx_req_bits_returnTxnID),
+    .io_tx_req_bits_opcode                   (_mmioBridge_io_tx_req_bits_opcode),
+    .io_tx_req_bits_size                     (_mmioBridge_io_tx_req_bits_size),
+    .io_tx_req_bits_addr                     (_mmioBridge_io_tx_req_bits_addr),
+    .io_tx_req_bits_ns                       (_mmioBridge_io_tx_req_bits_ns),
+    .io_tx_req_bits_likelyshared             (_mmioBridge_io_tx_req_bits_likelyshared),
+    .io_tx_req_bits_allowRetry               (_mmioBridge_io_tx_req_bits_allowRetry),
+    .io_tx_req_bits_order                    (_mmioBridge_io_tx_req_bits_order),
+    .io_tx_req_bits_pCrdType                 (_mmioBridge_io_tx_req_bits_pCrdType),
+    .io_tx_req_bits_memAttr_allocate
+      (_mmioBridge_io_tx_req_bits_memAttr_allocate),
+    .io_tx_req_bits_memAttr_cacheable
+      (_mmioBridge_io_tx_req_bits_memAttr_cacheable),
+    .io_tx_req_bits_memAttr_device           (_mmioBridge_io_tx_req_bits_memAttr_device),
+    .io_tx_req_bits_memAttr_ewa              (_mmioBridge_io_tx_req_bits_memAttr_ewa),
+    .io_tx_req_bits_snpAttr                  (_mmioBridge_io_tx_req_bits_snpAttr),
+    .io_tx_req_bits_lpIDWithPadding          (_mmioBridge_io_tx_req_bits_lpIDWithPadding),
+    .io_tx_req_bits_snoopMe                  (_mmioBridge_io_tx_req_bits_snoopMe),
+    .io_tx_req_bits_expCompAck               (_mmioBridge_io_tx_req_bits_expCompAck),
+    .io_tx_req_bits_tagOp                    (_mmioBridge_io_tx_req_bits_tagOp),
+    .io_tx_req_bits_traceTag                 (_mmioBridge_io_tx_req_bits_traceTag),
+    .io_tx_req_bits_mpam_perfMonGroup
+      (_mmioBridge_io_tx_req_bits_mpam_perfMonGroup),
+    .io_tx_req_bits_mpam_partID              (_mmioBridge_io_tx_req_bits_mpam_partID),
+    .io_tx_req_bits_mpam_mpamNS              (_mmioBridge_io_tx_req_bits_mpam_mpamNS),
+    .io_tx_req_bits_rsvdc                    (_mmioBridge_io_tx_req_bits_rsvdc),
+    .io_tx_dat_ready                         (_txdat_arb_io_in_1_ready),
+    .io_tx_dat_valid                         (_mmioBridge_io_tx_dat_valid),
+    .io_tx_dat_bits_qos                      (_mmioBridge_io_tx_dat_bits_qos),
+    .io_tx_dat_bits_tgtID                    (_mmioBridge_io_tx_dat_bits_tgtID),
+    .io_tx_dat_bits_srcID                    (_mmioBridge_io_tx_dat_bits_srcID),
+    .io_tx_dat_bits_txnID                    (_mmioBridge_io_tx_dat_bits_txnID),
+    .io_tx_dat_bits_homeNID                  (_mmioBridge_io_tx_dat_bits_homeNID),
+    .io_tx_dat_bits_opcode                   (_mmioBridge_io_tx_dat_bits_opcode),
+    .io_tx_dat_bits_respErr                  (_mmioBridge_io_tx_dat_bits_respErr),
+    .io_tx_dat_bits_resp                     (_mmioBridge_io_tx_dat_bits_resp),
+    .io_tx_dat_bits_dataSource               (_mmioBridge_io_tx_dat_bits_dataSource),
+    .io_tx_dat_bits_cBusy                    (_mmioBridge_io_tx_dat_bits_cBusy),
+    .io_tx_dat_bits_dbID                     (_mmioBridge_io_tx_dat_bits_dbID),
+    .io_tx_dat_bits_ccID                     (_mmioBridge_io_tx_dat_bits_ccID),
+    .io_tx_dat_bits_dataID                   (_mmioBridge_io_tx_dat_bits_dataID),
+    .io_tx_dat_bits_tagOp                    (_mmioBridge_io_tx_dat_bits_tagOp),
+    .io_tx_dat_bits_tag                      (_mmioBridge_io_tx_dat_bits_tag),
+    .io_tx_dat_bits_tu                       (_mmioBridge_io_tx_dat_bits_tu),
+    .io_tx_dat_bits_traceTag                 (_mmioBridge_io_tx_dat_bits_traceTag),
+    .io_tx_dat_bits_rsvdc                    (_mmioBridge_io_tx_dat_bits_rsvdc),
+    .io_tx_dat_bits_be                       (_mmioBridge_io_tx_dat_bits_be),
+    .io_tx_dat_bits_data                     (_mmioBridge_io_tx_dat_bits_data),
+    .io_tx_dat_bits_dataCheck                (_mmioBridge_io_tx_dat_bits_dataCheck),
+    .io_tx_dat_bits_poison                   (_mmioBridge_io_tx_dat_bits_poison),
+    .io_rx_rsp_ready                         (_mmioBridge_io_rx_rsp_ready),
+    .io_rx_rsp_valid
+      (_rxrspPipe_pipeline_io_out_valid & _rxrspPipe_pipeline_io_out_bits_txnID[11]
+       & ~isPCrdGrant),
+    .io_rx_rsp_bits_qos                      (_rxrspPipe_pipeline_io_out_bits_qos),
+    .io_rx_rsp_bits_tgtID                    (_rxrspPipe_pipeline_io_out_bits_tgtID),
+    .io_rx_rsp_bits_srcID                    (_rxrspPipe_pipeline_io_out_bits_srcID),
+    .io_rx_rsp_bits_txnID
+      ({1'h0, _rxrspPipe_pipeline_io_out_bits_txnID[10:0]}),
+    .io_rx_rsp_bits_opcode                   (_rxrspPipe_pipeline_io_out_bits_opcode),
+    .io_rx_rsp_bits_respErr                  (_rxrspPipe_pipeline_io_out_bits_respErr),
+    .io_rx_rsp_bits_resp                     (_rxrspPipe_pipeline_io_out_bits_resp),
+    .io_rx_rsp_bits_fwdState                 (_rxrspPipe_pipeline_io_out_bits_fwdState),
+    .io_rx_rsp_bits_cBusy                    (_rxrspPipe_pipeline_io_out_bits_cBusy),
+    .io_rx_rsp_bits_dbID                     (_rxrspPipe_pipeline_io_out_bits_dbID),
+    .io_rx_rsp_bits_pCrdType                 (_rxrspPipe_pipeline_io_out_bits_pCrdType),
+    .io_rx_rsp_bits_tagOp                    (_rxrspPipe_pipeline_io_out_bits_tagOp),
+    .io_rx_rsp_bits_traceTag                 (_rxrspPipe_pipeline_io_out_bits_traceTag),
+    .io_rx_dat_ready                         (_mmioBridge_io_rx_dat_ready),
+    .io_rx_dat_valid
+      (_rxdatPipe_pipeline_io_out_valid & _rxdatPipe_pipeline_io_out_bits_txnID[11]),
+    .io_rx_dat_bits_qos                      (_rxdatPipe_pipeline_io_out_bits_qos),
+    .io_rx_dat_bits_tgtID                    (_rxdatPipe_pipeline_io_out_bits_tgtID),
+    .io_rx_dat_bits_srcID                    (_rxdatPipe_pipeline_io_out_bits_srcID),
+    .io_rx_dat_bits_txnID
+      ({1'h0, _rxdatPipe_pipeline_io_out_bits_txnID[10:0]}),
+    .io_rx_dat_bits_homeNID                  (_rxdatPipe_pipeline_io_out_bits_homeNID),
+    .io_rx_dat_bits_opcode                   (_rxdatPipe_pipeline_io_out_bits_opcode),
+    .io_rx_dat_bits_respErr                  (_rxdatPipe_pipeline_io_out_bits_respErr),
+    .io_rx_dat_bits_resp                     (_rxdatPipe_pipeline_io_out_bits_resp),
+    .io_rx_dat_bits_dataSource               (_rxdatPipe_pipeline_io_out_bits_dataSource),
+    .io_rx_dat_bits_cBusy                    (_rxdatPipe_pipeline_io_out_bits_cBusy),
+    .io_rx_dat_bits_dbID                     (_rxdatPipe_pipeline_io_out_bits_dbID),
+    .io_rx_dat_bits_ccID                     (_rxdatPipe_pipeline_io_out_bits_ccID),
+    .io_rx_dat_bits_dataID                   (_rxdatPipe_pipeline_io_out_bits_dataID),
+    .io_rx_dat_bits_tagOp                    (_rxdatPipe_pipeline_io_out_bits_tagOp),
+    .io_rx_dat_bits_tag                      (_rxdatPipe_pipeline_io_out_bits_tag),
+    .io_rx_dat_bits_tu                       (_rxdatPipe_pipeline_io_out_bits_tu),
+    .io_rx_dat_bits_traceTag                 (_rxdatPipe_pipeline_io_out_bits_traceTag),
+    .io_rx_dat_bits_rsvdc                    (_rxdatPipe_pipeline_io_out_bits_rsvdc),
+    .io_rx_dat_bits_be                       (_rxdatPipe_pipeline_io_out_bits_be),
+    .io_rx_dat_bits_data                     (_rxdatPipe_pipeline_io_out_bits_data),
+    .io_rx_dat_bits_dataCheck                (_rxdatPipe_pipeline_io_out_bits_dataCheck),
+    .io_rx_dat_bits_poison                   (_rxdatPipe_pipeline_io_out_bits_poison),
+    .io_pCrd_0_query_valid                   (_mmioBridge_io_pCrd_0_query_valid),
+    .io_pCrd_0_query_bits_pCrdType           (_mmioBridge_io_pCrd_0_query_bits_pCrdType),
+    .io_pCrd_0_query_bits_srcID              (_mmioBridge_io_pCrd_0_query_bits_srcID),
+    .io_pCrd_0_grant                         (_pcrdgrant_arb_io_in_0_ready),
+    .io_pCrd_1_query_valid                   (_mmioBridge_io_pCrd_1_query_valid),
+    .io_pCrd_1_query_bits_pCrdType           (_mmioBridge_io_pCrd_1_query_bits_pCrdType),
+    .io_pCrd_1_query_bits_srcID              (_mmioBridge_io_pCrd_1_query_bits_srcID),
+    .io_pCrd_1_grant                         (_pcrdgrant_arb_io_in_1_ready),
+    .io_pCrd_2_query_valid                   (_mmioBridge_io_pCrd_2_query_valid),
+    .io_pCrd_2_query_bits_pCrdType           (_mmioBridge_io_pCrd_2_query_bits_pCrdType),
+    .io_pCrd_2_query_bits_srcID              (_mmioBridge_io_pCrd_2_query_bits_srcID),
+    .io_pCrd_2_grant                         (_pcrdgrant_arb_io_in_2_ready),
+    .io_pCrd_3_query_valid                   (_mmioBridge_io_pCrd_3_query_valid),
+    .io_pCrd_3_query_bits_pCrdType           (_mmioBridge_io_pCrd_3_query_bits_pCrdType),
+    .io_pCrd_3_query_bits_srcID              (_mmioBridge_io_pCrd_3_query_bits_srcID),
+    .io_pCrd_3_grant                         (_pcrdgrant_arb_io_in_3_ready),
+    .io_pCrd_4_query_valid                   (_mmioBridge_io_pCrd_4_query_valid),
+    .io_pCrd_4_query_bits_pCrdType           (_mmioBridge_io_pCrd_4_query_bits_pCrdType),
+    .io_pCrd_4_query_bits_srcID              (_mmioBridge_io_pCrd_4_query_bits_srcID),
+    .io_pCrd_4_grant                         (_pcrdgrant_arb_io_in_4_ready),
+    .io_pCrd_5_query_valid                   (_mmioBridge_io_pCrd_5_query_valid),
+    .io_pCrd_5_query_bits_pCrdType           (_mmioBridge_io_pCrd_5_query_bits_pCrdType),
+    .io_pCrd_5_query_bits_srcID              (_mmioBridge_io_pCrd_5_query_bits_srcID),
+    .io_pCrd_5_grant                         (_pcrdgrant_arb_io_in_5_ready),
+    .io_pCrd_6_query_valid                   (_mmioBridge_io_pCrd_6_query_valid),
+    .io_pCrd_6_query_bits_pCrdType           (_mmioBridge_io_pCrd_6_query_bits_pCrdType),
+    .io_pCrd_6_query_bits_srcID              (_mmioBridge_io_pCrd_6_query_bits_srcID),
+    .io_pCrd_6_grant                         (_pcrdgrant_arb_io_in_6_ready),
+    .io_pCrd_7_query_valid                   (_mmioBridge_io_pCrd_7_query_valid),
+    .io_pCrd_7_query_bits_pCrdType           (_mmioBridge_io_pCrd_7_query_bits_pCrdType),
+    .io_pCrd_7_query_bits_srcID              (_mmioBridge_io_pCrd_7_query_bits_srcID),
+    .io_pCrd_7_grant                         (_pcrdgrant_arb_io_in_7_ready),
+    .io_pCrd_8_query_valid                   (_mmioBridge_io_pCrd_8_query_valid),
+    .io_pCrd_8_query_bits_pCrdType           (_mmioBridge_io_pCrd_8_query_bits_pCrdType),
+    .io_pCrd_8_query_bits_srcID              (_mmioBridge_io_pCrd_8_query_bits_srcID),
+    .io_pCrd_8_grant                         (_pcrdgrant_arb_io_in_8_ready),
+    .io_pCrd_9_query_valid                   (_mmioBridge_io_pCrd_9_query_valid),
+    .io_pCrd_9_query_bits_pCrdType           (_mmioBridge_io_pCrd_9_query_bits_pCrdType),
+    .io_pCrd_9_query_bits_srcID              (_mmioBridge_io_pCrd_9_query_bits_srcID),
+    .io_pCrd_9_grant                         (_pcrdgrant_arb_io_in_9_ready),
+    .io_pCrd_10_query_valid                  (_mmioBridge_io_pCrd_10_query_valid),
+    .io_pCrd_10_query_bits_pCrdType          (_mmioBridge_io_pCrd_10_query_bits_pCrdType),
+    .io_pCrd_10_query_bits_srcID             (_mmioBridge_io_pCrd_10_query_bits_srcID),
+    .io_pCrd_10_grant                        (_pcrdgrant_arb_io_in_10_ready),
+    .io_pCrd_11_query_valid                  (_mmioBridge_io_pCrd_11_query_valid),
+    .io_pCrd_11_query_bits_pCrdType          (_mmioBridge_io_pCrd_11_query_bits_pCrdType),
+    .io_pCrd_11_query_bits_srcID             (_mmioBridge_io_pCrd_11_query_bits_srcID),
+    .io_pCrd_11_grant                        (_pcrdgrant_arb_io_in_11_ready),
+    .io_pCrd_12_query_valid                  (_mmioBridge_io_pCrd_12_query_valid),
+    .io_pCrd_12_query_bits_pCrdType          (_mmioBridge_io_pCrd_12_query_bits_pCrdType),
+    .io_pCrd_12_query_bits_srcID             (_mmioBridge_io_pCrd_12_query_bits_srcID),
+    .io_pCrd_12_grant                        (_pcrdgrant_arb_io_in_12_ready),
+    .io_pCrd_13_query_valid                  (_mmioBridge_io_pCrd_13_query_valid),
+    .io_pCrd_13_query_bits_pCrdType          (_mmioBridge_io_pCrd_13_query_bits_pCrdType),
+    .io_pCrd_13_query_bits_srcID             (_mmioBridge_io_pCrd_13_query_bits_srcID),
+    .io_pCrd_13_grant                        (_pcrdgrant_arb_io_in_13_ready),
+    .io_pCrd_14_query_valid                  (_mmioBridge_io_pCrd_14_query_valid),
+    .io_pCrd_14_query_bits_pCrdType          (_mmioBridge_io_pCrd_14_query_bits_pCrdType),
+    .io_pCrd_14_query_bits_srcID             (_mmioBridge_io_pCrd_14_query_bits_srcID),
+    .io_pCrd_14_grant                        (_pcrdgrant_arb_io_in_14_ready),
+    .io_pCrd_15_query_valid                  (_mmioBridge_io_pCrd_15_query_valid),
+    .io_pCrd_15_query_bits_pCrdType          (_mmioBridge_io_pCrd_15_query_bits_pCrdType),
+    .io_pCrd_15_query_bits_srcID             (_mmioBridge_io_pCrd_15_query_bits_srcID),
+    .io_pCrd_15_grant                        (_pcrdgrant_arb_io_in_15_ready)
+  );
+  wire         childBd_array;
+  wire         childBd_all;
+  wire         childBd_req;
+  wire         childBd_writeen;
+  wire         childBd_be;
+  wire [8:0]   childBd_addr;
+  wire [12:0]  childBd_indata;
+  wire         childBd_readen;
+  wire [8:0]   childBd_addr_rd;
+  Prefetcher prefetcher (
+    .clock                              (clock),
+    .reset                              (reset),
+    .io_train_0_ready                   (_prefetcher_io_train_0_ready),
+    .io_train_0_valid                   (_train_pipeline_io_out_valid),
+    .io_train_0_bits_tag                (_train_pipeline_io_out_bits_tag),
+    .io_train_0_bits_set                (_train_pipeline_io_out_bits_set),
+    .io_train_0_bits_needT              (_train_pipeline_io_out_bits_needT),
+    .io_train_0_bits_source             (_train_pipeline_io_out_bits_source),
+    .io_train_0_bits_vaddr              (_train_pipeline_io_out_bits_vaddr),
+    .io_train_0_bits_reqsource          (_train_pipeline_io_out_bits_reqsource),
+    .io_tlb_req_req_valid               (io_l2_tlb_req_req_valid),
+    .io_tlb_req_req_bits_vaddr          (io_l2_tlb_req_req_bits_vaddr),
+    .io_tlb_req_resp_valid              (io_l2_tlb_req_resp_valid),
+    .io_tlb_req_resp_bits_paddr_0       (io_l2_tlb_req_resp_bits_paddr_0),
+    .io_tlb_req_resp_bits_pbmt          (io_l2_tlb_req_resp_bits_pbmt),
+    .io_tlb_req_resp_bits_miss          (io_l2_tlb_req_resp_bits_miss),
+    .io_tlb_req_resp_bits_excp_0_gpf_ld (io_l2_tlb_req_resp_bits_excp_0_gpf_ld),
+    .io_tlb_req_resp_bits_excp_0_pf_ld  (io_l2_tlb_req_resp_bits_excp_0_pf_ld),
+    .io_tlb_req_resp_bits_excp_0_af_ld  (io_l2_tlb_req_resp_bits_excp_0_af_ld),
+    .io_tlb_req_pmp_resp_ld             (io_l2_tlb_req_pmp_resp_ld),
+    .io_tlb_req_pmp_resp_mmio           (io_l2_tlb_req_pmp_resp_mmio),
+    .io_req_0_ready                     (_slices_0_io_prefetch_req_ready),
+    .io_req_0_valid                     (_prefetcher_io_req_0_valid),
+    .io_req_0_bits_tag                  (_prefetcher_io_req_0_bits_tag),
+    .io_req_0_bits_set                  (_prefetcher_io_req_0_bits_set),
+    .io_req_0_bits_vaddr                (_prefetcher_io_req_0_bits_vaddr),
+    .io_req_0_bits_needT                (_prefetcher_io_req_0_bits_needT),
+    .io_req_0_bits_source               (_prefetcher_io_req_0_bits_source),
+    .io_req_0_bits_pfSource             (_prefetcher_io_req_0_bits_pfSource),
+    .io_resp_0_ready                    (_prefetcher_io_resp_0_ready),
+    .io_resp_0_valid                    (_resp_pipeline_io_out_valid),
+    .pfCtrlFromCore_l2_pf_master_en     (io_pfCtrlFromCore_l2_pf_master_en),
+    .pfCtrlFromCore_l2_pbop_en          (io_pfCtrlFromCore_l2_pbop_en),
+    .pfCtrlFromCore_l2_vbop_en          (io_pfCtrlFromCore_l2_vbop_en),
+    .pfCtrlFromCore_l2_pf_delay_latency (io_pfCtrlFromCore_l2_pf_delay_latency),
+    .sigFromSrams_bore_ram_hold         (io_dft_ram_hold),
+    .sigFromSrams_bore_ram_bypass       (io_dft_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken     (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk      (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp     (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold     (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_cgen             (io_dft_cgen),
+    .sigFromSrams_bore_1_ram_hold       (io_dft_ram_hold),
+    .sigFromSrams_bore_1_ram_bypass     (io_dft_ram_bypass),
+    .sigFromSrams_bore_1_ram_bp_clken   (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_1_ram_aux_clk    (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_1_ram_aux_ckbp   (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_1_ram_mcp_hold   (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_1_cgen           (io_dft_cgen),
+    .boreChildrenBd_bore_array          (childBd_array),
+    .boreChildrenBd_bore_all            (childBd_all),
+    .boreChildrenBd_bore_req            (childBd_req),
+    .boreChildrenBd_bore_ack            (childBd_ack),
+    .boreChildrenBd_bore_writeen        (childBd_writeen),
+    .boreChildrenBd_bore_be             (childBd_be),
+    .boreChildrenBd_bore_addr           (childBd_addr),
+    .boreChildrenBd_bore_indata         (childBd_indata),
+    .boreChildrenBd_bore_readen         (childBd_readen),
+    .boreChildrenBd_bore_addr_rd        (childBd_addr_rd),
+    .boreChildrenBd_bore_outdata        (childBd_outdata)
+  );
+  wire [3:0]   childBd_1_array;
+  wire         childBd_1_all;
+  wire         childBd_1_req;
+  wire         childBd_1_writeen;
+  wire [7:0]   childBd_1_be;
+  wire [11:0]  childBd_1_addr;
+  wire [163:0] childBd_1_indata;
+  wire         childBd_1_readen;
+  wire [11:0]  childBd_1_addr_rd;
+  Slice slices_0 (
+    .clock                                (clock),
+    .reset                                (reset),
+    .io_in_a_ready                        (auto_in_a_ready),
+    .io_in_a_valid                        (auto_in_a_valid),
+    .io_in_a_bits_opcode                  (auto_in_a_bits_opcode),
+    .io_in_a_bits_param                   (auto_in_a_bits_param),
+    .io_in_a_bits_size                    (auto_in_a_bits_size),
+    .io_in_a_bits_source                  (auto_in_a_bits_source),
+    .io_in_a_bits_address                 (auto_in_a_bits_address),
+    .io_in_a_bits_user_reqSource          (auto_in_a_bits_user_reqSource),
+    .io_in_a_bits_user_alias              (auto_in_a_bits_user_alias),
+    .io_in_a_bits_user_vaddr              (auto_in_a_bits_user_vaddr),
+    .io_in_a_bits_user_needHint           (auto_in_a_bits_user_needHint),
+    .io_in_a_bits_echo_isKeyword          (auto_in_a_bits_echo_isKeyword),
+    .io_in_a_bits_corrupt                 (auto_in_a_bits_corrupt),
+    .io_in_b_ready                        (auto_in_b_ready),
+    .io_in_b_valid                        (auto_in_b_valid),
+    .io_in_b_bits_opcode                  (auto_in_b_bits_opcode),
+    .io_in_b_bits_param                   (auto_in_b_bits_param),
+    .io_in_b_bits_address                 (auto_in_b_bits_address),
+    .io_in_b_bits_data                    (auto_in_b_bits_data),
+    .io_in_c_ready                        (auto_in_c_ready),
+    .io_in_c_valid                        (auto_in_c_valid),
+    .io_in_c_bits_opcode                  (auto_in_c_bits_opcode),
+    .io_in_c_bits_param                   (auto_in_c_bits_param),
+    .io_in_c_bits_size                    (auto_in_c_bits_size),
+    .io_in_c_bits_source                  (auto_in_c_bits_source),
+    .io_in_c_bits_address                 (auto_in_c_bits_address),
+    .io_in_c_bits_data                    (auto_in_c_bits_data),
+    .io_in_c_bits_corrupt                 (auto_in_c_bits_corrupt),
+    .io_in_d_ready                        (auto_in_d_ready & _slice_io_in_d_ready_T),
+    .io_in_d_valid                        (_slices_0_io_in_d_valid),
+    .io_in_d_bits_opcode                  (auto_in_d_bits_opcode),
+    .io_in_d_bits_param                   (auto_in_d_bits_param),
+    .io_in_d_bits_source                  (auto_in_d_bits_source),
+    .io_in_d_bits_sink                    (auto_in_d_bits_sink),
+    .io_in_d_bits_denied                  (auto_in_d_bits_denied),
+    .io_in_d_bits_echo_isKeyword          (auto_in_d_bits_echo_isKeyword),
+    .io_in_d_bits_data                    (auto_in_d_bits_data),
+    .io_in_d_bits_corrupt                 (auto_in_d_bits_corrupt),
+    .io_in_e_valid                        (auto_in_e_valid),
+    .io_in_e_bits_sink                    (auto_in_e_bits_sink),
+    .io_l1Hint_ready
+      (contains & ~master_ready_REG | contains_1 & ~master_ready_REG_1 | contains_2
+       & ~master_ready_REG_2),
+    .io_l1Hint_valid                      (_slices_0_io_l1Hint_valid),
+    .io_l1Hint_bits_sourceId              (_slices_0_io_l1Hint_bits_sourceId),
+    .io_l1Hint_bits_isKeyword             (io_l2_hint_bits_isKeyword),
+    .io_l1Hint_bits_hasData               (_slices_0_io_l1Hint_bits_hasData),
+    .io_prefetch_train_valid              (_slices_0_io_prefetch_train_valid),
+    .io_prefetch_train_bits_tag           (_slices_0_io_prefetch_train_bits_tag),
+    .io_prefetch_train_bits_set           (_slices_0_io_prefetch_train_bits_set),
+    .io_prefetch_train_bits_needT         (_slices_0_io_prefetch_train_bits_needT),
+    .io_prefetch_train_bits_source        (_slices_0_io_prefetch_train_bits_source),
+    .io_prefetch_train_bits_vaddr         (_slices_0_io_prefetch_train_bits_vaddr),
+    .io_prefetch_train_bits_hit           (_slices_0_io_prefetch_train_bits_hit),
+    .io_prefetch_train_bits_prefetched    (_slices_0_io_prefetch_train_bits_prefetched),
+    .io_prefetch_train_bits_pfsource      (_slices_0_io_prefetch_train_bits_pfsource),
+    .io_prefetch_train_bits_reqsource     (_slices_0_io_prefetch_train_bits_reqsource),
+    .io_prefetch_req_ready                (_slices_0_io_prefetch_req_ready),
+    .io_prefetch_req_valid                (_prefetcher_io_req_0_valid),
+    .io_prefetch_req_bits_tag             (_prefetcher_io_req_0_bits_tag),
+    .io_prefetch_req_bits_set             (_prefetcher_io_req_0_bits_set),
+    .io_prefetch_req_bits_vaddr           (_prefetcher_io_req_0_bits_vaddr),
+    .io_prefetch_req_bits_needT           (_prefetcher_io_req_0_bits_needT),
+    .io_prefetch_req_bits_source          (_prefetcher_io_req_0_bits_source),
+    .io_prefetch_req_bits_pfSource        (_prefetcher_io_req_0_bits_pfSource),
+    .io_prefetch_resp_ready               (_resp_pipeline_io_in_ready),
+    .io_prefetch_resp_valid               (_slices_0_io_prefetch_resp_valid),
+    .io_error_valid                       (_slices_0_io_error_valid),
+    .io_error_bits_valid                  (_slices_0_io_error_bits_valid),
+    .io_error_bits_address                (_slices_0_io_error_bits_address),
+    .io_l2Miss                            (_slices_0_io_l2Miss),
+    .io_out_tx_req_ready                  (_txreq_arb_io_in_0_ready),
+    .io_out_tx_req_valid                  (_slices_0_io_out_tx_req_valid),
+    .io_out_tx_req_bits_qos               (_slices_0_io_out_tx_req_bits_qos),
+    .io_out_tx_req_bits_srcID             (_slices_0_io_out_tx_req_bits_srcID),
+    .io_out_tx_req_bits_txnID             (_slices_0_io_out_tx_req_bits_txnID),
+    .io_out_tx_req_bits_returnNID         (_slices_0_io_out_tx_req_bits_returnNID),
+    .io_out_tx_req_bits_stashNIDValid     (_slices_0_io_out_tx_req_bits_stashNIDValid),
+    .io_out_tx_req_bits_returnTxnID       (_slices_0_io_out_tx_req_bits_returnTxnID),
+    .io_out_tx_req_bits_opcode            (_slices_0_io_out_tx_req_bits_opcode),
+    .io_out_tx_req_bits_addr              (_slices_0_io_out_tx_req_bits_addr),
+    .io_out_tx_req_bits_ns                (_slices_0_io_out_tx_req_bits_ns),
+    .io_out_tx_req_bits_likelyshared      (_slices_0_io_out_tx_req_bits_likelyshared),
+    .io_out_tx_req_bits_allowRetry        (_slices_0_io_out_tx_req_bits_allowRetry),
+    .io_out_tx_req_bits_order             (_slices_0_io_out_tx_req_bits_order),
+    .io_out_tx_req_bits_pCrdType          (_slices_0_io_out_tx_req_bits_pCrdType),
+    .io_out_tx_req_bits_memAttr_allocate  (_slices_0_io_out_tx_req_bits_memAttr_allocate),
+    .io_out_tx_req_bits_memAttr_cacheable
+      (_slices_0_io_out_tx_req_bits_memAttr_cacheable),
+    .io_out_tx_req_bits_memAttr_device    (_slices_0_io_out_tx_req_bits_memAttr_device),
+    .io_out_tx_req_bits_memAttr_ewa       (_slices_0_io_out_tx_req_bits_memAttr_ewa),
+    .io_out_tx_req_bits_snpAttr           (_slices_0_io_out_tx_req_bits_snpAttr),
+    .io_out_tx_req_bits_lpIDWithPadding   (_slices_0_io_out_tx_req_bits_lpIDWithPadding),
+    .io_out_tx_req_bits_snoopMe           (_slices_0_io_out_tx_req_bits_snoopMe),
+    .io_out_tx_req_bits_expCompAck        (_slices_0_io_out_tx_req_bits_expCompAck),
+    .io_out_tx_req_bits_tagOp             (_slices_0_io_out_tx_req_bits_tagOp),
+    .io_out_tx_req_bits_traceTag          (_slices_0_io_out_tx_req_bits_traceTag),
+    .io_out_tx_req_bits_mpam_perfMonGroup
+      (_slices_0_io_out_tx_req_bits_mpam_perfMonGroup),
+    .io_out_tx_req_bits_mpam_partID       (_slices_0_io_out_tx_req_bits_mpam_partID),
+    .io_out_tx_req_bits_mpam_mpamNS       (_slices_0_io_out_tx_req_bits_mpam_mpamNS),
+    .io_out_tx_req_bits_rsvdc             (_slices_0_io_out_tx_req_bits_rsvdc),
+    .io_out_tx_rsp_ready                  (_txrsp_arb_io_in_0_ready),
+    .io_out_tx_rsp_valid                  (_slices_0_io_out_tx_rsp_valid),
+    .io_out_tx_rsp_bits_qos               (_slices_0_io_out_tx_rsp_bits_qos),
+    .io_out_tx_rsp_bits_tgtID             (_slices_0_io_out_tx_rsp_bits_tgtID),
+    .io_out_tx_rsp_bits_srcID             (_slices_0_io_out_tx_rsp_bits_srcID),
+    .io_out_tx_rsp_bits_txnID             (_slices_0_io_out_tx_rsp_bits_txnID),
+    .io_out_tx_rsp_bits_opcode            (_slices_0_io_out_tx_rsp_bits_opcode),
+    .io_out_tx_rsp_bits_respErr           (_slices_0_io_out_tx_rsp_bits_respErr),
+    .io_out_tx_rsp_bits_resp              (_slices_0_io_out_tx_rsp_bits_resp),
+    .io_out_tx_rsp_bits_fwdState          (_slices_0_io_out_tx_rsp_bits_fwdState),
+    .io_out_tx_rsp_bits_cBusy             (_slices_0_io_out_tx_rsp_bits_cBusy),
+    .io_out_tx_rsp_bits_dbID              (_slices_0_io_out_tx_rsp_bits_dbID),
+    .io_out_tx_rsp_bits_pCrdType          (_slices_0_io_out_tx_rsp_bits_pCrdType),
+    .io_out_tx_rsp_bits_tagOp             (_slices_0_io_out_tx_rsp_bits_tagOp),
+    .io_out_tx_rsp_bits_traceTag          (_slices_0_io_out_tx_rsp_bits_traceTag),
+    .io_out_tx_dat_ready                  (_txdat_arb_io_in_0_ready),
+    .io_out_tx_dat_valid                  (_slices_0_io_out_tx_dat_valid),
+    .io_out_tx_dat_bits_tgtID             (_slices_0_io_out_tx_dat_bits_tgtID),
+    .io_out_tx_dat_bits_srcID             (_slices_0_io_out_tx_dat_bits_srcID),
+    .io_out_tx_dat_bits_txnID             (_slices_0_io_out_tx_dat_bits_txnID),
+    .io_out_tx_dat_bits_homeNID           (_slices_0_io_out_tx_dat_bits_homeNID),
+    .io_out_tx_dat_bits_opcode            (_slices_0_io_out_tx_dat_bits_opcode),
+    .io_out_tx_dat_bits_respErr           (_slices_0_io_out_tx_dat_bits_respErr),
+    .io_out_tx_dat_bits_resp              (_slices_0_io_out_tx_dat_bits_resp),
+    .io_out_tx_dat_bits_dataSource        (_slices_0_io_out_tx_dat_bits_dataSource),
+    .io_out_tx_dat_bits_dbID              (_slices_0_io_out_tx_dat_bits_dbID),
+    .io_out_tx_dat_bits_ccID              (_slices_0_io_out_tx_dat_bits_ccID),
+    .io_out_tx_dat_bits_dataID            (_slices_0_io_out_tx_dat_bits_dataID),
+    .io_out_tx_dat_bits_traceTag          (_slices_0_io_out_tx_dat_bits_traceTag),
+    .io_out_tx_dat_bits_be                (_slices_0_io_out_tx_dat_bits_be),
+    .io_out_tx_dat_bits_data              (_slices_0_io_out_tx_dat_bits_data),
+    .io_out_tx_dat_bits_dataCheck         (_slices_0_io_out_tx_dat_bits_dataCheck),
+    .io_out_tx_dat_bits_poison            (_slices_0_io_out_tx_dat_bits_poison),
+    .io_out_rx_rsp_valid
+      (_rxrspPipe_pipeline_io_out_valid & ~(_rxrspPipe_pipeline_io_out_bits_txnID[11])
+       & ~isPCrdGrant),
+    .io_out_rx_rsp_bits_srcID             (_rxrspPipe_pipeline_io_out_bits_srcID),
+    .io_out_rx_rsp_bits_txnID
+      ({1'h0, _rxrspPipe_pipeline_io_out_bits_txnID[10:0]}),
+    .io_out_rx_rsp_bits_opcode            (_rxrspPipe_pipeline_io_out_bits_opcode),
+    .io_out_rx_rsp_bits_respErr           (_rxrspPipe_pipeline_io_out_bits_respErr),
+    .io_out_rx_rsp_bits_resp              (_rxrspPipe_pipeline_io_out_bits_resp),
+    .io_out_rx_rsp_bits_dbID              (_rxrspPipe_pipeline_io_out_bits_dbID),
+    .io_out_rx_rsp_bits_pCrdType          (_rxrspPipe_pipeline_io_out_bits_pCrdType),
+    .io_out_rx_rsp_bits_traceTag          (_rxrspPipe_pipeline_io_out_bits_traceTag),
+    .io_out_rx_dat_valid
+      (_rxdatPipe_pipeline_io_out_valid & ~(_rxdatPipe_pipeline_io_out_bits_txnID[11])),
+    .io_out_rx_dat_bits_txnID
+      ({1'h0, _rxdatPipe_pipeline_io_out_bits_txnID[10:0]}),
+    .io_out_rx_dat_bits_homeNID           (_rxdatPipe_pipeline_io_out_bits_homeNID),
+    .io_out_rx_dat_bits_opcode            (_rxdatPipe_pipeline_io_out_bits_opcode),
+    .io_out_rx_dat_bits_respErr           (_rxdatPipe_pipeline_io_out_bits_respErr),
+    .io_out_rx_dat_bits_resp              (_rxdatPipe_pipeline_io_out_bits_resp),
+    .io_out_rx_dat_bits_dbID              (_rxdatPipe_pipeline_io_out_bits_dbID),
+    .io_out_rx_dat_bits_dataID            (_rxdatPipe_pipeline_io_out_bits_dataID),
+    .io_out_rx_dat_bits_traceTag          (_rxdatPipe_pipeline_io_out_bits_traceTag),
+    .io_out_rx_dat_bits_data              (_rxdatPipe_pipeline_io_out_bits_data),
+    .io_out_rx_dat_bits_dataCheck         (_rxdatPipe_pipeline_io_out_bits_dataCheck),
+    .io_out_rx_dat_bits_poison            (_rxdatPipe_pipeline_io_out_bits_poison),
+    .io_out_rx_snp_ready                  (_slices_0_io_out_rx_snp_ready),
+    .io_out_rx_snp_valid                  (_linkMonitor_io_in_rx_snp_valid),
+    .io_out_rx_snp_bits_qos               (_linkMonitor_io_in_rx_snp_bits_qos),
+    .io_out_rx_snp_bits_srcID             (_linkMonitor_io_in_rx_snp_bits_srcID),
+    .io_out_rx_snp_bits_txnID             (_linkMonitor_io_in_rx_snp_bits_txnID),
+    .io_out_rx_snp_bits_fwdNID            (_linkMonitor_io_in_rx_snp_bits_fwdNID),
+    .io_out_rx_snp_bits_fwdTxnID          (_linkMonitor_io_in_rx_snp_bits_fwdTxnID),
+    .io_out_rx_snp_bits_opcode            (_linkMonitor_io_in_rx_snp_bits_opcode),
+    .io_out_rx_snp_bits_addr              (_linkMonitor_io_in_rx_snp_bits_addr),
+    .io_out_rx_snp_bits_ns                (_linkMonitor_io_in_rx_snp_bits_ns),
+    .io_out_rx_snp_bits_doNotGoToSD       (_linkMonitor_io_in_rx_snp_bits_doNotGoToSD),
+    .io_out_rx_snp_bits_retToSrc          (_linkMonitor_io_in_rx_snp_bits_retToSrc),
+    .io_out_rx_snp_bits_traceTag          (_linkMonitor_io_in_rx_snp_bits_traceTag),
+    .io_out_rx_snp_bits_mpam_perfMonGroup
+      (_linkMonitor_io_in_rx_snp_bits_mpam_perfMonGroup),
+    .io_out_rx_snp_bits_mpam_partID       (_linkMonitor_io_in_rx_snp_bits_mpam_partID),
+    .io_out_rx_snp_bits_mpam_mpamNS       (_linkMonitor_io_in_rx_snp_bits_mpam_mpamNS),
+    .io_pCrd_0_query_valid                (_slices_0_io_pCrd_0_query_valid),
+    .io_pCrd_0_query_bits_pCrdType        (_slices_0_io_pCrd_0_query_bits_pCrdType),
+    .io_pCrd_0_query_bits_srcID           (_slices_0_io_pCrd_0_query_bits_srcID),
+    .io_pCrd_0_grant                      (_pcrdgrant_arb_io_in_16_ready),
+    .io_pCrd_1_query_valid                (_slices_0_io_pCrd_1_query_valid),
+    .io_pCrd_1_query_bits_pCrdType        (_slices_0_io_pCrd_1_query_bits_pCrdType),
+    .io_pCrd_1_query_bits_srcID           (_slices_0_io_pCrd_1_query_bits_srcID),
+    .io_pCrd_1_grant                      (_pcrdgrant_arb_io_in_17_ready),
+    .io_pCrd_2_query_valid                (_slices_0_io_pCrd_2_query_valid),
+    .io_pCrd_2_query_bits_pCrdType        (_slices_0_io_pCrd_2_query_bits_pCrdType),
+    .io_pCrd_2_query_bits_srcID           (_slices_0_io_pCrd_2_query_bits_srcID),
+    .io_pCrd_2_grant                      (_pcrdgrant_arb_io_in_18_ready),
+    .io_pCrd_3_query_valid                (_slices_0_io_pCrd_3_query_valid),
+    .io_pCrd_3_query_bits_pCrdType        (_slices_0_io_pCrd_3_query_bits_pCrdType),
+    .io_pCrd_3_query_bits_srcID           (_slices_0_io_pCrd_3_query_bits_srcID),
+    .io_pCrd_3_grant                      (_pcrdgrant_arb_io_in_19_ready),
+    .io_pCrd_4_query_valid                (_slices_0_io_pCrd_4_query_valid),
+    .io_pCrd_4_query_bits_pCrdType        (_slices_0_io_pCrd_4_query_bits_pCrdType),
+    .io_pCrd_4_query_bits_srcID           (_slices_0_io_pCrd_4_query_bits_srcID),
+    .io_pCrd_4_grant                      (_pcrdgrant_arb_io_in_20_ready),
+    .io_pCrd_5_query_valid                (_slices_0_io_pCrd_5_query_valid),
+    .io_pCrd_5_query_bits_pCrdType        (_slices_0_io_pCrd_5_query_bits_pCrdType),
+    .io_pCrd_5_query_bits_srcID           (_slices_0_io_pCrd_5_query_bits_srcID),
+    .io_pCrd_5_grant                      (_pcrdgrant_arb_io_in_21_ready),
+    .io_pCrd_6_query_valid                (_slices_0_io_pCrd_6_query_valid),
+    .io_pCrd_6_query_bits_pCrdType        (_slices_0_io_pCrd_6_query_bits_pCrdType),
+    .io_pCrd_6_query_bits_srcID           (_slices_0_io_pCrd_6_query_bits_srcID),
+    .io_pCrd_6_grant                      (_pcrdgrant_arb_io_in_22_ready),
+    .io_pCrd_7_query_valid                (_slices_0_io_pCrd_7_query_valid),
+    .io_pCrd_7_query_bits_pCrdType        (_slices_0_io_pCrd_7_query_bits_pCrdType),
+    .io_pCrd_7_query_bits_srcID           (_slices_0_io_pCrd_7_query_bits_srcID),
+    .io_pCrd_7_grant                      (_pcrdgrant_arb_io_in_23_ready),
+    .io_pCrd_8_query_valid                (_slices_0_io_pCrd_8_query_valid),
+    .io_pCrd_8_query_bits_pCrdType        (_slices_0_io_pCrd_8_query_bits_pCrdType),
+    .io_pCrd_8_query_bits_srcID           (_slices_0_io_pCrd_8_query_bits_srcID),
+    .io_pCrd_8_grant                      (_pcrdgrant_arb_io_in_24_ready),
+    .io_pCrd_9_query_valid                (_slices_0_io_pCrd_9_query_valid),
+    .io_pCrd_9_query_bits_pCrdType        (_slices_0_io_pCrd_9_query_bits_pCrdType),
+    .io_pCrd_9_query_bits_srcID           (_slices_0_io_pCrd_9_query_bits_srcID),
+    .io_pCrd_9_grant                      (_pcrdgrant_arb_io_in_25_ready),
+    .io_pCrd_10_query_valid               (_slices_0_io_pCrd_10_query_valid),
+    .io_pCrd_10_query_bits_pCrdType       (_slices_0_io_pCrd_10_query_bits_pCrdType),
+    .io_pCrd_10_query_bits_srcID          (_slices_0_io_pCrd_10_query_bits_srcID),
+    .io_pCrd_10_grant                     (_pcrdgrant_arb_io_in_26_ready),
+    .io_pCrd_11_query_valid               (_slices_0_io_pCrd_11_query_valid),
+    .io_pCrd_11_query_bits_pCrdType       (_slices_0_io_pCrd_11_query_bits_pCrdType),
+    .io_pCrd_11_query_bits_srcID          (_slices_0_io_pCrd_11_query_bits_srcID),
+    .io_pCrd_11_grant                     (_pcrdgrant_arb_io_in_27_ready),
+    .io_pCrd_12_query_valid               (_slices_0_io_pCrd_12_query_valid),
+    .io_pCrd_12_query_bits_pCrdType       (_slices_0_io_pCrd_12_query_bits_pCrdType),
+    .io_pCrd_12_query_bits_srcID          (_slices_0_io_pCrd_12_query_bits_srcID),
+    .io_pCrd_12_grant                     (_pcrdgrant_arb_io_in_28_ready),
+    .io_pCrd_13_query_valid               (_slices_0_io_pCrd_13_query_valid),
+    .io_pCrd_13_query_bits_pCrdType       (_slices_0_io_pCrd_13_query_bits_pCrdType),
+    .io_pCrd_13_query_bits_srcID          (_slices_0_io_pCrd_13_query_bits_srcID),
+    .io_pCrd_13_grant                     (_pcrdgrant_arb_io_in_29_ready),
+    .io_pCrd_14_query_valid               (_slices_0_io_pCrd_14_query_valid),
+    .io_pCrd_14_query_bits_pCrdType       (_slices_0_io_pCrd_14_query_bits_pCrdType),
+    .io_pCrd_14_query_bits_srcID          (_slices_0_io_pCrd_14_query_bits_srcID),
+    .io_pCrd_14_grant                     (_pcrdgrant_arb_io_in_30_ready),
+    .io_pCrd_15_query_valid               (_slices_0_io_pCrd_15_query_valid),
+    .io_pCrd_15_query_bits_pCrdType       (_slices_0_io_pCrd_15_query_bits_pCrdType),
+    .io_pCrd_15_query_bits_srcID          (_slices_0_io_pCrd_15_query_bits_srcID),
+    .io_pCrd_15_grant                     (_pcrdgrant_arb_io_in_31_ready),
+    .io_perf_0_value                      (_slices_0_io_perf_0_value),
+    .io_perf_1_value                      (_slices_0_io_perf_1_value),
+    .io_perf_3_value                      (_slices_0_io_perf_3_value),
+    .io_perf_4_value                      (_slices_0_io_perf_4_value),
+    .io_perf_5_value                      (_slices_0_io_perf_5_value),
+    .io_perf_6_value                      (_slices_0_io_perf_6_value),
+    .io_perf_7_value                      (_slices_0_io_perf_7_value),
+    .io_perf_8_value                      (_slices_0_io_perf_8_value),
+    .io_perf_9_value                      (_slices_0_io_perf_9_value),
+    .io_perf_10_value                     (_slices_0_io_perf_10_value),
+    .io_perf_11_value                     (_slices_0_io_perf_11_value),
+    .io_perf_12_value                     (_slices_0_io_perf_12_value),
+    .io_perf_13_value                     (_slices_0_io_perf_13_value),
+    .io_perf_14_value                     (_slices_0_io_perf_14_value),
+    .io_perf_15_value                     (_slices_0_io_perf_15_value),
+    .io_perf_16_value                     (_slices_0_io_perf_16_value),
+    .sigFromSrams_bore_ram_hold           (io_dft_ram_hold),
+    .sigFromSrams_bore_ram_bypass         (io_dft_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken       (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk        (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp       (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold       (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_cgen               (io_dft_cgen),
+    .sigFromSrams_bore_1_ram_hold         (io_dft_ram_hold),
+    .sigFromSrams_bore_1_ram_bypass       (io_dft_ram_bypass),
+    .sigFromSrams_bore_1_ram_bp_clken     (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_1_ram_aux_clk      (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_1_ram_aux_ckbp     (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_1_ram_mcp_hold     (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_1_cgen             (io_dft_cgen),
+    .sigFromSrams_bore_2_ram_hold         (io_dft_ram_hold),
+    .sigFromSrams_bore_2_ram_bypass       (io_dft_ram_bypass),
+    .sigFromSrams_bore_2_ram_bp_clken     (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_2_ram_aux_clk      (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_2_ram_aux_ckbp     (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_2_ram_mcp_hold     (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_2_cgen             (io_dft_cgen),
+    .sigFromSrams_bore_3_ram_hold         (io_dft_ram_hold),
+    .sigFromSrams_bore_3_ram_bypass       (io_dft_ram_bypass),
+    .sigFromSrams_bore_3_ram_bp_clken     (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_3_ram_aux_clk      (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_3_ram_aux_ckbp     (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_3_ram_mcp_hold     (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_3_cgen             (io_dft_cgen),
+    .sigFromSrams_bore_4_ram_hold         (io_dft_ram_hold),
+    .sigFromSrams_bore_4_ram_bypass       (io_dft_ram_bypass),
+    .sigFromSrams_bore_4_ram_bp_clken     (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_4_ram_aux_clk      (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_4_ram_aux_ckbp     (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_4_ram_mcp_hold     (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_4_cgen             (io_dft_cgen),
+    .sigFromSrams_bore_5_ram_hold         (io_dft_ram_hold),
+    .sigFromSrams_bore_5_ram_bypass       (io_dft_ram_bypass),
+    .sigFromSrams_bore_5_ram_bp_clken     (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_5_ram_aux_clk      (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_5_ram_aux_ckbp     (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_5_ram_mcp_hold     (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_5_cgen             (io_dft_cgen),
+    .sigFromSrams_bore_6_ram_hold         (io_dft_ram_hold),
+    .sigFromSrams_bore_6_ram_bypass       (io_dft_ram_bypass),
+    .sigFromSrams_bore_6_ram_bp_clken     (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_6_ram_aux_clk      (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_6_ram_aux_ckbp     (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_6_ram_mcp_hold     (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_6_cgen             (io_dft_cgen),
+    .sigFromSrams_bore_7_ram_hold         (io_dft_ram_hold),
+    .sigFromSrams_bore_7_ram_bypass       (io_dft_ram_bypass),
+    .sigFromSrams_bore_7_ram_bp_clken     (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_7_ram_aux_clk      (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_7_ram_aux_ckbp     (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_7_ram_mcp_hold     (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_7_cgen             (io_dft_cgen),
+    .sigFromSrams_bore_8_ram_hold         (io_dft_ram_hold),
+    .sigFromSrams_bore_8_ram_bypass       (io_dft_ram_bypass),
+    .sigFromSrams_bore_8_ram_bp_clken     (io_dft_ram_bp_clken),
+    .sigFromSrams_bore_8_ram_aux_clk      (io_dft_ram_aux_clk),
+    .sigFromSrams_bore_8_ram_aux_ckbp     (io_dft_ram_aux_ckbp),
+    .sigFromSrams_bore_8_ram_mcp_hold     (io_dft_ram_mcp_hold),
+    .sigFromSrams_bore_8_cgen             (io_dft_cgen),
+    .boreChildrenBd_bore_array            (childBd_1_array),
+    .boreChildrenBd_bore_all              (childBd_1_all),
+    .boreChildrenBd_bore_req              (childBd_1_req),
+    .boreChildrenBd_bore_ack              (childBd_1_ack),
+    .boreChildrenBd_bore_writeen          (childBd_1_writeen),
+    .boreChildrenBd_bore_be               (childBd_1_be),
+    .boreChildrenBd_bore_addr             (childBd_1_addr),
+    .boreChildrenBd_bore_indata           (childBd_1_indata),
+    .boreChildrenBd_bore_readen           (childBd_1_readen),
+    .boreChildrenBd_bore_addr_rd          (childBd_1_addr_rd),
+    .boreChildrenBd_bore_outdata          (childBd_1_outdata)
+  );
+  Pipeline_7 train_pipeline (
+    .clock                 (clock),
+    .reset                 (reset),
+    .io_in_valid           (_slices_0_io_prefetch_train_valid),
+    .io_in_bits_tag        (_slices_0_io_prefetch_train_bits_tag),
+    .io_in_bits_set        (_slices_0_io_prefetch_train_bits_set),
+    .io_in_bits_needT      (_slices_0_io_prefetch_train_bits_needT),
+    .io_in_bits_source     (_slices_0_io_prefetch_train_bits_source),
+    .io_in_bits_vaddr      (_slices_0_io_prefetch_train_bits_vaddr),
+    .io_in_bits_hit        (_slices_0_io_prefetch_train_bits_hit),
+    .io_in_bits_prefetched (_slices_0_io_prefetch_train_bits_prefetched),
+    .io_in_bits_pfsource   (_slices_0_io_prefetch_train_bits_pfsource),
+    .io_in_bits_reqsource  (_slices_0_io_prefetch_train_bits_reqsource),
+    .io_out_ready          (_prefetcher_io_train_0_ready),
+    .io_out_valid          (_train_pipeline_io_out_valid),
+    .io_out_bits_tag       (_train_pipeline_io_out_bits_tag),
+    .io_out_bits_set       (_train_pipeline_io_out_bits_set),
+    .io_out_bits_needT     (_train_pipeline_io_out_bits_needT),
+    .io_out_bits_source    (_train_pipeline_io_out_bits_source),
+    .io_out_bits_vaddr     (_train_pipeline_io_out_bits_vaddr),
+    .io_out_bits_reqsource (_train_pipeline_io_out_bits_reqsource)
+  );
+  Pipeline_8 resp_pipeline (
+    .clock        (clock),
+    .reset        (reset),
+    .io_in_ready  (_resp_pipeline_io_in_ready),
+    .io_in_valid  (_slices_0_io_prefetch_resp_valid),
+    .io_out_ready (_prefetcher_io_resp_0_ready),
+    .io_out_valid (_resp_pipeline_io_out_valid)
+  );
+  TwoLevelRRArbiter_11 txreq_arb (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_in_0_ready                  (_txreq_arb_io_in_0_ready),
+    .io_in_0_valid                  (_slices_0_io_out_tx_req_valid),
+    .io_in_0_bits_qos               (_slices_0_io_out_tx_req_bits_qos),
+    .io_in_0_bits_srcID             (_slices_0_io_out_tx_req_bits_srcID),
+    .io_in_0_bits_txnID             (_slices_0_io_out_tx_req_bits_txnID),
+    .io_in_0_bits_returnNID         (_slices_0_io_out_tx_req_bits_returnNID),
+    .io_in_0_bits_stashNIDValid     (_slices_0_io_out_tx_req_bits_stashNIDValid),
+    .io_in_0_bits_returnTxnID       (_slices_0_io_out_tx_req_bits_returnTxnID),
+    .io_in_0_bits_opcode            (_slices_0_io_out_tx_req_bits_opcode),
+    .io_in_0_bits_addr              (_slices_0_io_out_tx_req_bits_addr),
+    .io_in_0_bits_ns                (_slices_0_io_out_tx_req_bits_ns),
+    .io_in_0_bits_likelyshared      (_slices_0_io_out_tx_req_bits_likelyshared),
+    .io_in_0_bits_allowRetry        (_slices_0_io_out_tx_req_bits_allowRetry),
+    .io_in_0_bits_order             (_slices_0_io_out_tx_req_bits_order),
+    .io_in_0_bits_pCrdType          (_slices_0_io_out_tx_req_bits_pCrdType),
+    .io_in_0_bits_memAttr_allocate  (_slices_0_io_out_tx_req_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable (_slices_0_io_out_tx_req_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_device    (_slices_0_io_out_tx_req_bits_memAttr_device),
+    .io_in_0_bits_memAttr_ewa       (_slices_0_io_out_tx_req_bits_memAttr_ewa),
+    .io_in_0_bits_snpAttr           (_slices_0_io_out_tx_req_bits_snpAttr),
+    .io_in_0_bits_lpIDWithPadding   (_slices_0_io_out_tx_req_bits_lpIDWithPadding),
+    .io_in_0_bits_snoopMe           (_slices_0_io_out_tx_req_bits_snoopMe),
+    .io_in_0_bits_expCompAck        (_slices_0_io_out_tx_req_bits_expCompAck),
+    .io_in_0_bits_tagOp             (_slices_0_io_out_tx_req_bits_tagOp),
+    .io_in_0_bits_traceTag          (_slices_0_io_out_tx_req_bits_traceTag),
+    .io_in_0_bits_mpam_perfMonGroup (_slices_0_io_out_tx_req_bits_mpam_perfMonGroup),
+    .io_in_0_bits_mpam_partID       (_slices_0_io_out_tx_req_bits_mpam_partID),
+    .io_in_0_bits_mpam_mpamNS       (_slices_0_io_out_tx_req_bits_mpam_mpamNS),
+    .io_in_0_bits_rsvdc             (_slices_0_io_out_tx_req_bits_rsvdc),
+    .io_in_1_ready                  (_txreq_arb_io_in_1_ready),
+    .io_in_1_valid                  (_mmioBridge_io_tx_req_valid),
+    .io_in_1_bits_qos               (_mmioBridge_io_tx_req_bits_qos),
+    .io_in_1_bits_tgtID             (_mmioBridge_io_tx_req_bits_tgtID),
+    .io_in_1_bits_srcID             (_mmioBridge_io_tx_req_bits_srcID),
+    .io_in_1_bits_txnID             (_mmioBridge_io_tx_req_bits_txnID),
+    .io_in_1_bits_returnNID         (_mmioBridge_io_tx_req_bits_returnNID),
+    .io_in_1_bits_stashNIDValid     (_mmioBridge_io_tx_req_bits_stashNIDValid),
+    .io_in_1_bits_returnTxnID       (_mmioBridge_io_tx_req_bits_returnTxnID),
+    .io_in_1_bits_opcode            (_mmioBridge_io_tx_req_bits_opcode),
+    .io_in_1_bits_size              (_mmioBridge_io_tx_req_bits_size),
+    .io_in_1_bits_addr              (_mmioBridge_io_tx_req_bits_addr),
+    .io_in_1_bits_ns                (_mmioBridge_io_tx_req_bits_ns),
+    .io_in_1_bits_likelyshared      (_mmioBridge_io_tx_req_bits_likelyshared),
+    .io_in_1_bits_allowRetry        (_mmioBridge_io_tx_req_bits_allowRetry),
+    .io_in_1_bits_order             (_mmioBridge_io_tx_req_bits_order),
+    .io_in_1_bits_pCrdType          (_mmioBridge_io_tx_req_bits_pCrdType),
+    .io_in_1_bits_memAttr_allocate  (_mmioBridge_io_tx_req_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable (_mmioBridge_io_tx_req_bits_memAttr_cacheable),
+    .io_in_1_bits_memAttr_device    (_mmioBridge_io_tx_req_bits_memAttr_device),
+    .io_in_1_bits_memAttr_ewa       (_mmioBridge_io_tx_req_bits_memAttr_ewa),
+    .io_in_1_bits_snpAttr           (_mmioBridge_io_tx_req_bits_snpAttr),
+    .io_in_1_bits_lpIDWithPadding   (_mmioBridge_io_tx_req_bits_lpIDWithPadding),
+    .io_in_1_bits_snoopMe           (_mmioBridge_io_tx_req_bits_snoopMe),
+    .io_in_1_bits_expCompAck        (_mmioBridge_io_tx_req_bits_expCompAck),
+    .io_in_1_bits_tagOp             (_mmioBridge_io_tx_req_bits_tagOp),
+    .io_in_1_bits_traceTag          (_mmioBridge_io_tx_req_bits_traceTag),
+    .io_in_1_bits_mpam_perfMonGroup (_mmioBridge_io_tx_req_bits_mpam_perfMonGroup),
+    .io_in_1_bits_mpam_partID       (_mmioBridge_io_tx_req_bits_mpam_partID),
+    .io_in_1_bits_mpam_mpamNS       (_mmioBridge_io_tx_req_bits_mpam_mpamNS),
+    .io_in_1_bits_rsvdc             (_mmioBridge_io_tx_req_bits_rsvdc),
+    .io_out_ready                   (_linkMonitor_io_in_tx_req_ready),
+    .io_out_valid                   (_txreq_arb_io_out_valid),
+    .io_out_bits_qos                (_txreq_arb_io_out_bits_qos),
+    .io_out_bits_tgtID              (_txreq_arb_io_out_bits_tgtID),
+    .io_out_bits_txnID              (_txreq_arb_io_out_bits_txnID),
+    .io_out_bits_returnNID          (_txreq_arb_io_out_bits_returnNID),
+    .io_out_bits_stashNIDValid      (_txreq_arb_io_out_bits_stashNIDValid),
+    .io_out_bits_returnTxnID        (_txreq_arb_io_out_bits_returnTxnID),
+    .io_out_bits_opcode             (_txreq_arb_io_out_bits_opcode),
+    .io_out_bits_size               (_txreq_arb_io_out_bits_size),
+    .io_out_bits_addr               (_txreq_arb_io_out_bits_addr),
+    .io_out_bits_ns                 (_txreq_arb_io_out_bits_ns),
+    .io_out_bits_likelyshared       (_txreq_arb_io_out_bits_likelyshared),
+    .io_out_bits_allowRetry         (_txreq_arb_io_out_bits_allowRetry),
+    .io_out_bits_order              (_txreq_arb_io_out_bits_order),
+    .io_out_bits_pCrdType           (_txreq_arb_io_out_bits_pCrdType),
+    .io_out_bits_memAttr_allocate   (_txreq_arb_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable  (_txreq_arb_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device     (_txreq_arb_io_out_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa        (_txreq_arb_io_out_bits_memAttr_ewa),
+    .io_out_bits_snpAttr            (_txreq_arb_io_out_bits_snpAttr),
+    .io_out_bits_lpIDWithPadding    (_txreq_arb_io_out_bits_lpIDWithPadding),
+    .io_out_bits_snoopMe            (_txreq_arb_io_out_bits_snoopMe),
+    .io_out_bits_expCompAck         (_txreq_arb_io_out_bits_expCompAck),
+    .io_out_bits_tagOp              (_txreq_arb_io_out_bits_tagOp),
+    .io_out_bits_traceTag           (_txreq_arb_io_out_bits_traceTag),
+    .io_out_bits_mpam_perfMonGroup  (_txreq_arb_io_out_bits_mpam_perfMonGroup),
+    .io_out_bits_mpam_partID        (_txreq_arb_io_out_bits_mpam_partID),
+    .io_out_bits_mpam_mpamNS        (_txreq_arb_io_out_bits_mpam_mpamNS),
+    .io_out_bits_rsvdc              (_txreq_arb_io_out_bits_rsvdc)
+  );
+  FastArbiter_26 txrsp_arb (
+    .io_in_0_ready         (_txrsp_arb_io_in_0_ready),
+    .io_in_0_valid         (_slices_0_io_out_tx_rsp_valid),
+    .io_in_0_bits_qos      (_slices_0_io_out_tx_rsp_bits_qos),
+    .io_in_0_bits_tgtID    (_slices_0_io_out_tx_rsp_bits_tgtID),
+    .io_in_0_bits_srcID    (_slices_0_io_out_tx_rsp_bits_srcID),
+    .io_in_0_bits_txnID    (_slices_0_io_out_tx_rsp_bits_txnID),
+    .io_in_0_bits_opcode   (_slices_0_io_out_tx_rsp_bits_opcode),
+    .io_in_0_bits_respErr  (_slices_0_io_out_tx_rsp_bits_respErr),
+    .io_in_0_bits_resp     (_slices_0_io_out_tx_rsp_bits_resp),
+    .io_in_0_bits_fwdState (_slices_0_io_out_tx_rsp_bits_fwdState),
+    .io_in_0_bits_cBusy    (_slices_0_io_out_tx_rsp_bits_cBusy),
+    .io_in_0_bits_dbID     (_slices_0_io_out_tx_rsp_bits_dbID),
+    .io_in_0_bits_pCrdType (_slices_0_io_out_tx_rsp_bits_pCrdType),
+    .io_in_0_bits_tagOp    (_slices_0_io_out_tx_rsp_bits_tagOp),
+    .io_in_0_bits_traceTag (_slices_0_io_out_tx_rsp_bits_traceTag),
+    .io_out_ready          (_linkMonitor_io_in_tx_rsp_ready),
+    .io_out_valid          (_txrsp_arb_io_out_valid),
+    .io_out_bits_qos       (_txrsp_arb_io_out_bits_qos),
+    .io_out_bits_tgtID     (_txrsp_arb_io_out_bits_tgtID),
+    .io_out_bits_srcID     (/* unused */),
+    .io_out_bits_txnID     (_txrsp_arb_io_out_bits_txnID),
+    .io_out_bits_opcode    (_txrsp_arb_io_out_bits_opcode),
+    .io_out_bits_respErr   (_txrsp_arb_io_out_bits_respErr),
+    .io_out_bits_resp      (_txrsp_arb_io_out_bits_resp),
+    .io_out_bits_fwdState  (_txrsp_arb_io_out_bits_fwdState),
+    .io_out_bits_cBusy     (_txrsp_arb_io_out_bits_cBusy),
+    .io_out_bits_dbID      (_txrsp_arb_io_out_bits_dbID),
+    .io_out_bits_pCrdType  (_txrsp_arb_io_out_bits_pCrdType),
+    .io_out_bits_tagOp     (_txrsp_arb_io_out_bits_tagOp),
+    .io_out_bits_traceTag  (_txrsp_arb_io_out_bits_traceTag)
+  );
+  FastArbiter_27 txdat_arb (
+    .clock                   (clock),
+    .reset                   (reset),
+    .io_in_0_ready           (_txdat_arb_io_in_0_ready),
+    .io_in_0_valid           (_slices_0_io_out_tx_dat_valid),
+    .io_in_0_bits_qos        (4'h0),
+    .io_in_0_bits_tgtID      (_slices_0_io_out_tx_dat_bits_tgtID),
+    .io_in_0_bits_srcID      (_slices_0_io_out_tx_dat_bits_srcID),
+    .io_in_0_bits_txnID      (_slices_0_io_out_tx_dat_bits_txnID),
+    .io_in_0_bits_homeNID    (_slices_0_io_out_tx_dat_bits_homeNID),
+    .io_in_0_bits_opcode     (_slices_0_io_out_tx_dat_bits_opcode),
+    .io_in_0_bits_respErr    (_slices_0_io_out_tx_dat_bits_respErr),
+    .io_in_0_bits_resp       (_slices_0_io_out_tx_dat_bits_resp),
+    .io_in_0_bits_dataSource (_slices_0_io_out_tx_dat_bits_dataSource),
+    .io_in_0_bits_cBusy      (3'h0),
+    .io_in_0_bits_dbID       (_slices_0_io_out_tx_dat_bits_dbID),
+    .io_in_0_bits_ccID       (_slices_0_io_out_tx_dat_bits_ccID),
+    .io_in_0_bits_dataID     (_slices_0_io_out_tx_dat_bits_dataID),
+    .io_in_0_bits_tagOp      (2'h0),
+    .io_in_0_bits_tag        (8'h0),
+    .io_in_0_bits_tu         (2'h0),
+    .io_in_0_bits_traceTag   (_slices_0_io_out_tx_dat_bits_traceTag),
+    .io_in_0_bits_rsvdc      (4'h0),
+    .io_in_0_bits_be         (_slices_0_io_out_tx_dat_bits_be),
+    .io_in_0_bits_data       (_slices_0_io_out_tx_dat_bits_data),
+    .io_in_0_bits_dataCheck  (_slices_0_io_out_tx_dat_bits_dataCheck),
+    .io_in_0_bits_poison     (_slices_0_io_out_tx_dat_bits_poison),
+    .io_in_1_ready           (_txdat_arb_io_in_1_ready),
+    .io_in_1_valid           (_mmioBridge_io_tx_dat_valid),
+    .io_in_1_bits_qos        (_mmioBridge_io_tx_dat_bits_qos),
+    .io_in_1_bits_tgtID      (_mmioBridge_io_tx_dat_bits_tgtID),
+    .io_in_1_bits_srcID      (_mmioBridge_io_tx_dat_bits_srcID),
+    .io_in_1_bits_txnID      (_mmioBridge_io_tx_dat_bits_txnID),
+    .io_in_1_bits_homeNID    (_mmioBridge_io_tx_dat_bits_homeNID),
+    .io_in_1_bits_opcode     (_mmioBridge_io_tx_dat_bits_opcode),
+    .io_in_1_bits_respErr    (_mmioBridge_io_tx_dat_bits_respErr),
+    .io_in_1_bits_resp       (_mmioBridge_io_tx_dat_bits_resp),
+    .io_in_1_bits_dataSource (_mmioBridge_io_tx_dat_bits_dataSource),
+    .io_in_1_bits_cBusy      (_mmioBridge_io_tx_dat_bits_cBusy),
+    .io_in_1_bits_dbID       (_mmioBridge_io_tx_dat_bits_dbID),
+    .io_in_1_bits_ccID       (_mmioBridge_io_tx_dat_bits_ccID),
+    .io_in_1_bits_dataID     (_mmioBridge_io_tx_dat_bits_dataID),
+    .io_in_1_bits_tagOp      (_mmioBridge_io_tx_dat_bits_tagOp),
+    .io_in_1_bits_tag        (_mmioBridge_io_tx_dat_bits_tag),
+    .io_in_1_bits_tu         (_mmioBridge_io_tx_dat_bits_tu),
+    .io_in_1_bits_traceTag   (_mmioBridge_io_tx_dat_bits_traceTag),
+    .io_in_1_bits_rsvdc      (_mmioBridge_io_tx_dat_bits_rsvdc),
+    .io_in_1_bits_be         (_mmioBridge_io_tx_dat_bits_be),
+    .io_in_1_bits_data       (_mmioBridge_io_tx_dat_bits_data),
+    .io_in_1_bits_dataCheck  (_mmioBridge_io_tx_dat_bits_dataCheck),
+    .io_in_1_bits_poison     (_mmioBridge_io_tx_dat_bits_poison),
+    .io_out_ready            (_linkMonitor_io_in_tx_dat_ready),
+    .io_out_valid            (_txdat_arb_io_out_valid),
+    .io_out_bits_qos         (_txdat_arb_io_out_bits_qos),
+    .io_out_bits_tgtID       (_txdat_arb_io_out_bits_tgtID),
+    .io_out_bits_srcID       (/* unused */),
+    .io_out_bits_txnID       (_txdat_arb_io_out_bits_txnID),
+    .io_out_bits_homeNID     (_txdat_arb_io_out_bits_homeNID),
+    .io_out_bits_opcode      (_txdat_arb_io_out_bits_opcode),
+    .io_out_bits_respErr     (_txdat_arb_io_out_bits_respErr),
+    .io_out_bits_resp        (_txdat_arb_io_out_bits_resp),
+    .io_out_bits_dataSource  (_txdat_arb_io_out_bits_dataSource),
+    .io_out_bits_cBusy       (_txdat_arb_io_out_bits_cBusy),
+    .io_out_bits_dbID        (_txdat_arb_io_out_bits_dbID),
+    .io_out_bits_ccID        (_txdat_arb_io_out_bits_ccID),
+    .io_out_bits_dataID      (_txdat_arb_io_out_bits_dataID),
+    .io_out_bits_tagOp       (_txdat_arb_io_out_bits_tagOp),
+    .io_out_bits_tag         (_txdat_arb_io_out_bits_tag),
+    .io_out_bits_tu          (_txdat_arb_io_out_bits_tu),
+    .io_out_bits_traceTag    (_txdat_arb_io_out_bits_traceTag),
+    .io_out_bits_rsvdc       (_txdat_arb_io_out_bits_rsvdc),
+    .io_out_bits_be          (_txdat_arb_io_out_bits_be),
+    .io_out_bits_data        (_txdat_arb_io_out_bits_data),
+    .io_out_bits_dataCheck   (_txdat_arb_io_out_bits_dataCheck),
+    .io_out_bits_poison      (_txdat_arb_io_out_bits_poison),
+    .io_chosen               (/* unused */)
+  );
+  Queue30_PCrdGranted pCrdQueue_s2 (
+    .clock                (clock),
+    .reset                (reset),
+    .io_enq_valid         (pCrdGrantValid_s1),
+    .io_enq_bits_pCrdType (pCrdGrantType_s1),
+    .io_enq_bits_srcID    (pCrdGrantSrcID_s1),
+    .io_deq_ready         (_pCrdQueue_s3_io_enq_ready),
+    .io_deq_valid         (_pCrdQueue_s2_io_deq_valid),
+    .io_deq_bits_pCrdType (_pCrdQueue_s2_io_deq_bits_pCrdType),
+    .io_deq_bits_srcID    (_pCrdQueue_s2_io_deq_bits_srcID)
+  );
+  Queue2_PCrdGranted pCrdQueue_s3 (
+    .clock                (clock),
+    .reset                (reset),
+    .io_enq_ready         (_pCrdQueue_s3_io_enq_ready),
+    .io_enq_valid         (_pCrdQueue_s2_io_deq_valid),
+    .io_enq_bits_pCrdType (_pCrdQueue_s2_io_deq_bits_pCrdType),
+    .io_enq_bits_srcID    (_pCrdQueue_s2_io_deq_bits_srcID),
+    .io_deq_ready         (_pcrdgrant_arb_io_out_valid),
+    .io_deq_valid         (_pCrdQueue_s3_io_deq_valid),
+    .io_deq_bits_pCrdType (_pCrdQueue_s3_io_deq_bits_pCrdType),
+    .io_deq_bits_srcID    (_pCrdQueue_s3_io_deq_bits_srcID)
+  );
+  TwoLevelRRArbiter_12 pcrdgrant_arb (
+    .clock          (clock),
+    .reset          (reset),
+    .io_in_0_ready  (_pcrdgrant_arb_io_in_0_ready),
+    .io_in_0_valid
+      (_mmioBridge_io_pCrd_0_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_0_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_0_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_1_ready  (_pcrdgrant_arb_io_in_1_ready),
+    .io_in_1_valid
+      (_mmioBridge_io_pCrd_1_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_1_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_1_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_2_ready  (_pcrdgrant_arb_io_in_2_ready),
+    .io_in_2_valid
+      (_mmioBridge_io_pCrd_2_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_2_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_2_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_3_ready  (_pcrdgrant_arb_io_in_3_ready),
+    .io_in_3_valid
+      (_mmioBridge_io_pCrd_3_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_3_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_3_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_4_ready  (_pcrdgrant_arb_io_in_4_ready),
+    .io_in_4_valid
+      (_mmioBridge_io_pCrd_4_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_4_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_4_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_5_ready  (_pcrdgrant_arb_io_in_5_ready),
+    .io_in_5_valid
+      (_mmioBridge_io_pCrd_5_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_5_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_5_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_6_ready  (_pcrdgrant_arb_io_in_6_ready),
+    .io_in_6_valid
+      (_mmioBridge_io_pCrd_6_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_6_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_6_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_7_ready  (_pcrdgrant_arb_io_in_7_ready),
+    .io_in_7_valid
+      (_mmioBridge_io_pCrd_7_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_7_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_7_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_8_ready  (_pcrdgrant_arb_io_in_8_ready),
+    .io_in_8_valid
+      (_mmioBridge_io_pCrd_8_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_8_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_8_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_9_ready  (_pcrdgrant_arb_io_in_9_ready),
+    .io_in_9_valid
+      (_mmioBridge_io_pCrd_9_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_9_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_9_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_10_ready (_pcrdgrant_arb_io_in_10_ready),
+    .io_in_10_valid
+      (_mmioBridge_io_pCrd_10_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_10_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_10_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_11_ready (_pcrdgrant_arb_io_in_11_ready),
+    .io_in_11_valid
+      (_mmioBridge_io_pCrd_11_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_11_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_11_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_12_ready (_pcrdgrant_arb_io_in_12_ready),
+    .io_in_12_valid
+      (_mmioBridge_io_pCrd_12_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_12_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_12_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_13_ready (_pcrdgrant_arb_io_in_13_ready),
+    .io_in_13_valid
+      (_mmioBridge_io_pCrd_13_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_13_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_13_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_14_ready (_pcrdgrant_arb_io_in_14_ready),
+    .io_in_14_valid
+      (_mmioBridge_io_pCrd_14_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_14_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_14_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_15_ready (_pcrdgrant_arb_io_in_15_ready),
+    .io_in_15_valid
+      (_mmioBridge_io_pCrd_15_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _mmioBridge_io_pCrd_15_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _mmioBridge_io_pCrd_15_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_16_ready (_pcrdgrant_arb_io_in_16_ready),
+    .io_in_16_valid
+      (_slices_0_io_pCrd_0_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_0_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_0_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_17_ready (_pcrdgrant_arb_io_in_17_ready),
+    .io_in_17_valid
+      (_slices_0_io_pCrd_1_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_1_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_1_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_18_ready (_pcrdgrant_arb_io_in_18_ready),
+    .io_in_18_valid
+      (_slices_0_io_pCrd_2_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_2_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_2_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_19_ready (_pcrdgrant_arb_io_in_19_ready),
+    .io_in_19_valid
+      (_slices_0_io_pCrd_3_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_3_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_3_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_20_ready (_pcrdgrant_arb_io_in_20_ready),
+    .io_in_20_valid
+      (_slices_0_io_pCrd_4_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_4_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_4_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_21_ready (_pcrdgrant_arb_io_in_21_ready),
+    .io_in_21_valid
+      (_slices_0_io_pCrd_5_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_5_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_5_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_22_ready (_pcrdgrant_arb_io_in_22_ready),
+    .io_in_22_valid
+      (_slices_0_io_pCrd_6_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_6_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_6_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_23_ready (_pcrdgrant_arb_io_in_23_ready),
+    .io_in_23_valid
+      (_slices_0_io_pCrd_7_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_7_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_7_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_24_ready (_pcrdgrant_arb_io_in_24_ready),
+    .io_in_24_valid
+      (_slices_0_io_pCrd_8_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_8_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_8_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_25_ready (_pcrdgrant_arb_io_in_25_ready),
+    .io_in_25_valid
+      (_slices_0_io_pCrd_9_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_9_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_9_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_26_ready (_pcrdgrant_arb_io_in_26_ready),
+    .io_in_26_valid
+      (_slices_0_io_pCrd_10_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_10_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_10_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_27_ready (_pcrdgrant_arb_io_in_27_ready),
+    .io_in_27_valid
+      (_slices_0_io_pCrd_11_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_11_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_11_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_28_ready (_pcrdgrant_arb_io_in_28_ready),
+    .io_in_28_valid
+      (_slices_0_io_pCrd_12_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_12_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_12_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_29_ready (_pcrdgrant_arb_io_in_29_ready),
+    .io_in_29_valid
+      (_slices_0_io_pCrd_13_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_13_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_13_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_30_ready (_pcrdgrant_arb_io_in_30_ready),
+    .io_in_30_valid
+      (_slices_0_io_pCrd_14_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_14_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_14_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_in_31_ready (_pcrdgrant_arb_io_in_31_ready),
+    .io_in_31_valid
+      (_slices_0_io_pCrd_15_query_valid & _pCrdQueue_s3_io_deq_valid
+       & _slices_0_io_pCrd_15_query_bits_pCrdType == _pCrdQueue_s3_io_deq_bits_pCrdType
+       & _slices_0_io_pCrd_15_query_bits_srcID == _pCrdQueue_s3_io_deq_bits_srcID),
+    .io_out_valid   (_pcrdgrant_arb_io_out_valid)
+  );
+  LinkMonitor linkMonitor (
+    .clock                               (clock),
+    .reset                               (reset),
+    .io_in_tx_req_ready                  (_linkMonitor_io_in_tx_req_ready),
+    .io_in_tx_req_valid                  (_txreq_arb_io_out_valid),
+    .io_in_tx_req_bits_qos               (_txreq_arb_io_out_bits_qos),
+    .io_in_tx_req_bits_tgtID             (_txreq_arb_io_out_bits_tgtID),
+    .io_in_tx_req_bits_txnID
+      ({_txreq_arb_io_in_1_ready & _mmioBridge_io_tx_req_valid,
+        _txreq_arb_io_out_bits_txnID[10:0]}),
+    .io_in_tx_req_bits_returnNID         (_txreq_arb_io_out_bits_returnNID),
+    .io_in_tx_req_bits_stashNIDValid     (_txreq_arb_io_out_bits_stashNIDValid),
+    .io_in_tx_req_bits_returnTxnID       (_txreq_arb_io_out_bits_returnTxnID),
+    .io_in_tx_req_bits_opcode            (_txreq_arb_io_out_bits_opcode),
+    .io_in_tx_req_bits_size              (_txreq_arb_io_out_bits_size),
+    .io_in_tx_req_bits_addr              (_txreq_arb_io_out_bits_addr),
+    .io_in_tx_req_bits_ns                (_txreq_arb_io_out_bits_ns),
+    .io_in_tx_req_bits_likelyshared      (_txreq_arb_io_out_bits_likelyshared),
+    .io_in_tx_req_bits_allowRetry        (_txreq_arb_io_out_bits_allowRetry),
+    .io_in_tx_req_bits_order             (_txreq_arb_io_out_bits_order),
+    .io_in_tx_req_bits_pCrdType          (_txreq_arb_io_out_bits_pCrdType),
+    .io_in_tx_req_bits_memAttr_allocate  (_txreq_arb_io_out_bits_memAttr_allocate),
+    .io_in_tx_req_bits_memAttr_cacheable (_txreq_arb_io_out_bits_memAttr_cacheable),
+    .io_in_tx_req_bits_memAttr_device    (_txreq_arb_io_out_bits_memAttr_device),
+    .io_in_tx_req_bits_memAttr_ewa       (_txreq_arb_io_out_bits_memAttr_ewa),
+    .io_in_tx_req_bits_snpAttr           (_txreq_arb_io_out_bits_snpAttr),
+    .io_in_tx_req_bits_lpIDWithPadding   (_txreq_arb_io_out_bits_lpIDWithPadding),
+    .io_in_tx_req_bits_snoopMe           (_txreq_arb_io_out_bits_snoopMe),
+    .io_in_tx_req_bits_expCompAck        (_txreq_arb_io_out_bits_expCompAck),
+    .io_in_tx_req_bits_tagOp             (_txreq_arb_io_out_bits_tagOp),
+    .io_in_tx_req_bits_traceTag          (_txreq_arb_io_out_bits_traceTag),
+    .io_in_tx_req_bits_mpam_perfMonGroup (_txreq_arb_io_out_bits_mpam_perfMonGroup),
+    .io_in_tx_req_bits_mpam_partID       (_txreq_arb_io_out_bits_mpam_partID),
+    .io_in_tx_req_bits_mpam_mpamNS       (_txreq_arb_io_out_bits_mpam_mpamNS),
+    .io_in_tx_req_bits_rsvdc             (_txreq_arb_io_out_bits_rsvdc),
+    .io_in_tx_rsp_ready                  (_linkMonitor_io_in_tx_rsp_ready),
+    .io_in_tx_rsp_valid                  (_txrsp_arb_io_out_valid),
+    .io_in_tx_rsp_bits_qos               (_txrsp_arb_io_out_bits_qos),
+    .io_in_tx_rsp_bits_tgtID             (_txrsp_arb_io_out_bits_tgtID),
+    .io_in_tx_rsp_bits_txnID             (_txrsp_arb_io_out_bits_txnID),
+    .io_in_tx_rsp_bits_opcode            (_txrsp_arb_io_out_bits_opcode),
+    .io_in_tx_rsp_bits_respErr           (_txrsp_arb_io_out_bits_respErr),
+    .io_in_tx_rsp_bits_resp              (_txrsp_arb_io_out_bits_resp),
+    .io_in_tx_rsp_bits_fwdState          (_txrsp_arb_io_out_bits_fwdState),
+    .io_in_tx_rsp_bits_cBusy             (_txrsp_arb_io_out_bits_cBusy),
+    .io_in_tx_rsp_bits_dbID              (_txrsp_arb_io_out_bits_dbID),
+    .io_in_tx_rsp_bits_pCrdType          (_txrsp_arb_io_out_bits_pCrdType),
+    .io_in_tx_rsp_bits_tagOp             (_txrsp_arb_io_out_bits_tagOp),
+    .io_in_tx_rsp_bits_traceTag          (_txrsp_arb_io_out_bits_traceTag),
+    .io_in_tx_dat_ready                  (_linkMonitor_io_in_tx_dat_ready),
+    .io_in_tx_dat_valid                  (_txdat_arb_io_out_valid),
+    .io_in_tx_dat_bits_qos               (_txdat_arb_io_out_bits_qos),
+    .io_in_tx_dat_bits_tgtID             (_txdat_arb_io_out_bits_tgtID),
+    .io_in_tx_dat_bits_txnID             (_txdat_arb_io_out_bits_txnID),
+    .io_in_tx_dat_bits_homeNID           (_txdat_arb_io_out_bits_homeNID),
+    .io_in_tx_dat_bits_opcode            (_txdat_arb_io_out_bits_opcode),
+    .io_in_tx_dat_bits_respErr           (_txdat_arb_io_out_bits_respErr),
+    .io_in_tx_dat_bits_resp              (_txdat_arb_io_out_bits_resp),
+    .io_in_tx_dat_bits_dataSource        (_txdat_arb_io_out_bits_dataSource),
+    .io_in_tx_dat_bits_cBusy             (_txdat_arb_io_out_bits_cBusy),
+    .io_in_tx_dat_bits_dbID              (_txdat_arb_io_out_bits_dbID),
+    .io_in_tx_dat_bits_ccID              (_txdat_arb_io_out_bits_ccID),
+    .io_in_tx_dat_bits_dataID            (_txdat_arb_io_out_bits_dataID),
+    .io_in_tx_dat_bits_tagOp             (_txdat_arb_io_out_bits_tagOp),
+    .io_in_tx_dat_bits_tag               (_txdat_arb_io_out_bits_tag),
+    .io_in_tx_dat_bits_tu                (_txdat_arb_io_out_bits_tu),
+    .io_in_tx_dat_bits_traceTag          (_txdat_arb_io_out_bits_traceTag),
+    .io_in_tx_dat_bits_rsvdc             (_txdat_arb_io_out_bits_rsvdc),
+    .io_in_tx_dat_bits_be                (_txdat_arb_io_out_bits_be),
+    .io_in_tx_dat_bits_data              (_txdat_arb_io_out_bits_data),
+    .io_in_tx_dat_bits_dataCheck         (_txdat_arb_io_out_bits_dataCheck),
+    .io_in_tx_dat_bits_poison            (_txdat_arb_io_out_bits_poison),
+    .io_in_rx_rsp_ready                  (_rxrspPipe_pipeline_io_in_ready),
+    .io_in_rx_rsp_valid                  (_linkMonitor_io_in_rx_rsp_valid),
+    .io_in_rx_rsp_bits_qos               (_linkMonitor_io_in_rx_rsp_bits_qos),
+    .io_in_rx_rsp_bits_tgtID             (_linkMonitor_io_in_rx_rsp_bits_tgtID),
+    .io_in_rx_rsp_bits_srcID             (_linkMonitor_io_in_rx_rsp_bits_srcID),
+    .io_in_rx_rsp_bits_txnID             (_linkMonitor_io_in_rx_rsp_bits_txnID),
+    .io_in_rx_rsp_bits_opcode            (_linkMonitor_io_in_rx_rsp_bits_opcode),
+    .io_in_rx_rsp_bits_respErr           (_linkMonitor_io_in_rx_rsp_bits_respErr),
+    .io_in_rx_rsp_bits_resp              (_linkMonitor_io_in_rx_rsp_bits_resp),
+    .io_in_rx_rsp_bits_fwdState          (_linkMonitor_io_in_rx_rsp_bits_fwdState),
+    .io_in_rx_rsp_bits_cBusy             (_linkMonitor_io_in_rx_rsp_bits_cBusy),
+    .io_in_rx_rsp_bits_dbID              (_linkMonitor_io_in_rx_rsp_bits_dbID),
+    .io_in_rx_rsp_bits_pCrdType          (_linkMonitor_io_in_rx_rsp_bits_pCrdType),
+    .io_in_rx_rsp_bits_tagOp             (_linkMonitor_io_in_rx_rsp_bits_tagOp),
+    .io_in_rx_rsp_bits_traceTag          (_linkMonitor_io_in_rx_rsp_bits_traceTag),
+    .io_in_rx_dat_ready                  (_rxdatPipe_pipeline_io_in_ready),
+    .io_in_rx_dat_valid                  (_linkMonitor_io_in_rx_dat_valid),
+    .io_in_rx_dat_bits_qos               (_linkMonitor_io_in_rx_dat_bits_qos),
+    .io_in_rx_dat_bits_tgtID             (_linkMonitor_io_in_rx_dat_bits_tgtID),
+    .io_in_rx_dat_bits_srcID             (_linkMonitor_io_in_rx_dat_bits_srcID),
+    .io_in_rx_dat_bits_txnID             (_linkMonitor_io_in_rx_dat_bits_txnID),
+    .io_in_rx_dat_bits_homeNID           (_linkMonitor_io_in_rx_dat_bits_homeNID),
+    .io_in_rx_dat_bits_opcode            (_linkMonitor_io_in_rx_dat_bits_opcode),
+    .io_in_rx_dat_bits_respErr           (_linkMonitor_io_in_rx_dat_bits_respErr),
+    .io_in_rx_dat_bits_resp              (_linkMonitor_io_in_rx_dat_bits_resp),
+    .io_in_rx_dat_bits_dataSource        (_linkMonitor_io_in_rx_dat_bits_dataSource),
+    .io_in_rx_dat_bits_cBusy             (_linkMonitor_io_in_rx_dat_bits_cBusy),
+    .io_in_rx_dat_bits_dbID              (_linkMonitor_io_in_rx_dat_bits_dbID),
+    .io_in_rx_dat_bits_ccID              (_linkMonitor_io_in_rx_dat_bits_ccID),
+    .io_in_rx_dat_bits_dataID            (_linkMonitor_io_in_rx_dat_bits_dataID),
+    .io_in_rx_dat_bits_tagOp             (_linkMonitor_io_in_rx_dat_bits_tagOp),
+    .io_in_rx_dat_bits_tag               (_linkMonitor_io_in_rx_dat_bits_tag),
+    .io_in_rx_dat_bits_tu                (_linkMonitor_io_in_rx_dat_bits_tu),
+    .io_in_rx_dat_bits_traceTag          (_linkMonitor_io_in_rx_dat_bits_traceTag),
+    .io_in_rx_dat_bits_rsvdc             (_linkMonitor_io_in_rx_dat_bits_rsvdc),
+    .io_in_rx_dat_bits_be                (_linkMonitor_io_in_rx_dat_bits_be),
+    .io_in_rx_dat_bits_data              (_linkMonitor_io_in_rx_dat_bits_data),
+    .io_in_rx_dat_bits_dataCheck         (_linkMonitor_io_in_rx_dat_bits_dataCheck),
+    .io_in_rx_dat_bits_poison            (_linkMonitor_io_in_rx_dat_bits_poison),
+    .io_in_rx_snp_ready                  (_slices_0_io_out_rx_snp_ready),
+    .io_in_rx_snp_valid                  (_linkMonitor_io_in_rx_snp_valid),
+    .io_in_rx_snp_bits_qos               (_linkMonitor_io_in_rx_snp_bits_qos),
+    .io_in_rx_snp_bits_srcID             (_linkMonitor_io_in_rx_snp_bits_srcID),
+    .io_in_rx_snp_bits_txnID             (_linkMonitor_io_in_rx_snp_bits_txnID),
+    .io_in_rx_snp_bits_fwdNID            (_linkMonitor_io_in_rx_snp_bits_fwdNID),
+    .io_in_rx_snp_bits_fwdTxnID          (_linkMonitor_io_in_rx_snp_bits_fwdTxnID),
+    .io_in_rx_snp_bits_opcode            (_linkMonitor_io_in_rx_snp_bits_opcode),
+    .io_in_rx_snp_bits_addr              (_linkMonitor_io_in_rx_snp_bits_addr),
+    .io_in_rx_snp_bits_ns                (_linkMonitor_io_in_rx_snp_bits_ns),
+    .io_in_rx_snp_bits_doNotGoToSD       (_linkMonitor_io_in_rx_snp_bits_doNotGoToSD),
+    .io_in_rx_snp_bits_retToSrc          (_linkMonitor_io_in_rx_snp_bits_retToSrc),
+    .io_in_rx_snp_bits_traceTag          (_linkMonitor_io_in_rx_snp_bits_traceTag),
+    .io_in_rx_snp_bits_mpam_perfMonGroup
+      (_linkMonitor_io_in_rx_snp_bits_mpam_perfMonGroup),
+    .io_in_rx_snp_bits_mpam_partID       (_linkMonitor_io_in_rx_snp_bits_mpam_partID),
+    .io_in_rx_snp_bits_mpam_mpamNS       (_linkMonitor_io_in_rx_snp_bits_mpam_mpamNS),
+    .io_out_txsactive                    (io_chi_txsactive),
+    .io_out_rxsactive                    (io_chi_rxsactive),
+    .io_out_syscoreq                     (io_chi_syscoreq),
+    .io_out_syscoack                     (io_chi_syscoack),
+    .io_out_tx_linkactivereq             (io_chi_tx_linkactivereq),
+    .io_out_tx_linkactiveack             (io_chi_tx_linkactiveack),
+    .io_out_tx_req_flitpend              (io_chi_tx_req_flitpend),
+    .io_out_tx_req_flitv                 (io_chi_tx_req_flitv),
+    .io_out_tx_req_flit                  (io_chi_tx_req_flit),
+    .io_out_tx_req_lcrdv                 (io_chi_tx_req_lcrdv),
+    .io_out_tx_rsp_flitpend              (io_chi_tx_rsp_flitpend),
+    .io_out_tx_rsp_flitv                 (io_chi_tx_rsp_flitv),
+    .io_out_tx_rsp_flit                  (io_chi_tx_rsp_flit),
+    .io_out_tx_rsp_lcrdv                 (io_chi_tx_rsp_lcrdv),
+    .io_out_tx_dat_flitpend              (io_chi_tx_dat_flitpend),
+    .io_out_tx_dat_flitv                 (io_chi_tx_dat_flitv),
+    .io_out_tx_dat_flit                  (io_chi_tx_dat_flit),
+    .io_out_tx_dat_lcrdv                 (io_chi_tx_dat_lcrdv),
+    .io_out_rx_linkactivereq             (io_chi_rx_linkactivereq),
+    .io_out_rx_linkactiveack             (io_chi_rx_linkactiveack),
+    .io_out_rx_rsp_flitpend              (io_chi_rx_rsp_flitpend),
+    .io_out_rx_rsp_flitv                 (io_chi_rx_rsp_flitv),
+    .io_out_rx_rsp_flit                  (io_chi_rx_rsp_flit),
+    .io_out_rx_rsp_lcrdv                 (io_chi_rx_rsp_lcrdv),
+    .io_out_rx_dat_flitpend              (io_chi_rx_dat_flitpend),
+    .io_out_rx_dat_flitv                 (io_chi_rx_dat_flitv),
+    .io_out_rx_dat_flit                  (io_chi_rx_dat_flit),
+    .io_out_rx_dat_lcrdv                 (io_chi_rx_dat_lcrdv),
+    .io_out_rx_snp_flitpend              (io_chi_rx_snp_flitpend),
+    .io_out_rx_snp_flitv                 (io_chi_rx_snp_flitv),
+    .io_out_rx_snp_flit                  (io_chi_rx_snp_flit),
+    .io_out_rx_snp_lcrdv                 (io_chi_rx_snp_lcrdv),
+    .io_nodeID                           (io_nodeID)
+  );
+  Pipeline_9 rxdatPipe_pipeline (
+    .clock                  (clock),
+    .reset                  (reset),
+    .io_in_ready            (_rxdatPipe_pipeline_io_in_ready),
+    .io_in_valid            (_linkMonitor_io_in_rx_dat_valid),
+    .io_in_bits_qos         (_linkMonitor_io_in_rx_dat_bits_qos),
+    .io_in_bits_tgtID       (_linkMonitor_io_in_rx_dat_bits_tgtID),
+    .io_in_bits_srcID       (_linkMonitor_io_in_rx_dat_bits_srcID),
+    .io_in_bits_txnID       (_linkMonitor_io_in_rx_dat_bits_txnID),
+    .io_in_bits_homeNID     (_linkMonitor_io_in_rx_dat_bits_homeNID),
+    .io_in_bits_opcode      (_linkMonitor_io_in_rx_dat_bits_opcode),
+    .io_in_bits_respErr     (_linkMonitor_io_in_rx_dat_bits_respErr),
+    .io_in_bits_resp        (_linkMonitor_io_in_rx_dat_bits_resp),
+    .io_in_bits_dataSource  (_linkMonitor_io_in_rx_dat_bits_dataSource),
+    .io_in_bits_cBusy       (_linkMonitor_io_in_rx_dat_bits_cBusy),
+    .io_in_bits_dbID        (_linkMonitor_io_in_rx_dat_bits_dbID),
+    .io_in_bits_ccID        (_linkMonitor_io_in_rx_dat_bits_ccID),
+    .io_in_bits_dataID      (_linkMonitor_io_in_rx_dat_bits_dataID),
+    .io_in_bits_tagOp       (_linkMonitor_io_in_rx_dat_bits_tagOp),
+    .io_in_bits_tag         (_linkMonitor_io_in_rx_dat_bits_tag),
+    .io_in_bits_tu          (_linkMonitor_io_in_rx_dat_bits_tu),
+    .io_in_bits_traceTag    (_linkMonitor_io_in_rx_dat_bits_traceTag),
+    .io_in_bits_rsvdc       (_linkMonitor_io_in_rx_dat_bits_rsvdc),
+    .io_in_bits_be          (_linkMonitor_io_in_rx_dat_bits_be),
+    .io_in_bits_data        (_linkMonitor_io_in_rx_dat_bits_data),
+    .io_in_bits_dataCheck   (_linkMonitor_io_in_rx_dat_bits_dataCheck),
+    .io_in_bits_poison      (_linkMonitor_io_in_rx_dat_bits_poison),
+    .io_out_ready
+      (~(_rxdatPipe_pipeline_io_out_bits_txnID[11]) | _mmioBridge_io_rx_dat_ready),
+    .io_out_valid           (_rxdatPipe_pipeline_io_out_valid),
+    .io_out_bits_qos        (_rxdatPipe_pipeline_io_out_bits_qos),
+    .io_out_bits_tgtID      (_rxdatPipe_pipeline_io_out_bits_tgtID),
+    .io_out_bits_srcID      (_rxdatPipe_pipeline_io_out_bits_srcID),
+    .io_out_bits_txnID      (_rxdatPipe_pipeline_io_out_bits_txnID),
+    .io_out_bits_homeNID    (_rxdatPipe_pipeline_io_out_bits_homeNID),
+    .io_out_bits_opcode     (_rxdatPipe_pipeline_io_out_bits_opcode),
+    .io_out_bits_respErr    (_rxdatPipe_pipeline_io_out_bits_respErr),
+    .io_out_bits_resp       (_rxdatPipe_pipeline_io_out_bits_resp),
+    .io_out_bits_dataSource (_rxdatPipe_pipeline_io_out_bits_dataSource),
+    .io_out_bits_cBusy      (_rxdatPipe_pipeline_io_out_bits_cBusy),
+    .io_out_bits_dbID       (_rxdatPipe_pipeline_io_out_bits_dbID),
+    .io_out_bits_ccID       (_rxdatPipe_pipeline_io_out_bits_ccID),
+    .io_out_bits_dataID     (_rxdatPipe_pipeline_io_out_bits_dataID),
+    .io_out_bits_tagOp      (_rxdatPipe_pipeline_io_out_bits_tagOp),
+    .io_out_bits_tag        (_rxdatPipe_pipeline_io_out_bits_tag),
+    .io_out_bits_tu         (_rxdatPipe_pipeline_io_out_bits_tu),
+    .io_out_bits_traceTag   (_rxdatPipe_pipeline_io_out_bits_traceTag),
+    .io_out_bits_rsvdc      (_rxdatPipe_pipeline_io_out_bits_rsvdc),
+    .io_out_bits_be         (_rxdatPipe_pipeline_io_out_bits_be),
+    .io_out_bits_data       (_rxdatPipe_pipeline_io_out_bits_data),
+    .io_out_bits_dataCheck  (_rxdatPipe_pipeline_io_out_bits_dataCheck),
+    .io_out_bits_poison     (_rxdatPipe_pipeline_io_out_bits_poison)
+  );
+  Pipeline_10 rxrspPipe_pipeline (
+    .clock                (clock),
+    .reset                (reset),
+    .io_in_ready          (_rxrspPipe_pipeline_io_in_ready),
+    .io_in_valid          (_linkMonitor_io_in_rx_rsp_valid),
+    .io_in_bits_qos       (_linkMonitor_io_in_rx_rsp_bits_qos),
+    .io_in_bits_tgtID     (_linkMonitor_io_in_rx_rsp_bits_tgtID),
+    .io_in_bits_srcID     (_linkMonitor_io_in_rx_rsp_bits_srcID),
+    .io_in_bits_txnID     (_linkMonitor_io_in_rx_rsp_bits_txnID),
+    .io_in_bits_opcode    (_linkMonitor_io_in_rx_rsp_bits_opcode),
+    .io_in_bits_respErr   (_linkMonitor_io_in_rx_rsp_bits_respErr),
+    .io_in_bits_resp      (_linkMonitor_io_in_rx_rsp_bits_resp),
+    .io_in_bits_fwdState  (_linkMonitor_io_in_rx_rsp_bits_fwdState),
+    .io_in_bits_cBusy     (_linkMonitor_io_in_rx_rsp_bits_cBusy),
+    .io_in_bits_dbID      (_linkMonitor_io_in_rx_rsp_bits_dbID),
+    .io_in_bits_pCrdType  (_linkMonitor_io_in_rx_rsp_bits_pCrdType),
+    .io_in_bits_tagOp     (_linkMonitor_io_in_rx_rsp_bits_tagOp),
+    .io_in_bits_traceTag  (_linkMonitor_io_in_rx_rsp_bits_traceTag),
+    .io_out_ready
+      (_rxrsp_ready_T | ~(_rxrspPipe_pipeline_io_out_bits_txnID[11])
+       | _mmioBridge_io_rx_rsp_ready),
+    .io_out_valid         (_rxrspPipe_pipeline_io_out_valid),
+    .io_out_bits_qos      (_rxrspPipe_pipeline_io_out_bits_qos),
+    .io_out_bits_tgtID    (_rxrspPipe_pipeline_io_out_bits_tgtID),
+    .io_out_bits_srcID    (_rxrspPipe_pipeline_io_out_bits_srcID),
+    .io_out_bits_txnID    (_rxrspPipe_pipeline_io_out_bits_txnID),
+    .io_out_bits_opcode   (_rxrspPipe_pipeline_io_out_bits_opcode),
+    .io_out_bits_respErr  (_rxrspPipe_pipeline_io_out_bits_respErr),
+    .io_out_bits_resp     (_rxrspPipe_pipeline_io_out_bits_resp),
+    .io_out_bits_fwdState (_rxrspPipe_pipeline_io_out_bits_fwdState),
+    .io_out_bits_cBusy    (_rxrspPipe_pipeline_io_out_bits_cBusy),
+    .io_out_bits_dbID     (_rxrspPipe_pipeline_io_out_bits_dbID),
+    .io_out_bits_pCrdType (_rxrspPipe_pipeline_io_out_bits_pCrdType),
+    .io_out_bits_tagOp    (_rxrspPipe_pipeline_io_out_bits_tagOp),
+    .io_out_bits_traceTag (_rxrspPipe_pipeline_io_out_bits_traceTag)
+  );
+  Arbiter1_L2CacheErrorInfo l2ECCArb (
+    .io_in_0_valid        (_slices_0_io_error_valid),
+    .io_in_0_bits_valid   (_slices_0_io_error_bits_valid),
+    .io_in_0_bits_address (_slices_0_io_error_bits_address),
+    .io_out_valid         (_l2ECCArb_io_out_valid),
+    .io_out_bits_valid    (_l2ECCArb_io_out_bits_valid),
+    .io_out_bits_address  (io_error_address)
+  );
+  L2Cache mbistPl (
+    .clock                    (clock),
+    .reset                    (reset),
+    .mbist_array              (_l2MbistIntf_toPipeline_0_array),
+    .mbist_all                (_l2MbistIntf_toPipeline_0_all),
+    .mbist_req                (_l2MbistIntf_toPipeline_0_req),
+    .mbist_ack                (_mbistPl_mbist_ack),
+    .mbist_writeen            (_l2MbistIntf_toPipeline_0_writeen),
+    .mbist_be                 (_l2MbistIntf_toPipeline_0_be),
+    .mbist_addr               (_l2MbistIntf_toPipeline_0_addr),
+    .mbist_indata             (_l2MbistIntf_toPipeline_0_indata),
+    .mbist_readen             (_l2MbistIntf_toPipeline_0_readen),
+    .mbist_addr_rd            (_l2MbistIntf_toPipeline_0_addr_rd),
+    .mbist_outdata            (_mbistPl_mbist_outdata),
+    .toNextPipeline_0_array   (childBd_array),
+    .toNextPipeline_0_all     (childBd_all),
+    .toNextPipeline_0_req     (childBd_req),
+    .toNextPipeline_0_ack     (childBd_ack),
+    .toNextPipeline_0_writeen (childBd_writeen),
+    .toNextPipeline_0_be      (childBd_be),
+    .toNextPipeline_0_addr    (childBd_addr),
+    .toNextPipeline_0_indata  (childBd_indata),
+    .toNextPipeline_0_readen  (childBd_readen),
+    .toNextPipeline_0_addr_rd (childBd_addr_rd),
+    .toNextPipeline_0_outdata (childBd_outdata),
+    .toNextPipeline_1_array   (childBd_1_array),
+    .toNextPipeline_1_all     (childBd_1_all),
+    .toNextPipeline_1_req     (childBd_1_req),
+    .toNextPipeline_1_ack     (childBd_1_ack),
+    .toNextPipeline_1_writeen (childBd_1_writeen),
+    .toNextPipeline_1_be      (childBd_1_be),
+    .toNextPipeline_1_addr    (childBd_1_addr),
+    .toNextPipeline_1_indata  (childBd_1_indata),
+    .toNextPipeline_1_readen  (childBd_1_readen),
+    .toNextPipeline_1_addr_rd (childBd_1_addr_rd),
+    .toNextPipeline_1_outdata (childBd_1_outdata)
+  );
+  wire         bd_ack;
+  assign bd_ack = _mbistPl_mbist_ack;
+  wire [163:0] bd_outdata;
+  assign bd_outdata = _mbistPl_mbist_outdata;
+  MbistIntfL2 l2MbistIntf (
+    .toPipeline_0_array   (_l2MbistIntf_toPipeline_0_array),
+    .toPipeline_0_all     (_l2MbistIntf_toPipeline_0_all),
+    .toPipeline_0_req     (_l2MbistIntf_toPipeline_0_req),
+    .toPipeline_0_ack     (_mbistPl_mbist_ack),
+    .toPipeline_0_writeen (_l2MbistIntf_toPipeline_0_writeen),
+    .toPipeline_0_be      (_l2MbistIntf_toPipeline_0_be),
+    .toPipeline_0_addr    (_l2MbistIntf_toPipeline_0_addr),
+    .toPipeline_0_indata  (_l2MbistIntf_toPipeline_0_indata),
+    .toPipeline_0_readen  (_l2MbistIntf_toPipeline_0_readen),
+    .toPipeline_0_addr_rd (_l2MbistIntf_toPipeline_0_addr_rd),
+    .toPipeline_0_outdata (_mbistPl_mbist_outdata),
+    .mbist_array          (4'h0),
+    .mbist_all            (1'h0),
+    .mbist_req            (1'h0),
+    .mbist_ack            (/* unused */),
+    .mbist_writeen        (1'h0),
+    .mbist_be             (8'h0),
+    .mbist_addr           (12'h0),
+    .mbist_indata         (164'h0),
+    .mbist_readen         (1'h0),
+    .mbist_addr_rd        (12'h0),
+    .mbist_outdata        (/* unused */)
+  );
+  assign auto_in_d_valid = _slices_0_io_in_d_valid & _slice_io_in_d_ready_T;
+  assign io_l2_hint_valid = hintChosenVec_0_valid & _slices_0_io_l1Hint_bits_hasData;
+  assign io_l2_hint_bits_sourceId = _slices_0_io_l1Hint_bits_sourceId;
+  assign io_l2Miss = io_l2Miss_REG;
+  assign io_error_valid = _l2ECCArb_io_out_valid & _l2ECCArb_io_out_bits_valid;
+  assign io_perf_1_value = io_perf_1_value_REG_1;
+  assign io_perf_2_value = io_perf_2_value_REG_1;
+  assign io_perf_4_value = io_perf_4_value_REG_1;
+  assign io_perf_5_value = io_perf_5_value_REG_1;
+  assign io_perf_6_value = io_perf_6_value_REG_1;
+  assign io_perf_7_value = io_perf_7_value_REG_1;
+  assign io_perf_8_value = io_perf_8_value_REG_1;
+  assign io_perf_9_value = io_perf_9_value_REG_1;
+  assign io_perf_10_value = io_perf_10_value_REG_1;
+  assign io_perf_11_value = io_perf_11_value_REG_1;
+  assign io_perf_12_value = io_perf_12_value_REG_1;
+  assign io_perf_13_value = io_perf_13_value_REG_1;
+  assign io_perf_14_value = io_perf_14_value_REG_1;
+  assign io_perf_15_value = io_perf_15_value_REG_1;
+  assign io_perf_16_value = io_perf_16_value_REG_1;
+  assign io_perf_17_value = io_perf_17_value_REG_1;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/LICENSES/Chisel-Apache-2.0.txt b/flow/designs/src/xiangshan_coupledl2/LICENSES/Chisel-Apache-2.0.txt
new file mode 100644
index 0000000000..c6d9f269e6
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/LICENSES/Chisel-Apache-2.0.txt
@@ -0,0 +1,183 @@
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
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+          the Derivative Works; and
+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   ------------------------------------------------------------------------
+   Note:
+   Individual files contain the following tag instead of the full license text.
+
+   // SPDX-License-Identifier: Apache-2.0
diff --git a/flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XSCache-MulanPSL-2.0.txt b/flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XSCache-MulanPSL-2.0.txt
new file mode 100644
index 0000000000..68d8753110
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XSCache-MulanPSL-2.0.txt
@@ -0,0 +1,132 @@
+
+                     木兰宽松许可证, 第2版
+
+   木兰宽松许可证， 第2版
+   2020年1月 http://license.coscl.org.cn/MulanPSL2
+
+
+   您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束：
+
+   0. 定义
+
+      “软件”是指由“贡献”构成的许可在“本许可证”下的程序和相关文档的集合。
+
+      “贡献”是指由任一“贡献者”许可在“本许可证”下的受版权法保护的作品。
+
+      “贡献者”是指将受版权法保护的作品许可在“本许可证”下的自然人或“法人实体”。
+
+      “法人实体”是指提交贡献的机构及其“关联实体”。
+
+      “关联实体”是指，对“本许可证”下的行为方而言，控制、受控制或与其共同受控制的机构，此处的控制是指有受控方或共同受控方至少50%直接或间接的投票权、资金或其他有价证券。
+
+   1. 授予版权许可
+
+      每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的版权许可，您可以复制、使用、修改、分发其“贡献”，不论修改与否。
+
+   2. 授予专利许可
+
+      每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的（根据本条规定撤销除外）专利许可，供您制造、委托制造、使用、许诺销售、销售、进口其“贡献”或以其他方式转移其“贡献”。前述专利许可仅限于“贡献者”现在或将来拥有或控制的其“贡献”本身或其“贡献”与许可“贡献”时的“软件”结合而将必然会侵犯的专利权利要求，不包括对“贡献”的修改或包含“贡献”的其他结合。如果您或您的“关联实体”直接或间接地，就“软件”或其中的“贡献”对任何人发起专利侵权诉讼（包括反诉或交叉诉讼）或其他专利维权行动，指控其侵犯专利权，则“本许可证”授予您对“软件”的专利许可自您提起诉讼或发起维权行动之日终止。
+
+   3. 无商标许可
+
+      “本许可证”不提供对“贡献者”的商品名称、商标、服务标志或产品名称的商标许可，但您为满足第4条规定的声明义务而必须使用除外。
+
+   4. 分发限制
+
+      您可以在任何媒介中将“软件”以源程序形式或可执行形式重新分发，不论修改与否，但您必须向接收者提供“本许可证”的副本，并保留“软件”中的版权、商标、专利及免责声明。
+
+   5. 免责声明与责任限制
+
+      “软件”及其中的“贡献”在提供时不带任何明示或默示的担保。在任何情况下，“贡献者”或版权所有者不对任何人因使用“软件”或其中的“贡献”而引发的任何直接或间接损失承担责任，不论因何种原因导致或者基于何种法律理论，即使其曾被建议有此种损失的可能性。
+
+   6. 语言
+      “本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文版为准。
+
+   条款结束
+
+   如何将木兰宽松许可证，第2版，应用到您的软件
+
+   如果您希望将木兰宽松许可证，第2版，应用到您的新软件，为了方便接收者查阅，建议您完成如下三步：
+
+      1， 请您补充如下声明中的空白，包括软件名、软件的首次发表年份以及您作为版权人的名字；
+
+      2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中；
+
+      3， 请将如下声明文本放入每个源文件的头部注释中。
+
+   Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
+   Copyright (c) 2020-2021 Peng Cheng Laboratory
+
+   XiangShan is licensed under Mulan PSL v2.
+   You can use this software according to the terms and conditions of the Mulan PSL v2.
+   You may obtain a copy of Mulan PSL v2 at:
+            http://license.coscl.org.cn/MulanPSL2
+   THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+   See the Mulan PSL v2 for more details.
+
+
+                     Mulan Permissive Software License，Version 2
+
+   Mulan Permissive Software License，Version 2 (Mulan PSL v2)
+   January 2020 http://license.coscl.org.cn/MulanPSL2
+
+   Your reproduction, use, modification and distribution of the Software shall be subject to Mulan PSL v2 (this License) with the following terms and conditions:
+
+   0. Definition
+
+      Software means the program and related documents which are licensed under this License and comprise all Contribution(s).
+
+      Contribution means the copyrightable work licensed by a particular Contributor under this License.
+
+      Contributor means the Individual or Legal Entity who licenses its copyrightable work under this License.
+
+      Legal Entity means the entity making a Contribution and all its Affiliates.
+
+      Affiliates means entities that control, are controlled by, or are under common control with the acting entity under this License, ‘control’ means direct or indirect ownership of at least fifty percent (50%) of the voting power, capital or other securities of controlled or commonly controlled entity.
+
+   1. Grant of Copyright License
+
+      Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable copyright license to reproduce, use, modify, or distribute its Contribution, with modification or not.
+
+   2. Grant of Patent License
+
+      Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable (except for revocation under this Section) patent license to make, have made, use, offer for sale, sell, import or otherwise transfer its Contribution, where such patent license is only limited to the patent claims owned or controlled by such Contributor now or in future which will be necessarily infringed by its Contribution alone, or by combination of the Contribution with the Software to which the Contribution was contributed. The patent license shall not apply to any modification of the Contribution, and any other combination which includes the Contribution. If you or your Affiliates directly or indirectly institute patent litigation (including a cross claim or counterclaim in a litigation) or other patent enforcement activities against any individual or entity by alleging that the Software or any Contribution in it infringes patents, then any patent license granted to you under this License for the Software shall terminate as of the date such litigation or activity is filed or taken.
+
+   3. No Trademark License
+
+      No trademark license is granted to use the trade names, trademarks, service marks, or product names of Contributor, except as required to fulfill notice requirements in Section 4.
+
+   4. Distribution Restriction
+
+      You may distribute the Software in any medium with or without modification, whether in source or executable forms, provided that you provide recipients with a copy of this License and retain copyright, patent, trademark and disclaimer statements in the Software.
+
+   5. Disclaimer of Warranty and Limitation of Liability
+
+      THE SOFTWARE AND CONTRIBUTION IN IT ARE PROVIDED WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED. IN NO EVENT SHALL ANY CONTRIBUTOR OR COPYRIGHT HOLDER BE LIABLE TO YOU FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO ANY DIRECT, OR INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING FROM YOUR USE OR INABILITY TO USE THE SOFTWARE OR THE CONTRIBUTION IN IT, NO MATTER HOW IT’S CAUSED OR BASED ON WHICH LEGAL THEORY, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+   6. Language
+
+      THIS LICENSE IS WRITTEN IN BOTH CHINESE AND ENGLISH, AND THE CHINESE VERSION AND ENGLISH VERSION SHALL HAVE THE SAME LEGAL EFFECT. IN THE CASE OF DIVERGENCE BETWEEN THE CHINESE AND ENGLISH VERSIONS, THE CHINESE VERSION SHALL PREVAIL.
+
+   END OF THE TERMS AND CONDITIONS
+
+   How to Apply the Mulan Permissive Software License，Version 2 (Mulan PSL v2) to Your Software
+
+      To apply the Mulan PSL v2 to your work, for easy identification by recipients, you are suggested to complete following three steps:
+
+      i Fill in the blanks in following statement, including insert your software name, the year of the first publication of your software, and your name identified as the copyright owner;
+
+      ii Create a file named “LICENSE” which contains the whole context of this License in the first directory of your software package;
+
+      iii Attach the statement to the appropriate annotated syntax at the beginning of each source file.
+
+
+   Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
+   Copyright (c) 2020-2021 Peng Cheng Laboratory
+
+   XiangShan is licensed under Mulan PSL v2.
+   You can use this software according to the terms and conditions of the Mulan PSL v2.
+   You may obtain a copy of Mulan PSL v2 at:
+               http://license.coscl.org.cn/MulanPSL2
+   THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+   See the Mulan PSL v2 for more details.
\ No newline at end of file
diff --git a/flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XSCache-SiFive-Apache-2.0.txt b/flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XSCache-SiFive-Apache-2.0.txt
new file mode 100644
index 0000000000..7e70933754
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XSCache-SiFive-Apache-2.0.txt
@@ -0,0 +1,202 @@
+
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
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+      "Source" form shall mean the preferred form for making modifications,
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+      source, and configuration files.
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+      "Object" form shall mean any form resulting from mechanical
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+
+      "Work" shall mean the work of authorship, whether in Source or
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+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
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+      the Work and Derivative Works thereof.
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+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
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+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
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+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
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+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
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+      or a Contribution incorporated within the Work constitutes direct
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+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
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+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
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+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
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+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
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+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "[]"
+      replaced with your own identifying information. (Don't include
+      the brackets!)  The text should be enclosed in the appropriate
+      comment syntax for the file format. We also recommend that a
+      file or class name and description of purpose be included on the
+      same "printed page" as the copyright notice for easier
+      identification within third-party archives.
+
+   Copyright 2016-2017 SiFive, Inc.
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
diff --git a/flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XiangShan-MulanPSL-2.0.txt b/flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XiangShan-MulanPSL-2.0.txt
new file mode 100644
index 0000000000..f167963277
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/LICENSES/OpenXiangShan-XiangShan-MulanPSL-2.0.txt
@@ -0,0 +1,127 @@
+                     木兰宽松许可证, 第2版
+
+   木兰宽松许可证， 第2版
+   2020年1月 http://license.coscl.org.cn/MulanPSL2
+
+
+   您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束：
+
+   0. 定义
+
+      “软件”是指由“贡献”构成的许可在“本许可证”下的程序和相关文档的集合。
+
+      “贡献”是指由任一“贡献者”许可在“本许可证”下的受版权法保护的作品。
+
+      “贡献者”是指将受版权法保护的作品许可在“本许可证”下的自然人或“法人实体”。
+
+      “法人实体”是指提交贡献的机构及其“关联实体”。
+
+      “关联实体”是指，对“本许可证”下的行为方而言，控制、受控制或与其共同受控制的机构，此处的控制是指有受控方或共同受控方至少50%直接或间接的投票权、资金或其他有价证券。
+
+   1. 授予版权许可
+
+      每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的版权许可，您可以复制、使用、修改、分发其“贡献”，不论修改与否。
+
+   2. 授予专利许可
+
+      每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的（根据本条规定撤销除外）专利许可，供您制造、委托制造、使用、许诺销售、销售、进口其“贡献”或以其他方式转移其“贡献”。前述专利许可仅限于“贡献者”现在或将来拥有或控制的其“贡献”本身或其“贡献”与许可“贡献”时的“软件”结合而将必然会侵犯的专利权利要求，不包括对“贡献”的修改或包含“贡献”的其他结合。如果您或您的“关联实体”直接或间接地，就“软件”或其中的“贡献”对任何人发起专利侵权诉讼（包括反诉或交叉诉讼）或其他专利维权行动，指控其侵犯专利权，则“本许可证”授予您对“软件”的专利许可自您提起诉讼或发起维权行动之日终止。
+
+   3. 无商标许可
+
+      “本许可证”不提供对“贡献者”的商品名称、商标、服务标志或产品名称的商标许可，但您为满足第4条规定的声明义务而必须使用除外。
+
+   4. 分发限制
+
+      您可以在任何媒介中将“软件”以源程序形式或可执行形式重新分发，不论修改与否，但您必须向接收者提供“本许可证”的副本，并保留“软件”中的版权、商标、专利及免责声明。
+
+   5. 免责声明与责任限制
+
+      “软件”及其中的“贡献”在提供时不带任何明示或默示的担保。在任何情况下，“贡献者”或版权所有者不对任何人因使用“软件”或其中的“贡献”而引发的任何直接或间接损失承担责任，不论因何种原因导致或者基于何种法律理论，即使其曾被建议有此种损失的可能性。
+
+   6. 语言
+      “本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文版为准。
+
+   条款结束
+
+   如何将木兰宽松许可证，第2版，应用到您的软件
+
+   如果您希望将木兰宽松许可证，第2版，应用到您的新软件，为了方便接收者查阅，建议您完成如下三步：
+
+      1， 请您补充如下声明中的空白，包括软件名、软件的首次发表年份以及您作为版权人的名字；
+
+      2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中；
+
+      3， 请将如下声明文本放入每个源文件的头部注释中。
+
+   Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
+   XiangShan is licensed under Mulan PSL v2.
+   You can use this software according to the terms and conditions of the Mulan PSL v2.
+   You may obtain a copy of Mulan PSL v2 at:
+            http://license.coscl.org.cn/MulanPSL2
+   THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+   See the Mulan PSL v2 for more details.
+
+
+                     Mulan Permissive Software License，Version 2
+
+   Mulan Permissive Software License，Version 2 (Mulan PSL v2)
+   January 2020 http://license.coscl.org.cn/MulanPSL2
+
+   Your reproduction, use, modification and distribution of the Software shall be subject to Mulan PSL v2 (this License) with the following terms and conditions:
+
+   0. Definition
+
+      Software means the program and related documents which are licensed under this License and comprise all Contribution(s).
+
+      Contribution means the copyrightable work licensed by a particular Contributor under this License.
+
+      Contributor means the Individual or Legal Entity who licenses its copyrightable work under this License.
+
+      Legal Entity means the entity making a Contribution and all its Affiliates.
+
+      Affiliates means entities that control, are controlled by, or are under common control with the acting entity under this License, ‘control’ means direct or indirect ownership of at least fifty percent (50%) of the voting power, capital or other securities of controlled or commonly controlled entity.
+
+   1. Grant of Copyright License
+
+      Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable copyright license to reproduce, use, modify, or distribute its Contribution, with modification or not.
+
+   2. Grant of Patent License
+
+      Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable (except for revocation under this Section) patent license to make, have made, use, offer for sale, sell, import or otherwise transfer its Contribution, where such patent license is only limited to the patent claims owned or controlled by such Contributor now or in future which will be necessarily infringed by its Contribution alone, or by combination of the Contribution with the Software to which the Contribution was contributed. The patent license shall not apply to any modification of the Contribution, and any other combination which includes the Contribution. If you or your Affiliates directly or indirectly institute patent litigation (including a cross claim or counterclaim in a litigation) or other patent enforcement activities against any individual or entity by alleging that the Software or any Contribution in it infringes patents, then any patent license granted to you under this License for the Software shall terminate as of the date such litigation or activity is filed or taken.
+
+   3. No Trademark License
+
+      No trademark license is granted to use the trade names, trademarks, service marks, or product names of Contributor, except as required to fulfill notice requirements in Section 4.
+
+   4. Distribution Restriction
+
+      You may distribute the Software in any medium with or without modification, whether in source or executable forms, provided that you provide recipients with a copy of this License and retain copyright, patent, trademark and disclaimer statements in the Software.
+
+   5. Disclaimer of Warranty and Limitation of Liability
+
+      THE SOFTWARE AND CONTRIBUTION IN IT ARE PROVIDED WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED. IN NO EVENT SHALL ANY CONTRIBUTOR OR COPYRIGHT HOLDER BE LIABLE TO YOU FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO ANY DIRECT, OR INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING FROM YOUR USE OR INABILITY TO USE THE SOFTWARE OR THE CONTRIBUTION IN IT, NO MATTER HOW IT’S CAUSED OR BASED ON WHICH LEGAL THEORY, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+   6. Language
+
+      THIS LICENSE IS WRITTEN IN BOTH CHINESE AND ENGLISH, AND THE CHINESE VERSION AND ENGLISH VERSION SHALL HAVE THE SAME LEGAL EFFECT. IN THE CASE OF DIVERGENCE BETWEEN THE CHINESE AND ENGLISH VERSIONS, THE CHINESE VERSION SHALL PREVAIL.
+
+   END OF THE TERMS AND CONDITIONS
+
+   How to Apply the Mulan Permissive Software License，Version 2 (Mulan PSL v2) to Your Software
+
+      To apply the Mulan PSL v2 to your work, for easy identification by recipients, you are suggested to complete following three steps:
+
+      i Fill in the blanks in following statement, including insert your software name, the year of the first publication of your software, and your name identified as the copyright owner;
+
+      ii Create a file named “LICENSE” which contains the whole context of this License in the first directory of your software package;
+
+      iii Attach the statement to the appropriate annotated syntax at the beginning of each source file.
+
+
+   Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
+   XiangShan is licensed under Mulan PSL v2.
+   You can use this software according to the terms and conditions of the Mulan PSL v2.
+   You may obtain a copy of Mulan PSL v2 at:
+               http://license.coscl.org.cn/MulanPSL2
+   THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+   See the Mulan PSL v2 for more details.
\ No newline at end of file
diff --git a/flow/designs/src/xiangshan_coupledl2/LICENSES/README.md b/flow/designs/src/xiangshan_coupledl2/LICENSES/README.md
new file mode 100644
index 0000000000..40110a8ee8
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/LICENSES/README.md
@@ -0,0 +1,16 @@
+# License map
+
+- `OpenXiangShan-XiangShan-MulanPSL-2.0.txt`: exact XiangShan root license at
+  `96c3f568f943a096ffd3d712dc6f462ac4b1ba33`.
+- `OpenXiangShan-XSCache-MulanPSL-2.0.txt`: exact XSCache root license at
+  `54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f`.
+- `OpenXiangShan-XSCache-SiFive-Apache-2.0.txt`: the exact additional license
+  referenced by `CoupledL2.scala` at that XSCache pin.
+- `Chisel-Apache-2.0.txt`: exact Chisel v7.3.0 root license.
+- `VLSIDA-bsg_fakeram-BSD-3-Clause.txt`: exact license for the pinned macro
+  generator used to reconstruct the SRAM boundaries.
+
+Utility `bab34605babce74732f7f441c5d126a0869285bd` has no root license file.
+Every Utility source responsible for a selected generated module has a Mulan
+PSL v2 per-file notice; the complete source-to-module and license mapping is
+in `../PROVENANCE/selected-rtl.tsv`.
diff --git a/flow/designs/src/xiangshan_coupledl2/LICENSES/VLSIDA-bsg_fakeram-BSD-3-Clause.txt b/flow/designs/src/xiangshan_coupledl2/LICENSES/VLSIDA-bsg_fakeram-BSD-3-Clause.txt
new file mode 100644
index 0000000000..a179727372
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/LICENSES/VLSIDA-bsg_fakeram-BSD-3-Clause.txt
@@ -0,0 +1,29 @@
+BSD 3-Clause License
+
+Copyright (c) 2019, Bespoke Silicon Group
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/flow/designs/src/xiangshan_coupledl2/PROVENANCE/selected-rtl.tsv b/flow/designs/src/xiangshan_coupledl2/PROVENANCE/selected-rtl.tsv
new file mode 100644
index 0000000000..f7f41ce0ff
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/PROVENANCE/selected-rtl.tsv
@@ -0,0 +1,139 @@
+case_path	generator_sha256	packaged_sha256	packaging_transform	archive_member	archive_byte_match	pair_byte_match	origin	source_pin	source_locator	license_basis
+RTL/deps/MMIOBridgeEntry.sv	2e42acb5aec9768a50a0c344826efd82b103b455be86de5a2947c5de45e4c999	1a9a2f964a6aa9082169c4623566ff316a89f95adcaced6d8a974ac379a2b39b	trim-extra-eof-newline	./MMIOBridgeEntry.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MMIOBridge.scala:69:7	Mulan-PSL-2.0
+RTL/deps/MMIOBridgeEntry_2.sv	9ef3866571120ad0f22a887e81ef9c4f890984a88edac34ff002f7c7df36fd5f	12fe6c610e6e9d534fb07f52e9b2c46d18237aa4316ad5233bb0d8da0df5b200	trim-extra-eof-newline	./MMIOBridgeEntry_2.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MMIOBridge.scala:69:7	Mulan-PSL-2.0
+RTL/deps/MMIOBridgeEntry_4.sv	f60438e273af3077b67e3aa856b907c82bf874b5834134b07c343c76307c47f4	2977343a0fe51f8916a8298f1700181898e97adba8b15410c0ace976081363d3	trim-extra-eof-newline	./MMIOBridgeEntry_4.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MMIOBridge.scala:69:7	Mulan-PSL-2.0
+RTL/deps/MMIOBridgeEntry_8.sv	b628c9e7918c02f29dbb5a5310dea5e6205814b1ff915013159b6394cf46cb99	109332558f61e60653c1dbe7821b7893f9e037da1f3d0628207d73c60d37313b	trim-extra-eof-newline	./MMIOBridgeEntry_8.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MMIOBridge.scala:69:7	Mulan-PSL-2.0
+RTL/deps/FastArbiter_2.sv	a51cc590d8f32b4345d221006da7b29d51258a9bae7d5407d58f92f72373eedc	d008127dc7cd23b204041e601dedac1e1c74c27724d77bd0867c31c2559cb080	trim-extra-eof-newline	./FastArbiter_2.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_1.sv	f93e3f1f653ac742f83cf54a13a40f27512327797748999e459ca8552fe7d679	691a7844ba3fd8a281dc36eddd8c7daef00e95dbfa79159042b0d3d05afa8f27	trim-extra-eof-newline	./TwoLevelRRArbiter_1.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Arbiter16_CHIDAT.sv	d6c5806657ffeb6f9bb45c853712af17d2fda276656732fc86dcd3ef740fd5c8	61cedf8d43d55d6c3065cf921596d4802655b616ff220c5cbaca0ef6ffd77df0	trim-extra-eof-newline	./Arbiter16_CHIDAT.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Arbiter.scala:149:7	Apache-2.0
+RTL/deps/Arbiter16_TLBundleD.sv	783a9534dc494bdd5e870884d691493b42fd723c55104135dc0f2954dee8807f	1708613f3168f82426263a25477acb15e41fa50ef8c24c7e914cd4e85ff08a77	trim-extra-eof-newline	./Arbiter16_TLBundleD.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Arbiter.scala:149:7	Apache-2.0
+RTL/deps/MMIOBridge.sv	56bcdd4209c058bca6e52db8f8fb8b0d4ad407ed8b06ddc8aa598fe7063c5ee4	2f3f21678b64c6d2da17924d7653f0013973e90a9828e79dc8f99406bfba1805	trim-extra-eof-newline	./MMIOBridge.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MMIOBridge.scala:345:7	Mulan-PSL-2.0
+RTL/deps/DelayQueue.sv	c007063b555340293d6d3e035b283a0f1e494dea28ce81280f302aab23669961	aeca61575e71cc1ac30cc86434ee91941144a5532183c18002852fc0f2da6564	trim-extra-eof-newline	./DelayQueue.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala:612:7	Mulan-PSL-2.0
+RTL/deps/sram_array_1p256x13m13s1h0l1b_l2_pftch_rrt.sv	1fc290cf8f5b13a3b4395ff023625111a67cb1a65f6dca5690598535386ca3d3	48b83dd3dd32d90b5d1a150578adae43625526f35bc2e42b8f5fce733832b1d8	trim-extra-eof-newline	./sram_array_1p256x13m13s1h0l1b_l2_pftch_rrt.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SramProto.scala:99:2	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SRAMTemplate_239.sv	2f91c768256c0bbab81a39eeafcd744068dad5ce7df8ca65929236283175e76b	293a772bff66890a77fe079d7d6c46042de610aedafea95e8759a265102eeb79	trim-extra-eof-newline	./SRAMTemplate_239.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SRAMTemplate.scala:203:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/RecentRequestTable.sv	7c215d84a0bd7c16c85422ef465fa592b65dbdcab9b3dee6a02607df42cfacf1	8569a0206d6642e755835199a5f0c0f925dcc4e954e023e3b82f76e02b8e1ea3	trim-extra-eof-newline	./RecentRequestTable.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala:152:7	Mulan-PSL-2.0
+RTL/deps/OffsetScoreTable.sv	18c3bbb783e472d4f1d2234d2a45f5f5e71e0b35770de865abbb97a0c1deaf94	c84b02ffc6ebf80b17c28a9d59a1882502cfbf5161329d3a5a836e645bf9ec41	trim-extra-eof-newline	./OffsetScoreTable.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala:226:7	Mulan-PSL-2.0
+RTL/deps/PBestOffsetPrefetch.sv	33deaaef81d6bdc0c8d3af8b1cadd47b6dcd9fe8b5f95fb70869f17ff846eef7	b6bb709e0261710632f0238e171e5bd38802b32f44006c3e47cf99d278440334	trim-extra-eof-newline	./PBestOffsetPrefetch.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala:812:7	Mulan-PSL-2.0
+RTL/deps/DelayQueue_1.sv	d59740394465cc70adecf083135acbb0da27136f2bdd7de7157f04e4c616f816	44f8bba3119250ca750047f0d389431afc43618121dbdc1bafde06f1e0f0e886	trim-extra-eof-newline	./DelayQueue_1.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala:612:7	Mulan-PSL-2.0
+RTL/deps/RecentRequestTable_1.sv	97ca2affc63444239f3bdde6e526351a12d4aeb61a0945c95dc6b00be7ac008d	80bd941b394f910219f07c0c3dea06d1820c35aade93db98fc3a1f1f75bf2971	trim-extra-eof-newline	./RecentRequestTable_1.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala:152:7	Mulan-PSL-2.0
+RTL/deps/OffsetScoreTable_1.sv	c5ca7e1ef371aeddbe84298ded628a09e5c68e478e815197fe679a35f164e818	4fd4badd221690928085f8393ed572f8423420a3b2c4a32c652754d762aa8ad6	trim-extra-eof-newline	./OffsetScoreTable_1.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala:226:7	Mulan-PSL-2.0
+RTL/deps/FastArbiter_4.sv	bfc22aaa80c877eb8c97b1065235ef19ef0928f1d18ac6cca4217fce6301bca1	1728bb7d009a1d79661d73be7129a784e57ed2e97e4b77dee7adb3901f9babe6	trim-extra-eof-newline	./FastArbiter_4.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_2.sv	18d0df95fc0bfc70d367682209d2acc39928d13a67c949d3a80ac24fa9772a58	98335b2f66ca6299f07fc2125b15b7583c040f97b1279a50f5d89f6b66c7125f	trim-extra-eof-newline	./TwoLevelRRArbiter_2.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/FastArbiter_6.sv	aeed517b1792c51e0161b5177f18370ce600bf9dbf5253df136ca5a6184292c9	4a8b3231c53c1d4c5d6c08b0c71ddd282649f3146b107537cbb56fac733335f0	trim-extra-eof-newline	./FastArbiter_6.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_3.sv	4a88f88b1b42cc335b65c3f6de70df9f3bbabb578f4e71fdac281c98c4a8f4f0	75de88372abffc8fc284d80660c546283241c08b84c99fb0ac438225788d00de	trim-extra-eof-newline	./TwoLevelRRArbiter_3.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/PrefetchReqBuffer.sv	b707585ba371b89b7d1dd1aeb657180b65b37db52a09087685a02a823e705209	71ff1d0f2d47e008693911acebed68188f9da14a94f035ed1b34f61dc86b7062	trim-extra-eof-newline	./PrefetchReqBuffer.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala:410:7	Mulan-PSL-2.0
+RTL/deps/VBestOffsetPrefetch.sv	f610238446e1828a4bccf54f3e1b32038e1613f237d4d493f7e6510208132c0e	03497c5868fc25960539fb89d3d3257fa858187cc32d7c79a003c5d9b8847362	trim-extra-eof-newline	./VBestOffsetPrefetch.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala:682:7	Mulan-PSL-2.0
+RTL/deps/FastArbiter_8.sv	6a21af2e53adc172ad9180e357677182723d0c78587f2a38bf6fc345eac60ca8	8190437e7818918712a747c146b05b9e0e0a9d2f60b2aae1103484adafe52905	trim-extra-eof-newline	./FastArbiter_8.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/FastArbiter_9.sv	a25a6f8568363da4c5ef91941278bc38fd012f258b33343e8c865e925a70baa2	089c715bca77c86e79bb7b6aab888914c82d90b1e28c08aea90a9a45a1d0dfd8	trim-extra-eof-newline	./FastArbiter_9.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/MbistPipeL2Prefetcher.sv	6776eaacccce4d38dbc669a4820f8e53b6916f985d0c20a47c802603bbe41155	c8c5aab68511110a573ded297d91189657de32092b720efc52ee1f25f321e389	trim-extra-eof-newline	./MbistPipeL2Prefetcher.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/mbist/MbistPipeline.scala:164:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/OverwriteQueue.sv	c630e1005ffd7f54b6efbb53bcf0f61bc7d70b73b58169a6ee3323d388689684	628bdcca6c4479d3e128c6c9e9e66b01f0b9c9c30d09bff87e6075548ab48b90	trim-extra-eof-newline	./OverwriteQueue.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/utils/OverwriteQueue.scala:34:7	Mulan-PSL-2.0
+RTL/deps/Queue1_PrefetchReq.sv	8e93aa948cf3dfde63c0a31c5c17e0729cdc9ae77784fcd5afae34566485a87f	d216ba38adfe26a4f20f89241fd4c79a5ea7ad53822ad08e86e78880dd44ded1	trim-extra-eof-newline	./Queue1_PrefetchReq.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/Pipeline_5.sv	3ee7bedc3471a14658abd7f850c2f697c9f3a20bafa2e739db7bee8212856cbb	0b7c6088b4f055b854d923f3641d171fc1c02a0a5640e31ea70533c9a0c59270	trim-extra-eof-newline	./Pipeline_5.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/Pipeline.scala:22:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Prefetcher.sv	5731035fe8d7c3a8a8264c9b10a0dcacdbc42a3a7b59fe4d6e8eb40f1fc15c43	503250e13313d2c3525ed0368abf986f5af8a089ac77f1c560fd6d50e2233c65	trim-extra-eof-newline	./Prefetcher.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/prefetch/Prefetcher.scala:197:7	Mulan-PSL-2.0
+RTL/deps/SinkA.sv	0aa3e79b1ade11d5561a1f7606c1117149c8b57a23d81cecab6f721a3294af50	7f58521ed8ff6a9971aae5304fcc04cdaf40df44873dec85069330a9f97ad35e	trim-extra-eof-newline	./SinkA.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/SinkA.scala:30:7	Mulan-PSL-2.0
+RTL/deps/FastArbiter_10.sv	59b007eb0456d46710ff8c91f9c5cb804f3514e1e4853ed402487d737b6e78ac	0d442e1322b262d72a75fd03954861889bd3e688a0ff0328d9c5d136317304a9	trim-extra-eof-newline	./FastArbiter_10.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_4.sv	c5e0a4f30c5e25d57ddd2196c819409de9e768619ddec05a3c308027d2787fdb	9cbfd8ae08f573d45ed665eebcc2a0da1b4310b5dc8d221461a3c97f2cb151a7	trim-extra-eof-newline	./TwoLevelRRArbiter_4.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SinkC.sv	c045b007eefaa4166c3a22617e88b9a2707535ba3be75ca424cdeb4605404508	cf6b2dc2265c7a215a21a0269148baab2effe58c1a5ab3ff2a9d7f36cdc625ac	trim-extra-eof-newline	./SinkC.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/SinkC.scala:36:7	Mulan-PSL-2.0
+RTL/deps/ram_16x25.sv	525d5c4c52719674534309db8447c3cf68ed1118937df992311ae6900db33f1a	1644aee47d44d5df376c890330b6609b42cd7e08c617dc88c62d120f9c534393	trim-extra-eof-newline	./ram_16x25.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue16_GrantQueueTask.sv	f28d791af7c2d23bbe7060a21a9a90127d3bc0dfead623a89ac692721c8a16db	6797f8c3449cbe39e5173fb39efb35b6f13a312abe9884d8dd17d9b937576638	trim-extra-eof-newline	./Queue16_GrantQueueTask.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/ram_data_16x256.sv	4ddd0342605892f6e24706a625a3540c07778b0a825ea941bca34304d7b2fdf8	397a763d4daa315de504987c76dbc0f04d3df588f1cd072f33d9f723f18ebaad	trim-extra-eof-newline	./ram_data_16x256.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue16_GrantQueueData.sv	88a56fcf216a4d4874d4535d092bc1fac5db6fe73543d06f5c5a1d7fb8aa6fb4	843ba5cc5c34675f3a4cd58d1048360ad4cf5c45e94dceaf361e5d954afc8e9f	trim-extra-eof-newline	./Queue16_GrantQueueData.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/Queue10_GrantBuffer_Anon.sv	4e3f2210e513b5038fdfee33b8f7e5dce3e7e8544a3e07e35dd901ecc2d7414e	664a5354852308633bad093a1fd6eb364315bfe993b7f017bb4b5b057aaaf2a1	trim-extra-eof-newline	./Queue10_GrantBuffer_Anon.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/GrantBuffer.sv	43c50f938ef21d7a9115ac17be3cc5c678bec48217b49de7fa2a9244bdcddab4	449e78b2a0a56a632b3cde7d37e9912800dd34cae287cadec814a3e80e3b2f79	trim-extra-eof-newline	./GrantBuffer.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/GrantBuffer.scala:59:7	Mulan-PSL-2.0
+RTL/deps/ram_16x148.sv	d4518c41257396d14d3386a3fb401e5449b3773bcd0a833406596de76b297cdc	fc880ec7c2ae9f6641a6b408dde3043714c2e04d5d6a254acdcaf67c5ddee2b8	trim-extra-eof-newline	./ram_16x148.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue16_CHIREQ.sv	23745eb68e9c5dccf622fa96f7d8b2d29dd35e57aedcfdc42dc60c677fd70237	a05df2b1a45be6dfbbc99f7f28bc3ee913c5a4844e0fdc9306b6488d411d999a	trim-extra-eof-newline	./Queue16_CHIREQ.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/TXREQ.sv	539451ab0e906880d1eb208d282dfd1a1de321aa11d25ff33ade1e8a82d82945	86a5512445ce769d6886cb7fac51629bf54d72776b07668a9095536e28742178	trim-extra-eof-newline	./TXREQ.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/TXREQ.scala:33:7	Mulan-PSL-2.0
+RTL/deps/ram_16x78.sv	83efab9933b900293accf74ca39d4807c43d33f058be5c21f60f7c9aaf94b9c0	d46a3c3a7dbd20fb80c1392360a45295ae36c564f2447e952e974d53a7ec999c	trim-extra-eof-newline	./ram_16x78.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue16_TaskBundle.sv	85785ab1c49cda58f06fb0f894a22e144366f02f37b9c531c4acc5d4dcc6c87e	800353244eb571233f9c9ee5f25ae8d49dea4d4347162e92f69aecb00edaa8bd	trim-extra-eof-newline	./Queue16_TaskBundle.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/Queue16_DSBeat.sv	1f74f5674e9d6173f13dec034cd93e7948a576836e108fe8714b8656706adf57	01e5c098f6778e989414f75e890187d8f180705e83edbf354f2a867f144f436d	trim-extra-eof-newline	./Queue16_DSBeat.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/TXDAT.sv	664f9f3cfb7ce149492c2989e9f2c112ecc1df62710c76e2af44036862aaaa42	3ed9034a9b03068809bc3b37824eb80c5244fe222a0c8444141ad07ceae8aa9b	trim-extra-eof-newline	./TXDAT.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/TXDAT.scala:34:7	Mulan-PSL-2.0
+RTL/deps/ram_16x73.sv	c3daf17a2f68863879f4235b2d949a14e1a658d984a6e241abe3ef79940c8408	46655030d387f888afd6dc7d205b8be2c4d401c752bc90f64c1633d609ccc60e	trim-extra-eof-newline	./ram_16x73.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue16_CHIRSP.sv	e1a8335076745771af524985075249243efb399cc0161833c5c7073d26c03cd2	fb3ac60ab739a64a87845b7dc62b3ec1118af861dd55b6e412c884436cc551bf	trim-extra-eof-newline	./Queue16_CHIRSP.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/TXRSP.sv	f225d3494d6856301538de22e51e2e3272a40cd34878c9afafd799269495c6d7	ec8ba24bd2e7ac22e4c2c598fabbad11999fc544b3fb686c781312f11f066492	trim-extra-eof-newline	./TXRSP.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/TXRSP.scala:33:7	Mulan-PSL-2.0
+RTL/deps/ram_2x98.sv	e0696c9df5991f7a1605cd79865aa9273ab8cb3adbb7d5ce50ff781fe00acb45	34dddbdca0a32aa682bd777e1a3edb7012133bc6e73553fe9957dbf2d54ec446	trim-extra-eof-newline	./ram_2x98.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue2_CHISNP.sv	a7793b85e95f7b23008bf976c8f08e4673fcaf61092f152a9519e21bf74fb370	8a0d9a831f21de53e29de8e48ad9af82165aa3a1faa2eb36de2640e09dbb7b70	trim-extra-eof-newline	./Queue2_CHISNP.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/RXSNP.sv	eb9fbaedd21a56efebf8771b22ee45cf279ec2a89ca3d6e380dec580c0b89cc9	c9eef96b33f0b37c37523428080151ae1d1a690cadbda6ced46fd9c86153ef51	trim-extra-eof-newline	./RXSNP.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/RXSNP.scala:29:7	Mulan-PSL-2.0
+RTL/deps/RXDAT.sv	c2be059ff547fd20c21ec3dbb4d540aa8a1376ba33c52ddaf6f24ff3387b44d1	1d8209b3a96949d27559c30bd923054034e89d8fa71f62d81cb12e498ccb1104	trim-extra-eof-newline	./RXDAT.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/RXDAT.scala:27:7	Mulan-PSL-2.0
+RTL/deps/RXRSP.sv	b33579be3f0c0b4f0964a9420521b0f3ccf2d8c65b7202e97e9ad600a702071c	28b4aaf90a2b4ca3ad73ea8012314a3bef8c2cd5dad007f1bd793427c56bca48	trim-extra-eof-newline	./RXRSP.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/RXRSP.scala:27:7	Mulan-PSL-2.0
+RTL/deps/sram_array_1p256x164m41s1h0l1b_l2_tag.sv	3b107e57dd31214ea4d6a8fef2aac7255f811ba83d0fb0af8261c585855cfc8c	571270ecc32ea4c8b1c79d702394fbba159490eaa153622f2e3fa3daa2962094	trim-extra-eof-newline	./sram_array_1p256x164m41s1h0l1b_l2_tag.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SramProto.scala:99:2	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SRAMTemplate_241.sv	3133b82ab38bb18096e428fda78333780f90d8782d20373c72d0a4f4d3e98e49	54dd61cc3c476c4aecca5315015377f889ed7d33680c520137e0a67a50fec683	trim-extra-eof-newline	./SRAMTemplate_241.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SRAMTemplate.scala:203:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SplittedSRAM_3.sv	a2762d96dfee93ecb09249b3b826fc07511d3b1b0d43d3a2f445ac87e6095b1a	6797cff1aac78b042e8f020b6a3df8e44ed71cc7bc27b8eaaa0046cef671650f	trim-extra-eof-newline	./SplittedSRAM_3.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/utils/SplittedSRAM.scala:13:7	Mulan-PSL-2.0
+RTL/deps/sram_array_1p256x104m13s1h0l1b_l2_meta.sv	53e4afabe638980a8cd7ab2251c58d1cd126a3c1c93cd46da75f45cc37ccda6e	eaa74cdae9d1418a04760bddd9765b54b849c889d3b99a11b7ec85ecc70302fe	trim-extra-eof-newline	./sram_array_1p256x104m13s1h0l1b_l2_meta.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SramProto.scala:99:2	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SRAMTemplate_243.sv	13528f64e705d16232bf24a0debac3f5a5a088008a65a88e9d45aa20464f0fe0	1a345cb96f808a15b8f4a0a25a5c956a8dfde4fb85bbf890f68b77b592a63f3e	trim-extra-eof-newline	./SRAMTemplate_243.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SRAMTemplate.scala:203:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/sram_array_1p256x16m16s1h0l1b_l2_repl.sv	1008454d6401d9d1872df7c460826ecb74af14897fae4b5076ac50f165650f44	3f85ae9e040d9e0ec38eee79d0dc0457b9b9e062391d0db9ab10c062bf8c7c95	trim-extra-eof-newline	./sram_array_1p256x16m16s1h0l1b_l2_repl.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SramProto.scala:99:2	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SRAMTemplate_244.sv	1bffb34062ae9a019a2416b31e9ac2d2350fd16beb4d667b798013bd06f3931a	ba5ca2d57930d01e813ad9d7a0978b821482beef33e3417fad3fb82e0d985062	trim-extra-eof-newline	./SRAMTemplate_244.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SRAMTemplate.scala:203:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/sram_array_1p256x8m1s1h0l1b_l2_orgb.sv	587a031d9919c98c67188c477a75a964ab3f797eccaeb78e67e14138a174c574	3c35ecfcc0d2bc25080c1f939c124a2c617e6d57f80161f96dd3e823d8e4a4ba	trim-extra-eof-newline	./sram_array_1p256x8m1s1h0l1b_l2_orgb.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SramProto.scala:99:2	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SRAMTemplate_245.sv	21008888220180d94293df55e70013f4d6a0a85965a443785c0f90deac122063	e589b63111ead96159aaa65d197e73d3285b220826b2af1fe798a6d245917cf1	trim-extra-eof-newline	./SRAMTemplate_245.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SRAMTemplate.scala:203:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/L2Directory.sv	db2a31e66f14d7b711f8c1847bb8c9684d2c58fa4c57375152efcfe161fed7ff	a681d7deb599369a5988f39ddd93fa5ea45213b618be9f6509a96c4ef4058a8b	trim-extra-eof-newline	./L2Directory.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/mbist/MbistPipeline.scala:164:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Directory.sv	b8c7611fe602a9100998934ae251313560b4da97d65a88a4a5ddb9a9eb15d3ef	083ecb7f1be18aa07ca538c90668239b89befea5e8c317cf57c02dd764d7cc7a	trim-extra-eof-newline	./Directory.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/Directory.scala:129:7	Mulan-PSL-2.0
+RTL/deps/sram_array_1p2048x137m137s1h1l2b_l2_dat.sv	6f9536100ced28ecb4c6d060a38a3ee91324c2743e9a36c6cf5d5f0dfdfea7f7	73afa64ff86147d0664373b894864683a42e0572d38f835b22bca93c7d41c4a9	trim-extra-eof-newline	./sram_array_1p2048x137m137s1h1l2b_l2_dat.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SramProto.scala:99:2	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SRAMTemplate_246.sv	7e2efdc3f5a396403e3846982d884c740b89bd291144558addd7f5d6cddf1f2d	d65a60be64ef062500de90c61584a77da576af175dfe8dea019b385557a44515	trim-extra-eof-newline	./SRAMTemplate_246.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SRAMTemplate.scala:203:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SRAMTemplate_247.sv	3c29c58011ad8a322596bc378982e8cf0efd55e2e8ed19f3e7d5112124b5c433	52defe0636d81885a2f2aa854bd658ff9871742649b2910454e37dc5062b70e5	trim-extra-eof-newline	./SRAMTemplate_247.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/sram/SRAMTemplate.scala:203:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/ClockGate.sv	aa011546df177ee70291f8bad61dfdf6325bb73a283fd25825f524f9d01cfe5d	aa011546df177ee70291f8bad61dfdf6325bb73a283fd25825f524f9d01cfe5d	identity	./ClockGate.sv	yes	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/ClockGate.scala:24:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/ClockMux.sv	4060c41171d075acfc94f1150b36a683501dc60650465fb29870e3eed8d5272e	88fab7217c0c97d2d45f1b8d95fabae267fdc1f19150c7297618883fe2ba6056	trim-extra-eof-newline	./ClockMux.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/ClockMux.scala:21:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/MbistClockGateCell_186.sv	f19ab95e6acdfecf671a0744881d0422cb13e1845e479d72356a1598fe70ab8e	bb1c49a329b2b6b9eff42abfa865e0247d686d0e4176500fe578477a14925e79	trim-extra-eof-newline	./MbistClockGateCell_186.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/mbist/MbistClockGateCell.scala:35:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/GatedSplittedSRAM.sv	e4f7fe176d4741d5e3fb6aada677bfc717ab5e45a2e42118f1e0189725b53d5b	1ac41fe21bb66cbd0bcfd10baabd305e962436272f37bbedd6beceb2d7a5a2e5	trim-extra-eof-newline	./GatedSplittedSRAM.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/utils/GatedSplittedSRAM.scala:14:7	Mulan-PSL-2.0
+RTL/deps/L2DataStorage.sv	3f84f9c98e98cc4dcb7c1c4f02b1efc3f2c77e9b02ddd5d13280e3c092486c41	27f2327e1ee625da3a409189c77d63c4b1c2c79e2a86892da4c55e756a670de8	trim-extra-eof-newline	./L2DataStorage.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/mbist/MbistPipeline.scala:164:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/DataStorage.sv	a1592701cb53687202df0a9d4a403a6392be98eea190b0a5d8549ad95f58fcbb	b7f70254ebd9a935bf070f7e0c33de3eb26a476f6e57f69de9a58eb9948ddd7d	trim-extra-eof-newline	./DataStorage.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/DataStorage.scala:50:7	Mulan-PSL-2.0
+RTL/deps/MSHRBuffer.sv	9872f3d34cfa7a3cd200c367f4e7a2b22ba11c06ac1cd64a52eef079296badf7	aaec2be28910c0e2817ebb973c328e074f799d4839afcff9025a11f72e2cca12	trim-extra-eof-newline	./MSHRBuffer.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MSHRBuffer.scala:40:7	Mulan-PSL-2.0
+RTL/deps/MSHRBuffer_1.sv	7ff57655074451cce7ad0dac0bb6554ed5eac16d107ba8ba7253c5a3f9406777	d0d885836cdd3652cfc617c48b62b73d7260c12827b8380371addefb91c1ee8f	trim-extra-eof-newline	./MSHRBuffer_1.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MSHRBuffer.scala:40:7	Mulan-PSL-2.0
+RTL/deps/RequestArb.sv	99a1baf39db8cf5b1fc17a7927bd7036d7879419e3db76ab735693d2875d6a36	01d3cc5ea258d0ea9c2be49dc86a6d9f5c2a8804ab1e46039879e84bbf4519c0	trim-extra-eof-newline	./RequestArb.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/RequestArb.scala:29:7	Mulan-PSL-2.0
+RTL/deps/ram_16x9.sv	3e37d29c71cb7f06b85907f5d37691647df85ca1e5908060849d7c64fe1596bc	a9d8362556ed7d4de0c41e69d4296c259e0a6da1e1416b5ab8498e4de896a58b	trim-extra-eof-newline	./ram_16x9.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue16_HintQueueEntry.sv	3c9a79be88de076c5a451154d26a4286d71ebc04b812d12f3b29585776e44b04	43bb24c8782253f6b50fc6259556d13d8a0bb516fbe80dbfd0fcf3ba53a890aa	trim-extra-eof-newline	./Queue16_HintQueueEntry.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/Queue1_HintQueueEntry.sv	d884527f7f11c485118a9acfec0d40e2b59c1a0472a5143130c708e0fcfadbb7	3781aa65668dbb1d4b5b700604bc7315d37deddde02f84d3a557b8f4d2a0d4a6	trim-extra-eof-newline	./Queue1_HintQueueEntry.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/Pipeline_6.sv	0513dc97e5ca82380a5cc5cd8dffd9d3a3cec9e292d8cddff1974bd90fe1ef60	722a07affde70d48fed18c55f0391898882a0153749ea8a940c2bcf79c290694	trim-extra-eof-newline	./Pipeline_6.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/Pipeline.scala:22:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Arbiter3_HintQueueEntry.sv	32112abd1d47ea63536f896004b582979b2042fe773180d9f7fd2c0165a1f63c	99d7639d63945a9757662d7c0f40982d1d5c4199d5005edd498134dde6a8eb96	trim-extra-eof-newline	./Arbiter3_HintQueueEntry.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Arbiter.scala:149:7	Apache-2.0
+RTL/deps/CustomL1Hint.sv	0a93f8f2ee2810f5b81336d9f079f395726ce7983fd1325b6c82e4ea6defdeef	b7424dd6009e0ebb938962b396d4a2a797d4ca80cac6a1d31211db897bb67f3c	trim-extra-eof-newline	./CustomL1Hint.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/CustomL1Hint.scala:51:7	Mulan-PSL-2.0
+RTL/deps/Arbiter3_TaskWithData.sv	57aad82fa83397778f3d2b981df6fab6fdba5acf0b13d61ca9689639d791d575	f99debb949ba68dc4d7fab430f81c94f87a9c1c79650e573cb5ce8cf3279864f	trim-extra-eof-newline	./Arbiter3_TaskWithData.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Arbiter.scala:149:7	Apache-2.0
+RTL/deps/Arbiter3_CHIREQ.sv	4569e095eb4ab94cb1d8f607213c2c3e284b3eaed57ff646fce6b5d476c16088	6ea29b5f012faaa48cde17e0a7ef370e581baa868e0fe939b6278aab390e4253	trim-extra-eof-newline	./Arbiter3_CHIREQ.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Arbiter.scala:149:7	Apache-2.0
+RTL/deps/Arbiter3_TaskBundle.sv	07cf4dbd2812ccce9fc9e75439d1256978e6c1409cfb0d47f840179897add385	6e4fdd16538028d0851a3034f8500290cf56deef8baf43f5e09aa05274a50265	trim-extra-eof-newline	./Arbiter3_TaskBundle.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Arbiter.scala:149:7	Apache-2.0
+RTL/deps/MainPipe_1.sv	ed95ab8ef4972c9aa581ca41b707b5b80640d75874e5a9ead749086bf3f16ab6	351fe1478de686aa4fecadbf02ecd704e4644093998380ec47334ff132e03557	trim-extra-eof-newline	./MainPipe_1.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MainPipe.scala:33:7	Mulan-PSL-2.0
+RTL/deps/FastArbiter_12.sv	2c804dfa041845e6fca169f223e67f09b3529b673b0ac56bc5a88fa45cc420bf	ad607c0897cb3c78b741203e4cd65f74e9f18bd53edc3fc1f9e0fa16543c2c48	trim-extra-eof-newline	./FastArbiter_12.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_5.sv	0f717db453519fed949d08149ca7424e7df4822c6e7a7aabe6071ad4553d4600	56433e5842fccdb11cdd8fb83a5977bcb0418abaec9e40a40029b9d76024cc77	trim-extra-eof-newline	./TwoLevelRRArbiter_5.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Queue1_ChosenQBundle.sv	b8502a1e9e07bd8662fd8edbda630f78a9a4eeaf6e345f7b9deeada2e3effa6b	9385019fd96985034d826ebbd78d0ee143eabdf38df3c6412120f2577ecb5c42	trim-extra-eof-newline	./Queue1_ChosenQBundle.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/RequestBuffer.sv	5323cfa8c91185c6bcb19998be49cf2a6cda777cc0cb1aae2bf5b1fe1e48cee4	c44c229fe148303221fcb4f73110015aaa51ad0d4c26bc2c2045cf8e27b299b3	trim-extra-eof-newline	./RequestBuffer.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/RequestBuffer.scala:71:7	Mulan-PSL-2.0
+RTL/deps/MSHR.sv	0b2feca3c50543c4603a18ce696475ef6441dc41babc6ba3b78db48a1be0fa2d	ffc6c9884b0d40f63217a487ef85df67a23a1e04221bd8a6664c6af53c6e22a6	trim-extra-eof-newline	./MSHR.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MSHR.scala:51:7	Mulan-PSL-2.0
+RTL/deps/MSHRSelector.sv	edf41bfad9a1dd4785c5933e3ae7ac1bc0cd3cab147b40674d3505e9ff001ce9	b110ba4a787f039e1c45d17e5001abbb9a517e570f559ee8b7ef785d9c63fa6a	trim-extra-eof-newline	./MSHRSelector.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MSHRCtl.scala:95:9	Mulan-PSL-2.0
+RTL/deps/FastArbiter_16.sv	b60b9714a29aa6c64c704b3054da953c8c331d0b6f82892c00b83f2733785356	e72c12d35d3d7b23c85e8669e3a736ea03ee16570e20fa73c0f1cb531226ef8a	trim-extra-eof-newline	./FastArbiter_16.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_7.sv	dbf5b8cb2cd54a9b15d7ee1ea11f918026ca6f9a4de6bcd527daa5d9f9066250	a2143f294de5f9532f4409fad27fff08ee958df4572bf79d0e00bb966bf0aec8	trim-extra-eof-newline	./TwoLevelRRArbiter_7.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/FastArbiter_18.sv	770b581549a3931245966f1e949a06040d168c7740476d5631cb455232cca393	5e7a49d11db8b217bd14dd34d72a8e3cb6def58f38ba9ced54b1d180b01c8061	trim-extra-eof-newline	./FastArbiter_18.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_8.sv	a64186f540af5339151b6dfedac98e7d692df574683a098f09dfcb50e284c709	e0eb0555929398030ab4b9b090b81678d2cf78b614f50cdd9469c9a406a24d13	trim-extra-eof-newline	./TwoLevelRRArbiter_8.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/SourceB.sv	748fd61ce8dc52662acd7b09f0174fcb61248ce5b88bd9e059bc969c9f4f0d2e	43481234736a26bfe63cdab567dfd4ec365185d1c7f29f2a89e477dc6bc17537	trim-extra-eof-newline	./SourceB.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/SourceB.scala:43:7	Mulan-PSL-2.0
+RTL/deps/FastArbiter_20.sv	ea6f82f823e4b48bab4a23f1b6f5b017b7bf3af182835f41a2347ec2668caff4	4aa176c4ca8dbc5752714d97762a7eb63ad75491b759ef77f3c136896aed6359	trim-extra-eof-newline	./FastArbiter_20.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_9.sv	9f40dd0820dec762fd4e95364444e3055b5a9dfa2c75e250dde32ee6c9bcb69a	c887500fd5eec4e7115215049d862f2f06853ed29b20dd384a695103c74ade04	trim-extra-eof-newline	./TwoLevelRRArbiter_9.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/FastArbiter_22.sv	e2ea8113c6869edf8e1a4f73a459f5aa98e812205059f625ad002506db1f09f4	eab91a93803d1250585f4091cc13effa62ee806e2b479d96ea3f235fc3cda939	trim-extra-eof-newline	./FastArbiter_22.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_10.sv	bb9b7aad0a2ca3b25cf5c24f890bd51794f5d41ffe1396b58237110d2e9f69cb	123f44ec3305a423e38e20698d229da2334fe3c75faf194d1b95df3b1b53ef5e	trim-extra-eof-newline	./TwoLevelRRArbiter_10.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/MSHRCtl.sv	dde6e0c5d9ada6f4e6ae81a20388ecbdd957e18cc39692fe24c16a9df95502d9	2aa0ca731c23e6dc2bfed5f288680eb538ea71d3499fc649bfa5309f5f06224e	trim-extra-eof-newline	./MSHRCtl.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/MSHRCtl.scala:32:7	Mulan-PSL-2.0
+RTL/deps/L2Slice.sv	c9cd234040cb03dd4c5d60356e902fec3094f09c2033116b28134d712f514d45	cf0515bf88c04c2c7f17b75a902ecb071d9aee10042e147df1e31b329204effb	trim-extra-eof-newline	./L2Slice.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/mbist/MbistPipeline.scala:164:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Slice.sv	a37b3819a9ee61646569d5f22cd6ace20fbf2fc9e5bed3aeb8e1657b2bda4e02	99f7218fd3a61ee5db9b26e49a6119199e7772d8377ad1c0933c1128f07910bd	trim-extra-eof-newline	./Slice.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/Slice.scala:31:7	Mulan-PSL-2.0
+RTL/deps/Queue1_PrefetchTrain.sv	470b764e0a46e9164f357cf06310c960e2c7e37fe7c1fb07ea4d9aa1707a218b	1b00f549f07a2774548d520ccca9257fa39480b6f7cf44879562287d79cb6a87	trim-extra-eof-newline	./Queue1_PrefetchTrain.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/Pipeline_7.sv	304e258377879f325353a1cf2bfab777f8135188be9b3427e51df1129695c922	75a429684fa2ece17a89dacc505a508ad2c11eb773c04cae478ae8ce0a4d4eee	trim-extra-eof-newline	./Pipeline_7.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/Pipeline.scala:22:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Queue1_PrefetchResp.sv	15a363b4c08d1c538262d101163721479f8fccd2d4d469cbffcea67b874e3e18	e857e5ab4d9ee694afe1916dfac2e2e0dbb7078512f1751666560380bb6f32d9	trim-extra-eof-newline	./Queue1_PrefetchResp.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/Pipeline_8.sv	18f33bed9d428b7fdc24745c4ab8cd8ca35f71311ac9e35783c8300b7803c1fb	4d4eb495da675e6054d629be15a025eeb74a0a00fe40808f5a0568f1f2e7955e	trim-extra-eof-newline	./Pipeline_8.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/Pipeline.scala:22:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/FastArbiter_24.sv	0a99625ea4cae0ecdad35929dd6345fb5a8ec44d23a5eefe9b2aaff238cb3144	88d8908a92739b565c03a5e25a5442abf9b624d3918f40bec4618627a402724e	trim-extra-eof-newline	./FastArbiter_24.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_11.sv	bb2d66a88a268a73b535c9cf20dada7f35731a5da28bbe746ecb0dafd6d39259	9c84e4a12b54ce2096a71f26efdf1e7ab96fd2638973414b817350217eaea024	trim-extra-eof-newline	./TwoLevelRRArbiter_11.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/FastArbiter_26.sv	442e35c194173c8d35851081d468c009d205bb63f570e3052076020e37f68178	72ff5b0ca61a6a47ab611b9f0a869fed8de9d18afbb39e0acba389a8763cdcde	trim-extra-eof-newline	./FastArbiter_26.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/FastArbiter_27.sv	7bb764e255598bfc1b18340841e78bad32551a490deb92fb1d49c4631728bfe2	1563ce2879d7bbe19d6c90b96c91c0cf221d05da784ac457f5cc4095b2014d6a	trim-extra-eof-newline	./FastArbiter_27.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/ram_30x15.sv	e62008d1f84ea8a20f2dd33f5dcae3a11a044648bace96ccd8c9289a87b3e19d	82c0eb6eebdb56b4594d0deb3347234bc8eed4fd68b481ffca0269069c9603ef	trim-extra-eof-newline	./ram_30x15.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue30_PCrdGranted.sv	95a0fadc9ce8ada54880a3940b919b896da8a29675fbee0bf02c9662c72b167a	9596bebd46a1b7a98e7fb725c7d91aa3aec52eb4e2a1ca6eda98d41b9ec9381c	trim-extra-eof-newline	./Queue30_PCrdGranted.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/ram_2x15.sv	b7856bef427f6b27b7f8e1cc20c7e475e7db9b97ac918c729f4452162a77b85d	c613f002fa06e716580bf74a9860d8881c5efe4de2e9228bf5c90aea1815375d	trim-extra-eof-newline	./ram_2x15.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue2_PCrdGranted.sv	e9c075b995b7f3d4e7ec5d41f87813fd63cdd565ee4aee9d8f4f77f3edce3fc9	639cf47432d0a9f770b10caeb89e0ef6ad955355129983650ca5f78871e517dc	trim-extra-eof-newline	./Queue2_PCrdGranted.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/FastArbiter_28.sv	7296694fba7078da39a930255140dfb9cea5c4e40bb10ce7b0f852191de4371b	80d9365848ebbfe6f5334607489aa0f012beec755d14b9231ebdec24b2488021	trim-extra-eof-newline	./FastArbiter_28.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:30:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/TwoLevelRRArbiter_12.sv	46efc98f42b14cd51787af19464dd13cf0325cf86306d8d090a75918d68c7d99	ad283ae13ae798fde2ce8ae9cd0884dd694b0a1d07ce3ec783df03332d655990	trim-extra-eof-newline	./TwoLevelRRArbiter_12.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/FastArbiter.scala:108:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Decoupled2LCredit.sv	56932136772881147f31c3e5d6f9ed0b62ca0242289a89d194ef53a1dc3c076f	bf06dd821f9dd8af1cdb17b836d3f32a3d2bff7d7dd3ba9db354eea9d249cb20	trim-extra-eof-newline	./Decoupled2LCredit.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/xscache/chi/LinkLayer.scala:256:7	Mulan-PSL-2.0
+RTL/deps/Decoupled2LCredit_1.sv	215c47193c2d231f08513dc66b14b054d708ba59b4d2c1b217b9cdfcd4083bcf	355d9c55d84ee68aadd947997cf19ced1559fbed6a6d6dd02db5cff788881ba6	trim-extra-eof-newline	./Decoupled2LCredit_1.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/xscache/chi/LinkLayer.scala:256:7	Mulan-PSL-2.0
+RTL/deps/Decoupled2LCredit_2.sv	3c79009e8f0e7b7eabde23a91f8fe83ef5c249919b2272cc1ac54e38c4e41dba	cc8ee867d71719a29736fda61940ec5806e800bbdabd2007714215f41328f805	trim-extra-eof-newline	./Decoupled2LCredit_2.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/xscache/chi/LinkLayer.scala:256:7	Mulan-PSL-2.0
+RTL/deps/ram_4x115.sv	fe846e93950282cb3125a672bfa80616ea47f03c3d61f516471078b94a27d15e	07dc2a1458b6c2b233d85c8d1f8aa2477c81acdd01937844cf70c9b0fbe5e1a6	trim-extra-eof-newline	./ram_4x115.sv	no	yes	CIRCT memory lowering from Chisel Queue	chipsalliance/chisel@42f1a1e1a9f6bbf940344113da155d77499dcaa7; llvm/circt@4d750dbb2971d5f97e2fc48c700e01e460a5bdc8	src/main/scala/chisel3/util/Queue.scala (parent Queue module; generated memory has no direct FIR locator)	Apache-2.0 (Queue.scala source)
+RTL/deps/Queue4_CHISNP.sv	d4ccea7eb74dd3a2c96fd8e8fe60033e7cc09e6226e96be2700c406f167d280d	fea27ed7d1608c3f85a64a2104a4fe6d988b6307f25c44a19cb2171127b2e2cf	trim-extra-eof-newline	./Queue4_CHISNP.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/LCredit2Decoupled.sv	c394bb1823ad281c840f750c9e43d44f9c3091dfc43d24af0ecdc5b367df7d89	495ee3b7fce58417deddc73da478841a988a4cfdfbc9d755c7a26083af6424a2	trim-extra-eof-newline	./LCredit2Decoupled.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/xscache/chi/LinkLayer.scala:131:7	Mulan-PSL-2.0
+RTL/deps/LCredit2Decoupled_1.sv	58f60df899042881dd62535af6aff55193fb9ef09157456ef5c36578f4ec44e2	32d2085b8707e15a8e3d1e78139250d612c7a82ccb29c57b582b98ba83a075ae	trim-extra-eof-newline	./LCredit2Decoupled_1.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/xscache/chi/LinkLayer.scala:131:7	Mulan-PSL-2.0
+RTL/deps/LCredit2Decoupled_2.sv	ab109ee7da825c0b96978c809df001cff4f714b7447bd8b2919b780d9a4a43c2	e188504ac7c062375401c2415c5290ab3ec78357a656e25863e6074d4b659a5e	trim-extra-eof-newline	./LCredit2Decoupled_2.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/xscache/chi/LinkLayer.scala:131:7	Mulan-PSL-2.0
+RTL/deps/LinkMonitor.sv	10a6582500229446f3c4be5fd53d65e123c6e7ac0c5ccbe8902d8a7a10ae9d3f	acc88a735d2bc2b74f323d25fe88bd40ad6ffe6862c1e445483499cdb4ce9ae4	trim-extra-eof-newline	./LinkMonitor.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/LinkMonitor.scala:25:7	Mulan-PSL-2.0
+RTL/deps/Queue1_CHIDAT.sv	4ab6e36456ce376fbfb4686210811cb1413e46279afdccf15408f1802cff7683	77518262103943a5c434e9af52c76a0d390e09666928ae641dfd29804ffe75e0	trim-extra-eof-newline	./Queue1_CHIDAT.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/Pipeline_9.sv	64f9dc0a29a3ec0c72d798ecd85cad7ef177fc8f504910cb63b92e5ed23168af	7f4966bc525a8850395f60d94bcb5a04adc0519173dc63d37e3ec407c1eb9dbd	trim-extra-eof-newline	./Pipeline_9.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/Pipeline.scala:22:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Queue1_CHIRSP.sv	feefcdfcc0b487dba213c5ee56704595f08cbe0dd9c88b8388cadd06b408e9aa	bc243adae5ea2071c9831152eab2b84f12b80e851be07780cb856f42851add57	trim-extra-eof-newline	./Queue1_CHIRSP.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Queue.scala:60:7	Apache-2.0
+RTL/deps/Pipeline_10.sv	55778fc33b90cd8e24d0b41052aa079d556a08a01ba071e137b10f5d1a64d082	119eb1c37f3e082ff28888a8a8b19643007a3e7dabdf980f5644cc2a519943d9	trim-extra-eof-newline	./Pipeline_10.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/Pipeline.scala:22:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/Arbiter1_L2CacheErrorInfo.sv	fa6658193ffa57e5f68a277584102621650bdd1db274f642df2768db6a1ac425	7988282438b1c8e1031a0b3d93e5c363c497e3a84db5f9de403d94e5de4e8365	trim-extra-eof-newline	./Arbiter1_L2CacheErrorInfo.sv	no	yes	chipsalliance/chisel	v7.3.0@42f1a1e1a9f6bbf940344113da155d77499dcaa7	src/main/scala/chisel3/util/Arbiter.scala:149:7	Apache-2.0
+RTL/deps/L2Cache.sv	4260141f104ad9b5171b0b0909a18b56a6d0b02b11ff3bff43da295d080ec572	098ace6482dc50922465dc76aface116f4915971a42057cdacedc666fbb874a7	trim-extra-eof-newline	./L2Cache.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/mbist/MbistPipeline.scala:164:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/deps/MbistIntfL2.sv	e55349aa83d9779f7bbb90540c651b71ca5e2a52ef98009e1f3f284ebd5c4147	40df96ad5d02611ab8c3a436a8be3fe24c56c58067bd1a6e52e419ff59da718e	trim-extra-eof-newline	./MbistIntfL2.sv	no	yes	OpenXiangShan/Utility	bab34605babce74732f7f441c5d126a0869285bd	src/main/scala/utility/mbist/MbistPipeline.scala:52:7	Mulan-PSL-2.0 (per-file notice; repository has no root LICENSE at pin)
+RTL/CoupledL2.sv	fcb751d162cc928495351e1a39e47db06b4bf47733b61154cf62e5b5e3d3fdf1	a1862a6e175741625b4365e0e891e7d98e102b370250dd4e903369b77e03c1b1	trim-extra-eof-newline	./CoupledL2.sv	no	yes	OpenXiangShan/XSCache	54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f	src/main/scala/coupledL2/CoupledL2.scala:356:9	Mulan-PSL-2.0 + Apache-2.0 (file also references LICENSE.SiFive)
diff --git a/flow/designs/src/xiangshan_coupledl2/SOURCE.md b/flow/designs/src/xiangshan_coupledl2/SOURCE.md
new file mode 100644
index 0000000000..c831b24cff
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/SOURCE.md
@@ -0,0 +1,51 @@
+# XiangShan CoupledL2
+
+- Benchmark id: `xiangshan_coupledl2`
+- RTL top: `CoupledL2`
+- XiangShan source root: [OpenXiangShan/XiangShan](https://github.com/OpenXiangShan/XiangShan)
+  `96c3f568f943a096ffd3d712dc6f462ac4b1ba33`
+- CoupledL2 source: [OpenXiangShan/XSCache](https://github.com/OpenXiangShan/XSCache)
+  `54a2a7527f7366e3cb3fe378b1f1e92f18cbf33f`
+- Utility source: [OpenXiangShan/Utility](https://github.com/OpenXiangShan/Utility)
+  `bab34605babce74732f7f441c5d126a0869285bd`
+- Generator selection: `top.TopMain --config MinimalConfig --issue E.b
+  --num-cores 1 --target systemverilog --split-verilog --fpga-platform`
+- Generator: Chisel `7.3.0`, CIRCT firtool `1.135.0`
+- RTL closure: 145 SystemVerilog files; top file `CoupledL2.sv`
+
+Generator dependency pins at the XiangShan source root:
+
+| Component | Repository | Commit or version |
+|---|---|---|
+| rocket-chip | `OpenXiangShan/rocket-chip` | `c4ba35a80758881da59399b693a6b51448eea1e4` |
+| cde | `chipsalliance/cde` | `52768c97a27b254c0cc0ac9401feb55b29e18c28` |
+| hardfloat | `ucb-bar/berkeley-hardfloat` | `d93aa570806013dea479a92ba9bb33d1f2d4f69f` |
+| OpenNCB | `OpenXiangShan/OpenNCB` | `9a83eb7e6c0e36e0d6b72642ff93641ec65819cf` |
+| ChiselAIA | `OpenXiangShan/ChiselAIA` | `53edde5226123e0ce9daa016b9f9b049866d3980` |
+| ChiselIOPMP | `OpenXiangShan/ChiselIOPMP` | `435815008053614c2e338439a16b2a1359931c9e` |
+| difftest | `OpenXiangShan/difftest` | `36062fbd54579220e8aff92bc820e2fd3e749539` |
+| ready-to-run | `OpenXiangShan/ready-to-run` | `955e6e2a5b5a51426d000597710cd632aeba2f52` |
+| YunSuan | `OpenXiangShan/YunSuan` | `447cd17b1637f998daeb6be3efcd4890f48cb2b9` |
+| Chisel | `chipsalliance/chisel` | `v7.3.0` (`42f1a1e1a9f6bbf940344113da155d77499dcaa7`) |
+| firtool | `llvm/circt` | `firtool-1.135.0` (`4d750dbb2971d5f97e2fc48c700e01e460a5bdc8`) |
+| mill / scala | `com-lihaoyi/mill`, `org.scala-lang/scala` | `0.12.15` / `2.13.17` |
+
+Two offline generator replays emit 138 selected SystemVerilog files byte for
+byte from the pinned source graph. The only replay difference is disclosed
+enum ordering in an unshipped full-chip FIR file. Of the 138 generated files,
+48 come from XSCache sources, 54 from Utility sources, 26 are Chisel standard
+library modules (`Arbiter*`, `Queue*`), and 10 are CIRCT memory lowerings of
+Chisel queues (`ram_*`). The other seven files in the 145-file closure are
+local physical-memory boundary files: six `array_*_bb` blackbox declarations
+and the banking wrapper `deps/array_2048x137_wrap.sv`. They are not attributed
+to the OpenXiangShan generator. Their legacy `.v` suffixes were migrated to
+`.sv` without behavioral changes. The license basis of each group is described
+in `LICENSES/README.md`.
+
+The SRAM macro views are shared platform collateral: the LEF, Liberty, and
+`array_*_bb` blackbox declarations live under
+`platforms/<pdk>/{lef,lib,verilog}/`, and `fakeram.cfg` in each design
+directory records the generator parameters they were built with.
+
+The functional L2 shares the `XSTileWrap` core clock; the pinned source does
+not divide it into a separate 500 MHz domain.
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Arbiter16_CHIDAT.sv b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter16_CHIDAT.sv
new file mode 100644
index 0000000000..766e1f0168
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter16_CHIDAT.sv
@@ -0,0 +1,560 @@
+// Generated by CIRCT firtool-1.135.0
+module Arbiter16_CHIDAT(
+  output         io_in_0_ready,
+  input          io_in_0_valid,
+  input  [10:0]  io_in_0_bits_tgtID,
+  input  [11:0]  io_in_0_bits_txnID,
+  input  [1:0]   io_in_0_bits_respErr,
+  input  [1:0]   io_in_0_bits_ccID,
+  input  [1:0]   io_in_0_bits_dataID,
+  input          io_in_0_bits_traceTag,
+  input  [31:0]  io_in_0_bits_be,
+  input  [255:0] io_in_0_bits_data,
+  input  [31:0]  io_in_0_bits_dataCheck,
+  input  [3:0]   io_in_0_bits_poison,
+  output         io_in_1_ready,
+  input          io_in_1_valid,
+  input  [10:0]  io_in_1_bits_tgtID,
+  input  [11:0]  io_in_1_bits_txnID,
+  input  [1:0]   io_in_1_bits_respErr,
+  input  [1:0]   io_in_1_bits_ccID,
+  input  [1:0]   io_in_1_bits_dataID,
+  input          io_in_1_bits_traceTag,
+  input  [31:0]  io_in_1_bits_be,
+  input  [255:0] io_in_1_bits_data,
+  input  [31:0]  io_in_1_bits_dataCheck,
+  input  [3:0]   io_in_1_bits_poison,
+  output         io_in_2_ready,
+  input          io_in_2_valid,
+  input  [10:0]  io_in_2_bits_tgtID,
+  input  [11:0]  io_in_2_bits_txnID,
+  input  [1:0]   io_in_2_bits_respErr,
+  input  [1:0]   io_in_2_bits_ccID,
+  input  [1:0]   io_in_2_bits_dataID,
+  input          io_in_2_bits_traceTag,
+  input  [31:0]  io_in_2_bits_be,
+  input  [255:0] io_in_2_bits_data,
+  input  [31:0]  io_in_2_bits_dataCheck,
+  input  [3:0]   io_in_2_bits_poison,
+  output         io_in_3_ready,
+  input          io_in_3_valid,
+  input  [10:0]  io_in_3_bits_tgtID,
+  input  [11:0]  io_in_3_bits_txnID,
+  input  [1:0]   io_in_3_bits_respErr,
+  input  [1:0]   io_in_3_bits_ccID,
+  input  [1:0]   io_in_3_bits_dataID,
+  input          io_in_3_bits_traceTag,
+  input  [31:0]  io_in_3_bits_be,
+  input  [255:0] io_in_3_bits_data,
+  input  [31:0]  io_in_3_bits_dataCheck,
+  input  [3:0]   io_in_3_bits_poison,
+  output         io_in_4_ready,
+  input          io_in_4_valid,
+  input  [10:0]  io_in_4_bits_tgtID,
+  input  [11:0]  io_in_4_bits_txnID,
+  input  [1:0]   io_in_4_bits_respErr,
+  input  [1:0]   io_in_4_bits_ccID,
+  input  [1:0]   io_in_4_bits_dataID,
+  input          io_in_4_bits_traceTag,
+  input  [31:0]  io_in_4_bits_be,
+  input  [255:0] io_in_4_bits_data,
+  input  [31:0]  io_in_4_bits_dataCheck,
+  input  [3:0]   io_in_4_bits_poison,
+  output         io_in_5_ready,
+  input          io_in_5_valid,
+  input  [10:0]  io_in_5_bits_tgtID,
+  input  [11:0]  io_in_5_bits_txnID,
+  input  [1:0]   io_in_5_bits_respErr,
+  input  [1:0]   io_in_5_bits_ccID,
+  input  [1:0]   io_in_5_bits_dataID,
+  input          io_in_5_bits_traceTag,
+  input  [31:0]  io_in_5_bits_be,
+  input  [255:0] io_in_5_bits_data,
+  input  [31:0]  io_in_5_bits_dataCheck,
+  input  [3:0]   io_in_5_bits_poison,
+  output         io_in_6_ready,
+  input          io_in_6_valid,
+  input  [10:0]  io_in_6_bits_tgtID,
+  input  [11:0]  io_in_6_bits_txnID,
+  input  [1:0]   io_in_6_bits_respErr,
+  input  [1:0]   io_in_6_bits_ccID,
+  input  [1:0]   io_in_6_bits_dataID,
+  input          io_in_6_bits_traceTag,
+  input  [31:0]  io_in_6_bits_be,
+  input  [255:0] io_in_6_bits_data,
+  input  [31:0]  io_in_6_bits_dataCheck,
+  input  [3:0]   io_in_6_bits_poison,
+  output         io_in_7_ready,
+  input          io_in_7_valid,
+  input  [10:0]  io_in_7_bits_tgtID,
+  input  [11:0]  io_in_7_bits_txnID,
+  input  [1:0]   io_in_7_bits_respErr,
+  input  [1:0]   io_in_7_bits_ccID,
+  input  [1:0]   io_in_7_bits_dataID,
+  input          io_in_7_bits_traceTag,
+  input  [31:0]  io_in_7_bits_be,
+  input  [255:0] io_in_7_bits_data,
+  input  [31:0]  io_in_7_bits_dataCheck,
+  input  [3:0]   io_in_7_bits_poison,
+  output         io_in_8_ready,
+  input          io_in_8_valid,
+  input  [10:0]  io_in_8_bits_tgtID,
+  input  [11:0]  io_in_8_bits_txnID,
+  input  [1:0]   io_in_8_bits_respErr,
+  input  [1:0]   io_in_8_bits_ccID,
+  input  [1:0]   io_in_8_bits_dataID,
+  input          io_in_8_bits_traceTag,
+  input  [31:0]  io_in_8_bits_be,
+  input  [255:0] io_in_8_bits_data,
+  input  [31:0]  io_in_8_bits_dataCheck,
+  input  [3:0]   io_in_8_bits_poison,
+  output         io_in_9_ready,
+  input          io_in_9_valid,
+  input  [10:0]  io_in_9_bits_tgtID,
+  input  [11:0]  io_in_9_bits_txnID,
+  input  [1:0]   io_in_9_bits_respErr,
+  input  [1:0]   io_in_9_bits_ccID,
+  input  [1:0]   io_in_9_bits_dataID,
+  input          io_in_9_bits_traceTag,
+  input  [31:0]  io_in_9_bits_be,
+  input  [255:0] io_in_9_bits_data,
+  input  [31:0]  io_in_9_bits_dataCheck,
+  input  [3:0]   io_in_9_bits_poison,
+  output         io_in_10_ready,
+  input          io_in_10_valid,
+  input  [10:0]  io_in_10_bits_tgtID,
+  input  [11:0]  io_in_10_bits_txnID,
+  input  [1:0]   io_in_10_bits_respErr,
+  input  [1:0]   io_in_10_bits_ccID,
+  input  [1:0]   io_in_10_bits_dataID,
+  input          io_in_10_bits_traceTag,
+  input  [31:0]  io_in_10_bits_be,
+  input  [255:0] io_in_10_bits_data,
+  input  [31:0]  io_in_10_bits_dataCheck,
+  input  [3:0]   io_in_10_bits_poison,
+  output         io_in_11_ready,
+  input          io_in_11_valid,
+  input  [10:0]  io_in_11_bits_tgtID,
+  input  [11:0]  io_in_11_bits_txnID,
+  input  [1:0]   io_in_11_bits_respErr,
+  input  [1:0]   io_in_11_bits_ccID,
+  input  [1:0]   io_in_11_bits_dataID,
+  input          io_in_11_bits_traceTag,
+  input  [31:0]  io_in_11_bits_be,
+  input  [255:0] io_in_11_bits_data,
+  input  [31:0]  io_in_11_bits_dataCheck,
+  input  [3:0]   io_in_11_bits_poison,
+  output         io_in_12_ready,
+  input          io_in_12_valid,
+  input  [10:0]  io_in_12_bits_tgtID,
+  input  [11:0]  io_in_12_bits_txnID,
+  input  [1:0]   io_in_12_bits_respErr,
+  input  [1:0]   io_in_12_bits_ccID,
+  input  [1:0]   io_in_12_bits_dataID,
+  input          io_in_12_bits_traceTag,
+  input  [31:0]  io_in_12_bits_be,
+  input  [255:0] io_in_12_bits_data,
+  input  [31:0]  io_in_12_bits_dataCheck,
+  input  [3:0]   io_in_12_bits_poison,
+  output         io_in_13_ready,
+  input          io_in_13_valid,
+  input  [10:0]  io_in_13_bits_tgtID,
+  input  [11:0]  io_in_13_bits_txnID,
+  input  [1:0]   io_in_13_bits_respErr,
+  input  [1:0]   io_in_13_bits_ccID,
+  input  [1:0]   io_in_13_bits_dataID,
+  input          io_in_13_bits_traceTag,
+  input  [31:0]  io_in_13_bits_be,
+  input  [255:0] io_in_13_bits_data,
+  input  [31:0]  io_in_13_bits_dataCheck,
+  input  [3:0]   io_in_13_bits_poison,
+  output         io_in_14_ready,
+  input          io_in_14_valid,
+  input  [10:0]  io_in_14_bits_tgtID,
+  input  [11:0]  io_in_14_bits_txnID,
+  input  [1:0]   io_in_14_bits_respErr,
+  input  [1:0]   io_in_14_bits_ccID,
+  input  [1:0]   io_in_14_bits_dataID,
+  input          io_in_14_bits_traceTag,
+  input  [31:0]  io_in_14_bits_be,
+  input  [255:0] io_in_14_bits_data,
+  input  [31:0]  io_in_14_bits_dataCheck,
+  input  [3:0]   io_in_14_bits_poison,
+  output         io_in_15_ready,
+  input          io_in_15_valid,
+  input  [10:0]  io_in_15_bits_tgtID,
+  input  [11:0]  io_in_15_bits_txnID,
+  input  [1:0]   io_in_15_bits_respErr,
+  input  [1:0]   io_in_15_bits_ccID,
+  input  [1:0]   io_in_15_bits_dataID,
+  input          io_in_15_bits_traceTag,
+  input  [31:0]  io_in_15_bits_be,
+  input  [255:0] io_in_15_bits_data,
+  input  [31:0]  io_in_15_bits_dataCheck,
+  input  [3:0]   io_in_15_bits_poison,
+  input          io_out_ready,
+  output         io_out_valid,
+  output [10:0]  io_out_bits_tgtID,
+  output [11:0]  io_out_bits_txnID,
+  output [1:0]   io_out_bits_respErr,
+  output [1:0]   io_out_bits_ccID,
+  output [1:0]   io_out_bits_dataID,
+  output         io_out_bits_traceTag,
+  output [31:0]  io_out_bits_be,
+  output [255:0] io_out_bits_data,
+  output [31:0]  io_out_bits_dataCheck,
+  output [3:0]   io_out_bits_poison
+);
+
+  wire _grant_T = io_in_0_valid | io_in_1_valid;
+  wire _grant_T_1 = _grant_T | io_in_2_valid;
+  wire _grant_T_2 = _grant_T_1 | io_in_3_valid;
+  wire _grant_T_3 = _grant_T_2 | io_in_4_valid;
+  wire _grant_T_4 = _grant_T_3 | io_in_5_valid;
+  wire _grant_T_5 = _grant_T_4 | io_in_6_valid;
+  wire _grant_T_6 = _grant_T_5 | io_in_7_valid;
+  wire _grant_T_7 = _grant_T_6 | io_in_8_valid;
+  wire _grant_T_8 = _grant_T_7 | io_in_9_valid;
+  wire _grant_T_9 = _grant_T_8 | io_in_10_valid;
+  wire _grant_T_10 = _grant_T_9 | io_in_11_valid;
+  wire _grant_T_11 = _grant_T_10 | io_in_12_valid;
+  wire _grant_T_12 = _grant_T_11 | io_in_13_valid;
+  wire _io_out_valid_T = _grant_T_12 | io_in_14_valid;
+  assign io_in_0_ready = io_out_ready;
+  assign io_in_1_ready = ~io_in_0_valid & io_out_ready;
+  assign io_in_2_ready = ~_grant_T & io_out_ready;
+  assign io_in_3_ready = ~_grant_T_1 & io_out_ready;
+  assign io_in_4_ready = ~_grant_T_2 & io_out_ready;
+  assign io_in_5_ready = ~_grant_T_3 & io_out_ready;
+  assign io_in_6_ready = ~_grant_T_4 & io_out_ready;
+  assign io_in_7_ready = ~_grant_T_5 & io_out_ready;
+  assign io_in_8_ready = ~_grant_T_6 & io_out_ready;
+  assign io_in_9_ready = ~_grant_T_7 & io_out_ready;
+  assign io_in_10_ready = ~_grant_T_8 & io_out_ready;
+  assign io_in_11_ready = ~_grant_T_9 & io_out_ready;
+  assign io_in_12_ready = ~_grant_T_10 & io_out_ready;
+  assign io_in_13_ready = ~_grant_T_11 & io_out_ready;
+  assign io_in_14_ready = ~_grant_T_12 & io_out_ready;
+  assign io_in_15_ready = ~_io_out_valid_T & io_out_ready;
+  assign io_out_valid = _io_out_valid_T | io_in_15_valid;
+  assign io_out_bits_tgtID =
+    io_in_0_valid
+      ? io_in_0_bits_tgtID
+      : io_in_1_valid
+          ? io_in_1_bits_tgtID
+          : io_in_2_valid
+              ? io_in_2_bits_tgtID
+              : io_in_3_valid
+                  ? io_in_3_bits_tgtID
+                  : io_in_4_valid
+                      ? io_in_4_bits_tgtID
+                      : io_in_5_valid
+                          ? io_in_5_bits_tgtID
+                          : io_in_6_valid
+                              ? io_in_6_bits_tgtID
+                              : io_in_7_valid
+                                  ? io_in_7_bits_tgtID
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_tgtID
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_tgtID
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_tgtID
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_tgtID
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_tgtID
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_tgtID
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_tgtID
+                                                              : io_in_15_bits_tgtID;
+  assign io_out_bits_txnID =
+    io_in_0_valid
+      ? io_in_0_bits_txnID
+      : io_in_1_valid
+          ? io_in_1_bits_txnID
+          : io_in_2_valid
+              ? io_in_2_bits_txnID
+              : io_in_3_valid
+                  ? io_in_3_bits_txnID
+                  : io_in_4_valid
+                      ? io_in_4_bits_txnID
+                      : io_in_5_valid
+                          ? io_in_5_bits_txnID
+                          : io_in_6_valid
+                              ? io_in_6_bits_txnID
+                              : io_in_7_valid
+                                  ? io_in_7_bits_txnID
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_txnID
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_txnID
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_txnID
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_txnID
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_txnID
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_txnID
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_txnID
+                                                              : io_in_15_bits_txnID;
+  assign io_out_bits_respErr =
+    io_in_0_valid
+      ? io_in_0_bits_respErr
+      : io_in_1_valid
+          ? io_in_1_bits_respErr
+          : io_in_2_valid
+              ? io_in_2_bits_respErr
+              : io_in_3_valid
+                  ? io_in_3_bits_respErr
+                  : io_in_4_valid
+                      ? io_in_4_bits_respErr
+                      : io_in_5_valid
+                          ? io_in_5_bits_respErr
+                          : io_in_6_valid
+                              ? io_in_6_bits_respErr
+                              : io_in_7_valid
+                                  ? io_in_7_bits_respErr
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_respErr
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_respErr
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_respErr
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_respErr
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_respErr
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_respErr
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_respErr
+                                                              : io_in_15_bits_respErr;
+  assign io_out_bits_ccID =
+    io_in_0_valid
+      ? io_in_0_bits_ccID
+      : io_in_1_valid
+          ? io_in_1_bits_ccID
+          : io_in_2_valid
+              ? io_in_2_bits_ccID
+              : io_in_3_valid
+                  ? io_in_3_bits_ccID
+                  : io_in_4_valid
+                      ? io_in_4_bits_ccID
+                      : io_in_5_valid
+                          ? io_in_5_bits_ccID
+                          : io_in_6_valid
+                              ? io_in_6_bits_ccID
+                              : io_in_7_valid
+                                  ? io_in_7_bits_ccID
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_ccID
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_ccID
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_ccID
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_ccID
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_ccID
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_ccID
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_ccID
+                                                              : io_in_15_bits_ccID;
+  assign io_out_bits_dataID =
+    io_in_0_valid
+      ? io_in_0_bits_dataID
+      : io_in_1_valid
+          ? io_in_1_bits_dataID
+          : io_in_2_valid
+              ? io_in_2_bits_dataID
+              : io_in_3_valid
+                  ? io_in_3_bits_dataID
+                  : io_in_4_valid
+                      ? io_in_4_bits_dataID
+                      : io_in_5_valid
+                          ? io_in_5_bits_dataID
+                          : io_in_6_valid
+                              ? io_in_6_bits_dataID
+                              : io_in_7_valid
+                                  ? io_in_7_bits_dataID
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_dataID
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_dataID
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_dataID
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_dataID
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_dataID
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_dataID
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_dataID
+                                                              : io_in_15_bits_dataID;
+  assign io_out_bits_traceTag =
+    io_in_0_valid
+      ? io_in_0_bits_traceTag
+      : io_in_1_valid
+          ? io_in_1_bits_traceTag
+          : io_in_2_valid
+              ? io_in_2_bits_traceTag
+              : io_in_3_valid
+                  ? io_in_3_bits_traceTag
+                  : io_in_4_valid
+                      ? io_in_4_bits_traceTag
+                      : io_in_5_valid
+                          ? io_in_5_bits_traceTag
+                          : io_in_6_valid
+                              ? io_in_6_bits_traceTag
+                              : io_in_7_valid
+                                  ? io_in_7_bits_traceTag
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_traceTag
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_traceTag
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_traceTag
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_traceTag
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_traceTag
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_traceTag
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_traceTag
+                                                              : io_in_15_bits_traceTag;
+  assign io_out_bits_be =
+    io_in_0_valid
+      ? io_in_0_bits_be
+      : io_in_1_valid
+          ? io_in_1_bits_be
+          : io_in_2_valid
+              ? io_in_2_bits_be
+              : io_in_3_valid
+                  ? io_in_3_bits_be
+                  : io_in_4_valid
+                      ? io_in_4_bits_be
+                      : io_in_5_valid
+                          ? io_in_5_bits_be
+                          : io_in_6_valid
+                              ? io_in_6_bits_be
+                              : io_in_7_valid
+                                  ? io_in_7_bits_be
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_be
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_be
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_be
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_be
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_be
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_be
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_be
+                                                              : io_in_15_bits_be;
+  assign io_out_bits_data =
+    io_in_0_valid
+      ? io_in_0_bits_data
+      : io_in_1_valid
+          ? io_in_1_bits_data
+          : io_in_2_valid
+              ? io_in_2_bits_data
+              : io_in_3_valid
+                  ? io_in_3_bits_data
+                  : io_in_4_valid
+                      ? io_in_4_bits_data
+                      : io_in_5_valid
+                          ? io_in_5_bits_data
+                          : io_in_6_valid
+                              ? io_in_6_bits_data
+                              : io_in_7_valid
+                                  ? io_in_7_bits_data
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_data
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_data
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_data
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_data
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_data
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_data
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_data
+                                                              : io_in_15_bits_data;
+  assign io_out_bits_dataCheck =
+    io_in_0_valid
+      ? io_in_0_bits_dataCheck
+      : io_in_1_valid
+          ? io_in_1_bits_dataCheck
+          : io_in_2_valid
+              ? io_in_2_bits_dataCheck
+              : io_in_3_valid
+                  ? io_in_3_bits_dataCheck
+                  : io_in_4_valid
+                      ? io_in_4_bits_dataCheck
+                      : io_in_5_valid
+                          ? io_in_5_bits_dataCheck
+                          : io_in_6_valid
+                              ? io_in_6_bits_dataCheck
+                              : io_in_7_valid
+                                  ? io_in_7_bits_dataCheck
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_dataCheck
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_dataCheck
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_dataCheck
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_dataCheck
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_dataCheck
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_dataCheck
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_dataCheck
+                                                              : io_in_15_bits_dataCheck;
+  assign io_out_bits_poison =
+    io_in_0_valid
+      ? io_in_0_bits_poison
+      : io_in_1_valid
+          ? io_in_1_bits_poison
+          : io_in_2_valid
+              ? io_in_2_bits_poison
+              : io_in_3_valid
+                  ? io_in_3_bits_poison
+                  : io_in_4_valid
+                      ? io_in_4_bits_poison
+                      : io_in_5_valid
+                          ? io_in_5_bits_poison
+                          : io_in_6_valid
+                              ? io_in_6_bits_poison
+                              : io_in_7_valid
+                                  ? io_in_7_bits_poison
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_poison
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_poison
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_poison
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_poison
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_poison
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_poison
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_poison
+                                                              : io_in_15_bits_poison;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Arbiter16_TLBundleD.sv b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter16_TLBundleD.sv
new file mode 100644
index 0000000000..97dd0a225b
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter16_TLBundleD.sv
@@ -0,0 +1,364 @@
+// Generated by CIRCT firtool-1.135.0
+module Arbiter16_TLBundleD(
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [3:0]  io_in_0_bits_opcode,
+  input  [1:0]  io_in_0_bits_size,
+  input  [4:0]  io_in_0_bits_source,
+  input         io_in_0_bits_denied,
+  input  [63:0] io_in_0_bits_data,
+  input         io_in_0_bits_corrupt,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [3:0]  io_in_1_bits_opcode,
+  input  [1:0]  io_in_1_bits_size,
+  input  [4:0]  io_in_1_bits_source,
+  input         io_in_1_bits_denied,
+  input  [63:0] io_in_1_bits_data,
+  input         io_in_1_bits_corrupt,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [3:0]  io_in_2_bits_opcode,
+  input  [1:0]  io_in_2_bits_size,
+  input  [4:0]  io_in_2_bits_source,
+  input         io_in_2_bits_denied,
+  input  [63:0] io_in_2_bits_data,
+  input         io_in_2_bits_corrupt,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [3:0]  io_in_3_bits_opcode,
+  input  [1:0]  io_in_3_bits_size,
+  input  [4:0]  io_in_3_bits_source,
+  input         io_in_3_bits_denied,
+  input  [63:0] io_in_3_bits_data,
+  input         io_in_3_bits_corrupt,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [3:0]  io_in_4_bits_opcode,
+  input  [1:0]  io_in_4_bits_size,
+  input  [4:0]  io_in_4_bits_source,
+  input         io_in_4_bits_denied,
+  input  [63:0] io_in_4_bits_data,
+  input         io_in_4_bits_corrupt,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [3:0]  io_in_5_bits_opcode,
+  input  [1:0]  io_in_5_bits_size,
+  input  [4:0]  io_in_5_bits_source,
+  input         io_in_5_bits_denied,
+  input  [63:0] io_in_5_bits_data,
+  input         io_in_5_bits_corrupt,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [3:0]  io_in_6_bits_opcode,
+  input  [1:0]  io_in_6_bits_size,
+  input  [4:0]  io_in_6_bits_source,
+  input         io_in_6_bits_denied,
+  input  [63:0] io_in_6_bits_data,
+  input         io_in_6_bits_corrupt,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [3:0]  io_in_7_bits_opcode,
+  input  [1:0]  io_in_7_bits_size,
+  input  [4:0]  io_in_7_bits_source,
+  input         io_in_7_bits_denied,
+  input  [63:0] io_in_7_bits_data,
+  input         io_in_7_bits_corrupt,
+  output        io_in_8_ready,
+  input         io_in_8_valid,
+  input  [3:0]  io_in_8_bits_opcode,
+  input  [1:0]  io_in_8_bits_size,
+  input  [4:0]  io_in_8_bits_source,
+  input         io_in_8_bits_denied,
+  input  [63:0] io_in_8_bits_data,
+  input         io_in_8_bits_corrupt,
+  output        io_in_9_ready,
+  input         io_in_9_valid,
+  input  [3:0]  io_in_9_bits_opcode,
+  input  [1:0]  io_in_9_bits_size,
+  input  [4:0]  io_in_9_bits_source,
+  input         io_in_9_bits_denied,
+  input  [63:0] io_in_9_bits_data,
+  input         io_in_9_bits_corrupt,
+  output        io_in_10_ready,
+  input         io_in_10_valid,
+  input  [3:0]  io_in_10_bits_opcode,
+  input  [1:0]  io_in_10_bits_size,
+  input  [4:0]  io_in_10_bits_source,
+  input         io_in_10_bits_denied,
+  input  [63:0] io_in_10_bits_data,
+  input         io_in_10_bits_corrupt,
+  output        io_in_11_ready,
+  input         io_in_11_valid,
+  input  [3:0]  io_in_11_bits_opcode,
+  input  [1:0]  io_in_11_bits_size,
+  input  [4:0]  io_in_11_bits_source,
+  input         io_in_11_bits_denied,
+  input  [63:0] io_in_11_bits_data,
+  input         io_in_11_bits_corrupt,
+  output        io_in_12_ready,
+  input         io_in_12_valid,
+  input  [3:0]  io_in_12_bits_opcode,
+  input  [1:0]  io_in_12_bits_size,
+  input  [4:0]  io_in_12_bits_source,
+  input         io_in_12_bits_denied,
+  input  [63:0] io_in_12_bits_data,
+  input         io_in_12_bits_corrupt,
+  output        io_in_13_ready,
+  input         io_in_13_valid,
+  input  [3:0]  io_in_13_bits_opcode,
+  input  [1:0]  io_in_13_bits_size,
+  input  [4:0]  io_in_13_bits_source,
+  input         io_in_13_bits_denied,
+  input  [63:0] io_in_13_bits_data,
+  input         io_in_13_bits_corrupt,
+  output        io_in_14_ready,
+  input         io_in_14_valid,
+  input  [3:0]  io_in_14_bits_opcode,
+  input  [1:0]  io_in_14_bits_size,
+  input  [4:0]  io_in_14_bits_source,
+  input         io_in_14_bits_denied,
+  input  [63:0] io_in_14_bits_data,
+  input         io_in_14_bits_corrupt,
+  output        io_in_15_ready,
+  input         io_in_15_valid,
+  input  [3:0]  io_in_15_bits_opcode,
+  input  [1:0]  io_in_15_bits_size,
+  input  [4:0]  io_in_15_bits_source,
+  input         io_in_15_bits_denied,
+  input  [63:0] io_in_15_bits_data,
+  input         io_in_15_bits_corrupt,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_opcode,
+  output [1:0]  io_out_bits_size,
+  output [4:0]  io_out_bits_source,
+  output        io_out_bits_denied,
+  output [63:0] io_out_bits_data,
+  output        io_out_bits_corrupt
+);
+
+  wire _grant_T = io_in_0_valid | io_in_1_valid;
+  wire _grant_T_1 = _grant_T | io_in_2_valid;
+  wire _grant_T_2 = _grant_T_1 | io_in_3_valid;
+  wire _grant_T_3 = _grant_T_2 | io_in_4_valid;
+  wire _grant_T_4 = _grant_T_3 | io_in_5_valid;
+  wire _grant_T_5 = _grant_T_4 | io_in_6_valid;
+  wire _grant_T_6 = _grant_T_5 | io_in_7_valid;
+  wire _grant_T_7 = _grant_T_6 | io_in_8_valid;
+  wire _grant_T_8 = _grant_T_7 | io_in_9_valid;
+  wire _grant_T_9 = _grant_T_8 | io_in_10_valid;
+  wire _grant_T_10 = _grant_T_9 | io_in_11_valid;
+  wire _grant_T_11 = _grant_T_10 | io_in_12_valid;
+  wire _grant_T_12 = _grant_T_11 | io_in_13_valid;
+  wire _io_out_valid_T = _grant_T_12 | io_in_14_valid;
+  assign io_in_0_ready = io_out_ready;
+  assign io_in_1_ready = ~io_in_0_valid & io_out_ready;
+  assign io_in_2_ready = ~_grant_T & io_out_ready;
+  assign io_in_3_ready = ~_grant_T_1 & io_out_ready;
+  assign io_in_4_ready = ~_grant_T_2 & io_out_ready;
+  assign io_in_5_ready = ~_grant_T_3 & io_out_ready;
+  assign io_in_6_ready = ~_grant_T_4 & io_out_ready;
+  assign io_in_7_ready = ~_grant_T_5 & io_out_ready;
+  assign io_in_8_ready = ~_grant_T_6 & io_out_ready;
+  assign io_in_9_ready = ~_grant_T_7 & io_out_ready;
+  assign io_in_10_ready = ~_grant_T_8 & io_out_ready;
+  assign io_in_11_ready = ~_grant_T_9 & io_out_ready;
+  assign io_in_12_ready = ~_grant_T_10 & io_out_ready;
+  assign io_in_13_ready = ~_grant_T_11 & io_out_ready;
+  assign io_in_14_ready = ~_grant_T_12 & io_out_ready;
+  assign io_in_15_ready = ~_io_out_valid_T & io_out_ready;
+  assign io_out_valid = _io_out_valid_T | io_in_15_valid;
+  assign io_out_bits_opcode =
+    io_in_0_valid
+      ? io_in_0_bits_opcode
+      : io_in_1_valid
+          ? io_in_1_bits_opcode
+          : io_in_2_valid
+              ? io_in_2_bits_opcode
+              : io_in_3_valid
+                  ? io_in_3_bits_opcode
+                  : io_in_4_valid
+                      ? io_in_4_bits_opcode
+                      : io_in_5_valid
+                          ? io_in_5_bits_opcode
+                          : io_in_6_valid
+                              ? io_in_6_bits_opcode
+                              : io_in_7_valid
+                                  ? io_in_7_bits_opcode
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_opcode
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_opcode
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_opcode
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_opcode
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_opcode
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_opcode
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_opcode
+                                                              : io_in_15_bits_opcode;
+  assign io_out_bits_size =
+    io_in_0_valid
+      ? io_in_0_bits_size
+      : io_in_1_valid
+          ? io_in_1_bits_size
+          : io_in_2_valid
+              ? io_in_2_bits_size
+              : io_in_3_valid
+                  ? io_in_3_bits_size
+                  : io_in_4_valid
+                      ? io_in_4_bits_size
+                      : io_in_5_valid
+                          ? io_in_5_bits_size
+                          : io_in_6_valid
+                              ? io_in_6_bits_size
+                              : io_in_7_valid
+                                  ? io_in_7_bits_size
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_size
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_size
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_size
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_size
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_size
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_size
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_size
+                                                              : io_in_15_bits_size;
+  assign io_out_bits_source =
+    io_in_0_valid
+      ? io_in_0_bits_source
+      : io_in_1_valid
+          ? io_in_1_bits_source
+          : io_in_2_valid
+              ? io_in_2_bits_source
+              : io_in_3_valid
+                  ? io_in_3_bits_source
+                  : io_in_4_valid
+                      ? io_in_4_bits_source
+                      : io_in_5_valid
+                          ? io_in_5_bits_source
+                          : io_in_6_valid
+                              ? io_in_6_bits_source
+                              : io_in_7_valid
+                                  ? io_in_7_bits_source
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_source
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_source
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_source
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_source
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_source
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_source
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_source
+                                                              : io_in_15_bits_source;
+  assign io_out_bits_denied =
+    io_in_0_valid
+      ? io_in_0_bits_denied
+      : io_in_1_valid
+          ? io_in_1_bits_denied
+          : io_in_2_valid
+              ? io_in_2_bits_denied
+              : io_in_3_valid
+                  ? io_in_3_bits_denied
+                  : io_in_4_valid
+                      ? io_in_4_bits_denied
+                      : io_in_5_valid
+                          ? io_in_5_bits_denied
+                          : io_in_6_valid
+                              ? io_in_6_bits_denied
+                              : io_in_7_valid
+                                  ? io_in_7_bits_denied
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_denied
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_denied
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_denied
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_denied
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_denied
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_denied
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_denied
+                                                              : io_in_15_bits_denied;
+  assign io_out_bits_data =
+    io_in_0_valid
+      ? io_in_0_bits_data
+      : io_in_1_valid
+          ? io_in_1_bits_data
+          : io_in_2_valid
+              ? io_in_2_bits_data
+              : io_in_3_valid
+                  ? io_in_3_bits_data
+                  : io_in_4_valid
+                      ? io_in_4_bits_data
+                      : io_in_5_valid
+                          ? io_in_5_bits_data
+                          : io_in_6_valid
+                              ? io_in_6_bits_data
+                              : io_in_7_valid
+                                  ? io_in_7_bits_data
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_data
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_data
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_data
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_data
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_data
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_data
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_data
+                                                              : io_in_15_bits_data;
+  assign io_out_bits_corrupt =
+    io_in_0_valid
+      ? io_in_0_bits_corrupt
+      : io_in_1_valid
+          ? io_in_1_bits_corrupt
+          : io_in_2_valid
+              ? io_in_2_bits_corrupt
+              : io_in_3_valid
+                  ? io_in_3_bits_corrupt
+                  : io_in_4_valid
+                      ? io_in_4_bits_corrupt
+                      : io_in_5_valid
+                          ? io_in_5_bits_corrupt
+                          : io_in_6_valid
+                              ? io_in_6_bits_corrupt
+                              : io_in_7_valid
+                                  ? io_in_7_bits_corrupt
+                                  : io_in_8_valid
+                                      ? io_in_8_bits_corrupt
+                                      : io_in_9_valid
+                                          ? io_in_9_bits_corrupt
+                                          : io_in_10_valid
+                                              ? io_in_10_bits_corrupt
+                                              : io_in_11_valid
+                                                  ? io_in_11_bits_corrupt
+                                                  : io_in_12_valid
+                                                      ? io_in_12_bits_corrupt
+                                                      : io_in_13_valid
+                                                          ? io_in_13_bits_corrupt
+                                                          : io_in_14_valid
+                                                              ? io_in_14_bits_corrupt
+                                                              : io_in_15_bits_corrupt;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Arbiter1_L2CacheErrorInfo.sv b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter1_L2CacheErrorInfo.sv
new file mode 100644
index 0000000000..bafe9f58ce
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter1_L2CacheErrorInfo.sv
@@ -0,0 +1,14 @@
+// Generated by CIRCT firtool-1.135.0
+module Arbiter1_L2CacheErrorInfo(
+  input         io_in_0_valid,
+  input         io_in_0_bits_valid,
+  input  [47:0] io_in_0_bits_address,
+  output        io_out_valid,
+  output        io_out_bits_valid,
+  output [47:0] io_out_bits_address
+);
+
+  assign io_out_valid = io_in_0_valid;
+  assign io_out_bits_valid = io_in_0_bits_valid;
+  assign io_out_bits_address = io_in_0_bits_address;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_CHIREQ.sv b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_CHIREQ.sv
new file mode 100644
index 0000000000..a611a538af
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_CHIREQ.sv
@@ -0,0 +1,119 @@
+// Generated by CIRCT firtool-1.135.0
+module Arbiter3_CHIREQ(
+  input         io_in_0_valid,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [10:0] io_in_0_bits_srcID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [6:0]  io_in_0_bits_opcode,
+  input  [47:0] io_in_0_bits_addr,
+  input         io_in_0_bits_likelyshared,
+  input         io_in_0_bits_allowRetry,
+  input  [3:0]  io_in_0_bits_pCrdType,
+  input         io_in_0_bits_memAttr_allocate,
+  input         io_in_0_bits_memAttr_cacheable,
+  input         io_in_0_bits_memAttr_device,
+  input         io_in_0_bits_memAttr_ewa,
+  input         io_in_0_bits_expCompAck,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [10:0] io_in_1_bits_srcID,
+  input  [11:0] io_in_1_bits_txnID,
+  input  [6:0]  io_in_1_bits_opcode,
+  input  [47:0] io_in_1_bits_addr,
+  input         io_in_1_bits_likelyshared,
+  input         io_in_1_bits_allowRetry,
+  input  [3:0]  io_in_1_bits_pCrdType,
+  input         io_in_1_bits_memAttr_allocate,
+  input         io_in_1_bits_memAttr_cacheable,
+  input         io_in_1_bits_memAttr_device,
+  input         io_in_1_bits_memAttr_ewa,
+  input         io_in_1_bits_expCompAck,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [10:0] io_in_2_bits_tgtID,
+  input  [10:0] io_in_2_bits_srcID,
+  input  [11:0] io_in_2_bits_txnID,
+  input  [6:0]  io_in_2_bits_opcode,
+  input  [47:0] io_in_2_bits_addr,
+  input         io_in_2_bits_likelyshared,
+  input         io_in_2_bits_allowRetry,
+  input  [3:0]  io_in_2_bits_pCrdType,
+  input         io_in_2_bits_memAttr_allocate,
+  input         io_in_2_bits_memAttr_cacheable,
+  input         io_in_2_bits_memAttr_device,
+  input         io_in_2_bits_memAttr_ewa,
+  input         io_in_2_bits_expCompAck,
+  output        io_out_valid,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [6:0]  io_out_bits_opcode,
+  output [47:0] io_out_bits_addr,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_allowRetry,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_device,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_expCompAck
+);
+
+  wire _io_out_valid_T = io_in_0_valid | io_in_1_valid;
+  assign io_in_1_ready = ~io_in_0_valid;
+  assign io_in_2_ready = ~_io_out_valid_T;
+  assign io_out_valid = _io_out_valid_T | io_in_2_valid;
+  assign io_out_bits_tgtID =
+    io_in_0_valid
+      ? io_in_0_bits_tgtID
+      : io_in_1_valid ? io_in_1_bits_tgtID : io_in_2_bits_tgtID;
+  assign io_out_bits_srcID =
+    io_in_0_valid
+      ? io_in_0_bits_srcID
+      : io_in_1_valid ? io_in_1_bits_srcID : io_in_2_bits_srcID;
+  assign io_out_bits_txnID =
+    io_in_0_valid
+      ? io_in_0_bits_txnID
+      : io_in_1_valid ? io_in_1_bits_txnID : io_in_2_bits_txnID;
+  assign io_out_bits_opcode =
+    io_in_0_valid
+      ? io_in_0_bits_opcode
+      : io_in_1_valid ? io_in_1_bits_opcode : io_in_2_bits_opcode;
+  assign io_out_bits_addr =
+    io_in_0_valid
+      ? io_in_0_bits_addr
+      : io_in_1_valid ? io_in_1_bits_addr : io_in_2_bits_addr;
+  assign io_out_bits_likelyshared =
+    io_in_0_valid
+      ? io_in_0_bits_likelyshared
+      : io_in_1_valid ? io_in_1_bits_likelyshared : io_in_2_bits_likelyshared;
+  assign io_out_bits_allowRetry =
+    io_in_0_valid
+      ? io_in_0_bits_allowRetry
+      : io_in_1_valid ? io_in_1_bits_allowRetry : io_in_2_bits_allowRetry;
+  assign io_out_bits_pCrdType =
+    io_in_0_valid
+      ? io_in_0_bits_pCrdType
+      : io_in_1_valid ? io_in_1_bits_pCrdType : io_in_2_bits_pCrdType;
+  assign io_out_bits_memAttr_allocate =
+    io_in_0_valid
+      ? io_in_0_bits_memAttr_allocate
+      : io_in_1_valid ? io_in_1_bits_memAttr_allocate : io_in_2_bits_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable =
+    io_in_0_valid
+      ? io_in_0_bits_memAttr_cacheable
+      : io_in_1_valid ? io_in_1_bits_memAttr_cacheable : io_in_2_bits_memAttr_cacheable;
+  assign io_out_bits_memAttr_device =
+    io_in_0_valid
+      ? io_in_0_bits_memAttr_device
+      : io_in_1_valid ? io_in_1_bits_memAttr_device : io_in_2_bits_memAttr_device;
+  assign io_out_bits_memAttr_ewa =
+    io_in_0_valid
+      ? io_in_0_bits_memAttr_ewa
+      : io_in_1_valid ? io_in_1_bits_memAttr_ewa : io_in_2_bits_memAttr_ewa;
+  assign io_out_bits_expCompAck =
+    io_in_0_valid
+      ? io_in_0_bits_expCompAck
+      : io_in_1_valid ? io_in_1_bits_expCompAck : io_in_2_bits_expCompAck;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_HintQueueEntry.sv b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_HintQueueEntry.sv
new file mode 100644
index 0000000000..153367f9c5
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_HintQueueEntry.sv
@@ -0,0 +1,48 @@
+// Generated by CIRCT firtool-1.135.0
+module Arbiter3_HintQueueEntry(
+  input        io_in_0_valid,
+  input  [6:0] io_in_0_bits_source,
+  input        io_in_0_bits_isGrantData,
+  input        io_in_0_bits_isKeyword,
+  input        io_in_0_bits_hasData,
+  output       io_in_1_ready,
+  input        io_in_1_valid,
+  input  [6:0] io_in_1_bits_source,
+  input        io_in_1_bits_isGrantData,
+  input        io_in_1_bits_isKeyword,
+  input        io_in_1_bits_hasData,
+  output       io_in_2_ready,
+  input        io_in_2_valid,
+  input  [6:0] io_in_2_bits_source,
+  input        io_in_2_bits_isGrantData,
+  input        io_in_2_bits_isKeyword,
+  input        io_in_2_bits_hasData,
+  input        io_out_ready,
+  output       io_out_valid,
+  output [6:0] io_out_bits_source,
+  output       io_out_bits_isGrantData,
+  output       io_out_bits_isKeyword,
+  output       io_out_bits_hasData
+);
+
+  wire _io_out_valid_T = io_in_0_valid | io_in_1_valid;
+  assign io_in_1_ready = ~io_in_0_valid & io_out_ready;
+  assign io_in_2_ready = ~_io_out_valid_T & io_out_ready;
+  assign io_out_valid = _io_out_valid_T | io_in_2_valid;
+  assign io_out_bits_source =
+    io_in_0_valid
+      ? io_in_0_bits_source
+      : io_in_1_valid ? io_in_1_bits_source : io_in_2_bits_source;
+  assign io_out_bits_isGrantData =
+    io_in_0_valid
+      ? io_in_0_bits_isGrantData
+      : io_in_1_valid ? io_in_1_bits_isGrantData : io_in_2_bits_isGrantData;
+  assign io_out_bits_isKeyword =
+    io_in_0_valid
+      ? io_in_0_bits_isKeyword
+      : io_in_1_valid ? io_in_1_bits_isKeyword : io_in_2_bits_isKeyword;
+  assign io_out_bits_hasData =
+    io_in_0_valid
+      ? io_in_0_bits_hasData
+      : io_in_1_valid ? io_in_1_bits_hasData : io_in_2_bits_hasData;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_TaskBundle.sv b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_TaskBundle.sv
new file mode 100644
index 0000000000..329d911a83
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_TaskBundle.sv
@@ -0,0 +1,95 @@
+// Generated by CIRCT firtool-1.135.0
+module Arbiter3_TaskBundle(
+  input         io_in_0_valid,
+  input         io_in_0_bits_denied,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [10:0] io_in_0_bits_srcID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [11:0] io_in_0_bits_dbID,
+  input  [6:0]  io_in_0_bits_chiOpcode,
+  input  [2:0]  io_in_0_bits_resp,
+  input  [2:0]  io_in_0_bits_fwdState,
+  input  [3:0]  io_in_0_bits_pCrdType,
+  input         io_in_0_bits_traceTag,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input         io_in_1_bits_denied,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [10:0] io_in_1_bits_srcID,
+  input  [11:0] io_in_1_bits_txnID,
+  input  [11:0] io_in_1_bits_dbID,
+  input  [6:0]  io_in_1_bits_chiOpcode,
+  input  [2:0]  io_in_1_bits_resp,
+  input  [2:0]  io_in_1_bits_fwdState,
+  input  [3:0]  io_in_1_bits_pCrdType,
+  input         io_in_1_bits_traceTag,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input         io_in_2_bits_denied,
+  input  [10:0] io_in_2_bits_tgtID,
+  input  [10:0] io_in_2_bits_srcID,
+  input  [11:0] io_in_2_bits_txnID,
+  input  [11:0] io_in_2_bits_dbID,
+  input  [6:0]  io_in_2_bits_chiOpcode,
+  input  [2:0]  io_in_2_bits_resp,
+  input  [2:0]  io_in_2_bits_fwdState,
+  input  [3:0]  io_in_2_bits_pCrdType,
+  input         io_in_2_bits_traceTag,
+  output        io_out_valid,
+  output        io_out_bits_denied,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [11:0] io_out_bits_dbID,
+  output [6:0]  io_out_bits_chiOpcode,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_traceTag
+);
+
+  wire _io_out_valid_T = io_in_0_valid | io_in_1_valid;
+  assign io_in_1_ready = ~io_in_0_valid;
+  assign io_in_2_ready = ~_io_out_valid_T;
+  assign io_out_valid = _io_out_valid_T | io_in_2_valid;
+  assign io_out_bits_denied =
+    io_in_0_valid
+      ? io_in_0_bits_denied
+      : io_in_1_valid ? io_in_1_bits_denied : io_in_2_bits_denied;
+  assign io_out_bits_tgtID =
+    io_in_0_valid
+      ? io_in_0_bits_tgtID
+      : io_in_1_valid ? io_in_1_bits_tgtID : io_in_2_bits_tgtID;
+  assign io_out_bits_srcID =
+    io_in_0_valid
+      ? io_in_0_bits_srcID
+      : io_in_1_valid ? io_in_1_bits_srcID : io_in_2_bits_srcID;
+  assign io_out_bits_txnID =
+    io_in_0_valid
+      ? io_in_0_bits_txnID
+      : io_in_1_valid ? io_in_1_bits_txnID : io_in_2_bits_txnID;
+  assign io_out_bits_dbID =
+    io_in_0_valid
+      ? io_in_0_bits_dbID
+      : io_in_1_valid ? io_in_1_bits_dbID : io_in_2_bits_dbID;
+  assign io_out_bits_chiOpcode =
+    io_in_0_valid
+      ? io_in_0_bits_chiOpcode
+      : io_in_1_valid ? io_in_1_bits_chiOpcode : io_in_2_bits_chiOpcode;
+  assign io_out_bits_resp =
+    io_in_0_valid
+      ? io_in_0_bits_resp
+      : io_in_1_valid ? io_in_1_bits_resp : io_in_2_bits_resp;
+  assign io_out_bits_fwdState =
+    io_in_0_valid
+      ? io_in_0_bits_fwdState
+      : io_in_1_valid ? io_in_1_bits_fwdState : io_in_2_bits_fwdState;
+  assign io_out_bits_pCrdType =
+    io_in_0_valid
+      ? io_in_0_bits_pCrdType
+      : io_in_1_valid ? io_in_1_bits_pCrdType : io_in_2_bits_pCrdType;
+  assign io_out_bits_traceTag =
+    io_in_0_valid
+      ? io_in_0_bits_traceTag
+      : io_in_1_valid ? io_in_1_bits_traceTag : io_in_2_bits_traceTag;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_TaskWithData.sv b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_TaskWithData.sv
new file mode 100644
index 0000000000..b939f3e6f8
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Arbiter3_TaskWithData.sv
@@ -0,0 +1,846 @@
+// Generated by CIRCT firtool-1.135.0
+module Arbiter3_TaskWithData(
+  input          io_in_0_valid,
+  input  [2:0]   io_in_0_bits_task_channel,
+  input  [2:0]   io_in_0_bits_task_txChannel,
+  input  [7:0]   io_in_0_bits_task_set,
+  input  [33:0]  io_in_0_bits_task_tag,
+  input  [5:0]   io_in_0_bits_task_off,
+  input          io_in_0_bits_task_alias,
+  input  [43:0]  io_in_0_bits_task_vaddr,
+  input          io_in_0_bits_task_isKeyword,
+  input  [3:0]   io_in_0_bits_task_opcode,
+  input  [2:0]   io_in_0_bits_task_param,
+  input  [2:0]   io_in_0_bits_task_size,
+  input  [6:0]   io_in_0_bits_task_sourceId,
+  input  [1:0]   io_in_0_bits_task_bufIdx,
+  input          io_in_0_bits_task_needProbeAckData,
+  input          io_in_0_bits_task_denied,
+  input          io_in_0_bits_task_corrupt,
+  input          io_in_0_bits_task_mshrTask,
+  input  [7:0]   io_in_0_bits_task_mshrId,
+  input          io_in_0_bits_task_aliasTask,
+  input          io_in_0_bits_task_useProbeData,
+  input          io_in_0_bits_task_mshrRetry,
+  input          io_in_0_bits_task_readProbeDataDown,
+  input          io_in_0_bits_task_fromL2pft,
+  input          io_in_0_bits_task_needHint,
+  input          io_in_0_bits_task_dirty,
+  input  [2:0]   io_in_0_bits_task_way,
+  input          io_in_0_bits_task_meta_dirty,
+  input  [1:0]   io_in_0_bits_task_meta_state,
+  input          io_in_0_bits_task_meta_clients,
+  input          io_in_0_bits_task_meta_alias,
+  input          io_in_0_bits_task_meta_prefetch,
+  input  [3:0]   io_in_0_bits_task_meta_prefetchSrc,
+  input          io_in_0_bits_task_meta_accessed,
+  input          io_in_0_bits_task_meta_tagErr,
+  input          io_in_0_bits_task_meta_dataErr,
+  input          io_in_0_bits_task_metaWen,
+  input          io_in_0_bits_task_tagWen,
+  input          io_in_0_bits_task_dsWen,
+  input  [7:0]   io_in_0_bits_task_wayMask,
+  input          io_in_0_bits_task_replTask,
+  input          io_in_0_bits_task_cmoTask,
+  input          io_in_0_bits_task_cmoAll,
+  input  [4:0]   io_in_0_bits_task_reqSource,
+  input          io_in_0_bits_task_mergeA,
+  input  [5:0]   io_in_0_bits_task_aMergeTask_off,
+  input          io_in_0_bits_task_aMergeTask_alias,
+  input  [43:0]  io_in_0_bits_task_aMergeTask_vaddr,
+  input          io_in_0_bits_task_aMergeTask_isKeyword,
+  input  [2:0]   io_in_0_bits_task_aMergeTask_opcode,
+  input  [2:0]   io_in_0_bits_task_aMergeTask_param,
+  input  [6:0]   io_in_0_bits_task_aMergeTask_sourceId,
+  input          io_in_0_bits_task_aMergeTask_meta_dirty,
+  input  [1:0]   io_in_0_bits_task_aMergeTask_meta_state,
+  input          io_in_0_bits_task_aMergeTask_meta_clients,
+  input          io_in_0_bits_task_aMergeTask_meta_alias,
+  input          io_in_0_bits_task_aMergeTask_meta_prefetch,
+  input  [3:0]   io_in_0_bits_task_aMergeTask_meta_prefetchSrc,
+  input          io_in_0_bits_task_aMergeTask_meta_accessed,
+  input          io_in_0_bits_task_aMergeTask_meta_tagErr,
+  input          io_in_0_bits_task_aMergeTask_meta_dataErr,
+  input          io_in_0_bits_task_snpHitRelease,
+  input          io_in_0_bits_task_snpHitReleaseToInval,
+  input          io_in_0_bits_task_snpHitReleaseToClean,
+  input          io_in_0_bits_task_snpHitReleaseWithData,
+  input  [7:0]   io_in_0_bits_task_snpHitReleaseIdx,
+  input          io_in_0_bits_task_snpHitReleaseMeta_dirty,
+  input  [1:0]   io_in_0_bits_task_snpHitReleaseMeta_state,
+  input          io_in_0_bits_task_snpHitReleaseMeta_clients,
+  input          io_in_0_bits_task_snpHitReleaseMeta_alias,
+  input          io_in_0_bits_task_snpHitReleaseMeta_prefetch,
+  input  [3:0]   io_in_0_bits_task_snpHitReleaseMeta_prefetchSrc,
+  input          io_in_0_bits_task_snpHitReleaseMeta_accessed,
+  input          io_in_0_bits_task_snpHitReleaseMeta_tagErr,
+  input          io_in_0_bits_task_snpHitReleaseMeta_dataErr,
+  input  [10:0]  io_in_0_bits_task_tgtID,
+  input  [10:0]  io_in_0_bits_task_srcID,
+  input  [11:0]  io_in_0_bits_task_txnID,
+  input  [10:0]  io_in_0_bits_task_homeNID,
+  input  [11:0]  io_in_0_bits_task_dbID,
+  input  [10:0]  io_in_0_bits_task_fwdNID,
+  input  [11:0]  io_in_0_bits_task_fwdTxnID,
+  input  [6:0]   io_in_0_bits_task_chiOpcode,
+  input  [2:0]   io_in_0_bits_task_resp,
+  input  [2:0]   io_in_0_bits_task_fwdState,
+  input  [3:0]   io_in_0_bits_task_pCrdType,
+  input          io_in_0_bits_task_retToSrc,
+  input          io_in_0_bits_task_likelyshared,
+  input          io_in_0_bits_task_expCompAck,
+  input          io_in_0_bits_task_allowRetry,
+  input          io_in_0_bits_task_memAttr_allocate,
+  input          io_in_0_bits_task_memAttr_cacheable,
+  input          io_in_0_bits_task_memAttr_device,
+  input          io_in_0_bits_task_memAttr_ewa,
+  input          io_in_0_bits_task_traceTag,
+  input  [511:0] io_in_0_bits_data_data,
+  output         io_in_1_ready,
+  input          io_in_1_valid,
+  input  [2:0]   io_in_1_bits_task_channel,
+  input  [2:0]   io_in_1_bits_task_txChannel,
+  input  [7:0]   io_in_1_bits_task_set,
+  input  [33:0]  io_in_1_bits_task_tag,
+  input  [5:0]   io_in_1_bits_task_off,
+  input          io_in_1_bits_task_alias,
+  input  [43:0]  io_in_1_bits_task_vaddr,
+  input          io_in_1_bits_task_isKeyword,
+  input  [3:0]   io_in_1_bits_task_opcode,
+  input  [2:0]   io_in_1_bits_task_param,
+  input  [2:0]   io_in_1_bits_task_size,
+  input  [6:0]   io_in_1_bits_task_sourceId,
+  input  [1:0]   io_in_1_bits_task_bufIdx,
+  input          io_in_1_bits_task_needProbeAckData,
+  input          io_in_1_bits_task_denied,
+  input          io_in_1_bits_task_corrupt,
+  input          io_in_1_bits_task_mshrTask,
+  input  [7:0]   io_in_1_bits_task_mshrId,
+  input          io_in_1_bits_task_aliasTask,
+  input          io_in_1_bits_task_useProbeData,
+  input          io_in_1_bits_task_mshrRetry,
+  input          io_in_1_bits_task_readProbeDataDown,
+  input          io_in_1_bits_task_fromL2pft,
+  input          io_in_1_bits_task_needHint,
+  input          io_in_1_bits_task_dirty,
+  input  [2:0]   io_in_1_bits_task_way,
+  input          io_in_1_bits_task_meta_dirty,
+  input  [1:0]   io_in_1_bits_task_meta_state,
+  input          io_in_1_bits_task_meta_clients,
+  input          io_in_1_bits_task_meta_alias,
+  input          io_in_1_bits_task_meta_prefetch,
+  input  [3:0]   io_in_1_bits_task_meta_prefetchSrc,
+  input          io_in_1_bits_task_meta_accessed,
+  input          io_in_1_bits_task_meta_tagErr,
+  input          io_in_1_bits_task_meta_dataErr,
+  input          io_in_1_bits_task_metaWen,
+  input          io_in_1_bits_task_tagWen,
+  input          io_in_1_bits_task_dsWen,
+  input  [7:0]   io_in_1_bits_task_wayMask,
+  input          io_in_1_bits_task_replTask,
+  input          io_in_1_bits_task_cmoTask,
+  input          io_in_1_bits_task_cmoAll,
+  input  [4:0]   io_in_1_bits_task_reqSource,
+  input          io_in_1_bits_task_mergeA,
+  input  [5:0]   io_in_1_bits_task_aMergeTask_off,
+  input          io_in_1_bits_task_aMergeTask_alias,
+  input  [43:0]  io_in_1_bits_task_aMergeTask_vaddr,
+  input          io_in_1_bits_task_aMergeTask_isKeyword,
+  input  [2:0]   io_in_1_bits_task_aMergeTask_opcode,
+  input  [2:0]   io_in_1_bits_task_aMergeTask_param,
+  input  [6:0]   io_in_1_bits_task_aMergeTask_sourceId,
+  input          io_in_1_bits_task_aMergeTask_meta_dirty,
+  input  [1:0]   io_in_1_bits_task_aMergeTask_meta_state,
+  input          io_in_1_bits_task_aMergeTask_meta_clients,
+  input          io_in_1_bits_task_aMergeTask_meta_alias,
+  input          io_in_1_bits_task_aMergeTask_meta_prefetch,
+  input  [3:0]   io_in_1_bits_task_aMergeTask_meta_prefetchSrc,
+  input          io_in_1_bits_task_aMergeTask_meta_accessed,
+  input          io_in_1_bits_task_aMergeTask_meta_tagErr,
+  input          io_in_1_bits_task_aMergeTask_meta_dataErr,
+  input          io_in_1_bits_task_snpHitRelease,
+  input          io_in_1_bits_task_snpHitReleaseToInval,
+  input          io_in_1_bits_task_snpHitReleaseToClean,
+  input          io_in_1_bits_task_snpHitReleaseWithData,
+  input  [7:0]   io_in_1_bits_task_snpHitReleaseIdx,
+  input          io_in_1_bits_task_snpHitReleaseMeta_dirty,
+  input  [1:0]   io_in_1_bits_task_snpHitReleaseMeta_state,
+  input          io_in_1_bits_task_snpHitReleaseMeta_clients,
+  input          io_in_1_bits_task_snpHitReleaseMeta_alias,
+  input          io_in_1_bits_task_snpHitReleaseMeta_prefetch,
+  input  [3:0]   io_in_1_bits_task_snpHitReleaseMeta_prefetchSrc,
+  input          io_in_1_bits_task_snpHitReleaseMeta_accessed,
+  input          io_in_1_bits_task_snpHitReleaseMeta_tagErr,
+  input          io_in_1_bits_task_snpHitReleaseMeta_dataErr,
+  input  [10:0]  io_in_1_bits_task_tgtID,
+  input  [10:0]  io_in_1_bits_task_srcID,
+  input  [11:0]  io_in_1_bits_task_txnID,
+  input  [10:0]  io_in_1_bits_task_homeNID,
+  input  [11:0]  io_in_1_bits_task_dbID,
+  input  [10:0]  io_in_1_bits_task_fwdNID,
+  input  [11:0]  io_in_1_bits_task_fwdTxnID,
+  input  [6:0]   io_in_1_bits_task_chiOpcode,
+  input  [2:0]   io_in_1_bits_task_resp,
+  input  [2:0]   io_in_1_bits_task_fwdState,
+  input  [3:0]   io_in_1_bits_task_pCrdType,
+  input          io_in_1_bits_task_retToSrc,
+  input          io_in_1_bits_task_likelyshared,
+  input          io_in_1_bits_task_expCompAck,
+  input          io_in_1_bits_task_allowRetry,
+  input          io_in_1_bits_task_memAttr_allocate,
+  input          io_in_1_bits_task_memAttr_cacheable,
+  input          io_in_1_bits_task_memAttr_device,
+  input          io_in_1_bits_task_memAttr_ewa,
+  input          io_in_1_bits_task_traceTag,
+  input  [511:0] io_in_1_bits_data_data,
+  output         io_in_2_ready,
+  input          io_in_2_valid,
+  input  [2:0]   io_in_2_bits_task_channel,
+  input  [2:0]   io_in_2_bits_task_txChannel,
+  input  [7:0]   io_in_2_bits_task_set,
+  input  [33:0]  io_in_2_bits_task_tag,
+  input  [5:0]   io_in_2_bits_task_off,
+  input          io_in_2_bits_task_alias,
+  input  [43:0]  io_in_2_bits_task_vaddr,
+  input          io_in_2_bits_task_isKeyword,
+  input  [3:0]   io_in_2_bits_task_opcode,
+  input  [2:0]   io_in_2_bits_task_param,
+  input  [2:0]   io_in_2_bits_task_size,
+  input  [6:0]   io_in_2_bits_task_sourceId,
+  input  [1:0]   io_in_2_bits_task_bufIdx,
+  input          io_in_2_bits_task_needProbeAckData,
+  input          io_in_2_bits_task_denied,
+  input          io_in_2_bits_task_corrupt,
+  input          io_in_2_bits_task_mshrTask,
+  input  [7:0]   io_in_2_bits_task_mshrId,
+  input          io_in_2_bits_task_aliasTask,
+  input          io_in_2_bits_task_useProbeData,
+  input          io_in_2_bits_task_mshrRetry,
+  input          io_in_2_bits_task_readProbeDataDown,
+  input          io_in_2_bits_task_fromL2pft,
+  input          io_in_2_bits_task_needHint,
+  input          io_in_2_bits_task_dirty,
+  input  [2:0]   io_in_2_bits_task_way,
+  input          io_in_2_bits_task_meta_dirty,
+  input  [1:0]   io_in_2_bits_task_meta_state,
+  input          io_in_2_bits_task_meta_clients,
+  input          io_in_2_bits_task_meta_alias,
+  input          io_in_2_bits_task_meta_prefetch,
+  input  [3:0]   io_in_2_bits_task_meta_prefetchSrc,
+  input          io_in_2_bits_task_meta_accessed,
+  input          io_in_2_bits_task_meta_tagErr,
+  input          io_in_2_bits_task_meta_dataErr,
+  input          io_in_2_bits_task_metaWen,
+  input          io_in_2_bits_task_tagWen,
+  input          io_in_2_bits_task_dsWen,
+  input  [7:0]   io_in_2_bits_task_wayMask,
+  input          io_in_2_bits_task_replTask,
+  input          io_in_2_bits_task_cmoTask,
+  input          io_in_2_bits_task_cmoAll,
+  input  [4:0]   io_in_2_bits_task_reqSource,
+  input          io_in_2_bits_task_mergeA,
+  input  [5:0]   io_in_2_bits_task_aMergeTask_off,
+  input          io_in_2_bits_task_aMergeTask_alias,
+  input  [43:0]  io_in_2_bits_task_aMergeTask_vaddr,
+  input          io_in_2_bits_task_aMergeTask_isKeyword,
+  input  [2:0]   io_in_2_bits_task_aMergeTask_opcode,
+  input  [2:0]   io_in_2_bits_task_aMergeTask_param,
+  input  [6:0]   io_in_2_bits_task_aMergeTask_sourceId,
+  input          io_in_2_bits_task_aMergeTask_meta_dirty,
+  input  [1:0]   io_in_2_bits_task_aMergeTask_meta_state,
+  input          io_in_2_bits_task_aMergeTask_meta_clients,
+  input          io_in_2_bits_task_aMergeTask_meta_alias,
+  input          io_in_2_bits_task_aMergeTask_meta_prefetch,
+  input  [3:0]   io_in_2_bits_task_aMergeTask_meta_prefetchSrc,
+  input          io_in_2_bits_task_aMergeTask_meta_accessed,
+  input          io_in_2_bits_task_aMergeTask_meta_tagErr,
+  input          io_in_2_bits_task_aMergeTask_meta_dataErr,
+  input          io_in_2_bits_task_snpHitRelease,
+  input          io_in_2_bits_task_snpHitReleaseToInval,
+  input          io_in_2_bits_task_snpHitReleaseToClean,
+  input          io_in_2_bits_task_snpHitReleaseWithData,
+  input  [7:0]   io_in_2_bits_task_snpHitReleaseIdx,
+  input          io_in_2_bits_task_snpHitReleaseMeta_dirty,
+  input  [1:0]   io_in_2_bits_task_snpHitReleaseMeta_state,
+  input          io_in_2_bits_task_snpHitReleaseMeta_clients,
+  input          io_in_2_bits_task_snpHitReleaseMeta_alias,
+  input          io_in_2_bits_task_snpHitReleaseMeta_prefetch,
+  input  [3:0]   io_in_2_bits_task_snpHitReleaseMeta_prefetchSrc,
+  input          io_in_2_bits_task_snpHitReleaseMeta_accessed,
+  input          io_in_2_bits_task_snpHitReleaseMeta_tagErr,
+  input          io_in_2_bits_task_snpHitReleaseMeta_dataErr,
+  input  [10:0]  io_in_2_bits_task_tgtID,
+  input  [10:0]  io_in_2_bits_task_srcID,
+  input  [11:0]  io_in_2_bits_task_txnID,
+  input  [10:0]  io_in_2_bits_task_homeNID,
+  input  [11:0]  io_in_2_bits_task_dbID,
+  input  [10:0]  io_in_2_bits_task_fwdNID,
+  input  [11:0]  io_in_2_bits_task_fwdTxnID,
+  input  [6:0]   io_in_2_bits_task_chiOpcode,
+  input  [2:0]   io_in_2_bits_task_resp,
+  input  [2:0]   io_in_2_bits_task_fwdState,
+  input  [3:0]   io_in_2_bits_task_pCrdType,
+  input          io_in_2_bits_task_retToSrc,
+  input          io_in_2_bits_task_likelyshared,
+  input          io_in_2_bits_task_expCompAck,
+  input          io_in_2_bits_task_allowRetry,
+  input          io_in_2_bits_task_memAttr_allocate,
+  input          io_in_2_bits_task_memAttr_cacheable,
+  input          io_in_2_bits_task_memAttr_device,
+  input          io_in_2_bits_task_memAttr_ewa,
+  input          io_in_2_bits_task_traceTag,
+  input  [511:0] io_in_2_bits_data_data,
+  input          io_out_ready,
+  output         io_out_valid,
+  output [2:0]   io_out_bits_task_channel,
+  output [2:0]   io_out_bits_task_txChannel,
+  output [7:0]   io_out_bits_task_set,
+  output [33:0]  io_out_bits_task_tag,
+  output [5:0]   io_out_bits_task_off,
+  output         io_out_bits_task_alias,
+  output [43:0]  io_out_bits_task_vaddr,
+  output         io_out_bits_task_isKeyword,
+  output [3:0]   io_out_bits_task_opcode,
+  output [2:0]   io_out_bits_task_param,
+  output [2:0]   io_out_bits_task_size,
+  output [6:0]   io_out_bits_task_sourceId,
+  output [1:0]   io_out_bits_task_bufIdx,
+  output         io_out_bits_task_needProbeAckData,
+  output         io_out_bits_task_denied,
+  output         io_out_bits_task_corrupt,
+  output         io_out_bits_task_mshrTask,
+  output [7:0]   io_out_bits_task_mshrId,
+  output         io_out_bits_task_aliasTask,
+  output         io_out_bits_task_useProbeData,
+  output         io_out_bits_task_mshrRetry,
+  output         io_out_bits_task_readProbeDataDown,
+  output         io_out_bits_task_fromL2pft,
+  output         io_out_bits_task_needHint,
+  output         io_out_bits_task_dirty,
+  output [2:0]   io_out_bits_task_way,
+  output         io_out_bits_task_meta_dirty,
+  output [1:0]   io_out_bits_task_meta_state,
+  output         io_out_bits_task_meta_clients,
+  output         io_out_bits_task_meta_alias,
+  output         io_out_bits_task_meta_prefetch,
+  output [3:0]   io_out_bits_task_meta_prefetchSrc,
+  output         io_out_bits_task_meta_accessed,
+  output         io_out_bits_task_meta_tagErr,
+  output         io_out_bits_task_meta_dataErr,
+  output         io_out_bits_task_metaWen,
+  output         io_out_bits_task_tagWen,
+  output         io_out_bits_task_dsWen,
+  output [7:0]   io_out_bits_task_wayMask,
+  output         io_out_bits_task_replTask,
+  output         io_out_bits_task_cmoTask,
+  output         io_out_bits_task_cmoAll,
+  output [4:0]   io_out_bits_task_reqSource,
+  output         io_out_bits_task_mergeA,
+  output [5:0]   io_out_bits_task_aMergeTask_off,
+  output         io_out_bits_task_aMergeTask_alias,
+  output [43:0]  io_out_bits_task_aMergeTask_vaddr,
+  output         io_out_bits_task_aMergeTask_isKeyword,
+  output [2:0]   io_out_bits_task_aMergeTask_opcode,
+  output [2:0]   io_out_bits_task_aMergeTask_param,
+  output [6:0]   io_out_bits_task_aMergeTask_sourceId,
+  output         io_out_bits_task_aMergeTask_meta_dirty,
+  output [1:0]   io_out_bits_task_aMergeTask_meta_state,
+  output         io_out_bits_task_aMergeTask_meta_clients,
+  output         io_out_bits_task_aMergeTask_meta_alias,
+  output         io_out_bits_task_aMergeTask_meta_prefetch,
+  output [3:0]   io_out_bits_task_aMergeTask_meta_prefetchSrc,
+  output         io_out_bits_task_aMergeTask_meta_accessed,
+  output         io_out_bits_task_aMergeTask_meta_tagErr,
+  output         io_out_bits_task_aMergeTask_meta_dataErr,
+  output         io_out_bits_task_snpHitRelease,
+  output         io_out_bits_task_snpHitReleaseToInval,
+  output         io_out_bits_task_snpHitReleaseToClean,
+  output         io_out_bits_task_snpHitReleaseWithData,
+  output [7:0]   io_out_bits_task_snpHitReleaseIdx,
+  output         io_out_bits_task_snpHitReleaseMeta_dirty,
+  output [1:0]   io_out_bits_task_snpHitReleaseMeta_state,
+  output         io_out_bits_task_snpHitReleaseMeta_clients,
+  output         io_out_bits_task_snpHitReleaseMeta_alias,
+  output         io_out_bits_task_snpHitReleaseMeta_prefetch,
+  output [3:0]   io_out_bits_task_snpHitReleaseMeta_prefetchSrc,
+  output         io_out_bits_task_snpHitReleaseMeta_accessed,
+  output         io_out_bits_task_snpHitReleaseMeta_tagErr,
+  output         io_out_bits_task_snpHitReleaseMeta_dataErr,
+  output [10:0]  io_out_bits_task_tgtID,
+  output [10:0]  io_out_bits_task_srcID,
+  output [11:0]  io_out_bits_task_txnID,
+  output [10:0]  io_out_bits_task_homeNID,
+  output [11:0]  io_out_bits_task_dbID,
+  output [10:0]  io_out_bits_task_fwdNID,
+  output [11:0]  io_out_bits_task_fwdTxnID,
+  output [6:0]   io_out_bits_task_chiOpcode,
+  output [2:0]   io_out_bits_task_resp,
+  output [2:0]   io_out_bits_task_fwdState,
+  output [3:0]   io_out_bits_task_pCrdType,
+  output         io_out_bits_task_retToSrc,
+  output         io_out_bits_task_likelyshared,
+  output         io_out_bits_task_expCompAck,
+  output         io_out_bits_task_allowRetry,
+  output         io_out_bits_task_memAttr_allocate,
+  output         io_out_bits_task_memAttr_cacheable,
+  output         io_out_bits_task_memAttr_device,
+  output         io_out_bits_task_memAttr_ewa,
+  output         io_out_bits_task_traceTag,
+  output [511:0] io_out_bits_data_data
+);
+
+  wire _io_out_valid_T = io_in_0_valid | io_in_1_valid;
+  assign io_in_1_ready = ~io_in_0_valid & io_out_ready;
+  assign io_in_2_ready = ~_io_out_valid_T & io_out_ready;
+  assign io_out_valid = _io_out_valid_T | io_in_2_valid;
+  assign io_out_bits_task_channel =
+    io_in_0_valid
+      ? io_in_0_bits_task_channel
+      : io_in_1_valid ? io_in_1_bits_task_channel : io_in_2_bits_task_channel;
+  assign io_out_bits_task_txChannel =
+    io_in_0_valid
+      ? io_in_0_bits_task_txChannel
+      : io_in_1_valid ? io_in_1_bits_task_txChannel : io_in_2_bits_task_txChannel;
+  assign io_out_bits_task_set =
+    io_in_0_valid
+      ? io_in_0_bits_task_set
+      : io_in_1_valid ? io_in_1_bits_task_set : io_in_2_bits_task_set;
+  assign io_out_bits_task_tag =
+    io_in_0_valid
+      ? io_in_0_bits_task_tag
+      : io_in_1_valid ? io_in_1_bits_task_tag : io_in_2_bits_task_tag;
+  assign io_out_bits_task_off =
+    io_in_0_valid
+      ? io_in_0_bits_task_off
+      : io_in_1_valid ? io_in_1_bits_task_off : io_in_2_bits_task_off;
+  assign io_out_bits_task_alias =
+    io_in_0_valid
+      ? io_in_0_bits_task_alias
+      : io_in_1_valid ? io_in_1_bits_task_alias : io_in_2_bits_task_alias;
+  assign io_out_bits_task_vaddr =
+    io_in_0_valid
+      ? io_in_0_bits_task_vaddr
+      : io_in_1_valid ? io_in_1_bits_task_vaddr : io_in_2_bits_task_vaddr;
+  assign io_out_bits_task_isKeyword =
+    io_in_0_valid
+      ? io_in_0_bits_task_isKeyword
+      : io_in_1_valid ? io_in_1_bits_task_isKeyword : io_in_2_bits_task_isKeyword;
+  assign io_out_bits_task_opcode =
+    io_in_0_valid
+      ? io_in_0_bits_task_opcode
+      : io_in_1_valid ? io_in_1_bits_task_opcode : io_in_2_bits_task_opcode;
+  assign io_out_bits_task_param =
+    io_in_0_valid
+      ? io_in_0_bits_task_param
+      : io_in_1_valid ? io_in_1_bits_task_param : io_in_2_bits_task_param;
+  assign io_out_bits_task_size =
+    io_in_0_valid
+      ? io_in_0_bits_task_size
+      : io_in_1_valid ? io_in_1_bits_task_size : io_in_2_bits_task_size;
+  assign io_out_bits_task_sourceId =
+    io_in_0_valid
+      ? io_in_0_bits_task_sourceId
+      : io_in_1_valid ? io_in_1_bits_task_sourceId : io_in_2_bits_task_sourceId;
+  assign io_out_bits_task_bufIdx =
+    io_in_0_valid
+      ? io_in_0_bits_task_bufIdx
+      : io_in_1_valid ? io_in_1_bits_task_bufIdx : io_in_2_bits_task_bufIdx;
+  assign io_out_bits_task_needProbeAckData =
+    io_in_0_valid
+      ? io_in_0_bits_task_needProbeAckData
+      : io_in_1_valid
+          ? io_in_1_bits_task_needProbeAckData
+          : io_in_2_bits_task_needProbeAckData;
+  assign io_out_bits_task_denied =
+    io_in_0_valid
+      ? io_in_0_bits_task_denied
+      : io_in_1_valid ? io_in_1_bits_task_denied : io_in_2_bits_task_denied;
+  assign io_out_bits_task_corrupt =
+    io_in_0_valid
+      ? io_in_0_bits_task_corrupt
+      : io_in_1_valid ? io_in_1_bits_task_corrupt : io_in_2_bits_task_corrupt;
+  assign io_out_bits_task_mshrTask =
+    io_in_0_valid
+      ? io_in_0_bits_task_mshrTask
+      : io_in_1_valid ? io_in_1_bits_task_mshrTask : io_in_2_bits_task_mshrTask;
+  assign io_out_bits_task_mshrId =
+    io_in_0_valid
+      ? io_in_0_bits_task_mshrId
+      : io_in_1_valid ? io_in_1_bits_task_mshrId : io_in_2_bits_task_mshrId;
+  assign io_out_bits_task_aliasTask =
+    io_in_0_valid
+      ? io_in_0_bits_task_aliasTask
+      : io_in_1_valid ? io_in_1_bits_task_aliasTask : io_in_2_bits_task_aliasTask;
+  assign io_out_bits_task_useProbeData =
+    io_in_0_valid
+      ? io_in_0_bits_task_useProbeData
+      : io_in_1_valid ? io_in_1_bits_task_useProbeData : io_in_2_bits_task_useProbeData;
+  assign io_out_bits_task_mshrRetry =
+    io_in_0_valid
+      ? io_in_0_bits_task_mshrRetry
+      : io_in_1_valid ? io_in_1_bits_task_mshrRetry : io_in_2_bits_task_mshrRetry;
+  assign io_out_bits_task_readProbeDataDown =
+    io_in_0_valid
+      ? io_in_0_bits_task_readProbeDataDown
+      : io_in_1_valid
+          ? io_in_1_bits_task_readProbeDataDown
+          : io_in_2_bits_task_readProbeDataDown;
+  assign io_out_bits_task_fromL2pft =
+    io_in_0_valid
+      ? io_in_0_bits_task_fromL2pft
+      : io_in_1_valid ? io_in_1_bits_task_fromL2pft : io_in_2_bits_task_fromL2pft;
+  assign io_out_bits_task_needHint =
+    io_in_0_valid
+      ? io_in_0_bits_task_needHint
+      : io_in_1_valid ? io_in_1_bits_task_needHint : io_in_2_bits_task_needHint;
+  assign io_out_bits_task_dirty =
+    io_in_0_valid
+      ? io_in_0_bits_task_dirty
+      : io_in_1_valid ? io_in_1_bits_task_dirty : io_in_2_bits_task_dirty;
+  assign io_out_bits_task_way =
+    io_in_0_valid
+      ? io_in_0_bits_task_way
+      : io_in_1_valid ? io_in_1_bits_task_way : io_in_2_bits_task_way;
+  assign io_out_bits_task_meta_dirty =
+    io_in_0_valid
+      ? io_in_0_bits_task_meta_dirty
+      : io_in_1_valid ? io_in_1_bits_task_meta_dirty : io_in_2_bits_task_meta_dirty;
+  assign io_out_bits_task_meta_state =
+    io_in_0_valid
+      ? io_in_0_bits_task_meta_state
+      : io_in_1_valid ? io_in_1_bits_task_meta_state : io_in_2_bits_task_meta_state;
+  assign io_out_bits_task_meta_clients =
+    io_in_0_valid
+      ? io_in_0_bits_task_meta_clients
+      : io_in_1_valid ? io_in_1_bits_task_meta_clients : io_in_2_bits_task_meta_clients;
+  assign io_out_bits_task_meta_alias =
+    io_in_0_valid
+      ? io_in_0_bits_task_meta_alias
+      : io_in_1_valid ? io_in_1_bits_task_meta_alias : io_in_2_bits_task_meta_alias;
+  assign io_out_bits_task_meta_prefetch =
+    io_in_0_valid
+      ? io_in_0_bits_task_meta_prefetch
+      : io_in_1_valid ? io_in_1_bits_task_meta_prefetch : io_in_2_bits_task_meta_prefetch;
+  assign io_out_bits_task_meta_prefetchSrc =
+    io_in_0_valid
+      ? io_in_0_bits_task_meta_prefetchSrc
+      : io_in_1_valid
+          ? io_in_1_bits_task_meta_prefetchSrc
+          : io_in_2_bits_task_meta_prefetchSrc;
+  assign io_out_bits_task_meta_accessed =
+    io_in_0_valid
+      ? io_in_0_bits_task_meta_accessed
+      : io_in_1_valid ? io_in_1_bits_task_meta_accessed : io_in_2_bits_task_meta_accessed;
+  assign io_out_bits_task_meta_tagErr =
+    io_in_0_valid
+      ? io_in_0_bits_task_meta_tagErr
+      : io_in_1_valid ? io_in_1_bits_task_meta_tagErr : io_in_2_bits_task_meta_tagErr;
+  assign io_out_bits_task_meta_dataErr =
+    io_in_0_valid
+      ? io_in_0_bits_task_meta_dataErr
+      : io_in_1_valid ? io_in_1_bits_task_meta_dataErr : io_in_2_bits_task_meta_dataErr;
+  assign io_out_bits_task_metaWen =
+    io_in_0_valid
+      ? io_in_0_bits_task_metaWen
+      : io_in_1_valid ? io_in_1_bits_task_metaWen : io_in_2_bits_task_metaWen;
+  assign io_out_bits_task_tagWen =
+    io_in_0_valid
+      ? io_in_0_bits_task_tagWen
+      : io_in_1_valid ? io_in_1_bits_task_tagWen : io_in_2_bits_task_tagWen;
+  assign io_out_bits_task_dsWen =
+    io_in_0_valid
+      ? io_in_0_bits_task_dsWen
+      : io_in_1_valid ? io_in_1_bits_task_dsWen : io_in_2_bits_task_dsWen;
+  assign io_out_bits_task_wayMask =
+    io_in_0_valid
+      ? io_in_0_bits_task_wayMask
+      : io_in_1_valid ? io_in_1_bits_task_wayMask : io_in_2_bits_task_wayMask;
+  assign io_out_bits_task_replTask =
+    io_in_0_valid
+      ? io_in_0_bits_task_replTask
+      : io_in_1_valid ? io_in_1_bits_task_replTask : io_in_2_bits_task_replTask;
+  assign io_out_bits_task_cmoTask =
+    io_in_0_valid
+      ? io_in_0_bits_task_cmoTask
+      : io_in_1_valid ? io_in_1_bits_task_cmoTask : io_in_2_bits_task_cmoTask;
+  assign io_out_bits_task_cmoAll =
+    io_in_0_valid
+      ? io_in_0_bits_task_cmoAll
+      : io_in_1_valid ? io_in_1_bits_task_cmoAll : io_in_2_bits_task_cmoAll;
+  assign io_out_bits_task_reqSource =
+    io_in_0_valid
+      ? io_in_0_bits_task_reqSource
+      : io_in_1_valid ? io_in_1_bits_task_reqSource : io_in_2_bits_task_reqSource;
+  assign io_out_bits_task_mergeA =
+    io_in_0_valid
+      ? io_in_0_bits_task_mergeA
+      : io_in_1_valid ? io_in_1_bits_task_mergeA : io_in_2_bits_task_mergeA;
+  assign io_out_bits_task_aMergeTask_off =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_off
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_off
+          : io_in_2_bits_task_aMergeTask_off;
+  assign io_out_bits_task_aMergeTask_alias =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_alias
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_alias
+          : io_in_2_bits_task_aMergeTask_alias;
+  assign io_out_bits_task_aMergeTask_vaddr =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_vaddr
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_vaddr
+          : io_in_2_bits_task_aMergeTask_vaddr;
+  assign io_out_bits_task_aMergeTask_isKeyword =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_isKeyword
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_isKeyword
+          : io_in_2_bits_task_aMergeTask_isKeyword;
+  assign io_out_bits_task_aMergeTask_opcode =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_opcode
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_opcode
+          : io_in_2_bits_task_aMergeTask_opcode;
+  assign io_out_bits_task_aMergeTask_param =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_param
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_param
+          : io_in_2_bits_task_aMergeTask_param;
+  assign io_out_bits_task_aMergeTask_sourceId =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_sourceId
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_sourceId
+          : io_in_2_bits_task_aMergeTask_sourceId;
+  assign io_out_bits_task_aMergeTask_meta_dirty =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_meta_dirty
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_meta_dirty
+          : io_in_2_bits_task_aMergeTask_meta_dirty;
+  assign io_out_bits_task_aMergeTask_meta_state =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_meta_state
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_meta_state
+          : io_in_2_bits_task_aMergeTask_meta_state;
+  assign io_out_bits_task_aMergeTask_meta_clients =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_meta_clients
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_meta_clients
+          : io_in_2_bits_task_aMergeTask_meta_clients;
+  assign io_out_bits_task_aMergeTask_meta_alias =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_meta_alias
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_meta_alias
+          : io_in_2_bits_task_aMergeTask_meta_alias;
+  assign io_out_bits_task_aMergeTask_meta_prefetch =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_meta_prefetch
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_meta_prefetch
+          : io_in_2_bits_task_aMergeTask_meta_prefetch;
+  assign io_out_bits_task_aMergeTask_meta_prefetchSrc =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_meta_prefetchSrc
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_meta_prefetchSrc
+          : io_in_2_bits_task_aMergeTask_meta_prefetchSrc;
+  assign io_out_bits_task_aMergeTask_meta_accessed =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_meta_accessed
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_meta_accessed
+          : io_in_2_bits_task_aMergeTask_meta_accessed;
+  assign io_out_bits_task_aMergeTask_meta_tagErr =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_meta_tagErr
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_meta_tagErr
+          : io_in_2_bits_task_aMergeTask_meta_tagErr;
+  assign io_out_bits_task_aMergeTask_meta_dataErr =
+    io_in_0_valid
+      ? io_in_0_bits_task_aMergeTask_meta_dataErr
+      : io_in_1_valid
+          ? io_in_1_bits_task_aMergeTask_meta_dataErr
+          : io_in_2_bits_task_aMergeTask_meta_dataErr;
+  assign io_out_bits_task_snpHitRelease =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitRelease
+      : io_in_1_valid ? io_in_1_bits_task_snpHitRelease : io_in_2_bits_task_snpHitRelease;
+  assign io_out_bits_task_snpHitReleaseToInval =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseToInval
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseToInval
+          : io_in_2_bits_task_snpHitReleaseToInval;
+  assign io_out_bits_task_snpHitReleaseToClean =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseToClean
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseToClean
+          : io_in_2_bits_task_snpHitReleaseToClean;
+  assign io_out_bits_task_snpHitReleaseWithData =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseWithData
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseWithData
+          : io_in_2_bits_task_snpHitReleaseWithData;
+  assign io_out_bits_task_snpHitReleaseIdx =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseIdx
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseIdx
+          : io_in_2_bits_task_snpHitReleaseIdx;
+  assign io_out_bits_task_snpHitReleaseMeta_dirty =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseMeta_dirty
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseMeta_dirty
+          : io_in_2_bits_task_snpHitReleaseMeta_dirty;
+  assign io_out_bits_task_snpHitReleaseMeta_state =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseMeta_state
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseMeta_state
+          : io_in_2_bits_task_snpHitReleaseMeta_state;
+  assign io_out_bits_task_snpHitReleaseMeta_clients =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseMeta_clients
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseMeta_clients
+          : io_in_2_bits_task_snpHitReleaseMeta_clients;
+  assign io_out_bits_task_snpHitReleaseMeta_alias =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseMeta_alias
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseMeta_alias
+          : io_in_2_bits_task_snpHitReleaseMeta_alias;
+  assign io_out_bits_task_snpHitReleaseMeta_prefetch =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseMeta_prefetch
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseMeta_prefetch
+          : io_in_2_bits_task_snpHitReleaseMeta_prefetch;
+  assign io_out_bits_task_snpHitReleaseMeta_prefetchSrc =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseMeta_prefetchSrc
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseMeta_prefetchSrc
+          : io_in_2_bits_task_snpHitReleaseMeta_prefetchSrc;
+  assign io_out_bits_task_snpHitReleaseMeta_accessed =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseMeta_accessed
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseMeta_accessed
+          : io_in_2_bits_task_snpHitReleaseMeta_accessed;
+  assign io_out_bits_task_snpHitReleaseMeta_tagErr =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseMeta_tagErr
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseMeta_tagErr
+          : io_in_2_bits_task_snpHitReleaseMeta_tagErr;
+  assign io_out_bits_task_snpHitReleaseMeta_dataErr =
+    io_in_0_valid
+      ? io_in_0_bits_task_snpHitReleaseMeta_dataErr
+      : io_in_1_valid
+          ? io_in_1_bits_task_snpHitReleaseMeta_dataErr
+          : io_in_2_bits_task_snpHitReleaseMeta_dataErr;
+  assign io_out_bits_task_tgtID =
+    io_in_0_valid
+      ? io_in_0_bits_task_tgtID
+      : io_in_1_valid ? io_in_1_bits_task_tgtID : io_in_2_bits_task_tgtID;
+  assign io_out_bits_task_srcID =
+    io_in_0_valid
+      ? io_in_0_bits_task_srcID
+      : io_in_1_valid ? io_in_1_bits_task_srcID : io_in_2_bits_task_srcID;
+  assign io_out_bits_task_txnID =
+    io_in_0_valid
+      ? io_in_0_bits_task_txnID
+      : io_in_1_valid ? io_in_1_bits_task_txnID : io_in_2_bits_task_txnID;
+  assign io_out_bits_task_homeNID =
+    io_in_0_valid
+      ? io_in_0_bits_task_homeNID
+      : io_in_1_valid ? io_in_1_bits_task_homeNID : io_in_2_bits_task_homeNID;
+  assign io_out_bits_task_dbID =
+    io_in_0_valid
+      ? io_in_0_bits_task_dbID
+      : io_in_1_valid ? io_in_1_bits_task_dbID : io_in_2_bits_task_dbID;
+  assign io_out_bits_task_fwdNID =
+    io_in_0_valid
+      ? io_in_0_bits_task_fwdNID
+      : io_in_1_valid ? io_in_1_bits_task_fwdNID : io_in_2_bits_task_fwdNID;
+  assign io_out_bits_task_fwdTxnID =
+    io_in_0_valid
+      ? io_in_0_bits_task_fwdTxnID
+      : io_in_1_valid ? io_in_1_bits_task_fwdTxnID : io_in_2_bits_task_fwdTxnID;
+  assign io_out_bits_task_chiOpcode =
+    io_in_0_valid
+      ? io_in_0_bits_task_chiOpcode
+      : io_in_1_valid ? io_in_1_bits_task_chiOpcode : io_in_2_bits_task_chiOpcode;
+  assign io_out_bits_task_resp =
+    io_in_0_valid
+      ? io_in_0_bits_task_resp
+      : io_in_1_valid ? io_in_1_bits_task_resp : io_in_2_bits_task_resp;
+  assign io_out_bits_task_fwdState =
+    io_in_0_valid
+      ? io_in_0_bits_task_fwdState
+      : io_in_1_valid ? io_in_1_bits_task_fwdState : io_in_2_bits_task_fwdState;
+  assign io_out_bits_task_pCrdType =
+    io_in_0_valid
+      ? io_in_0_bits_task_pCrdType
+      : io_in_1_valid ? io_in_1_bits_task_pCrdType : io_in_2_bits_task_pCrdType;
+  assign io_out_bits_task_retToSrc =
+    io_in_0_valid
+      ? io_in_0_bits_task_retToSrc
+      : io_in_1_valid ? io_in_1_bits_task_retToSrc : io_in_2_bits_task_retToSrc;
+  assign io_out_bits_task_likelyshared =
+    io_in_0_valid
+      ? io_in_0_bits_task_likelyshared
+      : io_in_1_valid ? io_in_1_bits_task_likelyshared : io_in_2_bits_task_likelyshared;
+  assign io_out_bits_task_expCompAck =
+    io_in_0_valid
+      ? io_in_0_bits_task_expCompAck
+      : io_in_1_valid ? io_in_1_bits_task_expCompAck : io_in_2_bits_task_expCompAck;
+  assign io_out_bits_task_allowRetry =
+    io_in_0_valid
+      ? io_in_0_bits_task_allowRetry
+      : io_in_1_valid ? io_in_1_bits_task_allowRetry : io_in_2_bits_task_allowRetry;
+  assign io_out_bits_task_memAttr_allocate =
+    io_in_0_valid
+      ? io_in_0_bits_task_memAttr_allocate
+      : io_in_1_valid
+          ? io_in_1_bits_task_memAttr_allocate
+          : io_in_2_bits_task_memAttr_allocate;
+  assign io_out_bits_task_memAttr_cacheable =
+    io_in_0_valid
+      ? io_in_0_bits_task_memAttr_cacheable
+      : io_in_1_valid
+          ? io_in_1_bits_task_memAttr_cacheable
+          : io_in_2_bits_task_memAttr_cacheable;
+  assign io_out_bits_task_memAttr_device =
+    io_in_0_valid
+      ? io_in_0_bits_task_memAttr_device
+      : io_in_1_valid
+          ? io_in_1_bits_task_memAttr_device
+          : io_in_2_bits_task_memAttr_device;
+  assign io_out_bits_task_memAttr_ewa =
+    io_in_0_valid
+      ? io_in_0_bits_task_memAttr_ewa
+      : io_in_1_valid ? io_in_1_bits_task_memAttr_ewa : io_in_2_bits_task_memAttr_ewa;
+  assign io_out_bits_task_traceTag =
+    io_in_0_valid
+      ? io_in_0_bits_task_traceTag
+      : io_in_1_valid ? io_in_1_bits_task_traceTag : io_in_2_bits_task_traceTag;
+  assign io_out_bits_data_data =
+    io_in_0_valid
+      ? io_in_0_bits_data_data
+      : io_in_1_valid ? io_in_1_bits_data_data : io_in_2_bits_data_data;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ClockGate.sv b/flow/designs/src/xiangshan_coupledl2/deps/ClockGate.sv
new file mode 100644
index 0000000000..bfd378b7eb
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ClockGate.sv
@@ -0,0 +1,14 @@
+// Generated by CIRCT firtool-1.135.0
+
+module ClockGate (
+  input  wire TE,
+  input  wire E,
+  input  wire CK,
+  output wire Q
+);
+  reg EN;
+  always_latch begin
+    if(!CK) EN = TE | E;
+  end
+  assign Q = CK & EN;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ClockMux.sv b/flow/designs/src/xiangshan_coupledl2/deps/ClockMux.sv
new file mode 100644
index 0000000000..60d2ffbdc0
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ClockMux.sv
@@ -0,0 +1,10 @@
+// Generated by CIRCT firtool-1.135.0
+module ClockMux(
+  input  clk0,
+  input  clk1,
+  input  sel,
+  output clkout
+);
+
+  assign clkout = sel ? clk1 : clk0;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/CustomL1Hint.sv b/flow/designs/src/xiangshan_coupledl2/deps/CustomL1Hint.sv
new file mode 100644
index 0000000000..cf342516f9
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/CustomL1Hint.sv
@@ -0,0 +1,230 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module CustomL1Hint(
+  input        clock,
+  input        reset,
+  input        io_mshrHintQInfo_valid,
+  input  [2:0] io_mshrHintQInfo_bits_channel,
+  input        io_mshrHintQInfo_bits_isKeyword,
+  input  [3:0] io_mshrHintQInfo_bits_opcode,
+  input  [6:0] io_mshrHintQInfo_bits_sourceId,
+  input        io_mshrHintQInfo_bits_mergeA,
+  input        io_mshrHintQInfo_bits_aMergeTask_isKeyword,
+  input  [2:0] io_mshrHintQInfo_bits_aMergeTask_opcode,
+  input  [6:0] io_mshrHintQInfo_bits_aMergeTask_sourceId,
+  input        io_sinkCHintQInfo_valid,
+  input  [6:0] io_sinkCHintQInfo_bits_sourceId,
+  input        io_retry_s2,
+  input        io_s3_task_valid,
+  input  [2:0] io_s3_task_bits_channel,
+  input        io_s3_task_bits_isKeyword,
+  input  [3:0] io_s3_task_bits_opcode,
+  input  [6:0] io_s3_task_bits_sourceId,
+  input        io_s3_task_bits_mshrTask,
+  input        io_s3_need_mshr,
+  input        io_l1Hint_ready,
+  output       io_l1Hint_valid,
+  output [6:0] io_l1Hint_bits_sourceId,
+  output       io_l1Hint_bits_isKeyword,
+  output       io_l1Hint_bits_hasData
+);
+
+  wire       hintQueue_io_deq_ready;
+  wire       _Hint_arb_io_in_1_ready;
+  wire       _Hint_arb_io_in_2_ready;
+  wire       _Hint_arb_io_out_valid;
+  wire [6:0] _Hint_arb_io_out_bits_source;
+  wire       _Hint_arb_io_out_bits_isGrantData;
+  wire       _Hint_arb_io_out_bits_isKeyword;
+  wire       _Hint_arb_io_out_bits_hasData;
+  wire       _hint_s1Queue_io_out_valid;
+  wire [6:0] _hint_s1Queue_io_out_bits_source;
+  wire       _hint_s1Queue_io_out_bits_isGrantData;
+  wire       _hint_s1Queue_io_out_bits_isKeyword;
+  wire       _hint_s1Queue_io_out_bits_hasData;
+  wire       _hintQueue_io_enq_ready;
+  wire       _hintQueue_io_deq_valid;
+  wire       _hintQueue_io_deq_bits_hasData;
+  wire [4:0] _hintQueue_io_count;
+  wire       mshr_GrantData_s1 =
+    io_mshrHintQInfo_valid
+    & (io_mshrHintQInfo_bits_channel[0] & io_mshrHintQInfo_bits_opcode == 4'h5
+       | io_mshrHintQInfo_bits_channel[0] & io_mshrHintQInfo_bits_mergeA
+       & io_mshrHintQInfo_bits_aMergeTask_opcode == 3'h5);
+  wire       mshr_AccessAckData_s1 =
+    io_mshrHintQInfo_valid & io_mshrHintQInfo_bits_channel[0]
+    & io_mshrHintQInfo_bits_opcode == 4'h1;
+  wire [6:0] enqBits_s1_source =
+    (io_mshrHintQInfo_valid & io_mshrHintQInfo_bits_mergeA
+       ? io_mshrHintQInfo_bits_aMergeTask_sourceId
+       : 7'h0)
+    | (io_mshrHintQInfo_valid & ~io_mshrHintQInfo_bits_mergeA
+         ? io_mshrHintQInfo_bits_sourceId
+         : 7'h0) | (io_sinkCHintQInfo_valid ? io_sinkCHintQInfo_bits_sourceId : 7'h0);
+  wire       enqBits_s1_isKeyword =
+    io_mshrHintQInfo_bits_mergeA
+      ? io_mshrHintQInfo_bits_aMergeTask_isKeyword
+      : io_mshrHintQInfo_bits_isKeyword;
+  wire       enqBits_s1_hasData = mshr_GrantData_s1 | mshr_AccessAckData_s1;
+  wire       chn_GrantData_s3 =
+    io_s3_task_valid & ~io_s3_task_bits_mshrTask & ~io_s3_need_mshr
+    & io_s3_task_bits_channel[0] & io_s3_task_bits_opcode == 4'h5;
+  wire       chn_AccessAckData_s3 =
+    io_s3_task_valid & ~io_s3_task_bits_mshrTask & ~io_s3_need_mshr
+    & io_s3_task_bits_channel[0] & io_s3_task_bits_opcode == 4'h1;
+  wire       canFlow_s1 =
+    ~_hintQueue_io_deq_valid | _hintQueue_io_count == 5'h1 & hintQueue_io_deq_ready
+    & _hintQueue_io_deq_valid;
+  wire       valid_s1 =
+    mshr_GrantData_s1 | io_mshrHintQInfo_valid
+    & (io_mshrHintQInfo_bits_channel[0] & io_mshrHintQInfo_bits_opcode == 4'h4
+       | io_mshrHintQInfo_bits_channel[0] & io_mshrHintQInfo_bits_mergeA
+       & io_mshrHintQInfo_bits_aMergeTask_opcode == 3'h4) | mshr_AccessAckData_s1
+    | io_mshrHintQInfo_valid & io_mshrHintQInfo_bits_channel[0]
+    & io_mshrHintQInfo_bits_opcode == 4'h8 | io_sinkCHintQInfo_valid;
+  reg        hintQueue_io_deq_ready_REG;
+  assign hintQueue_io_deq_ready = io_l1Hint_ready & ~hintQueue_io_deq_ready_REG;
+  reg        io_l1Hint_valid_REG;
+  wire       io_l1Hint_valid_0 =
+    _hintQueue_io_deq_valid & ~(io_retry_s2 & ~_hint_s1Queue_io_out_valid)
+    & ~io_l1Hint_valid_REG;
+  wire       respWithDataFire =
+    io_l1Hint_ready & io_l1Hint_valid_0 & _hintQueue_io_deq_bits_hasData;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      hintQueue_io_deq_ready_REG <= 1'h0;
+      io_l1Hint_valid_REG <= 1'h0;
+    end
+    else begin
+      hintQueue_io_deq_ready_REG <= respWithDataFire;
+      io_l1Hint_valid_REG <= respWithDataFire;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        hintQueue_io_deq_ready_REG = _RANDOM[/*Zero width*/ 1'b0][0];
+        io_l1Hint_valid_REG = _RANDOM[/*Zero width*/ 1'b0][1];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        hintQueue_io_deq_ready_REG = 1'h0;
+        io_l1Hint_valid_REG = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  Queue16_HintQueueEntry hintQueue (
+    .clock                   (clock),
+    .reset                   (reset),
+    .io_enq_ready            (_hintQueue_io_enq_ready),
+    .io_enq_valid            (_Hint_arb_io_out_valid),
+    .io_enq_bits_source      (_Hint_arb_io_out_bits_source),
+    .io_enq_bits_isGrantData (_Hint_arb_io_out_bits_isGrantData),
+    .io_enq_bits_isKeyword   (_Hint_arb_io_out_bits_isKeyword),
+    .io_enq_bits_hasData     (_Hint_arb_io_out_bits_hasData),
+    .io_deq_ready            (hintQueue_io_deq_ready),
+    .io_deq_valid            (_hintQueue_io_deq_valid),
+    .io_deq_bits_source      (io_l1Hint_bits_sourceId),
+    .io_deq_bits_isKeyword   (io_l1Hint_bits_isKeyword),
+    .io_deq_bits_hasData     (_hintQueue_io_deq_bits_hasData),
+    .io_count                (_hintQueue_io_count)
+  );
+  Pipeline_6 hint_s1Queue (
+    .clock                   (clock),
+    .reset                   (reset),
+    .io_in_valid             (valid_s1 & (~canFlow_s1 | ~_Hint_arb_io_in_2_ready)),
+    .io_in_bits_source       (enqBits_s1_source),
+    .io_in_bits_isGrantData  (mshr_GrantData_s1),
+    .io_in_bits_isKeyword    (enqBits_s1_isKeyword),
+    .io_in_bits_hasData      (enqBits_s1_hasData),
+    .io_out_ready            (_Hint_arb_io_in_1_ready | io_retry_s2),
+    .io_out_valid            (_hint_s1Queue_io_out_valid),
+    .io_out_bits_source      (_hint_s1Queue_io_out_bits_source),
+    .io_out_bits_isGrantData (_hint_s1Queue_io_out_bits_isGrantData),
+    .io_out_bits_isKeyword   (_hint_s1Queue_io_out_bits_isKeyword),
+    .io_out_bits_hasData     (_hint_s1Queue_io_out_bits_hasData)
+  );
+  Arbiter3_HintQueueEntry Hint_arb (
+    .io_in_0_valid
+      (io_s3_task_valid & ~io_s3_task_bits_mshrTask & ~io_s3_need_mshr
+       & io_s3_task_bits_channel[0] & io_s3_task_bits_opcode == 4'h4 | chn_GrantData_s3
+       | chn_AccessAckData_s3),
+    .io_in_0_bits_source      (io_s3_task_bits_sourceId),
+    .io_in_0_bits_isGrantData (chn_GrantData_s3),
+    .io_in_0_bits_isKeyword   (io_s3_task_bits_isKeyword),
+    .io_in_0_bits_hasData     (chn_GrantData_s3 | chn_AccessAckData_s3),
+    .io_in_1_ready            (_Hint_arb_io_in_1_ready),
+    .io_in_1_valid            (_hint_s1Queue_io_out_valid & ~io_retry_s2),
+    .io_in_1_bits_source      (_hint_s1Queue_io_out_bits_source),
+    .io_in_1_bits_isGrantData (_hint_s1Queue_io_out_bits_isGrantData),
+    .io_in_1_bits_isKeyword   (_hint_s1Queue_io_out_bits_isKeyword),
+    .io_in_1_bits_hasData     (_hint_s1Queue_io_out_bits_hasData),
+    .io_in_2_ready            (_Hint_arb_io_in_2_ready),
+    .io_in_2_valid            (valid_s1 & canFlow_s1),
+    .io_in_2_bits_source      (enqBits_s1_source),
+    .io_in_2_bits_isGrantData (mshr_GrantData_s1),
+    .io_in_2_bits_isKeyword   (enqBits_s1_isKeyword),
+    .io_in_2_bits_hasData     (enqBits_s1_hasData),
+    .io_out_ready             (_hintQueue_io_enq_ready),
+    .io_out_valid             (_Hint_arb_io_out_valid),
+    .io_out_bits_source       (_Hint_arb_io_out_bits_source),
+    .io_out_bits_isGrantData  (_Hint_arb_io_out_bits_isGrantData),
+    .io_out_bits_isKeyword    (_Hint_arb_io_out_bits_isKeyword),
+    .io_out_bits_hasData      (_Hint_arb_io_out_bits_hasData)
+  );
+  assign io_l1Hint_valid = io_l1Hint_valid_0;
+  assign io_l1Hint_bits_hasData = _hintQueue_io_deq_bits_hasData;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/DataStorage.sv b/flow/designs/src/xiangshan_coupledl2/deps/DataStorage.sv
new file mode 100644
index 0000000000..6b590c67d2
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/DataStorage.sv
@@ -0,0 +1,511 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module DataStorage(
+  input          clock,
+  input          reset,
+  input          io_en,
+  output         io_error,
+  input          io_req_valid,
+  input  [2:0]   io_req_bits_way,
+  input  [7:0]   io_req_bits_set,
+  input          io_req_bits_wen,
+  output [511:0] io_rdata_data,
+  input  [511:0] io_wdata_data,
+  input  [3:0]   boreChildrenBd_bore_array,
+  input          boreChildrenBd_bore_all,
+  input          boreChildrenBd_bore_req,
+  output         boreChildrenBd_bore_ack,
+  input          boreChildrenBd_bore_writeen,
+  input          boreChildrenBd_bore_be,
+  input  [11:0]  boreChildrenBd_bore_addr,
+  input  [136:0] boreChildrenBd_bore_indata,
+  input          boreChildrenBd_bore_readen,
+  input  [11:0]  boreChildrenBd_bore_addr_rd,
+  output [136:0] boreChildrenBd_bore_outdata,
+  input          sigFromSrams_bore_ram_hold,
+  input          sigFromSrams_bore_ram_bypass,
+  input          sigFromSrams_bore_ram_bp_clken,
+  input          sigFromSrams_bore_ram_aux_clk,
+  input          sigFromSrams_bore_ram_aux_ckbp,
+  input          sigFromSrams_bore_ram_mcp_hold,
+  input          sigFromSrams_bore_cgen,
+  input          sigFromSrams_bore_1_ram_hold,
+  input          sigFromSrams_bore_1_ram_bypass,
+  input          sigFromSrams_bore_1_ram_bp_clken,
+  input          sigFromSrams_bore_1_ram_aux_clk,
+  input          sigFromSrams_bore_1_ram_aux_ckbp,
+  input          sigFromSrams_bore_1_ram_mcp_hold,
+  input          sigFromSrams_bore_1_cgen,
+  input          sigFromSrams_bore_2_ram_hold,
+  input          sigFromSrams_bore_2_ram_bypass,
+  input          sigFromSrams_bore_2_ram_bp_clken,
+  input          sigFromSrams_bore_2_ram_aux_clk,
+  input          sigFromSrams_bore_2_ram_aux_ckbp,
+  input          sigFromSrams_bore_2_ram_mcp_hold,
+  input          sigFromSrams_bore_2_cgen,
+  input          sigFromSrams_bore_3_ram_hold,
+  input          sigFromSrams_bore_3_ram_bypass,
+  input          sigFromSrams_bore_3_ram_bp_clken,
+  input          sigFromSrams_bore_3_ram_aux_clk,
+  input          sigFromSrams_bore_3_ram_aux_ckbp,
+  input          sigFromSrams_bore_3_ram_mcp_hold,
+  input          sigFromSrams_bore_3_cgen
+);
+
+  wire [136:0] bd_outdata;
+  wire         bd_ack;
+  wire [136:0] childBd_3_rdata;
+  wire [136:0] childBd_2_rdata;
+  wire [136:0] childBd_1_rdata;
+  wire [136:0] childBd_rdata;
+  wire [547:0] _array_io_r_resp_data_0_data;
+  wire [3:0]   bd_array = boreChildrenBd_bore_array;
+  wire         bd_all = boreChildrenBd_bore_all;
+  wire         bd_req = boreChildrenBd_bore_req;
+  wire         bd_writeen = boreChildrenBd_bore_writeen;
+  wire         bd_be = boreChildrenBd_bore_be;
+  wire [11:0]  bd_addr = boreChildrenBd_bore_addr;
+  wire [136:0] bd_indata = boreChildrenBd_bore_indata;
+  wire         bd_readen = boreChildrenBd_bore_readen;
+  wire [11:0]  bd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire [10:0]  arrayIdx = {io_req_bits_way, io_req_bits_set};
+  wire [127:0] _arrayWriteData_syndromeUInt_T =
+    {1'h0, io_wdata_data[126:0] & 127'h55AAAAAAAAAAAAAAAB55555556AAAD5B};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_3 =
+    {1'h0, io_wdata_data[126:0] & 127'h66CCCCCCCCCCCCCCCD9999999B33366D};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_6 =
+    {1'h0, io_wdata_data[126:1] & 126'h3C7878787878787878F0F0F0F1E1E3C7, 1'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_9 =
+    {io_wdata_data[127:4] & 124'h80FF00FF00FF00FF01FE01FE03FC07F, 4'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_12 =
+    {8'h0, io_wdata_data[119:11] & 109'h1FFFE0001FFFE0003FFFC0007FFF, 11'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_15 =
+    {8'h0, io_wdata_data[119:26] & 94'h3FFFFFFFC00000007FFFFFFF, 26'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_18 = {8'h0, io_wdata_data[119:57], 57'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_21 = {io_wdata_data[127:120], 120'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_24 =
+    {1'h0, io_wdata_data[254:128] & 127'h55AAAAAAAAAAAAAAAB55555556AAAD5B};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_27 =
+    {1'h0, io_wdata_data[254:128] & 127'h66CCCCCCCCCCCCCCCD9999999B33366D};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_30 =
+    {1'h0, io_wdata_data[254:129] & 126'h3C7878787878787878F0F0F0F1E1E3C7, 1'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_33 =
+    {io_wdata_data[255:132] & 124'h80FF00FF00FF00FF01FE01FE03FC07F, 4'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_36 =
+    {8'h0, io_wdata_data[247:139] & 109'h1FFFE0001FFFE0003FFFC0007FFF, 11'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_39 =
+    {8'h0, io_wdata_data[247:154] & 94'h3FFFFFFFC00000007FFFFFFF, 26'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_42 = {8'h0, io_wdata_data[247:185], 57'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_45 = {io_wdata_data[255:248], 120'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_48 =
+    {1'h0, io_wdata_data[382:256] & 127'h55AAAAAAAAAAAAAAAB55555556AAAD5B};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_51 =
+    {1'h0, io_wdata_data[382:256] & 127'h66CCCCCCCCCCCCCCCD9999999B33366D};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_54 =
+    {1'h0, io_wdata_data[382:257] & 126'h3C7878787878787878F0F0F0F1E1E3C7, 1'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_57 =
+    {io_wdata_data[383:260] & 124'h80FF00FF00FF00FF01FE01FE03FC07F, 4'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_60 =
+    {8'h0, io_wdata_data[375:267] & 109'h1FFFE0001FFFE0003FFFC0007FFF, 11'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_63 =
+    {8'h0, io_wdata_data[375:282] & 94'h3FFFFFFFC00000007FFFFFFF, 26'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_66 = {8'h0, io_wdata_data[375:313], 57'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_69 = {io_wdata_data[383:376], 120'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_72 =
+    {1'h0, io_wdata_data[510:384] & 127'h55AAAAAAAAAAAAAAAB55555556AAAD5B};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_75 =
+    {1'h0, io_wdata_data[510:384] & 127'h66CCCCCCCCCCCCCCCD9999999B33366D};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_78 =
+    {1'h0, io_wdata_data[510:385] & 126'h3C7878787878787878F0F0F0F1E1E3C7, 1'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_81 =
+    {io_wdata_data[511:388] & 124'h80FF00FF00FF00FF01FE01FE03FC07F, 4'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_84 =
+    {8'h0, io_wdata_data[503:395] & 109'h1FFFE0001FFFE0003FFFC0007FFF, 11'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_87 =
+    {8'h0, io_wdata_data[503:410] & 94'h3FFFFFFFC00000007FFFFFFF, 26'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_90 = {8'h0, io_wdata_data[503:441], 57'h0};
+  wire [127:0] _arrayWriteData_syndromeUInt_T_93 = {io_wdata_data[511:504], 120'h0};
+  reg          error_REG;
+  reg          error_REG_1;
+  always @(posedge clock) begin
+    error_REG <= io_req_valid & ~io_req_bits_wen;
+    error_REG_1 <= error_REG;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        error_REG = _RANDOM[/*Zero width*/ 1'b0][0];
+        error_REG_1 = _RANDOM[/*Zero width*/ 1'b0][1];
+      `endif // RANDOMIZE_REG_INIT
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  wire [11:0]  childBd_addr;
+  wire [11:0]  childBd_addr_rd;
+  wire [136:0] childBd_wdata;
+  wire         childBd_wmask;
+  wire         childBd_re;
+  wire         childBd_we;
+  wire         childBd_ack;
+  wire         childBd_selectedOH;
+  wire [2:0]   childBd_array;
+  wire [11:0]  childBd_1_addr;
+  wire [11:0]  childBd_1_addr_rd;
+  wire [136:0] childBd_1_wdata;
+  wire         childBd_1_wmask;
+  wire         childBd_1_re;
+  wire         childBd_1_we;
+  wire         childBd_1_ack;
+  wire         childBd_1_selectedOH;
+  wire [3:0]   childBd_1_array;
+  wire [11:0]  childBd_2_addr;
+  wire [11:0]  childBd_2_addr_rd;
+  wire [136:0] childBd_2_wdata;
+  wire         childBd_2_wmask;
+  wire         childBd_2_re;
+  wire         childBd_2_we;
+  wire         childBd_2_ack;
+  wire         childBd_2_selectedOH;
+  wire [3:0]   childBd_2_array;
+  wire [11:0]  childBd_3_addr;
+  wire [11:0]  childBd_3_addr_rd;
+  wire [136:0] childBd_3_wdata;
+  wire         childBd_3_wmask;
+  wire         childBd_3_re;
+  wire         childBd_3_we;
+  wire         childBd_3_ack;
+  wire         childBd_3_selectedOH;
+  wire [3:0]   childBd_3_array;
+  GatedSplittedSRAM array (
+    .clock                            (clock),
+    .reset                            (reset),
+    .io_r_req_valid                   (io_req_valid & ~io_req_bits_wen),
+    .io_r_req_bits_setIdx             (arrayIdx),
+    .io_r_resp_data_0_data            (_array_io_r_resp_data_0_data),
+    .io_w_req_valid                   (io_req_valid & io_req_bits_wen),
+    .io_w_req_bits_setIdx             (arrayIdx),
+    .io_w_req_bits_data_0_data
+      ({^{^_arrayWriteData_syndromeUInt_T_21,
+          ^_arrayWriteData_syndromeUInt_T_18,
+          ^_arrayWriteData_syndromeUInt_T_15,
+          ^_arrayWriteData_syndromeUInt_T_12,
+          ^_arrayWriteData_syndromeUInt_T_9,
+          ^_arrayWriteData_syndromeUInt_T_6,
+          ^_arrayWriteData_syndromeUInt_T_3,
+          ^_arrayWriteData_syndromeUInt_T,
+          io_wdata_data[127:0]},
+        ^_arrayWriteData_syndromeUInt_T_21,
+        ^_arrayWriteData_syndromeUInt_T_18,
+        ^_arrayWriteData_syndromeUInt_T_15,
+        ^_arrayWriteData_syndromeUInt_T_12,
+        ^_arrayWriteData_syndromeUInt_T_9,
+        ^_arrayWriteData_syndromeUInt_T_6,
+        ^_arrayWriteData_syndromeUInt_T_3,
+        ^_arrayWriteData_syndromeUInt_T,
+        io_wdata_data[127:0],
+        ^{^_arrayWriteData_syndromeUInt_T_45,
+          ^_arrayWriteData_syndromeUInt_T_42,
+          ^_arrayWriteData_syndromeUInt_T_39,
+          ^_arrayWriteData_syndromeUInt_T_36,
+          ^_arrayWriteData_syndromeUInt_T_33,
+          ^_arrayWriteData_syndromeUInt_T_30,
+          ^_arrayWriteData_syndromeUInt_T_27,
+          ^_arrayWriteData_syndromeUInt_T_24,
+          io_wdata_data[255:128]},
+        ^_arrayWriteData_syndromeUInt_T_45,
+        ^_arrayWriteData_syndromeUInt_T_42,
+        ^_arrayWriteData_syndromeUInt_T_39,
+        ^_arrayWriteData_syndromeUInt_T_36,
+        ^_arrayWriteData_syndromeUInt_T_33,
+        ^_arrayWriteData_syndromeUInt_T_30,
+        ^_arrayWriteData_syndromeUInt_T_27,
+        ^_arrayWriteData_syndromeUInt_T_24,
+        io_wdata_data[255:128],
+        ^{^_arrayWriteData_syndromeUInt_T_69,
+          ^_arrayWriteData_syndromeUInt_T_66,
+          ^_arrayWriteData_syndromeUInt_T_63,
+          ^_arrayWriteData_syndromeUInt_T_60,
+          ^_arrayWriteData_syndromeUInt_T_57,
+          ^_arrayWriteData_syndromeUInt_T_54,
+          ^_arrayWriteData_syndromeUInt_T_51,
+          ^_arrayWriteData_syndromeUInt_T_48,
+          io_wdata_data[383:256]},
+        ^_arrayWriteData_syndromeUInt_T_69,
+        ^_arrayWriteData_syndromeUInt_T_66,
+        ^_arrayWriteData_syndromeUInt_T_63,
+        ^_arrayWriteData_syndromeUInt_T_60,
+        ^_arrayWriteData_syndromeUInt_T_57,
+        ^_arrayWriteData_syndromeUInt_T_54,
+        ^_arrayWriteData_syndromeUInt_T_51,
+        ^_arrayWriteData_syndromeUInt_T_48,
+        io_wdata_data[383:256],
+        ^{^_arrayWriteData_syndromeUInt_T_93,
+          ^_arrayWriteData_syndromeUInt_T_90,
+          ^_arrayWriteData_syndromeUInt_T_87,
+          ^_arrayWriteData_syndromeUInt_T_84,
+          ^_arrayWriteData_syndromeUInt_T_81,
+          ^_arrayWriteData_syndromeUInt_T_78,
+          ^_arrayWriteData_syndromeUInt_T_75,
+          ^_arrayWriteData_syndromeUInt_T_72,
+          io_wdata_data[511:384]},
+        ^_arrayWriteData_syndromeUInt_T_93,
+        ^_arrayWriteData_syndromeUInt_T_90,
+        ^_arrayWriteData_syndromeUInt_T_87,
+        ^_arrayWriteData_syndromeUInt_T_84,
+        ^_arrayWriteData_syndromeUInt_T_81,
+        ^_arrayWriteData_syndromeUInt_T_78,
+        ^_arrayWriteData_syndromeUInt_T_75,
+        ^_arrayWriteData_syndromeUInt_T_72,
+        io_wdata_data[511:384]}),
+    .io_en                            (io_en),
+    .boreChildrenBd_bore_addr         (childBd_addr),
+    .boreChildrenBd_bore_addr_rd      (childBd_addr_rd),
+    .boreChildrenBd_bore_wdata        (childBd_wdata),
+    .boreChildrenBd_bore_wmask        (childBd_wmask),
+    .boreChildrenBd_bore_re           (childBd_re),
+    .boreChildrenBd_bore_we           (childBd_we),
+    .boreChildrenBd_bore_rdata        (childBd_rdata),
+    .boreChildrenBd_bore_ack          (childBd_ack),
+    .boreChildrenBd_bore_selectedOH   (childBd_selectedOH),
+    .boreChildrenBd_bore_array        (childBd_array),
+    .boreChildrenBd_bore_1_addr       (childBd_1_addr),
+    .boreChildrenBd_bore_1_addr_rd    (childBd_1_addr_rd),
+    .boreChildrenBd_bore_1_wdata      (childBd_1_wdata),
+    .boreChildrenBd_bore_1_wmask      (childBd_1_wmask),
+    .boreChildrenBd_bore_1_re         (childBd_1_re),
+    .boreChildrenBd_bore_1_we         (childBd_1_we),
+    .boreChildrenBd_bore_1_rdata      (childBd_1_rdata),
+    .boreChildrenBd_bore_1_ack        (childBd_1_ack),
+    .boreChildrenBd_bore_1_selectedOH (childBd_1_selectedOH),
+    .boreChildrenBd_bore_1_array      (childBd_1_array),
+    .boreChildrenBd_bore_2_addr       (childBd_2_addr),
+    .boreChildrenBd_bore_2_addr_rd    (childBd_2_addr_rd),
+    .boreChildrenBd_bore_2_wdata      (childBd_2_wdata),
+    .boreChildrenBd_bore_2_wmask      (childBd_2_wmask),
+    .boreChildrenBd_bore_2_re         (childBd_2_re),
+    .boreChildrenBd_bore_2_we         (childBd_2_we),
+    .boreChildrenBd_bore_2_rdata      (childBd_2_rdata),
+    .boreChildrenBd_bore_2_ack        (childBd_2_ack),
+    .boreChildrenBd_bore_2_selectedOH (childBd_2_selectedOH),
+    .boreChildrenBd_bore_2_array      (childBd_2_array),
+    .boreChildrenBd_bore_3_addr       (childBd_3_addr),
+    .boreChildrenBd_bore_3_addr_rd    (childBd_3_addr_rd),
+    .boreChildrenBd_bore_3_wdata      (childBd_3_wdata),
+    .boreChildrenBd_bore_3_wmask      (childBd_3_wmask),
+    .boreChildrenBd_bore_3_re         (childBd_3_re),
+    .boreChildrenBd_bore_3_we         (childBd_3_we),
+    .boreChildrenBd_bore_3_rdata      (childBd_3_rdata),
+    .boreChildrenBd_bore_3_ack        (childBd_3_ack),
+    .boreChildrenBd_bore_3_selectedOH (childBd_3_selectedOH),
+    .boreChildrenBd_bore_3_array      (childBd_3_array),
+    .sigFromSrams_bore_ram_hold       (sigFromSrams_bore_ram_hold),
+    .sigFromSrams_bore_ram_bypass     (sigFromSrams_bore_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken   (sigFromSrams_bore_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk    (sigFromSrams_bore_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp   (sigFromSrams_bore_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold   (sigFromSrams_bore_ram_mcp_hold),
+    .sigFromSrams_bore_cgen           (sigFromSrams_bore_cgen),
+    .sigFromSrams_bore_1_ram_hold     (sigFromSrams_bore_1_ram_hold),
+    .sigFromSrams_bore_1_ram_bypass   (sigFromSrams_bore_1_ram_bypass),
+    .sigFromSrams_bore_1_ram_bp_clken (sigFromSrams_bore_1_ram_bp_clken),
+    .sigFromSrams_bore_1_ram_aux_clk  (sigFromSrams_bore_1_ram_aux_clk),
+    .sigFromSrams_bore_1_ram_aux_ckbp (sigFromSrams_bore_1_ram_aux_ckbp),
+    .sigFromSrams_bore_1_ram_mcp_hold (sigFromSrams_bore_1_ram_mcp_hold),
+    .sigFromSrams_bore_1_cgen         (sigFromSrams_bore_1_cgen),
+    .sigFromSrams_bore_2_ram_hold     (sigFromSrams_bore_2_ram_hold),
+    .sigFromSrams_bore_2_ram_bypass   (sigFromSrams_bore_2_ram_bypass),
+    .sigFromSrams_bore_2_ram_bp_clken (sigFromSrams_bore_2_ram_bp_clken),
+    .sigFromSrams_bore_2_ram_aux_clk  (sigFromSrams_bore_2_ram_aux_clk),
+    .sigFromSrams_bore_2_ram_aux_ckbp (sigFromSrams_bore_2_ram_aux_ckbp),
+    .sigFromSrams_bore_2_ram_mcp_hold (sigFromSrams_bore_2_ram_mcp_hold),
+    .sigFromSrams_bore_2_cgen         (sigFromSrams_bore_2_cgen),
+    .sigFromSrams_bore_3_ram_hold     (sigFromSrams_bore_3_ram_hold),
+    .sigFromSrams_bore_3_ram_bypass   (sigFromSrams_bore_3_ram_bypass),
+    .sigFromSrams_bore_3_ram_bp_clken (sigFromSrams_bore_3_ram_bp_clken),
+    .sigFromSrams_bore_3_ram_aux_clk  (sigFromSrams_bore_3_ram_aux_clk),
+    .sigFromSrams_bore_3_ram_aux_ckbp (sigFromSrams_bore_3_ram_aux_ckbp),
+    .sigFromSrams_bore_3_ram_mcp_hold (sigFromSrams_bore_3_ram_mcp_hold),
+    .sigFromSrams_bore_3_cgen         (sigFromSrams_bore_3_cgen)
+  );
+  L2DataStorage mbistPl (
+    .clock               (clock),
+    .reset               (reset),
+    .mbist_array         (bd_array),
+    .mbist_all           (bd_all),
+    .mbist_req           (bd_req),
+    .mbist_ack           (bd_ack),
+    .mbist_writeen       (bd_writeen),
+    .mbist_be            (bd_be),
+    .mbist_addr          (bd_addr),
+    .mbist_indata        (bd_indata),
+    .mbist_readen        (bd_readen),
+    .mbist_addr_rd       (bd_addr_rd),
+    .mbist_outdata       (bd_outdata),
+    .toSRAM_0_addr       (childBd_addr),
+    .toSRAM_0_addr_rd    (childBd_addr_rd),
+    .toSRAM_0_wdata      (childBd_wdata),
+    .toSRAM_0_wmask      (childBd_wmask),
+    .toSRAM_0_re         (childBd_re),
+    .toSRAM_0_we         (childBd_we),
+    .toSRAM_0_rdata      (childBd_rdata),
+    .toSRAM_0_ack        (childBd_ack),
+    .toSRAM_0_selectedOH (childBd_selectedOH),
+    .toSRAM_0_array      (childBd_array),
+    .toSRAM_1_addr       (childBd_1_addr),
+    .toSRAM_1_addr_rd    (childBd_1_addr_rd),
+    .toSRAM_1_wdata      (childBd_1_wdata),
+    .toSRAM_1_wmask      (childBd_1_wmask),
+    .toSRAM_1_re         (childBd_1_re),
+    .toSRAM_1_we         (childBd_1_we),
+    .toSRAM_1_rdata      (childBd_1_rdata),
+    .toSRAM_1_ack        (childBd_1_ack),
+    .toSRAM_1_selectedOH (childBd_1_selectedOH),
+    .toSRAM_1_array      (childBd_1_array),
+    .toSRAM_2_addr       (childBd_2_addr),
+    .toSRAM_2_addr_rd    (childBd_2_addr_rd),
+    .toSRAM_2_wdata      (childBd_2_wdata),
+    .toSRAM_2_wmask      (childBd_2_wmask),
+    .toSRAM_2_re         (childBd_2_re),
+    .toSRAM_2_we         (childBd_2_we),
+    .toSRAM_2_rdata      (childBd_2_rdata),
+    .toSRAM_2_ack        (childBd_2_ack),
+    .toSRAM_2_selectedOH (childBd_2_selectedOH),
+    .toSRAM_2_array      (childBd_2_array),
+    .toSRAM_3_addr       (childBd_3_addr),
+    .toSRAM_3_addr_rd    (childBd_3_addr_rd),
+    .toSRAM_3_wdata      (childBd_3_wdata),
+    .toSRAM_3_wmask      (childBd_3_wmask),
+    .toSRAM_3_re         (childBd_3_re),
+    .toSRAM_3_we         (childBd_3_we),
+    .toSRAM_3_rdata      (childBd_3_rdata),
+    .toSRAM_3_ack        (childBd_3_ack),
+    .toSRAM_3_selectedOH (childBd_3_selectedOH),
+    .toSRAM_3_array      (childBd_3_array)
+  );
+  assign io_error =
+    (^(_array_io_r_resp_data_0_data[136:0]) | ~(^(_array_io_r_resp_data_0_data[136:0]))
+     & (|{^{_array_io_r_resp_data_0_data[135:120] & 16'h80FF, 120'h0},
+          ^{_array_io_r_resp_data_0_data[134:57] & 78'h20007FFFFFFFFFFFFFFF, 57'h0},
+          ^{_array_io_r_resp_data_0_data[133:26] & 108'h8003FFFFFFFC00000007FFFFFFF,
+            26'h0},
+          ^{_array_io_r_resp_data_0_data[132:11] & 122'h2001FFFE0001FFFE0003FFFC0007FFF,
+            11'h0},
+          ^{_array_io_r_resp_data_0_data[131:4] & 128'h880FF00FF00FF00FF01FE01FE03FC07F,
+            4'h0},
+          ^{_array_io_r_resp_data_0_data[130:1] & 130'h23C7878787878787878F0F0F0F1E1E3C7,
+            1'h0},
+          ^(_array_io_r_resp_data_0_data[129:0] & 130'h266CCCCCCCCCCCCCCCD9999999B33366D),
+          ^(_array_io_r_resp_data_0_data[128:0]
+            & 129'h155AAAAAAAAAAAAAAAB55555556AAAD5B)})
+     | ^(_array_io_r_resp_data_0_data[273:137])
+     | ~(^(_array_io_r_resp_data_0_data[273:137]))
+     & (|{^{_array_io_r_resp_data_0_data[272:257] & 16'h80FF, 120'h0},
+          ^{_array_io_r_resp_data_0_data[271:194] & 78'h20007FFFFFFFFFFFFFFF, 57'h0},
+          ^{_array_io_r_resp_data_0_data[270:163] & 108'h8003FFFFFFFC00000007FFFFFFF,
+            26'h0},
+          ^{_array_io_r_resp_data_0_data[269:148] & 122'h2001FFFE0001FFFE0003FFFC0007FFF,
+            11'h0},
+          ^{_array_io_r_resp_data_0_data[268:141] & 128'h880FF00FF00FF00FF01FE01FE03FC07F,
+            4'h0},
+          ^{_array_io_r_resp_data_0_data[267:138]
+              & 130'h23C7878787878787878F0F0F0F1E1E3C7,
+            1'h0},
+          ^(_array_io_r_resp_data_0_data[266:137]
+            & 130'h266CCCCCCCCCCCCCCCD9999999B33366D),
+          ^(_array_io_r_resp_data_0_data[265:137]
+            & 129'h155AAAAAAAAAAAAAAAB55555556AAAD5B)})
+     | ^(_array_io_r_resp_data_0_data[410:274])
+     | ~(^(_array_io_r_resp_data_0_data[410:274]))
+     & (|{^{_array_io_r_resp_data_0_data[409:394] & 16'h80FF, 120'h0},
+          ^{_array_io_r_resp_data_0_data[408:331] & 78'h20007FFFFFFFFFFFFFFF, 57'h0},
+          ^{_array_io_r_resp_data_0_data[407:300] & 108'h8003FFFFFFFC00000007FFFFFFF,
+            26'h0},
+          ^{_array_io_r_resp_data_0_data[406:285] & 122'h2001FFFE0001FFFE0003FFFC0007FFF,
+            11'h0},
+          ^{_array_io_r_resp_data_0_data[405:278] & 128'h880FF00FF00FF00FF01FE01FE03FC07F,
+            4'h0},
+          ^{_array_io_r_resp_data_0_data[404:275]
+              & 130'h23C7878787878787878F0F0F0F1E1E3C7,
+            1'h0},
+          ^(_array_io_r_resp_data_0_data[403:274]
+            & 130'h266CCCCCCCCCCCCCCCD9999999B33366D),
+          ^(_array_io_r_resp_data_0_data[402:274]
+            & 129'h155AAAAAAAAAAAAAAAB55555556AAAD5B)})
+     | ^(_array_io_r_resp_data_0_data[547:411])
+     | ~(^(_array_io_r_resp_data_0_data[547:411]))
+     & (|{^{_array_io_r_resp_data_0_data[546:531] & 16'h80FF, 120'h0},
+          ^{_array_io_r_resp_data_0_data[545:468] & 78'h20007FFFFFFFFFFFFFFF, 57'h0},
+          ^{_array_io_r_resp_data_0_data[544:437] & 108'h8003FFFFFFFC00000007FFFFFFF,
+            26'h0},
+          ^{_array_io_r_resp_data_0_data[543:422] & 122'h2001FFFE0001FFFE0003FFFC0007FFF,
+            11'h0},
+          ^{_array_io_r_resp_data_0_data[542:415] & 128'h880FF00FF00FF00FF01FE01FE03FC07F,
+            4'h0},
+          ^{_array_io_r_resp_data_0_data[541:412]
+              & 130'h23C7878787878787878F0F0F0F1E1E3C7,
+            1'h0},
+          ^(_array_io_r_resp_data_0_data[540:411]
+            & 130'h266CCCCCCCCCCCCCCCD9999999B33366D),
+          ^(_array_io_r_resp_data_0_data[539:411]
+            & 129'h155AAAAAAAAAAAAAAAB55555556AAAD5B)})) & error_REG_1;
+  assign io_rdata_data =
+    {_array_io_r_resp_data_0_data[127:0],
+     _array_io_r_resp_data_0_data[264:137],
+     _array_io_r_resp_data_0_data[401:274],
+     _array_io_r_resp_data_0_data[538:411]};
+  assign boreChildrenBd_bore_ack = bd_ack;
+  assign boreChildrenBd_bore_outdata = bd_outdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit.sv b/flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit.sv
new file mode 100644
index 0000000000..d65c03460a
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit.sv
@@ -0,0 +1,185 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Decoupled2LCredit(
+  input          clock,
+  input          reset,
+  output         io_in_ready,
+  input          io_in_valid,
+  input  [3:0]   io_in_bits_qos,
+  input  [10:0]  io_in_bits_tgtID,
+  input  [10:0]  io_in_bits_srcID,
+  input  [11:0]  io_in_bits_txnID,
+  input  [10:0]  io_in_bits_returnNID,
+  input          io_in_bits_stashNIDValid,
+  input  [11:0]  io_in_bits_returnTxnID,
+  input  [6:0]   io_in_bits_opcode,
+  input  [2:0]   io_in_bits_size,
+  input  [47:0]  io_in_bits_addr,
+  input          io_in_bits_ns,
+  input          io_in_bits_likelyshared,
+  input          io_in_bits_allowRetry,
+  input  [1:0]   io_in_bits_order,
+  input  [3:0]   io_in_bits_pCrdType,
+  input          io_in_bits_memAttr_allocate,
+  input          io_in_bits_memAttr_cacheable,
+  input          io_in_bits_memAttr_device,
+  input          io_in_bits_memAttr_ewa,
+  input          io_in_bits_snpAttr,
+  input  [7:0]   io_in_bits_lpIDWithPadding,
+  input          io_in_bits_snoopMe,
+  input          io_in_bits_expCompAck,
+  input  [1:0]   io_in_bits_tagOp,
+  input          io_in_bits_traceTag,
+  input          io_in_bits_mpam_perfMonGroup,
+  input  [8:0]   io_in_bits_mpam_partID,
+  input          io_in_bits_mpam_mpamNS,
+  input  [3:0]   io_in_bits_rsvdc,
+  output         io_out_flitpend,
+  output         io_out_flitv,
+  output [161:0] io_out_flit,
+  input          io_out_lcrdv,
+  input  [1:0]   io_state_state
+);
+
+  wire         io_in_ready_0;
+  reg  [3:0]   lcreditPool;
+  wire         flitv =
+    io_in_ready_0 & io_in_valid | ~io_in_valid & (&io_state_state) & (|lcreditPool);
+  assign io_in_ready_0 = (|lcreditPool) & ~(~(|io_state_state) | io_state_state == 2'h1);
+  reg          out_flitpend_REG;
+  reg          out_flitv_REG;
+  reg  [161:0] out_flit_r;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      lcreditPool <= 4'h0;
+      out_flitpend_REG <= 1'h0;
+      out_flitv_REG <= 1'h0;
+    end
+    else begin
+      if (io_out_lcrdv & (|io_state_state)) begin
+        if (~flitv)
+          lcreditPool <= 4'(lcreditPool + 4'h1);
+      end
+      else if (flitv)
+        lcreditPool <= 4'(lcreditPool - 4'h1);
+      out_flitpend_REG <= 1'h1;
+      out_flitv_REG <= flitv;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (flitv)
+      out_flit_r <=
+        io_in_valid
+          ? {io_in_bits_rsvdc,
+             io_in_bits_mpam_perfMonGroup,
+             io_in_bits_mpam_partID,
+             io_in_bits_mpam_mpamNS,
+             io_in_bits_traceTag,
+             io_in_bits_tagOp,
+             io_in_bits_expCompAck,
+             io_in_bits_snoopMe,
+             io_in_bits_lpIDWithPadding,
+             io_in_bits_snpAttr,
+             io_in_bits_memAttr_allocate,
+             io_in_bits_memAttr_cacheable,
+             io_in_bits_memAttr_device,
+             io_in_bits_memAttr_ewa,
+             io_in_bits_pCrdType,
+             io_in_bits_order,
+             io_in_bits_allowRetry,
+             io_in_bits_likelyshared,
+             io_in_bits_ns,
+             io_in_bits_addr,
+             io_in_bits_size,
+             io_in_bits_opcode,
+             io_in_bits_returnTxnID,
+             io_in_bits_stashNIDValid,
+             io_in_bits_returnNID,
+             io_in_bits_txnID,
+             io_in_bits_srcID,
+             io_in_bits_tgtID,
+             io_in_bits_qos}
+          : 162'h0;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:5];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        lcreditPool = _RANDOM[3'h0][3:0];
+        out_flitpend_REG = _RANDOM[3'h0][4];
+        out_flitv_REG = _RANDOM[3'h0][5];
+        out_flit_r =
+          {_RANDOM[3'h0][31:6],
+           _RANDOM[3'h1],
+           _RANDOM[3'h2],
+           _RANDOM[3'h3],
+           _RANDOM[3'h4],
+           _RANDOM[3'h5][7:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        lcreditPool = 4'h0;
+        out_flitpend_REG = 1'h0;
+        out_flitv_REG = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_ready = io_in_ready_0;
+  assign io_out_flitpend = out_flitpend_REG;
+  assign io_out_flitv = out_flitv_REG;
+  assign io_out_flit = out_flit_r;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit_1.sv b/flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit_1.sv
new file mode 100644
index 0000000000..166dfea352
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit_1.sv
@@ -0,0 +1,147 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Decoupled2LCredit_1(
+  input         clock,
+  input         reset,
+  output        io_in_ready,
+  input         io_in_valid,
+  input  [3:0]  io_in_bits_qos,
+  input  [10:0] io_in_bits_tgtID,
+  input  [10:0] io_in_bits_srcID,
+  input  [11:0] io_in_bits_txnID,
+  input  [4:0]  io_in_bits_opcode,
+  input  [1:0]  io_in_bits_respErr,
+  input  [2:0]  io_in_bits_resp,
+  input  [2:0]  io_in_bits_fwdState,
+  input  [2:0]  io_in_bits_cBusy,
+  input  [11:0] io_in_bits_dbID,
+  input  [3:0]  io_in_bits_pCrdType,
+  input  [1:0]  io_in_bits_tagOp,
+  input         io_in_bits_traceTag,
+  output        io_out_flitpend,
+  output        io_out_flitv,
+  output [72:0] io_out_flit,
+  input         io_out_lcrdv,
+  input  [1:0]  io_state_state
+);
+
+  wire        io_in_ready_0;
+  reg  [3:0]  lcreditPool;
+  wire        flitv =
+    io_in_ready_0 & io_in_valid | ~io_in_valid & (&io_state_state) & (|lcreditPool);
+  assign io_in_ready_0 = (|lcreditPool) & ~(~(|io_state_state) | io_state_state == 2'h1);
+  reg         out_flitpend_REG;
+  reg         out_flitv_REG;
+  reg  [72:0] out_flit_r;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      lcreditPool <= 4'h0;
+      out_flitpend_REG <= 1'h0;
+      out_flitv_REG <= 1'h0;
+    end
+    else begin
+      if (io_out_lcrdv & (|io_state_state)) begin
+        if (~flitv)
+          lcreditPool <= 4'(lcreditPool + 4'h1);
+      end
+      else if (flitv)
+        lcreditPool <= 4'(lcreditPool - 4'h1);
+      out_flitpend_REG <= 1'h1;
+      out_flitv_REG <= flitv;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (flitv)
+      out_flit_r <=
+        io_in_valid
+          ? {io_in_bits_traceTag,
+             io_in_bits_tagOp,
+             io_in_bits_pCrdType,
+             io_in_bits_dbID,
+             io_in_bits_cBusy,
+             io_in_bits_fwdState,
+             io_in_bits_resp,
+             io_in_bits_respErr,
+             io_in_bits_opcode,
+             io_in_bits_txnID,
+             io_in_bits_srcID,
+             io_in_bits_tgtID,
+             io_in_bits_qos}
+          : 73'h0;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:2];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        lcreditPool = _RANDOM[2'h0][3:0];
+        out_flitpend_REG = _RANDOM[2'h0][4];
+        out_flitv_REG = _RANDOM[2'h0][5];
+        out_flit_r = {_RANDOM[2'h0][31:6], _RANDOM[2'h1], _RANDOM[2'h2][14:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        lcreditPool = 4'h0;
+        out_flitpend_REG = 1'h0;
+        out_flitv_REG = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_ready = io_in_ready_0;
+  assign io_out_flitpend = out_flitpend_REG;
+  assign io_out_flitv = out_flitv_REG;
+  assign io_out_flit = out_flit_r;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit_2.sv b/flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit_2.sv
new file mode 100644
index 0000000000..1523c35d0e
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Decoupled2LCredit_2.sv
@@ -0,0 +1,179 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Decoupled2LCredit_2(
+  input          clock,
+  input          reset,
+  output         io_in_ready,
+  input          io_in_valid,
+  input  [3:0]   io_in_bits_qos,
+  input  [10:0]  io_in_bits_tgtID,
+  input  [10:0]  io_in_bits_srcID,
+  input  [11:0]  io_in_bits_txnID,
+  input  [10:0]  io_in_bits_homeNID,
+  input  [3:0]   io_in_bits_opcode,
+  input  [1:0]   io_in_bits_respErr,
+  input  [2:0]   io_in_bits_resp,
+  input  [3:0]   io_in_bits_dataSource,
+  input  [2:0]   io_in_bits_cBusy,
+  input  [11:0]  io_in_bits_dbID,
+  input  [1:0]   io_in_bits_ccID,
+  input  [1:0]   io_in_bits_dataID,
+  input  [1:0]   io_in_bits_tagOp,
+  input  [7:0]   io_in_bits_tag,
+  input  [1:0]   io_in_bits_tu,
+  input          io_in_bits_traceTag,
+  input  [3:0]   io_in_bits_rsvdc,
+  input  [31:0]  io_in_bits_be,
+  input  [255:0] io_in_bits_data,
+  input  [31:0]  io_in_bits_dataCheck,
+  input  [3:0]   io_in_bits_poison,
+  output         io_out_flitpend,
+  output         io_out_flitv,
+  output [421:0] io_out_flit,
+  input          io_out_lcrdv,
+  input  [1:0]   io_state_state
+);
+
+  wire         io_in_ready_0;
+  reg  [3:0]   lcreditPool;
+  wire         flitv =
+    io_in_ready_0 & io_in_valid | ~io_in_valid & (&io_state_state) & (|lcreditPool);
+  assign io_in_ready_0 = (|lcreditPool) & ~(~(|io_state_state) | io_state_state == 2'h1);
+  reg          out_flitpend_REG;
+  reg          out_flitv_REG;
+  reg  [421:0] out_flit_r;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      lcreditPool <= 4'h0;
+      out_flitpend_REG <= 1'h0;
+      out_flitv_REG <= 1'h0;
+    end
+    else begin
+      if (io_out_lcrdv & (|io_state_state)) begin
+        if (~flitv)
+          lcreditPool <= 4'(lcreditPool + 4'h1);
+      end
+      else if (flitv)
+        lcreditPool <= 4'(lcreditPool - 4'h1);
+      out_flitpend_REG <= 1'h1;
+      out_flitv_REG <= flitv;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (flitv)
+      out_flit_r <=
+        io_in_valid
+          ? {io_in_bits_poison,
+             io_in_bits_dataCheck,
+             io_in_bits_data,
+             io_in_bits_be,
+             io_in_bits_rsvdc,
+             io_in_bits_traceTag,
+             io_in_bits_tu,
+             io_in_bits_tag,
+             io_in_bits_tagOp,
+             io_in_bits_dataID,
+             io_in_bits_ccID,
+             io_in_bits_dbID,
+             io_in_bits_cBusy,
+             io_in_bits_dataSource,
+             io_in_bits_resp,
+             io_in_bits_respErr,
+             io_in_bits_opcode,
+             io_in_bits_homeNID,
+             io_in_bits_txnID,
+             io_in_bits_srcID,
+             io_in_bits_tgtID,
+             io_in_bits_qos}
+          : 422'h0;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:13];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hE; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        lcreditPool = _RANDOM[4'h0][3:0];
+        out_flitpend_REG = _RANDOM[4'h0][4];
+        out_flitv_REG = _RANDOM[4'h0][5];
+        out_flit_r =
+          {_RANDOM[4'h0][31:6],
+           _RANDOM[4'h1],
+           _RANDOM[4'h2],
+           _RANDOM[4'h3],
+           _RANDOM[4'h4],
+           _RANDOM[4'h5],
+           _RANDOM[4'h6],
+           _RANDOM[4'h7],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB],
+           _RANDOM[4'hC],
+           _RANDOM[4'hD][11:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        lcreditPool = 4'h0;
+        out_flitpend_REG = 1'h0;
+        out_flitv_REG = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_ready = io_in_ready_0;
+  assign io_out_flitpend = out_flitpend_REG;
+  assign io_out_flitv = out_flitv_REG;
+  assign io_out_flit = out_flit_r;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/DelayQueue.sv b/flow/designs/src/xiangshan_coupledl2/deps/DelayQueue.sv
new file mode 100644
index 0000000000..44cedaca61
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/DelayQueue.sv
@@ -0,0 +1,478 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module DelayQueue(
+  input         clock,
+  input         reset,
+  input  [9:0]  io_pfCtrlOfDelayLatency,
+  input         io_in_valid,
+  input  [41:0] io_in_bits,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [47:0] io_out_bits
+);
+
+  reg  [41:0]       queue_0_addrNoOffset;
+  reg  [9:0]        queue_0_cnt;
+  reg  [41:0]       queue_1_addrNoOffset;
+  reg  [9:0]        queue_1_cnt;
+  reg  [41:0]       queue_2_addrNoOffset;
+  reg  [9:0]        queue_2_cnt;
+  reg  [41:0]       queue_3_addrNoOffset;
+  reg  [9:0]        queue_3_cnt;
+  reg  [41:0]       queue_4_addrNoOffset;
+  reg  [9:0]        queue_4_cnt;
+  reg  [41:0]       queue_5_addrNoOffset;
+  reg  [9:0]        queue_5_cnt;
+  reg  [41:0]       queue_6_addrNoOffset;
+  reg  [9:0]        queue_6_cnt;
+  reg  [41:0]       queue_7_addrNoOffset;
+  reg  [9:0]        queue_7_cnt;
+  reg  [41:0]       queue_8_addrNoOffset;
+  reg  [9:0]        queue_8_cnt;
+  reg  [41:0]       queue_9_addrNoOffset;
+  reg  [9:0]        queue_9_cnt;
+  reg  [41:0]       queue_10_addrNoOffset;
+  reg  [9:0]        queue_10_cnt;
+  reg  [41:0]       queue_11_addrNoOffset;
+  reg  [9:0]        queue_11_cnt;
+  reg  [41:0]       queue_12_addrNoOffset;
+  reg  [9:0]        queue_12_cnt;
+  reg  [41:0]       queue_13_addrNoOffset;
+  reg  [9:0]        queue_13_cnt;
+  reg  [41:0]       queue_14_addrNoOffset;
+  reg  [9:0]        queue_14_cnt;
+  reg  [41:0]       queue_15_addrNoOffset;
+  reg  [9:0]        queue_15_cnt;
+  reg               valids_0;
+  reg               valids_1;
+  reg               valids_2;
+  reg               valids_3;
+  reg               valids_4;
+  reg               valids_5;
+  reg               valids_6;
+  reg               valids_7;
+  reg               valids_8;
+  reg               valids_9;
+  reg               valids_10;
+  reg               valids_11;
+  reg               valids_12;
+  reg               valids_13;
+  reg               valids_14;
+  reg               valids_15;
+  reg  [3:0]        head;
+  reg  [3:0]        tail;
+  wire              _full_T = head == tail;
+  wire [15:0][41:0] _GEN =
+    {{queue_15_addrNoOffset},
+     {queue_14_addrNoOffset},
+     {queue_13_addrNoOffset},
+     {queue_12_addrNoOffset},
+     {queue_11_addrNoOffset},
+     {queue_10_addrNoOffset},
+     {queue_9_addrNoOffset},
+     {queue_8_addrNoOffset},
+     {queue_7_addrNoOffset},
+     {queue_6_addrNoOffset},
+     {queue_5_addrNoOffset},
+     {queue_4_addrNoOffset},
+     {queue_3_addrNoOffset},
+     {queue_2_addrNoOffset},
+     {queue_1_addrNoOffset},
+     {queue_0_addrNoOffset}};
+  wire [15:0][9:0]  _GEN_0 =
+    {{queue_15_cnt},
+     {queue_14_cnt},
+     {queue_13_cnt},
+     {queue_12_cnt},
+     {queue_11_cnt},
+     {queue_10_cnt},
+     {queue_9_cnt},
+     {queue_8_cnt},
+     {queue_7_cnt},
+     {queue_6_cnt},
+     {queue_5_cnt},
+     {queue_4_cnt},
+     {queue_3_cnt},
+     {queue_2_cnt},
+     {queue_1_cnt},
+     {queue_0_cnt}};
+  wire [15:0]       _GEN_1 =
+    {{valids_15},
+     {valids_14},
+     {valids_13},
+     {valids_12},
+     {valids_11},
+     {valids_10},
+     {valids_9},
+     {valids_8},
+     {valids_7},
+     {valids_6},
+     {valids_5},
+     {valids_4},
+     {valids_3},
+     {valids_2},
+     {valids_1},
+     {valids_0}};
+  wire              outValid =
+    ~(_full_T & ~valids_15) & _GEN_0[head] == 10'h0 & _GEN_1[head];
+  wire [9:0]        setDqLatency =
+    (|io_pfCtrlOfDelayLatency) ? io_pfCtrlOfDelayLatency : 10'h12C;
+  wire              _GEN_2 = io_in_valid & ~(_full_T & valids_15);
+  wire              _GEN_3 = _GEN_2 & tail == 4'h0;
+  wire              _GEN_4 = _GEN_2 & tail == 4'h1;
+  wire              _GEN_5 = _GEN_2 & tail == 4'h2;
+  wire              _GEN_6 = _GEN_2 & tail == 4'h3;
+  wire              _GEN_7 = _GEN_2 & tail == 4'h4;
+  wire              _GEN_8 = _GEN_2 & tail == 4'h5;
+  wire              _GEN_9 = _GEN_2 & tail == 4'h6;
+  wire              _GEN_10 = _GEN_2 & tail == 4'h7;
+  wire              _GEN_11 = _GEN_2 & tail == 4'h8;
+  wire              _GEN_12 = _GEN_2 & tail == 4'h9;
+  wire              _GEN_13 = _GEN_2 & tail == 4'hA;
+  wire              _GEN_14 = _GEN_2 & tail == 4'hB;
+  wire              _GEN_15 = _GEN_2 & tail == 4'hC;
+  wire              _GEN_16 = _GEN_2 & tail == 4'hD;
+  wire              _GEN_17 = _GEN_2 & tail == 4'hE;
+  wire              _GEN_18 = _GEN_2 & (&tail);
+  wire              _GEN_19 = outValid & io_out_ready;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      queue_0_addrNoOffset <= 42'h0;
+      queue_0_cnt <= 10'h0;
+      queue_1_addrNoOffset <= 42'h0;
+      queue_1_cnt <= 10'h0;
+      queue_2_addrNoOffset <= 42'h0;
+      queue_2_cnt <= 10'h0;
+      queue_3_addrNoOffset <= 42'h0;
+      queue_3_cnt <= 10'h0;
+      queue_4_addrNoOffset <= 42'h0;
+      queue_4_cnt <= 10'h0;
+      queue_5_addrNoOffset <= 42'h0;
+      queue_5_cnt <= 10'h0;
+      queue_6_addrNoOffset <= 42'h0;
+      queue_6_cnt <= 10'h0;
+      queue_7_addrNoOffset <= 42'h0;
+      queue_7_cnt <= 10'h0;
+      queue_8_addrNoOffset <= 42'h0;
+      queue_8_cnt <= 10'h0;
+      queue_9_addrNoOffset <= 42'h0;
+      queue_9_cnt <= 10'h0;
+      queue_10_addrNoOffset <= 42'h0;
+      queue_10_cnt <= 10'h0;
+      queue_11_addrNoOffset <= 42'h0;
+      queue_11_cnt <= 10'h0;
+      queue_12_addrNoOffset <= 42'h0;
+      queue_12_cnt <= 10'h0;
+      queue_13_addrNoOffset <= 42'h0;
+      queue_13_cnt <= 10'h0;
+      queue_14_addrNoOffset <= 42'h0;
+      queue_14_cnt <= 10'h0;
+      queue_15_addrNoOffset <= 42'h0;
+      queue_15_cnt <= 10'h0;
+      valids_0 <= 1'h0;
+      valids_1 <= 1'h0;
+      valids_2 <= 1'h0;
+      valids_3 <= 1'h0;
+      valids_4 <= 1'h0;
+      valids_5 <= 1'h0;
+      valids_6 <= 1'h0;
+      valids_7 <= 1'h0;
+      valids_8 <= 1'h0;
+      valids_9 <= 1'h0;
+      valids_10 <= 1'h0;
+      valids_11 <= 1'h0;
+      valids_12 <= 1'h0;
+      valids_13 <= 1'h0;
+      valids_14 <= 1'h0;
+      valids_15 <= 1'h0;
+      head <= 4'h0;
+      tail <= 4'h0;
+    end
+    else begin
+      if (_GEN_3)
+        queue_0_addrNoOffset <= io_in_bits;
+      if (|queue_0_cnt)
+        queue_0_cnt <= 10'(queue_0_cnt - 10'h1);
+      else if (_GEN_3)
+        queue_0_cnt <= setDqLatency;
+      if (_GEN_4)
+        queue_1_addrNoOffset <= io_in_bits;
+      if (|queue_1_cnt)
+        queue_1_cnt <= 10'(queue_1_cnt - 10'h1);
+      else if (_GEN_4)
+        queue_1_cnt <= setDqLatency;
+      if (_GEN_5)
+        queue_2_addrNoOffset <= io_in_bits;
+      if (|queue_2_cnt)
+        queue_2_cnt <= 10'(queue_2_cnt - 10'h1);
+      else if (_GEN_5)
+        queue_2_cnt <= setDqLatency;
+      if (_GEN_6)
+        queue_3_addrNoOffset <= io_in_bits;
+      if (|queue_3_cnt)
+        queue_3_cnt <= 10'(queue_3_cnt - 10'h1);
+      else if (_GEN_6)
+        queue_3_cnt <= setDqLatency;
+      if (_GEN_7)
+        queue_4_addrNoOffset <= io_in_bits;
+      if (|queue_4_cnt)
+        queue_4_cnt <= 10'(queue_4_cnt - 10'h1);
+      else if (_GEN_7)
+        queue_4_cnt <= setDqLatency;
+      if (_GEN_8)
+        queue_5_addrNoOffset <= io_in_bits;
+      if (|queue_5_cnt)
+        queue_5_cnt <= 10'(queue_5_cnt - 10'h1);
+      else if (_GEN_8)
+        queue_5_cnt <= setDqLatency;
+      if (_GEN_9)
+        queue_6_addrNoOffset <= io_in_bits;
+      if (|queue_6_cnt)
+        queue_6_cnt <= 10'(queue_6_cnt - 10'h1);
+      else if (_GEN_9)
+        queue_6_cnt <= setDqLatency;
+      if (_GEN_10)
+        queue_7_addrNoOffset <= io_in_bits;
+      if (|queue_7_cnt)
+        queue_7_cnt <= 10'(queue_7_cnt - 10'h1);
+      else if (_GEN_10)
+        queue_7_cnt <= setDqLatency;
+      if (_GEN_11)
+        queue_8_addrNoOffset <= io_in_bits;
+      if (|queue_8_cnt)
+        queue_8_cnt <= 10'(queue_8_cnt - 10'h1);
+      else if (_GEN_11)
+        queue_8_cnt <= setDqLatency;
+      if (_GEN_12)
+        queue_9_addrNoOffset <= io_in_bits;
+      if (|queue_9_cnt)
+        queue_9_cnt <= 10'(queue_9_cnt - 10'h1);
+      else if (_GEN_12)
+        queue_9_cnt <= setDqLatency;
+      if (_GEN_13)
+        queue_10_addrNoOffset <= io_in_bits;
+      if (|queue_10_cnt)
+        queue_10_cnt <= 10'(queue_10_cnt - 10'h1);
+      else if (_GEN_13)
+        queue_10_cnt <= setDqLatency;
+      if (_GEN_14)
+        queue_11_addrNoOffset <= io_in_bits;
+      if (|queue_11_cnt)
+        queue_11_cnt <= 10'(queue_11_cnt - 10'h1);
+      else if (_GEN_14)
+        queue_11_cnt <= setDqLatency;
+      if (_GEN_15)
+        queue_12_addrNoOffset <= io_in_bits;
+      if (|queue_12_cnt)
+        queue_12_cnt <= 10'(queue_12_cnt - 10'h1);
+      else if (_GEN_15)
+        queue_12_cnt <= setDqLatency;
+      if (_GEN_16)
+        queue_13_addrNoOffset <= io_in_bits;
+      if (|queue_13_cnt)
+        queue_13_cnt <= 10'(queue_13_cnt - 10'h1);
+      else if (_GEN_16)
+        queue_13_cnt <= setDqLatency;
+      if (_GEN_17)
+        queue_14_addrNoOffset <= io_in_bits;
+      if (|queue_14_cnt)
+        queue_14_cnt <= 10'(queue_14_cnt - 10'h1);
+      else if (_GEN_17)
+        queue_14_cnt <= setDqLatency;
+      if (_GEN_18)
+        queue_15_addrNoOffset <= io_in_bits;
+      if (|queue_15_cnt)
+        queue_15_cnt <= 10'(queue_15_cnt - 10'h1);
+      else if (_GEN_18)
+        queue_15_cnt <= setDqLatency;
+      valids_0 <= ~(_GEN_19 & head == 4'h0) & (_GEN_3 | valids_0);
+      valids_1 <= ~(_GEN_19 & head == 4'h1) & (_GEN_4 | valids_1);
+      valids_2 <= ~(_GEN_19 & head == 4'h2) & (_GEN_5 | valids_2);
+      valids_3 <= ~(_GEN_19 & head == 4'h3) & (_GEN_6 | valids_3);
+      valids_4 <= ~(_GEN_19 & head == 4'h4) & (_GEN_7 | valids_4);
+      valids_5 <= ~(_GEN_19 & head == 4'h5) & (_GEN_8 | valids_5);
+      valids_6 <= ~(_GEN_19 & head == 4'h6) & (_GEN_9 | valids_6);
+      valids_7 <= ~(_GEN_19 & head == 4'h7) & (_GEN_10 | valids_7);
+      valids_8 <= ~(_GEN_19 & head == 4'h8) & (_GEN_11 | valids_8);
+      valids_9 <= ~(_GEN_19 & head == 4'h9) & (_GEN_12 | valids_9);
+      valids_10 <= ~(_GEN_19 & head == 4'hA) & (_GEN_13 | valids_10);
+      valids_11 <= ~(_GEN_19 & head == 4'hB) & (_GEN_14 | valids_11);
+      valids_12 <= ~(_GEN_19 & head == 4'hC) & (_GEN_15 | valids_12);
+      valids_13 <= ~(_GEN_19 & head == 4'hD) & (_GEN_16 | valids_13);
+      valids_14 <= ~(_GEN_19 & head == 4'hE) & (_GEN_17 | valids_14);
+      valids_15 <= ~(_GEN_19 & (&head)) & (_GEN_18 | valids_15);
+      if (_GEN_19)
+        head <= 4'(head + 4'h1);
+      if (_GEN_2)
+        tail <= 4'(tail + 4'h1);
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:26];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h1B; i += 5'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        queue_0_addrNoOffset = {_RANDOM[5'h0], _RANDOM[5'h1][9:0]};
+        queue_0_cnt = _RANDOM[5'h1][19:10];
+        queue_1_addrNoOffset = {_RANDOM[5'h1][31:20], _RANDOM[5'h2][29:0]};
+        queue_1_cnt = {_RANDOM[5'h2][31:30], _RANDOM[5'h3][7:0]};
+        queue_2_addrNoOffset = {_RANDOM[5'h3][31:8], _RANDOM[5'h4][17:0]};
+        queue_2_cnt = _RANDOM[5'h4][27:18];
+        queue_3_addrNoOffset = {_RANDOM[5'h4][31:28], _RANDOM[5'h5], _RANDOM[5'h6][5:0]};
+        queue_3_cnt = _RANDOM[5'h6][15:6];
+        queue_4_addrNoOffset = {_RANDOM[5'h6][31:16], _RANDOM[5'h7][25:0]};
+        queue_4_cnt = {_RANDOM[5'h7][31:26], _RANDOM[5'h8][3:0]};
+        queue_5_addrNoOffset = {_RANDOM[5'h8][31:4], _RANDOM[5'h9][13:0]};
+        queue_5_cnt = _RANDOM[5'h9][23:14];
+        queue_6_addrNoOffset = {_RANDOM[5'h9][31:24], _RANDOM[5'hA], _RANDOM[5'hB][1:0]};
+        queue_6_cnt = _RANDOM[5'hB][11:2];
+        queue_7_addrNoOffset = {_RANDOM[5'hB][31:12], _RANDOM[5'hC][21:0]};
+        queue_7_cnt = _RANDOM[5'hC][31:22];
+        queue_8_addrNoOffset = {_RANDOM[5'hD], _RANDOM[5'hE][9:0]};
+        queue_8_cnt = _RANDOM[5'hE][19:10];
+        queue_9_addrNoOffset = {_RANDOM[5'hE][31:20], _RANDOM[5'hF][29:0]};
+        queue_9_cnt = {_RANDOM[5'hF][31:30], _RANDOM[5'h10][7:0]};
+        queue_10_addrNoOffset = {_RANDOM[5'h10][31:8], _RANDOM[5'h11][17:0]};
+        queue_10_cnt = _RANDOM[5'h11][27:18];
+        queue_11_addrNoOffset =
+          {_RANDOM[5'h11][31:28], _RANDOM[5'h12], _RANDOM[5'h13][5:0]};
+        queue_11_cnt = _RANDOM[5'h13][15:6];
+        queue_12_addrNoOffset = {_RANDOM[5'h13][31:16], _RANDOM[5'h14][25:0]};
+        queue_12_cnt = {_RANDOM[5'h14][31:26], _RANDOM[5'h15][3:0]};
+        queue_13_addrNoOffset = {_RANDOM[5'h15][31:4], _RANDOM[5'h16][13:0]};
+        queue_13_cnt = _RANDOM[5'h16][23:14];
+        queue_14_addrNoOffset =
+          {_RANDOM[5'h16][31:24], _RANDOM[5'h17], _RANDOM[5'h18][1:0]};
+        queue_14_cnt = _RANDOM[5'h18][11:2];
+        queue_15_addrNoOffset = {_RANDOM[5'h18][31:12], _RANDOM[5'h19][21:0]};
+        queue_15_cnt = _RANDOM[5'h19][31:22];
+        valids_0 = _RANDOM[5'h1A][0];
+        valids_1 = _RANDOM[5'h1A][1];
+        valids_2 = _RANDOM[5'h1A][2];
+        valids_3 = _RANDOM[5'h1A][3];
+        valids_4 = _RANDOM[5'h1A][4];
+        valids_5 = _RANDOM[5'h1A][5];
+        valids_6 = _RANDOM[5'h1A][6];
+        valids_7 = _RANDOM[5'h1A][7];
+        valids_8 = _RANDOM[5'h1A][8];
+        valids_9 = _RANDOM[5'h1A][9];
+        valids_10 = _RANDOM[5'h1A][10];
+        valids_11 = _RANDOM[5'h1A][11];
+        valids_12 = _RANDOM[5'h1A][12];
+        valids_13 = _RANDOM[5'h1A][13];
+        valids_14 = _RANDOM[5'h1A][14];
+        valids_15 = _RANDOM[5'h1A][15];
+        head = _RANDOM[5'h1A][19:16];
+        tail = _RANDOM[5'h1A][23:20];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        queue_0_addrNoOffset = 42'h0;
+        queue_0_cnt = 10'h0;
+        queue_1_addrNoOffset = 42'h0;
+        queue_1_cnt = 10'h0;
+        queue_2_addrNoOffset = 42'h0;
+        queue_2_cnt = 10'h0;
+        queue_3_addrNoOffset = 42'h0;
+        queue_3_cnt = 10'h0;
+        queue_4_addrNoOffset = 42'h0;
+        queue_4_cnt = 10'h0;
+        queue_5_addrNoOffset = 42'h0;
+        queue_5_cnt = 10'h0;
+        queue_6_addrNoOffset = 42'h0;
+        queue_6_cnt = 10'h0;
+        queue_7_addrNoOffset = 42'h0;
+        queue_7_cnt = 10'h0;
+        queue_8_addrNoOffset = 42'h0;
+        queue_8_cnt = 10'h0;
+        queue_9_addrNoOffset = 42'h0;
+        queue_9_cnt = 10'h0;
+        queue_10_addrNoOffset = 42'h0;
+        queue_10_cnt = 10'h0;
+        queue_11_addrNoOffset = 42'h0;
+        queue_11_cnt = 10'h0;
+        queue_12_addrNoOffset = 42'h0;
+        queue_12_cnt = 10'h0;
+        queue_13_addrNoOffset = 42'h0;
+        queue_13_cnt = 10'h0;
+        queue_14_addrNoOffset = 42'h0;
+        queue_14_cnt = 10'h0;
+        queue_15_addrNoOffset = 42'h0;
+        queue_15_cnt = 10'h0;
+        valids_0 = 1'h0;
+        valids_1 = 1'h0;
+        valids_2 = 1'h0;
+        valids_3 = 1'h0;
+        valids_4 = 1'h0;
+        valids_5 = 1'h0;
+        valids_6 = 1'h0;
+        valids_7 = 1'h0;
+        valids_8 = 1'h0;
+        valids_9 = 1'h0;
+        valids_10 = 1'h0;
+        valids_11 = 1'h0;
+        valids_12 = 1'h0;
+        valids_13 = 1'h0;
+        valids_14 = 1'h0;
+        valids_15 = 1'h0;
+        head = 4'h0;
+        tail = 4'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_out_valid = outValid;
+  assign io_out_bits = {_GEN[head], 6'h0};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/DelayQueue_1.sv b/flow/designs/src/xiangshan_coupledl2/deps/DelayQueue_1.sv
new file mode 100644
index 0000000000..7733841343
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/DelayQueue_1.sv
@@ -0,0 +1,478 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module DelayQueue_1(
+  input         clock,
+  input         reset,
+  input  [9:0]  io_pfCtrlOfDelayLatency,
+  input         io_in_valid,
+  input  [43:0] io_in_bits,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [49:0] io_out_bits
+);
+
+  reg  [43:0]       queue_0_addrNoOffset;
+  reg  [9:0]        queue_0_cnt;
+  reg  [43:0]       queue_1_addrNoOffset;
+  reg  [9:0]        queue_1_cnt;
+  reg  [43:0]       queue_2_addrNoOffset;
+  reg  [9:0]        queue_2_cnt;
+  reg  [43:0]       queue_3_addrNoOffset;
+  reg  [9:0]        queue_3_cnt;
+  reg  [43:0]       queue_4_addrNoOffset;
+  reg  [9:0]        queue_4_cnt;
+  reg  [43:0]       queue_5_addrNoOffset;
+  reg  [9:0]        queue_5_cnt;
+  reg  [43:0]       queue_6_addrNoOffset;
+  reg  [9:0]        queue_6_cnt;
+  reg  [43:0]       queue_7_addrNoOffset;
+  reg  [9:0]        queue_7_cnt;
+  reg  [43:0]       queue_8_addrNoOffset;
+  reg  [9:0]        queue_8_cnt;
+  reg  [43:0]       queue_9_addrNoOffset;
+  reg  [9:0]        queue_9_cnt;
+  reg  [43:0]       queue_10_addrNoOffset;
+  reg  [9:0]        queue_10_cnt;
+  reg  [43:0]       queue_11_addrNoOffset;
+  reg  [9:0]        queue_11_cnt;
+  reg  [43:0]       queue_12_addrNoOffset;
+  reg  [9:0]        queue_12_cnt;
+  reg  [43:0]       queue_13_addrNoOffset;
+  reg  [9:0]        queue_13_cnt;
+  reg  [43:0]       queue_14_addrNoOffset;
+  reg  [9:0]        queue_14_cnt;
+  reg  [43:0]       queue_15_addrNoOffset;
+  reg  [9:0]        queue_15_cnt;
+  reg               valids_0;
+  reg               valids_1;
+  reg               valids_2;
+  reg               valids_3;
+  reg               valids_4;
+  reg               valids_5;
+  reg               valids_6;
+  reg               valids_7;
+  reg               valids_8;
+  reg               valids_9;
+  reg               valids_10;
+  reg               valids_11;
+  reg               valids_12;
+  reg               valids_13;
+  reg               valids_14;
+  reg               valids_15;
+  reg  [3:0]        head;
+  reg  [3:0]        tail;
+  wire              _full_T = head == tail;
+  wire [15:0][43:0] _GEN =
+    {{queue_15_addrNoOffset},
+     {queue_14_addrNoOffset},
+     {queue_13_addrNoOffset},
+     {queue_12_addrNoOffset},
+     {queue_11_addrNoOffset},
+     {queue_10_addrNoOffset},
+     {queue_9_addrNoOffset},
+     {queue_8_addrNoOffset},
+     {queue_7_addrNoOffset},
+     {queue_6_addrNoOffset},
+     {queue_5_addrNoOffset},
+     {queue_4_addrNoOffset},
+     {queue_3_addrNoOffset},
+     {queue_2_addrNoOffset},
+     {queue_1_addrNoOffset},
+     {queue_0_addrNoOffset}};
+  wire [15:0][9:0]  _GEN_0 =
+    {{queue_15_cnt},
+     {queue_14_cnt},
+     {queue_13_cnt},
+     {queue_12_cnt},
+     {queue_11_cnt},
+     {queue_10_cnt},
+     {queue_9_cnt},
+     {queue_8_cnt},
+     {queue_7_cnt},
+     {queue_6_cnt},
+     {queue_5_cnt},
+     {queue_4_cnt},
+     {queue_3_cnt},
+     {queue_2_cnt},
+     {queue_1_cnt},
+     {queue_0_cnt}};
+  wire [15:0]       _GEN_1 =
+    {{valids_15},
+     {valids_14},
+     {valids_13},
+     {valids_12},
+     {valids_11},
+     {valids_10},
+     {valids_9},
+     {valids_8},
+     {valids_7},
+     {valids_6},
+     {valids_5},
+     {valids_4},
+     {valids_3},
+     {valids_2},
+     {valids_1},
+     {valids_0}};
+  wire              outValid =
+    ~(_full_T & ~valids_15) & _GEN_0[head] == 10'h0 & _GEN_1[head];
+  wire [9:0]        setDqLatency =
+    (|io_pfCtrlOfDelayLatency) ? io_pfCtrlOfDelayLatency : 10'h12C;
+  wire              _GEN_2 = io_in_valid & ~(_full_T & valids_15);
+  wire              _GEN_3 = _GEN_2 & tail == 4'h0;
+  wire              _GEN_4 = _GEN_2 & tail == 4'h1;
+  wire              _GEN_5 = _GEN_2 & tail == 4'h2;
+  wire              _GEN_6 = _GEN_2 & tail == 4'h3;
+  wire              _GEN_7 = _GEN_2 & tail == 4'h4;
+  wire              _GEN_8 = _GEN_2 & tail == 4'h5;
+  wire              _GEN_9 = _GEN_2 & tail == 4'h6;
+  wire              _GEN_10 = _GEN_2 & tail == 4'h7;
+  wire              _GEN_11 = _GEN_2 & tail == 4'h8;
+  wire              _GEN_12 = _GEN_2 & tail == 4'h9;
+  wire              _GEN_13 = _GEN_2 & tail == 4'hA;
+  wire              _GEN_14 = _GEN_2 & tail == 4'hB;
+  wire              _GEN_15 = _GEN_2 & tail == 4'hC;
+  wire              _GEN_16 = _GEN_2 & tail == 4'hD;
+  wire              _GEN_17 = _GEN_2 & tail == 4'hE;
+  wire              _GEN_18 = _GEN_2 & (&tail);
+  wire              _GEN_19 = outValid & io_out_ready;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      queue_0_addrNoOffset <= 44'h0;
+      queue_0_cnt <= 10'h0;
+      queue_1_addrNoOffset <= 44'h0;
+      queue_1_cnt <= 10'h0;
+      queue_2_addrNoOffset <= 44'h0;
+      queue_2_cnt <= 10'h0;
+      queue_3_addrNoOffset <= 44'h0;
+      queue_3_cnt <= 10'h0;
+      queue_4_addrNoOffset <= 44'h0;
+      queue_4_cnt <= 10'h0;
+      queue_5_addrNoOffset <= 44'h0;
+      queue_5_cnt <= 10'h0;
+      queue_6_addrNoOffset <= 44'h0;
+      queue_6_cnt <= 10'h0;
+      queue_7_addrNoOffset <= 44'h0;
+      queue_7_cnt <= 10'h0;
+      queue_8_addrNoOffset <= 44'h0;
+      queue_8_cnt <= 10'h0;
+      queue_9_addrNoOffset <= 44'h0;
+      queue_9_cnt <= 10'h0;
+      queue_10_addrNoOffset <= 44'h0;
+      queue_10_cnt <= 10'h0;
+      queue_11_addrNoOffset <= 44'h0;
+      queue_11_cnt <= 10'h0;
+      queue_12_addrNoOffset <= 44'h0;
+      queue_12_cnt <= 10'h0;
+      queue_13_addrNoOffset <= 44'h0;
+      queue_13_cnt <= 10'h0;
+      queue_14_addrNoOffset <= 44'h0;
+      queue_14_cnt <= 10'h0;
+      queue_15_addrNoOffset <= 44'h0;
+      queue_15_cnt <= 10'h0;
+      valids_0 <= 1'h0;
+      valids_1 <= 1'h0;
+      valids_2 <= 1'h0;
+      valids_3 <= 1'h0;
+      valids_4 <= 1'h0;
+      valids_5 <= 1'h0;
+      valids_6 <= 1'h0;
+      valids_7 <= 1'h0;
+      valids_8 <= 1'h0;
+      valids_9 <= 1'h0;
+      valids_10 <= 1'h0;
+      valids_11 <= 1'h0;
+      valids_12 <= 1'h0;
+      valids_13 <= 1'h0;
+      valids_14 <= 1'h0;
+      valids_15 <= 1'h0;
+      head <= 4'h0;
+      tail <= 4'h0;
+    end
+    else begin
+      if (_GEN_3)
+        queue_0_addrNoOffset <= io_in_bits;
+      if (|queue_0_cnt)
+        queue_0_cnt <= 10'(queue_0_cnt - 10'h1);
+      else if (_GEN_3)
+        queue_0_cnt <= setDqLatency;
+      if (_GEN_4)
+        queue_1_addrNoOffset <= io_in_bits;
+      if (|queue_1_cnt)
+        queue_1_cnt <= 10'(queue_1_cnt - 10'h1);
+      else if (_GEN_4)
+        queue_1_cnt <= setDqLatency;
+      if (_GEN_5)
+        queue_2_addrNoOffset <= io_in_bits;
+      if (|queue_2_cnt)
+        queue_2_cnt <= 10'(queue_2_cnt - 10'h1);
+      else if (_GEN_5)
+        queue_2_cnt <= setDqLatency;
+      if (_GEN_6)
+        queue_3_addrNoOffset <= io_in_bits;
+      if (|queue_3_cnt)
+        queue_3_cnt <= 10'(queue_3_cnt - 10'h1);
+      else if (_GEN_6)
+        queue_3_cnt <= setDqLatency;
+      if (_GEN_7)
+        queue_4_addrNoOffset <= io_in_bits;
+      if (|queue_4_cnt)
+        queue_4_cnt <= 10'(queue_4_cnt - 10'h1);
+      else if (_GEN_7)
+        queue_4_cnt <= setDqLatency;
+      if (_GEN_8)
+        queue_5_addrNoOffset <= io_in_bits;
+      if (|queue_5_cnt)
+        queue_5_cnt <= 10'(queue_5_cnt - 10'h1);
+      else if (_GEN_8)
+        queue_5_cnt <= setDqLatency;
+      if (_GEN_9)
+        queue_6_addrNoOffset <= io_in_bits;
+      if (|queue_6_cnt)
+        queue_6_cnt <= 10'(queue_6_cnt - 10'h1);
+      else if (_GEN_9)
+        queue_6_cnt <= setDqLatency;
+      if (_GEN_10)
+        queue_7_addrNoOffset <= io_in_bits;
+      if (|queue_7_cnt)
+        queue_7_cnt <= 10'(queue_7_cnt - 10'h1);
+      else if (_GEN_10)
+        queue_7_cnt <= setDqLatency;
+      if (_GEN_11)
+        queue_8_addrNoOffset <= io_in_bits;
+      if (|queue_8_cnt)
+        queue_8_cnt <= 10'(queue_8_cnt - 10'h1);
+      else if (_GEN_11)
+        queue_8_cnt <= setDqLatency;
+      if (_GEN_12)
+        queue_9_addrNoOffset <= io_in_bits;
+      if (|queue_9_cnt)
+        queue_9_cnt <= 10'(queue_9_cnt - 10'h1);
+      else if (_GEN_12)
+        queue_9_cnt <= setDqLatency;
+      if (_GEN_13)
+        queue_10_addrNoOffset <= io_in_bits;
+      if (|queue_10_cnt)
+        queue_10_cnt <= 10'(queue_10_cnt - 10'h1);
+      else if (_GEN_13)
+        queue_10_cnt <= setDqLatency;
+      if (_GEN_14)
+        queue_11_addrNoOffset <= io_in_bits;
+      if (|queue_11_cnt)
+        queue_11_cnt <= 10'(queue_11_cnt - 10'h1);
+      else if (_GEN_14)
+        queue_11_cnt <= setDqLatency;
+      if (_GEN_15)
+        queue_12_addrNoOffset <= io_in_bits;
+      if (|queue_12_cnt)
+        queue_12_cnt <= 10'(queue_12_cnt - 10'h1);
+      else if (_GEN_15)
+        queue_12_cnt <= setDqLatency;
+      if (_GEN_16)
+        queue_13_addrNoOffset <= io_in_bits;
+      if (|queue_13_cnt)
+        queue_13_cnt <= 10'(queue_13_cnt - 10'h1);
+      else if (_GEN_16)
+        queue_13_cnt <= setDqLatency;
+      if (_GEN_17)
+        queue_14_addrNoOffset <= io_in_bits;
+      if (|queue_14_cnt)
+        queue_14_cnt <= 10'(queue_14_cnt - 10'h1);
+      else if (_GEN_17)
+        queue_14_cnt <= setDqLatency;
+      if (_GEN_18)
+        queue_15_addrNoOffset <= io_in_bits;
+      if (|queue_15_cnt)
+        queue_15_cnt <= 10'(queue_15_cnt - 10'h1);
+      else if (_GEN_18)
+        queue_15_cnt <= setDqLatency;
+      valids_0 <= ~(_GEN_19 & head == 4'h0) & (_GEN_3 | valids_0);
+      valids_1 <= ~(_GEN_19 & head == 4'h1) & (_GEN_4 | valids_1);
+      valids_2 <= ~(_GEN_19 & head == 4'h2) & (_GEN_5 | valids_2);
+      valids_3 <= ~(_GEN_19 & head == 4'h3) & (_GEN_6 | valids_3);
+      valids_4 <= ~(_GEN_19 & head == 4'h4) & (_GEN_7 | valids_4);
+      valids_5 <= ~(_GEN_19 & head == 4'h5) & (_GEN_8 | valids_5);
+      valids_6 <= ~(_GEN_19 & head == 4'h6) & (_GEN_9 | valids_6);
+      valids_7 <= ~(_GEN_19 & head == 4'h7) & (_GEN_10 | valids_7);
+      valids_8 <= ~(_GEN_19 & head == 4'h8) & (_GEN_11 | valids_8);
+      valids_9 <= ~(_GEN_19 & head == 4'h9) & (_GEN_12 | valids_9);
+      valids_10 <= ~(_GEN_19 & head == 4'hA) & (_GEN_13 | valids_10);
+      valids_11 <= ~(_GEN_19 & head == 4'hB) & (_GEN_14 | valids_11);
+      valids_12 <= ~(_GEN_19 & head == 4'hC) & (_GEN_15 | valids_12);
+      valids_13 <= ~(_GEN_19 & head == 4'hD) & (_GEN_16 | valids_13);
+      valids_14 <= ~(_GEN_19 & head == 4'hE) & (_GEN_17 | valids_14);
+      valids_15 <= ~(_GEN_19 & (&head)) & (_GEN_18 | valids_15);
+      if (_GEN_19)
+        head <= 4'(head + 4'h1);
+      if (_GEN_2)
+        tail <= 4'(tail + 4'h1);
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:27];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h1C; i += 5'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        queue_0_addrNoOffset = {_RANDOM[5'h0], _RANDOM[5'h1][11:0]};
+        queue_0_cnt = _RANDOM[5'h1][21:12];
+        queue_1_addrNoOffset = {_RANDOM[5'h1][31:22], _RANDOM[5'h2], _RANDOM[5'h3][1:0]};
+        queue_1_cnt = _RANDOM[5'h3][11:2];
+        queue_2_addrNoOffset = {_RANDOM[5'h3][31:12], _RANDOM[5'h4][23:0]};
+        queue_2_cnt = {_RANDOM[5'h4][31:24], _RANDOM[5'h5][1:0]};
+        queue_3_addrNoOffset = {_RANDOM[5'h5][31:2], _RANDOM[5'h6][13:0]};
+        queue_3_cnt = _RANDOM[5'h6][23:14];
+        queue_4_addrNoOffset = {_RANDOM[5'h6][31:24], _RANDOM[5'h7], _RANDOM[5'h8][3:0]};
+        queue_4_cnt = _RANDOM[5'h8][13:4];
+        queue_5_addrNoOffset = {_RANDOM[5'h8][31:14], _RANDOM[5'h9][25:0]};
+        queue_5_cnt = {_RANDOM[5'h9][31:26], _RANDOM[5'hA][3:0]};
+        queue_6_addrNoOffset = {_RANDOM[5'hA][31:4], _RANDOM[5'hB][15:0]};
+        queue_6_cnt = _RANDOM[5'hB][25:16];
+        queue_7_addrNoOffset = {_RANDOM[5'hB][31:26], _RANDOM[5'hC], _RANDOM[5'hD][5:0]};
+        queue_7_cnt = _RANDOM[5'hD][15:6];
+        queue_8_addrNoOffset = {_RANDOM[5'hD][31:16], _RANDOM[5'hE][27:0]};
+        queue_8_cnt = {_RANDOM[5'hE][31:28], _RANDOM[5'hF][5:0]};
+        queue_9_addrNoOffset = {_RANDOM[5'hF][31:6], _RANDOM[5'h10][17:0]};
+        queue_9_cnt = _RANDOM[5'h10][27:18];
+        queue_10_addrNoOffset =
+          {_RANDOM[5'h10][31:28], _RANDOM[5'h11], _RANDOM[5'h12][7:0]};
+        queue_10_cnt = _RANDOM[5'h12][17:8];
+        queue_11_addrNoOffset = {_RANDOM[5'h12][31:18], _RANDOM[5'h13][29:0]};
+        queue_11_cnt = {_RANDOM[5'h13][31:30], _RANDOM[5'h14][7:0]};
+        queue_12_addrNoOffset = {_RANDOM[5'h14][31:8], _RANDOM[5'h15][19:0]};
+        queue_12_cnt = _RANDOM[5'h15][29:20];
+        queue_13_addrNoOffset =
+          {_RANDOM[5'h15][31:30], _RANDOM[5'h16], _RANDOM[5'h17][9:0]};
+        queue_13_cnt = _RANDOM[5'h17][19:10];
+        queue_14_addrNoOffset = {_RANDOM[5'h17][31:20], _RANDOM[5'h18]};
+        queue_14_cnt = _RANDOM[5'h19][9:0];
+        queue_15_addrNoOffset = {_RANDOM[5'h19][31:10], _RANDOM[5'h1A][21:0]};
+        queue_15_cnt = _RANDOM[5'h1A][31:22];
+        valids_0 = _RANDOM[5'h1B][0];
+        valids_1 = _RANDOM[5'h1B][1];
+        valids_2 = _RANDOM[5'h1B][2];
+        valids_3 = _RANDOM[5'h1B][3];
+        valids_4 = _RANDOM[5'h1B][4];
+        valids_5 = _RANDOM[5'h1B][5];
+        valids_6 = _RANDOM[5'h1B][6];
+        valids_7 = _RANDOM[5'h1B][7];
+        valids_8 = _RANDOM[5'h1B][8];
+        valids_9 = _RANDOM[5'h1B][9];
+        valids_10 = _RANDOM[5'h1B][10];
+        valids_11 = _RANDOM[5'h1B][11];
+        valids_12 = _RANDOM[5'h1B][12];
+        valids_13 = _RANDOM[5'h1B][13];
+        valids_14 = _RANDOM[5'h1B][14];
+        valids_15 = _RANDOM[5'h1B][15];
+        head = _RANDOM[5'h1B][19:16];
+        tail = _RANDOM[5'h1B][23:20];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        queue_0_addrNoOffset = 44'h0;
+        queue_0_cnt = 10'h0;
+        queue_1_addrNoOffset = 44'h0;
+        queue_1_cnt = 10'h0;
+        queue_2_addrNoOffset = 44'h0;
+        queue_2_cnt = 10'h0;
+        queue_3_addrNoOffset = 44'h0;
+        queue_3_cnt = 10'h0;
+        queue_4_addrNoOffset = 44'h0;
+        queue_4_cnt = 10'h0;
+        queue_5_addrNoOffset = 44'h0;
+        queue_5_cnt = 10'h0;
+        queue_6_addrNoOffset = 44'h0;
+        queue_6_cnt = 10'h0;
+        queue_7_addrNoOffset = 44'h0;
+        queue_7_cnt = 10'h0;
+        queue_8_addrNoOffset = 44'h0;
+        queue_8_cnt = 10'h0;
+        queue_9_addrNoOffset = 44'h0;
+        queue_9_cnt = 10'h0;
+        queue_10_addrNoOffset = 44'h0;
+        queue_10_cnt = 10'h0;
+        queue_11_addrNoOffset = 44'h0;
+        queue_11_cnt = 10'h0;
+        queue_12_addrNoOffset = 44'h0;
+        queue_12_cnt = 10'h0;
+        queue_13_addrNoOffset = 44'h0;
+        queue_13_cnt = 10'h0;
+        queue_14_addrNoOffset = 44'h0;
+        queue_14_cnt = 10'h0;
+        queue_15_addrNoOffset = 44'h0;
+        queue_15_cnt = 10'h0;
+        valids_0 = 1'h0;
+        valids_1 = 1'h0;
+        valids_2 = 1'h0;
+        valids_3 = 1'h0;
+        valids_4 = 1'h0;
+        valids_5 = 1'h0;
+        valids_6 = 1'h0;
+        valids_7 = 1'h0;
+        valids_8 = 1'h0;
+        valids_9 = 1'h0;
+        valids_10 = 1'h0;
+        valids_11 = 1'h0;
+        valids_12 = 1'h0;
+        valids_13 = 1'h0;
+        valids_14 = 1'h0;
+        valids_15 = 1'h0;
+        head = 4'h0;
+        tail = 4'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_out_valid = outValid;
+  assign io_out_bits = {_GEN[head], 6'h0};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Directory.sv b/flow/designs/src/xiangshan_coupledl2/deps/Directory.sv
new file mode 100644
index 0000000000..242b1dab7a
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Directory.sv
@@ -0,0 +1,2718 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Directory(
+  input          clock,
+  input          reset,
+  output         io_read_ready,
+  input          io_read_valid,
+  input  [33:0]  io_read_bits_tag,
+  input  [7:0]   io_read_bits_set,
+  input  [7:0]   io_read_bits_wayMask,
+  input  [2:0]   io_read_bits_replacerInfo_channel,
+  input  [2:0]   io_read_bits_replacerInfo_opcode,
+  input  [4:0]   io_read_bits_replacerInfo_reqSource,
+  input          io_read_bits_replacerInfo_refill_prefetch,
+  input          io_read_bits_refill,
+  input  [7:0]   io_read_bits_mshrId,
+  input          io_read_bits_cmoAll,
+  input  [2:0]   io_read_bits_cmoWay,
+  output         io_resp_valid,
+  output         io_resp_bits_hit,
+  output [33:0]  io_resp_bits_tag,
+  output [7:0]   io_resp_bits_set,
+  output [2:0]   io_resp_bits_way,
+  output         io_resp_bits_meta_dirty,
+  output [1:0]   io_resp_bits_meta_state,
+  output         io_resp_bits_meta_clients,
+  output         io_resp_bits_meta_alias,
+  output         io_resp_bits_meta_prefetch,
+  output [3:0]   io_resp_bits_meta_prefetchSrc,
+  output         io_resp_bits_meta_accessed,
+  output         io_resp_bits_meta_tagErr,
+  output         io_resp_bits_meta_dataErr,
+  output         io_resp_bits_error,
+  output [2:0]   io_resp_bits_replacerInfo_channel,
+  output [2:0]   io_resp_bits_replacerInfo_opcode,
+  output [4:0]   io_resp_bits_replacerInfo_reqSource,
+  output         io_resp_bits_replacerInfo_refill_prefetch,
+  input          io_metaWReq_valid,
+  input  [7:0]   io_metaWReq_bits_set,
+  input  [7:0]   io_metaWReq_bits_wayOH,
+  input          io_metaWReq_bits_wmeta_dirty,
+  input  [1:0]   io_metaWReq_bits_wmeta_state,
+  input          io_metaWReq_bits_wmeta_clients,
+  input          io_metaWReq_bits_wmeta_alias,
+  input          io_metaWReq_bits_wmeta_prefetch,
+  input  [3:0]   io_metaWReq_bits_wmeta_prefetchSrc,
+  input          io_metaWReq_bits_wmeta_accessed,
+  input          io_metaWReq_bits_wmeta_tagErr,
+  input          io_metaWReq_bits_wmeta_dataErr,
+  input          io_tagWReq_valid,
+  input  [7:0]   io_tagWReq_bits_set,
+  input  [7:0]   io_tagWReq_bits_wayOH,
+  input  [33:0]  io_tagWReq_bits_wtag,
+  output         io_replResp_valid,
+  output [33:0]  io_replResp_bits_tag,
+  output [7:0]   io_replResp_bits_set,
+  output [2:0]   io_replResp_bits_way,
+  output         io_replResp_bits_meta_dirty,
+  output [1:0]   io_replResp_bits_meta_state,
+  output         io_replResp_bits_meta_clients,
+  output         io_replResp_bits_meta_alias,
+  output         io_replResp_bits_meta_prefetch,
+  output [3:0]   io_replResp_bits_meta_prefetchSrc,
+  output         io_replResp_bits_meta_accessed,
+  output         io_replResp_bits_meta_tagErr,
+  output         io_replResp_bits_meta_dataErr,
+  output [7:0]   io_replResp_bits_mshrId,
+  output         io_replResp_bits_retry,
+  output         io_replResp_bits_validHold,
+  input          io_msInfo_0_valid,
+  input  [2:0]   io_msInfo_0_bits_channel,
+  input  [7:0]   io_msInfo_0_bits_set,
+  input  [2:0]   io_msInfo_0_bits_way,
+  input  [33:0]  io_msInfo_0_bits_reqTag,
+  input  [4:0]   io_msInfo_0_bits_reqSource,
+  input          io_msInfo_0_bits_willFree,
+  input          io_msInfo_0_bits_aliasTask,
+  input          io_msInfo_0_bits_needRelease,
+  input          io_msInfo_0_bits_blockRefill,
+  input          io_msInfo_0_bits_meta_dirty,
+  input  [1:0]   io_msInfo_0_bits_meta_state,
+  input          io_msInfo_0_bits_meta_clients,
+  input          io_msInfo_0_bits_meta_alias,
+  input          io_msInfo_0_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_0_bits_meta_prefetchSrc,
+  input          io_msInfo_0_bits_meta_accessed,
+  input          io_msInfo_0_bits_meta_tagErr,
+  input          io_msInfo_0_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_0_bits_metaTag,
+  input          io_msInfo_0_bits_dirHit,
+  input          io_msInfo_0_bits_isAcqOrPrefetch,
+  input          io_msInfo_0_bits_isPrefetch,
+  input  [2:0]   io_msInfo_0_bits_param,
+  input          io_msInfo_0_bits_mergeA,
+  input          io_msInfo_0_bits_w_grantfirst,
+  input          io_msInfo_0_bits_w_grantlast,
+  input          io_msInfo_0_bits_w_grant,
+  input          io_msInfo_0_bits_s_release,
+  input          io_msInfo_0_bits_s_refill,
+  input          io_msInfo_0_bits_s_cmoresp,
+  input          io_msInfo_0_bits_s_cmometaw,
+  input          io_msInfo_0_bits_w_releaseack,
+  input          io_msInfo_0_bits_w_replResp,
+  input          io_msInfo_0_bits_w_rprobeacklast,
+  input          io_msInfo_0_bits_replaceData,
+  input          io_msInfo_0_bits_releaseToClean,
+  input          io_msInfo_1_valid,
+  input  [2:0]   io_msInfo_1_bits_channel,
+  input  [7:0]   io_msInfo_1_bits_set,
+  input  [2:0]   io_msInfo_1_bits_way,
+  input  [33:0]  io_msInfo_1_bits_reqTag,
+  input  [4:0]   io_msInfo_1_bits_reqSource,
+  input          io_msInfo_1_bits_willFree,
+  input          io_msInfo_1_bits_aliasTask,
+  input          io_msInfo_1_bits_needRelease,
+  input          io_msInfo_1_bits_blockRefill,
+  input          io_msInfo_1_bits_meta_dirty,
+  input  [1:0]   io_msInfo_1_bits_meta_state,
+  input          io_msInfo_1_bits_meta_clients,
+  input          io_msInfo_1_bits_meta_alias,
+  input          io_msInfo_1_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_1_bits_meta_prefetchSrc,
+  input          io_msInfo_1_bits_meta_accessed,
+  input          io_msInfo_1_bits_meta_tagErr,
+  input          io_msInfo_1_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_1_bits_metaTag,
+  input          io_msInfo_1_bits_dirHit,
+  input          io_msInfo_1_bits_isAcqOrPrefetch,
+  input          io_msInfo_1_bits_isPrefetch,
+  input  [2:0]   io_msInfo_1_bits_param,
+  input          io_msInfo_1_bits_mergeA,
+  input          io_msInfo_1_bits_w_grantfirst,
+  input          io_msInfo_1_bits_w_grantlast,
+  input          io_msInfo_1_bits_w_grant,
+  input          io_msInfo_1_bits_s_release,
+  input          io_msInfo_1_bits_s_refill,
+  input          io_msInfo_1_bits_s_cmoresp,
+  input          io_msInfo_1_bits_s_cmometaw,
+  input          io_msInfo_1_bits_w_releaseack,
+  input          io_msInfo_1_bits_w_replResp,
+  input          io_msInfo_1_bits_w_rprobeacklast,
+  input          io_msInfo_1_bits_replaceData,
+  input          io_msInfo_1_bits_releaseToClean,
+  input          io_msInfo_2_valid,
+  input  [2:0]   io_msInfo_2_bits_channel,
+  input  [7:0]   io_msInfo_2_bits_set,
+  input  [2:0]   io_msInfo_2_bits_way,
+  input  [33:0]  io_msInfo_2_bits_reqTag,
+  input  [4:0]   io_msInfo_2_bits_reqSource,
+  input          io_msInfo_2_bits_willFree,
+  input          io_msInfo_2_bits_aliasTask,
+  input          io_msInfo_2_bits_needRelease,
+  input          io_msInfo_2_bits_blockRefill,
+  input          io_msInfo_2_bits_meta_dirty,
+  input  [1:0]   io_msInfo_2_bits_meta_state,
+  input          io_msInfo_2_bits_meta_clients,
+  input          io_msInfo_2_bits_meta_alias,
+  input          io_msInfo_2_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_2_bits_meta_prefetchSrc,
+  input          io_msInfo_2_bits_meta_accessed,
+  input          io_msInfo_2_bits_meta_tagErr,
+  input          io_msInfo_2_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_2_bits_metaTag,
+  input          io_msInfo_2_bits_dirHit,
+  input          io_msInfo_2_bits_isAcqOrPrefetch,
+  input          io_msInfo_2_bits_isPrefetch,
+  input  [2:0]   io_msInfo_2_bits_param,
+  input          io_msInfo_2_bits_mergeA,
+  input          io_msInfo_2_bits_w_grantfirst,
+  input          io_msInfo_2_bits_w_grantlast,
+  input          io_msInfo_2_bits_w_grant,
+  input          io_msInfo_2_bits_s_release,
+  input          io_msInfo_2_bits_s_refill,
+  input          io_msInfo_2_bits_s_cmoresp,
+  input          io_msInfo_2_bits_s_cmometaw,
+  input          io_msInfo_2_bits_w_releaseack,
+  input          io_msInfo_2_bits_w_replResp,
+  input          io_msInfo_2_bits_w_rprobeacklast,
+  input          io_msInfo_2_bits_replaceData,
+  input          io_msInfo_2_bits_releaseToClean,
+  input          io_msInfo_3_valid,
+  input  [2:0]   io_msInfo_3_bits_channel,
+  input  [7:0]   io_msInfo_3_bits_set,
+  input  [2:0]   io_msInfo_3_bits_way,
+  input  [33:0]  io_msInfo_3_bits_reqTag,
+  input  [4:0]   io_msInfo_3_bits_reqSource,
+  input          io_msInfo_3_bits_willFree,
+  input          io_msInfo_3_bits_aliasTask,
+  input          io_msInfo_3_bits_needRelease,
+  input          io_msInfo_3_bits_blockRefill,
+  input          io_msInfo_3_bits_meta_dirty,
+  input  [1:0]   io_msInfo_3_bits_meta_state,
+  input          io_msInfo_3_bits_meta_clients,
+  input          io_msInfo_3_bits_meta_alias,
+  input          io_msInfo_3_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_3_bits_meta_prefetchSrc,
+  input          io_msInfo_3_bits_meta_accessed,
+  input          io_msInfo_3_bits_meta_tagErr,
+  input          io_msInfo_3_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_3_bits_metaTag,
+  input          io_msInfo_3_bits_dirHit,
+  input          io_msInfo_3_bits_isAcqOrPrefetch,
+  input          io_msInfo_3_bits_isPrefetch,
+  input  [2:0]   io_msInfo_3_bits_param,
+  input          io_msInfo_3_bits_mergeA,
+  input          io_msInfo_3_bits_w_grantfirst,
+  input          io_msInfo_3_bits_w_grantlast,
+  input          io_msInfo_3_bits_w_grant,
+  input          io_msInfo_3_bits_s_release,
+  input          io_msInfo_3_bits_s_refill,
+  input          io_msInfo_3_bits_s_cmoresp,
+  input          io_msInfo_3_bits_s_cmometaw,
+  input          io_msInfo_3_bits_w_releaseack,
+  input          io_msInfo_3_bits_w_replResp,
+  input          io_msInfo_3_bits_w_rprobeacklast,
+  input          io_msInfo_3_bits_replaceData,
+  input          io_msInfo_3_bits_releaseToClean,
+  input          io_msInfo_4_valid,
+  input  [2:0]   io_msInfo_4_bits_channel,
+  input  [7:0]   io_msInfo_4_bits_set,
+  input  [2:0]   io_msInfo_4_bits_way,
+  input  [33:0]  io_msInfo_4_bits_reqTag,
+  input  [4:0]   io_msInfo_4_bits_reqSource,
+  input          io_msInfo_4_bits_willFree,
+  input          io_msInfo_4_bits_aliasTask,
+  input          io_msInfo_4_bits_needRelease,
+  input          io_msInfo_4_bits_blockRefill,
+  input          io_msInfo_4_bits_meta_dirty,
+  input  [1:0]   io_msInfo_4_bits_meta_state,
+  input          io_msInfo_4_bits_meta_clients,
+  input          io_msInfo_4_bits_meta_alias,
+  input          io_msInfo_4_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_4_bits_meta_prefetchSrc,
+  input          io_msInfo_4_bits_meta_accessed,
+  input          io_msInfo_4_bits_meta_tagErr,
+  input          io_msInfo_4_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_4_bits_metaTag,
+  input          io_msInfo_4_bits_dirHit,
+  input          io_msInfo_4_bits_isAcqOrPrefetch,
+  input          io_msInfo_4_bits_isPrefetch,
+  input  [2:0]   io_msInfo_4_bits_param,
+  input          io_msInfo_4_bits_mergeA,
+  input          io_msInfo_4_bits_w_grantfirst,
+  input          io_msInfo_4_bits_w_grantlast,
+  input          io_msInfo_4_bits_w_grant,
+  input          io_msInfo_4_bits_s_release,
+  input          io_msInfo_4_bits_s_refill,
+  input          io_msInfo_4_bits_s_cmoresp,
+  input          io_msInfo_4_bits_s_cmometaw,
+  input          io_msInfo_4_bits_w_releaseack,
+  input          io_msInfo_4_bits_w_replResp,
+  input          io_msInfo_4_bits_w_rprobeacklast,
+  input          io_msInfo_4_bits_replaceData,
+  input          io_msInfo_4_bits_releaseToClean,
+  input          io_msInfo_5_valid,
+  input  [2:0]   io_msInfo_5_bits_channel,
+  input  [7:0]   io_msInfo_5_bits_set,
+  input  [2:0]   io_msInfo_5_bits_way,
+  input  [33:0]  io_msInfo_5_bits_reqTag,
+  input  [4:0]   io_msInfo_5_bits_reqSource,
+  input          io_msInfo_5_bits_willFree,
+  input          io_msInfo_5_bits_aliasTask,
+  input          io_msInfo_5_bits_needRelease,
+  input          io_msInfo_5_bits_blockRefill,
+  input          io_msInfo_5_bits_meta_dirty,
+  input  [1:0]   io_msInfo_5_bits_meta_state,
+  input          io_msInfo_5_bits_meta_clients,
+  input          io_msInfo_5_bits_meta_alias,
+  input          io_msInfo_5_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_5_bits_meta_prefetchSrc,
+  input          io_msInfo_5_bits_meta_accessed,
+  input          io_msInfo_5_bits_meta_tagErr,
+  input          io_msInfo_5_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_5_bits_metaTag,
+  input          io_msInfo_5_bits_dirHit,
+  input          io_msInfo_5_bits_isAcqOrPrefetch,
+  input          io_msInfo_5_bits_isPrefetch,
+  input  [2:0]   io_msInfo_5_bits_param,
+  input          io_msInfo_5_bits_mergeA,
+  input          io_msInfo_5_bits_w_grantfirst,
+  input          io_msInfo_5_bits_w_grantlast,
+  input          io_msInfo_5_bits_w_grant,
+  input          io_msInfo_5_bits_s_release,
+  input          io_msInfo_5_bits_s_refill,
+  input          io_msInfo_5_bits_s_cmoresp,
+  input          io_msInfo_5_bits_s_cmometaw,
+  input          io_msInfo_5_bits_w_releaseack,
+  input          io_msInfo_5_bits_w_replResp,
+  input          io_msInfo_5_bits_w_rprobeacklast,
+  input          io_msInfo_5_bits_replaceData,
+  input          io_msInfo_5_bits_releaseToClean,
+  input          io_msInfo_6_valid,
+  input  [2:0]   io_msInfo_6_bits_channel,
+  input  [7:0]   io_msInfo_6_bits_set,
+  input  [2:0]   io_msInfo_6_bits_way,
+  input  [33:0]  io_msInfo_6_bits_reqTag,
+  input  [4:0]   io_msInfo_6_bits_reqSource,
+  input          io_msInfo_6_bits_willFree,
+  input          io_msInfo_6_bits_aliasTask,
+  input          io_msInfo_6_bits_needRelease,
+  input          io_msInfo_6_bits_blockRefill,
+  input          io_msInfo_6_bits_meta_dirty,
+  input  [1:0]   io_msInfo_6_bits_meta_state,
+  input          io_msInfo_6_bits_meta_clients,
+  input          io_msInfo_6_bits_meta_alias,
+  input          io_msInfo_6_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_6_bits_meta_prefetchSrc,
+  input          io_msInfo_6_bits_meta_accessed,
+  input          io_msInfo_6_bits_meta_tagErr,
+  input          io_msInfo_6_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_6_bits_metaTag,
+  input          io_msInfo_6_bits_dirHit,
+  input          io_msInfo_6_bits_isAcqOrPrefetch,
+  input          io_msInfo_6_bits_isPrefetch,
+  input  [2:0]   io_msInfo_6_bits_param,
+  input          io_msInfo_6_bits_mergeA,
+  input          io_msInfo_6_bits_w_grantfirst,
+  input          io_msInfo_6_bits_w_grantlast,
+  input          io_msInfo_6_bits_w_grant,
+  input          io_msInfo_6_bits_s_release,
+  input          io_msInfo_6_bits_s_refill,
+  input          io_msInfo_6_bits_s_cmoresp,
+  input          io_msInfo_6_bits_s_cmometaw,
+  input          io_msInfo_6_bits_w_releaseack,
+  input          io_msInfo_6_bits_w_replResp,
+  input          io_msInfo_6_bits_w_rprobeacklast,
+  input          io_msInfo_6_bits_replaceData,
+  input          io_msInfo_6_bits_releaseToClean,
+  input          io_msInfo_7_valid,
+  input  [2:0]   io_msInfo_7_bits_channel,
+  input  [7:0]   io_msInfo_7_bits_set,
+  input  [2:0]   io_msInfo_7_bits_way,
+  input  [33:0]  io_msInfo_7_bits_reqTag,
+  input  [4:0]   io_msInfo_7_bits_reqSource,
+  input          io_msInfo_7_bits_willFree,
+  input          io_msInfo_7_bits_aliasTask,
+  input          io_msInfo_7_bits_needRelease,
+  input          io_msInfo_7_bits_blockRefill,
+  input          io_msInfo_7_bits_meta_dirty,
+  input  [1:0]   io_msInfo_7_bits_meta_state,
+  input          io_msInfo_7_bits_meta_clients,
+  input          io_msInfo_7_bits_meta_alias,
+  input          io_msInfo_7_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_7_bits_meta_prefetchSrc,
+  input          io_msInfo_7_bits_meta_accessed,
+  input          io_msInfo_7_bits_meta_tagErr,
+  input          io_msInfo_7_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_7_bits_metaTag,
+  input          io_msInfo_7_bits_dirHit,
+  input          io_msInfo_7_bits_isAcqOrPrefetch,
+  input          io_msInfo_7_bits_isPrefetch,
+  input  [2:0]   io_msInfo_7_bits_param,
+  input          io_msInfo_7_bits_mergeA,
+  input          io_msInfo_7_bits_w_grantfirst,
+  input          io_msInfo_7_bits_w_grantlast,
+  input          io_msInfo_7_bits_w_grant,
+  input          io_msInfo_7_bits_s_release,
+  input          io_msInfo_7_bits_s_refill,
+  input          io_msInfo_7_bits_s_cmoresp,
+  input          io_msInfo_7_bits_s_cmometaw,
+  input          io_msInfo_7_bits_w_releaseack,
+  input          io_msInfo_7_bits_w_replResp,
+  input          io_msInfo_7_bits_w_rprobeacklast,
+  input          io_msInfo_7_bits_replaceData,
+  input          io_msInfo_7_bits_releaseToClean,
+  input          io_msInfo_8_valid,
+  input  [2:0]   io_msInfo_8_bits_channel,
+  input  [7:0]   io_msInfo_8_bits_set,
+  input  [2:0]   io_msInfo_8_bits_way,
+  input  [33:0]  io_msInfo_8_bits_reqTag,
+  input  [4:0]   io_msInfo_8_bits_reqSource,
+  input          io_msInfo_8_bits_willFree,
+  input          io_msInfo_8_bits_aliasTask,
+  input          io_msInfo_8_bits_needRelease,
+  input          io_msInfo_8_bits_blockRefill,
+  input          io_msInfo_8_bits_meta_dirty,
+  input  [1:0]   io_msInfo_8_bits_meta_state,
+  input          io_msInfo_8_bits_meta_clients,
+  input          io_msInfo_8_bits_meta_alias,
+  input          io_msInfo_8_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_8_bits_meta_prefetchSrc,
+  input          io_msInfo_8_bits_meta_accessed,
+  input          io_msInfo_8_bits_meta_tagErr,
+  input          io_msInfo_8_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_8_bits_metaTag,
+  input          io_msInfo_8_bits_dirHit,
+  input          io_msInfo_8_bits_isAcqOrPrefetch,
+  input          io_msInfo_8_bits_isPrefetch,
+  input  [2:0]   io_msInfo_8_bits_param,
+  input          io_msInfo_8_bits_mergeA,
+  input          io_msInfo_8_bits_w_grantfirst,
+  input          io_msInfo_8_bits_w_grantlast,
+  input          io_msInfo_8_bits_w_grant,
+  input          io_msInfo_8_bits_s_release,
+  input          io_msInfo_8_bits_s_refill,
+  input          io_msInfo_8_bits_s_cmoresp,
+  input          io_msInfo_8_bits_s_cmometaw,
+  input          io_msInfo_8_bits_w_releaseack,
+  input          io_msInfo_8_bits_w_replResp,
+  input          io_msInfo_8_bits_w_rprobeacklast,
+  input          io_msInfo_8_bits_replaceData,
+  input          io_msInfo_8_bits_releaseToClean,
+  input          io_msInfo_9_valid,
+  input  [2:0]   io_msInfo_9_bits_channel,
+  input  [7:0]   io_msInfo_9_bits_set,
+  input  [2:0]   io_msInfo_9_bits_way,
+  input  [33:0]  io_msInfo_9_bits_reqTag,
+  input  [4:0]   io_msInfo_9_bits_reqSource,
+  input          io_msInfo_9_bits_willFree,
+  input          io_msInfo_9_bits_aliasTask,
+  input          io_msInfo_9_bits_needRelease,
+  input          io_msInfo_9_bits_blockRefill,
+  input          io_msInfo_9_bits_meta_dirty,
+  input  [1:0]   io_msInfo_9_bits_meta_state,
+  input          io_msInfo_9_bits_meta_clients,
+  input          io_msInfo_9_bits_meta_alias,
+  input          io_msInfo_9_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_9_bits_meta_prefetchSrc,
+  input          io_msInfo_9_bits_meta_accessed,
+  input          io_msInfo_9_bits_meta_tagErr,
+  input          io_msInfo_9_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_9_bits_metaTag,
+  input          io_msInfo_9_bits_dirHit,
+  input          io_msInfo_9_bits_isAcqOrPrefetch,
+  input          io_msInfo_9_bits_isPrefetch,
+  input  [2:0]   io_msInfo_9_bits_param,
+  input          io_msInfo_9_bits_mergeA,
+  input          io_msInfo_9_bits_w_grantfirst,
+  input          io_msInfo_9_bits_w_grantlast,
+  input          io_msInfo_9_bits_w_grant,
+  input          io_msInfo_9_bits_s_release,
+  input          io_msInfo_9_bits_s_refill,
+  input          io_msInfo_9_bits_s_cmoresp,
+  input          io_msInfo_9_bits_s_cmometaw,
+  input          io_msInfo_9_bits_w_releaseack,
+  input          io_msInfo_9_bits_w_replResp,
+  input          io_msInfo_9_bits_w_rprobeacklast,
+  input          io_msInfo_9_bits_replaceData,
+  input          io_msInfo_9_bits_releaseToClean,
+  input          io_msInfo_10_valid,
+  input  [2:0]   io_msInfo_10_bits_channel,
+  input  [7:0]   io_msInfo_10_bits_set,
+  input  [2:0]   io_msInfo_10_bits_way,
+  input  [33:0]  io_msInfo_10_bits_reqTag,
+  input  [4:0]   io_msInfo_10_bits_reqSource,
+  input          io_msInfo_10_bits_willFree,
+  input          io_msInfo_10_bits_aliasTask,
+  input          io_msInfo_10_bits_needRelease,
+  input          io_msInfo_10_bits_blockRefill,
+  input          io_msInfo_10_bits_meta_dirty,
+  input  [1:0]   io_msInfo_10_bits_meta_state,
+  input          io_msInfo_10_bits_meta_clients,
+  input          io_msInfo_10_bits_meta_alias,
+  input          io_msInfo_10_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_10_bits_meta_prefetchSrc,
+  input          io_msInfo_10_bits_meta_accessed,
+  input          io_msInfo_10_bits_meta_tagErr,
+  input          io_msInfo_10_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_10_bits_metaTag,
+  input          io_msInfo_10_bits_dirHit,
+  input          io_msInfo_10_bits_isAcqOrPrefetch,
+  input          io_msInfo_10_bits_isPrefetch,
+  input  [2:0]   io_msInfo_10_bits_param,
+  input          io_msInfo_10_bits_mergeA,
+  input          io_msInfo_10_bits_w_grantfirst,
+  input          io_msInfo_10_bits_w_grantlast,
+  input          io_msInfo_10_bits_w_grant,
+  input          io_msInfo_10_bits_s_release,
+  input          io_msInfo_10_bits_s_refill,
+  input          io_msInfo_10_bits_s_cmoresp,
+  input          io_msInfo_10_bits_s_cmometaw,
+  input          io_msInfo_10_bits_w_releaseack,
+  input          io_msInfo_10_bits_w_replResp,
+  input          io_msInfo_10_bits_w_rprobeacklast,
+  input          io_msInfo_10_bits_replaceData,
+  input          io_msInfo_10_bits_releaseToClean,
+  input          io_msInfo_11_valid,
+  input  [2:0]   io_msInfo_11_bits_channel,
+  input  [7:0]   io_msInfo_11_bits_set,
+  input  [2:0]   io_msInfo_11_bits_way,
+  input  [33:0]  io_msInfo_11_bits_reqTag,
+  input  [4:0]   io_msInfo_11_bits_reqSource,
+  input          io_msInfo_11_bits_willFree,
+  input          io_msInfo_11_bits_aliasTask,
+  input          io_msInfo_11_bits_needRelease,
+  input          io_msInfo_11_bits_blockRefill,
+  input          io_msInfo_11_bits_meta_dirty,
+  input  [1:0]   io_msInfo_11_bits_meta_state,
+  input          io_msInfo_11_bits_meta_clients,
+  input          io_msInfo_11_bits_meta_alias,
+  input          io_msInfo_11_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_11_bits_meta_prefetchSrc,
+  input          io_msInfo_11_bits_meta_accessed,
+  input          io_msInfo_11_bits_meta_tagErr,
+  input          io_msInfo_11_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_11_bits_metaTag,
+  input          io_msInfo_11_bits_dirHit,
+  input          io_msInfo_11_bits_isAcqOrPrefetch,
+  input          io_msInfo_11_bits_isPrefetch,
+  input  [2:0]   io_msInfo_11_bits_param,
+  input          io_msInfo_11_bits_mergeA,
+  input          io_msInfo_11_bits_w_grantfirst,
+  input          io_msInfo_11_bits_w_grantlast,
+  input          io_msInfo_11_bits_w_grant,
+  input          io_msInfo_11_bits_s_release,
+  input          io_msInfo_11_bits_s_refill,
+  input          io_msInfo_11_bits_s_cmoresp,
+  input          io_msInfo_11_bits_s_cmometaw,
+  input          io_msInfo_11_bits_w_releaseack,
+  input          io_msInfo_11_bits_w_replResp,
+  input          io_msInfo_11_bits_w_rprobeacklast,
+  input          io_msInfo_11_bits_replaceData,
+  input          io_msInfo_11_bits_releaseToClean,
+  input          io_msInfo_12_valid,
+  input  [2:0]   io_msInfo_12_bits_channel,
+  input  [7:0]   io_msInfo_12_bits_set,
+  input  [2:0]   io_msInfo_12_bits_way,
+  input  [33:0]  io_msInfo_12_bits_reqTag,
+  input  [4:0]   io_msInfo_12_bits_reqSource,
+  input          io_msInfo_12_bits_willFree,
+  input          io_msInfo_12_bits_aliasTask,
+  input          io_msInfo_12_bits_needRelease,
+  input          io_msInfo_12_bits_blockRefill,
+  input          io_msInfo_12_bits_meta_dirty,
+  input  [1:0]   io_msInfo_12_bits_meta_state,
+  input          io_msInfo_12_bits_meta_clients,
+  input          io_msInfo_12_bits_meta_alias,
+  input          io_msInfo_12_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_12_bits_meta_prefetchSrc,
+  input          io_msInfo_12_bits_meta_accessed,
+  input          io_msInfo_12_bits_meta_tagErr,
+  input          io_msInfo_12_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_12_bits_metaTag,
+  input          io_msInfo_12_bits_dirHit,
+  input          io_msInfo_12_bits_isAcqOrPrefetch,
+  input          io_msInfo_12_bits_isPrefetch,
+  input  [2:0]   io_msInfo_12_bits_param,
+  input          io_msInfo_12_bits_mergeA,
+  input          io_msInfo_12_bits_w_grantfirst,
+  input          io_msInfo_12_bits_w_grantlast,
+  input          io_msInfo_12_bits_w_grant,
+  input          io_msInfo_12_bits_s_release,
+  input          io_msInfo_12_bits_s_refill,
+  input          io_msInfo_12_bits_s_cmoresp,
+  input          io_msInfo_12_bits_s_cmometaw,
+  input          io_msInfo_12_bits_w_releaseack,
+  input          io_msInfo_12_bits_w_replResp,
+  input          io_msInfo_12_bits_w_rprobeacklast,
+  input          io_msInfo_12_bits_replaceData,
+  input          io_msInfo_12_bits_releaseToClean,
+  input          io_msInfo_13_valid,
+  input  [2:0]   io_msInfo_13_bits_channel,
+  input  [7:0]   io_msInfo_13_bits_set,
+  input  [2:0]   io_msInfo_13_bits_way,
+  input  [33:0]  io_msInfo_13_bits_reqTag,
+  input  [4:0]   io_msInfo_13_bits_reqSource,
+  input          io_msInfo_13_bits_willFree,
+  input          io_msInfo_13_bits_aliasTask,
+  input          io_msInfo_13_bits_needRelease,
+  input          io_msInfo_13_bits_blockRefill,
+  input          io_msInfo_13_bits_meta_dirty,
+  input  [1:0]   io_msInfo_13_bits_meta_state,
+  input          io_msInfo_13_bits_meta_clients,
+  input          io_msInfo_13_bits_meta_alias,
+  input          io_msInfo_13_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_13_bits_meta_prefetchSrc,
+  input          io_msInfo_13_bits_meta_accessed,
+  input          io_msInfo_13_bits_meta_tagErr,
+  input          io_msInfo_13_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_13_bits_metaTag,
+  input          io_msInfo_13_bits_dirHit,
+  input          io_msInfo_13_bits_isAcqOrPrefetch,
+  input          io_msInfo_13_bits_isPrefetch,
+  input  [2:0]   io_msInfo_13_bits_param,
+  input          io_msInfo_13_bits_mergeA,
+  input          io_msInfo_13_bits_w_grantfirst,
+  input          io_msInfo_13_bits_w_grantlast,
+  input          io_msInfo_13_bits_w_grant,
+  input          io_msInfo_13_bits_s_release,
+  input          io_msInfo_13_bits_s_refill,
+  input          io_msInfo_13_bits_s_cmoresp,
+  input          io_msInfo_13_bits_s_cmometaw,
+  input          io_msInfo_13_bits_w_releaseack,
+  input          io_msInfo_13_bits_w_replResp,
+  input          io_msInfo_13_bits_w_rprobeacklast,
+  input          io_msInfo_13_bits_replaceData,
+  input          io_msInfo_13_bits_releaseToClean,
+  input          io_msInfo_14_valid,
+  input  [2:0]   io_msInfo_14_bits_channel,
+  input  [7:0]   io_msInfo_14_bits_set,
+  input  [2:0]   io_msInfo_14_bits_way,
+  input  [33:0]  io_msInfo_14_bits_reqTag,
+  input  [4:0]   io_msInfo_14_bits_reqSource,
+  input          io_msInfo_14_bits_willFree,
+  input          io_msInfo_14_bits_aliasTask,
+  input          io_msInfo_14_bits_needRelease,
+  input          io_msInfo_14_bits_blockRefill,
+  input          io_msInfo_14_bits_meta_dirty,
+  input  [1:0]   io_msInfo_14_bits_meta_state,
+  input          io_msInfo_14_bits_meta_clients,
+  input          io_msInfo_14_bits_meta_alias,
+  input          io_msInfo_14_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_14_bits_meta_prefetchSrc,
+  input          io_msInfo_14_bits_meta_accessed,
+  input          io_msInfo_14_bits_meta_tagErr,
+  input          io_msInfo_14_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_14_bits_metaTag,
+  input          io_msInfo_14_bits_dirHit,
+  input          io_msInfo_14_bits_isAcqOrPrefetch,
+  input          io_msInfo_14_bits_isPrefetch,
+  input  [2:0]   io_msInfo_14_bits_param,
+  input          io_msInfo_14_bits_mergeA,
+  input          io_msInfo_14_bits_w_grantfirst,
+  input          io_msInfo_14_bits_w_grantlast,
+  input          io_msInfo_14_bits_w_grant,
+  input          io_msInfo_14_bits_s_release,
+  input          io_msInfo_14_bits_s_refill,
+  input          io_msInfo_14_bits_s_cmoresp,
+  input          io_msInfo_14_bits_s_cmometaw,
+  input          io_msInfo_14_bits_w_releaseack,
+  input          io_msInfo_14_bits_w_replResp,
+  input          io_msInfo_14_bits_w_rprobeacklast,
+  input          io_msInfo_14_bits_replaceData,
+  input          io_msInfo_14_bits_releaseToClean,
+  input          io_msInfo_15_valid,
+  input  [2:0]   io_msInfo_15_bits_channel,
+  input  [7:0]   io_msInfo_15_bits_set,
+  input  [2:0]   io_msInfo_15_bits_way,
+  input  [33:0]  io_msInfo_15_bits_reqTag,
+  input  [4:0]   io_msInfo_15_bits_reqSource,
+  input          io_msInfo_15_bits_willFree,
+  input          io_msInfo_15_bits_aliasTask,
+  input          io_msInfo_15_bits_needRelease,
+  input          io_msInfo_15_bits_blockRefill,
+  input          io_msInfo_15_bits_meta_dirty,
+  input  [1:0]   io_msInfo_15_bits_meta_state,
+  input          io_msInfo_15_bits_meta_clients,
+  input          io_msInfo_15_bits_meta_alias,
+  input          io_msInfo_15_bits_meta_prefetch,
+  input  [3:0]   io_msInfo_15_bits_meta_prefetchSrc,
+  input          io_msInfo_15_bits_meta_accessed,
+  input          io_msInfo_15_bits_meta_tagErr,
+  input          io_msInfo_15_bits_meta_dataErr,
+  input  [33:0]  io_msInfo_15_bits_metaTag,
+  input          io_msInfo_15_bits_dirHit,
+  input          io_msInfo_15_bits_isAcqOrPrefetch,
+  input          io_msInfo_15_bits_isPrefetch,
+  input  [2:0]   io_msInfo_15_bits_param,
+  input          io_msInfo_15_bits_mergeA,
+  input          io_msInfo_15_bits_w_grantfirst,
+  input          io_msInfo_15_bits_w_grantlast,
+  input          io_msInfo_15_bits_w_grant,
+  input          io_msInfo_15_bits_s_release,
+  input          io_msInfo_15_bits_s_refill,
+  input          io_msInfo_15_bits_s_cmoresp,
+  input          io_msInfo_15_bits_s_cmometaw,
+  input          io_msInfo_15_bits_w_releaseack,
+  input          io_msInfo_15_bits_w_replResp,
+  input          io_msInfo_15_bits_w_rprobeacklast,
+  input          io_msInfo_15_bits_replaceData,
+  input          io_msInfo_15_bits_releaseToClean,
+  output         io_metaOnHit_dirty,
+  output [1:0]   io_metaOnHit_state,
+  output         io_metaOnHit_clients,
+  output         io_metaOnHit_alias,
+  output         io_metaOnHit_prefetch,
+  output [3:0]   io_metaOnHit_prefetchSrc,
+  output         io_metaOnHit_accessed,
+  output         io_metaOnHit_tagErr,
+  output         io_metaOnHit_dataErr,
+  output         io_errOnSnp,
+  output [7:0]   io_wayOH,
+  output [7:0]   io_replWayOH,
+  output         io_cmoHitInvalid,
+  output         io_retryFastFwd,
+  input  [2:0]   boreChildrenBd_bore_array,
+  input          boreChildrenBd_bore_all,
+  input          boreChildrenBd_bore_req,
+  output         boreChildrenBd_bore_ack,
+  input          boreChildrenBd_bore_writeen,
+  input  [7:0]   boreChildrenBd_bore_be,
+  input  [8:0]   boreChildrenBd_bore_addr,
+  input  [163:0] boreChildrenBd_bore_indata,
+  input          boreChildrenBd_bore_readen,
+  input  [8:0]   boreChildrenBd_bore_addr_rd,
+  output [163:0] boreChildrenBd_bore_outdata,
+  input          sigFromSrams_bore_ram_hold,
+  input          sigFromSrams_bore_ram_bypass,
+  input          sigFromSrams_bore_ram_bp_clken,
+  input          sigFromSrams_bore_ram_aux_clk,
+  input          sigFromSrams_bore_ram_aux_ckbp,
+  input          sigFromSrams_bore_ram_mcp_hold,
+  input          sigFromSrams_bore_cgen,
+  input          sigFromSrams_bore_1_ram_hold,
+  input          sigFromSrams_bore_1_ram_bypass,
+  input          sigFromSrams_bore_1_ram_bp_clken,
+  input          sigFromSrams_bore_1_ram_aux_clk,
+  input          sigFromSrams_bore_1_ram_aux_ckbp,
+  input          sigFromSrams_bore_1_ram_mcp_hold,
+  input          sigFromSrams_bore_1_cgen,
+  input          sigFromSrams_bore_2_ram_hold,
+  input          sigFromSrams_bore_2_ram_bypass,
+  input          sigFromSrams_bore_2_ram_bp_clken,
+  input          sigFromSrams_bore_2_ram_aux_clk,
+  input          sigFromSrams_bore_2_ram_aux_ckbp,
+  input          sigFromSrams_bore_2_ram_mcp_hold,
+  input          sigFromSrams_bore_2_cgen,
+  input          sigFromSrams_bore_3_ram_hold,
+  input          sigFromSrams_bore_3_ram_bypass,
+  input          sigFromSrams_bore_3_ram_bp_clken,
+  input          sigFromSrams_bore_3_ram_aux_clk,
+  input          sigFromSrams_bore_3_ram_aux_ckbp,
+  input          sigFromSrams_bore_3_ram_mcp_hold,
+  input          sigFromSrams_bore_3_cgen,
+  input          sigFromSrams_bore_4_ram_hold,
+  input          sigFromSrams_bore_4_ram_bypass,
+  input          sigFromSrams_bore_4_ram_bp_clken,
+  input          sigFromSrams_bore_4_ram_aux_clk,
+  input          sigFromSrams_bore_4_ram_aux_ckbp,
+  input          sigFromSrams_bore_4_ram_mcp_hold,
+  input          sigFromSrams_bore_4_cgen
+);
+
+  wire [163:0] bd_outdata;
+  wire         bd_ack;
+  wire [7:0]   childBd_4_rdata;
+  wire [15:0]  childBd_3_rdata;
+  wire [103:0] childBd_2_rdata;
+  wire [163:0] childBd_1_rdata;
+  wire [163:0] childBd_rdata;
+  wire         replacerWen;
+  wire [7:0]   replaceOH;
+  wire         io_read_ready_0;
+  wire         _origin_bit_opt_io_r_resp_data_0;
+  wire         _origin_bit_opt_io_r_resp_data_1;
+  wire         _origin_bit_opt_io_r_resp_data_2;
+  wire         _origin_bit_opt_io_r_resp_data_3;
+  wire         _origin_bit_opt_io_r_resp_data_4;
+  wire         _origin_bit_opt_io_r_resp_data_5;
+  wire         _origin_bit_opt_io_r_resp_data_6;
+  wire         _origin_bit_opt_io_r_resp_data_7;
+  wire [15:0]  _replacer_sram_opt_io_r_resp_data_0;
+  wire         _metaArray_io_r_resp_data_0_dirty;
+  wire [1:0]   _metaArray_io_r_resp_data_0_state;
+  wire         _metaArray_io_r_resp_data_0_clients;
+  wire         _metaArray_io_r_resp_data_0_alias;
+  wire         _metaArray_io_r_resp_data_0_prefetch;
+  wire [3:0]   _metaArray_io_r_resp_data_0_prefetchSrc;
+  wire         _metaArray_io_r_resp_data_0_accessed;
+  wire         _metaArray_io_r_resp_data_0_tagErr;
+  wire         _metaArray_io_r_resp_data_0_dataErr;
+  wire         _metaArray_io_r_resp_data_1_dirty;
+  wire [1:0]   _metaArray_io_r_resp_data_1_state;
+  wire         _metaArray_io_r_resp_data_1_clients;
+  wire         _metaArray_io_r_resp_data_1_alias;
+  wire         _metaArray_io_r_resp_data_1_prefetch;
+  wire [3:0]   _metaArray_io_r_resp_data_1_prefetchSrc;
+  wire         _metaArray_io_r_resp_data_1_accessed;
+  wire         _metaArray_io_r_resp_data_1_tagErr;
+  wire         _metaArray_io_r_resp_data_1_dataErr;
+  wire         _metaArray_io_r_resp_data_2_dirty;
+  wire [1:0]   _metaArray_io_r_resp_data_2_state;
+  wire         _metaArray_io_r_resp_data_2_clients;
+  wire         _metaArray_io_r_resp_data_2_alias;
+  wire         _metaArray_io_r_resp_data_2_prefetch;
+  wire [3:0]   _metaArray_io_r_resp_data_2_prefetchSrc;
+  wire         _metaArray_io_r_resp_data_2_accessed;
+  wire         _metaArray_io_r_resp_data_2_tagErr;
+  wire         _metaArray_io_r_resp_data_2_dataErr;
+  wire         _metaArray_io_r_resp_data_3_dirty;
+  wire [1:0]   _metaArray_io_r_resp_data_3_state;
+  wire         _metaArray_io_r_resp_data_3_clients;
+  wire         _metaArray_io_r_resp_data_3_alias;
+  wire         _metaArray_io_r_resp_data_3_prefetch;
+  wire [3:0]   _metaArray_io_r_resp_data_3_prefetchSrc;
+  wire         _metaArray_io_r_resp_data_3_accessed;
+  wire         _metaArray_io_r_resp_data_3_tagErr;
+  wire         _metaArray_io_r_resp_data_3_dataErr;
+  wire         _metaArray_io_r_resp_data_4_dirty;
+  wire [1:0]   _metaArray_io_r_resp_data_4_state;
+  wire         _metaArray_io_r_resp_data_4_clients;
+  wire         _metaArray_io_r_resp_data_4_alias;
+  wire         _metaArray_io_r_resp_data_4_prefetch;
+  wire [3:0]   _metaArray_io_r_resp_data_4_prefetchSrc;
+  wire         _metaArray_io_r_resp_data_4_accessed;
+  wire         _metaArray_io_r_resp_data_4_tagErr;
+  wire         _metaArray_io_r_resp_data_4_dataErr;
+  wire         _metaArray_io_r_resp_data_5_dirty;
+  wire [1:0]   _metaArray_io_r_resp_data_5_state;
+  wire         _metaArray_io_r_resp_data_5_clients;
+  wire         _metaArray_io_r_resp_data_5_alias;
+  wire         _metaArray_io_r_resp_data_5_prefetch;
+  wire [3:0]   _metaArray_io_r_resp_data_5_prefetchSrc;
+  wire         _metaArray_io_r_resp_data_5_accessed;
+  wire         _metaArray_io_r_resp_data_5_tagErr;
+  wire         _metaArray_io_r_resp_data_5_dataErr;
+  wire         _metaArray_io_r_resp_data_6_dirty;
+  wire [1:0]   _metaArray_io_r_resp_data_6_state;
+  wire         _metaArray_io_r_resp_data_6_clients;
+  wire         _metaArray_io_r_resp_data_6_alias;
+  wire         _metaArray_io_r_resp_data_6_prefetch;
+  wire [3:0]   _metaArray_io_r_resp_data_6_prefetchSrc;
+  wire         _metaArray_io_r_resp_data_6_accessed;
+  wire         _metaArray_io_r_resp_data_6_tagErr;
+  wire         _metaArray_io_r_resp_data_6_dataErr;
+  wire         _metaArray_io_r_resp_data_7_dirty;
+  wire [1:0]   _metaArray_io_r_resp_data_7_state;
+  wire         _metaArray_io_r_resp_data_7_clients;
+  wire         _metaArray_io_r_resp_data_7_alias;
+  wire         _metaArray_io_r_resp_data_7_prefetch;
+  wire [3:0]   _metaArray_io_r_resp_data_7_prefetchSrc;
+  wire         _metaArray_io_r_resp_data_7_accessed;
+  wire         _metaArray_io_r_resp_data_7_tagErr;
+  wire         _metaArray_io_r_resp_data_7_dataErr;
+  wire [40:0]  _tagArray_io_r_resp_data_0;
+  wire [40:0]  _tagArray_io_r_resp_data_1;
+  wire [40:0]  _tagArray_io_r_resp_data_2;
+  wire [40:0]  _tagArray_io_r_resp_data_3;
+  wire [40:0]  _tagArray_io_r_resp_data_4;
+  wire [40:0]  _tagArray_io_r_resp_data_5;
+  wire [40:0]  _tagArray_io_r_resp_data_6;
+  wire [40:0]  _tagArray_io_r_resp_data_7;
+  wire [2:0]   bd_array = boreChildrenBd_bore_array;
+  wire         bd_all = boreChildrenBd_bore_all;
+  wire         bd_req = boreChildrenBd_bore_req;
+  wire         bd_writeen = boreChildrenBd_bore_writeen;
+  wire [7:0]   bd_be = boreChildrenBd_bore_be;
+  wire [8:0]   bd_addr = boreChildrenBd_bore_addr;
+  wire [163:0] bd_indata = boreChildrenBd_bore_indata;
+  wire         bd_readen = boreChildrenBd_bore_readen;
+  wire [8:0]   bd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire         tagArray_io_r_req_valid = io_read_ready_0 & io_read_valid;
+  reg          reqValid_s2;
+  reg          reqValid_s3;
+  reg  [33:0]  req_s2_tag;
+  reg  [7:0]   req_s2_set;
+  reg  [2:0]   req_s2_replacerInfo_channel;
+  reg  [2:0]   req_s2_replacerInfo_opcode;
+  reg  [4:0]   req_s2_replacerInfo_reqSource;
+  reg          req_s2_replacerInfo_refill_prefetch;
+  reg          req_s2_refill;
+  reg  [7:0]   req_s2_mshrId;
+  reg          req_s2_cmoAll;
+  reg  [2:0]   req_s2_cmoWay;
+  reg  [33:0]  req_s3_tag;
+  reg  [7:0]   req_s3_set;
+  reg  [2:0]   req_s3_replacerInfo_channel;
+  reg  [2:0]   req_s3_replacerInfo_opcode;
+  reg  [4:0]   req_s3_replacerInfo_reqSource;
+  reg          req_s3_replacerInfo_refill_prefetch;
+  reg          req_s3_refill;
+  reg  [7:0]   req_s3_mshrId;
+  reg          req_s3_cmoAll;
+  reg  [7:0]   cmoWayOH_s3;
+  reg          refillReqValid_s2;
+  reg          refillReqValid_s3;
+  reg          refillReqValid_hold_s3_REG;
+  reg          refillReqValid_hold_s3;
+  wire [33:0]  _tagWrite_syndromeUInt_T =
+    {1'h0, io_tagWReq_bits_wtag[32:0] & 33'h156AAAD5B};
+  wire [33:0]  _tagWrite_syndromeUInt_T_3 =
+    {1'h0, io_tagWReq_bits_wtag[32:0] & 33'h19B33366D};
+  wire [33:0]  _tagWrite_syndromeUInt_T_6 =
+    {1'h0, io_tagWReq_bits_wtag[32:1] & 32'hF1E1E3C7, 1'h0};
+  wire [33:0]  _tagWrite_syndromeUInt_T_9 =
+    {io_tagWReq_bits_wtag[33:4] & 30'h203FC07F, 4'h0};
+  wire [33:0]  _tagWrite_syndromeUInt_T_12 = {8'h0, io_tagWReq_bits_wtag[25:11], 11'h0};
+  wire [33:0]  _tagWrite_syndromeUInt_T_15 = {io_tagWReq_bits_wtag[33:26], 26'h0};
+  wire [40:0]  tagWrite =
+    {^{^_tagWrite_syndromeUInt_T_15,
+       ^_tagWrite_syndromeUInt_T_12,
+       ^_tagWrite_syndromeUInt_T_9,
+       ^_tagWrite_syndromeUInt_T_6,
+       ^_tagWrite_syndromeUInt_T_3,
+       ^_tagWrite_syndromeUInt_T,
+       io_tagWReq_bits_wtag},
+     ^_tagWrite_syndromeUInt_T_15,
+     ^_tagWrite_syndromeUInt_T_12,
+     ^_tagWrite_syndromeUInt_T_9,
+     ^_tagWrite_syndromeUInt_T_6,
+     ^_tagWrite_syndromeUInt_T_3,
+     ^_tagWrite_syndromeUInt_T,
+     io_tagWReq_bits_wtag};
+  reg          metaAll_s3_0_dirty;
+  reg  [1:0]   metaAll_s3_0_state;
+  reg          metaAll_s3_0_clients;
+  reg          metaAll_s3_0_alias;
+  reg          metaAll_s3_0_prefetch;
+  reg  [3:0]   metaAll_s3_0_prefetchSrc;
+  reg          metaAll_s3_0_accessed;
+  reg          metaAll_s3_0_tagErr;
+  reg          metaAll_s3_0_dataErr;
+  reg          metaAll_s3_1_dirty;
+  reg  [1:0]   metaAll_s3_1_state;
+  reg          metaAll_s3_1_clients;
+  reg          metaAll_s3_1_alias;
+  reg          metaAll_s3_1_prefetch;
+  reg  [3:0]   metaAll_s3_1_prefetchSrc;
+  reg          metaAll_s3_1_accessed;
+  reg          metaAll_s3_1_tagErr;
+  reg          metaAll_s3_1_dataErr;
+  reg          metaAll_s3_2_dirty;
+  reg  [1:0]   metaAll_s3_2_state;
+  reg          metaAll_s3_2_clients;
+  reg          metaAll_s3_2_alias;
+  reg          metaAll_s3_2_prefetch;
+  reg  [3:0]   metaAll_s3_2_prefetchSrc;
+  reg          metaAll_s3_2_accessed;
+  reg          metaAll_s3_2_tagErr;
+  reg          metaAll_s3_2_dataErr;
+  reg          metaAll_s3_3_dirty;
+  reg  [1:0]   metaAll_s3_3_state;
+  reg          metaAll_s3_3_clients;
+  reg          metaAll_s3_3_alias;
+  reg          metaAll_s3_3_prefetch;
+  reg  [3:0]   metaAll_s3_3_prefetchSrc;
+  reg          metaAll_s3_3_accessed;
+  reg          metaAll_s3_3_tagErr;
+  reg          metaAll_s3_3_dataErr;
+  reg          metaAll_s3_4_dirty;
+  reg  [1:0]   metaAll_s3_4_state;
+  reg          metaAll_s3_4_clients;
+  reg          metaAll_s3_4_alias;
+  reg          metaAll_s3_4_prefetch;
+  reg  [3:0]   metaAll_s3_4_prefetchSrc;
+  reg          metaAll_s3_4_accessed;
+  reg          metaAll_s3_4_tagErr;
+  reg          metaAll_s3_4_dataErr;
+  reg          metaAll_s3_5_dirty;
+  reg  [1:0]   metaAll_s3_5_state;
+  reg          metaAll_s3_5_clients;
+  reg          metaAll_s3_5_alias;
+  reg          metaAll_s3_5_prefetch;
+  reg  [3:0]   metaAll_s3_5_prefetchSrc;
+  reg          metaAll_s3_5_accessed;
+  reg          metaAll_s3_5_tagErr;
+  reg          metaAll_s3_5_dataErr;
+  reg          metaAll_s3_6_dirty;
+  reg  [1:0]   metaAll_s3_6_state;
+  reg          metaAll_s3_6_clients;
+  reg          metaAll_s3_6_alias;
+  reg          metaAll_s3_6_prefetch;
+  reg  [3:0]   metaAll_s3_6_prefetchSrc;
+  reg          metaAll_s3_6_accessed;
+  reg          metaAll_s3_6_tagErr;
+  reg          metaAll_s3_6_dataErr;
+  reg          metaAll_s3_7_dirty;
+  reg  [1:0]   metaAll_s3_7_state;
+  reg          metaAll_s3_7_clients;
+  reg          metaAll_s3_7_alias;
+  reg          metaAll_s3_7_prefetch;
+  reg  [3:0]   metaAll_s3_7_prefetchSrc;
+  reg          metaAll_s3_7_accessed;
+  reg          metaAll_s3_7_tagErr;
+  reg          metaAll_s3_7_dataErr;
+  reg  [40:0]  tagRead_s3_0;
+  reg  [40:0]  tagRead_s3_1;
+  reg  [40:0]  tagRead_s3_2;
+  reg  [40:0]  tagRead_s3_3;
+  reg  [40:0]  tagRead_s3_4;
+  reg  [40:0]  tagRead_s3_5;
+  reg  [40:0]  tagRead_s3_6;
+  reg  [40:0]  tagRead_s3_7;
+  wire         errorAll_s3_0 =
+    ^tagRead_s3_0 | ~(^tagRead_s3_0)
+    & (|{^{tagRead_s3_0[39:26] & 14'h20FF, 26'h0},
+         ^{tagRead_s3_0[38:11] & 28'h8007FFF, 11'h0},
+         ^{tagRead_s3_0[37:4] & 34'h2203FC07F, 4'h0},
+         ^{tagRead_s3_0[36:1] & 36'h8F1E1E3C7, 1'h0},
+         ^(tagRead_s3_0[35:0] & 36'h99B33366D),
+         ^(tagRead_s3_0[34:0] & 35'h556AAAD5B)});
+  wire         errorAll_s3_1 =
+    ^tagRead_s3_1 | ~(^tagRead_s3_1)
+    & (|{^{tagRead_s3_1[39:26] & 14'h20FF, 26'h0},
+         ^{tagRead_s3_1[38:11] & 28'h8007FFF, 11'h0},
+         ^{tagRead_s3_1[37:4] & 34'h2203FC07F, 4'h0},
+         ^{tagRead_s3_1[36:1] & 36'h8F1E1E3C7, 1'h0},
+         ^(tagRead_s3_1[35:0] & 36'h99B33366D),
+         ^(tagRead_s3_1[34:0] & 35'h556AAAD5B)});
+  wire         errorAll_s3_2 =
+    ^tagRead_s3_2 | ~(^tagRead_s3_2)
+    & (|{^{tagRead_s3_2[39:26] & 14'h20FF, 26'h0},
+         ^{tagRead_s3_2[38:11] & 28'h8007FFF, 11'h0},
+         ^{tagRead_s3_2[37:4] & 34'h2203FC07F, 4'h0},
+         ^{tagRead_s3_2[36:1] & 36'h8F1E1E3C7, 1'h0},
+         ^(tagRead_s3_2[35:0] & 36'h99B33366D),
+         ^(tagRead_s3_2[34:0] & 35'h556AAAD5B)});
+  wire         errorAll_s3_3 =
+    ^tagRead_s3_3 | ~(^tagRead_s3_3)
+    & (|{^{tagRead_s3_3[39:26] & 14'h20FF, 26'h0},
+         ^{tagRead_s3_3[38:11] & 28'h8007FFF, 11'h0},
+         ^{tagRead_s3_3[37:4] & 34'h2203FC07F, 4'h0},
+         ^{tagRead_s3_3[36:1] & 36'h8F1E1E3C7, 1'h0},
+         ^(tagRead_s3_3[35:0] & 36'h99B33366D),
+         ^(tagRead_s3_3[34:0] & 35'h556AAAD5B)});
+  wire         errorAll_s3_4 =
+    ^tagRead_s3_4 | ~(^tagRead_s3_4)
+    & (|{^{tagRead_s3_4[39:26] & 14'h20FF, 26'h0},
+         ^{tagRead_s3_4[38:11] & 28'h8007FFF, 11'h0},
+         ^{tagRead_s3_4[37:4] & 34'h2203FC07F, 4'h0},
+         ^{tagRead_s3_4[36:1] & 36'h8F1E1E3C7, 1'h0},
+         ^(tagRead_s3_4[35:0] & 36'h99B33366D),
+         ^(tagRead_s3_4[34:0] & 35'h556AAAD5B)});
+  wire         errorAll_s3_5 =
+    ^tagRead_s3_5 | ~(^tagRead_s3_5)
+    & (|{^{tagRead_s3_5[39:26] & 14'h20FF, 26'h0},
+         ^{tagRead_s3_5[38:11] & 28'h8007FFF, 11'h0},
+         ^{tagRead_s3_5[37:4] & 34'h2203FC07F, 4'h0},
+         ^{tagRead_s3_5[36:1] & 36'h8F1E1E3C7, 1'h0},
+         ^(tagRead_s3_5[35:0] & 36'h99B33366D),
+         ^(tagRead_s3_5[34:0] & 35'h556AAAD5B)});
+  wire         errorAll_s3_6 =
+    ^tagRead_s3_6 | ~(^tagRead_s3_6)
+    & (|{^{tagRead_s3_6[39:26] & 14'h20FF, 26'h0},
+         ^{tagRead_s3_6[38:11] & 28'h8007FFF, 11'h0},
+         ^{tagRead_s3_6[37:4] & 34'h2203FC07F, 4'h0},
+         ^{tagRead_s3_6[36:1] & 36'h8F1E1E3C7, 1'h0},
+         ^(tagRead_s3_6[35:0] & 36'h99B33366D),
+         ^(tagRead_s3_6[34:0] & 35'h556AAAD5B)});
+  wire         errorAll_s3_7 =
+    ^tagRead_s3_7 | ~(^tagRead_s3_7)
+    & (|{^{tagRead_s3_7[39:26] & 14'h20FF, 26'h0},
+         ^{tagRead_s3_7[38:11] & 28'h8007FFF, 11'h0},
+         ^{tagRead_s3_7[37:4] & 34'h2203FC07F, 4'h0},
+         ^{tagRead_s3_7[36:1] & 36'h8F1E1E3C7, 1'h0},
+         ^(tagRead_s3_7[35:0] & 36'h99B33366D),
+         ^(tagRead_s3_7[34:0] & 35'h556AAAD5B)});
+  wire         hitVec_0 = tagRead_s3_0[33:0] == req_s3_tag & (|metaAll_s3_0_state);
+  wire         hitVec_1 = tagRead_s3_1[33:0] == req_s3_tag & (|metaAll_s3_1_state);
+  wire         hitVec_2 = tagRead_s3_2[33:0] == req_s3_tag & (|metaAll_s3_2_state);
+  wire         hitVec_3 = tagRead_s3_3[33:0] == req_s3_tag & (|metaAll_s3_3_state);
+  wire         hitVec_4 = tagRead_s3_4[33:0] == req_s3_tag & (|metaAll_s3_4_state);
+  wire         hitVec_5 = tagRead_s3_5[33:0] == req_s3_tag & (|metaAll_s3_5_state);
+  wire         hitVec_6 = tagRead_s3_6[33:0] == req_s3_tag & (|metaAll_s3_6_state);
+  wire         hitVec_7 = tagRead_s3_7[33:0] == req_s3_tag & (|metaAll_s3_7_state);
+  reg  [7:0]   occWayMask_s2;
+  reg  [7:0]   freeWayMask_s3;
+  reg          refillRetry;
+  wire         invalid_vec_1 = metaAll_s3_1_state == 2'h0;
+  wire         invalid_vec_2 = metaAll_s3_2_state == 2'h0;
+  wire         invalid_vec_3 = metaAll_s3_3_state == 2'h0;
+  wire         invalid_vec_4 = metaAll_s3_4_state == 2'h0;
+  wire         invalid_vec_5 = metaAll_s3_5_state == 2'h0;
+  wire         invalid_vec_6 = metaAll_s3_6_state == 2'h0;
+  wire         invalid_vec_7 = metaAll_s3_7_state == 2'h0;
+  wire [7:0]   chosenOH =
+    (|{~(|metaAll_s3_0_state),
+       invalid_vec_1,
+       invalid_vec_2,
+       invalid_vec_3,
+       invalid_vec_4,
+       invalid_vec_5,
+       invalid_vec_6,
+       invalid_vec_7})
+      ? {invalid_vec_7
+           & {~(|metaAll_s3_0_state),
+              invalid_vec_1,
+              invalid_vec_2,
+              invalid_vec_3,
+              invalid_vec_4,
+              invalid_vec_5,
+              invalid_vec_6} == 7'h0,
+         invalid_vec_6
+           & {~(|metaAll_s3_0_state),
+              invalid_vec_1,
+              invalid_vec_2,
+              invalid_vec_3,
+              invalid_vec_4,
+              invalid_vec_5} == 6'h0,
+         invalid_vec_5
+           & {~(|metaAll_s3_0_state),
+              invalid_vec_1,
+              invalid_vec_2,
+              invalid_vec_3,
+              invalid_vec_4} == 5'h0,
+         invalid_vec_4
+           & {~(|metaAll_s3_0_state),
+              invalid_vec_1,
+              invalid_vec_2,
+              invalid_vec_3} == 4'h0,
+         invalid_vec_3 & {~(|metaAll_s3_0_state), invalid_vec_1, invalid_vec_2} == 3'h0,
+         invalid_vec_2 & {~(|metaAll_s3_0_state), invalid_vec_1} == 2'h0,
+         invalid_vec_1 & (|metaAll_s3_0_state),
+         ~(|metaAll_s3_0_state)}
+      : replaceOH;
+  wire [7:0]   finalReplOH =
+    (|(chosenOH & freeWayMask_s3))
+      ? chosenOH
+      : {freeWayMask_s3[7]
+           & {freeWayMask_s3[0],
+              freeWayMask_s3[1],
+              freeWayMask_s3[2],
+              freeWayMask_s3[3],
+              freeWayMask_s3[4],
+              freeWayMask_s3[5],
+              freeWayMask_s3[6]} == 7'h0,
+         freeWayMask_s3[6]
+           & {freeWayMask_s3[0],
+              freeWayMask_s3[1],
+              freeWayMask_s3[2],
+              freeWayMask_s3[3],
+              freeWayMask_s3[4],
+              freeWayMask_s3[5]} == 6'h0,
+         freeWayMask_s3[5]
+           & {freeWayMask_s3[0],
+              freeWayMask_s3[1],
+              freeWayMask_s3[2],
+              freeWayMask_s3[3],
+              freeWayMask_s3[4]} == 5'h0,
+         freeWayMask_s3[4]
+           & {freeWayMask_s3[0],
+              freeWayMask_s3[1],
+              freeWayMask_s3[2],
+              freeWayMask_s3[3]} == 4'h0,
+         freeWayMask_s3[3]
+           & {freeWayMask_s3[0], freeWayMask_s3[1], freeWayMask_s3[2]} == 3'h0,
+         freeWayMask_s3[2] & {freeWayMask_s3[0], freeWayMask_s3[1]} == 2'h0,
+         freeWayMask_s3[1] & ~(freeWayMask_s3[0]),
+         freeWayMask_s3[0]};
+  wire         hit_s3 =
+    (|{hitVec_0, hitVec_1, hitVec_2, hitVec_3, hitVec_4, hitVec_5, hitVec_6, hitVec_7})
+    | req_s3_cmoAll;
+  wire [7:0]   io_wayOH_0 =
+    req_s3_cmoAll
+      ? cmoWayOH_s3
+      : hit_s3
+          ? {hitVec_7,
+             hitVec_6,
+             hitVec_5,
+             hitVec_4,
+             hitVec_3,
+             hitVec_2,
+             hitVec_1,
+             hitVec_0}
+          : finalReplOH;
+  wire [2:0]   _way_s3_T_1 = io_wayOH_0[7:5] | io_wayOH_0[3:1];
+  wire         _way_s3_T_3 = _way_s3_T_1[2] | _way_s3_T_1[0];
+  wire [1:0]   meta_s3_state =
+    (io_wayOH_0[0] ? metaAll_s3_0_state : 2'h0)
+    | (io_wayOH_0[1] ? metaAll_s3_1_state : 2'h0)
+    | (io_wayOH_0[2] ? metaAll_s3_2_state : 2'h0)
+    | (io_wayOH_0[3] ? metaAll_s3_3_state : 2'h0)
+    | (io_wayOH_0[4] ? metaAll_s3_4_state : 2'h0)
+    | (io_wayOH_0[5] ? metaAll_s3_5_state : 2'h0)
+    | (io_wayOH_0[6] ? metaAll_s3_6_state : 2'h0)
+    | (io_wayOH_0[7] ? metaAll_s3_7_state : 2'h0);
+  assign io_read_ready_0 = ~io_metaWReq_valid & ~io_tagWReq_valid & ~replacerWen;
+  reg  [15:0]  repl_state_s3;
+  wire         _replaceOH_lrrWayVec_0_T_15 =
+    repl_state_s3[3:2] > repl_state_s3[1:0] | repl_state_s3[5:4] > repl_state_s3[1:0]
+    | repl_state_s3[7:6] > repl_state_s3[1:0] | repl_state_s3[9:8] > repl_state_s3[1:0]
+    | repl_state_s3[11:10] > repl_state_s3[1:0]
+    | repl_state_s3[13:12] > repl_state_s3[1:0]
+    | repl_state_s3[15:14] > repl_state_s3[1:0];
+  wire         _replaceOH_lrrWayVec_1_T_15 =
+    repl_state_s3[1:0] > repl_state_s3[3:2] | repl_state_s3[5:4] > repl_state_s3[3:2]
+    | repl_state_s3[7:6] > repl_state_s3[3:2] | repl_state_s3[9:8] > repl_state_s3[3:2]
+    | repl_state_s3[11:10] > repl_state_s3[3:2]
+    | repl_state_s3[13:12] > repl_state_s3[3:2]
+    | repl_state_s3[15:14] > repl_state_s3[3:2];
+  wire         _replaceOH_lrrWayVec_2_T_15 =
+    repl_state_s3[1:0] > repl_state_s3[5:4] | repl_state_s3[3:2] > repl_state_s3[5:4]
+    | repl_state_s3[7:6] > repl_state_s3[5:4] | repl_state_s3[9:8] > repl_state_s3[5:4]
+    | repl_state_s3[11:10] > repl_state_s3[5:4]
+    | repl_state_s3[13:12] > repl_state_s3[5:4]
+    | repl_state_s3[15:14] > repl_state_s3[5:4];
+  wire         _replaceOH_lrrWayVec_3_T_15 =
+    repl_state_s3[1:0] > repl_state_s3[7:6] | repl_state_s3[3:2] > repl_state_s3[7:6]
+    | repl_state_s3[5:4] > repl_state_s3[7:6] | repl_state_s3[9:8] > repl_state_s3[7:6]
+    | repl_state_s3[11:10] > repl_state_s3[7:6]
+    | repl_state_s3[13:12] > repl_state_s3[7:6]
+    | repl_state_s3[15:14] > repl_state_s3[7:6];
+  wire         _replaceOH_lrrWayVec_4_T_15 =
+    repl_state_s3[1:0] > repl_state_s3[9:8] | repl_state_s3[3:2] > repl_state_s3[9:8]
+    | repl_state_s3[5:4] > repl_state_s3[9:8] | repl_state_s3[7:6] > repl_state_s3[9:8]
+    | repl_state_s3[11:10] > repl_state_s3[9:8]
+    | repl_state_s3[13:12] > repl_state_s3[9:8]
+    | repl_state_s3[15:14] > repl_state_s3[9:8];
+  wire         _replaceOH_lrrWayVec_5_T_15 =
+    repl_state_s3[1:0] > repl_state_s3[11:10] | repl_state_s3[3:2] > repl_state_s3[11:10]
+    | repl_state_s3[5:4] > repl_state_s3[11:10]
+    | repl_state_s3[7:6] > repl_state_s3[11:10]
+    | repl_state_s3[9:8] > repl_state_s3[11:10]
+    | repl_state_s3[13:12] > repl_state_s3[11:10]
+    | repl_state_s3[15:14] > repl_state_s3[11:10];
+  wire         _replaceOH_lrrWayVec_6_T_15 =
+    repl_state_s3[1:0] > repl_state_s3[13:12] | repl_state_s3[3:2] > repl_state_s3[13:12]
+    | repl_state_s3[5:4] > repl_state_s3[13:12]
+    | repl_state_s3[7:6] > repl_state_s3[13:12]
+    | repl_state_s3[9:8] > repl_state_s3[13:12]
+    | repl_state_s3[11:10] > repl_state_s3[13:12]
+    | repl_state_s3[15:14] > repl_state_s3[13:12];
+  assign replaceOH =
+    {~(repl_state_s3[1:0] > repl_state_s3[15:14]
+       | repl_state_s3[3:2] > repl_state_s3[15:14]
+       | repl_state_s3[5:4] > repl_state_s3[15:14]
+       | repl_state_s3[7:6] > repl_state_s3[15:14]
+       | repl_state_s3[9:8] > repl_state_s3[15:14]
+       | repl_state_s3[11:10] > repl_state_s3[15:14]
+       | repl_state_s3[13:12] > repl_state_s3[15:14])
+       & {~_replaceOH_lrrWayVec_0_T_15,
+          ~_replaceOH_lrrWayVec_1_T_15,
+          ~_replaceOH_lrrWayVec_2_T_15,
+          ~_replaceOH_lrrWayVec_3_T_15,
+          ~_replaceOH_lrrWayVec_4_T_15,
+          ~_replaceOH_lrrWayVec_5_T_15,
+          ~_replaceOH_lrrWayVec_6_T_15} == 7'h0,
+     ~_replaceOH_lrrWayVec_6_T_15
+       & {~_replaceOH_lrrWayVec_0_T_15,
+          ~_replaceOH_lrrWayVec_1_T_15,
+          ~_replaceOH_lrrWayVec_2_T_15,
+          ~_replaceOH_lrrWayVec_3_T_15,
+          ~_replaceOH_lrrWayVec_4_T_15,
+          ~_replaceOH_lrrWayVec_5_T_15} == 6'h0,
+     ~_replaceOH_lrrWayVec_5_T_15
+       & {~_replaceOH_lrrWayVec_0_T_15,
+          ~_replaceOH_lrrWayVec_1_T_15,
+          ~_replaceOH_lrrWayVec_2_T_15,
+          ~_replaceOH_lrrWayVec_3_T_15,
+          ~_replaceOH_lrrWayVec_4_T_15} == 5'h0,
+     ~_replaceOH_lrrWayVec_4_T_15
+       & {~_replaceOH_lrrWayVec_0_T_15,
+          ~_replaceOH_lrrWayVec_1_T_15,
+          ~_replaceOH_lrrWayVec_2_T_15,
+          ~_replaceOH_lrrWayVec_3_T_15} == 4'h0,
+     ~_replaceOH_lrrWayVec_3_T_15
+       & {~_replaceOH_lrrWayVec_0_T_15,
+          ~_replaceOH_lrrWayVec_1_T_15,
+          ~_replaceOH_lrrWayVec_2_T_15} == 3'h0,
+     ~_replaceOH_lrrWayVec_2_T_15
+       & {~_replaceOH_lrrWayVec_0_T_15, ~_replaceOH_lrrWayVec_1_T_15} == 2'h0,
+     ~_replaceOH_lrrWayVec_1_T_15 & _replaceOH_lrrWayVec_0_T_15,
+     ~_replaceOH_lrrWayVec_0_T_15};
+  wire [2:0]   _io_replResp_bits_way_T_1 = finalReplOH[7:5] | finalReplOH[3:1];
+  wire         _updateHit_T_9 = req_s3_replacerInfo_opcode == 3'h6;
+  wire         _rrip_req_type_T_28 = req_s3_replacerInfo_opcode == 3'h5;
+  assign replacerWen =
+    reqValid_s3 & hit_s3
+    & (req_s3_replacerInfo_channel[0]
+       & ((&req_s3_replacerInfo_opcode) | _updateHit_T_9 | _rrip_req_type_T_28)
+       | req_s3_replacerInfo_channel[2]
+       & (_updateHit_T_9 | (&req_s3_replacerInfo_opcode))) | refillReqValid_s3
+    & ~refillRetry;
+  reg          r_0;
+  reg          r_1;
+  reg          r_2;
+  reg          r_3;
+  reg          r_4;
+  reg          r_5;
+  reg          r_6;
+  reg          r_7;
+  wire         _rrip_req_type_T_182 =
+    ~refillReqValid_s3 & req_s3_replacerInfo_channel[0] & _rrip_req_type_T_28
+    | req_s3_replacerInfo_channel[2]
+    & (io_wayOH_0[0] & metaAll_s3_0_prefetch | io_wayOH_0[1] & metaAll_s3_1_prefetch
+       | io_wayOH_0[2] & metaAll_s3_2_prefetch | io_wayOH_0[3] & metaAll_s3_3_prefetch
+       | io_wayOH_0[4] & metaAll_s3_4_prefetch | io_wayOH_0[5] & metaAll_s3_5_prefetch
+       | io_wayOH_0[6] & metaAll_s3_6_prefetch | io_wayOH_0[7] & metaAll_s3_7_prefetch)
+    | refillReqValid_s3 & req_s3_replacerInfo_refill_prefetch;
+  wire [3:0]   rrip_req_type =
+    {hitVec_0 & r_0 | hitVec_1 & r_1 | hitVec_2 & r_2 | hitVec_3 & r_3 | hitVec_4 & r_4
+       | hitVec_5 & r_5 | hitVec_6 & r_6 | hitVec_7 & r_7,
+     req_s3_replacerInfo_channel[2],
+     _rrip_req_type_T_182,
+     req_s3_refill};
+  reg  [9:0]   PSEL;
+  wire         match_a = req_s3_set[7:3] == {1'h0, req_s3_set[3:0]};
+  wire         match_b = req_s3_set[7:3] == {1'h0, ~(req_s3_set[3:0])};
+  wire [1:0]   _next_state_s3_increcement_T_23 =
+    2'(2'h3
+       - ((io_wayOH_0[0] ? repl_state_s3[1:0] : 2'h0)
+          | (io_wayOH_0[1] ? repl_state_s3[3:2] : 2'h0)
+          | (io_wayOH_0[2] ? repl_state_s3[5:4] : 2'h0)
+          | (io_wayOH_0[3] ? repl_state_s3[7:6] : 2'h0)
+          | (io_wayOH_0[4] ? repl_state_s3[9:8] : 2'h0)
+          | (io_wayOH_0[5] ? repl_state_s3[11:10] : 2'h0)
+          | (io_wayOH_0[6] ? repl_state_s3[13:12] : 2'h0)
+          | (io_wayOH_0[7] ? repl_state_s3[15:14] : 2'h0)));
+  wire [2:0]   _next_state_s3_nextState_7_T_33 =
+    {req_s3_replacerInfo_channel[2], _rrip_req_type_T_182, req_s3_refill};
+  wire         _next_state_s3_nextState_7_T_28 = rrip_req_type == 4'hC;
+  wire         _next_state_s3_nextState_7_T_32 = rrip_req_type == 4'h4;
+  wire [8:0]   _GEN =
+    {hit_s3,
+     ~(|metaAll_s3_0_state),
+     invalid_vec_1,
+     invalid_vec_2,
+     invalid_vec_3,
+     invalid_vec_4,
+     invalid_vec_5,
+     invalid_vec_6,
+     invalid_vec_7};
+  wire [1:0]   _next_state_s3_increcement_T_47 =
+    2'(2'h3
+       - ((io_wayOH_0[0] ? repl_state_s3[1:0] : 2'h0)
+          | (io_wayOH_0[1] ? repl_state_s3[3:2] : 2'h0)
+          | (io_wayOH_0[2] ? repl_state_s3[5:4] : 2'h0)
+          | (io_wayOH_0[3] ? repl_state_s3[7:6] : 2'h0)
+          | (io_wayOH_0[4] ? repl_state_s3[9:8] : 2'h0)
+          | (io_wayOH_0[5] ? repl_state_s3[11:10] : 2'h0)
+          | (io_wayOH_0[6] ? repl_state_s3[13:12] : 2'h0)
+          | (io_wayOH_0[7] ? repl_state_s3[15:14] : 2'h0)));
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      reqValid_s2 <= 1'h0;
+      reqValid_s3 <= 1'h0;
+      req_s3_tag <= 34'h0;
+      req_s3_set <= 8'h0;
+      req_s3_replacerInfo_channel <= 3'h0;
+      req_s3_replacerInfo_opcode <= 3'h0;
+      req_s3_replacerInfo_reqSource <= 5'h0;
+      req_s3_replacerInfo_refill_prefetch <= 1'h0;
+      req_s3_refill <= 1'h0;
+      req_s3_mshrId <= 8'h0;
+      req_s3_cmoAll <= 1'h0;
+      refillReqValid_s2 <= 1'h0;
+      refillReqValid_s3 <= 1'h0;
+      refillReqValid_hold_s3 <= 1'h0;
+      metaAll_s3_0_dirty <= 1'h0;
+      metaAll_s3_0_state <= 2'h0;
+      metaAll_s3_0_clients <= 1'h0;
+      metaAll_s3_0_alias <= 1'h0;
+      metaAll_s3_0_prefetch <= 1'h0;
+      metaAll_s3_0_prefetchSrc <= 4'h0;
+      metaAll_s3_0_accessed <= 1'h0;
+      metaAll_s3_0_tagErr <= 1'h0;
+      metaAll_s3_0_dataErr <= 1'h0;
+      metaAll_s3_1_dirty <= 1'h0;
+      metaAll_s3_1_state <= 2'h0;
+      metaAll_s3_1_clients <= 1'h0;
+      metaAll_s3_1_alias <= 1'h0;
+      metaAll_s3_1_prefetch <= 1'h0;
+      metaAll_s3_1_prefetchSrc <= 4'h0;
+      metaAll_s3_1_accessed <= 1'h0;
+      metaAll_s3_1_tagErr <= 1'h0;
+      metaAll_s3_1_dataErr <= 1'h0;
+      metaAll_s3_2_dirty <= 1'h0;
+      metaAll_s3_2_state <= 2'h0;
+      metaAll_s3_2_clients <= 1'h0;
+      metaAll_s3_2_alias <= 1'h0;
+      metaAll_s3_2_prefetch <= 1'h0;
+      metaAll_s3_2_prefetchSrc <= 4'h0;
+      metaAll_s3_2_accessed <= 1'h0;
+      metaAll_s3_2_tagErr <= 1'h0;
+      metaAll_s3_2_dataErr <= 1'h0;
+      metaAll_s3_3_dirty <= 1'h0;
+      metaAll_s3_3_state <= 2'h0;
+      metaAll_s3_3_clients <= 1'h0;
+      metaAll_s3_3_alias <= 1'h0;
+      metaAll_s3_3_prefetch <= 1'h0;
+      metaAll_s3_3_prefetchSrc <= 4'h0;
+      metaAll_s3_3_accessed <= 1'h0;
+      metaAll_s3_3_tagErr <= 1'h0;
+      metaAll_s3_3_dataErr <= 1'h0;
+      metaAll_s3_4_dirty <= 1'h0;
+      metaAll_s3_4_state <= 2'h0;
+      metaAll_s3_4_clients <= 1'h0;
+      metaAll_s3_4_alias <= 1'h0;
+      metaAll_s3_4_prefetch <= 1'h0;
+      metaAll_s3_4_prefetchSrc <= 4'h0;
+      metaAll_s3_4_accessed <= 1'h0;
+      metaAll_s3_4_tagErr <= 1'h0;
+      metaAll_s3_4_dataErr <= 1'h0;
+      metaAll_s3_5_dirty <= 1'h0;
+      metaAll_s3_5_state <= 2'h0;
+      metaAll_s3_5_clients <= 1'h0;
+      metaAll_s3_5_alias <= 1'h0;
+      metaAll_s3_5_prefetch <= 1'h0;
+      metaAll_s3_5_prefetchSrc <= 4'h0;
+      metaAll_s3_5_accessed <= 1'h0;
+      metaAll_s3_5_tagErr <= 1'h0;
+      metaAll_s3_5_dataErr <= 1'h0;
+      metaAll_s3_6_dirty <= 1'h0;
+      metaAll_s3_6_state <= 2'h0;
+      metaAll_s3_6_clients <= 1'h0;
+      metaAll_s3_6_alias <= 1'h0;
+      metaAll_s3_6_prefetch <= 1'h0;
+      metaAll_s3_6_prefetchSrc <= 4'h0;
+      metaAll_s3_6_accessed <= 1'h0;
+      metaAll_s3_6_tagErr <= 1'h0;
+      metaAll_s3_6_dataErr <= 1'h0;
+      metaAll_s3_7_dirty <= 1'h0;
+      metaAll_s3_7_state <= 2'h0;
+      metaAll_s3_7_clients <= 1'h0;
+      metaAll_s3_7_alias <= 1'h0;
+      metaAll_s3_7_prefetch <= 1'h0;
+      metaAll_s3_7_prefetchSrc <= 4'h0;
+      metaAll_s3_7_accessed <= 1'h0;
+      metaAll_s3_7_tagErr <= 1'h0;
+      metaAll_s3_7_dataErr <= 1'h0;
+      repl_state_s3 <= 16'h0;
+      PSEL <= 10'h200;
+    end
+    else begin
+      reqValid_s2 <= tagArray_io_r_req_valid;
+      reqValid_s3 <= reqValid_s2;
+      if (reqValid_s2) begin
+        req_s3_tag <= req_s2_tag;
+        req_s3_set <= req_s2_set;
+        req_s3_replacerInfo_channel <= req_s2_replacerInfo_channel;
+        req_s3_replacerInfo_opcode <= req_s2_replacerInfo_opcode;
+        req_s3_replacerInfo_reqSource <= req_s2_replacerInfo_reqSource;
+        req_s3_replacerInfo_refill_prefetch <= req_s2_replacerInfo_refill_prefetch;
+        req_s3_refill <= req_s2_refill;
+        req_s3_mshrId <= req_s2_mshrId;
+        req_s3_cmoAll <= req_s2_cmoAll;
+        metaAll_s3_0_dirty <= _metaArray_io_r_resp_data_0_dirty;
+        metaAll_s3_0_state <= _metaArray_io_r_resp_data_0_state;
+        metaAll_s3_0_clients <= _metaArray_io_r_resp_data_0_clients;
+        metaAll_s3_0_alias <= _metaArray_io_r_resp_data_0_alias;
+        metaAll_s3_0_prefetch <= _metaArray_io_r_resp_data_0_prefetch;
+        metaAll_s3_0_prefetchSrc <= _metaArray_io_r_resp_data_0_prefetchSrc;
+        metaAll_s3_0_accessed <= _metaArray_io_r_resp_data_0_accessed;
+        metaAll_s3_0_tagErr <= _metaArray_io_r_resp_data_0_tagErr;
+        metaAll_s3_0_dataErr <= _metaArray_io_r_resp_data_0_dataErr;
+        metaAll_s3_1_dirty <= _metaArray_io_r_resp_data_1_dirty;
+        metaAll_s3_1_state <= _metaArray_io_r_resp_data_1_state;
+        metaAll_s3_1_clients <= _metaArray_io_r_resp_data_1_clients;
+        metaAll_s3_1_alias <= _metaArray_io_r_resp_data_1_alias;
+        metaAll_s3_1_prefetch <= _metaArray_io_r_resp_data_1_prefetch;
+        metaAll_s3_1_prefetchSrc <= _metaArray_io_r_resp_data_1_prefetchSrc;
+        metaAll_s3_1_accessed <= _metaArray_io_r_resp_data_1_accessed;
+        metaAll_s3_1_tagErr <= _metaArray_io_r_resp_data_1_tagErr;
+        metaAll_s3_1_dataErr <= _metaArray_io_r_resp_data_1_dataErr;
+        metaAll_s3_2_dirty <= _metaArray_io_r_resp_data_2_dirty;
+        metaAll_s3_2_state <= _metaArray_io_r_resp_data_2_state;
+        metaAll_s3_2_clients <= _metaArray_io_r_resp_data_2_clients;
+        metaAll_s3_2_alias <= _metaArray_io_r_resp_data_2_alias;
+        metaAll_s3_2_prefetch <= _metaArray_io_r_resp_data_2_prefetch;
+        metaAll_s3_2_prefetchSrc <= _metaArray_io_r_resp_data_2_prefetchSrc;
+        metaAll_s3_2_accessed <= _metaArray_io_r_resp_data_2_accessed;
+        metaAll_s3_2_tagErr <= _metaArray_io_r_resp_data_2_tagErr;
+        metaAll_s3_2_dataErr <= _metaArray_io_r_resp_data_2_dataErr;
+        metaAll_s3_3_dirty <= _metaArray_io_r_resp_data_3_dirty;
+        metaAll_s3_3_state <= _metaArray_io_r_resp_data_3_state;
+        metaAll_s3_3_clients <= _metaArray_io_r_resp_data_3_clients;
+        metaAll_s3_3_alias <= _metaArray_io_r_resp_data_3_alias;
+        metaAll_s3_3_prefetch <= _metaArray_io_r_resp_data_3_prefetch;
+        metaAll_s3_3_prefetchSrc <= _metaArray_io_r_resp_data_3_prefetchSrc;
+        metaAll_s3_3_accessed <= _metaArray_io_r_resp_data_3_accessed;
+        metaAll_s3_3_tagErr <= _metaArray_io_r_resp_data_3_tagErr;
+        metaAll_s3_3_dataErr <= _metaArray_io_r_resp_data_3_dataErr;
+        metaAll_s3_4_dirty <= _metaArray_io_r_resp_data_4_dirty;
+        metaAll_s3_4_state <= _metaArray_io_r_resp_data_4_state;
+        metaAll_s3_4_clients <= _metaArray_io_r_resp_data_4_clients;
+        metaAll_s3_4_alias <= _metaArray_io_r_resp_data_4_alias;
+        metaAll_s3_4_prefetch <= _metaArray_io_r_resp_data_4_prefetch;
+        metaAll_s3_4_prefetchSrc <= _metaArray_io_r_resp_data_4_prefetchSrc;
+        metaAll_s3_4_accessed <= _metaArray_io_r_resp_data_4_accessed;
+        metaAll_s3_4_tagErr <= _metaArray_io_r_resp_data_4_tagErr;
+        metaAll_s3_4_dataErr <= _metaArray_io_r_resp_data_4_dataErr;
+        metaAll_s3_5_dirty <= _metaArray_io_r_resp_data_5_dirty;
+        metaAll_s3_5_state <= _metaArray_io_r_resp_data_5_state;
+        metaAll_s3_5_clients <= _metaArray_io_r_resp_data_5_clients;
+        metaAll_s3_5_alias <= _metaArray_io_r_resp_data_5_alias;
+        metaAll_s3_5_prefetch <= _metaArray_io_r_resp_data_5_prefetch;
+        metaAll_s3_5_prefetchSrc <= _metaArray_io_r_resp_data_5_prefetchSrc;
+        metaAll_s3_5_accessed <= _metaArray_io_r_resp_data_5_accessed;
+        metaAll_s3_5_tagErr <= _metaArray_io_r_resp_data_5_tagErr;
+        metaAll_s3_5_dataErr <= _metaArray_io_r_resp_data_5_dataErr;
+        metaAll_s3_6_dirty <= _metaArray_io_r_resp_data_6_dirty;
+        metaAll_s3_6_state <= _metaArray_io_r_resp_data_6_state;
+        metaAll_s3_6_clients <= _metaArray_io_r_resp_data_6_clients;
+        metaAll_s3_6_alias <= _metaArray_io_r_resp_data_6_alias;
+        metaAll_s3_6_prefetch <= _metaArray_io_r_resp_data_6_prefetch;
+        metaAll_s3_6_prefetchSrc <= _metaArray_io_r_resp_data_6_prefetchSrc;
+        metaAll_s3_6_accessed <= _metaArray_io_r_resp_data_6_accessed;
+        metaAll_s3_6_tagErr <= _metaArray_io_r_resp_data_6_tagErr;
+        metaAll_s3_6_dataErr <= _metaArray_io_r_resp_data_6_dataErr;
+        metaAll_s3_7_dirty <= _metaArray_io_r_resp_data_7_dirty;
+        metaAll_s3_7_state <= _metaArray_io_r_resp_data_7_state;
+        metaAll_s3_7_clients <= _metaArray_io_r_resp_data_7_clients;
+        metaAll_s3_7_alias <= _metaArray_io_r_resp_data_7_alias;
+        metaAll_s3_7_prefetch <= _metaArray_io_r_resp_data_7_prefetch;
+        metaAll_s3_7_prefetchSrc <= _metaArray_io_r_resp_data_7_prefetchSrc;
+        metaAll_s3_7_accessed <= _metaArray_io_r_resp_data_7_accessed;
+        metaAll_s3_7_tagErr <= _metaArray_io_r_resp_data_7_tagErr;
+        metaAll_s3_7_dataErr <= _metaArray_io_r_resp_data_7_dataErr;
+        repl_state_s3 <= _replacer_sram_opt_io_r_resp_data_0;
+      end
+      refillReqValid_s2 <= tagArray_io_r_req_valid & io_read_bits_refill;
+      refillReqValid_s3 <= refillReqValid_s2;
+      if (refillReqValid_hold_s3_REG) begin
+      end
+      else
+        refillReqValid_hold_s3 <= refillReqValid_s2;
+      if (refillReqValid_s3 & match_a & ~hit_s3 & PSEL != 10'h3FF)
+        PSEL <= 10'(PSEL + 10'h1);
+      else if (refillReqValid_s3 & match_b & ~hit_s3 & (|PSEL))
+        PSEL <= 10'(PSEL - 10'h1);
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (tagArray_io_r_req_valid) begin
+      req_s2_tag <= io_read_bits_tag;
+      req_s2_set <= io_read_bits_set;
+      req_s2_replacerInfo_channel <= io_read_bits_replacerInfo_channel;
+      req_s2_replacerInfo_opcode <= io_read_bits_replacerInfo_opcode;
+      req_s2_replacerInfo_reqSource <= io_read_bits_replacerInfo_reqSource;
+      req_s2_replacerInfo_refill_prefetch <= io_read_bits_replacerInfo_refill_prefetch;
+      req_s2_refill <= io_read_bits_refill;
+      req_s2_mshrId <= io_read_bits_mshrId;
+      req_s2_cmoAll <= io_read_bits_cmoAll;
+      req_s2_cmoWay <= io_read_bits_cmoWay;
+    end
+    if (reqValid_s2) begin
+      cmoWayOH_s3 <= 8'h1 << req_s2_cmoWay;
+      tagRead_s3_0 <= _tagArray_io_r_resp_data_0;
+      tagRead_s3_1 <= _tagArray_io_r_resp_data_1;
+      tagRead_s3_2 <= _tagArray_io_r_resp_data_2;
+      tagRead_s3_3 <= _tagArray_io_r_resp_data_3;
+      tagRead_s3_4 <= _tagArray_io_r_resp_data_4;
+      tagRead_s3_5 <= _tagArray_io_r_resp_data_5;
+      tagRead_s3_6 <= _tagArray_io_r_resp_data_6;
+      tagRead_s3_7 <= _tagArray_io_r_resp_data_7;
+      r_0 <= _origin_bit_opt_io_r_resp_data_0;
+      r_1 <= _origin_bit_opt_io_r_resp_data_1;
+      r_2 <= _origin_bit_opt_io_r_resp_data_2;
+      r_3 <= _origin_bit_opt_io_r_resp_data_3;
+      r_4 <= _origin_bit_opt_io_r_resp_data_4;
+      r_5 <= _origin_bit_opt_io_r_resp_data_5;
+      r_6 <= _origin_bit_opt_io_r_resp_data_6;
+      r_7 <= _origin_bit_opt_io_r_resp_data_7;
+    end
+    refillReqValid_hold_s3_REG <= refillReqValid_s2;
+    if (tagArray_io_r_req_valid & io_read_bits_refill)
+      occWayMask_s2 <=
+        (io_msInfo_0_valid & io_msInfo_0_bits_set == io_read_bits_set
+         & (io_msInfo_0_bits_blockRefill | io_msInfo_0_bits_dirHit)
+           ? 8'h1 << io_msInfo_0_bits_way
+           : 8'h0)
+        | (io_msInfo_1_valid & io_msInfo_1_bits_set == io_read_bits_set
+           & (io_msInfo_1_bits_blockRefill | io_msInfo_1_bits_dirHit)
+             ? 8'h1 << io_msInfo_1_bits_way
+             : 8'h0)
+        | (io_msInfo_2_valid & io_msInfo_2_bits_set == io_read_bits_set
+           & (io_msInfo_2_bits_blockRefill | io_msInfo_2_bits_dirHit)
+             ? 8'h1 << io_msInfo_2_bits_way
+             : 8'h0)
+        | (io_msInfo_3_valid & io_msInfo_3_bits_set == io_read_bits_set
+           & (io_msInfo_3_bits_blockRefill | io_msInfo_3_bits_dirHit)
+             ? 8'h1 << io_msInfo_3_bits_way
+             : 8'h0)
+        | (io_msInfo_4_valid & io_msInfo_4_bits_set == io_read_bits_set
+           & (io_msInfo_4_bits_blockRefill | io_msInfo_4_bits_dirHit)
+             ? 8'h1 << io_msInfo_4_bits_way
+             : 8'h0)
+        | (io_msInfo_5_valid & io_msInfo_5_bits_set == io_read_bits_set
+           & (io_msInfo_5_bits_blockRefill | io_msInfo_5_bits_dirHit)
+             ? 8'h1 << io_msInfo_5_bits_way
+             : 8'h0)
+        | (io_msInfo_6_valid & io_msInfo_6_bits_set == io_read_bits_set
+           & (io_msInfo_6_bits_blockRefill | io_msInfo_6_bits_dirHit)
+             ? 8'h1 << io_msInfo_6_bits_way
+             : 8'h0)
+        | (io_msInfo_7_valid & io_msInfo_7_bits_set == io_read_bits_set
+           & (io_msInfo_7_bits_blockRefill | io_msInfo_7_bits_dirHit)
+             ? 8'h1 << io_msInfo_7_bits_way
+             : 8'h0)
+        | (io_msInfo_8_valid & io_msInfo_8_bits_set == io_read_bits_set
+           & (io_msInfo_8_bits_blockRefill | io_msInfo_8_bits_dirHit)
+             ? 8'h1 << io_msInfo_8_bits_way
+             : 8'h0)
+        | (io_msInfo_9_valid & io_msInfo_9_bits_set == io_read_bits_set
+           & (io_msInfo_9_bits_blockRefill | io_msInfo_9_bits_dirHit)
+             ? 8'h1 << io_msInfo_9_bits_way
+             : 8'h0)
+        | (io_msInfo_10_valid & io_msInfo_10_bits_set == io_read_bits_set
+           & (io_msInfo_10_bits_blockRefill | io_msInfo_10_bits_dirHit)
+             ? 8'h1 << io_msInfo_10_bits_way
+             : 8'h0)
+        | (io_msInfo_11_valid & io_msInfo_11_bits_set == io_read_bits_set
+           & (io_msInfo_11_bits_blockRefill | io_msInfo_11_bits_dirHit)
+             ? 8'h1 << io_msInfo_11_bits_way
+             : 8'h0)
+        | (io_msInfo_12_valid & io_msInfo_12_bits_set == io_read_bits_set
+           & (io_msInfo_12_bits_blockRefill | io_msInfo_12_bits_dirHit)
+             ? 8'h1 << io_msInfo_12_bits_way
+             : 8'h0)
+        | (io_msInfo_13_valid & io_msInfo_13_bits_set == io_read_bits_set
+           & (io_msInfo_13_bits_blockRefill | io_msInfo_13_bits_dirHit)
+             ? 8'h1 << io_msInfo_13_bits_way
+             : 8'h0)
+        | (io_msInfo_14_valid & io_msInfo_14_bits_set == io_read_bits_set
+           & (io_msInfo_14_bits_blockRefill | io_msInfo_14_bits_dirHit)
+             ? 8'h1 << io_msInfo_14_bits_way
+             : 8'h0)
+        | (io_msInfo_15_valid & io_msInfo_15_bits_set == io_read_bits_set
+           & (io_msInfo_15_bits_blockRefill | io_msInfo_15_bits_dirHit)
+             ? 8'h1 << io_msInfo_15_bits_way
+             : 8'h0)
+        | (refillReqValid_s3 | reqValid_s3 & hit_s3
+             ? 8'h1 << {5'h0, |(io_wayOH_0[7:4]), |(_way_s3_T_1[2:1]), _way_s3_T_3}
+             : 8'h0);
+    if (refillReqValid_s2) begin
+      freeWayMask_s3 <= ~occWayMask_s2;
+      refillRetry <= &occWayMask_s2;
+    end
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:21];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h16; i += 5'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        reqValid_s2 = _RANDOM[5'h1][16];
+        reqValid_s3 = _RANDOM[5'h1][17];
+        req_s2_tag = {_RANDOM[5'h1][31:18], _RANDOM[5'h2][19:0]};
+        req_s2_set = _RANDOM[5'h2][27:20];
+        req_s2_replacerInfo_channel = _RANDOM[5'h3][6:4];
+        req_s2_replacerInfo_opcode = _RANDOM[5'h3][9:7];
+        req_s2_replacerInfo_reqSource = _RANDOM[5'h3][14:10];
+        req_s2_replacerInfo_refill_prefetch = _RANDOM[5'h3][15];
+        req_s2_refill = _RANDOM[5'h3][16];
+        req_s2_mshrId = _RANDOM[5'h3][24:17];
+        req_s2_cmoAll = _RANDOM[5'h3][25];
+        req_s2_cmoWay = _RANDOM[5'h3][28:26];
+        req_s3_tag = {_RANDOM[5'h3][31:29], _RANDOM[5'h4][30:0]};
+        req_s3_set = {_RANDOM[5'h4][31], _RANDOM[5'h5][6:0]};
+        req_s3_replacerInfo_channel = _RANDOM[5'h5][17:15];
+        req_s3_replacerInfo_opcode = _RANDOM[5'h5][20:18];
+        req_s3_replacerInfo_reqSource = _RANDOM[5'h5][25:21];
+        req_s3_replacerInfo_refill_prefetch = _RANDOM[5'h5][26];
+        req_s3_refill = _RANDOM[5'h5][27];
+        req_s3_mshrId = {_RANDOM[5'h5][31:28], _RANDOM[5'h6][3:0]};
+        req_s3_cmoAll = _RANDOM[5'h6][4];
+        cmoWayOH_s3 = _RANDOM[5'h6][15:8];
+        refillReqValid_s2 = _RANDOM[5'h6][16];
+        refillReqValid_s3 = _RANDOM[5'h6][17];
+        refillReqValid_hold_s3_REG = _RANDOM[5'h6][18];
+        refillReqValid_hold_s3 = _RANDOM[5'h6][19];
+        metaAll_s3_0_dirty = _RANDOM[5'h6][20];
+        metaAll_s3_0_state = _RANDOM[5'h6][22:21];
+        metaAll_s3_0_clients = _RANDOM[5'h6][23];
+        metaAll_s3_0_alias = _RANDOM[5'h6][24];
+        metaAll_s3_0_prefetch = _RANDOM[5'h6][25];
+        metaAll_s3_0_prefetchSrc = _RANDOM[5'h6][29:26];
+        metaAll_s3_0_accessed = _RANDOM[5'h6][30];
+        metaAll_s3_0_tagErr = _RANDOM[5'h6][31];
+        metaAll_s3_0_dataErr = _RANDOM[5'h7][0];
+        metaAll_s3_1_dirty = _RANDOM[5'h7][1];
+        metaAll_s3_1_state = _RANDOM[5'h7][3:2];
+        metaAll_s3_1_clients = _RANDOM[5'h7][4];
+        metaAll_s3_1_alias = _RANDOM[5'h7][5];
+        metaAll_s3_1_prefetch = _RANDOM[5'h7][6];
+        metaAll_s3_1_prefetchSrc = _RANDOM[5'h7][10:7];
+        metaAll_s3_1_accessed = _RANDOM[5'h7][11];
+        metaAll_s3_1_tagErr = _RANDOM[5'h7][12];
+        metaAll_s3_1_dataErr = _RANDOM[5'h7][13];
+        metaAll_s3_2_dirty = _RANDOM[5'h7][14];
+        metaAll_s3_2_state = _RANDOM[5'h7][16:15];
+        metaAll_s3_2_clients = _RANDOM[5'h7][17];
+        metaAll_s3_2_alias = _RANDOM[5'h7][18];
+        metaAll_s3_2_prefetch = _RANDOM[5'h7][19];
+        metaAll_s3_2_prefetchSrc = _RANDOM[5'h7][23:20];
+        metaAll_s3_2_accessed = _RANDOM[5'h7][24];
+        metaAll_s3_2_tagErr = _RANDOM[5'h7][25];
+        metaAll_s3_2_dataErr = _RANDOM[5'h7][26];
+        metaAll_s3_3_dirty = _RANDOM[5'h7][27];
+        metaAll_s3_3_state = _RANDOM[5'h7][29:28];
+        metaAll_s3_3_clients = _RANDOM[5'h7][30];
+        metaAll_s3_3_alias = _RANDOM[5'h7][31];
+        metaAll_s3_3_prefetch = _RANDOM[5'h8][0];
+        metaAll_s3_3_prefetchSrc = _RANDOM[5'h8][4:1];
+        metaAll_s3_3_accessed = _RANDOM[5'h8][5];
+        metaAll_s3_3_tagErr = _RANDOM[5'h8][6];
+        metaAll_s3_3_dataErr = _RANDOM[5'h8][7];
+        metaAll_s3_4_dirty = _RANDOM[5'h8][8];
+        metaAll_s3_4_state = _RANDOM[5'h8][10:9];
+        metaAll_s3_4_clients = _RANDOM[5'h8][11];
+        metaAll_s3_4_alias = _RANDOM[5'h8][12];
+        metaAll_s3_4_prefetch = _RANDOM[5'h8][13];
+        metaAll_s3_4_prefetchSrc = _RANDOM[5'h8][17:14];
+        metaAll_s3_4_accessed = _RANDOM[5'h8][18];
+        metaAll_s3_4_tagErr = _RANDOM[5'h8][19];
+        metaAll_s3_4_dataErr = _RANDOM[5'h8][20];
+        metaAll_s3_5_dirty = _RANDOM[5'h8][21];
+        metaAll_s3_5_state = _RANDOM[5'h8][23:22];
+        metaAll_s3_5_clients = _RANDOM[5'h8][24];
+        metaAll_s3_5_alias = _RANDOM[5'h8][25];
+        metaAll_s3_5_prefetch = _RANDOM[5'h8][26];
+        metaAll_s3_5_prefetchSrc = _RANDOM[5'h8][30:27];
+        metaAll_s3_5_accessed = _RANDOM[5'h8][31];
+        metaAll_s3_5_tagErr = _RANDOM[5'h9][0];
+        metaAll_s3_5_dataErr = _RANDOM[5'h9][1];
+        metaAll_s3_6_dirty = _RANDOM[5'h9][2];
+        metaAll_s3_6_state = _RANDOM[5'h9][4:3];
+        metaAll_s3_6_clients = _RANDOM[5'h9][5];
+        metaAll_s3_6_alias = _RANDOM[5'h9][6];
+        metaAll_s3_6_prefetch = _RANDOM[5'h9][7];
+        metaAll_s3_6_prefetchSrc = _RANDOM[5'h9][11:8];
+        metaAll_s3_6_accessed = _RANDOM[5'h9][12];
+        metaAll_s3_6_tagErr = _RANDOM[5'h9][13];
+        metaAll_s3_6_dataErr = _RANDOM[5'h9][14];
+        metaAll_s3_7_dirty = _RANDOM[5'h9][15];
+        metaAll_s3_7_state = _RANDOM[5'h9][17:16];
+        metaAll_s3_7_clients = _RANDOM[5'h9][18];
+        metaAll_s3_7_alias = _RANDOM[5'h9][19];
+        metaAll_s3_7_prefetch = _RANDOM[5'h9][20];
+        metaAll_s3_7_prefetchSrc = _RANDOM[5'h9][24:21];
+        metaAll_s3_7_accessed = _RANDOM[5'h9][25];
+        metaAll_s3_7_tagErr = _RANDOM[5'h9][26];
+        metaAll_s3_7_dataErr = _RANDOM[5'h9][27];
+        tagRead_s3_0 = {_RANDOM[5'h9][31:28], _RANDOM[5'hA], _RANDOM[5'hB][4:0]};
+        tagRead_s3_1 = {_RANDOM[5'hB][31:5], _RANDOM[5'hC][13:0]};
+        tagRead_s3_2 = {_RANDOM[5'hC][31:14], _RANDOM[5'hD][22:0]};
+        tagRead_s3_3 = {_RANDOM[5'hD][31:23], _RANDOM[5'hE]};
+        tagRead_s3_4 = {_RANDOM[5'hF], _RANDOM[5'h10][8:0]};
+        tagRead_s3_5 = {_RANDOM[5'h10][31:9], _RANDOM[5'h11][17:0]};
+        tagRead_s3_6 = {_RANDOM[5'h11][31:18], _RANDOM[5'h12][26:0]};
+        tagRead_s3_7 = {_RANDOM[5'h12][31:27], _RANDOM[5'h13], _RANDOM[5'h14][3:0]};
+        occWayMask_s2 = _RANDOM[5'h14][11:4];
+        freeWayMask_s3 = _RANDOM[5'h14][19:12];
+        refillRetry = _RANDOM[5'h14][20];
+        repl_state_s3 = {_RANDOM[5'h14][31:21], _RANDOM[5'h15][4:0]};
+        r_0 = _RANDOM[5'h15][5];
+        r_1 = _RANDOM[5'h15][6];
+        r_2 = _RANDOM[5'h15][7];
+        r_3 = _RANDOM[5'h15][8];
+        r_4 = _RANDOM[5'h15][9];
+        r_5 = _RANDOM[5'h15][10];
+        r_6 = _RANDOM[5'h15][11];
+        r_7 = _RANDOM[5'h15][12];
+        PSEL = _RANDOM[5'h15][22:13];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        reqValid_s2 = 1'h0;
+        reqValid_s3 = 1'h0;
+        req_s3_tag = 34'h0;
+        req_s3_set = 8'h0;
+        req_s3_replacerInfo_channel = 3'h0;
+        req_s3_replacerInfo_opcode = 3'h0;
+        req_s3_replacerInfo_reqSource = 5'h0;
+        req_s3_replacerInfo_refill_prefetch = 1'h0;
+        req_s3_refill = 1'h0;
+        req_s3_mshrId = 8'h0;
+        req_s3_cmoAll = 1'h0;
+        refillReqValid_s2 = 1'h0;
+        refillReqValid_s3 = 1'h0;
+        refillReqValid_hold_s3 = 1'h0;
+        metaAll_s3_0_dirty = 1'h0;
+        metaAll_s3_0_state = 2'h0;
+        metaAll_s3_0_clients = 1'h0;
+        metaAll_s3_0_alias = 1'h0;
+        metaAll_s3_0_prefetch = 1'h0;
+        metaAll_s3_0_prefetchSrc = 4'h0;
+        metaAll_s3_0_accessed = 1'h0;
+        metaAll_s3_0_tagErr = 1'h0;
+        metaAll_s3_0_dataErr = 1'h0;
+        metaAll_s3_1_dirty = 1'h0;
+        metaAll_s3_1_state = 2'h0;
+        metaAll_s3_1_clients = 1'h0;
+        metaAll_s3_1_alias = 1'h0;
+        metaAll_s3_1_prefetch = 1'h0;
+        metaAll_s3_1_prefetchSrc = 4'h0;
+        metaAll_s3_1_accessed = 1'h0;
+        metaAll_s3_1_tagErr = 1'h0;
+        metaAll_s3_1_dataErr = 1'h0;
+        metaAll_s3_2_dirty = 1'h0;
+        metaAll_s3_2_state = 2'h0;
+        metaAll_s3_2_clients = 1'h0;
+        metaAll_s3_2_alias = 1'h0;
+        metaAll_s3_2_prefetch = 1'h0;
+        metaAll_s3_2_prefetchSrc = 4'h0;
+        metaAll_s3_2_accessed = 1'h0;
+        metaAll_s3_2_tagErr = 1'h0;
+        metaAll_s3_2_dataErr = 1'h0;
+        metaAll_s3_3_dirty = 1'h0;
+        metaAll_s3_3_state = 2'h0;
+        metaAll_s3_3_clients = 1'h0;
+        metaAll_s3_3_alias = 1'h0;
+        metaAll_s3_3_prefetch = 1'h0;
+        metaAll_s3_3_prefetchSrc = 4'h0;
+        metaAll_s3_3_accessed = 1'h0;
+        metaAll_s3_3_tagErr = 1'h0;
+        metaAll_s3_3_dataErr = 1'h0;
+        metaAll_s3_4_dirty = 1'h0;
+        metaAll_s3_4_state = 2'h0;
+        metaAll_s3_4_clients = 1'h0;
+        metaAll_s3_4_alias = 1'h0;
+        metaAll_s3_4_prefetch = 1'h0;
+        metaAll_s3_4_prefetchSrc = 4'h0;
+        metaAll_s3_4_accessed = 1'h0;
+        metaAll_s3_4_tagErr = 1'h0;
+        metaAll_s3_4_dataErr = 1'h0;
+        metaAll_s3_5_dirty = 1'h0;
+        metaAll_s3_5_state = 2'h0;
+        metaAll_s3_5_clients = 1'h0;
+        metaAll_s3_5_alias = 1'h0;
+        metaAll_s3_5_prefetch = 1'h0;
+        metaAll_s3_5_prefetchSrc = 4'h0;
+        metaAll_s3_5_accessed = 1'h0;
+        metaAll_s3_5_tagErr = 1'h0;
+        metaAll_s3_5_dataErr = 1'h0;
+        metaAll_s3_6_dirty = 1'h0;
+        metaAll_s3_6_state = 2'h0;
+        metaAll_s3_6_clients = 1'h0;
+        metaAll_s3_6_alias = 1'h0;
+        metaAll_s3_6_prefetch = 1'h0;
+        metaAll_s3_6_prefetchSrc = 4'h0;
+        metaAll_s3_6_accessed = 1'h0;
+        metaAll_s3_6_tagErr = 1'h0;
+        metaAll_s3_6_dataErr = 1'h0;
+        metaAll_s3_7_dirty = 1'h0;
+        metaAll_s3_7_state = 2'h0;
+        metaAll_s3_7_clients = 1'h0;
+        metaAll_s3_7_alias = 1'h0;
+        metaAll_s3_7_prefetch = 1'h0;
+        metaAll_s3_7_prefetchSrc = 4'h0;
+        metaAll_s3_7_accessed = 1'h0;
+        metaAll_s3_7_tagErr = 1'h0;
+        metaAll_s3_7_dataErr = 1'h0;
+        repl_state_s3 = 16'h0;
+        PSEL = 10'h200;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  wire [8:0]   childBd_addr;
+  wire [8:0]   childBd_addr_rd;
+  wire [163:0] childBd_wdata;
+  wire [3:0]   childBd_wmask;
+  wire         childBd_re;
+  wire         childBd_we;
+  wire         childBd_ack;
+  wire         childBd_selectedOH;
+  wire [1:0]   childBd_array;
+  wire [8:0]   childBd_1_addr;
+  wire [8:0]   childBd_1_addr_rd;
+  wire [163:0] childBd_1_wdata;
+  wire [3:0]   childBd_1_wmask;
+  wire         childBd_1_re;
+  wire         childBd_1_we;
+  wire         childBd_1_ack;
+  wire         childBd_1_selectedOH;
+  wire [1:0]   childBd_1_array;
+  SplittedSRAM_3 tagArray (
+    .clock                            (clock),
+    .reset                            (reset),
+    .io_r_req_ready                   (/* unused */),
+    .io_r_req_valid                   (tagArray_io_r_req_valid),
+    .io_r_req_bits_setIdx             (io_read_bits_set),
+    .io_r_resp_data_0                 (_tagArray_io_r_resp_data_0),
+    .io_r_resp_data_1                 (_tagArray_io_r_resp_data_1),
+    .io_r_resp_data_2                 (_tagArray_io_r_resp_data_2),
+    .io_r_resp_data_3                 (_tagArray_io_r_resp_data_3),
+    .io_r_resp_data_4                 (_tagArray_io_r_resp_data_4),
+    .io_r_resp_data_5                 (_tagArray_io_r_resp_data_5),
+    .io_r_resp_data_6                 (_tagArray_io_r_resp_data_6),
+    .io_r_resp_data_7                 (_tagArray_io_r_resp_data_7),
+    .io_w_req_ready                   (/* unused */),
+    .io_w_req_valid                   (io_tagWReq_valid),
+    .io_w_req_bits_setIdx             (io_tagWReq_bits_set),
+    .io_w_req_bits_data_0             (tagWrite),
+    .io_w_req_bits_data_1             (tagWrite),
+    .io_w_req_bits_data_2             (tagWrite),
+    .io_w_req_bits_data_3             (tagWrite),
+    .io_w_req_bits_data_4             (tagWrite),
+    .io_w_req_bits_data_5             (tagWrite),
+    .io_w_req_bits_data_6             (tagWrite),
+    .io_w_req_bits_data_7             (tagWrite),
+    .io_w_req_bits_waymask            (io_tagWReq_bits_wayOH),
+    .boreChildrenBd_bore_addr         (childBd_addr),
+    .boreChildrenBd_bore_addr_rd      (childBd_addr_rd),
+    .boreChildrenBd_bore_wdata        (childBd_wdata),
+    .boreChildrenBd_bore_wmask        (childBd_wmask),
+    .boreChildrenBd_bore_re           (childBd_re),
+    .boreChildrenBd_bore_we           (childBd_we),
+    .boreChildrenBd_bore_rdata        (childBd_rdata),
+    .boreChildrenBd_bore_ack          (childBd_ack),
+    .boreChildrenBd_bore_selectedOH   (childBd_selectedOH),
+    .boreChildrenBd_bore_array        (childBd_array),
+    .boreChildrenBd_bore_1_addr       (childBd_1_addr),
+    .boreChildrenBd_bore_1_addr_rd    (childBd_1_addr_rd),
+    .boreChildrenBd_bore_1_wdata      (childBd_1_wdata),
+    .boreChildrenBd_bore_1_wmask      (childBd_1_wmask),
+    .boreChildrenBd_bore_1_re         (childBd_1_re),
+    .boreChildrenBd_bore_1_we         (childBd_1_we),
+    .boreChildrenBd_bore_1_rdata      (childBd_1_rdata),
+    .boreChildrenBd_bore_1_ack        (childBd_1_ack),
+    .boreChildrenBd_bore_1_selectedOH (childBd_1_selectedOH),
+    .boreChildrenBd_bore_1_array      (childBd_1_array),
+    .sigFromSrams_bore_ram_hold       (sigFromSrams_bore_ram_hold),
+    .sigFromSrams_bore_ram_bypass     (sigFromSrams_bore_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken   (sigFromSrams_bore_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk    (sigFromSrams_bore_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp   (sigFromSrams_bore_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold   (sigFromSrams_bore_ram_mcp_hold),
+    .sigFromSrams_bore_cgen           (sigFromSrams_bore_cgen),
+    .sigFromSrams_bore_1_ram_hold     (sigFromSrams_bore_1_ram_hold),
+    .sigFromSrams_bore_1_ram_bypass   (sigFromSrams_bore_1_ram_bypass),
+    .sigFromSrams_bore_1_ram_bp_clken (sigFromSrams_bore_1_ram_bp_clken),
+    .sigFromSrams_bore_1_ram_aux_clk  (sigFromSrams_bore_1_ram_aux_clk),
+    .sigFromSrams_bore_1_ram_aux_ckbp (sigFromSrams_bore_1_ram_aux_ckbp),
+    .sigFromSrams_bore_1_ram_mcp_hold (sigFromSrams_bore_1_ram_mcp_hold),
+    .sigFromSrams_bore_1_cgen         (sigFromSrams_bore_1_cgen)
+  );
+  wire [8:0]   childBd_2_addr;
+  wire [8:0]   childBd_2_addr_rd;
+  wire [103:0] childBd_2_wdata;
+  wire [7:0]   childBd_2_wmask;
+  wire         childBd_2_re;
+  wire         childBd_2_we;
+  wire         childBd_2_ack;
+  wire         childBd_2_selectedOH;
+  wire [2:0]   childBd_2_array;
+  SRAMTemplate_243 metaArray (
+    .clock                            (clock),
+    .reset                            (reset),
+    .io_r_req_ready                   (/* unused */),
+    .io_r_req_valid                   (tagArray_io_r_req_valid),
+    .io_r_req_bits_setIdx             (io_read_bits_set),
+    .io_r_resp_data_0_dirty           (_metaArray_io_r_resp_data_0_dirty),
+    .io_r_resp_data_0_state           (_metaArray_io_r_resp_data_0_state),
+    .io_r_resp_data_0_clients         (_metaArray_io_r_resp_data_0_clients),
+    .io_r_resp_data_0_alias           (_metaArray_io_r_resp_data_0_alias),
+    .io_r_resp_data_0_prefetch        (_metaArray_io_r_resp_data_0_prefetch),
+    .io_r_resp_data_0_prefetchSrc     (_metaArray_io_r_resp_data_0_prefetchSrc),
+    .io_r_resp_data_0_accessed        (_metaArray_io_r_resp_data_0_accessed),
+    .io_r_resp_data_0_tagErr          (_metaArray_io_r_resp_data_0_tagErr),
+    .io_r_resp_data_0_dataErr         (_metaArray_io_r_resp_data_0_dataErr),
+    .io_r_resp_data_1_dirty           (_metaArray_io_r_resp_data_1_dirty),
+    .io_r_resp_data_1_state           (_metaArray_io_r_resp_data_1_state),
+    .io_r_resp_data_1_clients         (_metaArray_io_r_resp_data_1_clients),
+    .io_r_resp_data_1_alias           (_metaArray_io_r_resp_data_1_alias),
+    .io_r_resp_data_1_prefetch        (_metaArray_io_r_resp_data_1_prefetch),
+    .io_r_resp_data_1_prefetchSrc     (_metaArray_io_r_resp_data_1_prefetchSrc),
+    .io_r_resp_data_1_accessed        (_metaArray_io_r_resp_data_1_accessed),
+    .io_r_resp_data_1_tagErr          (_metaArray_io_r_resp_data_1_tagErr),
+    .io_r_resp_data_1_dataErr         (_metaArray_io_r_resp_data_1_dataErr),
+    .io_r_resp_data_2_dirty           (_metaArray_io_r_resp_data_2_dirty),
+    .io_r_resp_data_2_state           (_metaArray_io_r_resp_data_2_state),
+    .io_r_resp_data_2_clients         (_metaArray_io_r_resp_data_2_clients),
+    .io_r_resp_data_2_alias           (_metaArray_io_r_resp_data_2_alias),
+    .io_r_resp_data_2_prefetch        (_metaArray_io_r_resp_data_2_prefetch),
+    .io_r_resp_data_2_prefetchSrc     (_metaArray_io_r_resp_data_2_prefetchSrc),
+    .io_r_resp_data_2_accessed        (_metaArray_io_r_resp_data_2_accessed),
+    .io_r_resp_data_2_tagErr          (_metaArray_io_r_resp_data_2_tagErr),
+    .io_r_resp_data_2_dataErr         (_metaArray_io_r_resp_data_2_dataErr),
+    .io_r_resp_data_3_dirty           (_metaArray_io_r_resp_data_3_dirty),
+    .io_r_resp_data_3_state           (_metaArray_io_r_resp_data_3_state),
+    .io_r_resp_data_3_clients         (_metaArray_io_r_resp_data_3_clients),
+    .io_r_resp_data_3_alias           (_metaArray_io_r_resp_data_3_alias),
+    .io_r_resp_data_3_prefetch        (_metaArray_io_r_resp_data_3_prefetch),
+    .io_r_resp_data_3_prefetchSrc     (_metaArray_io_r_resp_data_3_prefetchSrc),
+    .io_r_resp_data_3_accessed        (_metaArray_io_r_resp_data_3_accessed),
+    .io_r_resp_data_3_tagErr          (_metaArray_io_r_resp_data_3_tagErr),
+    .io_r_resp_data_3_dataErr         (_metaArray_io_r_resp_data_3_dataErr),
+    .io_r_resp_data_4_dirty           (_metaArray_io_r_resp_data_4_dirty),
+    .io_r_resp_data_4_state           (_metaArray_io_r_resp_data_4_state),
+    .io_r_resp_data_4_clients         (_metaArray_io_r_resp_data_4_clients),
+    .io_r_resp_data_4_alias           (_metaArray_io_r_resp_data_4_alias),
+    .io_r_resp_data_4_prefetch        (_metaArray_io_r_resp_data_4_prefetch),
+    .io_r_resp_data_4_prefetchSrc     (_metaArray_io_r_resp_data_4_prefetchSrc),
+    .io_r_resp_data_4_accessed        (_metaArray_io_r_resp_data_4_accessed),
+    .io_r_resp_data_4_tagErr          (_metaArray_io_r_resp_data_4_tagErr),
+    .io_r_resp_data_4_dataErr         (_metaArray_io_r_resp_data_4_dataErr),
+    .io_r_resp_data_5_dirty           (_metaArray_io_r_resp_data_5_dirty),
+    .io_r_resp_data_5_state           (_metaArray_io_r_resp_data_5_state),
+    .io_r_resp_data_5_clients         (_metaArray_io_r_resp_data_5_clients),
+    .io_r_resp_data_5_alias           (_metaArray_io_r_resp_data_5_alias),
+    .io_r_resp_data_5_prefetch        (_metaArray_io_r_resp_data_5_prefetch),
+    .io_r_resp_data_5_prefetchSrc     (_metaArray_io_r_resp_data_5_prefetchSrc),
+    .io_r_resp_data_5_accessed        (_metaArray_io_r_resp_data_5_accessed),
+    .io_r_resp_data_5_tagErr          (_metaArray_io_r_resp_data_5_tagErr),
+    .io_r_resp_data_5_dataErr         (_metaArray_io_r_resp_data_5_dataErr),
+    .io_r_resp_data_6_dirty           (_metaArray_io_r_resp_data_6_dirty),
+    .io_r_resp_data_6_state           (_metaArray_io_r_resp_data_6_state),
+    .io_r_resp_data_6_clients         (_metaArray_io_r_resp_data_6_clients),
+    .io_r_resp_data_6_alias           (_metaArray_io_r_resp_data_6_alias),
+    .io_r_resp_data_6_prefetch        (_metaArray_io_r_resp_data_6_prefetch),
+    .io_r_resp_data_6_prefetchSrc     (_metaArray_io_r_resp_data_6_prefetchSrc),
+    .io_r_resp_data_6_accessed        (_metaArray_io_r_resp_data_6_accessed),
+    .io_r_resp_data_6_tagErr          (_metaArray_io_r_resp_data_6_tagErr),
+    .io_r_resp_data_6_dataErr         (_metaArray_io_r_resp_data_6_dataErr),
+    .io_r_resp_data_7_dirty           (_metaArray_io_r_resp_data_7_dirty),
+    .io_r_resp_data_7_state           (_metaArray_io_r_resp_data_7_state),
+    .io_r_resp_data_7_clients         (_metaArray_io_r_resp_data_7_clients),
+    .io_r_resp_data_7_alias           (_metaArray_io_r_resp_data_7_alias),
+    .io_r_resp_data_7_prefetch        (_metaArray_io_r_resp_data_7_prefetch),
+    .io_r_resp_data_7_prefetchSrc     (_metaArray_io_r_resp_data_7_prefetchSrc),
+    .io_r_resp_data_7_accessed        (_metaArray_io_r_resp_data_7_accessed),
+    .io_r_resp_data_7_tagErr          (_metaArray_io_r_resp_data_7_tagErr),
+    .io_r_resp_data_7_dataErr         (_metaArray_io_r_resp_data_7_dataErr),
+    .io_w_req_ready                   (/* unused */),
+    .io_w_req_valid                   (io_metaWReq_valid),
+    .io_w_req_bits_setIdx             (io_metaWReq_bits_set),
+    .io_w_req_bits_data_0_dirty       (io_metaWReq_bits_wmeta_dirty),
+    .io_w_req_bits_data_0_state       (io_metaWReq_bits_wmeta_state),
+    .io_w_req_bits_data_0_clients     (io_metaWReq_bits_wmeta_clients),
+    .io_w_req_bits_data_0_alias       (io_metaWReq_bits_wmeta_alias),
+    .io_w_req_bits_data_0_prefetch    (io_metaWReq_bits_wmeta_prefetch),
+    .io_w_req_bits_data_0_prefetchSrc (io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_w_req_bits_data_0_accessed    (io_metaWReq_bits_wmeta_accessed),
+    .io_w_req_bits_data_0_tagErr      (io_metaWReq_bits_wmeta_tagErr),
+    .io_w_req_bits_data_0_dataErr     (io_metaWReq_bits_wmeta_dataErr),
+    .io_w_req_bits_data_1_dirty       (io_metaWReq_bits_wmeta_dirty),
+    .io_w_req_bits_data_1_state       (io_metaWReq_bits_wmeta_state),
+    .io_w_req_bits_data_1_clients     (io_metaWReq_bits_wmeta_clients),
+    .io_w_req_bits_data_1_alias       (io_metaWReq_bits_wmeta_alias),
+    .io_w_req_bits_data_1_prefetch    (io_metaWReq_bits_wmeta_prefetch),
+    .io_w_req_bits_data_1_prefetchSrc (io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_w_req_bits_data_1_accessed    (io_metaWReq_bits_wmeta_accessed),
+    .io_w_req_bits_data_1_tagErr      (io_metaWReq_bits_wmeta_tagErr),
+    .io_w_req_bits_data_1_dataErr     (io_metaWReq_bits_wmeta_dataErr),
+    .io_w_req_bits_data_2_dirty       (io_metaWReq_bits_wmeta_dirty),
+    .io_w_req_bits_data_2_state       (io_metaWReq_bits_wmeta_state),
+    .io_w_req_bits_data_2_clients     (io_metaWReq_bits_wmeta_clients),
+    .io_w_req_bits_data_2_alias       (io_metaWReq_bits_wmeta_alias),
+    .io_w_req_bits_data_2_prefetch    (io_metaWReq_bits_wmeta_prefetch),
+    .io_w_req_bits_data_2_prefetchSrc (io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_w_req_bits_data_2_accessed    (io_metaWReq_bits_wmeta_accessed),
+    .io_w_req_bits_data_2_tagErr      (io_metaWReq_bits_wmeta_tagErr),
+    .io_w_req_bits_data_2_dataErr     (io_metaWReq_bits_wmeta_dataErr),
+    .io_w_req_bits_data_3_dirty       (io_metaWReq_bits_wmeta_dirty),
+    .io_w_req_bits_data_3_state       (io_metaWReq_bits_wmeta_state),
+    .io_w_req_bits_data_3_clients     (io_metaWReq_bits_wmeta_clients),
+    .io_w_req_bits_data_3_alias       (io_metaWReq_bits_wmeta_alias),
+    .io_w_req_bits_data_3_prefetch    (io_metaWReq_bits_wmeta_prefetch),
+    .io_w_req_bits_data_3_prefetchSrc (io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_w_req_bits_data_3_accessed    (io_metaWReq_bits_wmeta_accessed),
+    .io_w_req_bits_data_3_tagErr      (io_metaWReq_bits_wmeta_tagErr),
+    .io_w_req_bits_data_3_dataErr     (io_metaWReq_bits_wmeta_dataErr),
+    .io_w_req_bits_data_4_dirty       (io_metaWReq_bits_wmeta_dirty),
+    .io_w_req_bits_data_4_state       (io_metaWReq_bits_wmeta_state),
+    .io_w_req_bits_data_4_clients     (io_metaWReq_bits_wmeta_clients),
+    .io_w_req_bits_data_4_alias       (io_metaWReq_bits_wmeta_alias),
+    .io_w_req_bits_data_4_prefetch    (io_metaWReq_bits_wmeta_prefetch),
+    .io_w_req_bits_data_4_prefetchSrc (io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_w_req_bits_data_4_accessed    (io_metaWReq_bits_wmeta_accessed),
+    .io_w_req_bits_data_4_tagErr      (io_metaWReq_bits_wmeta_tagErr),
+    .io_w_req_bits_data_4_dataErr     (io_metaWReq_bits_wmeta_dataErr),
+    .io_w_req_bits_data_5_dirty       (io_metaWReq_bits_wmeta_dirty),
+    .io_w_req_bits_data_5_state       (io_metaWReq_bits_wmeta_state),
+    .io_w_req_bits_data_5_clients     (io_metaWReq_bits_wmeta_clients),
+    .io_w_req_bits_data_5_alias       (io_metaWReq_bits_wmeta_alias),
+    .io_w_req_bits_data_5_prefetch    (io_metaWReq_bits_wmeta_prefetch),
+    .io_w_req_bits_data_5_prefetchSrc (io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_w_req_bits_data_5_accessed    (io_metaWReq_bits_wmeta_accessed),
+    .io_w_req_bits_data_5_tagErr      (io_metaWReq_bits_wmeta_tagErr),
+    .io_w_req_bits_data_5_dataErr     (io_metaWReq_bits_wmeta_dataErr),
+    .io_w_req_bits_data_6_dirty       (io_metaWReq_bits_wmeta_dirty),
+    .io_w_req_bits_data_6_state       (io_metaWReq_bits_wmeta_state),
+    .io_w_req_bits_data_6_clients     (io_metaWReq_bits_wmeta_clients),
+    .io_w_req_bits_data_6_alias       (io_metaWReq_bits_wmeta_alias),
+    .io_w_req_bits_data_6_prefetch    (io_metaWReq_bits_wmeta_prefetch),
+    .io_w_req_bits_data_6_prefetchSrc (io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_w_req_bits_data_6_accessed    (io_metaWReq_bits_wmeta_accessed),
+    .io_w_req_bits_data_6_tagErr      (io_metaWReq_bits_wmeta_tagErr),
+    .io_w_req_bits_data_6_dataErr     (io_metaWReq_bits_wmeta_dataErr),
+    .io_w_req_bits_data_7_dirty       (io_metaWReq_bits_wmeta_dirty),
+    .io_w_req_bits_data_7_state       (io_metaWReq_bits_wmeta_state),
+    .io_w_req_bits_data_7_clients     (io_metaWReq_bits_wmeta_clients),
+    .io_w_req_bits_data_7_alias       (io_metaWReq_bits_wmeta_alias),
+    .io_w_req_bits_data_7_prefetch    (io_metaWReq_bits_wmeta_prefetch),
+    .io_w_req_bits_data_7_prefetchSrc (io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_w_req_bits_data_7_accessed    (io_metaWReq_bits_wmeta_accessed),
+    .io_w_req_bits_data_7_tagErr      (io_metaWReq_bits_wmeta_tagErr),
+    .io_w_req_bits_data_7_dataErr     (io_metaWReq_bits_wmeta_dataErr),
+    .io_w_req_bits_waymask            (io_metaWReq_bits_wayOH),
+    .io_broadcast_ram_hold            (sigFromSrams_bore_2_ram_hold),
+    .io_broadcast_ram_bypass          (sigFromSrams_bore_2_ram_bypass),
+    .io_broadcast_ram_bp_clken        (sigFromSrams_bore_2_ram_bp_clken),
+    .io_broadcast_ram_aux_clk         (sigFromSrams_bore_2_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp        (sigFromSrams_bore_2_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold        (sigFromSrams_bore_2_ram_mcp_hold),
+    .io_broadcast_ram_ctl             (64'h0),
+    .io_broadcast_cgen                (sigFromSrams_bore_2_cgen),
+    .io_resetDone                     (/* unused */),
+    .boreChildrenBd_bore_addr         (childBd_2_addr),
+    .boreChildrenBd_bore_addr_rd      (childBd_2_addr_rd),
+    .boreChildrenBd_bore_wdata        (childBd_2_wdata),
+    .boreChildrenBd_bore_wmask        (childBd_2_wmask),
+    .boreChildrenBd_bore_re           (childBd_2_re),
+    .boreChildrenBd_bore_we           (childBd_2_we),
+    .boreChildrenBd_bore_rdata        (childBd_2_rdata),
+    .boreChildrenBd_bore_ack          (childBd_2_ack),
+    .boreChildrenBd_bore_selectedOH   (childBd_2_selectedOH),
+    .boreChildrenBd_bore_array        (childBd_2_array)
+  );
+  wire [8:0]   childBd_3_addr;
+  wire [8:0]   childBd_3_addr_rd;
+  wire [15:0]  childBd_3_wdata;
+  wire         childBd_3_wmask;
+  wire         childBd_3_re;
+  wire         childBd_3_we;
+  wire         childBd_3_ack;
+  wire         childBd_3_selectedOH;
+  wire [2:0]   childBd_3_array;
+  SRAMTemplate_244 replacer_sram_opt (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_valid                 (tagArray_io_r_req_valid),
+    .io_r_req_bits_setIdx           (io_read_bits_set),
+    .io_r_resp_data_0               (_replacer_sram_opt_io_r_resp_data_0),
+    .io_w_req_valid                 (replacerWen),
+    .io_w_req_bits_setIdx           (req_s3_set),
+    .io_w_req_bits_data_0
+      (~match_a & (match_b | PSEL[9])
+         ? {io_wayOH_0[7]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h3
+                           : repl_state_s3[15:14])
+              : (|_GEN)
+                  ? repl_state_s3[15:14]
+                  : 2'(repl_state_s3[15:14] + _next_state_s3_increcement_T_23),
+            io_wayOH_0[6]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h3
+                           : repl_state_s3[13:12])
+              : (|_GEN)
+                  ? repl_state_s3[13:12]
+                  : 2'(repl_state_s3[13:12] + _next_state_s3_increcement_T_23),
+            io_wayOH_0[5]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h3
+                           : repl_state_s3[11:10])
+              : (|_GEN)
+                  ? repl_state_s3[11:10]
+                  : 2'(repl_state_s3[11:10] + _next_state_s3_increcement_T_23),
+            io_wayOH_0[4]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h3
+                           : repl_state_s3[9:8])
+              : (|_GEN)
+                  ? repl_state_s3[9:8]
+                  : 2'(repl_state_s3[9:8] + _next_state_s3_increcement_T_23),
+            io_wayOH_0[3]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h3
+                           : repl_state_s3[7:6])
+              : (|_GEN)
+                  ? repl_state_s3[7:6]
+                  : 2'(repl_state_s3[7:6] + _next_state_s3_increcement_T_23),
+            io_wayOH_0[2]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h3
+                           : repl_state_s3[5:4])
+              : (|_GEN)
+                  ? repl_state_s3[5:4]
+                  : 2'(repl_state_s3[5:4] + _next_state_s3_increcement_T_23),
+            io_wayOH_0[1]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h3
+                           : repl_state_s3[3:2])
+              : (|_GEN)
+                  ? repl_state_s3[3:2]
+                  : 2'(repl_state_s3[3:2] + _next_state_s3_increcement_T_23),
+            io_wayOH_0[0]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h3
+                           : repl_state_s3[1:0])
+              : (|_GEN)
+                  ? repl_state_s3[1:0]
+                  : 2'(repl_state_s3[1:0] + _next_state_s3_increcement_T_23)}
+         : {io_wayOH_0[7]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h2
+                           : repl_state_s3[15:14])
+              : (|_GEN)
+                  ? repl_state_s3[15:14]
+                  : 2'(repl_state_s3[15:14] + _next_state_s3_increcement_T_47),
+            io_wayOH_0[6]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h2
+                           : repl_state_s3[13:12])
+              : (|_GEN)
+                  ? repl_state_s3[13:12]
+                  : 2'(repl_state_s3[13:12] + _next_state_s3_increcement_T_47),
+            io_wayOH_0[5]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h2
+                           : repl_state_s3[11:10])
+              : (|_GEN)
+                  ? repl_state_s3[11:10]
+                  : 2'(repl_state_s3[11:10] + _next_state_s3_increcement_T_47),
+            io_wayOH_0[4]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h2
+                           : repl_state_s3[9:8])
+              : (|_GEN)
+                  ? repl_state_s3[9:8]
+                  : 2'(repl_state_s3[9:8] + _next_state_s3_increcement_T_47),
+            io_wayOH_0[3]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h2
+                           : repl_state_s3[7:6])
+              : (|_GEN)
+                  ? repl_state_s3[7:6]
+                  : 2'(repl_state_s3[7:6] + _next_state_s3_increcement_T_47),
+            io_wayOH_0[2]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h2
+                           : repl_state_s3[5:4])
+              : (|_GEN)
+                  ? repl_state_s3[5:4]
+                  : 2'(repl_state_s3[5:4] + _next_state_s3_increcement_T_47),
+            io_wayOH_0[1]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h2
+                           : repl_state_s3[3:2])
+              : (|_GEN)
+                  ? repl_state_s3[3:2]
+                  : 2'(repl_state_s3[3:2] + _next_state_s3_increcement_T_47),
+            io_wayOH_0[0]
+              ? (~(|_next_state_s3_nextState_7_T_33) & hit_s3
+                 | _next_state_s3_nextState_7_T_33 == 3'h1
+                 | _next_state_s3_nextState_7_T_28
+                   ? 2'h0
+                   : _next_state_s3_nextState_7_T_33 == 3'h3
+                       ? 2'h1
+                       : _next_state_s3_nextState_7_T_32
+                         | _next_state_s3_nextState_7_T_33 == 3'h6
+                           ? 2'h2
+                           : repl_state_s3[1:0])
+              : (|_GEN)
+                  ? repl_state_s3[1:0]
+                  : 2'(repl_state_s3[1:0] + _next_state_s3_increcement_T_47)}),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_3_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_3_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_3_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_3_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_3_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_3_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_3_cgen),
+    .boreChildrenBd_bore_addr       (childBd_3_addr),
+    .boreChildrenBd_bore_addr_rd    (childBd_3_addr_rd),
+    .boreChildrenBd_bore_wdata      (childBd_3_wdata),
+    .boreChildrenBd_bore_wmask      (childBd_3_wmask),
+    .boreChildrenBd_bore_re         (childBd_3_re),
+    .boreChildrenBd_bore_we         (childBd_3_we),
+    .boreChildrenBd_bore_rdata      (childBd_3_rdata),
+    .boreChildrenBd_bore_ack        (childBd_3_ack),
+    .boreChildrenBd_bore_selectedOH (childBd_3_selectedOH),
+    .boreChildrenBd_bore_array      (childBd_3_array)
+  );
+  wire [8:0]   childBd_4_addr;
+  wire [8:0]   childBd_4_addr_rd;
+  wire [7:0]   childBd_4_wdata;
+  wire [7:0]   childBd_4_wmask;
+  wire         childBd_4_re;
+  wire         childBd_4_we;
+  wire         childBd_4_ack;
+  wire         childBd_4_selectedOH;
+  wire [2:0]   childBd_4_array;
+  SRAMTemplate_245 origin_bit_opt (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_valid                 (tagArray_io_r_req_valid),
+    .io_r_req_bits_setIdx           (io_read_bits_set),
+    .io_r_resp_data_0               (_origin_bit_opt_io_r_resp_data_0),
+    .io_r_resp_data_1               (_origin_bit_opt_io_r_resp_data_1),
+    .io_r_resp_data_2               (_origin_bit_opt_io_r_resp_data_2),
+    .io_r_resp_data_3               (_origin_bit_opt_io_r_resp_data_3),
+    .io_r_resp_data_4               (_origin_bit_opt_io_r_resp_data_4),
+    .io_r_resp_data_5               (_origin_bit_opt_io_r_resp_data_5),
+    .io_r_resp_data_6               (_origin_bit_opt_io_r_resp_data_6),
+    .io_r_resp_data_7               (_origin_bit_opt_io_r_resp_data_7),
+    .io_w_req_valid                 (replacerWen),
+    .io_w_req_bits_setIdx           (req_s3_set),
+    .io_w_req_bits_data_0           (hit_s3),
+    .io_w_req_bits_data_1           (hit_s3),
+    .io_w_req_bits_data_2           (hit_s3),
+    .io_w_req_bits_data_3           (hit_s3),
+    .io_w_req_bits_data_4           (hit_s3),
+    .io_w_req_bits_data_5           (hit_s3),
+    .io_w_req_bits_data_6           (hit_s3),
+    .io_w_req_bits_data_7           (hit_s3),
+    .io_w_req_bits_waymask          (io_wayOH_0),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_4_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_4_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_4_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_4_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_4_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_4_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_4_cgen),
+    .boreChildrenBd_bore_addr       (childBd_4_addr),
+    .boreChildrenBd_bore_addr_rd    (childBd_4_addr_rd),
+    .boreChildrenBd_bore_wdata      (childBd_4_wdata),
+    .boreChildrenBd_bore_wmask      (childBd_4_wmask),
+    .boreChildrenBd_bore_re         (childBd_4_re),
+    .boreChildrenBd_bore_we         (childBd_4_we),
+    .boreChildrenBd_bore_rdata      (childBd_4_rdata),
+    .boreChildrenBd_bore_ack        (childBd_4_ack),
+    .boreChildrenBd_bore_selectedOH (childBd_4_selectedOH),
+    .boreChildrenBd_bore_array      (childBd_4_array)
+  );
+  L2Directory mbistPl (
+    .clock               (clock),
+    .reset               (reset),
+    .mbist_array         (bd_array),
+    .mbist_all           (bd_all),
+    .mbist_req           (bd_req),
+    .mbist_ack           (bd_ack),
+    .mbist_writeen       (bd_writeen),
+    .mbist_be            (bd_be),
+    .mbist_addr          (bd_addr),
+    .mbist_indata        (bd_indata),
+    .mbist_readen        (bd_readen),
+    .mbist_addr_rd       (bd_addr_rd),
+    .mbist_outdata       (bd_outdata),
+    .toSRAM_0_addr       (childBd_addr),
+    .toSRAM_0_addr_rd    (childBd_addr_rd),
+    .toSRAM_0_wdata      (childBd_wdata),
+    .toSRAM_0_wmask      (childBd_wmask),
+    .toSRAM_0_re         (childBd_re),
+    .toSRAM_0_we         (childBd_we),
+    .toSRAM_0_rdata      (childBd_rdata),
+    .toSRAM_0_ack        (childBd_ack),
+    .toSRAM_0_selectedOH (childBd_selectedOH),
+    .toSRAM_0_array      (childBd_array),
+    .toSRAM_1_addr       (childBd_1_addr),
+    .toSRAM_1_addr_rd    (childBd_1_addr_rd),
+    .toSRAM_1_wdata      (childBd_1_wdata),
+    .toSRAM_1_wmask      (childBd_1_wmask),
+    .toSRAM_1_re         (childBd_1_re),
+    .toSRAM_1_we         (childBd_1_we),
+    .toSRAM_1_rdata      (childBd_1_rdata),
+    .toSRAM_1_ack        (childBd_1_ack),
+    .toSRAM_1_selectedOH (childBd_1_selectedOH),
+    .toSRAM_1_array      (childBd_1_array),
+    .toSRAM_2_addr       (childBd_2_addr),
+    .toSRAM_2_addr_rd    (childBd_2_addr_rd),
+    .toSRAM_2_wdata      (childBd_2_wdata),
+    .toSRAM_2_wmask      (childBd_2_wmask),
+    .toSRAM_2_re         (childBd_2_re),
+    .toSRAM_2_we         (childBd_2_we),
+    .toSRAM_2_rdata      (childBd_2_rdata),
+    .toSRAM_2_ack        (childBd_2_ack),
+    .toSRAM_2_selectedOH (childBd_2_selectedOH),
+    .toSRAM_2_array      (childBd_2_array),
+    .toSRAM_3_addr       (childBd_3_addr),
+    .toSRAM_3_addr_rd    (childBd_3_addr_rd),
+    .toSRAM_3_wdata      (childBd_3_wdata),
+    .toSRAM_3_wmask      (childBd_3_wmask),
+    .toSRAM_3_re         (childBd_3_re),
+    .toSRAM_3_we         (childBd_3_we),
+    .toSRAM_3_rdata      (childBd_3_rdata),
+    .toSRAM_3_ack        (childBd_3_ack),
+    .toSRAM_3_selectedOH (childBd_3_selectedOH),
+    .toSRAM_3_array      (childBd_3_array),
+    .toSRAM_4_addr       (childBd_4_addr),
+    .toSRAM_4_addr_rd    (childBd_4_addr_rd),
+    .toSRAM_4_wdata      (childBd_4_wdata),
+    .toSRAM_4_wmask      (childBd_4_wmask),
+    .toSRAM_4_re         (childBd_4_re),
+    .toSRAM_4_we         (childBd_4_we),
+    .toSRAM_4_rdata      (childBd_4_rdata),
+    .toSRAM_4_ack        (childBd_4_ack),
+    .toSRAM_4_selectedOH (childBd_4_selectedOH),
+    .toSRAM_4_array      (childBd_4_array)
+  );
+  assign io_read_ready = io_read_ready_0;
+  assign io_resp_valid = reqValid_s3;
+  assign io_resp_bits_hit = hit_s3;
+  assign io_resp_bits_tag =
+    (io_wayOH_0[0] ? tagRead_s3_0[33:0] : 34'h0)
+    | (io_wayOH_0[1] ? tagRead_s3_1[33:0] : 34'h0)
+    | (io_wayOH_0[2] ? tagRead_s3_2[33:0] : 34'h0)
+    | (io_wayOH_0[3] ? tagRead_s3_3[33:0] : 34'h0)
+    | (io_wayOH_0[4] ? tagRead_s3_4[33:0] : 34'h0)
+    | (io_wayOH_0[5] ? tagRead_s3_5[33:0] : 34'h0)
+    | (io_wayOH_0[6] ? tagRead_s3_6[33:0] : 34'h0)
+    | (io_wayOH_0[7] ? tagRead_s3_7[33:0] : 34'h0);
+  assign io_resp_bits_set = req_s3_set;
+  assign io_resp_bits_way = {|(io_wayOH_0[7:4]), |(_way_s3_T_1[2:1]), _way_s3_T_3};
+  assign io_resp_bits_meta_dirty =
+    io_wayOH_0[0] & metaAll_s3_0_dirty | io_wayOH_0[1] & metaAll_s3_1_dirty
+    | io_wayOH_0[2] & metaAll_s3_2_dirty | io_wayOH_0[3] & metaAll_s3_3_dirty
+    | io_wayOH_0[4] & metaAll_s3_4_dirty | io_wayOH_0[5] & metaAll_s3_5_dirty
+    | io_wayOH_0[6] & metaAll_s3_6_dirty | io_wayOH_0[7] & metaAll_s3_7_dirty;
+  assign io_resp_bits_meta_state = meta_s3_state;
+  assign io_resp_bits_meta_clients =
+    io_wayOH_0[0] & metaAll_s3_0_clients | io_wayOH_0[1] & metaAll_s3_1_clients
+    | io_wayOH_0[2] & metaAll_s3_2_clients | io_wayOH_0[3] & metaAll_s3_3_clients
+    | io_wayOH_0[4] & metaAll_s3_4_clients | io_wayOH_0[5] & metaAll_s3_5_clients
+    | io_wayOH_0[6] & metaAll_s3_6_clients | io_wayOH_0[7] & metaAll_s3_7_clients;
+  assign io_resp_bits_meta_alias =
+    io_wayOH_0[0] & metaAll_s3_0_alias | io_wayOH_0[1] & metaAll_s3_1_alias
+    | io_wayOH_0[2] & metaAll_s3_2_alias | io_wayOH_0[3] & metaAll_s3_3_alias
+    | io_wayOH_0[4] & metaAll_s3_4_alias | io_wayOH_0[5] & metaAll_s3_5_alias
+    | io_wayOH_0[6] & metaAll_s3_6_alias | io_wayOH_0[7] & metaAll_s3_7_alias;
+  assign io_resp_bits_meta_prefetch =
+    io_wayOH_0[0] & metaAll_s3_0_prefetch | io_wayOH_0[1] & metaAll_s3_1_prefetch
+    | io_wayOH_0[2] & metaAll_s3_2_prefetch | io_wayOH_0[3] & metaAll_s3_3_prefetch
+    | io_wayOH_0[4] & metaAll_s3_4_prefetch | io_wayOH_0[5] & metaAll_s3_5_prefetch
+    | io_wayOH_0[6] & metaAll_s3_6_prefetch | io_wayOH_0[7] & metaAll_s3_7_prefetch;
+  assign io_resp_bits_meta_prefetchSrc =
+    (io_wayOH_0[0] ? metaAll_s3_0_prefetchSrc : 4'h0)
+    | (io_wayOH_0[1] ? metaAll_s3_1_prefetchSrc : 4'h0)
+    | (io_wayOH_0[2] ? metaAll_s3_2_prefetchSrc : 4'h0)
+    | (io_wayOH_0[3] ? metaAll_s3_3_prefetchSrc : 4'h0)
+    | (io_wayOH_0[4] ? metaAll_s3_4_prefetchSrc : 4'h0)
+    | (io_wayOH_0[5] ? metaAll_s3_5_prefetchSrc : 4'h0)
+    | (io_wayOH_0[6] ? metaAll_s3_6_prefetchSrc : 4'h0)
+    | (io_wayOH_0[7] ? metaAll_s3_7_prefetchSrc : 4'h0);
+  assign io_resp_bits_meta_accessed =
+    io_wayOH_0[0] & metaAll_s3_0_accessed | io_wayOH_0[1] & metaAll_s3_1_accessed
+    | io_wayOH_0[2] & metaAll_s3_2_accessed | io_wayOH_0[3] & metaAll_s3_3_accessed
+    | io_wayOH_0[4] & metaAll_s3_4_accessed | io_wayOH_0[5] & metaAll_s3_5_accessed
+    | io_wayOH_0[6] & metaAll_s3_6_accessed | io_wayOH_0[7] & metaAll_s3_7_accessed;
+  assign io_resp_bits_meta_tagErr =
+    io_wayOH_0[0] & metaAll_s3_0_tagErr | io_wayOH_0[1] & metaAll_s3_1_tagErr
+    | io_wayOH_0[2] & metaAll_s3_2_tagErr | io_wayOH_0[3] & metaAll_s3_3_tagErr
+    | io_wayOH_0[4] & metaAll_s3_4_tagErr | io_wayOH_0[5] & metaAll_s3_5_tagErr
+    | io_wayOH_0[6] & metaAll_s3_6_tagErr | io_wayOH_0[7] & metaAll_s3_7_tagErr;
+  assign io_resp_bits_meta_dataErr =
+    io_wayOH_0[0] & metaAll_s3_0_dataErr | io_wayOH_0[1] & metaAll_s3_1_dataErr
+    | io_wayOH_0[2] & metaAll_s3_2_dataErr | io_wayOH_0[3] & metaAll_s3_3_dataErr
+    | io_wayOH_0[4] & metaAll_s3_4_dataErr | io_wayOH_0[5] & metaAll_s3_5_dataErr
+    | io_wayOH_0[6] & metaAll_s3_6_dataErr | io_wayOH_0[7] & metaAll_s3_7_dataErr;
+  assign io_resp_bits_error =
+    (io_wayOH_0[0] & errorAll_s3_0 | io_wayOH_0[1] & errorAll_s3_1 | io_wayOH_0[2]
+     & errorAll_s3_2 | io_wayOH_0[3] & errorAll_s3_3 | io_wayOH_0[4] & errorAll_s3_4
+     | io_wayOH_0[5] & errorAll_s3_5 | io_wayOH_0[6] & errorAll_s3_6 | io_wayOH_0[7]
+     & errorAll_s3_7) & reqValid_s3 & ~req_s3_cmoAll & (|meta_s3_state);
+  assign io_resp_bits_replacerInfo_channel = req_s3_replacerInfo_channel;
+  assign io_resp_bits_replacerInfo_opcode = req_s3_replacerInfo_opcode;
+  assign io_resp_bits_replacerInfo_reqSource = req_s3_replacerInfo_reqSource;
+  assign io_resp_bits_replacerInfo_refill_prefetch = req_s3_replacerInfo_refill_prefetch;
+  assign io_replResp_valid = refillReqValid_s3;
+  assign io_replResp_bits_tag =
+    (finalReplOH[0] ? tagRead_s3_0[33:0] : 34'h0)
+    | (finalReplOH[1] ? tagRead_s3_1[33:0] : 34'h0)
+    | (finalReplOH[2] ? tagRead_s3_2[33:0] : 34'h0)
+    | (finalReplOH[3] ? tagRead_s3_3[33:0] : 34'h0)
+    | (finalReplOH[4] ? tagRead_s3_4[33:0] : 34'h0)
+    | (finalReplOH[5] ? tagRead_s3_5[33:0] : 34'h0)
+    | (finalReplOH[6] ? tagRead_s3_6[33:0] : 34'h0)
+    | (finalReplOH[7] ? tagRead_s3_7[33:0] : 34'h0);
+  assign io_replResp_bits_set = req_s3_set;
+  assign io_replResp_bits_way =
+    {|(finalReplOH[7:4]),
+     |(_io_replResp_bits_way_T_1[2:1]),
+     _io_replResp_bits_way_T_1[2] | _io_replResp_bits_way_T_1[0]};
+  assign io_replResp_bits_meta_dirty =
+    finalReplOH[0] & metaAll_s3_0_dirty | finalReplOH[1] & metaAll_s3_1_dirty
+    | finalReplOH[2] & metaAll_s3_2_dirty | finalReplOH[3] & metaAll_s3_3_dirty
+    | finalReplOH[4] & metaAll_s3_4_dirty | finalReplOH[5] & metaAll_s3_5_dirty
+    | finalReplOH[6] & metaAll_s3_6_dirty | finalReplOH[7] & metaAll_s3_7_dirty;
+  assign io_replResp_bits_meta_state =
+    (finalReplOH[0] ? metaAll_s3_0_state : 2'h0)
+    | (finalReplOH[1] ? metaAll_s3_1_state : 2'h0)
+    | (finalReplOH[2] ? metaAll_s3_2_state : 2'h0)
+    | (finalReplOH[3] ? metaAll_s3_3_state : 2'h0)
+    | (finalReplOH[4] ? metaAll_s3_4_state : 2'h0)
+    | (finalReplOH[5] ? metaAll_s3_5_state : 2'h0)
+    | (finalReplOH[6] ? metaAll_s3_6_state : 2'h0)
+    | (finalReplOH[7] ? metaAll_s3_7_state : 2'h0);
+  assign io_replResp_bits_meta_clients =
+    finalReplOH[0] & metaAll_s3_0_clients | finalReplOH[1] & metaAll_s3_1_clients
+    | finalReplOH[2] & metaAll_s3_2_clients | finalReplOH[3] & metaAll_s3_3_clients
+    | finalReplOH[4] & metaAll_s3_4_clients | finalReplOH[5] & metaAll_s3_5_clients
+    | finalReplOH[6] & metaAll_s3_6_clients | finalReplOH[7] & metaAll_s3_7_clients;
+  assign io_replResp_bits_meta_alias =
+    finalReplOH[0] & metaAll_s3_0_alias | finalReplOH[1] & metaAll_s3_1_alias
+    | finalReplOH[2] & metaAll_s3_2_alias | finalReplOH[3] & metaAll_s3_3_alias
+    | finalReplOH[4] & metaAll_s3_4_alias | finalReplOH[5] & metaAll_s3_5_alias
+    | finalReplOH[6] & metaAll_s3_6_alias | finalReplOH[7] & metaAll_s3_7_alias;
+  assign io_replResp_bits_meta_prefetch =
+    finalReplOH[0] & metaAll_s3_0_prefetch | finalReplOH[1] & metaAll_s3_1_prefetch
+    | finalReplOH[2] & metaAll_s3_2_prefetch | finalReplOH[3] & metaAll_s3_3_prefetch
+    | finalReplOH[4] & metaAll_s3_4_prefetch | finalReplOH[5] & metaAll_s3_5_prefetch
+    | finalReplOH[6] & metaAll_s3_6_prefetch | finalReplOH[7] & metaAll_s3_7_prefetch;
+  assign io_replResp_bits_meta_prefetchSrc =
+    (finalReplOH[0] ? metaAll_s3_0_prefetchSrc : 4'h0)
+    | (finalReplOH[1] ? metaAll_s3_1_prefetchSrc : 4'h0)
+    | (finalReplOH[2] ? metaAll_s3_2_prefetchSrc : 4'h0)
+    | (finalReplOH[3] ? metaAll_s3_3_prefetchSrc : 4'h0)
+    | (finalReplOH[4] ? metaAll_s3_4_prefetchSrc : 4'h0)
+    | (finalReplOH[5] ? metaAll_s3_5_prefetchSrc : 4'h0)
+    | (finalReplOH[6] ? metaAll_s3_6_prefetchSrc : 4'h0)
+    | (finalReplOH[7] ? metaAll_s3_7_prefetchSrc : 4'h0);
+  assign io_replResp_bits_meta_accessed =
+    finalReplOH[0] & metaAll_s3_0_accessed | finalReplOH[1] & metaAll_s3_1_accessed
+    | finalReplOH[2] & metaAll_s3_2_accessed | finalReplOH[3] & metaAll_s3_3_accessed
+    | finalReplOH[4] & metaAll_s3_4_accessed | finalReplOH[5] & metaAll_s3_5_accessed
+    | finalReplOH[6] & metaAll_s3_6_accessed | finalReplOH[7] & metaAll_s3_7_accessed;
+  assign io_replResp_bits_meta_tagErr =
+    finalReplOH[0] & metaAll_s3_0_tagErr | finalReplOH[1] & metaAll_s3_1_tagErr
+    | finalReplOH[2] & metaAll_s3_2_tagErr | finalReplOH[3] & metaAll_s3_3_tagErr
+    | finalReplOH[4] & metaAll_s3_4_tagErr | finalReplOH[5] & metaAll_s3_5_tagErr
+    | finalReplOH[6] & metaAll_s3_6_tagErr | finalReplOH[7] & metaAll_s3_7_tagErr;
+  assign io_replResp_bits_meta_dataErr =
+    finalReplOH[0] & metaAll_s3_0_dataErr | finalReplOH[1] & metaAll_s3_1_dataErr
+    | finalReplOH[2] & metaAll_s3_2_dataErr | finalReplOH[3] & metaAll_s3_3_dataErr
+    | finalReplOH[4] & metaAll_s3_4_dataErr | finalReplOH[5] & metaAll_s3_5_dataErr
+    | finalReplOH[6] & metaAll_s3_6_dataErr | finalReplOH[7] & metaAll_s3_7_dataErr;
+  assign io_replResp_bits_mshrId = req_s3_mshrId;
+  assign io_replResp_bits_retry = refillRetry;
+  assign io_replResp_bits_validHold = refillReqValid_hold_s3;
+  assign io_metaOnHit_dirty =
+    hitVec_0 & metaAll_s3_0_dirty | hitVec_1 & metaAll_s3_1_dirty | hitVec_2
+    & metaAll_s3_2_dirty | hitVec_3 & metaAll_s3_3_dirty | hitVec_4 & metaAll_s3_4_dirty
+    | hitVec_5 & metaAll_s3_5_dirty | hitVec_6 & metaAll_s3_6_dirty | hitVec_7
+    & metaAll_s3_7_dirty;
+  assign io_metaOnHit_state =
+    (hitVec_0 ? metaAll_s3_0_state : 2'h0) | (hitVec_1 ? metaAll_s3_1_state : 2'h0)
+    | (hitVec_2 ? metaAll_s3_2_state : 2'h0) | (hitVec_3 ? metaAll_s3_3_state : 2'h0)
+    | (hitVec_4 ? metaAll_s3_4_state : 2'h0) | (hitVec_5 ? metaAll_s3_5_state : 2'h0)
+    | (hitVec_6 ? metaAll_s3_6_state : 2'h0) | (hitVec_7 ? metaAll_s3_7_state : 2'h0);
+  assign io_metaOnHit_clients =
+    hitVec_0 & metaAll_s3_0_clients | hitVec_1 & metaAll_s3_1_clients | hitVec_2
+    & metaAll_s3_2_clients | hitVec_3 & metaAll_s3_3_clients | hitVec_4
+    & metaAll_s3_4_clients | hitVec_5 & metaAll_s3_5_clients | hitVec_6
+    & metaAll_s3_6_clients | hitVec_7 & metaAll_s3_7_clients;
+  assign io_metaOnHit_alias =
+    hitVec_0 & metaAll_s3_0_alias | hitVec_1 & metaAll_s3_1_alias | hitVec_2
+    & metaAll_s3_2_alias | hitVec_3 & metaAll_s3_3_alias | hitVec_4 & metaAll_s3_4_alias
+    | hitVec_5 & metaAll_s3_5_alias | hitVec_6 & metaAll_s3_6_alias | hitVec_7
+    & metaAll_s3_7_alias;
+  assign io_metaOnHit_prefetch =
+    hitVec_0 & metaAll_s3_0_prefetch | hitVec_1 & metaAll_s3_1_prefetch | hitVec_2
+    & metaAll_s3_2_prefetch | hitVec_3 & metaAll_s3_3_prefetch | hitVec_4
+    & metaAll_s3_4_prefetch | hitVec_5 & metaAll_s3_5_prefetch | hitVec_6
+    & metaAll_s3_6_prefetch | hitVec_7 & metaAll_s3_7_prefetch;
+  assign io_metaOnHit_prefetchSrc =
+    (hitVec_0 ? metaAll_s3_0_prefetchSrc : 4'h0)
+    | (hitVec_1 ? metaAll_s3_1_prefetchSrc : 4'h0)
+    | (hitVec_2 ? metaAll_s3_2_prefetchSrc : 4'h0)
+    | (hitVec_3 ? metaAll_s3_3_prefetchSrc : 4'h0)
+    | (hitVec_4 ? metaAll_s3_4_prefetchSrc : 4'h0)
+    | (hitVec_5 ? metaAll_s3_5_prefetchSrc : 4'h0)
+    | (hitVec_6 ? metaAll_s3_6_prefetchSrc : 4'h0)
+    | (hitVec_7 ? metaAll_s3_7_prefetchSrc : 4'h0);
+  assign io_metaOnHit_accessed =
+    hitVec_0 & metaAll_s3_0_accessed | hitVec_1 & metaAll_s3_1_accessed | hitVec_2
+    & metaAll_s3_2_accessed | hitVec_3 & metaAll_s3_3_accessed | hitVec_4
+    & metaAll_s3_4_accessed | hitVec_5 & metaAll_s3_5_accessed | hitVec_6
+    & metaAll_s3_6_accessed | hitVec_7 & metaAll_s3_7_accessed;
+  assign io_metaOnHit_tagErr =
+    hitVec_0 & metaAll_s3_0_tagErr | hitVec_1 & metaAll_s3_1_tagErr | hitVec_2
+    & metaAll_s3_2_tagErr | hitVec_3 & metaAll_s3_3_tagErr | hitVec_4
+    & metaAll_s3_4_tagErr | hitVec_5 & metaAll_s3_5_tagErr | hitVec_6
+    & metaAll_s3_6_tagErr | hitVec_7 & metaAll_s3_7_tagErr;
+  assign io_metaOnHit_dataErr =
+    hitVec_0 & metaAll_s3_0_dataErr | hitVec_1 & metaAll_s3_1_dataErr | hitVec_2
+    & metaAll_s3_2_dataErr | hitVec_3 & metaAll_s3_3_dataErr | hitVec_4
+    & metaAll_s3_4_dataErr | hitVec_5 & metaAll_s3_5_dataErr | hitVec_6
+    & metaAll_s3_6_dataErr | hitVec_7 & metaAll_s3_7_dataErr;
+  assign io_errOnSnp =
+    hitVec_0 & errorAll_s3_0 | hitVec_1 & errorAll_s3_1 | hitVec_2 & errorAll_s3_2
+    | hitVec_3 & errorAll_s3_3 | hitVec_4 & errorAll_s3_4 | hitVec_5 & errorAll_s3_5
+    | hitVec_6 & errorAll_s3_6 | hitVec_7 & errorAll_s3_7;
+  assign io_wayOH = io_wayOH_0;
+  assign io_replWayOH = finalReplOH;
+  assign io_cmoHitInvalid =
+    ((cmoWayOH_s3[0] ? metaAll_s3_0_state : 2'h0)
+     | (cmoWayOH_s3[1] ? metaAll_s3_1_state : 2'h0)
+     | (cmoWayOH_s3[2] ? metaAll_s3_2_state : 2'h0)
+     | (cmoWayOH_s3[3] ? metaAll_s3_3_state : 2'h0)
+     | (cmoWayOH_s3[4] ? metaAll_s3_4_state : 2'h0)
+     | (cmoWayOH_s3[5] ? metaAll_s3_5_state : 2'h0)
+     | (cmoWayOH_s3[6] ? metaAll_s3_6_state : 2'h0)
+     | (cmoWayOH_s3[7] ? metaAll_s3_7_state : 2'h0)) == 2'h0;
+  assign io_retryFastFwd = (&occWayMask_s2) & refillReqValid_s2;
+  assign boreChildrenBd_bore_ack = bd_ack;
+  assign boreChildrenBd_bore_outdata = bd_outdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_10.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_10.sv
new file mode 100644
index 0000000000..b622f972ae
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_10.sv
@@ -0,0 +1,625 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_10(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [2:0]  io_in_0_bits_channel,
+  input  [2:0]  io_in_0_bits_txChannel,
+  input  [7:0]  io_in_0_bits_set,
+  input  [33:0] io_in_0_bits_tag,
+  input  [5:0]  io_in_0_bits_off,
+  input         io_in_0_bits_alias,
+  input  [43:0] io_in_0_bits_vaddr,
+  input         io_in_0_bits_isKeyword,
+  input  [3:0]  io_in_0_bits_opcode,
+  input  [2:0]  io_in_0_bits_param,
+  input  [2:0]  io_in_0_bits_size,
+  input  [6:0]  io_in_0_bits_sourceId,
+  input  [1:0]  io_in_0_bits_bufIdx,
+  input         io_in_0_bits_needProbeAckData,
+  input         io_in_0_bits_denied,
+  input         io_in_0_bits_corrupt,
+  input         io_in_0_bits_mshrTask,
+  input  [7:0]  io_in_0_bits_mshrId,
+  input         io_in_0_bits_aliasTask,
+  input         io_in_0_bits_useProbeData,
+  input         io_in_0_bits_mshrRetry,
+  input         io_in_0_bits_readProbeDataDown,
+  input         io_in_0_bits_fromL2pft,
+  input         io_in_0_bits_needHint,
+  input         io_in_0_bits_dirty,
+  input  [2:0]  io_in_0_bits_way,
+  input         io_in_0_bits_meta_dirty,
+  input  [1:0]  io_in_0_bits_meta_state,
+  input         io_in_0_bits_meta_clients,
+  input         io_in_0_bits_meta_alias,
+  input         io_in_0_bits_meta_prefetch,
+  input  [3:0]  io_in_0_bits_meta_prefetchSrc,
+  input         io_in_0_bits_meta_accessed,
+  input         io_in_0_bits_meta_tagErr,
+  input         io_in_0_bits_meta_dataErr,
+  input         io_in_0_bits_metaWen,
+  input         io_in_0_bits_tagWen,
+  input         io_in_0_bits_dsWen,
+  input  [7:0]  io_in_0_bits_wayMask,
+  input         io_in_0_bits_replTask,
+  input         io_in_0_bits_cmoTask,
+  input         io_in_0_bits_cmoAll,
+  input  [4:0]  io_in_0_bits_reqSource,
+  input         io_in_0_bits_mergeA,
+  input  [5:0]  io_in_0_bits_aMergeTask_off,
+  input         io_in_0_bits_aMergeTask_alias,
+  input  [43:0] io_in_0_bits_aMergeTask_vaddr,
+  input         io_in_0_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_0_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_0_bits_aMergeTask_param,
+  input  [6:0]  io_in_0_bits_aMergeTask_sourceId,
+  input         io_in_0_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_0_bits_aMergeTask_meta_state,
+  input         io_in_0_bits_aMergeTask_meta_clients,
+  input         io_in_0_bits_aMergeTask_meta_alias,
+  input         io_in_0_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_in_0_bits_aMergeTask_meta_prefetchSrc,
+  input         io_in_0_bits_aMergeTask_meta_accessed,
+  input         io_in_0_bits_aMergeTask_meta_tagErr,
+  input         io_in_0_bits_aMergeTask_meta_dataErr,
+  input         io_in_0_bits_snpHitRelease,
+  input         io_in_0_bits_snpHitReleaseToInval,
+  input         io_in_0_bits_snpHitReleaseToClean,
+  input         io_in_0_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_0_bits_snpHitReleaseIdx,
+  input         io_in_0_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_0_bits_snpHitReleaseMeta_state,
+  input         io_in_0_bits_snpHitReleaseMeta_clients,
+  input         io_in_0_bits_snpHitReleaseMeta_alias,
+  input         io_in_0_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_0_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_0_bits_snpHitReleaseMeta_accessed,
+  input         io_in_0_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_0_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [10:0] io_in_0_bits_srcID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [10:0] io_in_0_bits_homeNID,
+  input  [11:0] io_in_0_bits_dbID,
+  input  [10:0] io_in_0_bits_fwdNID,
+  input  [11:0] io_in_0_bits_fwdTxnID,
+  input  [6:0]  io_in_0_bits_chiOpcode,
+  input  [2:0]  io_in_0_bits_resp,
+  input  [2:0]  io_in_0_bits_fwdState,
+  input  [3:0]  io_in_0_bits_pCrdType,
+  input         io_in_0_bits_retToSrc,
+  input         io_in_0_bits_likelyshared,
+  input         io_in_0_bits_expCompAck,
+  input         io_in_0_bits_allowRetry,
+  input         io_in_0_bits_memAttr_allocate,
+  input         io_in_0_bits_memAttr_cacheable,
+  input         io_in_0_bits_memAttr_device,
+  input         io_in_0_bits_memAttr_ewa,
+  input         io_in_0_bits_traceTag,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [2:0]  io_in_1_bits_channel,
+  input  [2:0]  io_in_1_bits_txChannel,
+  input  [7:0]  io_in_1_bits_set,
+  input  [33:0] io_in_1_bits_tag,
+  input  [5:0]  io_in_1_bits_off,
+  input         io_in_1_bits_alias,
+  input  [43:0] io_in_1_bits_vaddr,
+  input         io_in_1_bits_isKeyword,
+  input  [3:0]  io_in_1_bits_opcode,
+  input  [2:0]  io_in_1_bits_param,
+  input  [2:0]  io_in_1_bits_size,
+  input  [6:0]  io_in_1_bits_sourceId,
+  input  [1:0]  io_in_1_bits_bufIdx,
+  input         io_in_1_bits_needProbeAckData,
+  input         io_in_1_bits_denied,
+  input         io_in_1_bits_corrupt,
+  input         io_in_1_bits_mshrTask,
+  input  [7:0]  io_in_1_bits_mshrId,
+  input         io_in_1_bits_aliasTask,
+  input         io_in_1_bits_useProbeData,
+  input         io_in_1_bits_mshrRetry,
+  input         io_in_1_bits_readProbeDataDown,
+  input         io_in_1_bits_fromL2pft,
+  input         io_in_1_bits_needHint,
+  input         io_in_1_bits_dirty,
+  input  [2:0]  io_in_1_bits_way,
+  input         io_in_1_bits_meta_dirty,
+  input  [1:0]  io_in_1_bits_meta_state,
+  input         io_in_1_bits_meta_clients,
+  input         io_in_1_bits_meta_alias,
+  input         io_in_1_bits_meta_prefetch,
+  input  [3:0]  io_in_1_bits_meta_prefetchSrc,
+  input         io_in_1_bits_meta_accessed,
+  input         io_in_1_bits_meta_tagErr,
+  input         io_in_1_bits_meta_dataErr,
+  input         io_in_1_bits_metaWen,
+  input         io_in_1_bits_tagWen,
+  input         io_in_1_bits_dsWen,
+  input  [7:0]  io_in_1_bits_wayMask,
+  input         io_in_1_bits_replTask,
+  input         io_in_1_bits_cmoTask,
+  input         io_in_1_bits_cmoAll,
+  input  [4:0]  io_in_1_bits_reqSource,
+  input         io_in_1_bits_mergeA,
+  input  [5:0]  io_in_1_bits_aMergeTask_off,
+  input         io_in_1_bits_aMergeTask_alias,
+  input  [43:0] io_in_1_bits_aMergeTask_vaddr,
+  input         io_in_1_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_1_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_1_bits_aMergeTask_param,
+  input  [6:0]  io_in_1_bits_aMergeTask_sourceId,
+  input         io_in_1_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_1_bits_aMergeTask_meta_state,
+  input         io_in_1_bits_aMergeTask_meta_clients,
+  input         io_in_1_bits_aMergeTask_meta_alias,
+  input         io_in_1_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_in_1_bits_aMergeTask_meta_prefetchSrc,
+  input         io_in_1_bits_aMergeTask_meta_accessed,
+  input         io_in_1_bits_aMergeTask_meta_tagErr,
+  input         io_in_1_bits_aMergeTask_meta_dataErr,
+  input         io_in_1_bits_snpHitRelease,
+  input         io_in_1_bits_snpHitReleaseToInval,
+  input         io_in_1_bits_snpHitReleaseToClean,
+  input         io_in_1_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_1_bits_snpHitReleaseIdx,
+  input         io_in_1_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_1_bits_snpHitReleaseMeta_state,
+  input         io_in_1_bits_snpHitReleaseMeta_clients,
+  input         io_in_1_bits_snpHitReleaseMeta_alias,
+  input         io_in_1_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_1_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_1_bits_snpHitReleaseMeta_accessed,
+  input         io_in_1_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_1_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [10:0] io_in_1_bits_srcID,
+  input  [11:0] io_in_1_bits_txnID,
+  input  [10:0] io_in_1_bits_homeNID,
+  input  [11:0] io_in_1_bits_dbID,
+  input  [10:0] io_in_1_bits_fwdNID,
+  input  [11:0] io_in_1_bits_fwdTxnID,
+  input  [6:0]  io_in_1_bits_chiOpcode,
+  input  [2:0]  io_in_1_bits_resp,
+  input  [2:0]  io_in_1_bits_fwdState,
+  input  [3:0]  io_in_1_bits_pCrdType,
+  input         io_in_1_bits_retToSrc,
+  input         io_in_1_bits_likelyshared,
+  input         io_in_1_bits_expCompAck,
+  input         io_in_1_bits_allowRetry,
+  input         io_in_1_bits_memAttr_allocate,
+  input         io_in_1_bits_memAttr_cacheable,
+  input         io_in_1_bits_memAttr_device,
+  input         io_in_1_bits_memAttr_ewa,
+  input         io_in_1_bits_traceTag,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [2:0]  io_out_bits_channel,
+  output [2:0]  io_out_bits_txChannel,
+  output [7:0]  io_out_bits_set,
+  output [33:0] io_out_bits_tag,
+  output [5:0]  io_out_bits_off,
+  output        io_out_bits_alias,
+  output [43:0] io_out_bits_vaddr,
+  output        io_out_bits_isKeyword,
+  output [3:0]  io_out_bits_opcode,
+  output [2:0]  io_out_bits_param,
+  output [2:0]  io_out_bits_size,
+  output [6:0]  io_out_bits_sourceId,
+  output [1:0]  io_out_bits_bufIdx,
+  output        io_out_bits_needProbeAckData,
+  output        io_out_bits_denied,
+  output        io_out_bits_corrupt,
+  output        io_out_bits_mshrTask,
+  output [7:0]  io_out_bits_mshrId,
+  output        io_out_bits_aliasTask,
+  output        io_out_bits_useProbeData,
+  output        io_out_bits_mshrRetry,
+  output        io_out_bits_readProbeDataDown,
+  output        io_out_bits_fromL2pft,
+  output        io_out_bits_needHint,
+  output        io_out_bits_dirty,
+  output [2:0]  io_out_bits_way,
+  output        io_out_bits_meta_dirty,
+  output [1:0]  io_out_bits_meta_state,
+  output        io_out_bits_meta_clients,
+  output        io_out_bits_meta_alias,
+  output        io_out_bits_meta_prefetch,
+  output [3:0]  io_out_bits_meta_prefetchSrc,
+  output        io_out_bits_meta_accessed,
+  output        io_out_bits_meta_tagErr,
+  output        io_out_bits_meta_dataErr,
+  output        io_out_bits_metaWen,
+  output        io_out_bits_tagWen,
+  output        io_out_bits_dsWen,
+  output [7:0]  io_out_bits_wayMask,
+  output        io_out_bits_replTask,
+  output        io_out_bits_cmoTask,
+  output        io_out_bits_cmoAll,
+  output [4:0]  io_out_bits_reqSource,
+  output        io_out_bits_mergeA,
+  output [5:0]  io_out_bits_aMergeTask_off,
+  output        io_out_bits_aMergeTask_alias,
+  output [43:0] io_out_bits_aMergeTask_vaddr,
+  output        io_out_bits_aMergeTask_isKeyword,
+  output [2:0]  io_out_bits_aMergeTask_opcode,
+  output [2:0]  io_out_bits_aMergeTask_param,
+  output [6:0]  io_out_bits_aMergeTask_sourceId,
+  output        io_out_bits_aMergeTask_meta_dirty,
+  output [1:0]  io_out_bits_aMergeTask_meta_state,
+  output        io_out_bits_aMergeTask_meta_clients,
+  output        io_out_bits_aMergeTask_meta_alias,
+  output        io_out_bits_aMergeTask_meta_prefetch,
+  output [3:0]  io_out_bits_aMergeTask_meta_prefetchSrc,
+  output        io_out_bits_aMergeTask_meta_accessed,
+  output        io_out_bits_aMergeTask_meta_tagErr,
+  output        io_out_bits_aMergeTask_meta_dataErr,
+  output        io_out_bits_snpHitRelease,
+  output        io_out_bits_snpHitReleaseToInval,
+  output        io_out_bits_snpHitReleaseToClean,
+  output        io_out_bits_snpHitReleaseWithData,
+  output [7:0]  io_out_bits_snpHitReleaseIdx,
+  output        io_out_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_out_bits_snpHitReleaseMeta_state,
+  output        io_out_bits_snpHitReleaseMeta_clients,
+  output        io_out_bits_snpHitReleaseMeta_alias,
+  output        io_out_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_out_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_out_bits_snpHitReleaseMeta_accessed,
+  output        io_out_bits_snpHitReleaseMeta_tagErr,
+  output        io_out_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [10:0] io_out_bits_homeNID,
+  output [11:0] io_out_bits_dbID,
+  output [10:0] io_out_bits_fwdNID,
+  output [11:0] io_out_bits_fwdTxnID,
+  output [6:0]  io_out_bits_chiOpcode,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_retToSrc,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_expCompAck,
+  output        io_out_bits_allowRetry,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_device,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_traceTag
+);
+
+  wire [1:0] chosenOH;
+  wire [1:0] valids = {io_in_1_valid, io_in_0_valid};
+  reg  [1:0] pendingMask;
+  reg  [1:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire [1:0] rrSelOH =
+    {rrGrantMask[1] & pendingMask[1] & ~_rrSelOH_oh_WIRE_0, _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids)) ? rrSelOH : {io_in_1_valid & ~io_in_0_valid, io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 2'h0;
+      rrGrantMask <= 2'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <= {chosenOH[0], 1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][1:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][3:2];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 2'h0;
+        rrGrantMask = 2'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_out_valid = |valids;
+  assign io_out_bits_channel =
+    (chosenOH[0] ? io_in_0_bits_channel : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_channel : 3'h0);
+  assign io_out_bits_txChannel =
+    (chosenOH[0] ? io_in_0_bits_txChannel : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_txChannel : 3'h0);
+  assign io_out_bits_set =
+    (chosenOH[0] ? io_in_0_bits_set : 8'h0) | (chosenOH[1] ? io_in_1_bits_set : 8'h0);
+  assign io_out_bits_tag =
+    (chosenOH[0] ? io_in_0_bits_tag : 34'h0) | (chosenOH[1] ? io_in_1_bits_tag : 34'h0);
+  assign io_out_bits_off =
+    (chosenOH[0] ? io_in_0_bits_off : 6'h0) | (chosenOH[1] ? io_in_1_bits_off : 6'h0);
+  assign io_out_bits_alias =
+    chosenOH[0] & io_in_0_bits_alias | chosenOH[1] & io_in_1_bits_alias;
+  assign io_out_bits_vaddr =
+    (chosenOH[0] ? io_in_0_bits_vaddr : 44'h0)
+    | (chosenOH[1] ? io_in_1_bits_vaddr : 44'h0);
+  assign io_out_bits_isKeyword =
+    chosenOH[0] & io_in_0_bits_isKeyword | chosenOH[1] & io_in_1_bits_isKeyword;
+  assign io_out_bits_opcode =
+    (chosenOH[0] ? io_in_0_bits_opcode : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_opcode : 4'h0);
+  assign io_out_bits_param =
+    (chosenOH[0] ? io_in_0_bits_param : 3'h0) | (chosenOH[1] ? io_in_1_bits_param : 3'h0);
+  assign io_out_bits_size =
+    (chosenOH[0] ? io_in_0_bits_size : 3'h0) | (chosenOH[1] ? io_in_1_bits_size : 3'h0);
+  assign io_out_bits_sourceId =
+    (chosenOH[0] ? io_in_0_bits_sourceId : 7'h0)
+    | (chosenOH[1] ? io_in_1_bits_sourceId : 7'h0);
+  assign io_out_bits_bufIdx =
+    (chosenOH[0] ? io_in_0_bits_bufIdx : 2'h0)
+    | (chosenOH[1] ? io_in_1_bits_bufIdx : 2'h0);
+  assign io_out_bits_needProbeAckData =
+    chosenOH[0] & io_in_0_bits_needProbeAckData | chosenOH[1]
+    & io_in_1_bits_needProbeAckData;
+  assign io_out_bits_denied =
+    chosenOH[0] & io_in_0_bits_denied | chosenOH[1] & io_in_1_bits_denied;
+  assign io_out_bits_corrupt =
+    chosenOH[0] & io_in_0_bits_corrupt | chosenOH[1] & io_in_1_bits_corrupt;
+  assign io_out_bits_mshrTask =
+    chosenOH[0] & io_in_0_bits_mshrTask | chosenOH[1] & io_in_1_bits_mshrTask;
+  assign io_out_bits_mshrId =
+    (chosenOH[0] ? io_in_0_bits_mshrId : 8'h0)
+    | (chosenOH[1] ? io_in_1_bits_mshrId : 8'h0);
+  assign io_out_bits_aliasTask =
+    chosenOH[0] & io_in_0_bits_aliasTask | chosenOH[1] & io_in_1_bits_aliasTask;
+  assign io_out_bits_useProbeData =
+    chosenOH[0] & io_in_0_bits_useProbeData | chosenOH[1] & io_in_1_bits_useProbeData;
+  assign io_out_bits_mshrRetry =
+    chosenOH[0] & io_in_0_bits_mshrRetry | chosenOH[1] & io_in_1_bits_mshrRetry;
+  assign io_out_bits_readProbeDataDown =
+    chosenOH[0] & io_in_0_bits_readProbeDataDown | chosenOH[1]
+    & io_in_1_bits_readProbeDataDown;
+  assign io_out_bits_fromL2pft =
+    chosenOH[0] & io_in_0_bits_fromL2pft | chosenOH[1] & io_in_1_bits_fromL2pft;
+  assign io_out_bits_needHint =
+    chosenOH[0] & io_in_0_bits_needHint | chosenOH[1] & io_in_1_bits_needHint;
+  assign io_out_bits_dirty =
+    chosenOH[0] & io_in_0_bits_dirty | chosenOH[1] & io_in_1_bits_dirty;
+  assign io_out_bits_way =
+    (chosenOH[0] ? io_in_0_bits_way : 3'h0) | (chosenOH[1] ? io_in_1_bits_way : 3'h0);
+  assign io_out_bits_meta_dirty =
+    chosenOH[0] & io_in_0_bits_meta_dirty | chosenOH[1] & io_in_1_bits_meta_dirty;
+  assign io_out_bits_meta_state =
+    (chosenOH[0] ? io_in_0_bits_meta_state : 2'h0)
+    | (chosenOH[1] ? io_in_1_bits_meta_state : 2'h0);
+  assign io_out_bits_meta_clients =
+    chosenOH[0] & io_in_0_bits_meta_clients | chosenOH[1] & io_in_1_bits_meta_clients;
+  assign io_out_bits_meta_alias =
+    chosenOH[0] & io_in_0_bits_meta_alias | chosenOH[1] & io_in_1_bits_meta_alias;
+  assign io_out_bits_meta_prefetch =
+    chosenOH[0] & io_in_0_bits_meta_prefetch | chosenOH[1] & io_in_1_bits_meta_prefetch;
+  assign io_out_bits_meta_prefetchSrc =
+    (chosenOH[0] ? io_in_0_bits_meta_prefetchSrc : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_meta_prefetchSrc : 4'h0);
+  assign io_out_bits_meta_accessed =
+    chosenOH[0] & io_in_0_bits_meta_accessed | chosenOH[1] & io_in_1_bits_meta_accessed;
+  assign io_out_bits_meta_tagErr =
+    chosenOH[0] & io_in_0_bits_meta_tagErr | chosenOH[1] & io_in_1_bits_meta_tagErr;
+  assign io_out_bits_meta_dataErr =
+    chosenOH[0] & io_in_0_bits_meta_dataErr | chosenOH[1] & io_in_1_bits_meta_dataErr;
+  assign io_out_bits_metaWen =
+    chosenOH[0] & io_in_0_bits_metaWen | chosenOH[1] & io_in_1_bits_metaWen;
+  assign io_out_bits_tagWen =
+    chosenOH[0] & io_in_0_bits_tagWen | chosenOH[1] & io_in_1_bits_tagWen;
+  assign io_out_bits_dsWen =
+    chosenOH[0] & io_in_0_bits_dsWen | chosenOH[1] & io_in_1_bits_dsWen;
+  assign io_out_bits_wayMask =
+    (chosenOH[0] ? io_in_0_bits_wayMask : 8'h0)
+    | (chosenOH[1] ? io_in_1_bits_wayMask : 8'h0);
+  assign io_out_bits_replTask =
+    chosenOH[0] & io_in_0_bits_replTask | chosenOH[1] & io_in_1_bits_replTask;
+  assign io_out_bits_cmoTask =
+    chosenOH[0] & io_in_0_bits_cmoTask | chosenOH[1] & io_in_1_bits_cmoTask;
+  assign io_out_bits_cmoAll =
+    chosenOH[0] & io_in_0_bits_cmoAll | chosenOH[1] & io_in_1_bits_cmoAll;
+  assign io_out_bits_reqSource =
+    (chosenOH[0] ? io_in_0_bits_reqSource : 5'h0)
+    | (chosenOH[1] ? io_in_1_bits_reqSource : 5'h0);
+  assign io_out_bits_mergeA =
+    chosenOH[0] & io_in_0_bits_mergeA | chosenOH[1] & io_in_1_bits_mergeA;
+  assign io_out_bits_aMergeTask_off =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_off : 6'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_off : 6'h0);
+  assign io_out_bits_aMergeTask_alias =
+    chosenOH[0] & io_in_0_bits_aMergeTask_alias | chosenOH[1]
+    & io_in_1_bits_aMergeTask_alias;
+  assign io_out_bits_aMergeTask_vaddr =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_vaddr : 44'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_vaddr : 44'h0);
+  assign io_out_bits_aMergeTask_isKeyword =
+    chosenOH[0] & io_in_0_bits_aMergeTask_isKeyword | chosenOH[1]
+    & io_in_1_bits_aMergeTask_isKeyword;
+  assign io_out_bits_aMergeTask_opcode =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_opcode : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_opcode : 3'h0);
+  assign io_out_bits_aMergeTask_param =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_param : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_param : 3'h0);
+  assign io_out_bits_aMergeTask_sourceId =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_sourceId : 7'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_sourceId : 7'h0);
+  assign io_out_bits_aMergeTask_meta_dirty =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_dirty | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_dirty;
+  assign io_out_bits_aMergeTask_meta_state =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_meta_state : 2'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_meta_state : 2'h0);
+  assign io_out_bits_aMergeTask_meta_clients =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_clients | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_clients;
+  assign io_out_bits_aMergeTask_meta_alias =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_alias | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_alias;
+  assign io_out_bits_aMergeTask_meta_prefetch =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_prefetch | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_prefetch;
+  assign io_out_bits_aMergeTask_meta_prefetchSrc =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_meta_prefetchSrc : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_meta_prefetchSrc : 4'h0);
+  assign io_out_bits_aMergeTask_meta_accessed =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_accessed | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_accessed;
+  assign io_out_bits_aMergeTask_meta_tagErr =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_tagErr | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_tagErr;
+  assign io_out_bits_aMergeTask_meta_dataErr =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_dataErr | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_dataErr;
+  assign io_out_bits_snpHitRelease =
+    chosenOH[0] & io_in_0_bits_snpHitRelease | chosenOH[1] & io_in_1_bits_snpHitRelease;
+  assign io_out_bits_snpHitReleaseToInval =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseToInval | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseToInval;
+  assign io_out_bits_snpHitReleaseToClean =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseToClean | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseToClean;
+  assign io_out_bits_snpHitReleaseWithData =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseWithData | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseWithData;
+  assign io_out_bits_snpHitReleaseIdx =
+    (chosenOH[0] ? io_in_0_bits_snpHitReleaseIdx : 8'h0)
+    | (chosenOH[1] ? io_in_1_bits_snpHitReleaseIdx : 8'h0);
+  assign io_out_bits_snpHitReleaseMeta_dirty =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_dirty | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_dirty;
+  assign io_out_bits_snpHitReleaseMeta_state =
+    (chosenOH[0] ? io_in_0_bits_snpHitReleaseMeta_state : 2'h0)
+    | (chosenOH[1] ? io_in_1_bits_snpHitReleaseMeta_state : 2'h0);
+  assign io_out_bits_snpHitReleaseMeta_clients =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_clients | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_clients;
+  assign io_out_bits_snpHitReleaseMeta_alias =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_alias | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_alias;
+  assign io_out_bits_snpHitReleaseMeta_prefetch =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_prefetch | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_prefetch;
+  assign io_out_bits_snpHitReleaseMeta_prefetchSrc =
+    (chosenOH[0] ? io_in_0_bits_snpHitReleaseMeta_prefetchSrc : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_snpHitReleaseMeta_prefetchSrc : 4'h0);
+  assign io_out_bits_snpHitReleaseMeta_accessed =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_accessed | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_accessed;
+  assign io_out_bits_snpHitReleaseMeta_tagErr =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_tagErr | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_tagErr;
+  assign io_out_bits_snpHitReleaseMeta_dataErr =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_dataErr | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_dataErr;
+  assign io_out_bits_tgtID =
+    (chosenOH[0] ? io_in_0_bits_tgtID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_tgtID : 11'h0);
+  assign io_out_bits_srcID =
+    (chosenOH[0] ? io_in_0_bits_srcID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_srcID : 11'h0);
+  assign io_out_bits_txnID =
+    (chosenOH[0] ? io_in_0_bits_txnID : 12'h0)
+    | (chosenOH[1] ? io_in_1_bits_txnID : 12'h0);
+  assign io_out_bits_homeNID =
+    (chosenOH[0] ? io_in_0_bits_homeNID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_homeNID : 11'h0);
+  assign io_out_bits_dbID =
+    (chosenOH[0] ? io_in_0_bits_dbID : 12'h0) | (chosenOH[1] ? io_in_1_bits_dbID : 12'h0);
+  assign io_out_bits_fwdNID =
+    (chosenOH[0] ? io_in_0_bits_fwdNID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_fwdNID : 11'h0);
+  assign io_out_bits_fwdTxnID =
+    (chosenOH[0] ? io_in_0_bits_fwdTxnID : 12'h0)
+    | (chosenOH[1] ? io_in_1_bits_fwdTxnID : 12'h0);
+  assign io_out_bits_chiOpcode =
+    (chosenOH[0] ? io_in_0_bits_chiOpcode : 7'h0)
+    | (chosenOH[1] ? io_in_1_bits_chiOpcode : 7'h0);
+  assign io_out_bits_resp =
+    (chosenOH[0] ? io_in_0_bits_resp : 3'h0) | (chosenOH[1] ? io_in_1_bits_resp : 3'h0);
+  assign io_out_bits_fwdState =
+    (chosenOH[0] ? io_in_0_bits_fwdState : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_fwdState : 3'h0);
+  assign io_out_bits_pCrdType =
+    (chosenOH[0] ? io_in_0_bits_pCrdType : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_pCrdType : 4'h0);
+  assign io_out_bits_retToSrc =
+    chosenOH[0] & io_in_0_bits_retToSrc | chosenOH[1] & io_in_1_bits_retToSrc;
+  assign io_out_bits_likelyshared =
+    chosenOH[0] & io_in_0_bits_likelyshared | chosenOH[1] & io_in_1_bits_likelyshared;
+  assign io_out_bits_expCompAck =
+    chosenOH[0] & io_in_0_bits_expCompAck | chosenOH[1] & io_in_1_bits_expCompAck;
+  assign io_out_bits_allowRetry =
+    chosenOH[0] & io_in_0_bits_allowRetry | chosenOH[1] & io_in_1_bits_allowRetry;
+  assign io_out_bits_memAttr_allocate =
+    chosenOH[0] & io_in_0_bits_memAttr_allocate | chosenOH[1]
+    & io_in_1_bits_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable =
+    chosenOH[0] & io_in_0_bits_memAttr_cacheable | chosenOH[1]
+    & io_in_1_bits_memAttr_cacheable;
+  assign io_out_bits_memAttr_device =
+    chosenOH[0] & io_in_0_bits_memAttr_device | chosenOH[1] & io_in_1_bits_memAttr_device;
+  assign io_out_bits_memAttr_ewa =
+    chosenOH[0] & io_in_0_bits_memAttr_ewa | chosenOH[1] & io_in_1_bits_memAttr_ewa;
+  assign io_out_bits_traceTag =
+    chosenOH[0] & io_in_0_bits_traceTag | chosenOH[1] & io_in_1_bits_traceTag;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_12.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_12.sv
new file mode 100644
index 0000000000..4b7ea139a8
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_12.sv
@@ -0,0 +1,207 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_12(
+  input         clock,
+  input         reset,
+  input         io_in_0_valid,
+  input         io_in_0_bits_valid,
+  input         io_in_0_bits_rdy,
+  input  [2:0]  io_in_0_bits_task_channel,
+  input  [7:0]  io_in_0_bits_task_set,
+  input  [33:0] io_in_0_bits_task_tag,
+  input  [5:0]  io_in_0_bits_task_off,
+  input         io_in_0_bits_task_alias,
+  input  [43:0] io_in_0_bits_task_vaddr,
+  input         io_in_0_bits_task_isKeyword,
+  input  [3:0]  io_in_0_bits_task_opcode,
+  input  [2:0]  io_in_0_bits_task_param,
+  input  [2:0]  io_in_0_bits_task_size,
+  input  [6:0]  io_in_0_bits_task_sourceId,
+  input         io_in_0_bits_task_corrupt,
+  input         io_in_0_bits_task_fromL2pft,
+  input         io_in_0_bits_task_needHint,
+  input  [4:0]  io_in_0_bits_task_reqSource,
+  input  [3:0]  io_in_0_bits_waitMP,
+  input  [15:0] io_in_0_bits_waitMS,
+  input         io_in_1_valid,
+  input         io_in_1_bits_valid,
+  input         io_in_1_bits_rdy,
+  input  [2:0]  io_in_1_bits_task_channel,
+  input  [7:0]  io_in_1_bits_task_set,
+  input  [33:0] io_in_1_bits_task_tag,
+  input  [5:0]  io_in_1_bits_task_off,
+  input         io_in_1_bits_task_alias,
+  input  [43:0] io_in_1_bits_task_vaddr,
+  input         io_in_1_bits_task_isKeyword,
+  input  [3:0]  io_in_1_bits_task_opcode,
+  input  [2:0]  io_in_1_bits_task_param,
+  input  [2:0]  io_in_1_bits_task_size,
+  input  [6:0]  io_in_1_bits_task_sourceId,
+  input         io_in_1_bits_task_corrupt,
+  input         io_in_1_bits_task_fromL2pft,
+  input         io_in_1_bits_task_needHint,
+  input  [4:0]  io_in_1_bits_task_reqSource,
+  input  [3:0]  io_in_1_bits_waitMP,
+  input  [15:0] io_in_1_bits_waitMS,
+  input         io_out_ready,
+  output        io_out_valid,
+  output        io_out_bits_valid,
+  output        io_out_bits_rdy,
+  output [2:0]  io_out_bits_task_channel,
+  output [7:0]  io_out_bits_task_set,
+  output [33:0] io_out_bits_task_tag,
+  output [5:0]  io_out_bits_task_off,
+  output        io_out_bits_task_alias,
+  output [43:0] io_out_bits_task_vaddr,
+  output        io_out_bits_task_isKeyword,
+  output [3:0]  io_out_bits_task_opcode,
+  output [2:0]  io_out_bits_task_param,
+  output [2:0]  io_out_bits_task_size,
+  output [6:0]  io_out_bits_task_sourceId,
+  output        io_out_bits_task_corrupt,
+  output        io_out_bits_task_fromL2pft,
+  output        io_out_bits_task_needHint,
+  output [4:0]  io_out_bits_task_reqSource,
+  output [3:0]  io_out_bits_waitMP,
+  output [15:0] io_out_bits_waitMS,
+  output [1:0]  io_chosenOH
+);
+
+  wire [1:0] chosenOH;
+  wire [1:0] valids = {io_in_1_valid, io_in_0_valid};
+  reg  [1:0] pendingMask;
+  reg  [1:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire [1:0] rrSelOH =
+    {rrGrantMask[1] & pendingMask[1] & ~_rrSelOH_oh_WIRE_0, _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids)) ? rrSelOH : {io_in_1_valid & ~io_in_0_valid, io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 2'h0;
+      rrGrantMask <= 2'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <= {chosenOH[0], 1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][1:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][3:2];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 2'h0;
+        rrGrantMask = 2'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_out_valid = |valids;
+  assign io_out_bits_valid =
+    chosenOH[0] & io_in_0_bits_valid | chosenOH[1] & io_in_1_bits_valid;
+  assign io_out_bits_rdy =
+    chosenOH[0] & io_in_0_bits_rdy | chosenOH[1] & io_in_1_bits_rdy;
+  assign io_out_bits_task_channel =
+    (chosenOH[0] ? io_in_0_bits_task_channel : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_channel : 3'h0);
+  assign io_out_bits_task_set =
+    (chosenOH[0] ? io_in_0_bits_task_set : 8'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_set : 8'h0);
+  assign io_out_bits_task_tag =
+    (chosenOH[0] ? io_in_0_bits_task_tag : 34'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_tag : 34'h0);
+  assign io_out_bits_task_off =
+    (chosenOH[0] ? io_in_0_bits_task_off : 6'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_off : 6'h0);
+  assign io_out_bits_task_alias =
+    chosenOH[0] & io_in_0_bits_task_alias | chosenOH[1] & io_in_1_bits_task_alias;
+  assign io_out_bits_task_vaddr =
+    (chosenOH[0] ? io_in_0_bits_task_vaddr : 44'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_vaddr : 44'h0);
+  assign io_out_bits_task_isKeyword =
+    chosenOH[0] & io_in_0_bits_task_isKeyword | chosenOH[1] & io_in_1_bits_task_isKeyword;
+  assign io_out_bits_task_opcode =
+    (chosenOH[0] ? io_in_0_bits_task_opcode : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_opcode : 4'h0);
+  assign io_out_bits_task_param =
+    (chosenOH[0] ? io_in_0_bits_task_param : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_param : 3'h0);
+  assign io_out_bits_task_size =
+    (chosenOH[0] ? io_in_0_bits_task_size : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_size : 3'h0);
+  assign io_out_bits_task_sourceId =
+    (chosenOH[0] ? io_in_0_bits_task_sourceId : 7'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_sourceId : 7'h0);
+  assign io_out_bits_task_corrupt =
+    chosenOH[0] & io_in_0_bits_task_corrupt | chosenOH[1] & io_in_1_bits_task_corrupt;
+  assign io_out_bits_task_fromL2pft =
+    chosenOH[0] & io_in_0_bits_task_fromL2pft | chosenOH[1] & io_in_1_bits_task_fromL2pft;
+  assign io_out_bits_task_needHint =
+    chosenOH[0] & io_in_0_bits_task_needHint | chosenOH[1] & io_in_1_bits_task_needHint;
+  assign io_out_bits_task_reqSource =
+    (chosenOH[0] ? io_in_0_bits_task_reqSource : 5'h0)
+    | (chosenOH[1] ? io_in_1_bits_task_reqSource : 5'h0);
+  assign io_out_bits_waitMP =
+    (chosenOH[0] ? io_in_0_bits_waitMP : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_waitMP : 4'h0);
+  assign io_out_bits_waitMS =
+    (chosenOH[0] ? io_in_0_bits_waitMS : 16'h0)
+    | (chosenOH[1] ? io_in_1_bits_waitMS : 16'h0);
+  assign io_chosenOH = chosenOH;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_16.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_16.sv
new file mode 100644
index 0000000000..b93e7cba09
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_16.sv
@@ -0,0 +1,251 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_16(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [11:0] io_in_0_bits_txnID,
+  input         io_in_0_bits_traceTag,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [11:0] io_in_1_bits_txnID,
+  input         io_in_1_bits_traceTag,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [10:0] io_in_2_bits_tgtID,
+  input  [11:0] io_in_2_bits_txnID,
+  input         io_in_2_bits_traceTag,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [10:0] io_in_3_bits_tgtID,
+  input  [11:0] io_in_3_bits_txnID,
+  input         io_in_3_bits_traceTag,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [10:0] io_in_4_bits_tgtID,
+  input  [11:0] io_in_4_bits_txnID,
+  input         io_in_4_bits_traceTag,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [10:0] io_in_5_bits_tgtID,
+  input  [11:0] io_in_5_bits_txnID,
+  input         io_in_5_bits_traceTag,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [10:0] io_in_6_bits_tgtID,
+  input  [11:0] io_in_6_bits_txnID,
+  input         io_in_6_bits_traceTag,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [10:0] io_in_7_bits_tgtID,
+  input  [11:0] io_in_7_bits_txnID,
+  input         io_in_7_bits_traceTag,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [10:0] io_out_bits_tgtID,
+  output [11:0] io_out_bits_txnID,
+  output [4:0]  io_out_bits_opcode,
+  output        io_out_bits_traceTag
+);
+
+  wire [7:0] chosenOH;
+  wire [7:0] valids =
+    {io_in_7_valid,
+     io_in_6_valid,
+     io_in_5_valid,
+     io_in_4_valid,
+     io_in_3_valid,
+     io_in_2_valid,
+     io_in_1_valid,
+     io_in_0_valid};
+  reg  [7:0] pendingMask;
+  reg  [7:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire       _rrSelOH_T_2 = rrGrantMask[1] & pendingMask[1];
+  wire       _rrSelOH_T_3 = rrGrantMask[2] & pendingMask[2];
+  wire       _rrSelOH_T_4 = rrGrantMask[3] & pendingMask[3];
+  wire       _rrSelOH_T_5 = rrGrantMask[4] & pendingMask[4];
+  wire       _rrSelOH_T_6 = rrGrantMask[5] & pendingMask[5];
+  wire       _rrSelOH_T_7 = rrGrantMask[6] & pendingMask[6];
+  wire [7:0] rrSelOH =
+    {rrGrantMask[7] & pendingMask[7]
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7} == 7'h0,
+     _rrSelOH_T_7
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6} == 6'h0,
+     _rrSelOH_T_6
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5} == 5'h0,
+     _rrSelOH_T_5
+       & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3, _rrSelOH_T_4} == 4'h0,
+     _rrSelOH_T_4 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3} == 3'h0,
+     _rrSelOH_T_3 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2} == 2'h0,
+     _rrSelOH_T_2 & ~_rrSelOH_oh_WIRE_0,
+     _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids))
+      ? rrSelOH
+      : {io_in_7_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid} == 7'h0,
+         io_in_6_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid} == 6'h0,
+         io_in_5_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid} == 5'h0,
+         io_in_4_valid
+           & {io_in_0_valid, io_in_1_valid, io_in_2_valid, io_in_3_valid} == 4'h0,
+         io_in_3_valid & {io_in_0_valid, io_in_1_valid, io_in_2_valid} == 3'h0,
+         io_in_2_valid & {io_in_0_valid, io_in_1_valid} == 2'h0,
+         io_in_1_valid & ~io_in_0_valid,
+         io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 8'h0;
+      rrGrantMask <= 8'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <=
+        {|(chosenOH[6:0]),
+         |(chosenOH[5:0]),
+         |(chosenOH[4:0]),
+         |(chosenOH[3:0]),
+         |(chosenOH[2:0]),
+         |(chosenOH[1:0]),
+         chosenOH[0],
+         1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][7:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][15:8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 8'h0;
+        rrGrantMask = 8'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_in_2_ready = chosenOH[2] & io_out_ready;
+  assign io_in_3_ready = chosenOH[3] & io_out_ready;
+  assign io_in_4_ready = chosenOH[4] & io_out_ready;
+  assign io_in_5_ready = chosenOH[5] & io_out_ready;
+  assign io_in_6_ready = chosenOH[6] & io_out_ready;
+  assign io_in_7_ready = chosenOH[7] & io_out_ready;
+  assign io_out_valid = |valids;
+  assign io_out_bits_tgtID =
+    (chosenOH[0] ? io_in_0_bits_tgtID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_tgtID : 11'h0)
+    | (chosenOH[2] ? io_in_2_bits_tgtID : 11'h0)
+    | (chosenOH[3] ? io_in_3_bits_tgtID : 11'h0)
+    | (chosenOH[4] ? io_in_4_bits_tgtID : 11'h0)
+    | (chosenOH[5] ? io_in_5_bits_tgtID : 11'h0)
+    | (chosenOH[6] ? io_in_6_bits_tgtID : 11'h0)
+    | (chosenOH[7] ? io_in_7_bits_tgtID : 11'h0);
+  assign io_out_bits_txnID =
+    (chosenOH[0] ? io_in_0_bits_txnID : 12'h0)
+    | (chosenOH[1] ? io_in_1_bits_txnID : 12'h0)
+    | (chosenOH[2] ? io_in_2_bits_txnID : 12'h0)
+    | (chosenOH[3] ? io_in_3_bits_txnID : 12'h0)
+    | (chosenOH[4] ? io_in_4_bits_txnID : 12'h0)
+    | (chosenOH[5] ? io_in_5_bits_txnID : 12'h0)
+    | (chosenOH[6] ? io_in_6_bits_txnID : 12'h0)
+    | (chosenOH[7] ? io_in_7_bits_txnID : 12'h0);
+  assign io_out_bits_opcode =
+    {3'h0, chosenOH[0], 1'h0} | {3'h0, chosenOH[1], 1'h0} | {3'h0, chosenOH[2], 1'h0}
+    | {3'h0, chosenOH[3], 1'h0} | {3'h0, chosenOH[4], 1'h0} | {3'h0, chosenOH[5], 1'h0}
+    | {3'h0, chosenOH[6], 1'h0} | {3'h0, chosenOH[7], 1'h0};
+  assign io_out_bits_traceTag =
+    chosenOH[0] & io_in_0_bits_traceTag | chosenOH[1] & io_in_1_bits_traceTag
+    | chosenOH[2] & io_in_2_bits_traceTag | chosenOH[3] & io_in_3_bits_traceTag
+    | chosenOH[4] & io_in_4_bits_traceTag | chosenOH[5] & io_in_5_bits_traceTag
+    | chosenOH[6] & io_in_6_bits_traceTag | chosenOH[7] & io_in_7_bits_traceTag;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_18.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_18.sv
new file mode 100644
index 0000000000..17b73bba38
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_18.sv
@@ -0,0 +1,128 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_18(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [33:0] io_in_0_bits_tag,
+  input  [7:0]  io_in_0_bits_set,
+  input  [2:0]  io_in_0_bits_opcode,
+  input  [1:0]  io_in_0_bits_param,
+  input         io_in_0_bits_alias,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [33:0] io_in_1_bits_tag,
+  input  [7:0]  io_in_1_bits_set,
+  input  [2:0]  io_in_1_bits_opcode,
+  input  [1:0]  io_in_1_bits_param,
+  input         io_in_1_bits_alias,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [33:0] io_out_bits_tag,
+  output [7:0]  io_out_bits_set,
+  output [2:0]  io_out_bits_opcode,
+  output [1:0]  io_out_bits_param,
+  output        io_out_bits_alias
+);
+
+  wire [1:0] chosenOH;
+  wire [1:0] valids = {io_in_1_valid, io_in_0_valid};
+  reg  [1:0] pendingMask;
+  reg  [1:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire [1:0] rrSelOH =
+    {rrGrantMask[1] & pendingMask[1] & ~_rrSelOH_oh_WIRE_0, _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids)) ? rrSelOH : {io_in_1_valid & ~io_in_0_valid, io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 2'h0;
+      rrGrantMask <= 2'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <= {chosenOH[0], 1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][1:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][3:2];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 2'h0;
+        rrGrantMask = 2'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_out_valid = |valids;
+  assign io_out_bits_tag =
+    (chosenOH[0] ? io_in_0_bits_tag : 34'h0) | (chosenOH[1] ? io_in_1_bits_tag : 34'h0);
+  assign io_out_bits_set =
+    (chosenOH[0] ? io_in_0_bits_set : 8'h0) | (chosenOH[1] ? io_in_1_bits_set : 8'h0);
+  assign io_out_bits_opcode =
+    (chosenOH[0] ? io_in_0_bits_opcode : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_opcode : 3'h0);
+  assign io_out_bits_param =
+    (chosenOH[0] ? io_in_0_bits_param : 2'h0) | (chosenOH[1] ? io_in_1_bits_param : 2'h0);
+  assign io_out_bits_alias =
+    chosenOH[0] & io_in_0_bits_alias | chosenOH[1] & io_in_1_bits_alias;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_2.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_2.sv
new file mode 100644
index 0000000000..65295258d2
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_2.sv
@@ -0,0 +1,435 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_2(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [6:0]  io_in_0_bits_opcode,
+  input  [2:0]  io_in_0_bits_size,
+  input  [47:0] io_in_0_bits_addr,
+  input         io_in_0_bits_likelyshared,
+  input         io_in_0_bits_allowRetry,
+  input  [1:0]  io_in_0_bits_order,
+  input  [3:0]  io_in_0_bits_pCrdType,
+  input         io_in_0_bits_memAttr_allocate,
+  input         io_in_0_bits_memAttr_cacheable,
+  input         io_in_0_bits_memAttr_device,
+  input         io_in_0_bits_memAttr_ewa,
+  input         io_in_0_bits_snpAttr,
+  input         io_in_0_bits_expCompAck,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [11:0] io_in_1_bits_txnID,
+  input  [6:0]  io_in_1_bits_opcode,
+  input  [2:0]  io_in_1_bits_size,
+  input  [47:0] io_in_1_bits_addr,
+  input         io_in_1_bits_likelyshared,
+  input         io_in_1_bits_allowRetry,
+  input  [1:0]  io_in_1_bits_order,
+  input  [3:0]  io_in_1_bits_pCrdType,
+  input         io_in_1_bits_memAttr_allocate,
+  input         io_in_1_bits_memAttr_cacheable,
+  input         io_in_1_bits_memAttr_device,
+  input         io_in_1_bits_memAttr_ewa,
+  input         io_in_1_bits_snpAttr,
+  input         io_in_1_bits_expCompAck,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [10:0] io_in_2_bits_tgtID,
+  input  [11:0] io_in_2_bits_txnID,
+  input  [6:0]  io_in_2_bits_opcode,
+  input  [2:0]  io_in_2_bits_size,
+  input  [47:0] io_in_2_bits_addr,
+  input         io_in_2_bits_likelyshared,
+  input         io_in_2_bits_allowRetry,
+  input  [1:0]  io_in_2_bits_order,
+  input  [3:0]  io_in_2_bits_pCrdType,
+  input         io_in_2_bits_memAttr_allocate,
+  input         io_in_2_bits_memAttr_cacheable,
+  input         io_in_2_bits_memAttr_device,
+  input         io_in_2_bits_memAttr_ewa,
+  input         io_in_2_bits_snpAttr,
+  input         io_in_2_bits_expCompAck,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [10:0] io_in_3_bits_tgtID,
+  input  [11:0] io_in_3_bits_txnID,
+  input  [6:0]  io_in_3_bits_opcode,
+  input  [2:0]  io_in_3_bits_size,
+  input  [47:0] io_in_3_bits_addr,
+  input         io_in_3_bits_likelyshared,
+  input         io_in_3_bits_allowRetry,
+  input  [1:0]  io_in_3_bits_order,
+  input  [3:0]  io_in_3_bits_pCrdType,
+  input         io_in_3_bits_memAttr_allocate,
+  input         io_in_3_bits_memAttr_cacheable,
+  input         io_in_3_bits_memAttr_device,
+  input         io_in_3_bits_memAttr_ewa,
+  input         io_in_3_bits_snpAttr,
+  input         io_in_3_bits_expCompAck,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [10:0] io_in_4_bits_tgtID,
+  input  [11:0] io_in_4_bits_txnID,
+  input  [6:0]  io_in_4_bits_opcode,
+  input  [2:0]  io_in_4_bits_size,
+  input  [47:0] io_in_4_bits_addr,
+  input         io_in_4_bits_likelyshared,
+  input         io_in_4_bits_allowRetry,
+  input  [1:0]  io_in_4_bits_order,
+  input  [3:0]  io_in_4_bits_pCrdType,
+  input         io_in_4_bits_memAttr_allocate,
+  input         io_in_4_bits_memAttr_cacheable,
+  input         io_in_4_bits_memAttr_device,
+  input         io_in_4_bits_memAttr_ewa,
+  input         io_in_4_bits_snpAttr,
+  input         io_in_4_bits_expCompAck,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [10:0] io_in_5_bits_tgtID,
+  input  [11:0] io_in_5_bits_txnID,
+  input  [6:0]  io_in_5_bits_opcode,
+  input  [2:0]  io_in_5_bits_size,
+  input  [47:0] io_in_5_bits_addr,
+  input         io_in_5_bits_likelyshared,
+  input         io_in_5_bits_allowRetry,
+  input  [1:0]  io_in_5_bits_order,
+  input  [3:0]  io_in_5_bits_pCrdType,
+  input         io_in_5_bits_memAttr_allocate,
+  input         io_in_5_bits_memAttr_cacheable,
+  input         io_in_5_bits_memAttr_device,
+  input         io_in_5_bits_memAttr_ewa,
+  input         io_in_5_bits_snpAttr,
+  input         io_in_5_bits_expCompAck,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [10:0] io_in_6_bits_tgtID,
+  input  [11:0] io_in_6_bits_txnID,
+  input  [6:0]  io_in_6_bits_opcode,
+  input  [2:0]  io_in_6_bits_size,
+  input  [47:0] io_in_6_bits_addr,
+  input         io_in_6_bits_likelyshared,
+  input         io_in_6_bits_allowRetry,
+  input  [1:0]  io_in_6_bits_order,
+  input  [3:0]  io_in_6_bits_pCrdType,
+  input         io_in_6_bits_memAttr_allocate,
+  input         io_in_6_bits_memAttr_cacheable,
+  input         io_in_6_bits_memAttr_device,
+  input         io_in_6_bits_memAttr_ewa,
+  input         io_in_6_bits_snpAttr,
+  input         io_in_6_bits_expCompAck,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [10:0] io_in_7_bits_tgtID,
+  input  [11:0] io_in_7_bits_txnID,
+  input  [6:0]  io_in_7_bits_opcode,
+  input  [2:0]  io_in_7_bits_size,
+  input  [47:0] io_in_7_bits_addr,
+  input         io_in_7_bits_likelyshared,
+  input         io_in_7_bits_allowRetry,
+  input  [1:0]  io_in_7_bits_order,
+  input  [3:0]  io_in_7_bits_pCrdType,
+  input         io_in_7_bits_memAttr_allocate,
+  input         io_in_7_bits_memAttr_cacheable,
+  input         io_in_7_bits_memAttr_device,
+  input         io_in_7_bits_memAttr_ewa,
+  input         io_in_7_bits_snpAttr,
+  input         io_in_7_bits_expCompAck,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_qos,
+  output [10:0] io_out_bits_tgtID,
+  output [11:0] io_out_bits_txnID,
+  output [6:0]  io_out_bits_opcode,
+  output [2:0]  io_out_bits_size,
+  output [47:0] io_out_bits_addr,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_allowRetry,
+  output [1:0]  io_out_bits_order,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_device,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_snpAttr,
+  output        io_out_bits_expCompAck
+);
+
+  wire [7:0] chosenOH;
+  wire [7:0] valids =
+    {io_in_7_valid,
+     io_in_6_valid,
+     io_in_5_valid,
+     io_in_4_valid,
+     io_in_3_valid,
+     io_in_2_valid,
+     io_in_1_valid,
+     io_in_0_valid};
+  reg  [7:0] pendingMask;
+  reg  [7:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire       _rrSelOH_T_2 = rrGrantMask[1] & pendingMask[1];
+  wire       _rrSelOH_T_3 = rrGrantMask[2] & pendingMask[2];
+  wire       _rrSelOH_T_4 = rrGrantMask[3] & pendingMask[3];
+  wire       _rrSelOH_T_5 = rrGrantMask[4] & pendingMask[4];
+  wire       _rrSelOH_T_6 = rrGrantMask[5] & pendingMask[5];
+  wire       _rrSelOH_T_7 = rrGrantMask[6] & pendingMask[6];
+  wire [7:0] rrSelOH =
+    {rrGrantMask[7] & pendingMask[7]
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7} == 7'h0,
+     _rrSelOH_T_7
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6} == 6'h0,
+     _rrSelOH_T_6
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5} == 5'h0,
+     _rrSelOH_T_5
+       & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3, _rrSelOH_T_4} == 4'h0,
+     _rrSelOH_T_4 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3} == 3'h0,
+     _rrSelOH_T_3 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2} == 2'h0,
+     _rrSelOH_T_2 & ~_rrSelOH_oh_WIRE_0,
+     _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids))
+      ? rrSelOH
+      : {io_in_7_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid} == 7'h0,
+         io_in_6_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid} == 6'h0,
+         io_in_5_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid} == 5'h0,
+         io_in_4_valid
+           & {io_in_0_valid, io_in_1_valid, io_in_2_valid, io_in_3_valid} == 4'h0,
+         io_in_3_valid & {io_in_0_valid, io_in_1_valid, io_in_2_valid} == 3'h0,
+         io_in_2_valid & {io_in_0_valid, io_in_1_valid} == 2'h0,
+         io_in_1_valid & ~io_in_0_valid,
+         io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 8'h0;
+      rrGrantMask <= 8'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <=
+        {|(chosenOH[6:0]),
+         |(chosenOH[5:0]),
+         |(chosenOH[4:0]),
+         |(chosenOH[3:0]),
+         |(chosenOH[2:0]),
+         |(chosenOH[1:0]),
+         chosenOH[0],
+         1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][7:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][15:8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 8'h0;
+        rrGrantMask = 8'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_in_2_ready = chosenOH[2] & io_out_ready;
+  assign io_in_3_ready = chosenOH[3] & io_out_ready;
+  assign io_in_4_ready = chosenOH[4] & io_out_ready;
+  assign io_in_5_ready = chosenOH[5] & io_out_ready;
+  assign io_in_6_ready = chosenOH[6] & io_out_ready;
+  assign io_in_7_ready = chosenOH[7] & io_out_ready;
+  assign io_out_valid = |valids;
+  assign io_out_bits_qos = (|chosenOH) ? 4'hE : 4'h0;
+  assign io_out_bits_tgtID =
+    (chosenOH[0] ? io_in_0_bits_tgtID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_tgtID : 11'h0)
+    | (chosenOH[2] ? io_in_2_bits_tgtID : 11'h0)
+    | (chosenOH[3] ? io_in_3_bits_tgtID : 11'h0)
+    | (chosenOH[4] ? io_in_4_bits_tgtID : 11'h0)
+    | (chosenOH[5] ? io_in_5_bits_tgtID : 11'h0)
+    | (chosenOH[6] ? io_in_6_bits_tgtID : 11'h0)
+    | (chosenOH[7] ? io_in_7_bits_tgtID : 11'h0);
+  assign io_out_bits_txnID =
+    (chosenOH[0] ? io_in_0_bits_txnID : 12'h0)
+    | (chosenOH[1] ? io_in_1_bits_txnID : 12'h0)
+    | (chosenOH[2] ? io_in_2_bits_txnID : 12'h0)
+    | (chosenOH[3] ? io_in_3_bits_txnID : 12'h0)
+    | (chosenOH[4] ? io_in_4_bits_txnID : 12'h0)
+    | (chosenOH[5] ? io_in_5_bits_txnID : 12'h0)
+    | (chosenOH[6] ? io_in_6_bits_txnID : 12'h0)
+    | (chosenOH[7] ? io_in_7_bits_txnID : 12'h0);
+  assign io_out_bits_opcode =
+    (chosenOH[0] ? io_in_0_bits_opcode : 7'h0)
+    | (chosenOH[1] ? io_in_1_bits_opcode : 7'h0)
+    | (chosenOH[2] ? io_in_2_bits_opcode : 7'h0)
+    | (chosenOH[3] ? io_in_3_bits_opcode : 7'h0)
+    | (chosenOH[4] ? io_in_4_bits_opcode : 7'h0)
+    | (chosenOH[5] ? io_in_5_bits_opcode : 7'h0)
+    | (chosenOH[6] ? io_in_6_bits_opcode : 7'h0)
+    | (chosenOH[7] ? io_in_7_bits_opcode : 7'h0);
+  assign io_out_bits_size =
+    (chosenOH[0] ? io_in_0_bits_size : 3'h0) | (chosenOH[1] ? io_in_1_bits_size : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_size : 3'h0) | (chosenOH[3] ? io_in_3_bits_size : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_size : 3'h0) | (chosenOH[5] ? io_in_5_bits_size : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_size : 3'h0) | (chosenOH[7] ? io_in_7_bits_size : 3'h0);
+  assign io_out_bits_addr =
+    (chosenOH[0] ? io_in_0_bits_addr : 48'h0) | (chosenOH[1] ? io_in_1_bits_addr : 48'h0)
+    | (chosenOH[2] ? io_in_2_bits_addr : 48'h0)
+    | (chosenOH[3] ? io_in_3_bits_addr : 48'h0)
+    | (chosenOH[4] ? io_in_4_bits_addr : 48'h0)
+    | (chosenOH[5] ? io_in_5_bits_addr : 48'h0)
+    | (chosenOH[6] ? io_in_6_bits_addr : 48'h0)
+    | (chosenOH[7] ? io_in_7_bits_addr : 48'h0);
+  assign io_out_bits_likelyshared =
+    chosenOH[0] & io_in_0_bits_likelyshared | chosenOH[1] & io_in_1_bits_likelyshared
+    | chosenOH[2] & io_in_2_bits_likelyshared | chosenOH[3] & io_in_3_bits_likelyshared
+    | chosenOH[4] & io_in_4_bits_likelyshared | chosenOH[5] & io_in_5_bits_likelyshared
+    | chosenOH[6] & io_in_6_bits_likelyshared | chosenOH[7] & io_in_7_bits_likelyshared;
+  assign io_out_bits_allowRetry =
+    chosenOH[0] & io_in_0_bits_allowRetry | chosenOH[1] & io_in_1_bits_allowRetry
+    | chosenOH[2] & io_in_2_bits_allowRetry | chosenOH[3] & io_in_3_bits_allowRetry
+    | chosenOH[4] & io_in_4_bits_allowRetry | chosenOH[5] & io_in_5_bits_allowRetry
+    | chosenOH[6] & io_in_6_bits_allowRetry | chosenOH[7] & io_in_7_bits_allowRetry;
+  assign io_out_bits_order =
+    (chosenOH[0] ? io_in_0_bits_order : 2'h0) | (chosenOH[1] ? io_in_1_bits_order : 2'h0)
+    | (chosenOH[2] ? io_in_2_bits_order : 2'h0)
+    | (chosenOH[3] ? io_in_3_bits_order : 2'h0)
+    | (chosenOH[4] ? io_in_4_bits_order : 2'h0)
+    | (chosenOH[5] ? io_in_5_bits_order : 2'h0)
+    | (chosenOH[6] ? io_in_6_bits_order : 2'h0)
+    | (chosenOH[7] ? io_in_7_bits_order : 2'h0);
+  assign io_out_bits_pCrdType =
+    (chosenOH[0] ? io_in_0_bits_pCrdType : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_pCrdType : 4'h0)
+    | (chosenOH[2] ? io_in_2_bits_pCrdType : 4'h0)
+    | (chosenOH[3] ? io_in_3_bits_pCrdType : 4'h0)
+    | (chosenOH[4] ? io_in_4_bits_pCrdType : 4'h0)
+    | (chosenOH[5] ? io_in_5_bits_pCrdType : 4'h0)
+    | (chosenOH[6] ? io_in_6_bits_pCrdType : 4'h0)
+    | (chosenOH[7] ? io_in_7_bits_pCrdType : 4'h0);
+  assign io_out_bits_memAttr_allocate =
+    chosenOH[0] & io_in_0_bits_memAttr_allocate | chosenOH[1]
+    & io_in_1_bits_memAttr_allocate | chosenOH[2] & io_in_2_bits_memAttr_allocate
+    | chosenOH[3] & io_in_3_bits_memAttr_allocate | chosenOH[4]
+    & io_in_4_bits_memAttr_allocate | chosenOH[5] & io_in_5_bits_memAttr_allocate
+    | chosenOH[6] & io_in_6_bits_memAttr_allocate | chosenOH[7]
+    & io_in_7_bits_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable =
+    chosenOH[0] & io_in_0_bits_memAttr_cacheable | chosenOH[1]
+    & io_in_1_bits_memAttr_cacheable | chosenOH[2] & io_in_2_bits_memAttr_cacheable
+    | chosenOH[3] & io_in_3_bits_memAttr_cacheable | chosenOH[4]
+    & io_in_4_bits_memAttr_cacheable | chosenOH[5] & io_in_5_bits_memAttr_cacheable
+    | chosenOH[6] & io_in_6_bits_memAttr_cacheable | chosenOH[7]
+    & io_in_7_bits_memAttr_cacheable;
+  assign io_out_bits_memAttr_device =
+    chosenOH[0] & io_in_0_bits_memAttr_device | chosenOH[1] & io_in_1_bits_memAttr_device
+    | chosenOH[2] & io_in_2_bits_memAttr_device | chosenOH[3]
+    & io_in_3_bits_memAttr_device | chosenOH[4] & io_in_4_bits_memAttr_device
+    | chosenOH[5] & io_in_5_bits_memAttr_device | chosenOH[6]
+    & io_in_6_bits_memAttr_device | chosenOH[7] & io_in_7_bits_memAttr_device;
+  assign io_out_bits_memAttr_ewa =
+    chosenOH[0] & io_in_0_bits_memAttr_ewa | chosenOH[1] & io_in_1_bits_memAttr_ewa
+    | chosenOH[2] & io_in_2_bits_memAttr_ewa | chosenOH[3] & io_in_3_bits_memAttr_ewa
+    | chosenOH[4] & io_in_4_bits_memAttr_ewa | chosenOH[5] & io_in_5_bits_memAttr_ewa
+    | chosenOH[6] & io_in_6_bits_memAttr_ewa | chosenOH[7] & io_in_7_bits_memAttr_ewa;
+  assign io_out_bits_snpAttr =
+    chosenOH[0] & io_in_0_bits_snpAttr | chosenOH[1] & io_in_1_bits_snpAttr | chosenOH[2]
+    & io_in_2_bits_snpAttr | chosenOH[3] & io_in_3_bits_snpAttr | chosenOH[4]
+    & io_in_4_bits_snpAttr | chosenOH[5] & io_in_5_bits_snpAttr | chosenOH[6]
+    & io_in_6_bits_snpAttr | chosenOH[7] & io_in_7_bits_snpAttr;
+  assign io_out_bits_expCompAck =
+    chosenOH[0] & io_in_0_bits_expCompAck | chosenOH[1] & io_in_1_bits_expCompAck
+    | chosenOH[2] & io_in_2_bits_expCompAck | chosenOH[3] & io_in_3_bits_expCompAck
+    | chosenOH[4] & io_in_4_bits_expCompAck | chosenOH[5] & io_in_5_bits_expCompAck
+    | chosenOH[6] & io_in_6_bits_expCompAck | chosenOH[7] & io_in_7_bits_expCompAck;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_20.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_20.sv
new file mode 100644
index 0000000000..c67fd24d80
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_20.sv
@@ -0,0 +1,257 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_20(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [33:0] io_in_0_bits_tag,
+  input  [7:0]  io_in_0_bits_set,
+  input  [1:0]  io_in_0_bits_param,
+  input         io_in_0_bits_alias,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [33:0] io_in_1_bits_tag,
+  input  [7:0]  io_in_1_bits_set,
+  input  [1:0]  io_in_1_bits_param,
+  input         io_in_1_bits_alias,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [33:0] io_in_2_bits_tag,
+  input  [7:0]  io_in_2_bits_set,
+  input  [1:0]  io_in_2_bits_param,
+  input         io_in_2_bits_alias,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [33:0] io_in_3_bits_tag,
+  input  [7:0]  io_in_3_bits_set,
+  input  [1:0]  io_in_3_bits_param,
+  input         io_in_3_bits_alias,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [33:0] io_in_4_bits_tag,
+  input  [7:0]  io_in_4_bits_set,
+  input  [1:0]  io_in_4_bits_param,
+  input         io_in_4_bits_alias,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [33:0] io_in_5_bits_tag,
+  input  [7:0]  io_in_5_bits_set,
+  input  [1:0]  io_in_5_bits_param,
+  input         io_in_5_bits_alias,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [33:0] io_in_6_bits_tag,
+  input  [7:0]  io_in_6_bits_set,
+  input  [1:0]  io_in_6_bits_param,
+  input         io_in_6_bits_alias,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [33:0] io_in_7_bits_tag,
+  input  [7:0]  io_in_7_bits_set,
+  input  [1:0]  io_in_7_bits_param,
+  input         io_in_7_bits_alias,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [33:0] io_out_bits_tag,
+  output [7:0]  io_out_bits_set,
+  output [2:0]  io_out_bits_opcode,
+  output [1:0]  io_out_bits_param,
+  output        io_out_bits_alias
+);
+
+  wire [7:0] chosenOH;
+  wire [7:0] valids =
+    {io_in_7_valid,
+     io_in_6_valid,
+     io_in_5_valid,
+     io_in_4_valid,
+     io_in_3_valid,
+     io_in_2_valid,
+     io_in_1_valid,
+     io_in_0_valid};
+  reg  [7:0] pendingMask;
+  reg  [7:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire       _rrSelOH_T_2 = rrGrantMask[1] & pendingMask[1];
+  wire       _rrSelOH_T_3 = rrGrantMask[2] & pendingMask[2];
+  wire       _rrSelOH_T_4 = rrGrantMask[3] & pendingMask[3];
+  wire       _rrSelOH_T_5 = rrGrantMask[4] & pendingMask[4];
+  wire       _rrSelOH_T_6 = rrGrantMask[5] & pendingMask[5];
+  wire       _rrSelOH_T_7 = rrGrantMask[6] & pendingMask[6];
+  wire [7:0] rrSelOH =
+    {rrGrantMask[7] & pendingMask[7]
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7} == 7'h0,
+     _rrSelOH_T_7
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6} == 6'h0,
+     _rrSelOH_T_6
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5} == 5'h0,
+     _rrSelOH_T_5
+       & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3, _rrSelOH_T_4} == 4'h0,
+     _rrSelOH_T_4 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3} == 3'h0,
+     _rrSelOH_T_3 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2} == 2'h0,
+     _rrSelOH_T_2 & ~_rrSelOH_oh_WIRE_0,
+     _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids))
+      ? rrSelOH
+      : {io_in_7_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid} == 7'h0,
+         io_in_6_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid} == 6'h0,
+         io_in_5_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid} == 5'h0,
+         io_in_4_valid
+           & {io_in_0_valid, io_in_1_valid, io_in_2_valid, io_in_3_valid} == 4'h0,
+         io_in_3_valid & {io_in_0_valid, io_in_1_valid, io_in_2_valid} == 3'h0,
+         io_in_2_valid & {io_in_0_valid, io_in_1_valid} == 2'h0,
+         io_in_1_valid & ~io_in_0_valid,
+         io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 8'h0;
+      rrGrantMask <= 8'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <=
+        {|(chosenOH[6:0]),
+         |(chosenOH[5:0]),
+         |(chosenOH[4:0]),
+         |(chosenOH[3:0]),
+         |(chosenOH[2:0]),
+         |(chosenOH[1:0]),
+         chosenOH[0],
+         1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][7:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][15:8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 8'h0;
+        rrGrantMask = 8'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_in_2_ready = chosenOH[2] & io_out_ready;
+  assign io_in_3_ready = chosenOH[3] & io_out_ready;
+  assign io_in_4_ready = chosenOH[4] & io_out_ready;
+  assign io_in_5_ready = chosenOH[5] & io_out_ready;
+  assign io_in_6_ready = chosenOH[6] & io_out_ready;
+  assign io_in_7_ready = chosenOH[7] & io_out_ready;
+  assign io_out_valid = |valids;
+  assign io_out_bits_tag =
+    (chosenOH[0] ? io_in_0_bits_tag : 34'h0) | (chosenOH[1] ? io_in_1_bits_tag : 34'h0)
+    | (chosenOH[2] ? io_in_2_bits_tag : 34'h0) | (chosenOH[3] ? io_in_3_bits_tag : 34'h0)
+    | (chosenOH[4] ? io_in_4_bits_tag : 34'h0) | (chosenOH[5] ? io_in_5_bits_tag : 34'h0)
+    | (chosenOH[6] ? io_in_6_bits_tag : 34'h0) | (chosenOH[7] ? io_in_7_bits_tag : 34'h0);
+  assign io_out_bits_set =
+    (chosenOH[0] ? io_in_0_bits_set : 8'h0) | (chosenOH[1] ? io_in_1_bits_set : 8'h0)
+    | (chosenOH[2] ? io_in_2_bits_set : 8'h0) | (chosenOH[3] ? io_in_3_bits_set : 8'h0)
+    | (chosenOH[4] ? io_in_4_bits_set : 8'h0) | (chosenOH[5] ? io_in_5_bits_set : 8'h0)
+    | (chosenOH[6] ? io_in_6_bits_set : 8'h0) | (chosenOH[7] ? io_in_7_bits_set : 8'h0);
+  assign io_out_bits_opcode = (|chosenOH) ? 3'h6 : 3'h0;
+  assign io_out_bits_param =
+    (chosenOH[0] ? io_in_0_bits_param : 2'h0) | (chosenOH[1] ? io_in_1_bits_param : 2'h0)
+    | (chosenOH[2] ? io_in_2_bits_param : 2'h0)
+    | (chosenOH[3] ? io_in_3_bits_param : 2'h0)
+    | (chosenOH[4] ? io_in_4_bits_param : 2'h0)
+    | (chosenOH[5] ? io_in_5_bits_param : 2'h0)
+    | (chosenOH[6] ? io_in_6_bits_param : 2'h0)
+    | (chosenOH[7] ? io_in_7_bits_param : 2'h0);
+  assign io_out_bits_alias =
+    chosenOH[0] & io_in_0_bits_alias | chosenOH[1] & io_in_1_bits_alias | chosenOH[2]
+    & io_in_2_bits_alias | chosenOH[3] & io_in_3_bits_alias | chosenOH[4]
+    & io_in_4_bits_alias | chosenOH[5] & io_in_5_bits_alias | chosenOH[6]
+    & io_in_6_bits_alias | chosenOH[7] & io_in_7_bits_alias;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_22.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_22.sv
new file mode 100644
index 0000000000..fbc907a2fb
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_22.sv
@@ -0,0 +1,1430 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_22(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [2:0]  io_in_0_bits_channel,
+  input  [2:0]  io_in_0_bits_txChannel,
+  input  [7:0]  io_in_0_bits_set,
+  input  [33:0] io_in_0_bits_tag,
+  input  [5:0]  io_in_0_bits_off,
+  input         io_in_0_bits_alias,
+  input         io_in_0_bits_isKeyword,
+  input  [3:0]  io_in_0_bits_opcode,
+  input  [2:0]  io_in_0_bits_param,
+  input  [2:0]  io_in_0_bits_size,
+  input  [6:0]  io_in_0_bits_sourceId,
+  input         io_in_0_bits_denied,
+  input         io_in_0_bits_corrupt,
+  input         io_in_0_bits_aliasTask,
+  input         io_in_0_bits_useProbeData,
+  input         io_in_0_bits_mshrRetry,
+  input         io_in_0_bits_readProbeDataDown,
+  input         io_in_0_bits_fromL2pft,
+  input         io_in_0_bits_dirty,
+  input  [2:0]  io_in_0_bits_way,
+  input         io_in_0_bits_meta_dirty,
+  input  [1:0]  io_in_0_bits_meta_state,
+  input         io_in_0_bits_meta_clients,
+  input         io_in_0_bits_meta_alias,
+  input         io_in_0_bits_meta_prefetch,
+  input  [3:0]  io_in_0_bits_meta_prefetchSrc,
+  input         io_in_0_bits_meta_accessed,
+  input         io_in_0_bits_meta_tagErr,
+  input         io_in_0_bits_meta_dataErr,
+  input         io_in_0_bits_metaWen,
+  input         io_in_0_bits_tagWen,
+  input         io_in_0_bits_dsWen,
+  input         io_in_0_bits_replTask,
+  input         io_in_0_bits_cmoTask,
+  input  [4:0]  io_in_0_bits_reqSource,
+  input         io_in_0_bits_mergeA,
+  input  [5:0]  io_in_0_bits_aMergeTask_off,
+  input         io_in_0_bits_aMergeTask_alias,
+  input  [43:0] io_in_0_bits_aMergeTask_vaddr,
+  input         io_in_0_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_0_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_0_bits_aMergeTask_param,
+  input  [6:0]  io_in_0_bits_aMergeTask_sourceId,
+  input         io_in_0_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_0_bits_aMergeTask_meta_state,
+  input         io_in_0_bits_aMergeTask_meta_clients,
+  input         io_in_0_bits_aMergeTask_meta_alias,
+  input         io_in_0_bits_aMergeTask_meta_accessed,
+  input         io_in_0_bits_snpHitRelease,
+  input         io_in_0_bits_snpHitReleaseToInval,
+  input         io_in_0_bits_snpHitReleaseToClean,
+  input         io_in_0_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_0_bits_snpHitReleaseIdx,
+  input         io_in_0_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_0_bits_snpHitReleaseMeta_state,
+  input         io_in_0_bits_snpHitReleaseMeta_clients,
+  input         io_in_0_bits_snpHitReleaseMeta_alias,
+  input         io_in_0_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_0_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_0_bits_snpHitReleaseMeta_accessed,
+  input         io_in_0_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_0_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [10:0] io_in_0_bits_homeNID,
+  input  [11:0] io_in_0_bits_dbID,
+  input  [6:0]  io_in_0_bits_chiOpcode,
+  input  [2:0]  io_in_0_bits_resp,
+  input  [2:0]  io_in_0_bits_fwdState,
+  input         io_in_0_bits_retToSrc,
+  input         io_in_0_bits_likelyshared,
+  input         io_in_0_bits_expCompAck,
+  input         io_in_0_bits_allowRetry,
+  input         io_in_0_bits_memAttr_allocate,
+  input         io_in_0_bits_memAttr_cacheable,
+  input         io_in_0_bits_memAttr_ewa,
+  input         io_in_0_bits_traceTag,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [2:0]  io_in_1_bits_channel,
+  input  [2:0]  io_in_1_bits_txChannel,
+  input  [7:0]  io_in_1_bits_set,
+  input  [33:0] io_in_1_bits_tag,
+  input  [5:0]  io_in_1_bits_off,
+  input         io_in_1_bits_alias,
+  input         io_in_1_bits_isKeyword,
+  input  [3:0]  io_in_1_bits_opcode,
+  input  [2:0]  io_in_1_bits_param,
+  input  [2:0]  io_in_1_bits_size,
+  input  [6:0]  io_in_1_bits_sourceId,
+  input         io_in_1_bits_denied,
+  input         io_in_1_bits_corrupt,
+  input         io_in_1_bits_aliasTask,
+  input         io_in_1_bits_useProbeData,
+  input         io_in_1_bits_mshrRetry,
+  input         io_in_1_bits_readProbeDataDown,
+  input         io_in_1_bits_fromL2pft,
+  input         io_in_1_bits_dirty,
+  input  [2:0]  io_in_1_bits_way,
+  input         io_in_1_bits_meta_dirty,
+  input  [1:0]  io_in_1_bits_meta_state,
+  input         io_in_1_bits_meta_clients,
+  input         io_in_1_bits_meta_alias,
+  input         io_in_1_bits_meta_prefetch,
+  input  [3:0]  io_in_1_bits_meta_prefetchSrc,
+  input         io_in_1_bits_meta_accessed,
+  input         io_in_1_bits_meta_tagErr,
+  input         io_in_1_bits_meta_dataErr,
+  input         io_in_1_bits_metaWen,
+  input         io_in_1_bits_tagWen,
+  input         io_in_1_bits_dsWen,
+  input         io_in_1_bits_replTask,
+  input         io_in_1_bits_cmoTask,
+  input  [4:0]  io_in_1_bits_reqSource,
+  input         io_in_1_bits_mergeA,
+  input  [5:0]  io_in_1_bits_aMergeTask_off,
+  input         io_in_1_bits_aMergeTask_alias,
+  input  [43:0] io_in_1_bits_aMergeTask_vaddr,
+  input         io_in_1_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_1_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_1_bits_aMergeTask_param,
+  input  [6:0]  io_in_1_bits_aMergeTask_sourceId,
+  input         io_in_1_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_1_bits_aMergeTask_meta_state,
+  input         io_in_1_bits_aMergeTask_meta_clients,
+  input         io_in_1_bits_aMergeTask_meta_alias,
+  input         io_in_1_bits_aMergeTask_meta_accessed,
+  input         io_in_1_bits_snpHitRelease,
+  input         io_in_1_bits_snpHitReleaseToInval,
+  input         io_in_1_bits_snpHitReleaseToClean,
+  input         io_in_1_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_1_bits_snpHitReleaseIdx,
+  input         io_in_1_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_1_bits_snpHitReleaseMeta_state,
+  input         io_in_1_bits_snpHitReleaseMeta_clients,
+  input         io_in_1_bits_snpHitReleaseMeta_alias,
+  input         io_in_1_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_1_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_1_bits_snpHitReleaseMeta_accessed,
+  input         io_in_1_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_1_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [11:0] io_in_1_bits_txnID,
+  input  [10:0] io_in_1_bits_homeNID,
+  input  [11:0] io_in_1_bits_dbID,
+  input  [6:0]  io_in_1_bits_chiOpcode,
+  input  [2:0]  io_in_1_bits_resp,
+  input  [2:0]  io_in_1_bits_fwdState,
+  input         io_in_1_bits_retToSrc,
+  input         io_in_1_bits_likelyshared,
+  input         io_in_1_bits_expCompAck,
+  input         io_in_1_bits_allowRetry,
+  input         io_in_1_bits_memAttr_allocate,
+  input         io_in_1_bits_memAttr_cacheable,
+  input         io_in_1_bits_memAttr_ewa,
+  input         io_in_1_bits_traceTag,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [2:0]  io_in_2_bits_channel,
+  input  [2:0]  io_in_2_bits_txChannel,
+  input  [7:0]  io_in_2_bits_set,
+  input  [33:0] io_in_2_bits_tag,
+  input  [5:0]  io_in_2_bits_off,
+  input         io_in_2_bits_alias,
+  input         io_in_2_bits_isKeyword,
+  input  [3:0]  io_in_2_bits_opcode,
+  input  [2:0]  io_in_2_bits_param,
+  input  [2:0]  io_in_2_bits_size,
+  input  [6:0]  io_in_2_bits_sourceId,
+  input         io_in_2_bits_denied,
+  input         io_in_2_bits_corrupt,
+  input         io_in_2_bits_aliasTask,
+  input         io_in_2_bits_useProbeData,
+  input         io_in_2_bits_mshrRetry,
+  input         io_in_2_bits_readProbeDataDown,
+  input         io_in_2_bits_fromL2pft,
+  input         io_in_2_bits_dirty,
+  input  [2:0]  io_in_2_bits_way,
+  input         io_in_2_bits_meta_dirty,
+  input  [1:0]  io_in_2_bits_meta_state,
+  input         io_in_2_bits_meta_clients,
+  input         io_in_2_bits_meta_alias,
+  input         io_in_2_bits_meta_prefetch,
+  input  [3:0]  io_in_2_bits_meta_prefetchSrc,
+  input         io_in_2_bits_meta_accessed,
+  input         io_in_2_bits_meta_tagErr,
+  input         io_in_2_bits_meta_dataErr,
+  input         io_in_2_bits_metaWen,
+  input         io_in_2_bits_tagWen,
+  input         io_in_2_bits_dsWen,
+  input         io_in_2_bits_replTask,
+  input         io_in_2_bits_cmoTask,
+  input  [4:0]  io_in_2_bits_reqSource,
+  input         io_in_2_bits_mergeA,
+  input  [5:0]  io_in_2_bits_aMergeTask_off,
+  input         io_in_2_bits_aMergeTask_alias,
+  input  [43:0] io_in_2_bits_aMergeTask_vaddr,
+  input         io_in_2_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_2_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_2_bits_aMergeTask_param,
+  input  [6:0]  io_in_2_bits_aMergeTask_sourceId,
+  input         io_in_2_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_2_bits_aMergeTask_meta_state,
+  input         io_in_2_bits_aMergeTask_meta_clients,
+  input         io_in_2_bits_aMergeTask_meta_alias,
+  input         io_in_2_bits_aMergeTask_meta_accessed,
+  input         io_in_2_bits_snpHitRelease,
+  input         io_in_2_bits_snpHitReleaseToInval,
+  input         io_in_2_bits_snpHitReleaseToClean,
+  input         io_in_2_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_2_bits_snpHitReleaseIdx,
+  input         io_in_2_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_2_bits_snpHitReleaseMeta_state,
+  input         io_in_2_bits_snpHitReleaseMeta_clients,
+  input         io_in_2_bits_snpHitReleaseMeta_alias,
+  input         io_in_2_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_2_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_2_bits_snpHitReleaseMeta_accessed,
+  input         io_in_2_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_2_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_2_bits_tgtID,
+  input  [11:0] io_in_2_bits_txnID,
+  input  [10:0] io_in_2_bits_homeNID,
+  input  [11:0] io_in_2_bits_dbID,
+  input  [6:0]  io_in_2_bits_chiOpcode,
+  input  [2:0]  io_in_2_bits_resp,
+  input  [2:0]  io_in_2_bits_fwdState,
+  input         io_in_2_bits_retToSrc,
+  input         io_in_2_bits_likelyshared,
+  input         io_in_2_bits_expCompAck,
+  input         io_in_2_bits_allowRetry,
+  input         io_in_2_bits_memAttr_allocate,
+  input         io_in_2_bits_memAttr_cacheable,
+  input         io_in_2_bits_memAttr_ewa,
+  input         io_in_2_bits_traceTag,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [2:0]  io_in_3_bits_channel,
+  input  [2:0]  io_in_3_bits_txChannel,
+  input  [7:0]  io_in_3_bits_set,
+  input  [33:0] io_in_3_bits_tag,
+  input  [5:0]  io_in_3_bits_off,
+  input         io_in_3_bits_alias,
+  input         io_in_3_bits_isKeyword,
+  input  [3:0]  io_in_3_bits_opcode,
+  input  [2:0]  io_in_3_bits_param,
+  input  [2:0]  io_in_3_bits_size,
+  input  [6:0]  io_in_3_bits_sourceId,
+  input         io_in_3_bits_denied,
+  input         io_in_3_bits_corrupt,
+  input         io_in_3_bits_aliasTask,
+  input         io_in_3_bits_useProbeData,
+  input         io_in_3_bits_mshrRetry,
+  input         io_in_3_bits_readProbeDataDown,
+  input         io_in_3_bits_fromL2pft,
+  input         io_in_3_bits_dirty,
+  input  [2:0]  io_in_3_bits_way,
+  input         io_in_3_bits_meta_dirty,
+  input  [1:0]  io_in_3_bits_meta_state,
+  input         io_in_3_bits_meta_clients,
+  input         io_in_3_bits_meta_alias,
+  input         io_in_3_bits_meta_prefetch,
+  input  [3:0]  io_in_3_bits_meta_prefetchSrc,
+  input         io_in_3_bits_meta_accessed,
+  input         io_in_3_bits_meta_tagErr,
+  input         io_in_3_bits_meta_dataErr,
+  input         io_in_3_bits_metaWen,
+  input         io_in_3_bits_tagWen,
+  input         io_in_3_bits_dsWen,
+  input         io_in_3_bits_replTask,
+  input         io_in_3_bits_cmoTask,
+  input  [4:0]  io_in_3_bits_reqSource,
+  input         io_in_3_bits_mergeA,
+  input  [5:0]  io_in_3_bits_aMergeTask_off,
+  input         io_in_3_bits_aMergeTask_alias,
+  input  [43:0] io_in_3_bits_aMergeTask_vaddr,
+  input         io_in_3_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_3_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_3_bits_aMergeTask_param,
+  input  [6:0]  io_in_3_bits_aMergeTask_sourceId,
+  input         io_in_3_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_3_bits_aMergeTask_meta_state,
+  input         io_in_3_bits_aMergeTask_meta_clients,
+  input         io_in_3_bits_aMergeTask_meta_alias,
+  input         io_in_3_bits_aMergeTask_meta_accessed,
+  input         io_in_3_bits_snpHitRelease,
+  input         io_in_3_bits_snpHitReleaseToInval,
+  input         io_in_3_bits_snpHitReleaseToClean,
+  input         io_in_3_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_3_bits_snpHitReleaseIdx,
+  input         io_in_3_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_3_bits_snpHitReleaseMeta_state,
+  input         io_in_3_bits_snpHitReleaseMeta_clients,
+  input         io_in_3_bits_snpHitReleaseMeta_alias,
+  input         io_in_3_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_3_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_3_bits_snpHitReleaseMeta_accessed,
+  input         io_in_3_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_3_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_3_bits_tgtID,
+  input  [11:0] io_in_3_bits_txnID,
+  input  [10:0] io_in_3_bits_homeNID,
+  input  [11:0] io_in_3_bits_dbID,
+  input  [6:0]  io_in_3_bits_chiOpcode,
+  input  [2:0]  io_in_3_bits_resp,
+  input  [2:0]  io_in_3_bits_fwdState,
+  input         io_in_3_bits_retToSrc,
+  input         io_in_3_bits_likelyshared,
+  input         io_in_3_bits_expCompAck,
+  input         io_in_3_bits_allowRetry,
+  input         io_in_3_bits_memAttr_allocate,
+  input         io_in_3_bits_memAttr_cacheable,
+  input         io_in_3_bits_memAttr_ewa,
+  input         io_in_3_bits_traceTag,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [2:0]  io_in_4_bits_channel,
+  input  [2:0]  io_in_4_bits_txChannel,
+  input  [7:0]  io_in_4_bits_set,
+  input  [33:0] io_in_4_bits_tag,
+  input  [5:0]  io_in_4_bits_off,
+  input         io_in_4_bits_alias,
+  input         io_in_4_bits_isKeyword,
+  input  [3:0]  io_in_4_bits_opcode,
+  input  [2:0]  io_in_4_bits_param,
+  input  [2:0]  io_in_4_bits_size,
+  input  [6:0]  io_in_4_bits_sourceId,
+  input         io_in_4_bits_denied,
+  input         io_in_4_bits_corrupt,
+  input         io_in_4_bits_aliasTask,
+  input         io_in_4_bits_useProbeData,
+  input         io_in_4_bits_mshrRetry,
+  input         io_in_4_bits_readProbeDataDown,
+  input         io_in_4_bits_fromL2pft,
+  input         io_in_4_bits_dirty,
+  input  [2:0]  io_in_4_bits_way,
+  input         io_in_4_bits_meta_dirty,
+  input  [1:0]  io_in_4_bits_meta_state,
+  input         io_in_4_bits_meta_clients,
+  input         io_in_4_bits_meta_alias,
+  input         io_in_4_bits_meta_prefetch,
+  input  [3:0]  io_in_4_bits_meta_prefetchSrc,
+  input         io_in_4_bits_meta_accessed,
+  input         io_in_4_bits_meta_tagErr,
+  input         io_in_4_bits_meta_dataErr,
+  input         io_in_4_bits_metaWen,
+  input         io_in_4_bits_tagWen,
+  input         io_in_4_bits_dsWen,
+  input         io_in_4_bits_replTask,
+  input         io_in_4_bits_cmoTask,
+  input  [4:0]  io_in_4_bits_reqSource,
+  input         io_in_4_bits_mergeA,
+  input  [5:0]  io_in_4_bits_aMergeTask_off,
+  input         io_in_4_bits_aMergeTask_alias,
+  input  [43:0] io_in_4_bits_aMergeTask_vaddr,
+  input         io_in_4_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_4_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_4_bits_aMergeTask_param,
+  input  [6:0]  io_in_4_bits_aMergeTask_sourceId,
+  input         io_in_4_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_4_bits_aMergeTask_meta_state,
+  input         io_in_4_bits_aMergeTask_meta_clients,
+  input         io_in_4_bits_aMergeTask_meta_alias,
+  input         io_in_4_bits_aMergeTask_meta_accessed,
+  input         io_in_4_bits_snpHitRelease,
+  input         io_in_4_bits_snpHitReleaseToInval,
+  input         io_in_4_bits_snpHitReleaseToClean,
+  input         io_in_4_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_4_bits_snpHitReleaseIdx,
+  input         io_in_4_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_4_bits_snpHitReleaseMeta_state,
+  input         io_in_4_bits_snpHitReleaseMeta_clients,
+  input         io_in_4_bits_snpHitReleaseMeta_alias,
+  input         io_in_4_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_4_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_4_bits_snpHitReleaseMeta_accessed,
+  input         io_in_4_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_4_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_4_bits_tgtID,
+  input  [11:0] io_in_4_bits_txnID,
+  input  [10:0] io_in_4_bits_homeNID,
+  input  [11:0] io_in_4_bits_dbID,
+  input  [6:0]  io_in_4_bits_chiOpcode,
+  input  [2:0]  io_in_4_bits_resp,
+  input  [2:0]  io_in_4_bits_fwdState,
+  input         io_in_4_bits_retToSrc,
+  input         io_in_4_bits_likelyshared,
+  input         io_in_4_bits_expCompAck,
+  input         io_in_4_bits_allowRetry,
+  input         io_in_4_bits_memAttr_allocate,
+  input         io_in_4_bits_memAttr_cacheable,
+  input         io_in_4_bits_memAttr_ewa,
+  input         io_in_4_bits_traceTag,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [2:0]  io_in_5_bits_channel,
+  input  [2:0]  io_in_5_bits_txChannel,
+  input  [7:0]  io_in_5_bits_set,
+  input  [33:0] io_in_5_bits_tag,
+  input  [5:0]  io_in_5_bits_off,
+  input         io_in_5_bits_alias,
+  input         io_in_5_bits_isKeyword,
+  input  [3:0]  io_in_5_bits_opcode,
+  input  [2:0]  io_in_5_bits_param,
+  input  [2:0]  io_in_5_bits_size,
+  input  [6:0]  io_in_5_bits_sourceId,
+  input         io_in_5_bits_denied,
+  input         io_in_5_bits_corrupt,
+  input         io_in_5_bits_aliasTask,
+  input         io_in_5_bits_useProbeData,
+  input         io_in_5_bits_mshrRetry,
+  input         io_in_5_bits_readProbeDataDown,
+  input         io_in_5_bits_fromL2pft,
+  input         io_in_5_bits_dirty,
+  input  [2:0]  io_in_5_bits_way,
+  input         io_in_5_bits_meta_dirty,
+  input  [1:0]  io_in_5_bits_meta_state,
+  input         io_in_5_bits_meta_clients,
+  input         io_in_5_bits_meta_alias,
+  input         io_in_5_bits_meta_prefetch,
+  input  [3:0]  io_in_5_bits_meta_prefetchSrc,
+  input         io_in_5_bits_meta_accessed,
+  input         io_in_5_bits_meta_tagErr,
+  input         io_in_5_bits_meta_dataErr,
+  input         io_in_5_bits_metaWen,
+  input         io_in_5_bits_tagWen,
+  input         io_in_5_bits_dsWen,
+  input         io_in_5_bits_replTask,
+  input         io_in_5_bits_cmoTask,
+  input  [4:0]  io_in_5_bits_reqSource,
+  input         io_in_5_bits_mergeA,
+  input  [5:0]  io_in_5_bits_aMergeTask_off,
+  input         io_in_5_bits_aMergeTask_alias,
+  input  [43:0] io_in_5_bits_aMergeTask_vaddr,
+  input         io_in_5_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_5_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_5_bits_aMergeTask_param,
+  input  [6:0]  io_in_5_bits_aMergeTask_sourceId,
+  input         io_in_5_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_5_bits_aMergeTask_meta_state,
+  input         io_in_5_bits_aMergeTask_meta_clients,
+  input         io_in_5_bits_aMergeTask_meta_alias,
+  input         io_in_5_bits_aMergeTask_meta_accessed,
+  input         io_in_5_bits_snpHitRelease,
+  input         io_in_5_bits_snpHitReleaseToInval,
+  input         io_in_5_bits_snpHitReleaseToClean,
+  input         io_in_5_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_5_bits_snpHitReleaseIdx,
+  input         io_in_5_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_5_bits_snpHitReleaseMeta_state,
+  input         io_in_5_bits_snpHitReleaseMeta_clients,
+  input         io_in_5_bits_snpHitReleaseMeta_alias,
+  input         io_in_5_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_5_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_5_bits_snpHitReleaseMeta_accessed,
+  input         io_in_5_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_5_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_5_bits_tgtID,
+  input  [11:0] io_in_5_bits_txnID,
+  input  [10:0] io_in_5_bits_homeNID,
+  input  [11:0] io_in_5_bits_dbID,
+  input  [6:0]  io_in_5_bits_chiOpcode,
+  input  [2:0]  io_in_5_bits_resp,
+  input  [2:0]  io_in_5_bits_fwdState,
+  input         io_in_5_bits_retToSrc,
+  input         io_in_5_bits_likelyshared,
+  input         io_in_5_bits_expCompAck,
+  input         io_in_5_bits_allowRetry,
+  input         io_in_5_bits_memAttr_allocate,
+  input         io_in_5_bits_memAttr_cacheable,
+  input         io_in_5_bits_memAttr_ewa,
+  input         io_in_5_bits_traceTag,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [2:0]  io_in_6_bits_channel,
+  input  [2:0]  io_in_6_bits_txChannel,
+  input  [7:0]  io_in_6_bits_set,
+  input  [33:0] io_in_6_bits_tag,
+  input  [5:0]  io_in_6_bits_off,
+  input         io_in_6_bits_alias,
+  input         io_in_6_bits_isKeyword,
+  input  [3:0]  io_in_6_bits_opcode,
+  input  [2:0]  io_in_6_bits_param,
+  input  [2:0]  io_in_6_bits_size,
+  input  [6:0]  io_in_6_bits_sourceId,
+  input         io_in_6_bits_denied,
+  input         io_in_6_bits_corrupt,
+  input         io_in_6_bits_aliasTask,
+  input         io_in_6_bits_useProbeData,
+  input         io_in_6_bits_mshrRetry,
+  input         io_in_6_bits_readProbeDataDown,
+  input         io_in_6_bits_fromL2pft,
+  input         io_in_6_bits_dirty,
+  input  [2:0]  io_in_6_bits_way,
+  input         io_in_6_bits_meta_dirty,
+  input  [1:0]  io_in_6_bits_meta_state,
+  input         io_in_6_bits_meta_clients,
+  input         io_in_6_bits_meta_alias,
+  input         io_in_6_bits_meta_prefetch,
+  input  [3:0]  io_in_6_bits_meta_prefetchSrc,
+  input         io_in_6_bits_meta_accessed,
+  input         io_in_6_bits_meta_tagErr,
+  input         io_in_6_bits_meta_dataErr,
+  input         io_in_6_bits_metaWen,
+  input         io_in_6_bits_tagWen,
+  input         io_in_6_bits_dsWen,
+  input         io_in_6_bits_replTask,
+  input         io_in_6_bits_cmoTask,
+  input  [4:0]  io_in_6_bits_reqSource,
+  input         io_in_6_bits_mergeA,
+  input  [5:0]  io_in_6_bits_aMergeTask_off,
+  input         io_in_6_bits_aMergeTask_alias,
+  input  [43:0] io_in_6_bits_aMergeTask_vaddr,
+  input         io_in_6_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_6_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_6_bits_aMergeTask_param,
+  input  [6:0]  io_in_6_bits_aMergeTask_sourceId,
+  input         io_in_6_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_6_bits_aMergeTask_meta_state,
+  input         io_in_6_bits_aMergeTask_meta_clients,
+  input         io_in_6_bits_aMergeTask_meta_alias,
+  input         io_in_6_bits_aMergeTask_meta_accessed,
+  input         io_in_6_bits_snpHitRelease,
+  input         io_in_6_bits_snpHitReleaseToInval,
+  input         io_in_6_bits_snpHitReleaseToClean,
+  input         io_in_6_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_6_bits_snpHitReleaseIdx,
+  input         io_in_6_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_6_bits_snpHitReleaseMeta_state,
+  input         io_in_6_bits_snpHitReleaseMeta_clients,
+  input         io_in_6_bits_snpHitReleaseMeta_alias,
+  input         io_in_6_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_6_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_6_bits_snpHitReleaseMeta_accessed,
+  input         io_in_6_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_6_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_6_bits_tgtID,
+  input  [11:0] io_in_6_bits_txnID,
+  input  [10:0] io_in_6_bits_homeNID,
+  input  [11:0] io_in_6_bits_dbID,
+  input  [6:0]  io_in_6_bits_chiOpcode,
+  input  [2:0]  io_in_6_bits_resp,
+  input  [2:0]  io_in_6_bits_fwdState,
+  input         io_in_6_bits_retToSrc,
+  input         io_in_6_bits_likelyshared,
+  input         io_in_6_bits_expCompAck,
+  input         io_in_6_bits_allowRetry,
+  input         io_in_6_bits_memAttr_allocate,
+  input         io_in_6_bits_memAttr_cacheable,
+  input         io_in_6_bits_memAttr_ewa,
+  input         io_in_6_bits_traceTag,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [2:0]  io_in_7_bits_channel,
+  input  [2:0]  io_in_7_bits_txChannel,
+  input  [7:0]  io_in_7_bits_set,
+  input  [33:0] io_in_7_bits_tag,
+  input  [5:0]  io_in_7_bits_off,
+  input         io_in_7_bits_alias,
+  input         io_in_7_bits_isKeyword,
+  input  [3:0]  io_in_7_bits_opcode,
+  input  [2:0]  io_in_7_bits_param,
+  input  [2:0]  io_in_7_bits_size,
+  input  [6:0]  io_in_7_bits_sourceId,
+  input         io_in_7_bits_denied,
+  input         io_in_7_bits_corrupt,
+  input         io_in_7_bits_aliasTask,
+  input         io_in_7_bits_useProbeData,
+  input         io_in_7_bits_mshrRetry,
+  input         io_in_7_bits_readProbeDataDown,
+  input         io_in_7_bits_fromL2pft,
+  input         io_in_7_bits_dirty,
+  input  [2:0]  io_in_7_bits_way,
+  input         io_in_7_bits_meta_dirty,
+  input  [1:0]  io_in_7_bits_meta_state,
+  input         io_in_7_bits_meta_clients,
+  input         io_in_7_bits_meta_alias,
+  input         io_in_7_bits_meta_prefetch,
+  input  [3:0]  io_in_7_bits_meta_prefetchSrc,
+  input         io_in_7_bits_meta_accessed,
+  input         io_in_7_bits_meta_tagErr,
+  input         io_in_7_bits_meta_dataErr,
+  input         io_in_7_bits_metaWen,
+  input         io_in_7_bits_tagWen,
+  input         io_in_7_bits_dsWen,
+  input         io_in_7_bits_replTask,
+  input         io_in_7_bits_cmoTask,
+  input  [4:0]  io_in_7_bits_reqSource,
+  input         io_in_7_bits_mergeA,
+  input  [5:0]  io_in_7_bits_aMergeTask_off,
+  input         io_in_7_bits_aMergeTask_alias,
+  input  [43:0] io_in_7_bits_aMergeTask_vaddr,
+  input         io_in_7_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_7_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_7_bits_aMergeTask_param,
+  input  [6:0]  io_in_7_bits_aMergeTask_sourceId,
+  input         io_in_7_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_7_bits_aMergeTask_meta_state,
+  input         io_in_7_bits_aMergeTask_meta_clients,
+  input         io_in_7_bits_aMergeTask_meta_alias,
+  input         io_in_7_bits_aMergeTask_meta_accessed,
+  input         io_in_7_bits_snpHitRelease,
+  input         io_in_7_bits_snpHitReleaseToInval,
+  input         io_in_7_bits_snpHitReleaseToClean,
+  input         io_in_7_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_7_bits_snpHitReleaseIdx,
+  input         io_in_7_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_7_bits_snpHitReleaseMeta_state,
+  input         io_in_7_bits_snpHitReleaseMeta_clients,
+  input         io_in_7_bits_snpHitReleaseMeta_alias,
+  input         io_in_7_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_7_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_7_bits_snpHitReleaseMeta_accessed,
+  input         io_in_7_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_7_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_7_bits_tgtID,
+  input  [11:0] io_in_7_bits_txnID,
+  input  [10:0] io_in_7_bits_homeNID,
+  input  [11:0] io_in_7_bits_dbID,
+  input  [6:0]  io_in_7_bits_chiOpcode,
+  input  [2:0]  io_in_7_bits_resp,
+  input  [2:0]  io_in_7_bits_fwdState,
+  input         io_in_7_bits_retToSrc,
+  input         io_in_7_bits_likelyshared,
+  input         io_in_7_bits_expCompAck,
+  input         io_in_7_bits_allowRetry,
+  input         io_in_7_bits_memAttr_allocate,
+  input         io_in_7_bits_memAttr_cacheable,
+  input         io_in_7_bits_memAttr_ewa,
+  input         io_in_7_bits_traceTag,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [2:0]  io_out_bits_channel,
+  output [2:0]  io_out_bits_txChannel,
+  output [7:0]  io_out_bits_set,
+  output [33:0] io_out_bits_tag,
+  output [5:0]  io_out_bits_off,
+  output        io_out_bits_alias,
+  output        io_out_bits_isKeyword,
+  output [3:0]  io_out_bits_opcode,
+  output [2:0]  io_out_bits_param,
+  output [2:0]  io_out_bits_size,
+  output [6:0]  io_out_bits_sourceId,
+  output        io_out_bits_denied,
+  output        io_out_bits_corrupt,
+  output        io_out_bits_mshrTask,
+  output        io_out_bits_aliasTask,
+  output        io_out_bits_useProbeData,
+  output        io_out_bits_mshrRetry,
+  output        io_out_bits_readProbeDataDown,
+  output        io_out_bits_fromL2pft,
+  output        io_out_bits_dirty,
+  output [2:0]  io_out_bits_way,
+  output        io_out_bits_meta_dirty,
+  output [1:0]  io_out_bits_meta_state,
+  output        io_out_bits_meta_clients,
+  output        io_out_bits_meta_alias,
+  output        io_out_bits_meta_prefetch,
+  output [3:0]  io_out_bits_meta_prefetchSrc,
+  output        io_out_bits_meta_accessed,
+  output        io_out_bits_meta_tagErr,
+  output        io_out_bits_meta_dataErr,
+  output        io_out_bits_metaWen,
+  output        io_out_bits_tagWen,
+  output        io_out_bits_dsWen,
+  output        io_out_bits_replTask,
+  output        io_out_bits_cmoTask,
+  output [4:0]  io_out_bits_reqSource,
+  output        io_out_bits_mergeA,
+  output [5:0]  io_out_bits_aMergeTask_off,
+  output        io_out_bits_aMergeTask_alias,
+  output [43:0] io_out_bits_aMergeTask_vaddr,
+  output        io_out_bits_aMergeTask_isKeyword,
+  output [2:0]  io_out_bits_aMergeTask_opcode,
+  output [2:0]  io_out_bits_aMergeTask_param,
+  output [6:0]  io_out_bits_aMergeTask_sourceId,
+  output        io_out_bits_aMergeTask_meta_dirty,
+  output [1:0]  io_out_bits_aMergeTask_meta_state,
+  output        io_out_bits_aMergeTask_meta_clients,
+  output        io_out_bits_aMergeTask_meta_alias,
+  output        io_out_bits_aMergeTask_meta_accessed,
+  output        io_out_bits_snpHitRelease,
+  output        io_out_bits_snpHitReleaseToInval,
+  output        io_out_bits_snpHitReleaseToClean,
+  output        io_out_bits_snpHitReleaseWithData,
+  output [7:0]  io_out_bits_snpHitReleaseIdx,
+  output        io_out_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_out_bits_snpHitReleaseMeta_state,
+  output        io_out_bits_snpHitReleaseMeta_clients,
+  output        io_out_bits_snpHitReleaseMeta_alias,
+  output        io_out_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_out_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_out_bits_snpHitReleaseMeta_accessed,
+  output        io_out_bits_snpHitReleaseMeta_tagErr,
+  output        io_out_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_out_bits_tgtID,
+  output [11:0] io_out_bits_txnID,
+  output [10:0] io_out_bits_homeNID,
+  output [11:0] io_out_bits_dbID,
+  output [6:0]  io_out_bits_chiOpcode,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output        io_out_bits_retToSrc,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_expCompAck,
+  output        io_out_bits_allowRetry,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_traceTag,
+  output [7:0]  io_chosenOH
+);
+
+  wire [7:0] chosenOH;
+  wire [7:0] valids =
+    {io_in_7_valid,
+     io_in_6_valid,
+     io_in_5_valid,
+     io_in_4_valid,
+     io_in_3_valid,
+     io_in_2_valid,
+     io_in_1_valid,
+     io_in_0_valid};
+  reg  [7:0] pendingMask;
+  reg  [7:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire       _rrSelOH_T_2 = rrGrantMask[1] & pendingMask[1];
+  wire       _rrSelOH_T_3 = rrGrantMask[2] & pendingMask[2];
+  wire       _rrSelOH_T_4 = rrGrantMask[3] & pendingMask[3];
+  wire       _rrSelOH_T_5 = rrGrantMask[4] & pendingMask[4];
+  wire       _rrSelOH_T_6 = rrGrantMask[5] & pendingMask[5];
+  wire       _rrSelOH_T_7 = rrGrantMask[6] & pendingMask[6];
+  wire [7:0] rrSelOH =
+    {rrGrantMask[7] & pendingMask[7]
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7} == 7'h0,
+     _rrSelOH_T_7
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6} == 6'h0,
+     _rrSelOH_T_6
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5} == 5'h0,
+     _rrSelOH_T_5
+       & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3, _rrSelOH_T_4} == 4'h0,
+     _rrSelOH_T_4 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3} == 3'h0,
+     _rrSelOH_T_3 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2} == 2'h0,
+     _rrSelOH_T_2 & ~_rrSelOH_oh_WIRE_0,
+     _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids))
+      ? rrSelOH
+      : {io_in_7_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid} == 7'h0,
+         io_in_6_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid} == 6'h0,
+         io_in_5_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid} == 5'h0,
+         io_in_4_valid
+           & {io_in_0_valid, io_in_1_valid, io_in_2_valid, io_in_3_valid} == 4'h0,
+         io_in_3_valid & {io_in_0_valid, io_in_1_valid, io_in_2_valid} == 3'h0,
+         io_in_2_valid & {io_in_0_valid, io_in_1_valid} == 2'h0,
+         io_in_1_valid & ~io_in_0_valid,
+         io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 8'h0;
+      rrGrantMask <= 8'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <=
+        {|(chosenOH[6:0]),
+         |(chosenOH[5:0]),
+         |(chosenOH[4:0]),
+         |(chosenOH[3:0]),
+         |(chosenOH[2:0]),
+         |(chosenOH[1:0]),
+         chosenOH[0],
+         1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][7:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][15:8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 8'h0;
+        rrGrantMask = 8'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_in_2_ready = chosenOH[2] & io_out_ready;
+  assign io_in_3_ready = chosenOH[3] & io_out_ready;
+  assign io_in_4_ready = chosenOH[4] & io_out_ready;
+  assign io_in_5_ready = chosenOH[5] & io_out_ready;
+  assign io_in_6_ready = chosenOH[6] & io_out_ready;
+  assign io_in_7_ready = chosenOH[7] & io_out_ready;
+  assign io_out_valid = |valids;
+  assign io_out_bits_channel =
+    (chosenOH[0] ? io_in_0_bits_channel : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_channel : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_channel : 3'h0)
+    | (chosenOH[3] ? io_in_3_bits_channel : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_channel : 3'h0)
+    | (chosenOH[5] ? io_in_5_bits_channel : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_channel : 3'h0)
+    | (chosenOH[7] ? io_in_7_bits_channel : 3'h0);
+  assign io_out_bits_txChannel =
+    (chosenOH[0] ? io_in_0_bits_txChannel : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_txChannel : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_txChannel : 3'h0)
+    | (chosenOH[3] ? io_in_3_bits_txChannel : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_txChannel : 3'h0)
+    | (chosenOH[5] ? io_in_5_bits_txChannel : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_txChannel : 3'h0)
+    | (chosenOH[7] ? io_in_7_bits_txChannel : 3'h0);
+  assign io_out_bits_set =
+    (chosenOH[0] ? io_in_0_bits_set : 8'h0) | (chosenOH[1] ? io_in_1_bits_set : 8'h0)
+    | (chosenOH[2] ? io_in_2_bits_set : 8'h0) | (chosenOH[3] ? io_in_3_bits_set : 8'h0)
+    | (chosenOH[4] ? io_in_4_bits_set : 8'h0) | (chosenOH[5] ? io_in_5_bits_set : 8'h0)
+    | (chosenOH[6] ? io_in_6_bits_set : 8'h0) | (chosenOH[7] ? io_in_7_bits_set : 8'h0);
+  assign io_out_bits_tag =
+    (chosenOH[0] ? io_in_0_bits_tag : 34'h0) | (chosenOH[1] ? io_in_1_bits_tag : 34'h0)
+    | (chosenOH[2] ? io_in_2_bits_tag : 34'h0) | (chosenOH[3] ? io_in_3_bits_tag : 34'h0)
+    | (chosenOH[4] ? io_in_4_bits_tag : 34'h0) | (chosenOH[5] ? io_in_5_bits_tag : 34'h0)
+    | (chosenOH[6] ? io_in_6_bits_tag : 34'h0) | (chosenOH[7] ? io_in_7_bits_tag : 34'h0);
+  assign io_out_bits_off =
+    (chosenOH[0] ? io_in_0_bits_off : 6'h0) | (chosenOH[1] ? io_in_1_bits_off : 6'h0)
+    | (chosenOH[2] ? io_in_2_bits_off : 6'h0) | (chosenOH[3] ? io_in_3_bits_off : 6'h0)
+    | (chosenOH[4] ? io_in_4_bits_off : 6'h0) | (chosenOH[5] ? io_in_5_bits_off : 6'h0)
+    | (chosenOH[6] ? io_in_6_bits_off : 6'h0) | (chosenOH[7] ? io_in_7_bits_off : 6'h0);
+  assign io_out_bits_alias =
+    chosenOH[0] & io_in_0_bits_alias | chosenOH[1] & io_in_1_bits_alias | chosenOH[2]
+    & io_in_2_bits_alias | chosenOH[3] & io_in_3_bits_alias | chosenOH[4]
+    & io_in_4_bits_alias | chosenOH[5] & io_in_5_bits_alias | chosenOH[6]
+    & io_in_6_bits_alias | chosenOH[7] & io_in_7_bits_alias;
+  assign io_out_bits_isKeyword =
+    chosenOH[0] & io_in_0_bits_isKeyword | chosenOH[1] & io_in_1_bits_isKeyword
+    | chosenOH[2] & io_in_2_bits_isKeyword | chosenOH[3] & io_in_3_bits_isKeyword
+    | chosenOH[4] & io_in_4_bits_isKeyword | chosenOH[5] & io_in_5_bits_isKeyword
+    | chosenOH[6] & io_in_6_bits_isKeyword | chosenOH[7] & io_in_7_bits_isKeyword;
+  assign io_out_bits_opcode =
+    (chosenOH[0] ? io_in_0_bits_opcode : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_opcode : 4'h0)
+    | (chosenOH[2] ? io_in_2_bits_opcode : 4'h0)
+    | (chosenOH[3] ? io_in_3_bits_opcode : 4'h0)
+    | (chosenOH[4] ? io_in_4_bits_opcode : 4'h0)
+    | (chosenOH[5] ? io_in_5_bits_opcode : 4'h0)
+    | (chosenOH[6] ? io_in_6_bits_opcode : 4'h0)
+    | (chosenOH[7] ? io_in_7_bits_opcode : 4'h0);
+  assign io_out_bits_param =
+    (chosenOH[0] ? io_in_0_bits_param : 3'h0) | (chosenOH[1] ? io_in_1_bits_param : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_param : 3'h0)
+    | (chosenOH[3] ? io_in_3_bits_param : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_param : 3'h0)
+    | (chosenOH[5] ? io_in_5_bits_param : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_param : 3'h0)
+    | (chosenOH[7] ? io_in_7_bits_param : 3'h0);
+  assign io_out_bits_size =
+    (chosenOH[0] ? io_in_0_bits_size : 3'h0) | (chosenOH[1] ? io_in_1_bits_size : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_size : 3'h0) | (chosenOH[3] ? io_in_3_bits_size : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_size : 3'h0) | (chosenOH[5] ? io_in_5_bits_size : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_size : 3'h0) | (chosenOH[7] ? io_in_7_bits_size : 3'h0);
+  assign io_out_bits_sourceId =
+    (chosenOH[0] ? io_in_0_bits_sourceId : 7'h0)
+    | (chosenOH[1] ? io_in_1_bits_sourceId : 7'h0)
+    | (chosenOH[2] ? io_in_2_bits_sourceId : 7'h0)
+    | (chosenOH[3] ? io_in_3_bits_sourceId : 7'h0)
+    | (chosenOH[4] ? io_in_4_bits_sourceId : 7'h0)
+    | (chosenOH[5] ? io_in_5_bits_sourceId : 7'h0)
+    | (chosenOH[6] ? io_in_6_bits_sourceId : 7'h0)
+    | (chosenOH[7] ? io_in_7_bits_sourceId : 7'h0);
+  assign io_out_bits_denied =
+    chosenOH[0] & io_in_0_bits_denied | chosenOH[1] & io_in_1_bits_denied | chosenOH[2]
+    & io_in_2_bits_denied | chosenOH[3] & io_in_3_bits_denied | chosenOH[4]
+    & io_in_4_bits_denied | chosenOH[5] & io_in_5_bits_denied | chosenOH[6]
+    & io_in_6_bits_denied | chosenOH[7] & io_in_7_bits_denied;
+  assign io_out_bits_corrupt =
+    chosenOH[0] & io_in_0_bits_corrupt | chosenOH[1] & io_in_1_bits_corrupt | chosenOH[2]
+    & io_in_2_bits_corrupt | chosenOH[3] & io_in_3_bits_corrupt | chosenOH[4]
+    & io_in_4_bits_corrupt | chosenOH[5] & io_in_5_bits_corrupt | chosenOH[6]
+    & io_in_6_bits_corrupt | chosenOH[7] & io_in_7_bits_corrupt;
+  assign io_out_bits_mshrTask = |chosenOH;
+  assign io_out_bits_aliasTask =
+    chosenOH[0] & io_in_0_bits_aliasTask | chosenOH[1] & io_in_1_bits_aliasTask
+    | chosenOH[2] & io_in_2_bits_aliasTask | chosenOH[3] & io_in_3_bits_aliasTask
+    | chosenOH[4] & io_in_4_bits_aliasTask | chosenOH[5] & io_in_5_bits_aliasTask
+    | chosenOH[6] & io_in_6_bits_aliasTask | chosenOH[7] & io_in_7_bits_aliasTask;
+  assign io_out_bits_useProbeData =
+    chosenOH[0] & io_in_0_bits_useProbeData | chosenOH[1] & io_in_1_bits_useProbeData
+    | chosenOH[2] & io_in_2_bits_useProbeData | chosenOH[3] & io_in_3_bits_useProbeData
+    | chosenOH[4] & io_in_4_bits_useProbeData | chosenOH[5] & io_in_5_bits_useProbeData
+    | chosenOH[6] & io_in_6_bits_useProbeData | chosenOH[7] & io_in_7_bits_useProbeData;
+  assign io_out_bits_mshrRetry =
+    chosenOH[0] & io_in_0_bits_mshrRetry | chosenOH[1] & io_in_1_bits_mshrRetry
+    | chosenOH[2] & io_in_2_bits_mshrRetry | chosenOH[3] & io_in_3_bits_mshrRetry
+    | chosenOH[4] & io_in_4_bits_mshrRetry | chosenOH[5] & io_in_5_bits_mshrRetry
+    | chosenOH[6] & io_in_6_bits_mshrRetry | chosenOH[7] & io_in_7_bits_mshrRetry;
+  assign io_out_bits_readProbeDataDown =
+    chosenOH[0] & io_in_0_bits_readProbeDataDown | chosenOH[1]
+    & io_in_1_bits_readProbeDataDown | chosenOH[2] & io_in_2_bits_readProbeDataDown
+    | chosenOH[3] & io_in_3_bits_readProbeDataDown | chosenOH[4]
+    & io_in_4_bits_readProbeDataDown | chosenOH[5] & io_in_5_bits_readProbeDataDown
+    | chosenOH[6] & io_in_6_bits_readProbeDataDown | chosenOH[7]
+    & io_in_7_bits_readProbeDataDown;
+  assign io_out_bits_fromL2pft =
+    chosenOH[0] & io_in_0_bits_fromL2pft | chosenOH[1] & io_in_1_bits_fromL2pft
+    | chosenOH[2] & io_in_2_bits_fromL2pft | chosenOH[3] & io_in_3_bits_fromL2pft
+    | chosenOH[4] & io_in_4_bits_fromL2pft | chosenOH[5] & io_in_5_bits_fromL2pft
+    | chosenOH[6] & io_in_6_bits_fromL2pft | chosenOH[7] & io_in_7_bits_fromL2pft;
+  assign io_out_bits_dirty =
+    chosenOH[0] & io_in_0_bits_dirty | chosenOH[1] & io_in_1_bits_dirty | chosenOH[2]
+    & io_in_2_bits_dirty | chosenOH[3] & io_in_3_bits_dirty | chosenOH[4]
+    & io_in_4_bits_dirty | chosenOH[5] & io_in_5_bits_dirty | chosenOH[6]
+    & io_in_6_bits_dirty | chosenOH[7] & io_in_7_bits_dirty;
+  assign io_out_bits_way =
+    (chosenOH[0] ? io_in_0_bits_way : 3'h0) | (chosenOH[1] ? io_in_1_bits_way : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_way : 3'h0) | (chosenOH[3] ? io_in_3_bits_way : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_way : 3'h0) | (chosenOH[5] ? io_in_5_bits_way : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_way : 3'h0) | (chosenOH[7] ? io_in_7_bits_way : 3'h0);
+  assign io_out_bits_meta_dirty =
+    chosenOH[0] & io_in_0_bits_meta_dirty | chosenOH[1] & io_in_1_bits_meta_dirty
+    | chosenOH[2] & io_in_2_bits_meta_dirty | chosenOH[3] & io_in_3_bits_meta_dirty
+    | chosenOH[4] & io_in_4_bits_meta_dirty | chosenOH[5] & io_in_5_bits_meta_dirty
+    | chosenOH[6] & io_in_6_bits_meta_dirty | chosenOH[7] & io_in_7_bits_meta_dirty;
+  assign io_out_bits_meta_state =
+    (chosenOH[0] ? io_in_0_bits_meta_state : 2'h0)
+    | (chosenOH[1] ? io_in_1_bits_meta_state : 2'h0)
+    | (chosenOH[2] ? io_in_2_bits_meta_state : 2'h0)
+    | (chosenOH[3] ? io_in_3_bits_meta_state : 2'h0)
+    | (chosenOH[4] ? io_in_4_bits_meta_state : 2'h0)
+    | (chosenOH[5] ? io_in_5_bits_meta_state : 2'h0)
+    | (chosenOH[6] ? io_in_6_bits_meta_state : 2'h0)
+    | (chosenOH[7] ? io_in_7_bits_meta_state : 2'h0);
+  assign io_out_bits_meta_clients =
+    chosenOH[0] & io_in_0_bits_meta_clients | chosenOH[1] & io_in_1_bits_meta_clients
+    | chosenOH[2] & io_in_2_bits_meta_clients | chosenOH[3] & io_in_3_bits_meta_clients
+    | chosenOH[4] & io_in_4_bits_meta_clients | chosenOH[5] & io_in_5_bits_meta_clients
+    | chosenOH[6] & io_in_6_bits_meta_clients | chosenOH[7] & io_in_7_bits_meta_clients;
+  assign io_out_bits_meta_alias =
+    chosenOH[0] & io_in_0_bits_meta_alias | chosenOH[1] & io_in_1_bits_meta_alias
+    | chosenOH[2] & io_in_2_bits_meta_alias | chosenOH[3] & io_in_3_bits_meta_alias
+    | chosenOH[4] & io_in_4_bits_meta_alias | chosenOH[5] & io_in_5_bits_meta_alias
+    | chosenOH[6] & io_in_6_bits_meta_alias | chosenOH[7] & io_in_7_bits_meta_alias;
+  assign io_out_bits_meta_prefetch =
+    chosenOH[0] & io_in_0_bits_meta_prefetch | chosenOH[1] & io_in_1_bits_meta_prefetch
+    | chosenOH[2] & io_in_2_bits_meta_prefetch | chosenOH[3] & io_in_3_bits_meta_prefetch
+    | chosenOH[4] & io_in_4_bits_meta_prefetch | chosenOH[5] & io_in_5_bits_meta_prefetch
+    | chosenOH[6] & io_in_6_bits_meta_prefetch | chosenOH[7] & io_in_7_bits_meta_prefetch;
+  assign io_out_bits_meta_prefetchSrc =
+    (chosenOH[0] ? io_in_0_bits_meta_prefetchSrc : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_meta_prefetchSrc : 4'h0)
+    | (chosenOH[2] ? io_in_2_bits_meta_prefetchSrc : 4'h0)
+    | (chosenOH[3] ? io_in_3_bits_meta_prefetchSrc : 4'h0)
+    | (chosenOH[4] ? io_in_4_bits_meta_prefetchSrc : 4'h0)
+    | (chosenOH[5] ? io_in_5_bits_meta_prefetchSrc : 4'h0)
+    | (chosenOH[6] ? io_in_6_bits_meta_prefetchSrc : 4'h0)
+    | (chosenOH[7] ? io_in_7_bits_meta_prefetchSrc : 4'h0);
+  assign io_out_bits_meta_accessed =
+    chosenOH[0] & io_in_0_bits_meta_accessed | chosenOH[1] & io_in_1_bits_meta_accessed
+    | chosenOH[2] & io_in_2_bits_meta_accessed | chosenOH[3] & io_in_3_bits_meta_accessed
+    | chosenOH[4] & io_in_4_bits_meta_accessed | chosenOH[5] & io_in_5_bits_meta_accessed
+    | chosenOH[6] & io_in_6_bits_meta_accessed | chosenOH[7] & io_in_7_bits_meta_accessed;
+  assign io_out_bits_meta_tagErr =
+    chosenOH[0] & io_in_0_bits_meta_tagErr | chosenOH[1] & io_in_1_bits_meta_tagErr
+    | chosenOH[2] & io_in_2_bits_meta_tagErr | chosenOH[3] & io_in_3_bits_meta_tagErr
+    | chosenOH[4] & io_in_4_bits_meta_tagErr | chosenOH[5] & io_in_5_bits_meta_tagErr
+    | chosenOH[6] & io_in_6_bits_meta_tagErr | chosenOH[7] & io_in_7_bits_meta_tagErr;
+  assign io_out_bits_meta_dataErr =
+    chosenOH[0] & io_in_0_bits_meta_dataErr | chosenOH[1] & io_in_1_bits_meta_dataErr
+    | chosenOH[2] & io_in_2_bits_meta_dataErr | chosenOH[3] & io_in_3_bits_meta_dataErr
+    | chosenOH[4] & io_in_4_bits_meta_dataErr | chosenOH[5] & io_in_5_bits_meta_dataErr
+    | chosenOH[6] & io_in_6_bits_meta_dataErr | chosenOH[7] & io_in_7_bits_meta_dataErr;
+  assign io_out_bits_metaWen =
+    chosenOH[0] & io_in_0_bits_metaWen | chosenOH[1] & io_in_1_bits_metaWen | chosenOH[2]
+    & io_in_2_bits_metaWen | chosenOH[3] & io_in_3_bits_metaWen | chosenOH[4]
+    & io_in_4_bits_metaWen | chosenOH[5] & io_in_5_bits_metaWen | chosenOH[6]
+    & io_in_6_bits_metaWen | chosenOH[7] & io_in_7_bits_metaWen;
+  assign io_out_bits_tagWen =
+    chosenOH[0] & io_in_0_bits_tagWen | chosenOH[1] & io_in_1_bits_tagWen | chosenOH[2]
+    & io_in_2_bits_tagWen | chosenOH[3] & io_in_3_bits_tagWen | chosenOH[4]
+    & io_in_4_bits_tagWen | chosenOH[5] & io_in_5_bits_tagWen | chosenOH[6]
+    & io_in_6_bits_tagWen | chosenOH[7] & io_in_7_bits_tagWen;
+  assign io_out_bits_dsWen =
+    chosenOH[0] & io_in_0_bits_dsWen | chosenOH[1] & io_in_1_bits_dsWen | chosenOH[2]
+    & io_in_2_bits_dsWen | chosenOH[3] & io_in_3_bits_dsWen | chosenOH[4]
+    & io_in_4_bits_dsWen | chosenOH[5] & io_in_5_bits_dsWen | chosenOH[6]
+    & io_in_6_bits_dsWen | chosenOH[7] & io_in_7_bits_dsWen;
+  assign io_out_bits_replTask =
+    chosenOH[0] & io_in_0_bits_replTask | chosenOH[1] & io_in_1_bits_replTask
+    | chosenOH[2] & io_in_2_bits_replTask | chosenOH[3] & io_in_3_bits_replTask
+    | chosenOH[4] & io_in_4_bits_replTask | chosenOH[5] & io_in_5_bits_replTask
+    | chosenOH[6] & io_in_6_bits_replTask | chosenOH[7] & io_in_7_bits_replTask;
+  assign io_out_bits_cmoTask =
+    chosenOH[0] & io_in_0_bits_cmoTask | chosenOH[1] & io_in_1_bits_cmoTask | chosenOH[2]
+    & io_in_2_bits_cmoTask | chosenOH[3] & io_in_3_bits_cmoTask | chosenOH[4]
+    & io_in_4_bits_cmoTask | chosenOH[5] & io_in_5_bits_cmoTask | chosenOH[6]
+    & io_in_6_bits_cmoTask | chosenOH[7] & io_in_7_bits_cmoTask;
+  assign io_out_bits_reqSource =
+    (chosenOH[0] ? io_in_0_bits_reqSource : 5'h0)
+    | (chosenOH[1] ? io_in_1_bits_reqSource : 5'h0)
+    | (chosenOH[2] ? io_in_2_bits_reqSource : 5'h0)
+    | (chosenOH[3] ? io_in_3_bits_reqSource : 5'h0)
+    | (chosenOH[4] ? io_in_4_bits_reqSource : 5'h0)
+    | (chosenOH[5] ? io_in_5_bits_reqSource : 5'h0)
+    | (chosenOH[6] ? io_in_6_bits_reqSource : 5'h0)
+    | (chosenOH[7] ? io_in_7_bits_reqSource : 5'h0);
+  assign io_out_bits_mergeA =
+    chosenOH[0] & io_in_0_bits_mergeA | chosenOH[1] & io_in_1_bits_mergeA | chosenOH[2]
+    & io_in_2_bits_mergeA | chosenOH[3] & io_in_3_bits_mergeA | chosenOH[4]
+    & io_in_4_bits_mergeA | chosenOH[5] & io_in_5_bits_mergeA | chosenOH[6]
+    & io_in_6_bits_mergeA | chosenOH[7] & io_in_7_bits_mergeA;
+  assign io_out_bits_aMergeTask_off =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_off : 6'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_off : 6'h0)
+    | (chosenOH[2] ? io_in_2_bits_aMergeTask_off : 6'h0)
+    | (chosenOH[3] ? io_in_3_bits_aMergeTask_off : 6'h0)
+    | (chosenOH[4] ? io_in_4_bits_aMergeTask_off : 6'h0)
+    | (chosenOH[5] ? io_in_5_bits_aMergeTask_off : 6'h0)
+    | (chosenOH[6] ? io_in_6_bits_aMergeTask_off : 6'h0)
+    | (chosenOH[7] ? io_in_7_bits_aMergeTask_off : 6'h0);
+  assign io_out_bits_aMergeTask_alias =
+    chosenOH[0] & io_in_0_bits_aMergeTask_alias | chosenOH[1]
+    & io_in_1_bits_aMergeTask_alias | chosenOH[2] & io_in_2_bits_aMergeTask_alias
+    | chosenOH[3] & io_in_3_bits_aMergeTask_alias | chosenOH[4]
+    & io_in_4_bits_aMergeTask_alias | chosenOH[5] & io_in_5_bits_aMergeTask_alias
+    | chosenOH[6] & io_in_6_bits_aMergeTask_alias | chosenOH[7]
+    & io_in_7_bits_aMergeTask_alias;
+  assign io_out_bits_aMergeTask_vaddr =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_vaddr : 44'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_vaddr : 44'h0)
+    | (chosenOH[2] ? io_in_2_bits_aMergeTask_vaddr : 44'h0)
+    | (chosenOH[3] ? io_in_3_bits_aMergeTask_vaddr : 44'h0)
+    | (chosenOH[4] ? io_in_4_bits_aMergeTask_vaddr : 44'h0)
+    | (chosenOH[5] ? io_in_5_bits_aMergeTask_vaddr : 44'h0)
+    | (chosenOH[6] ? io_in_6_bits_aMergeTask_vaddr : 44'h0)
+    | (chosenOH[7] ? io_in_7_bits_aMergeTask_vaddr : 44'h0);
+  assign io_out_bits_aMergeTask_isKeyword =
+    chosenOH[0] & io_in_0_bits_aMergeTask_isKeyword | chosenOH[1]
+    & io_in_1_bits_aMergeTask_isKeyword | chosenOH[2] & io_in_2_bits_aMergeTask_isKeyword
+    | chosenOH[3] & io_in_3_bits_aMergeTask_isKeyword | chosenOH[4]
+    & io_in_4_bits_aMergeTask_isKeyword | chosenOH[5] & io_in_5_bits_aMergeTask_isKeyword
+    | chosenOH[6] & io_in_6_bits_aMergeTask_isKeyword | chosenOH[7]
+    & io_in_7_bits_aMergeTask_isKeyword;
+  assign io_out_bits_aMergeTask_opcode =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_opcode : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_opcode : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_aMergeTask_opcode : 3'h0)
+    | (chosenOH[3] ? io_in_3_bits_aMergeTask_opcode : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_aMergeTask_opcode : 3'h0)
+    | (chosenOH[5] ? io_in_5_bits_aMergeTask_opcode : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_aMergeTask_opcode : 3'h0)
+    | (chosenOH[7] ? io_in_7_bits_aMergeTask_opcode : 3'h0);
+  assign io_out_bits_aMergeTask_param =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_param : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_param : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_aMergeTask_param : 3'h0)
+    | (chosenOH[3] ? io_in_3_bits_aMergeTask_param : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_aMergeTask_param : 3'h0)
+    | (chosenOH[5] ? io_in_5_bits_aMergeTask_param : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_aMergeTask_param : 3'h0)
+    | (chosenOH[7] ? io_in_7_bits_aMergeTask_param : 3'h0);
+  assign io_out_bits_aMergeTask_sourceId =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_sourceId : 7'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_sourceId : 7'h0)
+    | (chosenOH[2] ? io_in_2_bits_aMergeTask_sourceId : 7'h0)
+    | (chosenOH[3] ? io_in_3_bits_aMergeTask_sourceId : 7'h0)
+    | (chosenOH[4] ? io_in_4_bits_aMergeTask_sourceId : 7'h0)
+    | (chosenOH[5] ? io_in_5_bits_aMergeTask_sourceId : 7'h0)
+    | (chosenOH[6] ? io_in_6_bits_aMergeTask_sourceId : 7'h0)
+    | (chosenOH[7] ? io_in_7_bits_aMergeTask_sourceId : 7'h0);
+  assign io_out_bits_aMergeTask_meta_dirty =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_dirty | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_dirty | chosenOH[2]
+    & io_in_2_bits_aMergeTask_meta_dirty | chosenOH[3]
+    & io_in_3_bits_aMergeTask_meta_dirty | chosenOH[4]
+    & io_in_4_bits_aMergeTask_meta_dirty | chosenOH[5]
+    & io_in_5_bits_aMergeTask_meta_dirty | chosenOH[6]
+    & io_in_6_bits_aMergeTask_meta_dirty | chosenOH[7]
+    & io_in_7_bits_aMergeTask_meta_dirty;
+  assign io_out_bits_aMergeTask_meta_state =
+    (chosenOH[0] ? io_in_0_bits_aMergeTask_meta_state : 2'h0)
+    | (chosenOH[1] ? io_in_1_bits_aMergeTask_meta_state : 2'h0)
+    | (chosenOH[2] ? io_in_2_bits_aMergeTask_meta_state : 2'h0)
+    | (chosenOH[3] ? io_in_3_bits_aMergeTask_meta_state : 2'h0)
+    | (chosenOH[4] ? io_in_4_bits_aMergeTask_meta_state : 2'h0)
+    | (chosenOH[5] ? io_in_5_bits_aMergeTask_meta_state : 2'h0)
+    | (chosenOH[6] ? io_in_6_bits_aMergeTask_meta_state : 2'h0)
+    | (chosenOH[7] ? io_in_7_bits_aMergeTask_meta_state : 2'h0);
+  assign io_out_bits_aMergeTask_meta_clients =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_clients | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_clients | chosenOH[2]
+    & io_in_2_bits_aMergeTask_meta_clients | chosenOH[3]
+    & io_in_3_bits_aMergeTask_meta_clients | chosenOH[4]
+    & io_in_4_bits_aMergeTask_meta_clients | chosenOH[5]
+    & io_in_5_bits_aMergeTask_meta_clients | chosenOH[6]
+    & io_in_6_bits_aMergeTask_meta_clients | chosenOH[7]
+    & io_in_7_bits_aMergeTask_meta_clients;
+  assign io_out_bits_aMergeTask_meta_alias =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_alias | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_alias | chosenOH[2]
+    & io_in_2_bits_aMergeTask_meta_alias | chosenOH[3]
+    & io_in_3_bits_aMergeTask_meta_alias | chosenOH[4]
+    & io_in_4_bits_aMergeTask_meta_alias | chosenOH[5]
+    & io_in_5_bits_aMergeTask_meta_alias | chosenOH[6]
+    & io_in_6_bits_aMergeTask_meta_alias | chosenOH[7]
+    & io_in_7_bits_aMergeTask_meta_alias;
+  assign io_out_bits_aMergeTask_meta_accessed =
+    chosenOH[0] & io_in_0_bits_aMergeTask_meta_accessed | chosenOH[1]
+    & io_in_1_bits_aMergeTask_meta_accessed | chosenOH[2]
+    & io_in_2_bits_aMergeTask_meta_accessed | chosenOH[3]
+    & io_in_3_bits_aMergeTask_meta_accessed | chosenOH[4]
+    & io_in_4_bits_aMergeTask_meta_accessed | chosenOH[5]
+    & io_in_5_bits_aMergeTask_meta_accessed | chosenOH[6]
+    & io_in_6_bits_aMergeTask_meta_accessed | chosenOH[7]
+    & io_in_7_bits_aMergeTask_meta_accessed;
+  assign io_out_bits_snpHitRelease =
+    chosenOH[0] & io_in_0_bits_snpHitRelease | chosenOH[1] & io_in_1_bits_snpHitRelease
+    | chosenOH[2] & io_in_2_bits_snpHitRelease | chosenOH[3] & io_in_3_bits_snpHitRelease
+    | chosenOH[4] & io_in_4_bits_snpHitRelease | chosenOH[5] & io_in_5_bits_snpHitRelease
+    | chosenOH[6] & io_in_6_bits_snpHitRelease | chosenOH[7] & io_in_7_bits_snpHitRelease;
+  assign io_out_bits_snpHitReleaseToInval =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseToInval | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseToInval | chosenOH[2] & io_in_2_bits_snpHitReleaseToInval
+    | chosenOH[3] & io_in_3_bits_snpHitReleaseToInval | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseToInval | chosenOH[5] & io_in_5_bits_snpHitReleaseToInval
+    | chosenOH[6] & io_in_6_bits_snpHitReleaseToInval | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseToInval;
+  assign io_out_bits_snpHitReleaseToClean =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseToClean | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseToClean | chosenOH[2] & io_in_2_bits_snpHitReleaseToClean
+    | chosenOH[3] & io_in_3_bits_snpHitReleaseToClean | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseToClean | chosenOH[5] & io_in_5_bits_snpHitReleaseToClean
+    | chosenOH[6] & io_in_6_bits_snpHitReleaseToClean | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseToClean;
+  assign io_out_bits_snpHitReleaseWithData =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseWithData | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseWithData | chosenOH[2]
+    & io_in_2_bits_snpHitReleaseWithData | chosenOH[3]
+    & io_in_3_bits_snpHitReleaseWithData | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseWithData | chosenOH[5]
+    & io_in_5_bits_snpHitReleaseWithData | chosenOH[6]
+    & io_in_6_bits_snpHitReleaseWithData | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseWithData;
+  assign io_out_bits_snpHitReleaseIdx =
+    (chosenOH[0] ? io_in_0_bits_snpHitReleaseIdx : 8'h0)
+    | (chosenOH[1] ? io_in_1_bits_snpHitReleaseIdx : 8'h0)
+    | (chosenOH[2] ? io_in_2_bits_snpHitReleaseIdx : 8'h0)
+    | (chosenOH[3] ? io_in_3_bits_snpHitReleaseIdx : 8'h0)
+    | (chosenOH[4] ? io_in_4_bits_snpHitReleaseIdx : 8'h0)
+    | (chosenOH[5] ? io_in_5_bits_snpHitReleaseIdx : 8'h0)
+    | (chosenOH[6] ? io_in_6_bits_snpHitReleaseIdx : 8'h0)
+    | (chosenOH[7] ? io_in_7_bits_snpHitReleaseIdx : 8'h0);
+  assign io_out_bits_snpHitReleaseMeta_dirty =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_dirty | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_dirty | chosenOH[2]
+    & io_in_2_bits_snpHitReleaseMeta_dirty | chosenOH[3]
+    & io_in_3_bits_snpHitReleaseMeta_dirty | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseMeta_dirty | chosenOH[5]
+    & io_in_5_bits_snpHitReleaseMeta_dirty | chosenOH[6]
+    & io_in_6_bits_snpHitReleaseMeta_dirty | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseMeta_dirty;
+  assign io_out_bits_snpHitReleaseMeta_state =
+    (chosenOH[0] ? io_in_0_bits_snpHitReleaseMeta_state : 2'h0)
+    | (chosenOH[1] ? io_in_1_bits_snpHitReleaseMeta_state : 2'h0)
+    | (chosenOH[2] ? io_in_2_bits_snpHitReleaseMeta_state : 2'h0)
+    | (chosenOH[3] ? io_in_3_bits_snpHitReleaseMeta_state : 2'h0)
+    | (chosenOH[4] ? io_in_4_bits_snpHitReleaseMeta_state : 2'h0)
+    | (chosenOH[5] ? io_in_5_bits_snpHitReleaseMeta_state : 2'h0)
+    | (chosenOH[6] ? io_in_6_bits_snpHitReleaseMeta_state : 2'h0)
+    | (chosenOH[7] ? io_in_7_bits_snpHitReleaseMeta_state : 2'h0);
+  assign io_out_bits_snpHitReleaseMeta_clients =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_clients | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_clients | chosenOH[2]
+    & io_in_2_bits_snpHitReleaseMeta_clients | chosenOH[3]
+    & io_in_3_bits_snpHitReleaseMeta_clients | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseMeta_clients | chosenOH[5]
+    & io_in_5_bits_snpHitReleaseMeta_clients | chosenOH[6]
+    & io_in_6_bits_snpHitReleaseMeta_clients | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseMeta_clients;
+  assign io_out_bits_snpHitReleaseMeta_alias =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_alias | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_alias | chosenOH[2]
+    & io_in_2_bits_snpHitReleaseMeta_alias | chosenOH[3]
+    & io_in_3_bits_snpHitReleaseMeta_alias | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseMeta_alias | chosenOH[5]
+    & io_in_5_bits_snpHitReleaseMeta_alias | chosenOH[6]
+    & io_in_6_bits_snpHitReleaseMeta_alias | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseMeta_alias;
+  assign io_out_bits_snpHitReleaseMeta_prefetch =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_prefetch | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_prefetch | chosenOH[2]
+    & io_in_2_bits_snpHitReleaseMeta_prefetch | chosenOH[3]
+    & io_in_3_bits_snpHitReleaseMeta_prefetch | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseMeta_prefetch | chosenOH[5]
+    & io_in_5_bits_snpHitReleaseMeta_prefetch | chosenOH[6]
+    & io_in_6_bits_snpHitReleaseMeta_prefetch | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseMeta_prefetch;
+  assign io_out_bits_snpHitReleaseMeta_prefetchSrc =
+    (chosenOH[0] ? io_in_0_bits_snpHitReleaseMeta_prefetchSrc : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_snpHitReleaseMeta_prefetchSrc : 4'h0)
+    | (chosenOH[2] ? io_in_2_bits_snpHitReleaseMeta_prefetchSrc : 4'h0)
+    | (chosenOH[3] ? io_in_3_bits_snpHitReleaseMeta_prefetchSrc : 4'h0)
+    | (chosenOH[4] ? io_in_4_bits_snpHitReleaseMeta_prefetchSrc : 4'h0)
+    | (chosenOH[5] ? io_in_5_bits_snpHitReleaseMeta_prefetchSrc : 4'h0)
+    | (chosenOH[6] ? io_in_6_bits_snpHitReleaseMeta_prefetchSrc : 4'h0)
+    | (chosenOH[7] ? io_in_7_bits_snpHitReleaseMeta_prefetchSrc : 4'h0);
+  assign io_out_bits_snpHitReleaseMeta_accessed =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_accessed | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_accessed | chosenOH[2]
+    & io_in_2_bits_snpHitReleaseMeta_accessed | chosenOH[3]
+    & io_in_3_bits_snpHitReleaseMeta_accessed | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseMeta_accessed | chosenOH[5]
+    & io_in_5_bits_snpHitReleaseMeta_accessed | chosenOH[6]
+    & io_in_6_bits_snpHitReleaseMeta_accessed | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseMeta_accessed;
+  assign io_out_bits_snpHitReleaseMeta_tagErr =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_tagErr | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_tagErr | chosenOH[2]
+    & io_in_2_bits_snpHitReleaseMeta_tagErr | chosenOH[3]
+    & io_in_3_bits_snpHitReleaseMeta_tagErr | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseMeta_tagErr | chosenOH[5]
+    & io_in_5_bits_snpHitReleaseMeta_tagErr | chosenOH[6]
+    & io_in_6_bits_snpHitReleaseMeta_tagErr | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseMeta_tagErr;
+  assign io_out_bits_snpHitReleaseMeta_dataErr =
+    chosenOH[0] & io_in_0_bits_snpHitReleaseMeta_dataErr | chosenOH[1]
+    & io_in_1_bits_snpHitReleaseMeta_dataErr | chosenOH[2]
+    & io_in_2_bits_snpHitReleaseMeta_dataErr | chosenOH[3]
+    & io_in_3_bits_snpHitReleaseMeta_dataErr | chosenOH[4]
+    & io_in_4_bits_snpHitReleaseMeta_dataErr | chosenOH[5]
+    & io_in_5_bits_snpHitReleaseMeta_dataErr | chosenOH[6]
+    & io_in_6_bits_snpHitReleaseMeta_dataErr | chosenOH[7]
+    & io_in_7_bits_snpHitReleaseMeta_dataErr;
+  assign io_out_bits_tgtID =
+    (chosenOH[0] ? io_in_0_bits_tgtID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_tgtID : 11'h0)
+    | (chosenOH[2] ? io_in_2_bits_tgtID : 11'h0)
+    | (chosenOH[3] ? io_in_3_bits_tgtID : 11'h0)
+    | (chosenOH[4] ? io_in_4_bits_tgtID : 11'h0)
+    | (chosenOH[5] ? io_in_5_bits_tgtID : 11'h0)
+    | (chosenOH[6] ? io_in_6_bits_tgtID : 11'h0)
+    | (chosenOH[7] ? io_in_7_bits_tgtID : 11'h0);
+  assign io_out_bits_txnID =
+    (chosenOH[0] ? io_in_0_bits_txnID : 12'h0)
+    | (chosenOH[1] ? io_in_1_bits_txnID : 12'h0)
+    | (chosenOH[2] ? io_in_2_bits_txnID : 12'h0)
+    | (chosenOH[3] ? io_in_3_bits_txnID : 12'h0)
+    | (chosenOH[4] ? io_in_4_bits_txnID : 12'h0)
+    | (chosenOH[5] ? io_in_5_bits_txnID : 12'h0)
+    | (chosenOH[6] ? io_in_6_bits_txnID : 12'h0)
+    | (chosenOH[7] ? io_in_7_bits_txnID : 12'h0);
+  assign io_out_bits_homeNID =
+    (chosenOH[0] ? io_in_0_bits_homeNID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_homeNID : 11'h0)
+    | (chosenOH[2] ? io_in_2_bits_homeNID : 11'h0)
+    | (chosenOH[3] ? io_in_3_bits_homeNID : 11'h0)
+    | (chosenOH[4] ? io_in_4_bits_homeNID : 11'h0)
+    | (chosenOH[5] ? io_in_5_bits_homeNID : 11'h0)
+    | (chosenOH[6] ? io_in_6_bits_homeNID : 11'h0)
+    | (chosenOH[7] ? io_in_7_bits_homeNID : 11'h0);
+  assign io_out_bits_dbID =
+    (chosenOH[0] ? io_in_0_bits_dbID : 12'h0) | (chosenOH[1] ? io_in_1_bits_dbID : 12'h0)
+    | (chosenOH[2] ? io_in_2_bits_dbID : 12'h0)
+    | (chosenOH[3] ? io_in_3_bits_dbID : 12'h0)
+    | (chosenOH[4] ? io_in_4_bits_dbID : 12'h0)
+    | (chosenOH[5] ? io_in_5_bits_dbID : 12'h0)
+    | (chosenOH[6] ? io_in_6_bits_dbID : 12'h0)
+    | (chosenOH[7] ? io_in_7_bits_dbID : 12'h0);
+  assign io_out_bits_chiOpcode =
+    (chosenOH[0] ? io_in_0_bits_chiOpcode : 7'h0)
+    | (chosenOH[1] ? io_in_1_bits_chiOpcode : 7'h0)
+    | (chosenOH[2] ? io_in_2_bits_chiOpcode : 7'h0)
+    | (chosenOH[3] ? io_in_3_bits_chiOpcode : 7'h0)
+    | (chosenOH[4] ? io_in_4_bits_chiOpcode : 7'h0)
+    | (chosenOH[5] ? io_in_5_bits_chiOpcode : 7'h0)
+    | (chosenOH[6] ? io_in_6_bits_chiOpcode : 7'h0)
+    | (chosenOH[7] ? io_in_7_bits_chiOpcode : 7'h0);
+  assign io_out_bits_resp =
+    (chosenOH[0] ? io_in_0_bits_resp : 3'h0) | (chosenOH[1] ? io_in_1_bits_resp : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_resp : 3'h0) | (chosenOH[3] ? io_in_3_bits_resp : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_resp : 3'h0) | (chosenOH[5] ? io_in_5_bits_resp : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_resp : 3'h0) | (chosenOH[7] ? io_in_7_bits_resp : 3'h0);
+  assign io_out_bits_fwdState =
+    (chosenOH[0] ? io_in_0_bits_fwdState : 3'h0)
+    | (chosenOH[1] ? io_in_1_bits_fwdState : 3'h0)
+    | (chosenOH[2] ? io_in_2_bits_fwdState : 3'h0)
+    | (chosenOH[3] ? io_in_3_bits_fwdState : 3'h0)
+    | (chosenOH[4] ? io_in_4_bits_fwdState : 3'h0)
+    | (chosenOH[5] ? io_in_5_bits_fwdState : 3'h0)
+    | (chosenOH[6] ? io_in_6_bits_fwdState : 3'h0)
+    | (chosenOH[7] ? io_in_7_bits_fwdState : 3'h0);
+  assign io_out_bits_retToSrc =
+    chosenOH[0] & io_in_0_bits_retToSrc | chosenOH[1] & io_in_1_bits_retToSrc
+    | chosenOH[2] & io_in_2_bits_retToSrc | chosenOH[3] & io_in_3_bits_retToSrc
+    | chosenOH[4] & io_in_4_bits_retToSrc | chosenOH[5] & io_in_5_bits_retToSrc
+    | chosenOH[6] & io_in_6_bits_retToSrc | chosenOH[7] & io_in_7_bits_retToSrc;
+  assign io_out_bits_likelyshared =
+    chosenOH[0] & io_in_0_bits_likelyshared | chosenOH[1] & io_in_1_bits_likelyshared
+    | chosenOH[2] & io_in_2_bits_likelyshared | chosenOH[3] & io_in_3_bits_likelyshared
+    | chosenOH[4] & io_in_4_bits_likelyshared | chosenOH[5] & io_in_5_bits_likelyshared
+    | chosenOH[6] & io_in_6_bits_likelyshared | chosenOH[7] & io_in_7_bits_likelyshared;
+  assign io_out_bits_expCompAck =
+    chosenOH[0] & io_in_0_bits_expCompAck | chosenOH[1] & io_in_1_bits_expCompAck
+    | chosenOH[2] & io_in_2_bits_expCompAck | chosenOH[3] & io_in_3_bits_expCompAck
+    | chosenOH[4] & io_in_4_bits_expCompAck | chosenOH[5] & io_in_5_bits_expCompAck
+    | chosenOH[6] & io_in_6_bits_expCompAck | chosenOH[7] & io_in_7_bits_expCompAck;
+  assign io_out_bits_allowRetry =
+    chosenOH[0] & io_in_0_bits_allowRetry | chosenOH[1] & io_in_1_bits_allowRetry
+    | chosenOH[2] & io_in_2_bits_allowRetry | chosenOH[3] & io_in_3_bits_allowRetry
+    | chosenOH[4] & io_in_4_bits_allowRetry | chosenOH[5] & io_in_5_bits_allowRetry
+    | chosenOH[6] & io_in_6_bits_allowRetry | chosenOH[7] & io_in_7_bits_allowRetry;
+  assign io_out_bits_memAttr_allocate =
+    chosenOH[0] & io_in_0_bits_memAttr_allocate | chosenOH[1]
+    & io_in_1_bits_memAttr_allocate | chosenOH[2] & io_in_2_bits_memAttr_allocate
+    | chosenOH[3] & io_in_3_bits_memAttr_allocate | chosenOH[4]
+    & io_in_4_bits_memAttr_allocate | chosenOH[5] & io_in_5_bits_memAttr_allocate
+    | chosenOH[6] & io_in_6_bits_memAttr_allocate | chosenOH[7]
+    & io_in_7_bits_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable =
+    chosenOH[0] & io_in_0_bits_memAttr_cacheable | chosenOH[1]
+    & io_in_1_bits_memAttr_cacheable | chosenOH[2] & io_in_2_bits_memAttr_cacheable
+    | chosenOH[3] & io_in_3_bits_memAttr_cacheable | chosenOH[4]
+    & io_in_4_bits_memAttr_cacheable | chosenOH[5] & io_in_5_bits_memAttr_cacheable
+    | chosenOH[6] & io_in_6_bits_memAttr_cacheable | chosenOH[7]
+    & io_in_7_bits_memAttr_cacheable;
+  assign io_out_bits_memAttr_ewa =
+    chosenOH[0] & io_in_0_bits_memAttr_ewa | chosenOH[1] & io_in_1_bits_memAttr_ewa
+    | chosenOH[2] & io_in_2_bits_memAttr_ewa | chosenOH[3] & io_in_3_bits_memAttr_ewa
+    | chosenOH[4] & io_in_4_bits_memAttr_ewa | chosenOH[5] & io_in_5_bits_memAttr_ewa
+    | chosenOH[6] & io_in_6_bits_memAttr_ewa | chosenOH[7] & io_in_7_bits_memAttr_ewa;
+  assign io_out_bits_traceTag =
+    chosenOH[0] & io_in_0_bits_traceTag | chosenOH[1] & io_in_1_bits_traceTag
+    | chosenOH[2] & io_in_2_bits_traceTag | chosenOH[3] & io_in_3_bits_traceTag
+    | chosenOH[4] & io_in_4_bits_traceTag | chosenOH[5] & io_in_5_bits_traceTag
+    | chosenOH[6] & io_in_6_bits_traceTag | chosenOH[7] & io_in_7_bits_traceTag;
+  assign io_chosenOH = chosenOH;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_24.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_24.sv
new file mode 100644
index 0000000000..af996c06a5
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_24.sv
@@ -0,0 +1,98 @@
+// Generated by CIRCT firtool-1.135.0
+module FastArbiter_24(
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [3:0]  io_in_0_bits_qos,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [10:0] io_in_0_bits_srcID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [10:0] io_in_0_bits_returnNID,
+  input         io_in_0_bits_stashNIDValid,
+  input  [11:0] io_in_0_bits_returnTxnID,
+  input  [6:0]  io_in_0_bits_opcode,
+  input  [2:0]  io_in_0_bits_size,
+  input  [47:0] io_in_0_bits_addr,
+  input         io_in_0_bits_ns,
+  input         io_in_0_bits_likelyshared,
+  input         io_in_0_bits_allowRetry,
+  input  [1:0]  io_in_0_bits_order,
+  input  [3:0]  io_in_0_bits_pCrdType,
+  input         io_in_0_bits_memAttr_allocate,
+  input         io_in_0_bits_memAttr_cacheable,
+  input         io_in_0_bits_memAttr_device,
+  input         io_in_0_bits_memAttr_ewa,
+  input         io_in_0_bits_snpAttr,
+  input  [7:0]  io_in_0_bits_lpIDWithPadding,
+  input         io_in_0_bits_snoopMe,
+  input         io_in_0_bits_expCompAck,
+  input  [1:0]  io_in_0_bits_tagOp,
+  input         io_in_0_bits_traceTag,
+  input         io_in_0_bits_mpam_perfMonGroup,
+  input  [8:0]  io_in_0_bits_mpam_partID,
+  input         io_in_0_bits_mpam_mpamNS,
+  input  [3:0]  io_in_0_bits_rsvdc,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_qos,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [10:0] io_out_bits_returnNID,
+  output        io_out_bits_stashNIDValid,
+  output [11:0] io_out_bits_returnTxnID,
+  output [6:0]  io_out_bits_opcode,
+  output [2:0]  io_out_bits_size,
+  output [47:0] io_out_bits_addr,
+  output        io_out_bits_ns,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_allowRetry,
+  output [1:0]  io_out_bits_order,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_device,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_snpAttr,
+  output [7:0]  io_out_bits_lpIDWithPadding,
+  output        io_out_bits_snoopMe,
+  output        io_out_bits_expCompAck,
+  output [1:0]  io_out_bits_tagOp,
+  output        io_out_bits_traceTag,
+  output        io_out_bits_mpam_perfMonGroup,
+  output [8:0]  io_out_bits_mpam_partID,
+  output        io_out_bits_mpam_mpamNS,
+  output [3:0]  io_out_bits_rsvdc
+);
+
+  assign io_in_0_ready = io_in_0_valid & io_out_ready;
+  assign io_out_valid = io_in_0_valid;
+  assign io_out_bits_qos = io_in_0_bits_qos;
+  assign io_out_bits_tgtID = io_in_0_bits_tgtID;
+  assign io_out_bits_srcID = io_in_0_bits_srcID;
+  assign io_out_bits_txnID = io_in_0_bits_txnID;
+  assign io_out_bits_returnNID = io_in_0_bits_returnNID;
+  assign io_out_bits_stashNIDValid = io_in_0_bits_stashNIDValid;
+  assign io_out_bits_returnTxnID = io_in_0_bits_returnTxnID;
+  assign io_out_bits_opcode = io_in_0_bits_opcode;
+  assign io_out_bits_size = io_in_0_bits_size;
+  assign io_out_bits_addr = io_in_0_bits_addr;
+  assign io_out_bits_ns = io_in_0_bits_ns;
+  assign io_out_bits_likelyshared = io_in_0_bits_likelyshared;
+  assign io_out_bits_allowRetry = io_in_0_bits_allowRetry;
+  assign io_out_bits_order = io_in_0_bits_order;
+  assign io_out_bits_pCrdType = io_in_0_bits_pCrdType;
+  assign io_out_bits_memAttr_allocate = io_in_0_bits_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable = io_in_0_bits_memAttr_cacheable;
+  assign io_out_bits_memAttr_device = io_in_0_bits_memAttr_device;
+  assign io_out_bits_memAttr_ewa = io_in_0_bits_memAttr_ewa;
+  assign io_out_bits_snpAttr = io_in_0_bits_snpAttr;
+  assign io_out_bits_lpIDWithPadding = io_in_0_bits_lpIDWithPadding;
+  assign io_out_bits_snoopMe = io_in_0_bits_snoopMe;
+  assign io_out_bits_expCompAck = io_in_0_bits_expCompAck;
+  assign io_out_bits_tagOp = io_in_0_bits_tagOp;
+  assign io_out_bits_traceTag = io_in_0_bits_traceTag;
+  assign io_out_bits_mpam_perfMonGroup = io_in_0_bits_mpam_perfMonGroup;
+  assign io_out_bits_mpam_partID = io_in_0_bits_mpam_partID;
+  assign io_out_bits_mpam_mpamNS = io_in_0_bits_mpam_mpamNS;
+  assign io_out_bits_rsvdc = io_in_0_bits_rsvdc;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_26.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_26.sv
new file mode 100644
index 0000000000..0e8a314b6c
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_26.sv
@@ -0,0 +1,50 @@
+// Generated by CIRCT firtool-1.135.0
+module FastArbiter_26(
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [3:0]  io_in_0_bits_qos,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [10:0] io_in_0_bits_srcID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [4:0]  io_in_0_bits_opcode,
+  input  [1:0]  io_in_0_bits_respErr,
+  input  [2:0]  io_in_0_bits_resp,
+  input  [2:0]  io_in_0_bits_fwdState,
+  input  [2:0]  io_in_0_bits_cBusy,
+  input  [11:0] io_in_0_bits_dbID,
+  input  [3:0]  io_in_0_bits_pCrdType,
+  input  [1:0]  io_in_0_bits_tagOp,
+  input         io_in_0_bits_traceTag,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_qos,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [4:0]  io_out_bits_opcode,
+  output [1:0]  io_out_bits_respErr,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output [2:0]  io_out_bits_cBusy,
+  output [11:0] io_out_bits_dbID,
+  output [3:0]  io_out_bits_pCrdType,
+  output [1:0]  io_out_bits_tagOp,
+  output        io_out_bits_traceTag
+);
+
+  assign io_in_0_ready = io_in_0_valid & io_out_ready;
+  assign io_out_valid = io_in_0_valid;
+  assign io_out_bits_qos = io_in_0_bits_qos;
+  assign io_out_bits_tgtID = io_in_0_bits_tgtID;
+  assign io_out_bits_srcID = io_in_0_bits_srcID;
+  assign io_out_bits_txnID = io_in_0_bits_txnID;
+  assign io_out_bits_opcode = io_in_0_bits_opcode;
+  assign io_out_bits_respErr = io_in_0_bits_respErr;
+  assign io_out_bits_resp = io_in_0_bits_resp;
+  assign io_out_bits_fwdState = io_in_0_bits_fwdState;
+  assign io_out_bits_cBusy = io_in_0_bits_cBusy;
+  assign io_out_bits_dbID = io_in_0_bits_dbID;
+  assign io_out_bits_pCrdType = io_in_0_bits_pCrdType;
+  assign io_out_bits_tagOp = io_in_0_bits_tagOp;
+  assign io_out_bits_traceTag = io_in_0_bits_traceTag;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_27.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_27.sv
new file mode 100644
index 0000000000..839fb6668b
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_27.sv
@@ -0,0 +1,225 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_27(
+  input          clock,
+  input          reset,
+  output         io_in_0_ready,
+  input          io_in_0_valid,
+  input  [3:0]   io_in_0_bits_qos,
+  input  [10:0]  io_in_0_bits_tgtID,
+  input  [10:0]  io_in_0_bits_srcID,
+  input  [11:0]  io_in_0_bits_txnID,
+  input  [10:0]  io_in_0_bits_homeNID,
+  input  [3:0]   io_in_0_bits_opcode,
+  input  [1:0]   io_in_0_bits_respErr,
+  input  [2:0]   io_in_0_bits_resp,
+  input  [3:0]   io_in_0_bits_dataSource,
+  input  [2:0]   io_in_0_bits_cBusy,
+  input  [11:0]  io_in_0_bits_dbID,
+  input  [1:0]   io_in_0_bits_ccID,
+  input  [1:0]   io_in_0_bits_dataID,
+  input  [1:0]   io_in_0_bits_tagOp,
+  input  [7:0]   io_in_0_bits_tag,
+  input  [1:0]   io_in_0_bits_tu,
+  input          io_in_0_bits_traceTag,
+  input  [3:0]   io_in_0_bits_rsvdc,
+  input  [31:0]  io_in_0_bits_be,
+  input  [255:0] io_in_0_bits_data,
+  input  [31:0]  io_in_0_bits_dataCheck,
+  input  [3:0]   io_in_0_bits_poison,
+  output         io_in_1_ready,
+  input          io_in_1_valid,
+  input  [3:0]   io_in_1_bits_qos,
+  input  [10:0]  io_in_1_bits_tgtID,
+  input  [10:0]  io_in_1_bits_srcID,
+  input  [11:0]  io_in_1_bits_txnID,
+  input  [10:0]  io_in_1_bits_homeNID,
+  input  [3:0]   io_in_1_bits_opcode,
+  input  [1:0]   io_in_1_bits_respErr,
+  input  [2:0]   io_in_1_bits_resp,
+  input  [3:0]   io_in_1_bits_dataSource,
+  input  [2:0]   io_in_1_bits_cBusy,
+  input  [11:0]  io_in_1_bits_dbID,
+  input  [1:0]   io_in_1_bits_ccID,
+  input  [1:0]   io_in_1_bits_dataID,
+  input  [1:0]   io_in_1_bits_tagOp,
+  input  [7:0]   io_in_1_bits_tag,
+  input  [1:0]   io_in_1_bits_tu,
+  input          io_in_1_bits_traceTag,
+  input  [3:0]   io_in_1_bits_rsvdc,
+  input  [31:0]  io_in_1_bits_be,
+  input  [255:0] io_in_1_bits_data,
+  input  [31:0]  io_in_1_bits_dataCheck,
+  input  [3:0]   io_in_1_bits_poison,
+  input          io_out_ready,
+  output         io_out_valid,
+  output [3:0]   io_out_bits_qos,
+  output [10:0]  io_out_bits_tgtID,
+  output [10:0]  io_out_bits_srcID,
+  output [11:0]  io_out_bits_txnID,
+  output [10:0]  io_out_bits_homeNID,
+  output [3:0]   io_out_bits_opcode,
+  output [1:0]   io_out_bits_respErr,
+  output [2:0]   io_out_bits_resp,
+  output [3:0]   io_out_bits_dataSource,
+  output [2:0]   io_out_bits_cBusy,
+  output [11:0]  io_out_bits_dbID,
+  output [1:0]   io_out_bits_ccID,
+  output [1:0]   io_out_bits_dataID,
+  output [1:0]   io_out_bits_tagOp,
+  output [7:0]   io_out_bits_tag,
+  output [1:0]   io_out_bits_tu,
+  output         io_out_bits_traceTag,
+  output [3:0]   io_out_bits_rsvdc,
+  output [31:0]  io_out_bits_be,
+  output [255:0] io_out_bits_data,
+  output [31:0]  io_out_bits_dataCheck,
+  output [3:0]   io_out_bits_poison,
+  output         io_chosen
+);
+
+  wire [1:0] chosenOH;
+  wire [1:0] valids = {io_in_1_valid, io_in_0_valid};
+  reg  [1:0] pendingMask;
+  reg  [1:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire [1:0] rrSelOH =
+    {rrGrantMask[1] & pendingMask[1] & ~_rrSelOH_oh_WIRE_0, _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids)) ? rrSelOH : {io_in_1_valid & ~io_in_0_valid, io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 2'h0;
+      rrGrantMask <= 2'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <= {chosenOH[0], 1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][1:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][3:2];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 2'h0;
+        rrGrantMask = 2'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_out_valid = |valids;
+  assign io_out_bits_qos =
+    (chosenOH[0] ? io_in_0_bits_qos : 4'h0) | (chosenOH[1] ? io_in_1_bits_qos : 4'h0);
+  assign io_out_bits_tgtID =
+    (chosenOH[0] ? io_in_0_bits_tgtID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_tgtID : 11'h0);
+  assign io_out_bits_srcID =
+    (chosenOH[0] ? io_in_0_bits_srcID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_srcID : 11'h0);
+  assign io_out_bits_txnID =
+    (chosenOH[0] ? io_in_0_bits_txnID : 12'h0)
+    | (chosenOH[1] ? io_in_1_bits_txnID : 12'h0);
+  assign io_out_bits_homeNID =
+    (chosenOH[0] ? io_in_0_bits_homeNID : 11'h0)
+    | (chosenOH[1] ? io_in_1_bits_homeNID : 11'h0);
+  assign io_out_bits_opcode =
+    (chosenOH[0] ? io_in_0_bits_opcode : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_opcode : 4'h0);
+  assign io_out_bits_respErr =
+    (chosenOH[0] ? io_in_0_bits_respErr : 2'h0)
+    | (chosenOH[1] ? io_in_1_bits_respErr : 2'h0);
+  assign io_out_bits_resp =
+    (chosenOH[0] ? io_in_0_bits_resp : 3'h0) | (chosenOH[1] ? io_in_1_bits_resp : 3'h0);
+  assign io_out_bits_dataSource =
+    (chosenOH[0] ? io_in_0_bits_dataSource : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_dataSource : 4'h0);
+  assign io_out_bits_cBusy =
+    (chosenOH[0] ? io_in_0_bits_cBusy : 3'h0) | (chosenOH[1] ? io_in_1_bits_cBusy : 3'h0);
+  assign io_out_bits_dbID =
+    (chosenOH[0] ? io_in_0_bits_dbID : 12'h0) | (chosenOH[1] ? io_in_1_bits_dbID : 12'h0);
+  assign io_out_bits_ccID =
+    (chosenOH[0] ? io_in_0_bits_ccID : 2'h0) | (chosenOH[1] ? io_in_1_bits_ccID : 2'h0);
+  assign io_out_bits_dataID =
+    (chosenOH[0] ? io_in_0_bits_dataID : 2'h0)
+    | (chosenOH[1] ? io_in_1_bits_dataID : 2'h0);
+  assign io_out_bits_tagOp =
+    (chosenOH[0] ? io_in_0_bits_tagOp : 2'h0) | (chosenOH[1] ? io_in_1_bits_tagOp : 2'h0);
+  assign io_out_bits_tag =
+    (chosenOH[0] ? io_in_0_bits_tag : 8'h0) | (chosenOH[1] ? io_in_1_bits_tag : 8'h0);
+  assign io_out_bits_tu =
+    (chosenOH[0] ? io_in_0_bits_tu : 2'h0) | (chosenOH[1] ? io_in_1_bits_tu : 2'h0);
+  assign io_out_bits_traceTag =
+    chosenOH[0] & io_in_0_bits_traceTag | chosenOH[1] & io_in_1_bits_traceTag;
+  assign io_out_bits_rsvdc =
+    (chosenOH[0] ? io_in_0_bits_rsvdc : 4'h0) | (chosenOH[1] ? io_in_1_bits_rsvdc : 4'h0);
+  assign io_out_bits_be =
+    (chosenOH[0] ? io_in_0_bits_be : 32'h0) | (chosenOH[1] ? io_in_1_bits_be : 32'h0);
+  assign io_out_bits_data =
+    (chosenOH[0] ? io_in_0_bits_data : 256'h0)
+    | (chosenOH[1] ? io_in_1_bits_data : 256'h0);
+  assign io_out_bits_dataCheck =
+    (chosenOH[0] ? io_in_0_bits_dataCheck : 32'h0)
+    | (chosenOH[1] ? io_in_1_bits_dataCheck : 32'h0);
+  assign io_out_bits_poison =
+    (chosenOH[0] ? io_in_0_bits_poison : 4'h0)
+    | (chosenOH[1] ? io_in_1_bits_poison : 4'h0);
+  assign io_chosen = chosenOH[1];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_28.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_28.sv
new file mode 100644
index 0000000000..5e8051aea6
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_28.sv
@@ -0,0 +1,444 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_28(
+  input  clock,
+  input  reset,
+  output io_in_0_ready,
+  input  io_in_0_valid,
+  output io_in_1_ready,
+  input  io_in_1_valid,
+  output io_in_2_ready,
+  input  io_in_2_valid,
+  output io_in_3_ready,
+  input  io_in_3_valid,
+  output io_in_4_ready,
+  input  io_in_4_valid,
+  output io_in_5_ready,
+  input  io_in_5_valid,
+  output io_in_6_ready,
+  input  io_in_6_valid,
+  output io_in_7_ready,
+  input  io_in_7_valid,
+  output io_in_8_ready,
+  input  io_in_8_valid,
+  output io_in_9_ready,
+  input  io_in_9_valid,
+  output io_in_10_ready,
+  input  io_in_10_valid,
+  output io_in_11_ready,
+  input  io_in_11_valid,
+  output io_in_12_ready,
+  input  io_in_12_valid,
+  output io_in_13_ready,
+  input  io_in_13_valid,
+  output io_in_14_ready,
+  input  io_in_14_valid,
+  output io_in_15_ready,
+  input  io_in_15_valid,
+  input  io_out_ready,
+  output io_out_valid
+);
+
+  wire [15:0] chosenOH;
+  wire [15:0] valids =
+    {io_in_15_valid,
+     io_in_14_valid,
+     io_in_13_valid,
+     io_in_12_valid,
+     io_in_11_valid,
+     io_in_10_valid,
+     io_in_9_valid,
+     io_in_8_valid,
+     io_in_7_valid,
+     io_in_6_valid,
+     io_in_5_valid,
+     io_in_4_valid,
+     io_in_3_valid,
+     io_in_2_valid,
+     io_in_1_valid,
+     io_in_0_valid};
+  reg  [15:0] pendingMask;
+  reg  [15:0] rrGrantMask;
+  wire        _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire        _rrSelOH_T_2 = rrGrantMask[1] & pendingMask[1];
+  wire        _rrSelOH_T_3 = rrGrantMask[2] & pendingMask[2];
+  wire        _rrSelOH_T_4 = rrGrantMask[3] & pendingMask[3];
+  wire        _rrSelOH_T_5 = rrGrantMask[4] & pendingMask[4];
+  wire        _rrSelOH_T_6 = rrGrantMask[5] & pendingMask[5];
+  wire        _rrSelOH_T_7 = rrGrantMask[6] & pendingMask[6];
+  wire        _rrSelOH_T_8 = rrGrantMask[7] & pendingMask[7];
+  wire        _rrSelOH_T_9 = rrGrantMask[8] & pendingMask[8];
+  wire        _rrSelOH_T_10 = rrGrantMask[9] & pendingMask[9];
+  wire        _rrSelOH_T_11 = rrGrantMask[10] & pendingMask[10];
+  wire        _rrSelOH_T_12 = rrGrantMask[11] & pendingMask[11];
+  wire        _rrSelOH_T_13 = rrGrantMask[12] & pendingMask[12];
+  wire        _rrSelOH_T_14 = rrGrantMask[13] & pendingMask[13];
+  wire        _rrSelOH_T_15 = rrGrantMask[14] & pendingMask[14];
+  wire [15:0] rrSelOH =
+    {rrGrantMask[15] & pendingMask[15]
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7,
+          _rrSelOH_T_8,
+          _rrSelOH_T_9,
+          _rrSelOH_T_10,
+          _rrSelOH_T_11,
+          _rrSelOH_T_12,
+          _rrSelOH_T_13,
+          _rrSelOH_T_14,
+          _rrSelOH_T_15} == 15'h0,
+     _rrSelOH_T_15
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7,
+          _rrSelOH_T_8,
+          _rrSelOH_T_9,
+          _rrSelOH_T_10,
+          _rrSelOH_T_11,
+          _rrSelOH_T_12,
+          _rrSelOH_T_13,
+          _rrSelOH_T_14} == 14'h0,
+     _rrSelOH_T_14
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7,
+          _rrSelOH_T_8,
+          _rrSelOH_T_9,
+          _rrSelOH_T_10,
+          _rrSelOH_T_11,
+          _rrSelOH_T_12,
+          _rrSelOH_T_13} == 13'h0,
+     _rrSelOH_T_13
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7,
+          _rrSelOH_T_8,
+          _rrSelOH_T_9,
+          _rrSelOH_T_10,
+          _rrSelOH_T_11,
+          _rrSelOH_T_12} == 12'h0,
+     _rrSelOH_T_12
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7,
+          _rrSelOH_T_8,
+          _rrSelOH_T_9,
+          _rrSelOH_T_10,
+          _rrSelOH_T_11} == 11'h0,
+     _rrSelOH_T_11
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7,
+          _rrSelOH_T_8,
+          _rrSelOH_T_9,
+          _rrSelOH_T_10} == 10'h0,
+     _rrSelOH_T_10
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7,
+          _rrSelOH_T_8,
+          _rrSelOH_T_9} == 9'h0,
+     _rrSelOH_T_9
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7,
+          _rrSelOH_T_8} == 8'h0,
+     _rrSelOH_T_8
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7} == 7'h0,
+     _rrSelOH_T_7
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6} == 6'h0,
+     _rrSelOH_T_6
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5} == 5'h0,
+     _rrSelOH_T_5
+       & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3, _rrSelOH_T_4} == 4'h0,
+     _rrSelOH_T_4 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3} == 3'h0,
+     _rrSelOH_T_3 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2} == 2'h0,
+     _rrSelOH_T_2 & ~_rrSelOH_oh_WIRE_0,
+     _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids))
+      ? rrSelOH
+      : {io_in_15_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid,
+              io_in_7_valid,
+              io_in_8_valid,
+              io_in_9_valid,
+              io_in_10_valid,
+              io_in_11_valid,
+              io_in_12_valid,
+              io_in_13_valid,
+              io_in_14_valid} == 15'h0,
+         io_in_14_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid,
+              io_in_7_valid,
+              io_in_8_valid,
+              io_in_9_valid,
+              io_in_10_valid,
+              io_in_11_valid,
+              io_in_12_valid,
+              io_in_13_valid} == 14'h0,
+         io_in_13_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid,
+              io_in_7_valid,
+              io_in_8_valid,
+              io_in_9_valid,
+              io_in_10_valid,
+              io_in_11_valid,
+              io_in_12_valid} == 13'h0,
+         io_in_12_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid,
+              io_in_7_valid,
+              io_in_8_valid,
+              io_in_9_valid,
+              io_in_10_valid,
+              io_in_11_valid} == 12'h0,
+         io_in_11_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid,
+              io_in_7_valid,
+              io_in_8_valid,
+              io_in_9_valid,
+              io_in_10_valid} == 11'h0,
+         io_in_10_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid,
+              io_in_7_valid,
+              io_in_8_valid,
+              io_in_9_valid} == 10'h0,
+         io_in_9_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid,
+              io_in_7_valid,
+              io_in_8_valid} == 9'h0,
+         io_in_8_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid,
+              io_in_7_valid} == 8'h0,
+         io_in_7_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid} == 7'h0,
+         io_in_6_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid} == 6'h0,
+         io_in_5_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid} == 5'h0,
+         io_in_4_valid
+           & {io_in_0_valid, io_in_1_valid, io_in_2_valid, io_in_3_valid} == 4'h0,
+         io_in_3_valid & {io_in_0_valid, io_in_1_valid, io_in_2_valid} == 3'h0,
+         io_in_2_valid & {io_in_0_valid, io_in_1_valid} == 2'h0,
+         io_in_1_valid & ~io_in_0_valid,
+         io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 16'h0;
+      rrGrantMask <= 16'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <=
+        {|(chosenOH[14:0]),
+         |(chosenOH[13:0]),
+         |(chosenOH[12:0]),
+         |(chosenOH[11:0]),
+         |(chosenOH[10:0]),
+         |(chosenOH[9:0]),
+         |(chosenOH[8:0]),
+         |(chosenOH[7:0]),
+         |(chosenOH[6:0]),
+         |(chosenOH[5:0]),
+         |(chosenOH[4:0]),
+         |(chosenOH[3:0]),
+         |(chosenOH[2:0]),
+         |(chosenOH[1:0]),
+         chosenOH[0],
+         1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][15:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][31:16];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 16'h0;
+        rrGrantMask = 16'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_in_2_ready = chosenOH[2] & io_out_ready;
+  assign io_in_3_ready = chosenOH[3] & io_out_ready;
+  assign io_in_4_ready = chosenOH[4] & io_out_ready;
+  assign io_in_5_ready = chosenOH[5] & io_out_ready;
+  assign io_in_6_ready = chosenOH[6] & io_out_ready;
+  assign io_in_7_ready = chosenOH[7] & io_out_ready;
+  assign io_in_8_ready = chosenOH[8] & io_out_ready;
+  assign io_in_9_ready = chosenOH[9] & io_out_ready;
+  assign io_in_10_ready = chosenOH[10] & io_out_ready;
+  assign io_in_11_ready = chosenOH[11] & io_out_ready;
+  assign io_in_12_ready = chosenOH[12] & io_out_ready;
+  assign io_in_13_ready = chosenOH[13] & io_out_ready;
+  assign io_in_14_ready = chosenOH[14] & io_out_ready;
+  assign io_in_15_ready = chosenOH[15] & io_out_ready;
+  assign io_out_valid = |valids;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_4.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_4.sv
new file mode 100644
index 0000000000..cf54419e69
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_4.sv
@@ -0,0 +1,214 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_4(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [49:0] io_in_0_bits_vaddr,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [49:0] io_in_1_bits_vaddr,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [49:0] io_in_2_bits_vaddr,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [49:0] io_in_3_bits_vaddr,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [49:0] io_in_4_bits_vaddr,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [49:0] io_in_5_bits_vaddr,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [49:0] io_in_6_bits_vaddr,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [49:0] io_in_7_bits_vaddr,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [49:0] io_out_bits_vaddr
+);
+
+  wire [7:0] chosenOH;
+  wire [7:0] valids =
+    {io_in_7_valid,
+     io_in_6_valid,
+     io_in_5_valid,
+     io_in_4_valid,
+     io_in_3_valid,
+     io_in_2_valid,
+     io_in_1_valid,
+     io_in_0_valid};
+  reg  [7:0] pendingMask;
+  reg  [7:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire       _rrSelOH_T_2 = rrGrantMask[1] & pendingMask[1];
+  wire       _rrSelOH_T_3 = rrGrantMask[2] & pendingMask[2];
+  wire       _rrSelOH_T_4 = rrGrantMask[3] & pendingMask[3];
+  wire       _rrSelOH_T_5 = rrGrantMask[4] & pendingMask[4];
+  wire       _rrSelOH_T_6 = rrGrantMask[5] & pendingMask[5];
+  wire       _rrSelOH_T_7 = rrGrantMask[6] & pendingMask[6];
+  wire [7:0] rrSelOH =
+    {rrGrantMask[7] & pendingMask[7]
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7} == 7'h0,
+     _rrSelOH_T_7
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6} == 6'h0,
+     _rrSelOH_T_6
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5} == 5'h0,
+     _rrSelOH_T_5
+       & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3, _rrSelOH_T_4} == 4'h0,
+     _rrSelOH_T_4 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3} == 3'h0,
+     _rrSelOH_T_3 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2} == 2'h0,
+     _rrSelOH_T_2 & ~_rrSelOH_oh_WIRE_0,
+     _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids))
+      ? rrSelOH
+      : {io_in_7_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid} == 7'h0,
+         io_in_6_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid} == 6'h0,
+         io_in_5_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid} == 5'h0,
+         io_in_4_valid
+           & {io_in_0_valid, io_in_1_valid, io_in_2_valid, io_in_3_valid} == 4'h0,
+         io_in_3_valid & {io_in_0_valid, io_in_1_valid, io_in_2_valid} == 3'h0,
+         io_in_2_valid & {io_in_0_valid, io_in_1_valid} == 2'h0,
+         io_in_1_valid & ~io_in_0_valid,
+         io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 8'h0;
+      rrGrantMask <= 8'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <=
+        {|(chosenOH[6:0]),
+         |(chosenOH[5:0]),
+         |(chosenOH[4:0]),
+         |(chosenOH[3:0]),
+         |(chosenOH[2:0]),
+         |(chosenOH[1:0]),
+         chosenOH[0],
+         1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][7:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][15:8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 8'h0;
+        rrGrantMask = 8'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_in_2_ready = chosenOH[2] & io_out_ready;
+  assign io_in_3_ready = chosenOH[3] & io_out_ready;
+  assign io_in_4_ready = chosenOH[4] & io_out_ready;
+  assign io_in_5_ready = chosenOH[5] & io_out_ready;
+  assign io_in_6_ready = chosenOH[6] & io_out_ready;
+  assign io_in_7_ready = chosenOH[7] & io_out_ready;
+  assign io_out_valid = |valids;
+  assign io_out_bits_vaddr =
+    (chosenOH[0] ? io_in_0_bits_vaddr : 50'h0)
+    | (chosenOH[1] ? io_in_1_bits_vaddr : 50'h0)
+    | (chosenOH[2] ? io_in_2_bits_vaddr : 50'h0)
+    | (chosenOH[3] ? io_in_3_bits_vaddr : 50'h0)
+    | (chosenOH[4] ? io_in_4_bits_vaddr : 50'h0)
+    | (chosenOH[5] ? io_in_5_bits_vaddr : 50'h0)
+    | (chosenOH[6] ? io_in_6_bits_vaddr : 50'h0)
+    | (chosenOH[7] ? io_in_7_bits_vaddr : 50'h0);
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_6.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_6.sv
new file mode 100644
index 0000000000..d68689eeed
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_6.sv
@@ -0,0 +1,274 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module FastArbiter_6(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [33:0] io_in_0_bits_tag,
+  input  [7:0]  io_in_0_bits_set,
+  input  [43:0] io_in_0_bits_vaddr,
+  input         io_in_0_bits_needT,
+  input  [6:0]  io_in_0_bits_source,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [33:0] io_in_1_bits_tag,
+  input  [7:0]  io_in_1_bits_set,
+  input  [43:0] io_in_1_bits_vaddr,
+  input         io_in_1_bits_needT,
+  input  [6:0]  io_in_1_bits_source,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [33:0] io_in_2_bits_tag,
+  input  [7:0]  io_in_2_bits_set,
+  input  [43:0] io_in_2_bits_vaddr,
+  input         io_in_2_bits_needT,
+  input  [6:0]  io_in_2_bits_source,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [33:0] io_in_3_bits_tag,
+  input  [7:0]  io_in_3_bits_set,
+  input  [43:0] io_in_3_bits_vaddr,
+  input         io_in_3_bits_needT,
+  input  [6:0]  io_in_3_bits_source,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [33:0] io_in_4_bits_tag,
+  input  [7:0]  io_in_4_bits_set,
+  input  [43:0] io_in_4_bits_vaddr,
+  input         io_in_4_bits_needT,
+  input  [6:0]  io_in_4_bits_source,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [33:0] io_in_5_bits_tag,
+  input  [7:0]  io_in_5_bits_set,
+  input  [43:0] io_in_5_bits_vaddr,
+  input         io_in_5_bits_needT,
+  input  [6:0]  io_in_5_bits_source,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [33:0] io_in_6_bits_tag,
+  input  [7:0]  io_in_6_bits_set,
+  input  [43:0] io_in_6_bits_vaddr,
+  input         io_in_6_bits_needT,
+  input  [6:0]  io_in_6_bits_source,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [33:0] io_in_7_bits_tag,
+  input  [7:0]  io_in_7_bits_set,
+  input  [43:0] io_in_7_bits_vaddr,
+  input         io_in_7_bits_needT,
+  input  [6:0]  io_in_7_bits_source,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [33:0] io_out_bits_tag,
+  output [7:0]  io_out_bits_set,
+  output [43:0] io_out_bits_vaddr,
+  output        io_out_bits_needT,
+  output [6:0]  io_out_bits_source
+);
+
+  wire [7:0] chosenOH;
+  wire [7:0] valids =
+    {io_in_7_valid,
+     io_in_6_valid,
+     io_in_5_valid,
+     io_in_4_valid,
+     io_in_3_valid,
+     io_in_2_valid,
+     io_in_1_valid,
+     io_in_0_valid};
+  reg  [7:0] pendingMask;
+  reg  [7:0] rrGrantMask;
+  wire       _rrSelOH_oh_WIRE_0 = rrGrantMask[0] & pendingMask[0];
+  wire       _rrSelOH_T_2 = rrGrantMask[1] & pendingMask[1];
+  wire       _rrSelOH_T_3 = rrGrantMask[2] & pendingMask[2];
+  wire       _rrSelOH_T_4 = rrGrantMask[3] & pendingMask[3];
+  wire       _rrSelOH_T_5 = rrGrantMask[4] & pendingMask[4];
+  wire       _rrSelOH_T_6 = rrGrantMask[5] & pendingMask[5];
+  wire       _rrSelOH_T_7 = rrGrantMask[6] & pendingMask[6];
+  wire [7:0] rrSelOH =
+    {rrGrantMask[7] & pendingMask[7]
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6,
+          _rrSelOH_T_7} == 7'h0,
+     _rrSelOH_T_7
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5,
+          _rrSelOH_T_6} == 6'h0,
+     _rrSelOH_T_6
+       & {_rrSelOH_oh_WIRE_0,
+          _rrSelOH_T_2,
+          _rrSelOH_T_3,
+          _rrSelOH_T_4,
+          _rrSelOH_T_5} == 5'h0,
+     _rrSelOH_T_5
+       & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3, _rrSelOH_T_4} == 4'h0,
+     _rrSelOH_T_4 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2, _rrSelOH_T_3} == 3'h0,
+     _rrSelOH_T_3 & {_rrSelOH_oh_WIRE_0, _rrSelOH_T_2} == 2'h0,
+     _rrSelOH_T_2 & ~_rrSelOH_oh_WIRE_0,
+     _rrSelOH_oh_WIRE_0};
+  assign chosenOH =
+    (|(rrSelOH & valids))
+      ? rrSelOH
+      : {io_in_7_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid,
+              io_in_6_valid} == 7'h0,
+         io_in_6_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid,
+              io_in_5_valid} == 6'h0,
+         io_in_5_valid
+           & {io_in_0_valid,
+              io_in_1_valid,
+              io_in_2_valid,
+              io_in_3_valid,
+              io_in_4_valid} == 5'h0,
+         io_in_4_valid
+           & {io_in_0_valid, io_in_1_valid, io_in_2_valid, io_in_3_valid} == 4'h0,
+         io_in_3_valid & {io_in_0_valid, io_in_1_valid, io_in_2_valid} == 3'h0,
+         io_in_2_valid & {io_in_0_valid, io_in_1_valid} == 2'h0,
+         io_in_1_valid & ~io_in_0_valid,
+         io_in_0_valid};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      pendingMask <= 8'h0;
+      rrGrantMask <= 8'h0;
+    end
+    else if (io_out_ready & (|valids)) begin
+      pendingMask <= valids & ~chosenOH;
+      rrGrantMask <=
+        {|(chosenOH[6:0]),
+         |(chosenOH[5:0]),
+         |(chosenOH[4:0]),
+         |(chosenOH[3:0]),
+         |(chosenOH[2:0]),
+         |(chosenOH[1:0]),
+         chosenOH[0],
+         1'h0};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        pendingMask = _RANDOM[/*Zero width*/ 1'b0][7:0];
+        rrGrantMask = _RANDOM[/*Zero width*/ 1'b0][15:8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        pendingMask = 8'h0;
+        rrGrantMask = 8'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_0_ready = chosenOH[0] & io_out_ready;
+  assign io_in_1_ready = chosenOH[1] & io_out_ready;
+  assign io_in_2_ready = chosenOH[2] & io_out_ready;
+  assign io_in_3_ready = chosenOH[3] & io_out_ready;
+  assign io_in_4_ready = chosenOH[4] & io_out_ready;
+  assign io_in_5_ready = chosenOH[5] & io_out_ready;
+  assign io_in_6_ready = chosenOH[6] & io_out_ready;
+  assign io_in_7_ready = chosenOH[7] & io_out_ready;
+  assign io_out_valid = |valids;
+  assign io_out_bits_tag =
+    (chosenOH[0] ? io_in_0_bits_tag : 34'h0) | (chosenOH[1] ? io_in_1_bits_tag : 34'h0)
+    | (chosenOH[2] ? io_in_2_bits_tag : 34'h0) | (chosenOH[3] ? io_in_3_bits_tag : 34'h0)
+    | (chosenOH[4] ? io_in_4_bits_tag : 34'h0) | (chosenOH[5] ? io_in_5_bits_tag : 34'h0)
+    | (chosenOH[6] ? io_in_6_bits_tag : 34'h0) | (chosenOH[7] ? io_in_7_bits_tag : 34'h0);
+  assign io_out_bits_set =
+    (chosenOH[0] ? io_in_0_bits_set : 8'h0) | (chosenOH[1] ? io_in_1_bits_set : 8'h0)
+    | (chosenOH[2] ? io_in_2_bits_set : 8'h0) | (chosenOH[3] ? io_in_3_bits_set : 8'h0)
+    | (chosenOH[4] ? io_in_4_bits_set : 8'h0) | (chosenOH[5] ? io_in_5_bits_set : 8'h0)
+    | (chosenOH[6] ? io_in_6_bits_set : 8'h0) | (chosenOH[7] ? io_in_7_bits_set : 8'h0);
+  assign io_out_bits_vaddr =
+    (chosenOH[0] ? io_in_0_bits_vaddr : 44'h0)
+    | (chosenOH[1] ? io_in_1_bits_vaddr : 44'h0)
+    | (chosenOH[2] ? io_in_2_bits_vaddr : 44'h0)
+    | (chosenOH[3] ? io_in_3_bits_vaddr : 44'h0)
+    | (chosenOH[4] ? io_in_4_bits_vaddr : 44'h0)
+    | (chosenOH[5] ? io_in_5_bits_vaddr : 44'h0)
+    | (chosenOH[6] ? io_in_6_bits_vaddr : 44'h0)
+    | (chosenOH[7] ? io_in_7_bits_vaddr : 44'h0);
+  assign io_out_bits_needT =
+    chosenOH[0] & io_in_0_bits_needT | chosenOH[1] & io_in_1_bits_needT | chosenOH[2]
+    & io_in_2_bits_needT | chosenOH[3] & io_in_3_bits_needT | chosenOH[4]
+    & io_in_4_bits_needT | chosenOH[5] & io_in_5_bits_needT | chosenOH[6]
+    & io_in_6_bits_needT | chosenOH[7] & io_in_7_bits_needT;
+  assign io_out_bits_source =
+    (chosenOH[0] ? io_in_0_bits_source : 7'h0)
+    | (chosenOH[1] ? io_in_1_bits_source : 7'h0)
+    | (chosenOH[2] ? io_in_2_bits_source : 7'h0)
+    | (chosenOH[3] ? io_in_3_bits_source : 7'h0)
+    | (chosenOH[4] ? io_in_4_bits_source : 7'h0)
+    | (chosenOH[5] ? io_in_5_bits_source : 7'h0)
+    | (chosenOH[6] ? io_in_6_bits_source : 7'h0)
+    | (chosenOH[7] ? io_in_7_bits_source : 7'h0);
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_8.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_8.sv
new file mode 100644
index 0000000000..7fe00eb881
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_8.sv
@@ -0,0 +1,29 @@
+// Generated by CIRCT firtool-1.135.0
+module FastArbiter_8(
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [33:0] io_in_0_bits_tag,
+  input  [7:0]  io_in_0_bits_set,
+  input         io_in_0_bits_needT,
+  input  [6:0]  io_in_0_bits_source,
+  input  [43:0] io_in_0_bits_vaddr,
+  input  [4:0]  io_in_0_bits_reqsource,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [33:0] io_out_bits_tag,
+  output [7:0]  io_out_bits_set,
+  output        io_out_bits_needT,
+  output [6:0]  io_out_bits_source,
+  output [43:0] io_out_bits_vaddr,
+  output [4:0]  io_out_bits_reqsource
+);
+
+  assign io_in_0_ready = io_in_0_valid & io_out_ready;
+  assign io_out_valid = io_in_0_valid;
+  assign io_out_bits_tag = io_in_0_bits_tag;
+  assign io_out_bits_set = io_in_0_bits_set;
+  assign io_out_bits_needT = io_in_0_bits_needT;
+  assign io_out_bits_source = io_in_0_bits_source;
+  assign io_out_bits_vaddr = io_in_0_bits_vaddr;
+  assign io_out_bits_reqsource = io_in_0_bits_reqsource;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_9.sv b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_9.sv
new file mode 100644
index 0000000000..2aba35c5ab
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/FastArbiter_9.sv
@@ -0,0 +1,9 @@
+// Generated by CIRCT firtool-1.135.0
+module FastArbiter_9(
+  output io_in_0_ready,
+  input  io_in_0_valid,
+  input  io_out_ready
+);
+
+  assign io_in_0_ready = io_in_0_valid & io_out_ready;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/GatedSplittedSRAM.sv b/flow/designs/src/xiangshan_coupledl2/deps/GatedSplittedSRAM.sv
new file mode 100644
index 0000000000..0a8a5ef681
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/GatedSplittedSRAM.sv
@@ -0,0 +1,283 @@
+// Generated by CIRCT firtool-1.135.0
+module GatedSplittedSRAM(
+  input          clock,
+  input          reset,
+  input          io_r_req_valid,
+  input  [10:0]  io_r_req_bits_setIdx,
+  output [547:0] io_r_resp_data_0_data,
+  input          io_w_req_valid,
+  input  [10:0]  io_w_req_bits_setIdx,
+  input  [547:0] io_w_req_bits_data_0_data,
+  input          io_en,
+  input  [11:0]  boreChildrenBd_bore_addr,
+  input  [11:0]  boreChildrenBd_bore_addr_rd,
+  input  [136:0] boreChildrenBd_bore_wdata,
+  input          boreChildrenBd_bore_wmask,
+  input          boreChildrenBd_bore_re,
+  input          boreChildrenBd_bore_we,
+  output [136:0] boreChildrenBd_bore_rdata,
+  input          boreChildrenBd_bore_ack,
+  input          boreChildrenBd_bore_selectedOH,
+  input  [2:0]   boreChildrenBd_bore_array,
+  input  [11:0]  boreChildrenBd_bore_1_addr,
+  input  [11:0]  boreChildrenBd_bore_1_addr_rd,
+  input  [136:0] boreChildrenBd_bore_1_wdata,
+  input          boreChildrenBd_bore_1_wmask,
+  input          boreChildrenBd_bore_1_re,
+  input          boreChildrenBd_bore_1_we,
+  output [136:0] boreChildrenBd_bore_1_rdata,
+  input          boreChildrenBd_bore_1_ack,
+  input          boreChildrenBd_bore_1_selectedOH,
+  input  [3:0]   boreChildrenBd_bore_1_array,
+  input  [11:0]  boreChildrenBd_bore_2_addr,
+  input  [11:0]  boreChildrenBd_bore_2_addr_rd,
+  input  [136:0] boreChildrenBd_bore_2_wdata,
+  input          boreChildrenBd_bore_2_wmask,
+  input          boreChildrenBd_bore_2_re,
+  input          boreChildrenBd_bore_2_we,
+  output [136:0] boreChildrenBd_bore_2_rdata,
+  input          boreChildrenBd_bore_2_ack,
+  input          boreChildrenBd_bore_2_selectedOH,
+  input  [3:0]   boreChildrenBd_bore_2_array,
+  input  [11:0]  boreChildrenBd_bore_3_addr,
+  input  [11:0]  boreChildrenBd_bore_3_addr_rd,
+  input  [136:0] boreChildrenBd_bore_3_wdata,
+  input          boreChildrenBd_bore_3_wmask,
+  input          boreChildrenBd_bore_3_re,
+  input          boreChildrenBd_bore_3_we,
+  output [136:0] boreChildrenBd_bore_3_rdata,
+  input          boreChildrenBd_bore_3_ack,
+  input          boreChildrenBd_bore_3_selectedOH,
+  input  [3:0]   boreChildrenBd_bore_3_array,
+  input          sigFromSrams_bore_ram_hold,
+  input          sigFromSrams_bore_ram_bypass,
+  input          sigFromSrams_bore_ram_bp_clken,
+  input          sigFromSrams_bore_ram_aux_clk,
+  input          sigFromSrams_bore_ram_aux_ckbp,
+  input          sigFromSrams_bore_ram_mcp_hold,
+  input          sigFromSrams_bore_cgen,
+  input          sigFromSrams_bore_1_ram_hold,
+  input          sigFromSrams_bore_1_ram_bypass,
+  input          sigFromSrams_bore_1_ram_bp_clken,
+  input          sigFromSrams_bore_1_ram_aux_clk,
+  input          sigFromSrams_bore_1_ram_aux_ckbp,
+  input          sigFromSrams_bore_1_ram_mcp_hold,
+  input          sigFromSrams_bore_1_cgen,
+  input          sigFromSrams_bore_2_ram_hold,
+  input          sigFromSrams_bore_2_ram_bypass,
+  input          sigFromSrams_bore_2_ram_bp_clken,
+  input          sigFromSrams_bore_2_ram_aux_clk,
+  input          sigFromSrams_bore_2_ram_aux_ckbp,
+  input          sigFromSrams_bore_2_ram_mcp_hold,
+  input          sigFromSrams_bore_2_cgen,
+  input          sigFromSrams_bore_3_ram_hold,
+  input          sigFromSrams_bore_3_ram_bypass,
+  input          sigFromSrams_bore_3_ram_bp_clken,
+  input          sigFromSrams_bore_3_ram_aux_clk,
+  input          sigFromSrams_bore_3_ram_aux_ckbp,
+  input          sigFromSrams_bore_3_ram_mcp_hold,
+  input          sigFromSrams_bore_3_cgen
+);
+
+  wire         _cg_3_out_clock;
+  wire         _cg_2_out_clock;
+  wire         _cg_1_out_clock;
+  wire         _cg_out_clock;
+  wire [136:0] _array_0_0_3_io_r_resp_data_0;
+  wire         _array_0_0_3_io_mbistCgCtl_en;
+  wire         _array_0_0_3_io_mbistCgCtl_rckEn;
+  wire         _array_0_0_3_io_mbistCgCtl_wckEn;
+  wire [136:0] _array_0_0_2_io_r_resp_data_0;
+  wire         _array_0_0_2_io_mbistCgCtl_en;
+  wire         _array_0_0_2_io_mbistCgCtl_rckEn;
+  wire         _array_0_0_2_io_mbistCgCtl_wckEn;
+  wire [136:0] _array_0_0_1_io_r_resp_data_0;
+  wire         _array_0_0_1_io_mbistCgCtl_en;
+  wire         _array_0_0_1_io_mbistCgCtl_rckEn;
+  wire         _array_0_0_1_io_mbistCgCtl_wckEn;
+  wire [136:0] _array_0_0_0_io_r_resp_data_0;
+  wire         _array_0_0_0_io_mbistCgCtl_en;
+  wire         _array_0_0_0_io_mbistCgCtl_rckEn;
+  wire         _array_0_0_0_io_mbistCgCtl_wckEn;
+  SRAMTemplate_246 array_0_0_0 (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_valid                 (io_r_req_valid),
+    .io_r_req_bits_setIdx           (io_r_req_bits_setIdx),
+    .io_r_resp_data_0               (_array_0_0_0_io_r_resp_data_0),
+    .io_w_req_valid                 (io_w_req_valid),
+    .io_w_req_bits_setIdx           (io_w_req_bits_setIdx),
+    .io_w_req_bits_data_0           (io_w_req_bits_data_0_data[136:0]),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_cgen),
+    .io_mbistCgCtl_en               (_array_0_0_0_io_mbistCgCtl_en),
+    .io_mbistCgCtl_rckEn            (_array_0_0_0_io_mbistCgCtl_rckEn),
+    .io_mbistCgCtl_wckEn            (_array_0_0_0_io_mbistCgCtl_wckEn),
+    .io_mbistCgCtl_rclk             (_cg_out_clock),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_array)
+  );
+  SRAMTemplate_247 array_0_0_1 (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_valid                 (io_r_req_valid),
+    .io_r_req_bits_setIdx           (io_r_req_bits_setIdx),
+    .io_r_resp_data_0               (_array_0_0_1_io_r_resp_data_0),
+    .io_w_req_valid                 (io_w_req_valid),
+    .io_w_req_bits_setIdx           (io_w_req_bits_setIdx),
+    .io_w_req_bits_data_0           (io_w_req_bits_data_0_data[273:137]),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_1_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_1_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_1_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_1_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_1_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_1_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_1_cgen),
+    .io_mbistCgCtl_en               (_array_0_0_1_io_mbistCgCtl_en),
+    .io_mbistCgCtl_rckEn            (_array_0_0_1_io_mbistCgCtl_rckEn),
+    .io_mbistCgCtl_wckEn            (_array_0_0_1_io_mbistCgCtl_wckEn),
+    .io_mbistCgCtl_rclk             (_cg_1_out_clock),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_1_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_1_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_1_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_1_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_1_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_1_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_1_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_1_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_1_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_1_array)
+  );
+  SRAMTemplate_247 array_0_0_2 (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_valid                 (io_r_req_valid),
+    .io_r_req_bits_setIdx           (io_r_req_bits_setIdx),
+    .io_r_resp_data_0               (_array_0_0_2_io_r_resp_data_0),
+    .io_w_req_valid                 (io_w_req_valid),
+    .io_w_req_bits_setIdx           (io_w_req_bits_setIdx),
+    .io_w_req_bits_data_0           (io_w_req_bits_data_0_data[410:274]),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_2_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_2_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_2_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_2_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_2_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_2_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_2_cgen),
+    .io_mbistCgCtl_en               (_array_0_0_2_io_mbistCgCtl_en),
+    .io_mbistCgCtl_rckEn            (_array_0_0_2_io_mbistCgCtl_rckEn),
+    .io_mbistCgCtl_wckEn            (_array_0_0_2_io_mbistCgCtl_wckEn),
+    .io_mbistCgCtl_rclk             (_cg_2_out_clock),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_2_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_2_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_2_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_2_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_2_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_2_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_2_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_2_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_2_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_2_array)
+  );
+  SRAMTemplate_247 array_0_0_3 (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_valid                 (io_r_req_valid),
+    .io_r_req_bits_setIdx           (io_r_req_bits_setIdx),
+    .io_r_resp_data_0               (_array_0_0_3_io_r_resp_data_0),
+    .io_w_req_valid                 (io_w_req_valid),
+    .io_w_req_bits_setIdx           (io_w_req_bits_setIdx),
+    .io_w_req_bits_data_0           (io_w_req_bits_data_0_data[547:411]),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_3_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_3_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_3_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_3_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_3_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_3_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_3_cgen),
+    .io_mbistCgCtl_en               (_array_0_0_3_io_mbistCgCtl_en),
+    .io_mbistCgCtl_rckEn            (_array_0_0_3_io_mbistCgCtl_rckEn),
+    .io_mbistCgCtl_wckEn            (_array_0_0_3_io_mbistCgCtl_wckEn),
+    .io_mbistCgCtl_rclk             (_cg_3_out_clock),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_3_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_3_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_3_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_3_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_3_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_3_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_3_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_3_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_3_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_3_array)
+  );
+  MbistClockGateCell_186 cg (
+    .clock            (clock),
+    .mbist_writeen    (_array_0_0_0_io_mbistCgCtl_wckEn),
+    .mbist_readen     (_array_0_0_0_io_mbistCgCtl_rckEn),
+    .mbist_req        (_array_0_0_0_io_mbistCgCtl_en),
+    .E                (io_en),
+    .dft_ram_mcp_hold (sigFromSrams_bore_ram_mcp_hold),
+    .dft_ram_aux_clk  (sigFromSrams_bore_ram_aux_clk),
+    .dft_ram_aux_ckbp (sigFromSrams_bore_ram_aux_ckbp),
+    .dft_cgen         (sigFromSrams_bore_cgen),
+    .out_clock        (_cg_out_clock)
+  );
+  MbistClockGateCell_186 cg_1 (
+    .clock            (clock),
+    .mbist_writeen    (_array_0_0_1_io_mbistCgCtl_wckEn),
+    .mbist_readen     (_array_0_0_1_io_mbistCgCtl_rckEn),
+    .mbist_req        (_array_0_0_1_io_mbistCgCtl_en),
+    .E                (io_en),
+    .dft_ram_mcp_hold (sigFromSrams_bore_1_ram_mcp_hold),
+    .dft_ram_aux_clk  (sigFromSrams_bore_1_ram_aux_clk),
+    .dft_ram_aux_ckbp (sigFromSrams_bore_1_ram_aux_ckbp),
+    .dft_cgen         (sigFromSrams_bore_1_cgen),
+    .out_clock        (_cg_1_out_clock)
+  );
+  MbistClockGateCell_186 cg_2 (
+    .clock            (clock),
+    .mbist_writeen    (_array_0_0_2_io_mbistCgCtl_wckEn),
+    .mbist_readen     (_array_0_0_2_io_mbistCgCtl_rckEn),
+    .mbist_req        (_array_0_0_2_io_mbistCgCtl_en),
+    .E                (io_en),
+    .dft_ram_mcp_hold (sigFromSrams_bore_2_ram_mcp_hold),
+    .dft_ram_aux_clk  (sigFromSrams_bore_2_ram_aux_clk),
+    .dft_ram_aux_ckbp (sigFromSrams_bore_2_ram_aux_ckbp),
+    .dft_cgen         (sigFromSrams_bore_2_cgen),
+    .out_clock        (_cg_2_out_clock)
+  );
+  MbistClockGateCell_186 cg_3 (
+    .clock            (clock),
+    .mbist_writeen    (_array_0_0_3_io_mbistCgCtl_wckEn),
+    .mbist_readen     (_array_0_0_3_io_mbistCgCtl_rckEn),
+    .mbist_req        (_array_0_0_3_io_mbistCgCtl_en),
+    .E                (io_en),
+    .dft_ram_mcp_hold (sigFromSrams_bore_3_ram_mcp_hold),
+    .dft_ram_aux_clk  (sigFromSrams_bore_3_ram_aux_clk),
+    .dft_ram_aux_ckbp (sigFromSrams_bore_3_ram_aux_ckbp),
+    .dft_cgen         (sigFromSrams_bore_3_cgen),
+    .out_clock        (_cg_3_out_clock)
+  );
+  assign io_r_resp_data_0_data =
+    {_array_0_0_3_io_r_resp_data_0,
+     _array_0_0_2_io_r_resp_data_0,
+     _array_0_0_1_io_r_resp_data_0,
+     _array_0_0_0_io_r_resp_data_0};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/GrantBuffer.sv b/flow/designs/src/xiangshan_coupledl2/deps/GrantBuffer.sv
new file mode 100644
index 0000000000..256bca2054
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/GrantBuffer.sv
@@ -0,0 +1,1131 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module GrantBuffer(
+  input          clock,
+  input          reset,
+  input          io_d_task_valid,
+  input  [2:0]   io_d_task_bits_task_channel,
+  input  [2:0]   io_d_task_bits_task_txChannel,
+  input  [7:0]   io_d_task_bits_task_set,
+  input  [33:0]  io_d_task_bits_task_tag,
+  input  [5:0]   io_d_task_bits_task_off,
+  input          io_d_task_bits_task_alias,
+  input  [43:0]  io_d_task_bits_task_vaddr,
+  input          io_d_task_bits_task_isKeyword,
+  input  [3:0]   io_d_task_bits_task_opcode,
+  input  [2:0]   io_d_task_bits_task_param,
+  input  [2:0]   io_d_task_bits_task_size,
+  input  [6:0]   io_d_task_bits_task_sourceId,
+  input  [1:0]   io_d_task_bits_task_bufIdx,
+  input          io_d_task_bits_task_needProbeAckData,
+  input          io_d_task_bits_task_denied,
+  input          io_d_task_bits_task_corrupt,
+  input          io_d_task_bits_task_mshrTask,
+  input  [7:0]   io_d_task_bits_task_mshrId,
+  input          io_d_task_bits_task_aliasTask,
+  input          io_d_task_bits_task_useProbeData,
+  input          io_d_task_bits_task_mshrRetry,
+  input          io_d_task_bits_task_readProbeDataDown,
+  input          io_d_task_bits_task_fromL2pft,
+  input          io_d_task_bits_task_needHint,
+  input          io_d_task_bits_task_dirty,
+  input  [2:0]   io_d_task_bits_task_way,
+  input          io_d_task_bits_task_meta_dirty,
+  input  [1:0]   io_d_task_bits_task_meta_state,
+  input          io_d_task_bits_task_meta_clients,
+  input          io_d_task_bits_task_meta_alias,
+  input          io_d_task_bits_task_meta_prefetch,
+  input  [3:0]   io_d_task_bits_task_meta_prefetchSrc,
+  input          io_d_task_bits_task_meta_accessed,
+  input          io_d_task_bits_task_meta_tagErr,
+  input          io_d_task_bits_task_meta_dataErr,
+  input          io_d_task_bits_task_metaWen,
+  input          io_d_task_bits_task_tagWen,
+  input          io_d_task_bits_task_dsWen,
+  input  [7:0]   io_d_task_bits_task_wayMask,
+  input          io_d_task_bits_task_replTask,
+  input          io_d_task_bits_task_cmoTask,
+  input          io_d_task_bits_task_cmoAll,
+  input  [4:0]   io_d_task_bits_task_reqSource,
+  input          io_d_task_bits_task_mergeA,
+  input  [5:0]   io_d_task_bits_task_aMergeTask_off,
+  input          io_d_task_bits_task_aMergeTask_alias,
+  input  [43:0]  io_d_task_bits_task_aMergeTask_vaddr,
+  input          io_d_task_bits_task_aMergeTask_isKeyword,
+  input  [2:0]   io_d_task_bits_task_aMergeTask_opcode,
+  input  [2:0]   io_d_task_bits_task_aMergeTask_param,
+  input  [6:0]   io_d_task_bits_task_aMergeTask_sourceId,
+  input          io_d_task_bits_task_aMergeTask_meta_dirty,
+  input  [1:0]   io_d_task_bits_task_aMergeTask_meta_state,
+  input          io_d_task_bits_task_aMergeTask_meta_clients,
+  input          io_d_task_bits_task_aMergeTask_meta_alias,
+  input          io_d_task_bits_task_aMergeTask_meta_prefetch,
+  input  [3:0]   io_d_task_bits_task_aMergeTask_meta_prefetchSrc,
+  input          io_d_task_bits_task_aMergeTask_meta_accessed,
+  input          io_d_task_bits_task_aMergeTask_meta_tagErr,
+  input          io_d_task_bits_task_aMergeTask_meta_dataErr,
+  input          io_d_task_bits_task_snpHitRelease,
+  input          io_d_task_bits_task_snpHitReleaseToInval,
+  input          io_d_task_bits_task_snpHitReleaseToClean,
+  input          io_d_task_bits_task_snpHitReleaseWithData,
+  input  [7:0]   io_d_task_bits_task_snpHitReleaseIdx,
+  input          io_d_task_bits_task_snpHitReleaseMeta_dirty,
+  input  [1:0]   io_d_task_bits_task_snpHitReleaseMeta_state,
+  input          io_d_task_bits_task_snpHitReleaseMeta_clients,
+  input          io_d_task_bits_task_snpHitReleaseMeta_alias,
+  input          io_d_task_bits_task_snpHitReleaseMeta_prefetch,
+  input  [3:0]   io_d_task_bits_task_snpHitReleaseMeta_prefetchSrc,
+  input          io_d_task_bits_task_snpHitReleaseMeta_accessed,
+  input          io_d_task_bits_task_snpHitReleaseMeta_tagErr,
+  input          io_d_task_bits_task_snpHitReleaseMeta_dataErr,
+  input  [10:0]  io_d_task_bits_task_tgtID,
+  input  [10:0]  io_d_task_bits_task_srcID,
+  input  [11:0]  io_d_task_bits_task_txnID,
+  input  [10:0]  io_d_task_bits_task_homeNID,
+  input  [11:0]  io_d_task_bits_task_dbID,
+  input  [10:0]  io_d_task_bits_task_fwdNID,
+  input  [11:0]  io_d_task_bits_task_fwdTxnID,
+  input  [6:0]   io_d_task_bits_task_chiOpcode,
+  input  [2:0]   io_d_task_bits_task_resp,
+  input  [2:0]   io_d_task_bits_task_fwdState,
+  input  [3:0]   io_d_task_bits_task_pCrdType,
+  input          io_d_task_bits_task_retToSrc,
+  input          io_d_task_bits_task_likelyshared,
+  input          io_d_task_bits_task_expCompAck,
+  input          io_d_task_bits_task_allowRetry,
+  input          io_d_task_bits_task_memAttr_allocate,
+  input          io_d_task_bits_task_memAttr_cacheable,
+  input          io_d_task_bits_task_memAttr_device,
+  input          io_d_task_bits_task_memAttr_ewa,
+  input          io_d_task_bits_task_traceTag,
+  input  [511:0] io_d_task_bits_data_data,
+  input          io_d_ready,
+  output         io_d_valid,
+  output [3:0]   io_d_bits_opcode,
+  output [1:0]   io_d_bits_param,
+  output [6:0]   io_d_bits_source,
+  output [7:0]   io_d_bits_sink,
+  output         io_d_bits_denied,
+  output         io_d_bits_echo_isKeyword,
+  output [255:0] io_d_bits_data,
+  output         io_d_bits_corrupt,
+  input          io_e_valid,
+  input  [7:0]   io_e_bits_sink,
+  input  [33:0]  io_fromReqArb_status_s1_tags_1,
+  input  [7:0]   io_fromReqArb_status_s1_sets_1,
+  input          io_pipeStatusVec_1_valid,
+  input  [2:0]   io_pipeStatusVec_1_bits_channel,
+  input          io_pipeStatusVec_2_valid,
+  input  [2:0]   io_pipeStatusVec_2_bits_channel,
+  input          io_pipeStatusVec_3_valid,
+  input  [2:0]   io_pipeStatusVec_3_bits_channel,
+  input          io_pipeStatusVec_4_valid,
+  input  [2:0]   io_pipeStatusVec_4_bits_channel,
+  output         io_toReqArb_blockSinkReqEntrance_blockA_s1,
+  output         io_toReqArb_blockSinkReqEntrance_blockB_s1,
+  output         io_toReqArb_blockSinkReqEntrance_blockC_s1,
+  output         io_toReqArb_blockMSHRReqEntrance,
+  input          io_prefetchResp_ready,
+  output         io_prefetchResp_valid,
+  output         io_grantStatus_0_valid,
+  output [7:0]   io_grantStatus_0_set,
+  output [33:0]  io_grantStatus_0_tag,
+  output         io_grantStatus_1_valid,
+  output [7:0]   io_grantStatus_1_set,
+  output [33:0]  io_grantStatus_1_tag,
+  output         io_grantStatus_2_valid,
+  output [7:0]   io_grantStatus_2_set,
+  output [33:0]  io_grantStatus_2_tag,
+  output         io_grantStatus_3_valid,
+  output [7:0]   io_grantStatus_3_set,
+  output [33:0]  io_grantStatus_3_tag,
+  output         io_grantStatus_4_valid,
+  output [7:0]   io_grantStatus_4_set,
+  output [33:0]  io_grantStatus_4_tag,
+  output         io_grantStatus_5_valid,
+  output [7:0]   io_grantStatus_5_set,
+  output [33:0]  io_grantStatus_5_tag,
+  output         io_grantStatus_6_valid,
+  output [7:0]   io_grantStatus_6_set,
+  output [33:0]  io_grantStatus_6_tag,
+  output         io_grantStatus_7_valid,
+  output [7:0]   io_grantStatus_7_set,
+  output [33:0]  io_grantStatus_7_tag,
+  output         io_grantStatus_8_valid,
+  output [7:0]   io_grantStatus_8_set,
+  output [33:0]  io_grantStatus_8_tag,
+  output         io_grantStatus_9_valid,
+  output [7:0]   io_grantStatus_9_set,
+  output [33:0]  io_grantStatus_9_tag,
+  output         io_grantStatus_10_valid,
+  output [7:0]   io_grantStatus_10_set,
+  output [33:0]  io_grantStatus_10_tag,
+  output         io_grantStatus_11_valid,
+  output [7:0]   io_grantStatus_11_set,
+  output [33:0]  io_grantStatus_11_tag,
+  output         io_grantStatus_12_valid,
+  output [7:0]   io_grantStatus_12_set,
+  output [33:0]  io_grantStatus_12_tag,
+  output         io_grantStatus_13_valid,
+  output [7:0]   io_grantStatus_13_set,
+  output [33:0]  io_grantStatus_13_tag,
+  output         io_grantStatus_14_valid,
+  output [7:0]   io_grantStatus_14_set,
+  output [33:0]  io_grantStatus_14_tag,
+  output         io_grantStatus_15_valid,
+  output [7:0]   io_grantStatus_15_set,
+  output [33:0]  io_grantStatus_15_tag
+);
+
+  wire [3:0]   _pftRespQueue_io_count;
+  wire [255:0] _grantQueueData1_io_deq_bits_data_data;
+  wire [255:0] _grantQueueData0_io_deq_bits_data_data;
+  wire         _grantQueue_io_deq_valid;
+  wire         _grantQueue_io_deq_bits_task_isKeyword;
+  wire [3:0]   _grantQueue_io_deq_bits_task_opcode;
+  wire [2:0]   _grantQueue_io_deq_bits_task_param;
+  wire [6:0]   _grantQueue_io_deq_bits_task_sourceId;
+  wire         _grantQueue_io_deq_bits_task_denied;
+  wire         _grantQueue_io_deq_bits_task_corrupt;
+  wire [7:0]   _grantQueue_io_deq_bits_grantid;
+  wire [4:0]   _grantQueue_io_count;
+  reg          inflightGrant_0_valid;
+  reg  [7:0]   inflightGrant_0_bits_set;
+  reg  [33:0]  inflightGrant_0_bits_tag;
+  reg          inflightGrant_1_valid;
+  reg  [7:0]   inflightGrant_1_bits_set;
+  reg  [33:0]  inflightGrant_1_bits_tag;
+  reg          inflightGrant_2_valid;
+  reg  [7:0]   inflightGrant_2_bits_set;
+  reg  [33:0]  inflightGrant_2_bits_tag;
+  reg          inflightGrant_3_valid;
+  reg  [7:0]   inflightGrant_3_bits_set;
+  reg  [33:0]  inflightGrant_3_bits_tag;
+  reg          inflightGrant_4_valid;
+  reg  [7:0]   inflightGrant_4_bits_set;
+  reg  [33:0]  inflightGrant_4_bits_tag;
+  reg          inflightGrant_5_valid;
+  reg  [7:0]   inflightGrant_5_bits_set;
+  reg  [33:0]  inflightGrant_5_bits_tag;
+  reg          inflightGrant_6_valid;
+  reg  [7:0]   inflightGrant_6_bits_set;
+  reg  [33:0]  inflightGrant_6_bits_tag;
+  reg          inflightGrant_7_valid;
+  reg  [7:0]   inflightGrant_7_bits_set;
+  reg  [33:0]  inflightGrant_7_bits_tag;
+  reg          inflightGrant_8_valid;
+  reg  [7:0]   inflightGrant_8_bits_set;
+  reg  [33:0]  inflightGrant_8_bits_tag;
+  reg          inflightGrant_9_valid;
+  reg  [7:0]   inflightGrant_9_bits_set;
+  reg  [33:0]  inflightGrant_9_bits_tag;
+  reg          inflightGrant_10_valid;
+  reg  [7:0]   inflightGrant_10_bits_set;
+  reg  [33:0]  inflightGrant_10_bits_tag;
+  reg          inflightGrant_11_valid;
+  reg  [7:0]   inflightGrant_11_bits_set;
+  reg  [33:0]  inflightGrant_11_bits_tag;
+  reg          inflightGrant_12_valid;
+  reg  [7:0]   inflightGrant_12_bits_set;
+  reg  [33:0]  inflightGrant_12_bits_tag;
+  reg          inflightGrant_13_valid;
+  reg  [7:0]   inflightGrant_13_bits_set;
+  reg  [33:0]  inflightGrant_13_bits_tag;
+  reg          inflightGrant_14_valid;
+  reg  [7:0]   inflightGrant_14_bits_set;
+  reg  [33:0]  inflightGrant_14_bits_tag;
+  reg          inflightGrant_15_valid;
+  reg  [7:0]   inflightGrant_15_bits_set;
+  reg  [33:0]  inflightGrant_15_bits_tag;
+  wire [3:0]   inflight_insertIdx =
+    inflightGrant_0_valid
+      ? (inflightGrant_1_valid
+           ? (inflightGrant_2_valid
+                ? (inflightGrant_3_valid
+                     ? (inflightGrant_4_valid
+                          ? (inflightGrant_5_valid
+                               ? (inflightGrant_6_valid
+                                    ? (inflightGrant_7_valid
+                                         ? (inflightGrant_8_valid
+                                              ? (inflightGrant_9_valid
+                                                   ? (inflightGrant_10_valid
+                                                        ? (inflightGrant_11_valid
+                                                             ? (inflightGrant_12_valid
+                                                                  ? (inflightGrant_13_valid
+                                                                       ? {3'h7,
+                                                                          inflightGrant_14_valid}
+                                                                       : 4'hD)
+                                                                  : 4'hC)
+                                                             : 4'hB)
+                                                        : 4'hA)
+                                                   : 4'h9)
+                                              : 4'h8)
+                                         : 4'h7)
+                                    : 4'h6)
+                               : 4'h5)
+                          : 4'h4)
+                     : 4'h3)
+                : 4'h2)
+           : 4'h1)
+      : 4'h0;
+  wire         grantQueue_io_enq_valid =
+    io_d_task_valid & (io_d_task_bits_task_opcode != 4'h2 | io_d_task_bits_task_mergeA);
+  reg          grantBufValid;
+  reg          grantBuf_task_isKeyword;
+  reg  [3:0]   grantBuf_task_opcode;
+  reg  [2:0]   grantBuf_task_param;
+  reg  [6:0]   grantBuf_task_sourceId;
+  reg          grantBuf_task_denied;
+  reg          grantBuf_task_corrupt;
+  reg  [255:0] grantBuf_data_data;
+  reg  [7:0]   grantBuf_grantid;
+  wire         grantQueue_io_deq_ready = io_d_ready & ~grantBufValid;
+  wire [4:0]   _noSpaceForSinkReq_T_27 =
+    5'({2'h0,
+        3'({1'h0,
+            2'({1'h0,
+                io_pipeStatusVec_1_valid
+                  & (io_pipeStatusVec_1_bits_channel[0]
+                     | io_pipeStatusVec_1_bits_channel[2])}
+               + {1'h0,
+                  io_pipeStatusVec_2_valid
+                    & (io_pipeStatusVec_2_bits_channel[0]
+                       | io_pipeStatusVec_2_bits_channel[2])})}
+           + {1'h0,
+              2'({1'h0,
+                  io_pipeStatusVec_3_valid
+                    & (io_pipeStatusVec_3_bits_channel[0]
+                       | io_pipeStatusVec_3_bits_channel[2])}
+                 + {1'h0,
+                    io_pipeStatusVec_4_valid
+                      & (io_pipeStatusVec_4_bits_channel[0]
+                         | io_pipeStatusVec_4_bits_channel[2])})})}
+       + _grantQueue_io_count);
+  wire [1:0]   _GEN = {1'h0, inflightGrant_0_valid};
+  wire [1:0]   _GEN_0 = {1'h0, inflightGrant_1_valid};
+  wire [1:0]   _GEN_1 = {1'h0, inflightGrant_2_valid};
+  wire [1:0]   _GEN_2 = {1'h0, inflightGrant_3_valid};
+  wire [1:0]   _GEN_3 = {1'h0, inflightGrant_4_valid};
+  wire [1:0]   _GEN_4 = {1'h0, inflightGrant_5_valid};
+  wire [1:0]   _GEN_5 = {1'h0, inflightGrant_6_valid};
+  wire [1:0]   _GEN_6 = {1'h0, inflightGrant_7_valid};
+  wire [1:0]   _GEN_7 = {1'h0, inflightGrant_8_valid};
+  wire [1:0]   _GEN_8 = {1'h0, inflightGrant_9_valid};
+  wire [1:0]   _GEN_9 = {1'h0, inflightGrant_10_valid};
+  wire [1:0]   _GEN_10 = {1'h0, inflightGrant_11_valid};
+  wire [1:0]   _GEN_11 = {1'h0, inflightGrant_12_valid};
+  wire [1:0]   _GEN_12 = {1'h0, inflightGrant_13_valid};
+  wire [1:0]   _GEN_13 = {1'h0, inflightGrant_14_valid};
+  wire [1:0]   _GEN_14 = {1'h0, inflightGrant_15_valid};
+  wire [4:0]   _noSpaceWaitSinkEForSinkReq_T_49 =
+    5'({2'h0,
+        3'({1'h0,
+            2'({1'h0, io_pipeStatusVec_1_valid & io_pipeStatusVec_1_bits_channel[0]}
+               + {1'h0, io_pipeStatusVec_2_valid & io_pipeStatusVec_2_bits_channel[0]})}
+           + {1'h0,
+              2'({1'h0, io_pipeStatusVec_3_valid & io_pipeStatusVec_3_bits_channel[0]}
+                 + {1'h0,
+                    io_pipeStatusVec_4_valid & io_pipeStatusVec_4_bits_channel[0]})})}
+       + 5'({1'h0,
+             4'({1'h0, 3'({1'h0, 2'(_GEN + _GEN_0)} + {1'h0, 2'(_GEN_1 + _GEN_2)})}
+                + {1'h0, 3'({1'h0, 2'(_GEN_3 + _GEN_4)} + {1'h0, 2'(_GEN_5 + _GEN_6)})})}
+            + {1'h0,
+               4'({1'h0, 3'({1'h0, 2'(_GEN_7 + _GEN_8)} + {1'h0, 2'(_GEN_9 + _GEN_10)})}
+                  + {1'h0,
+                     3'({1'h0, 2'(_GEN_11 + _GEN_12)}
+                        + {1'h0, 2'(_GEN_13 + _GEN_14)})})}));
+  wire         _GEN_15 =
+    _grantQueue_io_deq_valid & io_d_ready & ~grantBufValid
+    & _grantQueue_io_deq_bits_task_opcode[0];
+  wire         _GEN_16 =
+    io_d_task_valid
+    & (io_d_task_bits_task_opcode == 4'h4 | io_d_task_bits_task_opcode == 4'h5
+       | io_d_task_bits_task_mergeA);
+  wire         _GEN_17 = _GEN_16 & inflight_insertIdx == 4'h0;
+  wire         _GEN_18 = _GEN_16 & inflight_insertIdx == 4'h1;
+  wire         _GEN_19 = _GEN_16 & inflight_insertIdx == 4'h2;
+  wire         _GEN_20 = _GEN_16 & inflight_insertIdx == 4'h3;
+  wire         _GEN_21 = _GEN_16 & inflight_insertIdx == 4'h4;
+  wire         _GEN_22 = _GEN_16 & inflight_insertIdx == 4'h5;
+  wire         _GEN_23 = _GEN_16 & inflight_insertIdx == 4'h6;
+  wire         _GEN_24 = _GEN_16 & inflight_insertIdx == 4'h7;
+  wire         _GEN_25 = _GEN_16 & inflight_insertIdx == 4'h8;
+  wire         _GEN_26 = _GEN_16 & inflight_insertIdx == 4'h9;
+  wire         _GEN_27 = _GEN_16 & inflight_insertIdx == 4'hA;
+  wire         _GEN_28 = _GEN_16 & inflight_insertIdx == 4'hB;
+  wire         _GEN_29 = _GEN_16 & inflight_insertIdx == 4'hC;
+  wire         _GEN_30 = _GEN_16 & inflight_insertIdx == 4'hD;
+  wire         _GEN_31 = _GEN_16 & inflight_insertIdx == 4'hE;
+  wire         _GEN_32 = _GEN_16 & (&inflight_insertIdx);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      inflightGrant_0_valid <= 1'h0;
+      inflightGrant_0_bits_set <= 8'h0;
+      inflightGrant_0_bits_tag <= 34'h0;
+      inflightGrant_1_valid <= 1'h0;
+      inflightGrant_1_bits_set <= 8'h0;
+      inflightGrant_1_bits_tag <= 34'h0;
+      inflightGrant_2_valid <= 1'h0;
+      inflightGrant_2_bits_set <= 8'h0;
+      inflightGrant_2_bits_tag <= 34'h0;
+      inflightGrant_3_valid <= 1'h0;
+      inflightGrant_3_bits_set <= 8'h0;
+      inflightGrant_3_bits_tag <= 34'h0;
+      inflightGrant_4_valid <= 1'h0;
+      inflightGrant_4_bits_set <= 8'h0;
+      inflightGrant_4_bits_tag <= 34'h0;
+      inflightGrant_5_valid <= 1'h0;
+      inflightGrant_5_bits_set <= 8'h0;
+      inflightGrant_5_bits_tag <= 34'h0;
+      inflightGrant_6_valid <= 1'h0;
+      inflightGrant_6_bits_set <= 8'h0;
+      inflightGrant_6_bits_tag <= 34'h0;
+      inflightGrant_7_valid <= 1'h0;
+      inflightGrant_7_bits_set <= 8'h0;
+      inflightGrant_7_bits_tag <= 34'h0;
+      inflightGrant_8_valid <= 1'h0;
+      inflightGrant_8_bits_set <= 8'h0;
+      inflightGrant_8_bits_tag <= 34'h0;
+      inflightGrant_9_valid <= 1'h0;
+      inflightGrant_9_bits_set <= 8'h0;
+      inflightGrant_9_bits_tag <= 34'h0;
+      inflightGrant_10_valid <= 1'h0;
+      inflightGrant_10_bits_set <= 8'h0;
+      inflightGrant_10_bits_tag <= 34'h0;
+      inflightGrant_11_valid <= 1'h0;
+      inflightGrant_11_bits_set <= 8'h0;
+      inflightGrant_11_bits_tag <= 34'h0;
+      inflightGrant_12_valid <= 1'h0;
+      inflightGrant_12_bits_set <= 8'h0;
+      inflightGrant_12_bits_tag <= 34'h0;
+      inflightGrant_13_valid <= 1'h0;
+      inflightGrant_13_bits_set <= 8'h0;
+      inflightGrant_13_bits_tag <= 34'h0;
+      inflightGrant_14_valid <= 1'h0;
+      inflightGrant_14_bits_set <= 8'h0;
+      inflightGrant_14_bits_tag <= 34'h0;
+      inflightGrant_15_valid <= 1'h0;
+      inflightGrant_15_bits_set <= 8'h0;
+      inflightGrant_15_bits_tag <= 34'h0;
+      grantBufValid <= 1'h0;
+      grantBuf_task_isKeyword <= 1'h0;
+      grantBuf_task_opcode <= 4'h0;
+      grantBuf_task_param <= 3'h0;
+      grantBuf_task_sourceId <= 7'h0;
+      grantBuf_task_denied <= 1'h0;
+      grantBuf_task_corrupt <= 1'h0;
+      grantBuf_data_data <= 256'h0;
+      grantBuf_grantid <= 8'h0;
+    end
+    else begin
+      inflightGrant_0_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h0) & (_GEN_17 | inflightGrant_0_valid);
+      if (_GEN_17) begin
+        inflightGrant_0_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_0_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_1_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h1) & (_GEN_18 | inflightGrant_1_valid);
+      if (_GEN_18) begin
+        inflightGrant_1_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_1_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_2_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h2) & (_GEN_19 | inflightGrant_2_valid);
+      if (_GEN_19) begin
+        inflightGrant_2_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_2_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_3_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h3) & (_GEN_20 | inflightGrant_3_valid);
+      if (_GEN_20) begin
+        inflightGrant_3_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_3_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_4_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h4) & (_GEN_21 | inflightGrant_4_valid);
+      if (_GEN_21) begin
+        inflightGrant_4_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_4_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_5_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h5) & (_GEN_22 | inflightGrant_5_valid);
+      if (_GEN_22) begin
+        inflightGrant_5_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_5_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_6_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h6) & (_GEN_23 | inflightGrant_6_valid);
+      if (_GEN_23) begin
+        inflightGrant_6_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_6_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_7_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h7) & (_GEN_24 | inflightGrant_7_valid);
+      if (_GEN_24) begin
+        inflightGrant_7_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_7_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_8_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h8) & (_GEN_25 | inflightGrant_8_valid);
+      if (_GEN_25) begin
+        inflightGrant_8_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_8_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_9_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'h9) & (_GEN_26 | inflightGrant_9_valid);
+      if (_GEN_26) begin
+        inflightGrant_9_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_9_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_10_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'hA) & (_GEN_27 | inflightGrant_10_valid);
+      if (_GEN_27) begin
+        inflightGrant_10_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_10_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_11_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'hB) & (_GEN_28 | inflightGrant_11_valid);
+      if (_GEN_28) begin
+        inflightGrant_11_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_11_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_12_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'hC) & (_GEN_29 | inflightGrant_12_valid);
+      if (_GEN_29) begin
+        inflightGrant_12_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_12_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_13_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'hD) & (_GEN_30 | inflightGrant_13_valid);
+      if (_GEN_30) begin
+        inflightGrant_13_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_13_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_14_valid <=
+        ~(io_e_valid & io_e_bits_sink[3:0] == 4'hE) & (_GEN_31 | inflightGrant_14_valid);
+      if (_GEN_31) begin
+        inflightGrant_14_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_14_bits_tag <= io_d_task_bits_task_tag;
+      end
+      inflightGrant_15_valid <=
+        ~(io_e_valid & (&(io_e_bits_sink[3:0]))) & (_GEN_32 | inflightGrant_15_valid);
+      if (_GEN_32) begin
+        inflightGrant_15_bits_set <= io_d_task_bits_task_set;
+        inflightGrant_15_bits_tag <= io_d_task_bits_task_tag;
+      end
+      grantBufValid <= ~(grantBufValid & io_d_ready) & (_GEN_15 | grantBufValid);
+      if (_GEN_15) begin
+        grantBuf_task_isKeyword <= _grantQueue_io_deq_bits_task_isKeyword;
+        grantBuf_task_opcode <= _grantQueue_io_deq_bits_task_opcode;
+        grantBuf_task_param <= _grantQueue_io_deq_bits_task_param;
+        grantBuf_task_sourceId <= _grantQueue_io_deq_bits_task_sourceId;
+        grantBuf_task_denied <= _grantQueue_io_deq_bits_task_denied;
+        grantBuf_task_corrupt <= _grantQueue_io_deq_bits_task_corrupt;
+        grantBuf_data_data <=
+          _grantQueue_io_deq_bits_task_isKeyword
+            ? _grantQueueData0_io_deq_bits_data_data
+            : _grantQueueData1_io_deq_bits_data_data;
+        grantBuf_grantid <= _grantQueue_io_deq_bits_grantid;
+      end
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:41];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [5:0] i = 6'h0; i < 6'h2A; i += 6'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        inflightGrant_0_valid = _RANDOM[6'h0][0];
+        inflightGrant_0_bits_set = _RANDOM[6'h0][8:1];
+        inflightGrant_0_bits_tag = {_RANDOM[6'h0][31:9], _RANDOM[6'h1][10:0]};
+        inflightGrant_1_valid = _RANDOM[6'h1][11];
+        inflightGrant_1_bits_set = _RANDOM[6'h1][19:12];
+        inflightGrant_1_bits_tag = {_RANDOM[6'h1][31:20], _RANDOM[6'h2][21:0]};
+        inflightGrant_2_valid = _RANDOM[6'h2][22];
+        inflightGrant_2_bits_set = _RANDOM[6'h2][30:23];
+        inflightGrant_2_bits_tag = {_RANDOM[6'h2][31], _RANDOM[6'h3], _RANDOM[6'h4][0]};
+        inflightGrant_3_valid = _RANDOM[6'h4][1];
+        inflightGrant_3_bits_set = _RANDOM[6'h4][9:2];
+        inflightGrant_3_bits_tag = {_RANDOM[6'h4][31:10], _RANDOM[6'h5][11:0]};
+        inflightGrant_4_valid = _RANDOM[6'h5][12];
+        inflightGrant_4_bits_set = _RANDOM[6'h5][20:13];
+        inflightGrant_4_bits_tag = {_RANDOM[6'h5][31:21], _RANDOM[6'h6][22:0]};
+        inflightGrant_5_valid = _RANDOM[6'h6][23];
+        inflightGrant_5_bits_set = _RANDOM[6'h6][31:24];
+        inflightGrant_5_bits_tag = {_RANDOM[6'h7], _RANDOM[6'h8][1:0]};
+        inflightGrant_6_valid = _RANDOM[6'h8][2];
+        inflightGrant_6_bits_set = _RANDOM[6'h8][10:3];
+        inflightGrant_6_bits_tag = {_RANDOM[6'h8][31:11], _RANDOM[6'h9][12:0]};
+        inflightGrant_7_valid = _RANDOM[6'h9][13];
+        inflightGrant_7_bits_set = _RANDOM[6'h9][21:14];
+        inflightGrant_7_bits_tag = {_RANDOM[6'h9][31:22], _RANDOM[6'hA][23:0]};
+        inflightGrant_8_valid = _RANDOM[6'hA][24];
+        inflightGrant_8_bits_set = {_RANDOM[6'hA][31:25], _RANDOM[6'hB][0]};
+        inflightGrant_8_bits_tag = {_RANDOM[6'hB][31:1], _RANDOM[6'hC][2:0]};
+        inflightGrant_9_valid = _RANDOM[6'hC][3];
+        inflightGrant_9_bits_set = _RANDOM[6'hC][11:4];
+        inflightGrant_9_bits_tag = {_RANDOM[6'hC][31:12], _RANDOM[6'hD][13:0]};
+        inflightGrant_10_valid = _RANDOM[6'hD][14];
+        inflightGrant_10_bits_set = _RANDOM[6'hD][22:15];
+        inflightGrant_10_bits_tag = {_RANDOM[6'hD][31:23], _RANDOM[6'hE][24:0]};
+        inflightGrant_11_valid = _RANDOM[6'hE][25];
+        inflightGrant_11_bits_set = {_RANDOM[6'hE][31:26], _RANDOM[6'hF][1:0]};
+        inflightGrant_11_bits_tag = {_RANDOM[6'hF][31:2], _RANDOM[6'h10][3:0]};
+        inflightGrant_12_valid = _RANDOM[6'h10][4];
+        inflightGrant_12_bits_set = _RANDOM[6'h10][12:5];
+        inflightGrant_12_bits_tag = {_RANDOM[6'h10][31:13], _RANDOM[6'h11][14:0]};
+        inflightGrant_13_valid = _RANDOM[6'h11][15];
+        inflightGrant_13_bits_set = _RANDOM[6'h11][23:16];
+        inflightGrant_13_bits_tag = {_RANDOM[6'h11][31:24], _RANDOM[6'h12][25:0]};
+        inflightGrant_14_valid = _RANDOM[6'h12][26];
+        inflightGrant_14_bits_set = {_RANDOM[6'h12][31:27], _RANDOM[6'h13][2:0]};
+        inflightGrant_14_bits_tag = {_RANDOM[6'h13][31:3], _RANDOM[6'h14][4:0]};
+        inflightGrant_15_valid = _RANDOM[6'h14][5];
+        inflightGrant_15_bits_set = _RANDOM[6'h14][13:6];
+        inflightGrant_15_bits_tag = {_RANDOM[6'h14][31:14], _RANDOM[6'h15][15:0]};
+        grantBufValid = _RANDOM[6'h15][16];
+        grantBuf_task_isKeyword = _RANDOM[6'h18][20];
+        grantBuf_task_opcode = _RANDOM[6'h18][24:21];
+        grantBuf_task_param = _RANDOM[6'h18][27:25];
+        grantBuf_task_sourceId = {_RANDOM[6'h18][31], _RANDOM[6'h19][5:0]};
+        grantBuf_task_denied = _RANDOM[6'h19][9];
+        grantBuf_task_corrupt = _RANDOM[6'h19][10];
+        grantBuf_data_data =
+          {_RANDOM[6'h21][31:16],
+           _RANDOM[6'h22],
+           _RANDOM[6'h23],
+           _RANDOM[6'h24],
+           _RANDOM[6'h25],
+           _RANDOM[6'h26],
+           _RANDOM[6'h27],
+           _RANDOM[6'h28],
+           _RANDOM[6'h29][15:0]};
+        grantBuf_grantid = _RANDOM[6'h29][23:16];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        inflightGrant_0_valid = 1'h0;
+        inflightGrant_0_bits_set = 8'h0;
+        inflightGrant_0_bits_tag = 34'h0;
+        inflightGrant_1_valid = 1'h0;
+        inflightGrant_1_bits_set = 8'h0;
+        inflightGrant_1_bits_tag = 34'h0;
+        inflightGrant_2_valid = 1'h0;
+        inflightGrant_2_bits_set = 8'h0;
+        inflightGrant_2_bits_tag = 34'h0;
+        inflightGrant_3_valid = 1'h0;
+        inflightGrant_3_bits_set = 8'h0;
+        inflightGrant_3_bits_tag = 34'h0;
+        inflightGrant_4_valid = 1'h0;
+        inflightGrant_4_bits_set = 8'h0;
+        inflightGrant_4_bits_tag = 34'h0;
+        inflightGrant_5_valid = 1'h0;
+        inflightGrant_5_bits_set = 8'h0;
+        inflightGrant_5_bits_tag = 34'h0;
+        inflightGrant_6_valid = 1'h0;
+        inflightGrant_6_bits_set = 8'h0;
+        inflightGrant_6_bits_tag = 34'h0;
+        inflightGrant_7_valid = 1'h0;
+        inflightGrant_7_bits_set = 8'h0;
+        inflightGrant_7_bits_tag = 34'h0;
+        inflightGrant_8_valid = 1'h0;
+        inflightGrant_8_bits_set = 8'h0;
+        inflightGrant_8_bits_tag = 34'h0;
+        inflightGrant_9_valid = 1'h0;
+        inflightGrant_9_bits_set = 8'h0;
+        inflightGrant_9_bits_tag = 34'h0;
+        inflightGrant_10_valid = 1'h0;
+        inflightGrant_10_bits_set = 8'h0;
+        inflightGrant_10_bits_tag = 34'h0;
+        inflightGrant_11_valid = 1'h0;
+        inflightGrant_11_bits_set = 8'h0;
+        inflightGrant_11_bits_tag = 34'h0;
+        inflightGrant_12_valid = 1'h0;
+        inflightGrant_12_bits_set = 8'h0;
+        inflightGrant_12_bits_tag = 34'h0;
+        inflightGrant_13_valid = 1'h0;
+        inflightGrant_13_bits_set = 8'h0;
+        inflightGrant_13_bits_tag = 34'h0;
+        inflightGrant_14_valid = 1'h0;
+        inflightGrant_14_bits_set = 8'h0;
+        inflightGrant_14_bits_tag = 34'h0;
+        inflightGrant_15_valid = 1'h0;
+        inflightGrant_15_bits_set = 8'h0;
+        inflightGrant_15_bits_tag = 34'h0;
+        grantBufValid = 1'h0;
+        grantBuf_task_isKeyword = 1'h0;
+        grantBuf_task_opcode = 4'h0;
+        grantBuf_task_param = 3'h0;
+        grantBuf_task_sourceId = 7'h0;
+        grantBuf_task_denied = 1'h0;
+        grantBuf_task_corrupt = 1'h0;
+        grantBuf_data_data = 256'h0;
+        grantBuf_grantid = 8'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  Queue16_GrantQueueTask grantQueue (
+    .clock                                          (clock),
+    .reset                                          (reset),
+    .io_enq_valid                                   (grantQueue_io_enq_valid),
+    .io_enq_bits_task_channel                       (io_d_task_bits_task_channel),
+    .io_enq_bits_task_txChannel                     (io_d_task_bits_task_txChannel),
+    .io_enq_bits_task_set                           (io_d_task_bits_task_set),
+    .io_enq_bits_task_tag                           (io_d_task_bits_task_tag),
+    .io_enq_bits_task_off
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_off
+         : io_d_task_bits_task_off),
+    .io_enq_bits_task_alias
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_alias
+         : io_d_task_bits_task_alias),
+    .io_enq_bits_task_vaddr                         (io_d_task_bits_task_vaddr),
+    .io_enq_bits_task_isKeyword
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_isKeyword
+         : io_d_task_bits_task_isKeyword),
+    .io_enq_bits_task_opcode
+      (io_d_task_bits_task_mergeA
+         ? {1'h0, io_d_task_bits_task_aMergeTask_opcode}
+         : io_d_task_bits_task_opcode),
+    .io_enq_bits_task_param
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_param
+         : io_d_task_bits_task_param),
+    .io_enq_bits_task_size                          (io_d_task_bits_task_size),
+    .io_enq_bits_task_sourceId
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_sourceId
+         : io_d_task_bits_task_sourceId),
+    .io_enq_bits_task_bufIdx                        (io_d_task_bits_task_bufIdx),
+    .io_enq_bits_task_needProbeAckData
+      (io_d_task_bits_task_needProbeAckData),
+    .io_enq_bits_task_denied                        (io_d_task_bits_task_denied),
+    .io_enq_bits_task_corrupt
+      (io_d_task_bits_task_mergeA & io_d_task_bits_task_denied
+       | io_d_task_bits_task_corrupt),
+    .io_enq_bits_task_mshrTask                      (io_d_task_bits_task_mshrTask),
+    .io_enq_bits_task_mshrId                        (io_d_task_bits_task_mshrId),
+    .io_enq_bits_task_aliasTask                     (io_d_task_bits_task_aliasTask),
+    .io_enq_bits_task_useProbeData
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_useProbeData),
+    .io_enq_bits_task_mshrRetry
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_mshrRetry),
+    .io_enq_bits_task_readProbeDataDown
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_readProbeDataDown),
+    .io_enq_bits_task_fromL2pft
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_fromL2pft),
+    .io_enq_bits_task_needHint
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_needHint),
+    .io_enq_bits_task_dirty                         (io_d_task_bits_task_dirty),
+    .io_enq_bits_task_way                           (io_d_task_bits_task_way),
+    .io_enq_bits_task_meta_dirty
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_meta_dirty
+         : io_d_task_bits_task_meta_dirty),
+    .io_enq_bits_task_meta_state
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_meta_state
+         : io_d_task_bits_task_meta_state),
+    .io_enq_bits_task_meta_clients
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_meta_clients
+         : io_d_task_bits_task_meta_clients),
+    .io_enq_bits_task_meta_alias
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_meta_alias
+         : io_d_task_bits_task_meta_alias),
+    .io_enq_bits_task_meta_prefetch
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_meta_prefetch
+         : io_d_task_bits_task_meta_prefetch),
+    .io_enq_bits_task_meta_prefetchSrc
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_meta_prefetchSrc
+         : io_d_task_bits_task_meta_prefetchSrc),
+    .io_enq_bits_task_meta_accessed
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_meta_accessed
+         : io_d_task_bits_task_meta_accessed),
+    .io_enq_bits_task_meta_tagErr
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_meta_tagErr
+         : io_d_task_bits_task_meta_tagErr),
+    .io_enq_bits_task_meta_dataErr
+      (io_d_task_bits_task_mergeA
+         ? io_d_task_bits_task_aMergeTask_meta_dataErr
+         : io_d_task_bits_task_meta_dataErr),
+    .io_enq_bits_task_metaWen                       (io_d_task_bits_task_metaWen),
+    .io_enq_bits_task_tagWen                        (io_d_task_bits_task_tagWen),
+    .io_enq_bits_task_dsWen                         (io_d_task_bits_task_dsWen),
+    .io_enq_bits_task_wayMask                       (io_d_task_bits_task_wayMask),
+    .io_enq_bits_task_replTask                      (io_d_task_bits_task_replTask),
+    .io_enq_bits_task_cmoTask
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_cmoTask),
+    .io_enq_bits_task_cmoAll
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_cmoAll),
+    .io_enq_bits_task_reqSource                     (io_d_task_bits_task_reqSource),
+    .io_enq_bits_task_mergeA                        (1'h0),
+    .io_enq_bits_task_aMergeTask_off
+      (io_d_task_bits_task_mergeA ? 6'h0 : io_d_task_bits_task_aMergeTask_off),
+    .io_enq_bits_task_aMergeTask_alias
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_aMergeTask_alias),
+    .io_enq_bits_task_aMergeTask_vaddr
+      (io_d_task_bits_task_mergeA ? 44'h0 : io_d_task_bits_task_aMergeTask_vaddr),
+    .io_enq_bits_task_aMergeTask_isKeyword
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_aMergeTask_isKeyword),
+    .io_enq_bits_task_aMergeTask_opcode
+      (io_d_task_bits_task_mergeA ? 3'h0 : io_d_task_bits_task_aMergeTask_opcode),
+    .io_enq_bits_task_aMergeTask_param
+      (io_d_task_bits_task_mergeA ? 3'h0 : io_d_task_bits_task_aMergeTask_param),
+    .io_enq_bits_task_aMergeTask_sourceId
+      (io_d_task_bits_task_mergeA ? 7'h0 : io_d_task_bits_task_aMergeTask_sourceId),
+    .io_enq_bits_task_aMergeTask_meta_dirty
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_aMergeTask_meta_dirty),
+    .io_enq_bits_task_aMergeTask_meta_state
+      (io_d_task_bits_task_mergeA ? 2'h0 : io_d_task_bits_task_aMergeTask_meta_state),
+    .io_enq_bits_task_aMergeTask_meta_clients
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_aMergeTask_meta_clients),
+    .io_enq_bits_task_aMergeTask_meta_alias
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_aMergeTask_meta_alias),
+    .io_enq_bits_task_aMergeTask_meta_prefetch
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_aMergeTask_meta_prefetch),
+    .io_enq_bits_task_aMergeTask_meta_prefetchSrc
+      (io_d_task_bits_task_mergeA
+         ? 4'h0
+         : io_d_task_bits_task_aMergeTask_meta_prefetchSrc),
+    .io_enq_bits_task_aMergeTask_meta_accessed
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_aMergeTask_meta_accessed),
+    .io_enq_bits_task_aMergeTask_meta_tagErr
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_aMergeTask_meta_tagErr),
+    .io_enq_bits_task_aMergeTask_meta_dataErr
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_aMergeTask_meta_dataErr),
+    .io_enq_bits_task_snpHitRelease
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitRelease),
+    .io_enq_bits_task_snpHitReleaseToInval
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseToInval),
+    .io_enq_bits_task_snpHitReleaseToClean
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseToClean),
+    .io_enq_bits_task_snpHitReleaseWithData
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseWithData),
+    .io_enq_bits_task_snpHitReleaseIdx
+      (io_d_task_bits_task_mergeA ? 8'h0 : io_d_task_bits_task_snpHitReleaseIdx),
+    .io_enq_bits_task_snpHitReleaseMeta_dirty
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseMeta_dirty),
+    .io_enq_bits_task_snpHitReleaseMeta_state
+      (io_d_task_bits_task_mergeA ? 2'h0 : io_d_task_bits_task_snpHitReleaseMeta_state),
+    .io_enq_bits_task_snpHitReleaseMeta_clients
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseMeta_clients),
+    .io_enq_bits_task_snpHitReleaseMeta_alias
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseMeta_alias),
+    .io_enq_bits_task_snpHitReleaseMeta_prefetch
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseMeta_prefetch),
+    .io_enq_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_d_task_bits_task_mergeA
+         ? 4'h0
+         : io_d_task_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_enq_bits_task_snpHitReleaseMeta_accessed
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseMeta_accessed),
+    .io_enq_bits_task_snpHitReleaseMeta_tagErr
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseMeta_tagErr),
+    .io_enq_bits_task_snpHitReleaseMeta_dataErr
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_snpHitReleaseMeta_dataErr),
+    .io_enq_bits_task_tgtID
+      (io_d_task_bits_task_mergeA ? 11'h0 : io_d_task_bits_task_tgtID),
+    .io_enq_bits_task_srcID
+      (io_d_task_bits_task_mergeA ? 11'h0 : io_d_task_bits_task_srcID),
+    .io_enq_bits_task_txnID
+      (io_d_task_bits_task_mergeA ? 12'h0 : io_d_task_bits_task_txnID),
+    .io_enq_bits_task_homeNID
+      (io_d_task_bits_task_mergeA ? 11'h0 : io_d_task_bits_task_homeNID),
+    .io_enq_bits_task_dbID
+      (io_d_task_bits_task_mergeA ? 12'h0 : io_d_task_bits_task_dbID),
+    .io_enq_bits_task_fwdNID
+      (io_d_task_bits_task_mergeA ? 11'h0 : io_d_task_bits_task_fwdNID),
+    .io_enq_bits_task_fwdTxnID
+      (io_d_task_bits_task_mergeA ? 12'h0 : io_d_task_bits_task_fwdTxnID),
+    .io_enq_bits_task_chiOpcode
+      (io_d_task_bits_task_mergeA ? 7'h0 : io_d_task_bits_task_chiOpcode),
+    .io_enq_bits_task_resp
+      (io_d_task_bits_task_mergeA ? 3'h0 : io_d_task_bits_task_resp),
+    .io_enq_bits_task_fwdState
+      (io_d_task_bits_task_mergeA ? 3'h0 : io_d_task_bits_task_fwdState),
+    .io_enq_bits_task_pCrdType
+      (io_d_task_bits_task_mergeA ? 4'h0 : io_d_task_bits_task_pCrdType),
+    .io_enq_bits_task_retToSrc
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_retToSrc),
+    .io_enq_bits_task_likelyshared
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_likelyshared),
+    .io_enq_bits_task_expCompAck
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_expCompAck),
+    .io_enq_bits_task_allowRetry
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_allowRetry),
+    .io_enq_bits_task_memAttr_allocate
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_memAttr_allocate),
+    .io_enq_bits_task_memAttr_cacheable
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_memAttr_cacheable),
+    .io_enq_bits_task_memAttr_device
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_memAttr_device),
+    .io_enq_bits_task_memAttr_ewa
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_memAttr_ewa),
+    .io_enq_bits_task_traceTag
+      (~io_d_task_bits_task_mergeA & io_d_task_bits_task_traceTag),
+    .io_enq_bits_grantid                            ({4'h0, inflight_insertIdx}),
+    .io_deq_ready                                   (grantQueue_io_deq_ready),
+    .io_deq_valid                                   (_grantQueue_io_deq_valid),
+    .io_deq_bits_task_isKeyword
+      (_grantQueue_io_deq_bits_task_isKeyword),
+    .io_deq_bits_task_opcode                        (_grantQueue_io_deq_bits_task_opcode),
+    .io_deq_bits_task_param                         (_grantQueue_io_deq_bits_task_param),
+    .io_deq_bits_task_sourceId
+      (_grantQueue_io_deq_bits_task_sourceId),
+    .io_deq_bits_task_denied                        (_grantQueue_io_deq_bits_task_denied),
+    .io_deq_bits_task_corrupt
+      (_grantQueue_io_deq_bits_task_corrupt),
+    .io_deq_bits_grantid                            (_grantQueue_io_deq_bits_grantid),
+    .io_count                                       (_grantQueue_io_count)
+  );
+  Queue16_GrantQueueData grantQueueData0 (
+    .clock                 (clock),
+    .reset                 (reset),
+    .io_enq_valid          (grantQueue_io_enq_valid),
+    .io_enq_bits_data_data (io_d_task_bits_data_data[255:0]),
+    .io_deq_ready          (grantQueue_io_deq_ready),
+    .io_deq_bits_data_data (_grantQueueData0_io_deq_bits_data_data)
+  );
+  Queue16_GrantQueueData grantQueueData1 (
+    .clock                 (clock),
+    .reset                 (reset),
+    .io_enq_valid          (grantQueue_io_enq_valid),
+    .io_enq_bits_data_data (io_d_task_bits_data_data[511:256]),
+    .io_deq_ready          (grantQueue_io_deq_ready),
+    .io_deq_bits_data_data (_grantQueueData1_io_deq_bits_data_data)
+  );
+  Queue10_GrantBuffer_Anon pftRespQueue (
+    .clock        (clock),
+    .reset        (reset),
+    .io_enq_valid
+      (io_d_task_valid & io_d_task_bits_task_opcode == 4'h2
+       & io_d_task_bits_task_fromL2pft),
+    .io_deq_ready (io_prefetchResp_ready),
+    .io_deq_valid (io_prefetchResp_valid),
+    .io_count     (_pftRespQueue_io_count)
+  );
+  assign io_d_valid = grantBufValid | _grantQueue_io_deq_valid;
+  assign io_d_bits_opcode =
+    grantBufValid ? grantBuf_task_opcode : _grantQueue_io_deq_bits_task_opcode;
+  assign io_d_bits_param =
+    grantBufValid ? grantBuf_task_param[1:0] : _grantQueue_io_deq_bits_task_param[1:0];
+  assign io_d_bits_source =
+    grantBufValid ? grantBuf_task_sourceId : _grantQueue_io_deq_bits_task_sourceId;
+  assign io_d_bits_sink =
+    grantBufValid ? grantBuf_grantid : _grantQueue_io_deq_bits_grantid;
+  assign io_d_bits_denied =
+    grantBufValid ? grantBuf_task_denied : _grantQueue_io_deq_bits_task_denied;
+  assign io_d_bits_echo_isKeyword =
+    grantBufValid ? grantBuf_task_isKeyword : _grantQueue_io_deq_bits_task_isKeyword;
+  assign io_d_bits_data =
+    grantBufValid
+      ? grantBuf_data_data
+      : _grantQueue_io_deq_bits_task_isKeyword
+          ? _grantQueueData1_io_deq_bits_data_data
+          : _grantQueueData0_io_deq_bits_data_data;
+  assign io_d_bits_corrupt =
+    grantBufValid
+      ? grantBuf_task_corrupt | grantBuf_task_denied
+      : _grantQueue_io_deq_bits_task_corrupt | _grantQueue_io_deq_bits_task_denied;
+  assign io_toReqArb_blockSinkReqEntrance_blockA_s1 =
+    _noSpaceForSinkReq_T_27[4] | _noSpaceWaitSinkEForSinkReq_T_49[4]
+    | 4'({1'h0,
+          3'({1'h0,
+              2'({1'h0, io_pipeStatusVec_1_valid & io_pipeStatusVec_1_bits_channel[0]}
+                 + {1'h0, io_pipeStatusVec_2_valid & io_pipeStatusVec_2_bits_channel[0]})}
+             + {1'h0,
+                2'({1'h0, io_pipeStatusVec_3_valid & io_pipeStatusVec_3_bits_channel[0]}
+                   + {1'h0,
+                      io_pipeStatusVec_4_valid & io_pipeStatusVec_4_bits_channel[0]})})}
+         + _pftRespQueue_io_count) > 4'h9;
+  assign io_toReqArb_blockSinkReqEntrance_blockB_s1 =
+    |{inflightGrant_0_valid & inflightGrant_0_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_0_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_1_valid & inflightGrant_1_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_1_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_2_valid & inflightGrant_2_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_2_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_3_valid & inflightGrant_3_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_3_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_4_valid & inflightGrant_4_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_4_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_5_valid & inflightGrant_5_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_5_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_6_valid & inflightGrant_6_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_6_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_7_valid & inflightGrant_7_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_7_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_8_valid & inflightGrant_8_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_8_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_9_valid & inflightGrant_9_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_9_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_10_valid & inflightGrant_10_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_10_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_11_valid & inflightGrant_11_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_11_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_12_valid & inflightGrant_12_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_12_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_13_valid & inflightGrant_13_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_13_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_14_valid & inflightGrant_14_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_14_bits_tag == io_fromReqArb_status_s1_tags_1,
+      inflightGrant_15_valid & inflightGrant_15_bits_set == io_fromReqArb_status_s1_sets_1
+        & inflightGrant_15_bits_tag == io_fromReqArb_status_s1_tags_1};
+  assign io_toReqArb_blockSinkReqEntrance_blockC_s1 = _noSpaceForSinkReq_T_27[4];
+  assign io_toReqArb_blockMSHRReqEntrance =
+    5'({2'h0,
+        3'({1'h0,
+            2'({1'h0,
+                io_pipeStatusVec_1_valid
+                  & (io_pipeStatusVec_1_bits_channel[0]
+                     | io_pipeStatusVec_1_bits_channel[2])}
+               + {1'h0,
+                  io_pipeStatusVec_2_valid
+                    & (io_pipeStatusVec_2_bits_channel[0]
+                       | io_pipeStatusVec_2_bits_channel[2])})}
+           + {1'h0,
+              2'({1'h0,
+                  io_pipeStatusVec_3_valid
+                    & (io_pipeStatusVec_3_bits_channel[0]
+                       | io_pipeStatusVec_3_bits_channel[2])}
+                 + {1'h0,
+                    io_pipeStatusVec_4_valid
+                      & (io_pipeStatusVec_4_bits_channel[0]
+                         | io_pipeStatusVec_4_bits_channel[2])})})}
+       + _grantQueue_io_count) > 5'hE
+    | 5'({2'h0,
+          3'({1'h0,
+              2'({1'h0, io_pipeStatusVec_1_valid & io_pipeStatusVec_1_bits_channel[0]}
+                 + {1'h0, io_pipeStatusVec_2_valid & io_pipeStatusVec_2_bits_channel[0]})}
+             + {1'h0,
+                2'({1'h0, io_pipeStatusVec_3_valid & io_pipeStatusVec_3_bits_channel[0]}
+                   + {1'h0,
+                      io_pipeStatusVec_4_valid & io_pipeStatusVec_4_bits_channel[0]})})}
+         + 5'({1'h0,
+               4'({1'h0, 3'({1'h0, 2'(_GEN + _GEN_0)} + {1'h0, 2'(_GEN_1 + _GEN_2)})}
+                  + {1'h0,
+                     3'({1'h0, 2'(_GEN_3 + _GEN_4)} + {1'h0, 2'(_GEN_5 + _GEN_6)})})}
+              + {1'h0,
+                 4'({1'h0, 3'({1'h0, 2'(_GEN_7 + _GEN_8)} + {1'h0, 2'(_GEN_9 + _GEN_10)})}
+                    + {1'h0,
+                       3'({1'h0, 2'(_GEN_11 + _GEN_12)}
+                          + {1'h0, 2'(_GEN_13 + _GEN_14)})})})) > 5'hE
+    | 4'({1'h0,
+          3'({1'h0,
+              2'({1'h0, io_pipeStatusVec_1_valid & io_pipeStatusVec_1_bits_channel[0]}
+                 + {1'h0, io_pipeStatusVec_2_valid & io_pipeStatusVec_2_bits_channel[0]})}
+             + {1'h0,
+                2'({1'h0, io_pipeStatusVec_3_valid & io_pipeStatusVec_3_bits_channel[0]}
+                   + {1'h0,
+                      io_pipeStatusVec_4_valid & io_pipeStatusVec_4_bits_channel[0]})})}
+         + _pftRespQueue_io_count) > 4'h8;
+  assign io_grantStatus_0_valid = inflightGrant_0_valid;
+  assign io_grantStatus_0_set = inflightGrant_0_bits_set;
+  assign io_grantStatus_0_tag = inflightGrant_0_bits_tag;
+  assign io_grantStatus_1_valid = inflightGrant_1_valid;
+  assign io_grantStatus_1_set = inflightGrant_1_bits_set;
+  assign io_grantStatus_1_tag = inflightGrant_1_bits_tag;
+  assign io_grantStatus_2_valid = inflightGrant_2_valid;
+  assign io_grantStatus_2_set = inflightGrant_2_bits_set;
+  assign io_grantStatus_2_tag = inflightGrant_2_bits_tag;
+  assign io_grantStatus_3_valid = inflightGrant_3_valid;
+  assign io_grantStatus_3_set = inflightGrant_3_bits_set;
+  assign io_grantStatus_3_tag = inflightGrant_3_bits_tag;
+  assign io_grantStatus_4_valid = inflightGrant_4_valid;
+  assign io_grantStatus_4_set = inflightGrant_4_bits_set;
+  assign io_grantStatus_4_tag = inflightGrant_4_bits_tag;
+  assign io_grantStatus_5_valid = inflightGrant_5_valid;
+  assign io_grantStatus_5_set = inflightGrant_5_bits_set;
+  assign io_grantStatus_5_tag = inflightGrant_5_bits_tag;
+  assign io_grantStatus_6_valid = inflightGrant_6_valid;
+  assign io_grantStatus_6_set = inflightGrant_6_bits_set;
+  assign io_grantStatus_6_tag = inflightGrant_6_bits_tag;
+  assign io_grantStatus_7_valid = inflightGrant_7_valid;
+  assign io_grantStatus_7_set = inflightGrant_7_bits_set;
+  assign io_grantStatus_7_tag = inflightGrant_7_bits_tag;
+  assign io_grantStatus_8_valid = inflightGrant_8_valid;
+  assign io_grantStatus_8_set = inflightGrant_8_bits_set;
+  assign io_grantStatus_8_tag = inflightGrant_8_bits_tag;
+  assign io_grantStatus_9_valid = inflightGrant_9_valid;
+  assign io_grantStatus_9_set = inflightGrant_9_bits_set;
+  assign io_grantStatus_9_tag = inflightGrant_9_bits_tag;
+  assign io_grantStatus_10_valid = inflightGrant_10_valid;
+  assign io_grantStatus_10_set = inflightGrant_10_bits_set;
+  assign io_grantStatus_10_tag = inflightGrant_10_bits_tag;
+  assign io_grantStatus_11_valid = inflightGrant_11_valid;
+  assign io_grantStatus_11_set = inflightGrant_11_bits_set;
+  assign io_grantStatus_11_tag = inflightGrant_11_bits_tag;
+  assign io_grantStatus_12_valid = inflightGrant_12_valid;
+  assign io_grantStatus_12_set = inflightGrant_12_bits_set;
+  assign io_grantStatus_12_tag = inflightGrant_12_bits_tag;
+  assign io_grantStatus_13_valid = inflightGrant_13_valid;
+  assign io_grantStatus_13_set = inflightGrant_13_bits_set;
+  assign io_grantStatus_13_tag = inflightGrant_13_bits_tag;
+  assign io_grantStatus_14_valid = inflightGrant_14_valid;
+  assign io_grantStatus_14_set = inflightGrant_14_bits_set;
+  assign io_grantStatus_14_tag = inflightGrant_14_bits_tag;
+  assign io_grantStatus_15_valid = inflightGrant_15_valid;
+  assign io_grantStatus_15_set = inflightGrant_15_bits_set;
+  assign io_grantStatus_15_tag = inflightGrant_15_bits_tag;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/L2Cache.sv b/flow/designs/src/xiangshan_coupledl2/deps/L2Cache.sv
new file mode 100644
index 0000000000..1f6ebf1327
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/L2Cache.sv
@@ -0,0 +1,213 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module L2Cache(
+  input          clock,
+  input          reset,
+  input  [3:0]   mbist_array,
+  input          mbist_all,
+  input          mbist_req,
+  output         mbist_ack,
+  input          mbist_writeen,
+  input  [7:0]   mbist_be,
+  input  [11:0]  mbist_addr,
+  input  [163:0] mbist_indata,
+  input          mbist_readen,
+  input  [11:0]  mbist_addr_rd,
+  output [163:0] mbist_outdata,
+  output         toNextPipeline_0_array,
+  output         toNextPipeline_0_all,
+  output         toNextPipeline_0_req,
+  input          toNextPipeline_0_ack,
+  output         toNextPipeline_0_writeen,
+  output         toNextPipeline_0_be,
+  output [8:0]   toNextPipeline_0_addr,
+  output [12:0]  toNextPipeline_0_indata,
+  output         toNextPipeline_0_readen,
+  output [8:0]   toNextPipeline_0_addr_rd,
+  input  [12:0]  toNextPipeline_0_outdata,
+  output [3:0]   toNextPipeline_1_array,
+  output         toNextPipeline_1_all,
+  output         toNextPipeline_1_req,
+  input          toNextPipeline_1_ack,
+  output         toNextPipeline_1_writeen,
+  output [7:0]   toNextPipeline_1_be,
+  output [11:0]  toNextPipeline_1_addr,
+  output [163:0] toNextPipeline_1_indata,
+  output         toNextPipeline_1_readen,
+  output [11:0]  toNextPipeline_1_addr_rd,
+  input  [163:0] toNextPipeline_1_outdata
+);
+
+  wire         activated =
+    mbist_all | mbist_req
+    & (mbist_array == 4'h0 | mbist_array == 4'h1 | mbist_array == 4'h2
+       | mbist_array == 4'h3 | mbist_array == 4'h4 | mbist_array == 4'h5
+       | mbist_array == 4'h6 | mbist_array == 4'h7 | mbist_array == 4'h8
+       | mbist_array == 4'h9 | mbist_array == 4'hA);
+  reg  [3:0]   arrayReg;
+  reg          reqReg;
+  reg          allReg;
+  reg          wenReg;
+  reg  [7:0]   beReg;
+  reg  [11:0]  addrReg;
+  reg  [163:0] dataInReg;
+  reg          renReg;
+  reg  [11:0]  addrRdReg;
+  reg  [163:0] pipelineDataOutReg;
+  wire         selected = arrayReg == 4'h0 | arrayReg == 4'h1;
+  wire         doSpread = selected | allReg;
+  wire         selected_1 =
+    arrayReg == 4'h2 | arrayReg == 4'h3 | arrayReg == 4'h4 | arrayReg == 4'h5
+    | arrayReg == 4'h6 | arrayReg == 4'h7 | arrayReg == 4'h8 | arrayReg == 4'h9
+    | arrayReg == 4'hA;
+  wire         doSpread_1 = selected_1 | allReg;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      arrayReg <= 4'h0;
+      reqReg <= 1'h0;
+      allReg <= 1'h0;
+      wenReg <= 1'h0;
+      beReg <= 8'h0;
+      addrReg <= 12'h0;
+      dataInReg <= 164'h0;
+      renReg <= 1'h0;
+      addrRdReg <= 12'h0;
+    end
+    else begin
+      if (activated) begin
+        arrayReg <= mbist_array;
+        allReg <= mbist_all;
+        wenReg <= mbist_writeen;
+        renReg <= mbist_readen;
+      end
+      reqReg <= mbist_req;
+      if (activated & (mbist_readen | mbist_writeen)) begin
+        beReg <= mbist_be;
+        addrReg <= mbist_addr;
+        dataInReg <= mbist_indata;
+        addrRdReg <= mbist_addr_rd;
+      end
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (activated)
+      pipelineDataOutReg <=
+        {151'h0, selected ? toNextPipeline_0_outdata : 13'h0}
+        | (selected_1 ? toNextPipeline_1_outdata : 164'h0);
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:11];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hC; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        arrayReg = _RANDOM[4'h0][3:0];
+        reqReg = _RANDOM[4'h0][4];
+        allReg = _RANDOM[4'h0][5];
+        wenReg = _RANDOM[4'h0][6];
+        beReg = _RANDOM[4'h0][14:7];
+        addrReg = _RANDOM[4'h0][26:15];
+        dataInReg =
+          {_RANDOM[4'h0][31:27],
+           _RANDOM[4'h1],
+           _RANDOM[4'h2],
+           _RANDOM[4'h3],
+           _RANDOM[4'h4],
+           _RANDOM[4'h5][30:0]};
+        renReg = _RANDOM[4'h5][31];
+        addrRdReg = _RANDOM[4'h6][11:0];
+        pipelineDataOutReg =
+          {_RANDOM[4'h6][31:12],
+           _RANDOM[4'h7],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB][15:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        arrayReg = 4'h0;
+        reqReg = 1'h0;
+        allReg = 1'h0;
+        wenReg = 1'h0;
+        beReg = 8'h0;
+        addrReg = 12'h0;
+        dataInReg = 164'h0;
+        renReg = 1'h0;
+        addrRdReg = 12'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign mbist_ack = reqReg & (toNextPipeline_0_ack | toNextPipeline_1_ack);
+  assign mbist_outdata = pipelineDataOutReg;
+  assign toNextPipeline_0_array = doSpread & arrayReg[0];
+  assign toNextPipeline_0_all = doSpread & allReg;
+  assign toNextPipeline_0_req = reqReg;
+  assign toNextPipeline_0_writeen = doSpread & wenReg;
+  assign toNextPipeline_0_be = beReg[0];
+  assign toNextPipeline_0_addr = doSpread ? addrReg[8:0] : 9'h0;
+  assign toNextPipeline_0_indata = dataInReg[12:0];
+  assign toNextPipeline_0_readen = doSpread & renReg;
+  assign toNextPipeline_0_addr_rd = doSpread ? addrRdReg[8:0] : 9'h0;
+  assign toNextPipeline_1_array = doSpread_1 ? arrayReg : 4'h0;
+  assign toNextPipeline_1_all = doSpread_1 & allReg;
+  assign toNextPipeline_1_req = reqReg;
+  assign toNextPipeline_1_writeen = doSpread_1 & wenReg;
+  assign toNextPipeline_1_be = beReg;
+  assign toNextPipeline_1_addr = doSpread_1 ? addrReg : 12'h0;
+  assign toNextPipeline_1_indata = dataInReg;
+  assign toNextPipeline_1_readen = doSpread_1 & renReg;
+  assign toNextPipeline_1_addr_rd = doSpread_1 ? addrRdReg : 12'h0;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/L2DataStorage.sv b/flow/designs/src/xiangshan_coupledl2/deps/L2DataStorage.sv
new file mode 100644
index 0000000000..501a7ce619
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/L2DataStorage.sv
@@ -0,0 +1,247 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module L2DataStorage(
+  input          clock,
+  input          reset,
+  input  [3:0]   mbist_array,
+  input          mbist_all,
+  input          mbist_req,
+  output         mbist_ack,
+  input          mbist_writeen,
+  input          mbist_be,
+  input  [11:0]  mbist_addr,
+  input  [136:0] mbist_indata,
+  input          mbist_readen,
+  input  [11:0]  mbist_addr_rd,
+  output [136:0] mbist_outdata,
+  output [11:0]  toSRAM_0_addr,
+  output [11:0]  toSRAM_0_addr_rd,
+  output [136:0] toSRAM_0_wdata,
+  output         toSRAM_0_wmask,
+  output         toSRAM_0_re,
+  output         toSRAM_0_we,
+  input  [136:0] toSRAM_0_rdata,
+  output         toSRAM_0_ack,
+  output         toSRAM_0_selectedOH,
+  output [2:0]   toSRAM_0_array,
+  output [11:0]  toSRAM_1_addr,
+  output [11:0]  toSRAM_1_addr_rd,
+  output [136:0] toSRAM_1_wdata,
+  output         toSRAM_1_wmask,
+  output         toSRAM_1_re,
+  output         toSRAM_1_we,
+  input  [136:0] toSRAM_1_rdata,
+  output         toSRAM_1_ack,
+  output         toSRAM_1_selectedOH,
+  output [3:0]   toSRAM_1_array,
+  output [11:0]  toSRAM_2_addr,
+  output [11:0]  toSRAM_2_addr_rd,
+  output [136:0] toSRAM_2_wdata,
+  output         toSRAM_2_wmask,
+  output         toSRAM_2_re,
+  output         toSRAM_2_we,
+  input  [136:0] toSRAM_2_rdata,
+  output         toSRAM_2_ack,
+  output         toSRAM_2_selectedOH,
+  output [3:0]   toSRAM_2_array,
+  output [11:0]  toSRAM_3_addr,
+  output [11:0]  toSRAM_3_addr_rd,
+  output [136:0] toSRAM_3_wdata,
+  output         toSRAM_3_wmask,
+  output         toSRAM_3_re,
+  output         toSRAM_3_we,
+  input  [136:0] toSRAM_3_rdata,
+  output         toSRAM_3_ack,
+  output         toSRAM_3_selectedOH,
+  output [3:0]   toSRAM_3_array
+);
+
+  wire [136:0] sramDataOut_3;
+  wire [136:0] sramDataOut_2;
+  wire [136:0] sramDataOut_1;
+  wire [136:0] sramDataOut_0;
+  reg  [3:0]   arrayReg;
+  reg          reqReg;
+  reg          allReg;
+  reg          beReg;
+  reg  [11:0]  addrReg;
+  reg  [136:0] dataInReg;
+  reg  [11:0]  addrRdReg;
+  reg  [1:0]   wenStretched;
+  reg  [1:0]   renStretched;
+  wire         selectedVec_0 = arrayReg == 4'h7;
+  wire         doSpread = selectedVec_0 | allReg;
+  assign sramDataOut_0 = selectedVec_0 ? toSRAM_0_rdata : 137'h0;
+  wire         selectedVec_0_1 = arrayReg == 4'h8;
+  wire         doSpread_1 = selectedVec_0_1 | allReg;
+  assign sramDataOut_1 = selectedVec_0_1 ? toSRAM_1_rdata : 137'h0;
+  wire         selectedVec_0_2 = arrayReg == 4'h9;
+  wire         doSpread_2 = selectedVec_0_2 | allReg;
+  assign sramDataOut_2 = selectedVec_0_2 ? toSRAM_2_rdata : 137'h0;
+  wire         selectedVec_0_3 = arrayReg == 4'hA;
+  wire         doSpread_3 = selectedVec_0_3 | allReg;
+  assign sramDataOut_3 = selectedVec_0_3 ? toSRAM_3_rdata : 137'h0;
+  wire         activated =
+    mbist_all | mbist_req
+    & (mbist_array == 4'h7 | mbist_array == 4'h8 | mbist_array == 4'h9
+       | mbist_array == 4'hA);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      arrayReg <= 4'h0;
+      reqReg <= 1'h0;
+      allReg <= 1'h0;
+      beReg <= 1'h0;
+      addrReg <= 12'h0;
+      dataInReg <= 137'h0;
+      addrRdReg <= 12'h0;
+      wenStretched <= 2'h0;
+      renStretched <= 2'h0;
+    end
+    else begin
+      if (activated) begin
+        arrayReg <= mbist_array;
+        allReg <= mbist_all;
+      end
+      reqReg <= mbist_req;
+      if (activated & (mbist_readen | mbist_writeen)) begin
+        beReg <= mbist_be;
+        addrReg <= mbist_addr;
+        dataInReg <= mbist_indata;
+        addrRdReg <= mbist_addr_rd;
+      end
+      if (activated & mbist_writeen)
+        wenStretched <= 2'h3;
+      else if (|wenStretched)
+        wenStretched <= {1'h0, wenStretched[1]};
+      if (activated & mbist_readen)
+        renStretched <= 2'h3;
+      else if (|renStretched)
+        renStretched <= {1'h0, renStretched[1]};
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:5];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        arrayReg = _RANDOM[3'h0][3:0];
+        reqReg = _RANDOM[3'h0][4];
+        allReg = _RANDOM[3'h0][5];
+        beReg = _RANDOM[3'h0][7];
+        addrReg = _RANDOM[3'h0][19:8];
+        dataInReg =
+          {_RANDOM[3'h0][31:20],
+           _RANDOM[3'h1],
+           _RANDOM[3'h2],
+           _RANDOM[3'h3],
+           _RANDOM[3'h4][28:0]};
+        addrRdReg = {_RANDOM[3'h4][31:30], _RANDOM[3'h5][9:0]};
+        wenStretched = _RANDOM[3'h5][12:11];
+        renStretched = _RANDOM[3'h5][14:13];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        arrayReg = 4'h0;
+        reqReg = 1'h0;
+        allReg = 1'h0;
+        beReg = 1'h0;
+        addrReg = 12'h0;
+        dataInReg = 137'h0;
+        addrRdReg = 12'h0;
+        wenStretched = 2'h0;
+        renStretched = 2'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign mbist_ack = reqReg;
+  assign mbist_outdata = sramDataOut_0 | sramDataOut_1 | sramDataOut_2 | sramDataOut_3;
+  assign toSRAM_0_addr = doSpread ? addrReg : 12'h0;
+  assign toSRAM_0_addr_rd = doSpread ? addrRdReg : 12'h0;
+  assign toSRAM_0_wdata = dataInReg;
+  assign toSRAM_0_wmask = beReg;
+  assign toSRAM_0_re = doSpread & renStretched[0];
+  assign toSRAM_0_we = doSpread & wenStretched[0];
+  assign toSRAM_0_ack = reqReg;
+  assign toSRAM_0_selectedOH = allReg | ~reqReg | selectedVec_0;
+  assign toSRAM_0_array = arrayReg[2:0];
+  assign toSRAM_1_addr = doSpread_1 ? addrReg : 12'h0;
+  assign toSRAM_1_addr_rd = doSpread_1 ? addrRdReg : 12'h0;
+  assign toSRAM_1_wdata = dataInReg;
+  assign toSRAM_1_wmask = beReg;
+  assign toSRAM_1_re = doSpread_1 & renStretched[0];
+  assign toSRAM_1_we = doSpread_1 & wenStretched[0];
+  assign toSRAM_1_ack = reqReg;
+  assign toSRAM_1_selectedOH = allReg | ~reqReg | selectedVec_0_1;
+  assign toSRAM_1_array = arrayReg;
+  assign toSRAM_2_addr = doSpread_2 ? addrReg : 12'h0;
+  assign toSRAM_2_addr_rd = doSpread_2 ? addrRdReg : 12'h0;
+  assign toSRAM_2_wdata = dataInReg;
+  assign toSRAM_2_wmask = beReg;
+  assign toSRAM_2_re = doSpread_2 & renStretched[0];
+  assign toSRAM_2_we = doSpread_2 & wenStretched[0];
+  assign toSRAM_2_ack = reqReg;
+  assign toSRAM_2_selectedOH = allReg | ~reqReg | selectedVec_0_2;
+  assign toSRAM_2_array = arrayReg;
+  assign toSRAM_3_addr = doSpread_3 ? addrReg : 12'h0;
+  assign toSRAM_3_addr_rd = doSpread_3 ? addrRdReg : 12'h0;
+  assign toSRAM_3_wdata = dataInReg;
+  assign toSRAM_3_wmask = beReg;
+  assign toSRAM_3_re = doSpread_3 & renStretched[0];
+  assign toSRAM_3_we = doSpread_3 & wenStretched[0];
+  assign toSRAM_3_ack = reqReg;
+  assign toSRAM_3_selectedOH = allReg | ~reqReg | selectedVec_0_3;
+  assign toSRAM_3_array = arrayReg;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/L2Directory.sv b/flow/designs/src/xiangshan_coupledl2/deps/L2Directory.sv
new file mode 100644
index 0000000000..953cdf1b9e
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/L2Directory.sv
@@ -0,0 +1,266 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module L2Directory(
+  input          clock,
+  input          reset,
+  input  [2:0]   mbist_array,
+  input          mbist_all,
+  input          mbist_req,
+  output         mbist_ack,
+  input          mbist_writeen,
+  input  [7:0]   mbist_be,
+  input  [8:0]   mbist_addr,
+  input  [163:0] mbist_indata,
+  input          mbist_readen,
+  input  [8:0]   mbist_addr_rd,
+  output [163:0] mbist_outdata,
+  output [8:0]   toSRAM_0_addr,
+  output [8:0]   toSRAM_0_addr_rd,
+  output [163:0] toSRAM_0_wdata,
+  output [3:0]   toSRAM_0_wmask,
+  output         toSRAM_0_re,
+  output         toSRAM_0_we,
+  input  [163:0] toSRAM_0_rdata,
+  output         toSRAM_0_ack,
+  output         toSRAM_0_selectedOH,
+  output [1:0]   toSRAM_0_array,
+  output [8:0]   toSRAM_1_addr,
+  output [8:0]   toSRAM_1_addr_rd,
+  output [163:0] toSRAM_1_wdata,
+  output [3:0]   toSRAM_1_wmask,
+  output         toSRAM_1_re,
+  output         toSRAM_1_we,
+  input  [163:0] toSRAM_1_rdata,
+  output         toSRAM_1_ack,
+  output         toSRAM_1_selectedOH,
+  output [1:0]   toSRAM_1_array,
+  output [8:0]   toSRAM_2_addr,
+  output [8:0]   toSRAM_2_addr_rd,
+  output [103:0] toSRAM_2_wdata,
+  output [7:0]   toSRAM_2_wmask,
+  output         toSRAM_2_re,
+  output         toSRAM_2_we,
+  input  [103:0] toSRAM_2_rdata,
+  output         toSRAM_2_ack,
+  output         toSRAM_2_selectedOH,
+  output [2:0]   toSRAM_2_array,
+  output [8:0]   toSRAM_3_addr,
+  output [8:0]   toSRAM_3_addr_rd,
+  output [15:0]  toSRAM_3_wdata,
+  output         toSRAM_3_wmask,
+  output         toSRAM_3_re,
+  output         toSRAM_3_we,
+  input  [15:0]  toSRAM_3_rdata,
+  output         toSRAM_3_ack,
+  output         toSRAM_3_selectedOH,
+  output [2:0]   toSRAM_3_array,
+  output [8:0]   toSRAM_4_addr,
+  output [8:0]   toSRAM_4_addr_rd,
+  output [7:0]   toSRAM_4_wdata,
+  output [7:0]   toSRAM_4_wmask,
+  output         toSRAM_4_re,
+  output         toSRAM_4_we,
+  input  [7:0]   toSRAM_4_rdata,
+  output         toSRAM_4_ack,
+  output         toSRAM_4_selectedOH,
+  output [2:0]   toSRAM_4_array
+);
+
+  wire [163:0] sramDataOut_4;
+  wire [163:0] sramDataOut_3;
+  wire [163:0] sramDataOut_2;
+  wire [163:0] sramDataOut_1;
+  wire [163:0] sramDataOut_0;
+  reg  [2:0]   arrayReg;
+  reg          reqReg;
+  reg          allReg;
+  reg          wenReg;
+  reg  [7:0]   beReg;
+  reg  [8:0]   addrReg;
+  reg  [163:0] dataInReg;
+  reg          renReg;
+  reg  [8:0]   addrRdReg;
+  wire         selectedVec_0 = arrayReg == 3'h2;
+  wire         doSpread = selectedVec_0 | allReg;
+  assign sramDataOut_0 = selectedVec_0 ? toSRAM_0_rdata : 164'h0;
+  wire         selectedVec_0_1 = arrayReg == 3'h3;
+  wire         doSpread_1 = selectedVec_0_1 | allReg;
+  assign sramDataOut_1 = selectedVec_0_1 ? toSRAM_1_rdata : 164'h0;
+  wire         selectedVec_0_2 = arrayReg == 3'h4;
+  wire         doSpread_2 = selectedVec_0_2 | allReg;
+  assign sramDataOut_2 = {60'h0, selectedVec_0_2 ? toSRAM_2_rdata : 104'h0};
+  wire         selectedVec_0_3 = arrayReg == 3'h5;
+  wire         doSpread_3 = selectedVec_0_3 | allReg;
+  assign sramDataOut_3 = {148'h0, selectedVec_0_3 ? toSRAM_3_rdata : 16'h0};
+  wire         selectedVec_0_4 = arrayReg == 3'h6;
+  wire         doSpread_4 = selectedVec_0_4 | allReg;
+  assign sramDataOut_4 = {156'h0, selectedVec_0_4 ? toSRAM_4_rdata : 8'h0};
+  wire         activated =
+    mbist_all | mbist_req
+    & (mbist_array == 3'h2 | mbist_array == 3'h3 | mbist_array == 3'h4
+       | mbist_array == 3'h5 | mbist_array == 3'h6);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      arrayReg <= 3'h0;
+      reqReg <= 1'h0;
+      allReg <= 1'h0;
+      wenReg <= 1'h0;
+      beReg <= 8'h0;
+      addrReg <= 9'h0;
+      dataInReg <= 164'h0;
+      renReg <= 1'h0;
+      addrRdReg <= 9'h0;
+    end
+    else begin
+      if (activated) begin
+        arrayReg <= mbist_array;
+        allReg <= mbist_all;
+        wenReg <= mbist_writeen;
+        renReg <= mbist_readen;
+      end
+      reqReg <= mbist_req;
+      if (activated & (mbist_readen | mbist_writeen)) begin
+        beReg <= mbist_be;
+        addrReg <= mbist_addr;
+        dataInReg <= mbist_indata;
+        addrRdReg <= mbist_addr_rd;
+      end
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:6];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h7; i += 3'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        arrayReg = _RANDOM[3'h0][2:0];
+        reqReg = _RANDOM[3'h0][3];
+        allReg = _RANDOM[3'h0][4];
+        wenReg = _RANDOM[3'h0][5];
+        beReg = _RANDOM[3'h0][13:6];
+        addrReg = _RANDOM[3'h0][22:14];
+        dataInReg =
+          {_RANDOM[3'h0][31:23],
+           _RANDOM[3'h1],
+           _RANDOM[3'h2],
+           _RANDOM[3'h3],
+           _RANDOM[3'h4],
+           _RANDOM[3'h5][26:0]};
+        renReg = _RANDOM[3'h5][27];
+        addrRdReg = {_RANDOM[3'h5][31:28], _RANDOM[3'h6][4:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        arrayReg = 3'h0;
+        reqReg = 1'h0;
+        allReg = 1'h0;
+        wenReg = 1'h0;
+        beReg = 8'h0;
+        addrReg = 9'h0;
+        dataInReg = 164'h0;
+        renReg = 1'h0;
+        addrRdReg = 9'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign mbist_ack = reqReg;
+  assign mbist_outdata =
+    sramDataOut_0 | sramDataOut_1 | sramDataOut_2 | sramDataOut_3 | sramDataOut_4;
+  assign toSRAM_0_addr = doSpread ? addrReg : 9'h0;
+  assign toSRAM_0_addr_rd = doSpread ? addrRdReg : 9'h0;
+  assign toSRAM_0_wdata = dataInReg;
+  assign toSRAM_0_wmask = beReg[3:0];
+  assign toSRAM_0_re = doSpread & renReg;
+  assign toSRAM_0_we = doSpread & wenReg;
+  assign toSRAM_0_ack = reqReg;
+  assign toSRAM_0_selectedOH = allReg | ~reqReg | selectedVec_0;
+  assign toSRAM_0_array = arrayReg[1:0];
+  assign toSRAM_1_addr = doSpread_1 ? addrReg : 9'h0;
+  assign toSRAM_1_addr_rd = doSpread_1 ? addrRdReg : 9'h0;
+  assign toSRAM_1_wdata = dataInReg;
+  assign toSRAM_1_wmask = beReg[3:0];
+  assign toSRAM_1_re = doSpread_1 & renReg;
+  assign toSRAM_1_we = doSpread_1 & wenReg;
+  assign toSRAM_1_ack = reqReg;
+  assign toSRAM_1_selectedOH = allReg | ~reqReg | selectedVec_0_1;
+  assign toSRAM_1_array = arrayReg[1:0];
+  assign toSRAM_2_addr = doSpread_2 ? addrReg : 9'h0;
+  assign toSRAM_2_addr_rd = doSpread_2 ? addrRdReg : 9'h0;
+  assign toSRAM_2_wdata = dataInReg[103:0];
+  assign toSRAM_2_wmask = beReg;
+  assign toSRAM_2_re = doSpread_2 & renReg;
+  assign toSRAM_2_we = doSpread_2 & wenReg;
+  assign toSRAM_2_ack = reqReg;
+  assign toSRAM_2_selectedOH = allReg | ~reqReg | selectedVec_0_2;
+  assign toSRAM_2_array = arrayReg;
+  assign toSRAM_3_addr = doSpread_3 ? addrReg : 9'h0;
+  assign toSRAM_3_addr_rd = doSpread_3 ? addrRdReg : 9'h0;
+  assign toSRAM_3_wdata = dataInReg[15:0];
+  assign toSRAM_3_wmask = beReg[0];
+  assign toSRAM_3_re = doSpread_3 & renReg;
+  assign toSRAM_3_we = doSpread_3 & wenReg;
+  assign toSRAM_3_ack = reqReg;
+  assign toSRAM_3_selectedOH = allReg | ~reqReg | selectedVec_0_3;
+  assign toSRAM_3_array = arrayReg;
+  assign toSRAM_4_addr = doSpread_4 ? addrReg : 9'h0;
+  assign toSRAM_4_addr_rd = doSpread_4 ? addrRdReg : 9'h0;
+  assign toSRAM_4_wdata = dataInReg[7:0];
+  assign toSRAM_4_wmask = beReg;
+  assign toSRAM_4_re = doSpread_4 & renReg;
+  assign toSRAM_4_we = doSpread_4 & wenReg;
+  assign toSRAM_4_ack = reqReg;
+  assign toSRAM_4_selectedOH = allReg | ~reqReg | selectedVec_0_4;
+  assign toSRAM_4_array = arrayReg;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/L2Slice.sv b/flow/designs/src/xiangshan_coupledl2/deps/L2Slice.sv
new file mode 100644
index 0000000000..d046b303ef
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/L2Slice.sv
@@ -0,0 +1,212 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module L2Slice(
+  input          clock,
+  input          reset,
+  input  [3:0]   mbist_array,
+  input          mbist_all,
+  input          mbist_req,
+  output         mbist_ack,
+  input          mbist_writeen,
+  input  [7:0]   mbist_be,
+  input  [11:0]  mbist_addr,
+  input  [163:0] mbist_indata,
+  input          mbist_readen,
+  input  [11:0]  mbist_addr_rd,
+  output [163:0] mbist_outdata,
+  output [2:0]   toNextPipeline_0_array,
+  output         toNextPipeline_0_all,
+  output         toNextPipeline_0_req,
+  input          toNextPipeline_0_ack,
+  output         toNextPipeline_0_writeen,
+  output [7:0]   toNextPipeline_0_be,
+  output [8:0]   toNextPipeline_0_addr,
+  output [163:0] toNextPipeline_0_indata,
+  output         toNextPipeline_0_readen,
+  output [8:0]   toNextPipeline_0_addr_rd,
+  input  [163:0] toNextPipeline_0_outdata,
+  output [3:0]   toNextPipeline_1_array,
+  output         toNextPipeline_1_all,
+  output         toNextPipeline_1_req,
+  input          toNextPipeline_1_ack,
+  output         toNextPipeline_1_writeen,
+  output         toNextPipeline_1_be,
+  output [11:0]  toNextPipeline_1_addr,
+  output [136:0] toNextPipeline_1_indata,
+  output         toNextPipeline_1_readen,
+  output [11:0]  toNextPipeline_1_addr_rd,
+  input  [136:0] toNextPipeline_1_outdata
+);
+
+  wire         activated =
+    mbist_all | mbist_req
+    & (mbist_array == 4'h2 | mbist_array == 4'h3 | mbist_array == 4'h4
+       | mbist_array == 4'h5 | mbist_array == 4'h6 | mbist_array == 4'h7
+       | mbist_array == 4'h8 | mbist_array == 4'h9 | mbist_array == 4'hA);
+  reg  [3:0]   arrayReg;
+  reg          reqReg;
+  reg          allReg;
+  reg          wenReg;
+  reg  [7:0]   beReg;
+  reg  [11:0]  addrReg;
+  reg  [163:0] dataInReg;
+  reg          renReg;
+  reg  [11:0]  addrRdReg;
+  reg  [163:0] pipelineDataOutReg;
+  wire         selected =
+    arrayReg == 4'h2 | arrayReg == 4'h3 | arrayReg == 4'h4 | arrayReg == 4'h5
+    | arrayReg == 4'h6;
+  wire         doSpread = selected | allReg;
+  wire         selected_1 =
+    arrayReg == 4'h7 | arrayReg == 4'h8 | arrayReg == 4'h9 | arrayReg == 4'hA;
+  wire         doSpread_1 = selected_1 | allReg;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      arrayReg <= 4'h0;
+      reqReg <= 1'h0;
+      allReg <= 1'h0;
+      wenReg <= 1'h0;
+      beReg <= 8'h0;
+      addrReg <= 12'h0;
+      dataInReg <= 164'h0;
+      renReg <= 1'h0;
+      addrRdReg <= 12'h0;
+    end
+    else begin
+      if (activated) begin
+        arrayReg <= mbist_array;
+        allReg <= mbist_all;
+        wenReg <= mbist_writeen;
+        renReg <= mbist_readen;
+      end
+      reqReg <= mbist_req;
+      if (activated & (mbist_readen | mbist_writeen)) begin
+        beReg <= mbist_be;
+        addrReg <= mbist_addr;
+        dataInReg <= mbist_indata;
+        addrRdReg <= mbist_addr_rd;
+      end
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (activated)
+      pipelineDataOutReg <=
+        (selected ? toNextPipeline_0_outdata : 164'h0)
+        | {27'h0, selected_1 ? toNextPipeline_1_outdata : 137'h0};
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:11];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hC; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        arrayReg = _RANDOM[4'h0][3:0];
+        reqReg = _RANDOM[4'h0][4];
+        allReg = _RANDOM[4'h0][5];
+        wenReg = _RANDOM[4'h0][6];
+        beReg = _RANDOM[4'h0][14:7];
+        addrReg = _RANDOM[4'h0][26:15];
+        dataInReg =
+          {_RANDOM[4'h0][31:27],
+           _RANDOM[4'h1],
+           _RANDOM[4'h2],
+           _RANDOM[4'h3],
+           _RANDOM[4'h4],
+           _RANDOM[4'h5][30:0]};
+        renReg = _RANDOM[4'h5][31];
+        addrRdReg = _RANDOM[4'h6][11:0];
+        pipelineDataOutReg =
+          {_RANDOM[4'h6][31:12],
+           _RANDOM[4'h7],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB][15:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        arrayReg = 4'h0;
+        reqReg = 1'h0;
+        allReg = 1'h0;
+        wenReg = 1'h0;
+        beReg = 8'h0;
+        addrReg = 12'h0;
+        dataInReg = 164'h0;
+        renReg = 1'h0;
+        addrRdReg = 12'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign mbist_ack = reqReg & (toNextPipeline_0_ack | toNextPipeline_1_ack);
+  assign mbist_outdata = pipelineDataOutReg;
+  assign toNextPipeline_0_array = doSpread ? arrayReg[2:0] : 3'h0;
+  assign toNextPipeline_0_all = doSpread & allReg;
+  assign toNextPipeline_0_req = reqReg;
+  assign toNextPipeline_0_writeen = doSpread & wenReg;
+  assign toNextPipeline_0_be = beReg;
+  assign toNextPipeline_0_addr = doSpread ? addrReg[8:0] : 9'h0;
+  assign toNextPipeline_0_indata = dataInReg;
+  assign toNextPipeline_0_readen = doSpread & renReg;
+  assign toNextPipeline_0_addr_rd = doSpread ? addrRdReg[8:0] : 9'h0;
+  assign toNextPipeline_1_array = doSpread_1 ? arrayReg : 4'h0;
+  assign toNextPipeline_1_all = doSpread_1 & allReg;
+  assign toNextPipeline_1_req = reqReg;
+  assign toNextPipeline_1_writeen = doSpread_1 & wenReg;
+  assign toNextPipeline_1_be = beReg[0];
+  assign toNextPipeline_1_addr = doSpread_1 ? addrReg : 12'h0;
+  assign toNextPipeline_1_indata = dataInReg[136:0];
+  assign toNextPipeline_1_readen = doSpread_1 & renReg;
+  assign toNextPipeline_1_addr_rd = doSpread_1 ? addrRdReg : 12'h0;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled.sv b/flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled.sv
new file mode 100644
index 0000000000..4ed575e39a
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled.sv
@@ -0,0 +1,166 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module LCredit2Decoupled(
+  input          clock,
+  input          reset,
+  input          io_in_flitv,
+  input  [114:0] io_in_flit,
+  output         io_in_lcrdv,
+  input          io_out_ready,
+  output         io_out_valid,
+  output [3:0]   io_out_bits_qos,
+  output [10:0]  io_out_bits_srcID,
+  output [11:0]  io_out_bits_txnID,
+  output [10:0]  io_out_bits_fwdNID,
+  output [11:0]  io_out_bits_fwdTxnID,
+  output [4:0]   io_out_bits_opcode,
+  output [44:0]  io_out_bits_addr,
+  output         io_out_bits_ns,
+  output         io_out_bits_doNotGoToSD,
+  output         io_out_bits_retToSrc,
+  output         io_out_bits_traceTag,
+  output         io_out_bits_mpam_perfMonGroup,
+  output [8:0]   io_out_bits_mpam_partID,
+  output         io_out_bits_mpam_mpamNS,
+  input  [1:0]   io_state_state,
+  output         io_reclaimLCredit
+);
+
+  wire       _queue_io_deq_valid;
+  wire [4:0] _queue_io_deq_bits_opcode;
+  wire [2:0] _queue_io_count;
+  reg  [2:0] lcreditInflight;
+  reg  [2:0] lcreditPool;
+  wire       accept = (|lcreditInflight) & io_in_flitv;
+  reg        io_in_lcrdv_REG;
+  wire       _GEN = _queue_io_deq_valid & _queue_io_deq_bits_opcode == 5'h0;
+  wire       lcreditOut = lcreditPool > _queue_io_count & io_state_state == 2'h2;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      lcreditInflight <= 3'h0;
+      lcreditPool <= 3'h4;
+      io_in_lcrdv_REG <= 1'h0;
+    end
+    else begin
+      if (lcreditOut) begin
+        if (~accept) begin
+          lcreditInflight <= 3'(lcreditInflight + 3'h1);
+          lcreditPool <= 3'(lcreditPool - 3'h1);
+        end
+      end
+      else if (accept) begin
+        lcreditInflight <= 3'(lcreditInflight - 3'h1);
+        lcreditPool <= 3'(lcreditPool + 3'h1);
+      end
+      io_in_lcrdv_REG <= lcreditOut;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        lcreditInflight = _RANDOM[/*Zero width*/ 1'b0][2:0];
+        lcreditPool = _RANDOM[/*Zero width*/ 1'b0][5:3];
+        io_in_lcrdv_REG = _RANDOM[/*Zero width*/ 1'b0][6];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        lcreditInflight = 3'h0;
+        lcreditPool = 3'h4;
+        io_in_lcrdv_REG = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  Queue4_CHISNP queue (
+    .clock                         (clock),
+    .reset                         (reset),
+    .io_enq_valid                  (accept),
+    .io_enq_bits_qos               (io_in_flit[3:0]),
+    .io_enq_bits_srcID             (io_in_flit[14:4]),
+    .io_enq_bits_txnID             (io_in_flit[26:15]),
+    .io_enq_bits_fwdNID            (io_in_flit[37:27]),
+    .io_enq_bits_fwdTxnID          (io_in_flit[49:38]),
+    .io_enq_bits_opcode            (io_in_flit[54:50]),
+    .io_enq_bits_addr              (io_in_flit[99:55]),
+    .io_enq_bits_ns                (io_in_flit[100]),
+    .io_enq_bits_doNotGoToSD       (io_in_flit[101]),
+    .io_enq_bits_retToSrc          (io_in_flit[102]),
+    .io_enq_bits_traceTag          (io_in_flit[103]),
+    .io_enq_bits_mpam_perfMonGroup (io_in_flit[114]),
+    .io_enq_bits_mpam_partID       (io_in_flit[113:105]),
+    .io_enq_bits_mpam_mpamNS       (io_in_flit[104]),
+    .io_deq_ready                  (_GEN | io_out_ready),
+    .io_deq_valid                  (_queue_io_deq_valid),
+    .io_deq_bits_qos               (io_out_bits_qos),
+    .io_deq_bits_srcID             (io_out_bits_srcID),
+    .io_deq_bits_txnID             (io_out_bits_txnID),
+    .io_deq_bits_fwdNID            (io_out_bits_fwdNID),
+    .io_deq_bits_fwdTxnID          (io_out_bits_fwdTxnID),
+    .io_deq_bits_opcode            (_queue_io_deq_bits_opcode),
+    .io_deq_bits_addr              (io_out_bits_addr),
+    .io_deq_bits_ns                (io_out_bits_ns),
+    .io_deq_bits_doNotGoToSD       (io_out_bits_doNotGoToSD),
+    .io_deq_bits_retToSrc          (io_out_bits_retToSrc),
+    .io_deq_bits_traceTag          (io_out_bits_traceTag),
+    .io_deq_bits_mpam_perfMonGroup (io_out_bits_mpam_perfMonGroup),
+    .io_deq_bits_mpam_partID       (io_out_bits_mpam_partID),
+    .io_deq_bits_mpam_mpamNS       (io_out_bits_mpam_mpamNS),
+    .io_count                      (_queue_io_count)
+  );
+  assign io_in_lcrdv = io_in_lcrdv_REG;
+  assign io_out_valid = ~_GEN & _queue_io_deq_valid;
+  assign io_out_bits_opcode = _queue_io_deq_bits_opcode;
+  assign io_reclaimLCredit = lcreditInflight == 3'h0;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled_1.sv b/flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled_1.sv
new file mode 100644
index 0000000000..eb75d69e2a
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled_1.sv
@@ -0,0 +1,139 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module LCredit2Decoupled_1(
+  input         clock,
+  input         reset,
+  input         io_in_flitv,
+  input  [72:0] io_in_flit,
+  output        io_in_lcrdv,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_qos,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [4:0]  io_out_bits_opcode,
+  output [1:0]  io_out_bits_respErr,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output [2:0]  io_out_bits_cBusy,
+  output [11:0] io_out_bits_dbID,
+  output [3:0]  io_out_bits_pCrdType,
+  output [1:0]  io_out_bits_tagOp,
+  output        io_out_bits_traceTag,
+  input  [1:0]  io_state_state,
+  output        io_reclaimLCredit
+);
+
+  wire       _GEN;
+  reg  [4:0] lcreditInflight;
+  reg  [4:0] lcreditPool;
+  wire       accept = (|lcreditInflight) & io_in_flitv;
+  reg        io_in_lcrdv_REG;
+  assign _GEN = |(io_in_flit[42:38]);
+  wire       lcreditOut = (|lcreditPool) & io_state_state == 2'h2 & io_out_ready;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      lcreditInflight <= 5'h0;
+      lcreditPool <= 5'hF;
+      io_in_lcrdv_REG <= 1'h0;
+    end
+    else begin
+      if (lcreditOut) begin
+        if (~accept) begin
+          lcreditInflight <= 5'(lcreditInflight + 5'h1);
+          lcreditPool <= 5'(lcreditPool - 5'h1);
+        end
+      end
+      else if (accept) begin
+        lcreditInflight <= 5'(lcreditInflight - 5'h1);
+        lcreditPool <= 5'(lcreditPool + 5'h1);
+      end
+      io_in_lcrdv_REG <= lcreditOut;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        lcreditInflight = _RANDOM[/*Zero width*/ 1'b0][4:0];
+        lcreditPool = _RANDOM[/*Zero width*/ 1'b0][9:5];
+        io_in_lcrdv_REG = _RANDOM[/*Zero width*/ 1'b0][10];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        lcreditInflight = 5'h0;
+        lcreditPool = 5'hF;
+        io_in_lcrdv_REG = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_lcrdv = io_in_lcrdv_REG;
+  assign io_out_valid = accept & _GEN;
+  assign io_out_bits_qos = io_in_flit[3:0];
+  assign io_out_bits_tgtID = io_in_flit[14:4];
+  assign io_out_bits_srcID = io_in_flit[25:15];
+  assign io_out_bits_txnID = io_in_flit[37:26];
+  assign io_out_bits_opcode = io_in_flit[42:38];
+  assign io_out_bits_respErr = io_in_flit[44:43];
+  assign io_out_bits_resp = io_in_flit[47:45];
+  assign io_out_bits_fwdState = io_in_flit[50:48];
+  assign io_out_bits_cBusy = io_in_flit[53:51];
+  assign io_out_bits_dbID = io_in_flit[65:54];
+  assign io_out_bits_pCrdType = io_in_flit[69:66];
+  assign io_out_bits_tagOp = io_in_flit[71:70];
+  assign io_out_bits_traceTag = io_in_flit[72];
+  assign io_reclaimLCredit = lcreditInflight == 5'h0;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled_2.sv b/flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled_2.sv
new file mode 100644
index 0000000000..9267deebbf
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/LCredit2Decoupled_2.sv
@@ -0,0 +1,157 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module LCredit2Decoupled_2(
+  input          clock,
+  input          reset,
+  input          io_in_flitv,
+  input  [421:0] io_in_flit,
+  output         io_in_lcrdv,
+  input          io_out_ready,
+  output         io_out_valid,
+  output [3:0]   io_out_bits_qos,
+  output [10:0]  io_out_bits_tgtID,
+  output [10:0]  io_out_bits_srcID,
+  output [11:0]  io_out_bits_txnID,
+  output [10:0]  io_out_bits_homeNID,
+  output [3:0]   io_out_bits_opcode,
+  output [1:0]   io_out_bits_respErr,
+  output [2:0]   io_out_bits_resp,
+  output [3:0]   io_out_bits_dataSource,
+  output [2:0]   io_out_bits_cBusy,
+  output [11:0]  io_out_bits_dbID,
+  output [1:0]   io_out_bits_ccID,
+  output [1:0]   io_out_bits_dataID,
+  output [1:0]   io_out_bits_tagOp,
+  output [7:0]   io_out_bits_tag,
+  output [1:0]   io_out_bits_tu,
+  output         io_out_bits_traceTag,
+  output [3:0]   io_out_bits_rsvdc,
+  output [31:0]  io_out_bits_be,
+  output [255:0] io_out_bits_data,
+  output [31:0]  io_out_bits_dataCheck,
+  output [3:0]   io_out_bits_poison,
+  input  [1:0]   io_state_state,
+  output         io_reclaimLCredit
+);
+
+  wire       _GEN;
+  reg  [4:0] lcreditInflight;
+  reg  [4:0] lcreditPool;
+  wire       accept = (|lcreditInflight) & io_in_flitv;
+  reg        io_in_lcrdv_REG;
+  assign _GEN = |(io_in_flit[52:49]);
+  wire       lcreditOut = (|lcreditPool) & io_state_state == 2'h2 & io_out_ready;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      lcreditInflight <= 5'h0;
+      lcreditPool <= 5'hF;
+      io_in_lcrdv_REG <= 1'h0;
+    end
+    else begin
+      if (lcreditOut) begin
+        if (~accept) begin
+          lcreditInflight <= 5'(lcreditInflight + 5'h1);
+          lcreditPool <= 5'(lcreditPool - 5'h1);
+        end
+      end
+      else if (accept) begin
+        lcreditInflight <= 5'(lcreditInflight - 5'h1);
+        lcreditPool <= 5'(lcreditPool + 5'h1);
+      end
+      io_in_lcrdv_REG <= lcreditOut;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        lcreditInflight = _RANDOM[/*Zero width*/ 1'b0][4:0];
+        lcreditPool = _RANDOM[/*Zero width*/ 1'b0][9:5];
+        io_in_lcrdv_REG = _RANDOM[/*Zero width*/ 1'b0][10];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        lcreditInflight = 5'h0;
+        lcreditPool = 5'hF;
+        io_in_lcrdv_REG = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_in_lcrdv = io_in_lcrdv_REG;
+  assign io_out_valid = accept & _GEN;
+  assign io_out_bits_qos = io_in_flit[3:0];
+  assign io_out_bits_tgtID = io_in_flit[14:4];
+  assign io_out_bits_srcID = io_in_flit[25:15];
+  assign io_out_bits_txnID = io_in_flit[37:26];
+  assign io_out_bits_homeNID = io_in_flit[48:38];
+  assign io_out_bits_opcode = io_in_flit[52:49];
+  assign io_out_bits_respErr = io_in_flit[54:53];
+  assign io_out_bits_resp = io_in_flit[57:55];
+  assign io_out_bits_dataSource = io_in_flit[61:58];
+  assign io_out_bits_cBusy = io_in_flit[64:62];
+  assign io_out_bits_dbID = io_in_flit[76:65];
+  assign io_out_bits_ccID = io_in_flit[78:77];
+  assign io_out_bits_dataID = io_in_flit[80:79];
+  assign io_out_bits_tagOp = io_in_flit[82:81];
+  assign io_out_bits_tag = io_in_flit[90:83];
+  assign io_out_bits_tu = io_in_flit[92:91];
+  assign io_out_bits_traceTag = io_in_flit[93];
+  assign io_out_bits_rsvdc = io_in_flit[97:94];
+  assign io_out_bits_be = io_in_flit[129:98];
+  assign io_out_bits_data = io_in_flit[385:130];
+  assign io_out_bits_dataCheck = io_in_flit[417:386];
+  assign io_out_bits_poison = io_in_flit[421:418];
+  assign io_reclaimLCredit = lcreditInflight == 5'h0;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/LinkMonitor.sv b/flow/designs/src/xiangshan_coupledl2/deps/LinkMonitor.sv
new file mode 100644
index 0000000000..6033cb82f3
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/LinkMonitor.sv
@@ -0,0 +1,493 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module LinkMonitor(
+  input          clock,
+  input          reset,
+  output         io_in_tx_req_ready,
+  input          io_in_tx_req_valid,
+  input  [3:0]   io_in_tx_req_bits_qos,
+  input  [10:0]  io_in_tx_req_bits_tgtID,
+  input  [11:0]  io_in_tx_req_bits_txnID,
+  input  [10:0]  io_in_tx_req_bits_returnNID,
+  input          io_in_tx_req_bits_stashNIDValid,
+  input  [11:0]  io_in_tx_req_bits_returnTxnID,
+  input  [6:0]   io_in_tx_req_bits_opcode,
+  input  [2:0]   io_in_tx_req_bits_size,
+  input  [47:0]  io_in_tx_req_bits_addr,
+  input          io_in_tx_req_bits_ns,
+  input          io_in_tx_req_bits_likelyshared,
+  input          io_in_tx_req_bits_allowRetry,
+  input  [1:0]   io_in_tx_req_bits_order,
+  input  [3:0]   io_in_tx_req_bits_pCrdType,
+  input          io_in_tx_req_bits_memAttr_allocate,
+  input          io_in_tx_req_bits_memAttr_cacheable,
+  input          io_in_tx_req_bits_memAttr_device,
+  input          io_in_tx_req_bits_memAttr_ewa,
+  input          io_in_tx_req_bits_snpAttr,
+  input  [7:0]   io_in_tx_req_bits_lpIDWithPadding,
+  input          io_in_tx_req_bits_snoopMe,
+  input          io_in_tx_req_bits_expCompAck,
+  input  [1:0]   io_in_tx_req_bits_tagOp,
+  input          io_in_tx_req_bits_traceTag,
+  input          io_in_tx_req_bits_mpam_perfMonGroup,
+  input  [8:0]   io_in_tx_req_bits_mpam_partID,
+  input          io_in_tx_req_bits_mpam_mpamNS,
+  input  [3:0]   io_in_tx_req_bits_rsvdc,
+  output         io_in_tx_rsp_ready,
+  input          io_in_tx_rsp_valid,
+  input  [3:0]   io_in_tx_rsp_bits_qos,
+  input  [10:0]  io_in_tx_rsp_bits_tgtID,
+  input  [11:0]  io_in_tx_rsp_bits_txnID,
+  input  [4:0]   io_in_tx_rsp_bits_opcode,
+  input  [1:0]   io_in_tx_rsp_bits_respErr,
+  input  [2:0]   io_in_tx_rsp_bits_resp,
+  input  [2:0]   io_in_tx_rsp_bits_fwdState,
+  input  [2:0]   io_in_tx_rsp_bits_cBusy,
+  input  [11:0]  io_in_tx_rsp_bits_dbID,
+  input  [3:0]   io_in_tx_rsp_bits_pCrdType,
+  input  [1:0]   io_in_tx_rsp_bits_tagOp,
+  input          io_in_tx_rsp_bits_traceTag,
+  output         io_in_tx_dat_ready,
+  input          io_in_tx_dat_valid,
+  input  [3:0]   io_in_tx_dat_bits_qos,
+  input  [10:0]  io_in_tx_dat_bits_tgtID,
+  input  [11:0]  io_in_tx_dat_bits_txnID,
+  input  [10:0]  io_in_tx_dat_bits_homeNID,
+  input  [3:0]   io_in_tx_dat_bits_opcode,
+  input  [1:0]   io_in_tx_dat_bits_respErr,
+  input  [2:0]   io_in_tx_dat_bits_resp,
+  input  [3:0]   io_in_tx_dat_bits_dataSource,
+  input  [2:0]   io_in_tx_dat_bits_cBusy,
+  input  [11:0]  io_in_tx_dat_bits_dbID,
+  input  [1:0]   io_in_tx_dat_bits_ccID,
+  input  [1:0]   io_in_tx_dat_bits_dataID,
+  input  [1:0]   io_in_tx_dat_bits_tagOp,
+  input  [7:0]   io_in_tx_dat_bits_tag,
+  input  [1:0]   io_in_tx_dat_bits_tu,
+  input          io_in_tx_dat_bits_traceTag,
+  input  [3:0]   io_in_tx_dat_bits_rsvdc,
+  input  [31:0]  io_in_tx_dat_bits_be,
+  input  [255:0] io_in_tx_dat_bits_data,
+  input  [31:0]  io_in_tx_dat_bits_dataCheck,
+  input  [3:0]   io_in_tx_dat_bits_poison,
+  input          io_in_rx_rsp_ready,
+  output         io_in_rx_rsp_valid,
+  output [3:0]   io_in_rx_rsp_bits_qos,
+  output [10:0]  io_in_rx_rsp_bits_tgtID,
+  output [10:0]  io_in_rx_rsp_bits_srcID,
+  output [11:0]  io_in_rx_rsp_bits_txnID,
+  output [4:0]   io_in_rx_rsp_bits_opcode,
+  output [1:0]   io_in_rx_rsp_bits_respErr,
+  output [2:0]   io_in_rx_rsp_bits_resp,
+  output [2:0]   io_in_rx_rsp_bits_fwdState,
+  output [2:0]   io_in_rx_rsp_bits_cBusy,
+  output [11:0]  io_in_rx_rsp_bits_dbID,
+  output [3:0]   io_in_rx_rsp_bits_pCrdType,
+  output [1:0]   io_in_rx_rsp_bits_tagOp,
+  output         io_in_rx_rsp_bits_traceTag,
+  input          io_in_rx_dat_ready,
+  output         io_in_rx_dat_valid,
+  output [3:0]   io_in_rx_dat_bits_qos,
+  output [10:0]  io_in_rx_dat_bits_tgtID,
+  output [10:0]  io_in_rx_dat_bits_srcID,
+  output [11:0]  io_in_rx_dat_bits_txnID,
+  output [10:0]  io_in_rx_dat_bits_homeNID,
+  output [3:0]   io_in_rx_dat_bits_opcode,
+  output [1:0]   io_in_rx_dat_bits_respErr,
+  output [2:0]   io_in_rx_dat_bits_resp,
+  output [3:0]   io_in_rx_dat_bits_dataSource,
+  output [2:0]   io_in_rx_dat_bits_cBusy,
+  output [11:0]  io_in_rx_dat_bits_dbID,
+  output [1:0]   io_in_rx_dat_bits_ccID,
+  output [1:0]   io_in_rx_dat_bits_dataID,
+  output [1:0]   io_in_rx_dat_bits_tagOp,
+  output [7:0]   io_in_rx_dat_bits_tag,
+  output [1:0]   io_in_rx_dat_bits_tu,
+  output         io_in_rx_dat_bits_traceTag,
+  output [3:0]   io_in_rx_dat_bits_rsvdc,
+  output [31:0]  io_in_rx_dat_bits_be,
+  output [255:0] io_in_rx_dat_bits_data,
+  output [31:0]  io_in_rx_dat_bits_dataCheck,
+  output [3:0]   io_in_rx_dat_bits_poison,
+  input          io_in_rx_snp_ready,
+  output         io_in_rx_snp_valid,
+  output [3:0]   io_in_rx_snp_bits_qos,
+  output [10:0]  io_in_rx_snp_bits_srcID,
+  output [11:0]  io_in_rx_snp_bits_txnID,
+  output [10:0]  io_in_rx_snp_bits_fwdNID,
+  output [11:0]  io_in_rx_snp_bits_fwdTxnID,
+  output [4:0]   io_in_rx_snp_bits_opcode,
+  output [44:0]  io_in_rx_snp_bits_addr,
+  output         io_in_rx_snp_bits_ns,
+  output         io_in_rx_snp_bits_doNotGoToSD,
+  output         io_in_rx_snp_bits_retToSrc,
+  output         io_in_rx_snp_bits_traceTag,
+  output         io_in_rx_snp_bits_mpam_perfMonGroup,
+  output [8:0]   io_in_rx_snp_bits_mpam_partID,
+  output         io_in_rx_snp_bits_mpam_mpamNS,
+  output         io_out_txsactive,
+  input          io_out_rxsactive,
+  output         io_out_syscoreq,
+  input          io_out_syscoack,
+  output         io_out_tx_linkactivereq,
+  input          io_out_tx_linkactiveack,
+  output         io_out_tx_req_flitpend,
+  output         io_out_tx_req_flitv,
+  output [161:0] io_out_tx_req_flit,
+  input          io_out_tx_req_lcrdv,
+  output         io_out_tx_rsp_flitpend,
+  output         io_out_tx_rsp_flitv,
+  output [72:0]  io_out_tx_rsp_flit,
+  input          io_out_tx_rsp_lcrdv,
+  output         io_out_tx_dat_flitpend,
+  output         io_out_tx_dat_flitv,
+  output [421:0] io_out_tx_dat_flit,
+  input          io_out_tx_dat_lcrdv,
+  input          io_out_rx_linkactivereq,
+  output         io_out_rx_linkactiveack,
+  input          io_out_rx_rsp_flitpend,
+  input          io_out_rx_rsp_flitv,
+  input  [72:0]  io_out_rx_rsp_flit,
+  output         io_out_rx_rsp_lcrdv,
+  input          io_out_rx_dat_flitpend,
+  input          io_out_rx_dat_flitv,
+  input  [421:0] io_out_rx_dat_flit,
+  output         io_out_rx_dat_lcrdv,
+  input          io_out_rx_snp_flitpend,
+  input          io_out_rx_snp_flitv,
+  input  [114:0] io_out_rx_snp_flit,
+  output         io_out_rx_snp_lcrdv,
+  input  [10:0]  io_nodeID
+);
+
+  wire            _LCredit2Decoupled_rxdat_io_reclaimLCredit;
+  wire            _LCredit2Decoupled_rxrsp_io_out_valid;
+  wire [4:0]      _LCredit2Decoupled_rxrsp_io_out_bits_opcode;
+  wire            _LCredit2Decoupled_rxrsp_io_reclaimLCredit;
+  wire            _LCredit2Decoupled_rxsnp_io_reclaimLCredit;
+  wire            _Decoupled2LCredit_txreq_io_in_ready;
+  reg  [1:0]      txState;
+  reg  [1:0]      rxState;
+  reg             exitcoDone_REG;
+  reg             io_out_tx_linkactivereq_REG;
+  reg             io_out_rx_linkactiveack_REG;
+  reg             io_out_rx_linkactiveack_REG_1;
+  reg             io_out_syscoreq_REG;
+  reg             io_out_txsactive_REG;
+  reg  [63:0]     retryAckCnt;
+  reg  [63:0]     pCrdGrantCnt;
+  reg  [63:0]     noAllowRetryCnt;
+  wire [1:0]      _txState_T = {io_out_tx_linkactivereq_REG, io_out_tx_linkactiveack};
+  wire [1:0]      _rxState_T = {io_out_rx_linkactivereq, io_out_rx_linkactiveack_REG_1};
+  wire            exitcoDone = ~io_out_syscoreq_REG & ~io_out_syscoack & exitcoDone_REG;
+  wire            _GEN = io_in_rx_rsp_ready & _LCredit2Decoupled_rxrsp_io_out_valid;
+  wire [3:0][1:0] _GEN_0 = {{2'h2}, {{1'h0, _txState_T == 2'h2}}, {2'h3}, {2'h0}};
+  wire [3:0][1:0] _GEN_1 = {{2'h2}, {{1'h0, _rxState_T == 2'h2}}, {2'h3}, {2'h0}};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      txState <= 2'h0;
+      rxState <= 2'h0;
+      exitcoDone_REG <= 1'h0;
+      io_out_tx_linkactivereq_REG <= 1'h0;
+      io_out_rx_linkactiveack_REG_1 <= 1'h0;
+      io_out_syscoreq_REG <= 1'h0;
+      io_out_txsactive_REG <= 1'h0;
+      retryAckCnt <= 64'h0;
+      pCrdGrantCnt <= 64'h0;
+      noAllowRetryCnt <= 64'h0;
+    end
+    else begin
+      txState <= _GEN_0[_txState_T];
+      rxState <= _GEN_1[_rxState_T];
+      exitcoDone_REG <= 1'h1;
+      io_out_tx_linkactivereq_REG <= ~exitcoDone;
+      io_out_rx_linkactiveack_REG_1 <=
+        io_out_rx_linkactiveack_REG
+        | ~(_LCredit2Decoupled_rxsnp_io_reclaimLCredit
+            & _LCredit2Decoupled_rxrsp_io_reclaimLCredit
+            & _LCredit2Decoupled_rxdat_io_reclaimLCredit);
+      io_out_syscoreq_REG <= 1'h1;
+      io_out_txsactive_REG <= ~exitcoDone;
+      if (_GEN & _LCredit2Decoupled_rxrsp_io_out_bits_opcode == 5'h3)
+        retryAckCnt <= 64'(retryAckCnt + 64'h1);
+      if (_GEN & _LCredit2Decoupled_rxrsp_io_out_bits_opcode == 5'h7)
+        pCrdGrantCnt <= 64'(pCrdGrantCnt + 64'h1);
+      if (_Decoupled2LCredit_txreq_io_in_ready & io_in_tx_req_valid
+          & ~io_in_tx_req_bits_allowRetry)
+        noAllowRetryCnt <= 64'(noAllowRetryCnt + 64'h1);
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock)
+    io_out_rx_linkactiveack_REG <= io_out_rx_linkactivereq;
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:6];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h7; i += 3'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        txState = _RANDOM[3'h0][1:0];
+        rxState = _RANDOM[3'h0][3:2];
+        exitcoDone_REG = _RANDOM[3'h0][4];
+        io_out_tx_linkactivereq_REG = _RANDOM[3'h0][5];
+        io_out_rx_linkactiveack_REG = _RANDOM[3'h0][6];
+        io_out_rx_linkactiveack_REG_1 = _RANDOM[3'h0][7];
+        io_out_syscoreq_REG = _RANDOM[3'h0][8];
+        io_out_txsactive_REG = _RANDOM[3'h0][9];
+        retryAckCnt = {_RANDOM[3'h0][31:10], _RANDOM[3'h1], _RANDOM[3'h2][9:0]};
+        pCrdGrantCnt = {_RANDOM[3'h2][31:10], _RANDOM[3'h3], _RANDOM[3'h4][9:0]};
+        noAllowRetryCnt = {_RANDOM[3'h4][31:10], _RANDOM[3'h5], _RANDOM[3'h6][9:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        txState = 2'h0;
+        rxState = 2'h0;
+        exitcoDone_REG = 1'h0;
+        io_out_tx_linkactivereq_REG = 1'h0;
+        io_out_rx_linkactiveack_REG_1 = 1'h0;
+        io_out_syscoreq_REG = 1'h0;
+        io_out_txsactive_REG = 1'h0;
+        retryAckCnt = 64'h0;
+        pCrdGrantCnt = 64'h0;
+        noAllowRetryCnt = 64'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  Decoupled2LCredit Decoupled2LCredit_txreq (
+    .clock                        (clock),
+    .reset                        (reset),
+    .io_in_ready                  (_Decoupled2LCredit_txreq_io_in_ready),
+    .io_in_valid                  (io_in_tx_req_valid),
+    .io_in_bits_qos               (io_in_tx_req_bits_qos),
+    .io_in_bits_tgtID             (io_in_tx_req_bits_tgtID),
+    .io_in_bits_srcID             (io_nodeID),
+    .io_in_bits_txnID             (io_in_tx_req_bits_txnID),
+    .io_in_bits_returnNID         (io_in_tx_req_bits_returnNID),
+    .io_in_bits_stashNIDValid     (io_in_tx_req_bits_stashNIDValid),
+    .io_in_bits_returnTxnID       (io_in_tx_req_bits_returnTxnID),
+    .io_in_bits_opcode            (io_in_tx_req_bits_opcode),
+    .io_in_bits_size              (io_in_tx_req_bits_size),
+    .io_in_bits_addr              (io_in_tx_req_bits_addr),
+    .io_in_bits_ns                (io_in_tx_req_bits_ns),
+    .io_in_bits_likelyshared      (io_in_tx_req_bits_likelyshared),
+    .io_in_bits_allowRetry        (io_in_tx_req_bits_allowRetry),
+    .io_in_bits_order             (io_in_tx_req_bits_order),
+    .io_in_bits_pCrdType          (io_in_tx_req_bits_pCrdType),
+    .io_in_bits_memAttr_allocate  (io_in_tx_req_bits_memAttr_allocate),
+    .io_in_bits_memAttr_cacheable (io_in_tx_req_bits_memAttr_cacheable),
+    .io_in_bits_memAttr_device    (io_in_tx_req_bits_memAttr_device),
+    .io_in_bits_memAttr_ewa       (io_in_tx_req_bits_memAttr_ewa),
+    .io_in_bits_snpAttr           (io_in_tx_req_bits_snpAttr),
+    .io_in_bits_lpIDWithPadding   (io_in_tx_req_bits_lpIDWithPadding),
+    .io_in_bits_snoopMe           (io_in_tx_req_bits_snoopMe),
+    .io_in_bits_expCompAck        (io_in_tx_req_bits_expCompAck),
+    .io_in_bits_tagOp             (io_in_tx_req_bits_tagOp),
+    .io_in_bits_traceTag          (io_in_tx_req_bits_traceTag),
+    .io_in_bits_mpam_perfMonGroup (io_in_tx_req_bits_mpam_perfMonGroup),
+    .io_in_bits_mpam_partID       (io_in_tx_req_bits_mpam_partID),
+    .io_in_bits_mpam_mpamNS       (io_in_tx_req_bits_mpam_mpamNS),
+    .io_in_bits_rsvdc             (io_in_tx_req_bits_rsvdc),
+    .io_out_flitpend              (io_out_tx_req_flitpend),
+    .io_out_flitv                 (io_out_tx_req_flitv),
+    .io_out_flit                  (io_out_tx_req_flit),
+    .io_out_lcrdv                 (io_out_tx_req_lcrdv),
+    .io_state_state               (txState)
+  );
+  Decoupled2LCredit_1 Decoupled2LCredit_txrsp (
+    .clock               (clock),
+    .reset               (reset),
+    .io_in_ready         (io_in_tx_rsp_ready),
+    .io_in_valid         (io_in_tx_rsp_valid),
+    .io_in_bits_qos      (io_in_tx_rsp_bits_qos),
+    .io_in_bits_tgtID    (io_in_tx_rsp_bits_tgtID),
+    .io_in_bits_srcID    (io_nodeID),
+    .io_in_bits_txnID    (io_in_tx_rsp_bits_txnID),
+    .io_in_bits_opcode   (io_in_tx_rsp_bits_opcode),
+    .io_in_bits_respErr  (io_in_tx_rsp_bits_respErr),
+    .io_in_bits_resp     (io_in_tx_rsp_bits_resp),
+    .io_in_bits_fwdState (io_in_tx_rsp_bits_fwdState),
+    .io_in_bits_cBusy    (io_in_tx_rsp_bits_cBusy),
+    .io_in_bits_dbID     (io_in_tx_rsp_bits_dbID),
+    .io_in_bits_pCrdType (io_in_tx_rsp_bits_pCrdType),
+    .io_in_bits_tagOp    (io_in_tx_rsp_bits_tagOp),
+    .io_in_bits_traceTag (io_in_tx_rsp_bits_traceTag),
+    .io_out_flitpend     (io_out_tx_rsp_flitpend),
+    .io_out_flitv        (io_out_tx_rsp_flitv),
+    .io_out_flit         (io_out_tx_rsp_flit),
+    .io_out_lcrdv        (io_out_tx_rsp_lcrdv),
+    .io_state_state      (txState)
+  );
+  Decoupled2LCredit_2 Decoupled2LCredit_txdat (
+    .clock                 (clock),
+    .reset                 (reset),
+    .io_in_ready           (io_in_tx_dat_ready),
+    .io_in_valid           (io_in_tx_dat_valid),
+    .io_in_bits_qos        (io_in_tx_dat_bits_qos),
+    .io_in_bits_tgtID      (io_in_tx_dat_bits_tgtID),
+    .io_in_bits_srcID      (io_nodeID),
+    .io_in_bits_txnID      (io_in_tx_dat_bits_txnID),
+    .io_in_bits_homeNID    (io_in_tx_dat_bits_homeNID),
+    .io_in_bits_opcode     (io_in_tx_dat_bits_opcode),
+    .io_in_bits_respErr    (io_in_tx_dat_bits_respErr),
+    .io_in_bits_resp       (io_in_tx_dat_bits_resp),
+    .io_in_bits_dataSource (io_in_tx_dat_bits_dataSource),
+    .io_in_bits_cBusy      (io_in_tx_dat_bits_cBusy),
+    .io_in_bits_dbID       (io_in_tx_dat_bits_dbID),
+    .io_in_bits_ccID       (io_in_tx_dat_bits_ccID),
+    .io_in_bits_dataID     (io_in_tx_dat_bits_dataID),
+    .io_in_bits_tagOp      (io_in_tx_dat_bits_tagOp),
+    .io_in_bits_tag        (io_in_tx_dat_bits_tag),
+    .io_in_bits_tu         (io_in_tx_dat_bits_tu),
+    .io_in_bits_traceTag   (io_in_tx_dat_bits_traceTag),
+    .io_in_bits_rsvdc      (io_in_tx_dat_bits_rsvdc),
+    .io_in_bits_be         (io_in_tx_dat_bits_be),
+    .io_in_bits_data       (io_in_tx_dat_bits_data),
+    .io_in_bits_dataCheck  (io_in_tx_dat_bits_dataCheck),
+    .io_in_bits_poison     (io_in_tx_dat_bits_poison),
+    .io_out_flitpend       (io_out_tx_dat_flitpend),
+    .io_out_flitv          (io_out_tx_dat_flitv),
+    .io_out_flit           (io_out_tx_dat_flit),
+    .io_out_lcrdv          (io_out_tx_dat_lcrdv),
+    .io_state_state        (txState)
+  );
+  LCredit2Decoupled LCredit2Decoupled_rxsnp (
+    .clock                         (clock),
+    .reset                         (reset),
+    .io_in_flitv                   (io_out_rx_snp_flitv),
+    .io_in_flit                    (io_out_rx_snp_flit),
+    .io_in_lcrdv                   (io_out_rx_snp_lcrdv),
+    .io_out_ready                  (io_in_rx_snp_ready),
+    .io_out_valid                  (io_in_rx_snp_valid),
+    .io_out_bits_qos               (io_in_rx_snp_bits_qos),
+    .io_out_bits_srcID             (io_in_rx_snp_bits_srcID),
+    .io_out_bits_txnID             (io_in_rx_snp_bits_txnID),
+    .io_out_bits_fwdNID            (io_in_rx_snp_bits_fwdNID),
+    .io_out_bits_fwdTxnID          (io_in_rx_snp_bits_fwdTxnID),
+    .io_out_bits_opcode            (io_in_rx_snp_bits_opcode),
+    .io_out_bits_addr              (io_in_rx_snp_bits_addr),
+    .io_out_bits_ns                (io_in_rx_snp_bits_ns),
+    .io_out_bits_doNotGoToSD       (io_in_rx_snp_bits_doNotGoToSD),
+    .io_out_bits_retToSrc          (io_in_rx_snp_bits_retToSrc),
+    .io_out_bits_traceTag          (io_in_rx_snp_bits_traceTag),
+    .io_out_bits_mpam_perfMonGroup (io_in_rx_snp_bits_mpam_perfMonGroup),
+    .io_out_bits_mpam_partID       (io_in_rx_snp_bits_mpam_partID),
+    .io_out_bits_mpam_mpamNS       (io_in_rx_snp_bits_mpam_mpamNS),
+    .io_state_state                (rxState),
+    .io_reclaimLCredit             (_LCredit2Decoupled_rxsnp_io_reclaimLCredit)
+  );
+  LCredit2Decoupled_1 LCredit2Decoupled_rxrsp (
+    .clock                (clock),
+    .reset                (reset),
+    .io_in_flitv          (io_out_rx_rsp_flitv),
+    .io_in_flit           (io_out_rx_rsp_flit),
+    .io_in_lcrdv          (io_out_rx_rsp_lcrdv),
+    .io_out_ready         (io_in_rx_rsp_ready),
+    .io_out_valid         (_LCredit2Decoupled_rxrsp_io_out_valid),
+    .io_out_bits_qos      (io_in_rx_rsp_bits_qos),
+    .io_out_bits_tgtID    (io_in_rx_rsp_bits_tgtID),
+    .io_out_bits_srcID    (io_in_rx_rsp_bits_srcID),
+    .io_out_bits_txnID    (io_in_rx_rsp_bits_txnID),
+    .io_out_bits_opcode   (_LCredit2Decoupled_rxrsp_io_out_bits_opcode),
+    .io_out_bits_respErr  (io_in_rx_rsp_bits_respErr),
+    .io_out_bits_resp     (io_in_rx_rsp_bits_resp),
+    .io_out_bits_fwdState (io_in_rx_rsp_bits_fwdState),
+    .io_out_bits_cBusy    (io_in_rx_rsp_bits_cBusy),
+    .io_out_bits_dbID     (io_in_rx_rsp_bits_dbID),
+    .io_out_bits_pCrdType (io_in_rx_rsp_bits_pCrdType),
+    .io_out_bits_tagOp    (io_in_rx_rsp_bits_tagOp),
+    .io_out_bits_traceTag (io_in_rx_rsp_bits_traceTag),
+    .io_state_state       (rxState),
+    .io_reclaimLCredit    (_LCredit2Decoupled_rxrsp_io_reclaimLCredit)
+  );
+  LCredit2Decoupled_2 LCredit2Decoupled_rxdat (
+    .clock                  (clock),
+    .reset                  (reset),
+    .io_in_flitv            (io_out_rx_dat_flitv),
+    .io_in_flit             (io_out_rx_dat_flit),
+    .io_in_lcrdv            (io_out_rx_dat_lcrdv),
+    .io_out_ready           (io_in_rx_dat_ready),
+    .io_out_valid           (io_in_rx_dat_valid),
+    .io_out_bits_qos        (io_in_rx_dat_bits_qos),
+    .io_out_bits_tgtID      (io_in_rx_dat_bits_tgtID),
+    .io_out_bits_srcID      (io_in_rx_dat_bits_srcID),
+    .io_out_bits_txnID      (io_in_rx_dat_bits_txnID),
+    .io_out_bits_homeNID    (io_in_rx_dat_bits_homeNID),
+    .io_out_bits_opcode     (io_in_rx_dat_bits_opcode),
+    .io_out_bits_respErr    (io_in_rx_dat_bits_respErr),
+    .io_out_bits_resp       (io_in_rx_dat_bits_resp),
+    .io_out_bits_dataSource (io_in_rx_dat_bits_dataSource),
+    .io_out_bits_cBusy      (io_in_rx_dat_bits_cBusy),
+    .io_out_bits_dbID       (io_in_rx_dat_bits_dbID),
+    .io_out_bits_ccID       (io_in_rx_dat_bits_ccID),
+    .io_out_bits_dataID     (io_in_rx_dat_bits_dataID),
+    .io_out_bits_tagOp      (io_in_rx_dat_bits_tagOp),
+    .io_out_bits_tag        (io_in_rx_dat_bits_tag),
+    .io_out_bits_tu         (io_in_rx_dat_bits_tu),
+    .io_out_bits_traceTag   (io_in_rx_dat_bits_traceTag),
+    .io_out_bits_rsvdc      (io_in_rx_dat_bits_rsvdc),
+    .io_out_bits_be         (io_in_rx_dat_bits_be),
+    .io_out_bits_data       (io_in_rx_dat_bits_data),
+    .io_out_bits_dataCheck  (io_in_rx_dat_bits_dataCheck),
+    .io_out_bits_poison     (io_in_rx_dat_bits_poison),
+    .io_state_state         (rxState),
+    .io_reclaimLCredit      (_LCredit2Decoupled_rxdat_io_reclaimLCredit)
+  );
+  assign io_in_tx_req_ready = _Decoupled2LCredit_txreq_io_in_ready;
+  assign io_in_rx_rsp_valid = _LCredit2Decoupled_rxrsp_io_out_valid;
+  assign io_in_rx_rsp_bits_opcode = _LCredit2Decoupled_rxrsp_io_out_bits_opcode;
+  assign io_out_txsactive = io_out_txsactive_REG;
+  assign io_out_syscoreq = io_out_syscoreq_REG;
+  assign io_out_tx_linkactivereq = io_out_tx_linkactivereq_REG;
+  assign io_out_rx_linkactiveack = io_out_rx_linkactiveack_REG_1;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridge.sv b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridge.sv
new file mode 100644
index 0000000000..6381483dc8
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridge.sv
@@ -0,0 +1,2607 @@
+// Generated by CIRCT firtool-1.135.0
+module MMIOBridge(
+  input          clock,
+  input          reset,
+  output         auto_mmio_in_a_ready,
+  input          auto_mmio_in_a_valid,
+  input  [3:0]   auto_mmio_in_a_bits_opcode,
+  input  [2:0]   auto_mmio_in_a_bits_param,
+  input  [1:0]   auto_mmio_in_a_bits_size,
+  input  [4:0]   auto_mmio_in_a_bits_source,
+  input  [47:0]  auto_mmio_in_a_bits_address,
+  input          auto_mmio_in_a_bits_user_memBackType_MM,
+  input          auto_mmio_in_a_bits_user_memPageType_NC,
+  input  [7:0]   auto_mmio_in_a_bits_mask,
+  input  [63:0]  auto_mmio_in_a_bits_data,
+  input          auto_mmio_in_a_bits_corrupt,
+  input          auto_mmio_in_d_ready,
+  output         auto_mmio_in_d_valid,
+  output [3:0]   auto_mmio_in_d_bits_opcode,
+  output [1:0]   auto_mmio_in_d_bits_param,
+  output [1:0]   auto_mmio_in_d_bits_size,
+  output [4:0]   auto_mmio_in_d_bits_source,
+  output         auto_mmio_in_d_bits_sink,
+  output         auto_mmio_in_d_bits_denied,
+  output [63:0]  auto_mmio_in_d_bits_data,
+  output         auto_mmio_in_d_bits_corrupt,
+  input          io_tx_req_ready,
+  output         io_tx_req_valid,
+  output [3:0]   io_tx_req_bits_qos,
+  output [10:0]  io_tx_req_bits_tgtID,
+  output [10:0]  io_tx_req_bits_srcID,
+  output [11:0]  io_tx_req_bits_txnID,
+  output [10:0]  io_tx_req_bits_returnNID,
+  output         io_tx_req_bits_stashNIDValid,
+  output [11:0]  io_tx_req_bits_returnTxnID,
+  output [6:0]   io_tx_req_bits_opcode,
+  output [2:0]   io_tx_req_bits_size,
+  output [47:0]  io_tx_req_bits_addr,
+  output         io_tx_req_bits_ns,
+  output         io_tx_req_bits_likelyshared,
+  output         io_tx_req_bits_allowRetry,
+  output [1:0]   io_tx_req_bits_order,
+  output [3:0]   io_tx_req_bits_pCrdType,
+  output         io_tx_req_bits_memAttr_allocate,
+  output         io_tx_req_bits_memAttr_cacheable,
+  output         io_tx_req_bits_memAttr_device,
+  output         io_tx_req_bits_memAttr_ewa,
+  output         io_tx_req_bits_snpAttr,
+  output [7:0]   io_tx_req_bits_lpIDWithPadding,
+  output         io_tx_req_bits_snoopMe,
+  output         io_tx_req_bits_expCompAck,
+  output [1:0]   io_tx_req_bits_tagOp,
+  output         io_tx_req_bits_traceTag,
+  output         io_tx_req_bits_mpam_perfMonGroup,
+  output [8:0]   io_tx_req_bits_mpam_partID,
+  output         io_tx_req_bits_mpam_mpamNS,
+  output [3:0]   io_tx_req_bits_rsvdc,
+  input          io_tx_dat_ready,
+  output         io_tx_dat_valid,
+  output [3:0]   io_tx_dat_bits_qos,
+  output [10:0]  io_tx_dat_bits_tgtID,
+  output [10:0]  io_tx_dat_bits_srcID,
+  output [11:0]  io_tx_dat_bits_txnID,
+  output [10:0]  io_tx_dat_bits_homeNID,
+  output [3:0]   io_tx_dat_bits_opcode,
+  output [1:0]   io_tx_dat_bits_respErr,
+  output [2:0]   io_tx_dat_bits_resp,
+  output [3:0]   io_tx_dat_bits_dataSource,
+  output [2:0]   io_tx_dat_bits_cBusy,
+  output [11:0]  io_tx_dat_bits_dbID,
+  output [1:0]   io_tx_dat_bits_ccID,
+  output [1:0]   io_tx_dat_bits_dataID,
+  output [1:0]   io_tx_dat_bits_tagOp,
+  output [7:0]   io_tx_dat_bits_tag,
+  output [1:0]   io_tx_dat_bits_tu,
+  output         io_tx_dat_bits_traceTag,
+  output [3:0]   io_tx_dat_bits_rsvdc,
+  output [31:0]  io_tx_dat_bits_be,
+  output [255:0] io_tx_dat_bits_data,
+  output [31:0]  io_tx_dat_bits_dataCheck,
+  output [3:0]   io_tx_dat_bits_poison,
+  output         io_rx_rsp_ready,
+  input          io_rx_rsp_valid,
+  input  [3:0]   io_rx_rsp_bits_qos,
+  input  [10:0]  io_rx_rsp_bits_tgtID,
+  input  [10:0]  io_rx_rsp_bits_srcID,
+  input  [11:0]  io_rx_rsp_bits_txnID,
+  input  [4:0]   io_rx_rsp_bits_opcode,
+  input  [1:0]   io_rx_rsp_bits_respErr,
+  input  [2:0]   io_rx_rsp_bits_resp,
+  input  [2:0]   io_rx_rsp_bits_fwdState,
+  input  [2:0]   io_rx_rsp_bits_cBusy,
+  input  [11:0]  io_rx_rsp_bits_dbID,
+  input  [3:0]   io_rx_rsp_bits_pCrdType,
+  input  [1:0]   io_rx_rsp_bits_tagOp,
+  input          io_rx_rsp_bits_traceTag,
+  output         io_rx_dat_ready,
+  input          io_rx_dat_valid,
+  input  [3:0]   io_rx_dat_bits_qos,
+  input  [10:0]  io_rx_dat_bits_tgtID,
+  input  [10:0]  io_rx_dat_bits_srcID,
+  input  [11:0]  io_rx_dat_bits_txnID,
+  input  [10:0]  io_rx_dat_bits_homeNID,
+  input  [3:0]   io_rx_dat_bits_opcode,
+  input  [1:0]   io_rx_dat_bits_respErr,
+  input  [2:0]   io_rx_dat_bits_resp,
+  input  [3:0]   io_rx_dat_bits_dataSource,
+  input  [2:0]   io_rx_dat_bits_cBusy,
+  input  [11:0]  io_rx_dat_bits_dbID,
+  input  [1:0]   io_rx_dat_bits_ccID,
+  input  [1:0]   io_rx_dat_bits_dataID,
+  input  [1:0]   io_rx_dat_bits_tagOp,
+  input  [7:0]   io_rx_dat_bits_tag,
+  input  [1:0]   io_rx_dat_bits_tu,
+  input          io_rx_dat_bits_traceTag,
+  input  [3:0]   io_rx_dat_bits_rsvdc,
+  input  [31:0]  io_rx_dat_bits_be,
+  input  [255:0] io_rx_dat_bits_data,
+  input  [31:0]  io_rx_dat_bits_dataCheck,
+  input  [3:0]   io_rx_dat_bits_poison,
+  output         io_pCrd_0_query_valid,
+  output [3:0]   io_pCrd_0_query_bits_pCrdType,
+  output [10:0]  io_pCrd_0_query_bits_srcID,
+  input          io_pCrd_0_grant,
+  output         io_pCrd_1_query_valid,
+  output [3:0]   io_pCrd_1_query_bits_pCrdType,
+  output [10:0]  io_pCrd_1_query_bits_srcID,
+  input          io_pCrd_1_grant,
+  output         io_pCrd_2_query_valid,
+  output [3:0]   io_pCrd_2_query_bits_pCrdType,
+  output [10:0]  io_pCrd_2_query_bits_srcID,
+  input          io_pCrd_2_grant,
+  output         io_pCrd_3_query_valid,
+  output [3:0]   io_pCrd_3_query_bits_pCrdType,
+  output [10:0]  io_pCrd_3_query_bits_srcID,
+  input          io_pCrd_3_grant,
+  output         io_pCrd_4_query_valid,
+  output [3:0]   io_pCrd_4_query_bits_pCrdType,
+  output [10:0]  io_pCrd_4_query_bits_srcID,
+  input          io_pCrd_4_grant,
+  output         io_pCrd_5_query_valid,
+  output [3:0]   io_pCrd_5_query_bits_pCrdType,
+  output [10:0]  io_pCrd_5_query_bits_srcID,
+  input          io_pCrd_5_grant,
+  output         io_pCrd_6_query_valid,
+  output [3:0]   io_pCrd_6_query_bits_pCrdType,
+  output [10:0]  io_pCrd_6_query_bits_srcID,
+  input          io_pCrd_6_grant,
+  output         io_pCrd_7_query_valid,
+  output [3:0]   io_pCrd_7_query_bits_pCrdType,
+  output [10:0]  io_pCrd_7_query_bits_srcID,
+  input          io_pCrd_7_grant,
+  output         io_pCrd_8_query_valid,
+  output [3:0]   io_pCrd_8_query_bits_pCrdType,
+  output [10:0]  io_pCrd_8_query_bits_srcID,
+  input          io_pCrd_8_grant,
+  output         io_pCrd_9_query_valid,
+  output [3:0]   io_pCrd_9_query_bits_pCrdType,
+  output [10:0]  io_pCrd_9_query_bits_srcID,
+  input          io_pCrd_9_grant,
+  output         io_pCrd_10_query_valid,
+  output [3:0]   io_pCrd_10_query_bits_pCrdType,
+  output [10:0]  io_pCrd_10_query_bits_srcID,
+  input          io_pCrd_10_grant,
+  output         io_pCrd_11_query_valid,
+  output [3:0]   io_pCrd_11_query_bits_pCrdType,
+  output [10:0]  io_pCrd_11_query_bits_srcID,
+  input          io_pCrd_11_grant,
+  output         io_pCrd_12_query_valid,
+  output [3:0]   io_pCrd_12_query_bits_pCrdType,
+  output [10:0]  io_pCrd_12_query_bits_srcID,
+  input          io_pCrd_12_grant,
+  output         io_pCrd_13_query_valid,
+  output [3:0]   io_pCrd_13_query_bits_pCrdType,
+  output [10:0]  io_pCrd_13_query_bits_srcID,
+  input          io_pCrd_13_grant,
+  output         io_pCrd_14_query_valid,
+  output [3:0]   io_pCrd_14_query_bits_pCrdType,
+  output [10:0]  io_pCrd_14_query_bits_srcID,
+  input          io_pCrd_14_grant,
+  output         io_pCrd_15_query_valid,
+  output [3:0]   io_pCrd_15_query_bits_pCrdType,
+  output [10:0]  io_pCrd_15_query_bits_srcID,
+  input          io_pCrd_15_grant
+);
+
+  wire         mmioNodeIn_d_bits_corrupt;
+  wire [63:0]  mmioNodeIn_d_bits_data;
+  wire         mmioNodeIn_d_bits_denied;
+  wire [4:0]   mmioNodeIn_d_bits_source;
+  wire [1:0]   mmioNodeIn_d_bits_size;
+  wire [3:0]   mmioNodeIn_d_bits_opcode;
+  wire         mmioNodeIn_d_valid;
+  wire         _mmio_channel_D_arb_io_in_0_ready;
+  wire         _mmio_channel_D_arb_io_in_1_ready;
+  wire         _mmio_channel_D_arb_io_in_2_ready;
+  wire         _mmio_channel_D_arb_io_in_3_ready;
+  wire         _mmio_channel_D_arb_io_in_4_ready;
+  wire         _mmio_channel_D_arb_io_in_5_ready;
+  wire         _mmio_channel_D_arb_io_in_6_ready;
+  wire         _mmio_channel_D_arb_io_in_7_ready;
+  wire         _mmio_channel_D_arb_io_in_8_ready;
+  wire         _mmio_channel_D_arb_io_in_9_ready;
+  wire         _mmio_channel_D_arb_io_in_10_ready;
+  wire         _mmio_channel_D_arb_io_in_11_ready;
+  wire         _mmio_channel_D_arb_io_in_12_ready;
+  wire         _mmio_channel_D_arb_io_in_13_ready;
+  wire         _mmio_channel_D_arb_io_in_14_ready;
+  wire         _mmio_channel_D_arb_io_in_15_ready;
+  wire         _mmio_txdat_arb_io_in_0_ready;
+  wire         _mmio_txdat_arb_io_in_1_ready;
+  wire         _mmio_txdat_arb_io_in_2_ready;
+  wire         _mmio_txdat_arb_io_in_3_ready;
+  wire         _mmio_txdat_arb_io_in_4_ready;
+  wire         _mmio_txdat_arb_io_in_5_ready;
+  wire         _mmio_txdat_arb_io_in_6_ready;
+  wire         _mmio_txdat_arb_io_in_7_ready;
+  wire         _mmio_txdat_arb_io_in_8_ready;
+  wire         _mmio_txdat_arb_io_in_9_ready;
+  wire         _mmio_txdat_arb_io_in_10_ready;
+  wire         _mmio_txdat_arb_io_in_11_ready;
+  wire         _mmio_txdat_arb_io_in_12_ready;
+  wire         _mmio_txdat_arb_io_in_13_ready;
+  wire         _mmio_txdat_arb_io_in_14_ready;
+  wire         _mmio_txdat_arb_io_in_15_ready;
+  wire         _txreqArb_io_in_0_ready;
+  wire         _txreqArb_io_in_1_ready;
+  wire         _txreqArb_io_in_2_ready;
+  wire         _txreqArb_io_in_3_ready;
+  wire         _txreqArb_io_in_4_ready;
+  wire         _txreqArb_io_in_5_ready;
+  wire         _txreqArb_io_in_6_ready;
+  wire         _txreqArb_io_in_7_ready;
+  wire         _txreqArb_io_in_8_ready;
+  wire         _txreqArb_io_in_9_ready;
+  wire         _txreqArb_io_in_10_ready;
+  wire         _txreqArb_io_in_11_ready;
+  wire         _txreqArb_io_in_12_ready;
+  wire         _txreqArb_io_in_13_ready;
+  wire         _txreqArb_io_in_14_ready;
+  wire         _txreqArb_io_in_15_ready;
+  wire         _entries_15_io_req_ready;
+  wire         _entries_15_io_resp_valid;
+  wire [3:0]   _entries_15_io_resp_bits_opcode;
+  wire [1:0]   _entries_15_io_resp_bits_size;
+  wire [4:0]   _entries_15_io_resp_bits_source;
+  wire         _entries_15_io_resp_bits_denied;
+  wire [63:0]  _entries_15_io_resp_bits_data;
+  wire         _entries_15_io_resp_bits_corrupt;
+  wire         _entries_15_io_chi_tx_req_valid;
+  wire [11:0]  _entries_15_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_15_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_15_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_15_io_chi_tx_req_bits_addr;
+  wire         _entries_15_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_15_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_15_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_15_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_15_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_15_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_15_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_15_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_15_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_15_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_15_io_chi_tx_dat_bits_dataID;
+  wire         _entries_15_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_15_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_15_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_15_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_15_io_chi_tx_dat_bits_poison;
+  wire         _entries_15_io_chi_rx_dat_ready;
+  wire         _entries_15_io_waitOnReadReceipt;
+  wire         _entries_15_io_isRead;
+  wire         _entries_14_io_req_ready;
+  wire         _entries_14_io_resp_valid;
+  wire [3:0]   _entries_14_io_resp_bits_opcode;
+  wire [1:0]   _entries_14_io_resp_bits_size;
+  wire [4:0]   _entries_14_io_resp_bits_source;
+  wire         _entries_14_io_resp_bits_denied;
+  wire [63:0]  _entries_14_io_resp_bits_data;
+  wire         _entries_14_io_resp_bits_corrupt;
+  wire         _entries_14_io_chi_tx_req_valid;
+  wire [11:0]  _entries_14_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_14_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_14_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_14_io_chi_tx_req_bits_addr;
+  wire         _entries_14_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_14_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_14_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_14_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_14_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_14_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_14_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_14_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_14_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_14_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_14_io_chi_tx_dat_bits_dataID;
+  wire         _entries_14_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_14_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_14_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_14_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_14_io_chi_tx_dat_bits_poison;
+  wire         _entries_14_io_chi_rx_dat_ready;
+  wire         _entries_14_io_waitOnReadReceipt;
+  wire         _entries_14_io_isRead;
+  wire         _entries_13_io_req_ready;
+  wire         _entries_13_io_resp_valid;
+  wire [3:0]   _entries_13_io_resp_bits_opcode;
+  wire [1:0]   _entries_13_io_resp_bits_size;
+  wire [4:0]   _entries_13_io_resp_bits_source;
+  wire         _entries_13_io_resp_bits_denied;
+  wire [63:0]  _entries_13_io_resp_bits_data;
+  wire         _entries_13_io_resp_bits_corrupt;
+  wire         _entries_13_io_chi_tx_req_valid;
+  wire [11:0]  _entries_13_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_13_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_13_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_13_io_chi_tx_req_bits_addr;
+  wire         _entries_13_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_13_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_13_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_13_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_13_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_13_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_13_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_13_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_13_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_13_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_13_io_chi_tx_dat_bits_dataID;
+  wire         _entries_13_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_13_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_13_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_13_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_13_io_chi_tx_dat_bits_poison;
+  wire         _entries_13_io_chi_rx_dat_ready;
+  wire         _entries_13_io_waitOnReadReceipt;
+  wire         _entries_13_io_isRead;
+  wire         _entries_12_io_req_ready;
+  wire         _entries_12_io_resp_valid;
+  wire [3:0]   _entries_12_io_resp_bits_opcode;
+  wire [1:0]   _entries_12_io_resp_bits_size;
+  wire [4:0]   _entries_12_io_resp_bits_source;
+  wire         _entries_12_io_resp_bits_denied;
+  wire [63:0]  _entries_12_io_resp_bits_data;
+  wire         _entries_12_io_resp_bits_corrupt;
+  wire         _entries_12_io_chi_tx_req_valid;
+  wire [11:0]  _entries_12_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_12_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_12_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_12_io_chi_tx_req_bits_addr;
+  wire         _entries_12_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_12_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_12_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_12_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_12_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_12_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_12_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_12_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_12_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_12_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_12_io_chi_tx_dat_bits_dataID;
+  wire         _entries_12_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_12_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_12_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_12_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_12_io_chi_tx_dat_bits_poison;
+  wire         _entries_12_io_chi_rx_dat_ready;
+  wire         _entries_12_io_waitOnReadReceipt;
+  wire         _entries_12_io_isRead;
+  wire         _entries_11_io_req_ready;
+  wire         _entries_11_io_resp_valid;
+  wire [3:0]   _entries_11_io_resp_bits_opcode;
+  wire [1:0]   _entries_11_io_resp_bits_size;
+  wire [4:0]   _entries_11_io_resp_bits_source;
+  wire         _entries_11_io_resp_bits_denied;
+  wire [63:0]  _entries_11_io_resp_bits_data;
+  wire         _entries_11_io_resp_bits_corrupt;
+  wire         _entries_11_io_chi_tx_req_valid;
+  wire [11:0]  _entries_11_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_11_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_11_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_11_io_chi_tx_req_bits_addr;
+  wire         _entries_11_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_11_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_11_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_11_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_11_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_11_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_11_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_11_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_11_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_11_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_11_io_chi_tx_dat_bits_dataID;
+  wire         _entries_11_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_11_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_11_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_11_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_11_io_chi_tx_dat_bits_poison;
+  wire         _entries_11_io_chi_rx_dat_ready;
+  wire         _entries_11_io_waitOnReadReceipt;
+  wire         _entries_11_io_isRead;
+  wire         _entries_10_io_req_ready;
+  wire         _entries_10_io_resp_valid;
+  wire [3:0]   _entries_10_io_resp_bits_opcode;
+  wire [1:0]   _entries_10_io_resp_bits_size;
+  wire [4:0]   _entries_10_io_resp_bits_source;
+  wire         _entries_10_io_resp_bits_denied;
+  wire [63:0]  _entries_10_io_resp_bits_data;
+  wire         _entries_10_io_resp_bits_corrupt;
+  wire         _entries_10_io_chi_tx_req_valid;
+  wire [11:0]  _entries_10_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_10_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_10_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_10_io_chi_tx_req_bits_addr;
+  wire         _entries_10_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_10_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_10_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_10_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_10_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_10_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_10_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_10_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_10_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_10_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_10_io_chi_tx_dat_bits_dataID;
+  wire         _entries_10_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_10_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_10_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_10_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_10_io_chi_tx_dat_bits_poison;
+  wire         _entries_10_io_chi_rx_dat_ready;
+  wire         _entries_10_io_waitOnReadReceipt;
+  wire         _entries_10_io_isRead;
+  wire         _entries_9_io_req_ready;
+  wire         _entries_9_io_resp_valid;
+  wire [3:0]   _entries_9_io_resp_bits_opcode;
+  wire [1:0]   _entries_9_io_resp_bits_size;
+  wire [4:0]   _entries_9_io_resp_bits_source;
+  wire         _entries_9_io_resp_bits_denied;
+  wire [63:0]  _entries_9_io_resp_bits_data;
+  wire         _entries_9_io_resp_bits_corrupt;
+  wire         _entries_9_io_chi_tx_req_valid;
+  wire [11:0]  _entries_9_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_9_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_9_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_9_io_chi_tx_req_bits_addr;
+  wire         _entries_9_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_9_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_9_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_9_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_9_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_9_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_9_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_9_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_9_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_9_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_9_io_chi_tx_dat_bits_dataID;
+  wire         _entries_9_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_9_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_9_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_9_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_9_io_chi_tx_dat_bits_poison;
+  wire         _entries_9_io_chi_rx_dat_ready;
+  wire         _entries_9_io_waitOnReadReceipt;
+  wire         _entries_9_io_isRead;
+  wire         _entries_8_io_req_ready;
+  wire         _entries_8_io_resp_valid;
+  wire [3:0]   _entries_8_io_resp_bits_opcode;
+  wire [1:0]   _entries_8_io_resp_bits_size;
+  wire [4:0]   _entries_8_io_resp_bits_source;
+  wire         _entries_8_io_resp_bits_denied;
+  wire [63:0]  _entries_8_io_resp_bits_data;
+  wire         _entries_8_io_resp_bits_corrupt;
+  wire         _entries_8_io_chi_tx_req_valid;
+  wire [11:0]  _entries_8_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_8_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_8_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_8_io_chi_tx_req_bits_addr;
+  wire         _entries_8_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_8_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_8_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_8_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_8_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_8_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_8_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_8_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_8_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_8_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_8_io_chi_tx_dat_bits_dataID;
+  wire         _entries_8_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_8_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_8_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_8_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_8_io_chi_tx_dat_bits_poison;
+  wire         _entries_8_io_chi_rx_dat_ready;
+  wire         _entries_8_io_waitOnReadReceipt;
+  wire         _entries_8_io_isRead;
+  wire         _entries_7_io_req_ready;
+  wire         _entries_7_io_resp_valid;
+  wire [3:0]   _entries_7_io_resp_bits_opcode;
+  wire [1:0]   _entries_7_io_resp_bits_size;
+  wire [4:0]   _entries_7_io_resp_bits_source;
+  wire         _entries_7_io_resp_bits_denied;
+  wire [63:0]  _entries_7_io_resp_bits_data;
+  wire         _entries_7_io_resp_bits_corrupt;
+  wire         _entries_7_io_chi_tx_req_valid;
+  wire [11:0]  _entries_7_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_7_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_7_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_7_io_chi_tx_req_bits_addr;
+  wire         _entries_7_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_7_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_7_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_7_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_7_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_7_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_7_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_7_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_7_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_7_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_7_io_chi_tx_dat_bits_dataID;
+  wire         _entries_7_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_7_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_7_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_7_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_7_io_chi_tx_dat_bits_poison;
+  wire         _entries_7_io_chi_rx_dat_ready;
+  wire         _entries_7_io_waitOnReadReceipt;
+  wire         _entries_7_io_isRead;
+  wire         _entries_6_io_req_ready;
+  wire         _entries_6_io_resp_valid;
+  wire [3:0]   _entries_6_io_resp_bits_opcode;
+  wire [1:0]   _entries_6_io_resp_bits_size;
+  wire [4:0]   _entries_6_io_resp_bits_source;
+  wire         _entries_6_io_resp_bits_denied;
+  wire [63:0]  _entries_6_io_resp_bits_data;
+  wire         _entries_6_io_resp_bits_corrupt;
+  wire         _entries_6_io_chi_tx_req_valid;
+  wire [11:0]  _entries_6_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_6_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_6_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_6_io_chi_tx_req_bits_addr;
+  wire         _entries_6_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_6_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_6_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_6_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_6_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_6_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_6_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_6_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_6_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_6_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_6_io_chi_tx_dat_bits_dataID;
+  wire         _entries_6_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_6_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_6_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_6_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_6_io_chi_tx_dat_bits_poison;
+  wire         _entries_6_io_chi_rx_dat_ready;
+  wire         _entries_6_io_waitOnReadReceipt;
+  wire         _entries_6_io_isRead;
+  wire         _entries_5_io_req_ready;
+  wire         _entries_5_io_resp_valid;
+  wire [3:0]   _entries_5_io_resp_bits_opcode;
+  wire [1:0]   _entries_5_io_resp_bits_size;
+  wire [4:0]   _entries_5_io_resp_bits_source;
+  wire         _entries_5_io_resp_bits_denied;
+  wire [63:0]  _entries_5_io_resp_bits_data;
+  wire         _entries_5_io_resp_bits_corrupt;
+  wire         _entries_5_io_chi_tx_req_valid;
+  wire [11:0]  _entries_5_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_5_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_5_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_5_io_chi_tx_req_bits_addr;
+  wire         _entries_5_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_5_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_5_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_5_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_5_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_5_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_5_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_5_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_5_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_5_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_5_io_chi_tx_dat_bits_dataID;
+  wire         _entries_5_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_5_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_5_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_5_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_5_io_chi_tx_dat_bits_poison;
+  wire         _entries_5_io_chi_rx_dat_ready;
+  wire         _entries_5_io_waitOnReadReceipt;
+  wire         _entries_5_io_isRead;
+  wire         _entries_4_io_req_ready;
+  wire         _entries_4_io_resp_valid;
+  wire [3:0]   _entries_4_io_resp_bits_opcode;
+  wire [1:0]   _entries_4_io_resp_bits_size;
+  wire [4:0]   _entries_4_io_resp_bits_source;
+  wire         _entries_4_io_resp_bits_denied;
+  wire [63:0]  _entries_4_io_resp_bits_data;
+  wire         _entries_4_io_resp_bits_corrupt;
+  wire         _entries_4_io_chi_tx_req_valid;
+  wire [11:0]  _entries_4_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_4_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_4_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_4_io_chi_tx_req_bits_addr;
+  wire         _entries_4_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_4_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_4_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_4_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_4_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_4_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_4_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_4_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_4_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_4_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_4_io_chi_tx_dat_bits_dataID;
+  wire         _entries_4_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_4_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_4_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_4_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_4_io_chi_tx_dat_bits_poison;
+  wire         _entries_4_io_chi_rx_dat_ready;
+  wire         _entries_4_io_waitOnReadReceipt;
+  wire         _entries_4_io_isRead;
+  wire         _entries_3_io_req_ready;
+  wire         _entries_3_io_resp_valid;
+  wire [3:0]   _entries_3_io_resp_bits_opcode;
+  wire [1:0]   _entries_3_io_resp_bits_size;
+  wire [4:0]   _entries_3_io_resp_bits_source;
+  wire         _entries_3_io_resp_bits_denied;
+  wire [63:0]  _entries_3_io_resp_bits_data;
+  wire         _entries_3_io_resp_bits_corrupt;
+  wire         _entries_3_io_chi_tx_req_valid;
+  wire [11:0]  _entries_3_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_3_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_3_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_3_io_chi_tx_req_bits_addr;
+  wire         _entries_3_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_3_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_3_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_3_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_3_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_3_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_3_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_3_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_3_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_3_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_3_io_chi_tx_dat_bits_dataID;
+  wire         _entries_3_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_3_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_3_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_3_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_3_io_chi_tx_dat_bits_poison;
+  wire         _entries_3_io_chi_rx_dat_ready;
+  wire         _entries_3_io_waitOnReadReceipt;
+  wire         _entries_3_io_isRead;
+  wire         _entries_2_io_req_ready;
+  wire         _entries_2_io_resp_valid;
+  wire [3:0]   _entries_2_io_resp_bits_opcode;
+  wire [1:0]   _entries_2_io_resp_bits_size;
+  wire [4:0]   _entries_2_io_resp_bits_source;
+  wire         _entries_2_io_resp_bits_denied;
+  wire [63:0]  _entries_2_io_resp_bits_data;
+  wire         _entries_2_io_resp_bits_corrupt;
+  wire         _entries_2_io_chi_tx_req_valid;
+  wire [11:0]  _entries_2_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_2_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_2_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_2_io_chi_tx_req_bits_addr;
+  wire         _entries_2_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_2_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_2_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_2_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_2_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_2_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_2_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_2_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_2_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_2_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_2_io_chi_tx_dat_bits_dataID;
+  wire         _entries_2_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_2_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_2_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_2_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_2_io_chi_tx_dat_bits_poison;
+  wire         _entries_2_io_chi_rx_dat_ready;
+  wire         _entries_2_io_waitOnReadReceipt;
+  wire         _entries_2_io_isRead;
+  wire         _entries_1_io_req_ready;
+  wire         _entries_1_io_resp_valid;
+  wire [3:0]   _entries_1_io_resp_bits_opcode;
+  wire [1:0]   _entries_1_io_resp_bits_size;
+  wire [4:0]   _entries_1_io_resp_bits_source;
+  wire         _entries_1_io_resp_bits_denied;
+  wire [63:0]  _entries_1_io_resp_bits_data;
+  wire         _entries_1_io_resp_bits_corrupt;
+  wire         _entries_1_io_chi_tx_req_valid;
+  wire [11:0]  _entries_1_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_1_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_1_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_1_io_chi_tx_req_bits_addr;
+  wire         _entries_1_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_1_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_1_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_1_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_1_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_1_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_1_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_1_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_1_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_1_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_1_io_chi_tx_dat_bits_dataID;
+  wire         _entries_1_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_1_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_1_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_1_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_1_io_chi_tx_dat_bits_poison;
+  wire         _entries_1_io_chi_rx_dat_ready;
+  wire         _entries_1_io_waitOnReadReceipt;
+  wire         _entries_1_io_isRead;
+  wire         _entries_0_io_req_ready;
+  wire         _entries_0_io_resp_valid;
+  wire [3:0]   _entries_0_io_resp_bits_opcode;
+  wire [1:0]   _entries_0_io_resp_bits_size;
+  wire [4:0]   _entries_0_io_resp_bits_source;
+  wire         _entries_0_io_resp_bits_denied;
+  wire [63:0]  _entries_0_io_resp_bits_data;
+  wire         _entries_0_io_resp_bits_corrupt;
+  wire         _entries_0_io_chi_tx_req_valid;
+  wire [11:0]  _entries_0_io_chi_tx_req_bits_txnID;
+  wire [6:0]   _entries_0_io_chi_tx_req_bits_opcode;
+  wire [2:0]   _entries_0_io_chi_tx_req_bits_size;
+  wire [47:0]  _entries_0_io_chi_tx_req_bits_addr;
+  wire         _entries_0_io_chi_tx_req_bits_allowRetry;
+  wire [1:0]   _entries_0_io_chi_tx_req_bits_order;
+  wire [3:0]   _entries_0_io_chi_tx_req_bits_pCrdType;
+  wire         _entries_0_io_chi_tx_req_bits_memAttr_device;
+  wire         _entries_0_io_chi_tx_req_bits_memAttr_ewa;
+  wire         _entries_0_io_chi_tx_dat_valid;
+  wire [10:0]  _entries_0_io_chi_tx_dat_bits_tgtID;
+  wire [11:0]  _entries_0_io_chi_tx_dat_bits_txnID;
+  wire [1:0]   _entries_0_io_chi_tx_dat_bits_respErr;
+  wire [1:0]   _entries_0_io_chi_tx_dat_bits_ccID;
+  wire [1:0]   _entries_0_io_chi_tx_dat_bits_dataID;
+  wire         _entries_0_io_chi_tx_dat_bits_traceTag;
+  wire [31:0]  _entries_0_io_chi_tx_dat_bits_be;
+  wire [255:0] _entries_0_io_chi_tx_dat_bits_data;
+  wire [31:0]  _entries_0_io_chi_tx_dat_bits_dataCheck;
+  wire [3:0]   _entries_0_io_chi_tx_dat_bits_poison;
+  wire         _entries_0_io_chi_rx_dat_ready;
+  wire         _entries_0_io_waitOnReadReceipt;
+  wire         _entries_0_io_isRead;
+  wire         mmioNodeIn_a_valid = auto_mmio_in_a_valid;
+  wire [3:0]   mmioNodeIn_a_bits_opcode = auto_mmio_in_a_bits_opcode;
+  wire [2:0]   mmioNodeIn_a_bits_param = auto_mmio_in_a_bits_param;
+  wire [1:0]   mmioNodeIn_a_bits_size = auto_mmio_in_a_bits_size;
+  wire [4:0]   mmioNodeIn_a_bits_source = auto_mmio_in_a_bits_source;
+  wire [47:0]  mmioNodeIn_a_bits_address = auto_mmio_in_a_bits_address;
+  wire         mmioNodeIn_a_bits_user_memBackType_MM =
+    auto_mmio_in_a_bits_user_memBackType_MM;
+  wire         mmioNodeIn_a_bits_user_memPageType_NC =
+    auto_mmio_in_a_bits_user_memPageType_NC;
+  wire [7:0]   mmioNodeIn_a_bits_mask = auto_mmio_in_a_bits_mask;
+  wire [63:0]  mmioNodeIn_a_bits_data = auto_mmio_in_a_bits_data;
+  wire         mmioNodeIn_a_bits_corrupt = auto_mmio_in_a_bits_corrupt;
+  wire         mmioNodeIn_d_ready = auto_mmio_in_d_ready;
+  wire [1:0]   mmioNodeIn_d_bits_param = 2'h0;
+  wire         mmioNodeIn_d_bits_sink = 1'h0;
+  wire         _selectOH_T = _entries_0_io_req_ready | _entries_1_io_req_ready;
+  wire         _selectOH_T_4 =
+    _selectOH_T | _entries_2_io_req_ready | _entries_3_io_req_ready;
+  wire         _selectOH_T_6 = _entries_4_io_req_ready | _entries_5_io_req_ready;
+  wire         _selectOH_T_14 = _entries_8_io_req_ready | _entries_9_io_req_ready;
+  wire [15:0]  _selectOH_T_29 =
+    _selectOH_T_4 | _selectOH_T_6 | _entries_6_io_req_ready | _entries_7_io_req_ready
+      ? {8'h0,
+         _selectOH_T_4
+           ? {4'h0,
+              _selectOH_T
+                ? {2'h0, _entries_0_io_req_ready ? 2'h1 : 2'h2}
+                : _entries_2_io_req_ready ? 4'h4 : 4'h8}
+           : _selectOH_T_6
+               ? {2'h0, _entries_4_io_req_ready ? 6'h10 : 6'h20}
+               : _entries_6_io_req_ready ? 8'h40 : 8'h80}
+      : _selectOH_T_14 | _entries_10_io_req_ready | _entries_11_io_req_ready
+          ? {4'h0,
+             _selectOH_T_14
+               ? {2'h0, _entries_8_io_req_ready ? 10'h100 : 10'h200}
+               : _entries_10_io_req_ready ? 12'h400 : 12'h800}
+          : _entries_12_io_req_ready | _entries_13_io_req_ready
+              ? {2'h0, _entries_12_io_req_ready ? 14'h1000 : 14'h2000}
+              : _entries_14_io_req_ready ? 16'h4000 : 16'h8000;
+  wire [15:0]  _waitOnReadReceipt_T =
+    {_entries_0_io_waitOnReadReceipt,
+     _entries_1_io_waitOnReadReceipt,
+     _entries_2_io_waitOnReadReceipt,
+     _entries_3_io_waitOnReadReceipt,
+     _entries_4_io_waitOnReadReceipt,
+     _entries_5_io_waitOnReadReceipt,
+     _entries_6_io_waitOnReadReceipt,
+     _entries_7_io_waitOnReadReceipt,
+     _entries_8_io_waitOnReadReceipt,
+     _entries_9_io_waitOnReadReceipt,
+     _entries_10_io_waitOnReadReceipt,
+     _entries_11_io_waitOnReadReceipt,
+     _entries_12_io_waitOnReadReceipt,
+     _entries_13_io_waitOnReadReceipt,
+     _entries_14_io_waitOnReadReceipt,
+     _entries_15_io_waitOnReadReceipt};
+  wire         _io_rx_dat_ready_T = io_rx_dat_bits_txnID == 12'h0;
+  wire         _io_rx_dat_ready_T_2 = io_rx_dat_bits_txnID == 12'h1;
+  wire         _io_rx_dat_ready_T_4 = io_rx_dat_bits_txnID == 12'h2;
+  wire         _io_rx_dat_ready_T_6 = io_rx_dat_bits_txnID == 12'h3;
+  wire         _io_rx_dat_ready_T_8 = io_rx_dat_bits_txnID == 12'h4;
+  wire         _io_rx_dat_ready_T_10 = io_rx_dat_bits_txnID == 12'h5;
+  wire         _io_rx_dat_ready_T_12 = io_rx_dat_bits_txnID == 12'h6;
+  wire         _io_rx_dat_ready_T_14 = io_rx_dat_bits_txnID == 12'h7;
+  wire         _io_rx_dat_ready_T_16 = io_rx_dat_bits_txnID == 12'h8;
+  wire         _io_rx_dat_ready_T_18 = io_rx_dat_bits_txnID == 12'h9;
+  wire         _io_rx_dat_ready_T_20 = io_rx_dat_bits_txnID == 12'hA;
+  wire         _io_rx_dat_ready_T_22 = io_rx_dat_bits_txnID == 12'hB;
+  wire         _io_rx_dat_ready_T_24 = io_rx_dat_bits_txnID == 12'hC;
+  wire         _io_rx_dat_ready_T_26 = io_rx_dat_bits_txnID == 12'hD;
+  wire         _io_rx_dat_ready_T_28 = io_rx_dat_bits_txnID == 12'hE;
+  wire         _io_rx_dat_ready_T_30 = io_rx_dat_bits_txnID == 12'hF;
+  wire         block = _entries_0_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_1 = _entries_1_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_2 = _entries_2_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_3 = _entries_3_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_4 = _entries_4_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_5 = _entries_5_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_6 = _entries_6_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_7 = _entries_7_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_8 = _entries_8_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_9 = _entries_9_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_10 = _entries_10_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_11 = _entries_11_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_12 = _entries_12_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_13 = _entries_13_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_14 = _entries_14_io_isRead & (|_waitOnReadReceipt_T);
+  wire         block_15 = _entries_15_io_isRead & (|_waitOnReadReceipt_T);
+  wire         mmioNodeIn_a_ready =
+    |{_entries_0_io_req_ready,
+      _entries_1_io_req_ready,
+      _entries_2_io_req_ready,
+      _entries_3_io_req_ready,
+      _entries_4_io_req_ready,
+      _entries_5_io_req_ready,
+      _entries_6_io_req_ready,
+      _entries_7_io_req_ready,
+      _entries_8_io_req_ready,
+      _entries_9_io_req_ready,
+      _entries_10_io_req_ready,
+      _entries_11_io_req_ready,
+      _entries_12_io_req_ready,
+      _entries_13_io_req_ready,
+      _entries_14_io_req_ready,
+      _entries_15_io_req_ready};
+  MMIOBridgeEntry entries_0 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_0_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[0]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_0_ready),
+    .io_resp_valid                     (_entries_0_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_0_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_0_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_0_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_0_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_0_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_0_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_0_ready & ~block),
+    .io_chi_tx_req_valid               (_entries_0_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_0_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_0_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_0_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_0_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_0_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_0_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_0_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_0_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_0_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_0_ready),
+    .io_chi_tx_dat_valid               (_entries_0_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_0_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_0_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_0_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_0_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_0_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_0_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_0_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_0_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_0_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_0_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h0),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_0_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (1'h0),
+    .io_pCrd_query_valid               (io_pCrd_0_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_0_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_0_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_0_grant),
+    .io_waitOnReadReceipt              (_entries_0_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_0_io_isRead)
+  );
+  MMIOBridgeEntry entries_1 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_1_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[1]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_1_ready),
+    .io_resp_valid                     (_entries_1_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_1_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_1_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_1_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_1_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_1_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_1_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_1_ready & ~block_1),
+    .io_chi_tx_req_valid               (_entries_1_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_1_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_1_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_1_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_1_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_1_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_1_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_1_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_1_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_1_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_1_ready),
+    .io_chi_tx_dat_valid               (_entries_1_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_1_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_1_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_1_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_1_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_1_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_1_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_1_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_1_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_1_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_1_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h1),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_1_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_2),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (1'h1),
+    .io_pCrd_query_valid               (io_pCrd_1_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_1_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_1_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_1_grant),
+    .io_waitOnReadReceipt              (_entries_1_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_1_io_isRead)
+  );
+  MMIOBridgeEntry_2 entries_2 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_2_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[2]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_2_ready),
+    .io_resp_valid                     (_entries_2_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_2_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_2_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_2_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_2_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_2_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_2_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_2_ready & ~block_2),
+    .io_chi_tx_req_valid               (_entries_2_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_2_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_2_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_2_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_2_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_2_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_2_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_2_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_2_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_2_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_2_ready),
+    .io_chi_tx_dat_valid               (_entries_2_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_2_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_2_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_2_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_2_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_2_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_2_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_2_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_2_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_2_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_2_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h2),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_2_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_4),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (2'h2),
+    .io_pCrd_query_valid               (io_pCrd_2_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_2_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_2_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_2_grant),
+    .io_waitOnReadReceipt              (_entries_2_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_2_io_isRead)
+  );
+  MMIOBridgeEntry_2 entries_3 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_3_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[3]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_3_ready),
+    .io_resp_valid                     (_entries_3_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_3_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_3_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_3_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_3_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_3_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_3_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_3_ready & ~block_3),
+    .io_chi_tx_req_valid               (_entries_3_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_3_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_3_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_3_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_3_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_3_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_3_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_3_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_3_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_3_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_3_ready),
+    .io_chi_tx_dat_valid               (_entries_3_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_3_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_3_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_3_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_3_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_3_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_3_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_3_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_3_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_3_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_3_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h3),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_3_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_6),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (2'h3),
+    .io_pCrd_query_valid               (io_pCrd_3_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_3_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_3_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_3_grant),
+    .io_waitOnReadReceipt              (_entries_3_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_3_io_isRead)
+  );
+  MMIOBridgeEntry_4 entries_4 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_4_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[4]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_4_ready),
+    .io_resp_valid                     (_entries_4_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_4_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_4_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_4_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_4_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_4_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_4_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_4_ready & ~block_4),
+    .io_chi_tx_req_valid               (_entries_4_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_4_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_4_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_4_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_4_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_4_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_4_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_4_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_4_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_4_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_4_ready),
+    .io_chi_tx_dat_valid               (_entries_4_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_4_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_4_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_4_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_4_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_4_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_4_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_4_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_4_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_4_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_4_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h4),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_4_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_8),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (3'h4),
+    .io_pCrd_query_valid               (io_pCrd_4_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_4_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_4_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_4_grant),
+    .io_waitOnReadReceipt              (_entries_4_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_4_io_isRead)
+  );
+  MMIOBridgeEntry_4 entries_5 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_5_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[5]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_5_ready),
+    .io_resp_valid                     (_entries_5_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_5_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_5_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_5_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_5_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_5_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_5_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_5_ready & ~block_5),
+    .io_chi_tx_req_valid               (_entries_5_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_5_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_5_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_5_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_5_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_5_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_5_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_5_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_5_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_5_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_5_ready),
+    .io_chi_tx_dat_valid               (_entries_5_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_5_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_5_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_5_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_5_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_5_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_5_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_5_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_5_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_5_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_5_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h5),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_5_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_10),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (3'h5),
+    .io_pCrd_query_valid               (io_pCrd_5_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_5_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_5_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_5_grant),
+    .io_waitOnReadReceipt              (_entries_5_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_5_io_isRead)
+  );
+  MMIOBridgeEntry_4 entries_6 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_6_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[6]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_6_ready),
+    .io_resp_valid                     (_entries_6_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_6_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_6_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_6_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_6_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_6_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_6_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_6_ready & ~block_6),
+    .io_chi_tx_req_valid               (_entries_6_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_6_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_6_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_6_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_6_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_6_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_6_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_6_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_6_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_6_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_6_ready),
+    .io_chi_tx_dat_valid               (_entries_6_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_6_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_6_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_6_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_6_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_6_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_6_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_6_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_6_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_6_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_6_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h6),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_6_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_12),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (3'h6),
+    .io_pCrd_query_valid               (io_pCrd_6_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_6_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_6_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_6_grant),
+    .io_waitOnReadReceipt              (_entries_6_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_6_io_isRead)
+  );
+  MMIOBridgeEntry_4 entries_7 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_7_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[7]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_7_ready),
+    .io_resp_valid                     (_entries_7_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_7_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_7_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_7_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_7_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_7_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_7_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_7_ready & ~block_7),
+    .io_chi_tx_req_valid               (_entries_7_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_7_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_7_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_7_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_7_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_7_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_7_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_7_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_7_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_7_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_7_ready),
+    .io_chi_tx_dat_valid               (_entries_7_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_7_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_7_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_7_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_7_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_7_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_7_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_7_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_7_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_7_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_7_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h7),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_7_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_14),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (3'h7),
+    .io_pCrd_query_valid               (io_pCrd_7_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_7_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_7_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_7_grant),
+    .io_waitOnReadReceipt              (_entries_7_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_7_io_isRead)
+  );
+  MMIOBridgeEntry_8 entries_8 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_8_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[8]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_8_ready),
+    .io_resp_valid                     (_entries_8_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_8_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_8_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_8_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_8_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_8_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_8_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_8_ready & ~block_8),
+    .io_chi_tx_req_valid               (_entries_8_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_8_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_8_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_8_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_8_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_8_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_8_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_8_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_8_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_8_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_8_ready),
+    .io_chi_tx_dat_valid               (_entries_8_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_8_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_8_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_8_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_8_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_8_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_8_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_8_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_8_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_8_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_8_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h8),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_8_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_16),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (4'h8),
+    .io_pCrd_query_valid               (io_pCrd_8_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_8_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_8_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_8_grant),
+    .io_waitOnReadReceipt              (_entries_8_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_8_io_isRead)
+  );
+  MMIOBridgeEntry_8 entries_9 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_9_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[9]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_9_ready),
+    .io_resp_valid                     (_entries_9_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_9_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_9_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_9_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_9_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_9_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_9_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_9_ready & ~block_9),
+    .io_chi_tx_req_valid               (_entries_9_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_9_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_9_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_9_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_9_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_9_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_9_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_9_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_9_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_9_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_9_ready),
+    .io_chi_tx_dat_valid               (_entries_9_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_9_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_9_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_9_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_9_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_9_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_9_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_9_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_9_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_9_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_9_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'h9),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_9_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_18),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (4'h9),
+    .io_pCrd_query_valid               (io_pCrd_9_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_9_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_9_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_9_grant),
+    .io_waitOnReadReceipt              (_entries_9_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_9_io_isRead)
+  );
+  MMIOBridgeEntry_8 entries_10 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_10_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[10]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_10_ready),
+    .io_resp_valid                     (_entries_10_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_10_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_10_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_10_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_10_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_10_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_10_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_10_ready & ~block_10),
+    .io_chi_tx_req_valid               (_entries_10_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_10_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_10_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_10_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_10_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_10_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_10_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_10_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_10_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_10_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_10_ready),
+    .io_chi_tx_dat_valid               (_entries_10_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_10_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_10_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_10_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_10_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_10_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_10_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_10_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_10_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_10_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_10_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'hA),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_10_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_20),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (4'hA),
+    .io_pCrd_query_valid               (io_pCrd_10_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_10_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_10_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_10_grant),
+    .io_waitOnReadReceipt              (_entries_10_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_10_io_isRead)
+  );
+  MMIOBridgeEntry_8 entries_11 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_11_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[11]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_11_ready),
+    .io_resp_valid                     (_entries_11_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_11_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_11_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_11_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_11_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_11_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_11_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_11_ready & ~block_11),
+    .io_chi_tx_req_valid               (_entries_11_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_11_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_11_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_11_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_11_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_11_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_11_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_11_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_11_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_11_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_11_ready),
+    .io_chi_tx_dat_valid               (_entries_11_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_11_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_11_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_11_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_11_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_11_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_11_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_11_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_11_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_11_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_11_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'hB),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_11_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_22),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (4'hB),
+    .io_pCrd_query_valid               (io_pCrd_11_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_11_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_11_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_11_grant),
+    .io_waitOnReadReceipt              (_entries_11_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_11_io_isRead)
+  );
+  MMIOBridgeEntry_8 entries_12 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_12_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[12]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_12_ready),
+    .io_resp_valid                     (_entries_12_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_12_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_12_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_12_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_12_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_12_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_12_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_12_ready & ~block_12),
+    .io_chi_tx_req_valid               (_entries_12_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_12_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_12_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_12_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_12_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_12_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_12_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_12_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_12_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_12_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_12_ready),
+    .io_chi_tx_dat_valid               (_entries_12_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_12_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_12_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_12_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_12_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_12_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_12_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_12_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_12_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_12_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_12_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'hC),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_12_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_24),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (4'hC),
+    .io_pCrd_query_valid               (io_pCrd_12_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_12_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_12_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_12_grant),
+    .io_waitOnReadReceipt              (_entries_12_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_12_io_isRead)
+  );
+  MMIOBridgeEntry_8 entries_13 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_13_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[13]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_13_ready),
+    .io_resp_valid                     (_entries_13_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_13_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_13_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_13_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_13_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_13_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_13_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_13_ready & ~block_13),
+    .io_chi_tx_req_valid               (_entries_13_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_13_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_13_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_13_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_13_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_13_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_13_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_13_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_13_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_13_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_13_ready),
+    .io_chi_tx_dat_valid               (_entries_13_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_13_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_13_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_13_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_13_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_13_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_13_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_13_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_13_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_13_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_13_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'hD),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_13_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_26),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (4'hD),
+    .io_pCrd_query_valid               (io_pCrd_13_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_13_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_13_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_13_grant),
+    .io_waitOnReadReceipt              (_entries_13_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_13_io_isRead)
+  );
+  MMIOBridgeEntry_8 entries_14 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_14_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[14]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_14_ready),
+    .io_resp_valid                     (_entries_14_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_14_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_14_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_14_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_14_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_14_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_14_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_14_ready & ~block_14),
+    .io_chi_tx_req_valid               (_entries_14_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_14_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_14_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_14_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_14_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_14_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_14_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_14_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_14_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_14_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_14_ready),
+    .io_chi_tx_dat_valid               (_entries_14_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_14_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_14_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_14_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_14_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_14_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_14_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_14_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_14_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_14_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_14_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'hE),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_14_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_28),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (4'hE),
+    .io_pCrd_query_valid               (io_pCrd_14_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_14_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_14_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_14_grant),
+    .io_waitOnReadReceipt              (_entries_14_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_14_io_isRead)
+  );
+  MMIOBridgeEntry_8 entries_15 (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_req_ready                      (_entries_15_io_req_ready),
+    .io_req_valid                      (mmioNodeIn_a_valid & _selectOH_T_29[15]),
+    .io_req_bits_opcode                (mmioNodeIn_a_bits_opcode),
+    .io_req_bits_size                  (mmioNodeIn_a_bits_size),
+    .io_req_bits_source                (mmioNodeIn_a_bits_source),
+    .io_req_bits_address               (mmioNodeIn_a_bits_address),
+    .io_req_bits_user_memBackType_MM   (mmioNodeIn_a_bits_user_memBackType_MM),
+    .io_req_bits_user_memPageType_NC   (mmioNodeIn_a_bits_user_memPageType_NC),
+    .io_req_bits_mask                  (mmioNodeIn_a_bits_mask),
+    .io_req_bits_data                  (mmioNodeIn_a_bits_data),
+    .io_req_bits_corrupt               (mmioNodeIn_a_bits_corrupt),
+    .io_resp_ready                     (_mmio_channel_D_arb_io_in_15_ready),
+    .io_resp_valid                     (_entries_15_io_resp_valid),
+    .io_resp_bits_opcode               (_entries_15_io_resp_bits_opcode),
+    .io_resp_bits_size                 (_entries_15_io_resp_bits_size),
+    .io_resp_bits_source               (_entries_15_io_resp_bits_source),
+    .io_resp_bits_denied               (_entries_15_io_resp_bits_denied),
+    .io_resp_bits_data                 (_entries_15_io_resp_bits_data),
+    .io_resp_bits_corrupt              (_entries_15_io_resp_bits_corrupt),
+    .io_chi_tx_req_ready               (_txreqArb_io_in_15_ready & ~block_15),
+    .io_chi_tx_req_valid               (_entries_15_io_chi_tx_req_valid),
+    .io_chi_tx_req_bits_txnID          (_entries_15_io_chi_tx_req_bits_txnID),
+    .io_chi_tx_req_bits_opcode         (_entries_15_io_chi_tx_req_bits_opcode),
+    .io_chi_tx_req_bits_size           (_entries_15_io_chi_tx_req_bits_size),
+    .io_chi_tx_req_bits_addr           (_entries_15_io_chi_tx_req_bits_addr),
+    .io_chi_tx_req_bits_allowRetry     (_entries_15_io_chi_tx_req_bits_allowRetry),
+    .io_chi_tx_req_bits_order          (_entries_15_io_chi_tx_req_bits_order),
+    .io_chi_tx_req_bits_pCrdType       (_entries_15_io_chi_tx_req_bits_pCrdType),
+    .io_chi_tx_req_bits_memAttr_device (_entries_15_io_chi_tx_req_bits_memAttr_device),
+    .io_chi_tx_req_bits_memAttr_ewa    (_entries_15_io_chi_tx_req_bits_memAttr_ewa),
+    .io_chi_tx_dat_ready               (_mmio_txdat_arb_io_in_15_ready),
+    .io_chi_tx_dat_valid               (_entries_15_io_chi_tx_dat_valid),
+    .io_chi_tx_dat_bits_tgtID          (_entries_15_io_chi_tx_dat_bits_tgtID),
+    .io_chi_tx_dat_bits_txnID          (_entries_15_io_chi_tx_dat_bits_txnID),
+    .io_chi_tx_dat_bits_respErr        (_entries_15_io_chi_tx_dat_bits_respErr),
+    .io_chi_tx_dat_bits_ccID           (_entries_15_io_chi_tx_dat_bits_ccID),
+    .io_chi_tx_dat_bits_dataID         (_entries_15_io_chi_tx_dat_bits_dataID),
+    .io_chi_tx_dat_bits_traceTag       (_entries_15_io_chi_tx_dat_bits_traceTag),
+    .io_chi_tx_dat_bits_be             (_entries_15_io_chi_tx_dat_bits_be),
+    .io_chi_tx_dat_bits_data           (_entries_15_io_chi_tx_dat_bits_data),
+    .io_chi_tx_dat_bits_dataCheck      (_entries_15_io_chi_tx_dat_bits_dataCheck),
+    .io_chi_tx_dat_bits_poison         (_entries_15_io_chi_tx_dat_bits_poison),
+    .io_chi_rx_rsp_valid               (io_rx_rsp_valid & io_rx_rsp_bits_txnID == 12'hF),
+    .io_chi_rx_rsp_bits_srcID          (io_rx_rsp_bits_srcID),
+    .io_chi_rx_rsp_bits_opcode         (io_rx_rsp_bits_opcode),
+    .io_chi_rx_rsp_bits_respErr        (io_rx_rsp_bits_respErr),
+    .io_chi_rx_rsp_bits_dbID           (io_rx_rsp_bits_dbID),
+    .io_chi_rx_rsp_bits_pCrdType       (io_rx_rsp_bits_pCrdType),
+    .io_chi_rx_rsp_bits_traceTag       (io_rx_rsp_bits_traceTag),
+    .io_chi_rx_dat_ready               (_entries_15_io_chi_rx_dat_ready),
+    .io_chi_rx_dat_valid               (io_rx_dat_valid & _io_rx_dat_ready_T_30),
+    .io_chi_rx_dat_bits_respErr        (io_rx_dat_bits_respErr),
+    .io_chi_rx_dat_bits_data           (io_rx_dat_bits_data),
+    .io_chi_rx_dat_bits_dataCheck      (io_rx_dat_bits_dataCheck),
+    .io_chi_rx_dat_bits_poison         (io_rx_dat_bits_poison),
+    .io_id                             (4'hF),
+    .io_pCrd_query_valid               (io_pCrd_15_query_valid),
+    .io_pCrd_query_bits_pCrdType       (io_pCrd_15_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID          (io_pCrd_15_query_bits_srcID),
+    .io_pCrd_grant                     (io_pCrd_15_grant),
+    .io_waitOnReadReceipt              (_entries_15_io_waitOnReadReceipt),
+    .io_isRead                         (_entries_15_io_isRead)
+  );
+  TwoLevelRRArbiter_1 txreqArb (
+    .clock                           (clock),
+    .reset                           (reset),
+    .io_in_0_ready                   (_txreqArb_io_in_0_ready),
+    .io_in_0_valid                   (_entries_0_io_chi_tx_req_valid & ~block),
+    .io_in_0_bits_tgtID              (11'h0),
+    .io_in_0_bits_txnID              (_entries_0_io_chi_tx_req_bits_txnID),
+    .io_in_0_bits_opcode             (_entries_0_io_chi_tx_req_bits_opcode),
+    .io_in_0_bits_size               (_entries_0_io_chi_tx_req_bits_size),
+    .io_in_0_bits_addr               (_entries_0_io_chi_tx_req_bits_addr),
+    .io_in_0_bits_likelyshared       (1'h0),
+    .io_in_0_bits_allowRetry         (_entries_0_io_chi_tx_req_bits_allowRetry),
+    .io_in_0_bits_order              (_entries_0_io_chi_tx_req_bits_order),
+    .io_in_0_bits_pCrdType           (_entries_0_io_chi_tx_req_bits_pCrdType),
+    .io_in_0_bits_memAttr_allocate   (1'h0),
+    .io_in_0_bits_memAttr_cacheable  (1'h0),
+    .io_in_0_bits_memAttr_device     (_entries_0_io_chi_tx_req_bits_memAttr_device),
+    .io_in_0_bits_memAttr_ewa        (_entries_0_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_0_bits_snpAttr            (1'h0),
+    .io_in_0_bits_expCompAck         (1'h0),
+    .io_in_1_ready                   (_txreqArb_io_in_1_ready),
+    .io_in_1_valid                   (_entries_1_io_chi_tx_req_valid & ~block_1),
+    .io_in_1_bits_tgtID              (11'h0),
+    .io_in_1_bits_txnID              (_entries_1_io_chi_tx_req_bits_txnID),
+    .io_in_1_bits_opcode             (_entries_1_io_chi_tx_req_bits_opcode),
+    .io_in_1_bits_size               (_entries_1_io_chi_tx_req_bits_size),
+    .io_in_1_bits_addr               (_entries_1_io_chi_tx_req_bits_addr),
+    .io_in_1_bits_likelyshared       (1'h0),
+    .io_in_1_bits_allowRetry         (_entries_1_io_chi_tx_req_bits_allowRetry),
+    .io_in_1_bits_order              (_entries_1_io_chi_tx_req_bits_order),
+    .io_in_1_bits_pCrdType           (_entries_1_io_chi_tx_req_bits_pCrdType),
+    .io_in_1_bits_memAttr_allocate   (1'h0),
+    .io_in_1_bits_memAttr_cacheable  (1'h0),
+    .io_in_1_bits_memAttr_device     (_entries_1_io_chi_tx_req_bits_memAttr_device),
+    .io_in_1_bits_memAttr_ewa        (_entries_1_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_1_bits_snpAttr            (1'h0),
+    .io_in_1_bits_expCompAck         (1'h0),
+    .io_in_2_ready                   (_txreqArb_io_in_2_ready),
+    .io_in_2_valid                   (_entries_2_io_chi_tx_req_valid & ~block_2),
+    .io_in_2_bits_tgtID              (11'h0),
+    .io_in_2_bits_txnID              (_entries_2_io_chi_tx_req_bits_txnID),
+    .io_in_2_bits_opcode             (_entries_2_io_chi_tx_req_bits_opcode),
+    .io_in_2_bits_size               (_entries_2_io_chi_tx_req_bits_size),
+    .io_in_2_bits_addr               (_entries_2_io_chi_tx_req_bits_addr),
+    .io_in_2_bits_likelyshared       (1'h0),
+    .io_in_2_bits_allowRetry         (_entries_2_io_chi_tx_req_bits_allowRetry),
+    .io_in_2_bits_order              (_entries_2_io_chi_tx_req_bits_order),
+    .io_in_2_bits_pCrdType           (_entries_2_io_chi_tx_req_bits_pCrdType),
+    .io_in_2_bits_memAttr_allocate   (1'h0),
+    .io_in_2_bits_memAttr_cacheable  (1'h0),
+    .io_in_2_bits_memAttr_device     (_entries_2_io_chi_tx_req_bits_memAttr_device),
+    .io_in_2_bits_memAttr_ewa        (_entries_2_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_2_bits_snpAttr            (1'h0),
+    .io_in_2_bits_expCompAck         (1'h0),
+    .io_in_3_ready                   (_txreqArb_io_in_3_ready),
+    .io_in_3_valid                   (_entries_3_io_chi_tx_req_valid & ~block_3),
+    .io_in_3_bits_tgtID              (11'h0),
+    .io_in_3_bits_txnID              (_entries_3_io_chi_tx_req_bits_txnID),
+    .io_in_3_bits_opcode             (_entries_3_io_chi_tx_req_bits_opcode),
+    .io_in_3_bits_size               (_entries_3_io_chi_tx_req_bits_size),
+    .io_in_3_bits_addr               (_entries_3_io_chi_tx_req_bits_addr),
+    .io_in_3_bits_likelyshared       (1'h0),
+    .io_in_3_bits_allowRetry         (_entries_3_io_chi_tx_req_bits_allowRetry),
+    .io_in_3_bits_order              (_entries_3_io_chi_tx_req_bits_order),
+    .io_in_3_bits_pCrdType           (_entries_3_io_chi_tx_req_bits_pCrdType),
+    .io_in_3_bits_memAttr_allocate   (1'h0),
+    .io_in_3_bits_memAttr_cacheable  (1'h0),
+    .io_in_3_bits_memAttr_device     (_entries_3_io_chi_tx_req_bits_memAttr_device),
+    .io_in_3_bits_memAttr_ewa        (_entries_3_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_3_bits_snpAttr            (1'h0),
+    .io_in_3_bits_expCompAck         (1'h0),
+    .io_in_4_ready                   (_txreqArb_io_in_4_ready),
+    .io_in_4_valid                   (_entries_4_io_chi_tx_req_valid & ~block_4),
+    .io_in_4_bits_tgtID              (11'h0),
+    .io_in_4_bits_txnID              (_entries_4_io_chi_tx_req_bits_txnID),
+    .io_in_4_bits_opcode             (_entries_4_io_chi_tx_req_bits_opcode),
+    .io_in_4_bits_size               (_entries_4_io_chi_tx_req_bits_size),
+    .io_in_4_bits_addr               (_entries_4_io_chi_tx_req_bits_addr),
+    .io_in_4_bits_likelyshared       (1'h0),
+    .io_in_4_bits_allowRetry         (_entries_4_io_chi_tx_req_bits_allowRetry),
+    .io_in_4_bits_order              (_entries_4_io_chi_tx_req_bits_order),
+    .io_in_4_bits_pCrdType           (_entries_4_io_chi_tx_req_bits_pCrdType),
+    .io_in_4_bits_memAttr_allocate   (1'h0),
+    .io_in_4_bits_memAttr_cacheable  (1'h0),
+    .io_in_4_bits_memAttr_device     (_entries_4_io_chi_tx_req_bits_memAttr_device),
+    .io_in_4_bits_memAttr_ewa        (_entries_4_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_4_bits_snpAttr            (1'h0),
+    .io_in_4_bits_expCompAck         (1'h0),
+    .io_in_5_ready                   (_txreqArb_io_in_5_ready),
+    .io_in_5_valid                   (_entries_5_io_chi_tx_req_valid & ~block_5),
+    .io_in_5_bits_tgtID              (11'h0),
+    .io_in_5_bits_txnID              (_entries_5_io_chi_tx_req_bits_txnID),
+    .io_in_5_bits_opcode             (_entries_5_io_chi_tx_req_bits_opcode),
+    .io_in_5_bits_size               (_entries_5_io_chi_tx_req_bits_size),
+    .io_in_5_bits_addr               (_entries_5_io_chi_tx_req_bits_addr),
+    .io_in_5_bits_likelyshared       (1'h0),
+    .io_in_5_bits_allowRetry         (_entries_5_io_chi_tx_req_bits_allowRetry),
+    .io_in_5_bits_order              (_entries_5_io_chi_tx_req_bits_order),
+    .io_in_5_bits_pCrdType           (_entries_5_io_chi_tx_req_bits_pCrdType),
+    .io_in_5_bits_memAttr_allocate   (1'h0),
+    .io_in_5_bits_memAttr_cacheable  (1'h0),
+    .io_in_5_bits_memAttr_device     (_entries_5_io_chi_tx_req_bits_memAttr_device),
+    .io_in_5_bits_memAttr_ewa        (_entries_5_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_5_bits_snpAttr            (1'h0),
+    .io_in_5_bits_expCompAck         (1'h0),
+    .io_in_6_ready                   (_txreqArb_io_in_6_ready),
+    .io_in_6_valid                   (_entries_6_io_chi_tx_req_valid & ~block_6),
+    .io_in_6_bits_tgtID              (11'h0),
+    .io_in_6_bits_txnID              (_entries_6_io_chi_tx_req_bits_txnID),
+    .io_in_6_bits_opcode             (_entries_6_io_chi_tx_req_bits_opcode),
+    .io_in_6_bits_size               (_entries_6_io_chi_tx_req_bits_size),
+    .io_in_6_bits_addr               (_entries_6_io_chi_tx_req_bits_addr),
+    .io_in_6_bits_likelyshared       (1'h0),
+    .io_in_6_bits_allowRetry         (_entries_6_io_chi_tx_req_bits_allowRetry),
+    .io_in_6_bits_order              (_entries_6_io_chi_tx_req_bits_order),
+    .io_in_6_bits_pCrdType           (_entries_6_io_chi_tx_req_bits_pCrdType),
+    .io_in_6_bits_memAttr_allocate   (1'h0),
+    .io_in_6_bits_memAttr_cacheable  (1'h0),
+    .io_in_6_bits_memAttr_device     (_entries_6_io_chi_tx_req_bits_memAttr_device),
+    .io_in_6_bits_memAttr_ewa        (_entries_6_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_6_bits_snpAttr            (1'h0),
+    .io_in_6_bits_expCompAck         (1'h0),
+    .io_in_7_ready                   (_txreqArb_io_in_7_ready),
+    .io_in_7_valid                   (_entries_7_io_chi_tx_req_valid & ~block_7),
+    .io_in_7_bits_tgtID              (11'h0),
+    .io_in_7_bits_txnID              (_entries_7_io_chi_tx_req_bits_txnID),
+    .io_in_7_bits_opcode             (_entries_7_io_chi_tx_req_bits_opcode),
+    .io_in_7_bits_size               (_entries_7_io_chi_tx_req_bits_size),
+    .io_in_7_bits_addr               (_entries_7_io_chi_tx_req_bits_addr),
+    .io_in_7_bits_likelyshared       (1'h0),
+    .io_in_7_bits_allowRetry         (_entries_7_io_chi_tx_req_bits_allowRetry),
+    .io_in_7_bits_order              (_entries_7_io_chi_tx_req_bits_order),
+    .io_in_7_bits_pCrdType           (_entries_7_io_chi_tx_req_bits_pCrdType),
+    .io_in_7_bits_memAttr_allocate   (1'h0),
+    .io_in_7_bits_memAttr_cacheable  (1'h0),
+    .io_in_7_bits_memAttr_device     (_entries_7_io_chi_tx_req_bits_memAttr_device),
+    .io_in_7_bits_memAttr_ewa        (_entries_7_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_7_bits_snpAttr            (1'h0),
+    .io_in_7_bits_expCompAck         (1'h0),
+    .io_in_8_ready                   (_txreqArb_io_in_8_ready),
+    .io_in_8_valid                   (_entries_8_io_chi_tx_req_valid & ~block_8),
+    .io_in_8_bits_tgtID              (11'h0),
+    .io_in_8_bits_txnID              (_entries_8_io_chi_tx_req_bits_txnID),
+    .io_in_8_bits_opcode             (_entries_8_io_chi_tx_req_bits_opcode),
+    .io_in_8_bits_size               (_entries_8_io_chi_tx_req_bits_size),
+    .io_in_8_bits_addr               (_entries_8_io_chi_tx_req_bits_addr),
+    .io_in_8_bits_likelyshared       (1'h0),
+    .io_in_8_bits_allowRetry         (_entries_8_io_chi_tx_req_bits_allowRetry),
+    .io_in_8_bits_order              (_entries_8_io_chi_tx_req_bits_order),
+    .io_in_8_bits_pCrdType           (_entries_8_io_chi_tx_req_bits_pCrdType),
+    .io_in_8_bits_memAttr_allocate   (1'h0),
+    .io_in_8_bits_memAttr_cacheable  (1'h0),
+    .io_in_8_bits_memAttr_device     (_entries_8_io_chi_tx_req_bits_memAttr_device),
+    .io_in_8_bits_memAttr_ewa        (_entries_8_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_8_bits_snpAttr            (1'h0),
+    .io_in_8_bits_expCompAck         (1'h0),
+    .io_in_9_ready                   (_txreqArb_io_in_9_ready),
+    .io_in_9_valid                   (_entries_9_io_chi_tx_req_valid & ~block_9),
+    .io_in_9_bits_tgtID              (11'h0),
+    .io_in_9_bits_txnID              (_entries_9_io_chi_tx_req_bits_txnID),
+    .io_in_9_bits_opcode             (_entries_9_io_chi_tx_req_bits_opcode),
+    .io_in_9_bits_size               (_entries_9_io_chi_tx_req_bits_size),
+    .io_in_9_bits_addr               (_entries_9_io_chi_tx_req_bits_addr),
+    .io_in_9_bits_likelyshared       (1'h0),
+    .io_in_9_bits_allowRetry         (_entries_9_io_chi_tx_req_bits_allowRetry),
+    .io_in_9_bits_order              (_entries_9_io_chi_tx_req_bits_order),
+    .io_in_9_bits_pCrdType           (_entries_9_io_chi_tx_req_bits_pCrdType),
+    .io_in_9_bits_memAttr_allocate   (1'h0),
+    .io_in_9_bits_memAttr_cacheable  (1'h0),
+    .io_in_9_bits_memAttr_device     (_entries_9_io_chi_tx_req_bits_memAttr_device),
+    .io_in_9_bits_memAttr_ewa        (_entries_9_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_9_bits_snpAttr            (1'h0),
+    .io_in_9_bits_expCompAck         (1'h0),
+    .io_in_10_ready                  (_txreqArb_io_in_10_ready),
+    .io_in_10_valid                  (_entries_10_io_chi_tx_req_valid & ~block_10),
+    .io_in_10_bits_tgtID             (11'h0),
+    .io_in_10_bits_txnID             (_entries_10_io_chi_tx_req_bits_txnID),
+    .io_in_10_bits_opcode            (_entries_10_io_chi_tx_req_bits_opcode),
+    .io_in_10_bits_size              (_entries_10_io_chi_tx_req_bits_size),
+    .io_in_10_bits_addr              (_entries_10_io_chi_tx_req_bits_addr),
+    .io_in_10_bits_likelyshared      (1'h0),
+    .io_in_10_bits_allowRetry        (_entries_10_io_chi_tx_req_bits_allowRetry),
+    .io_in_10_bits_order             (_entries_10_io_chi_tx_req_bits_order),
+    .io_in_10_bits_pCrdType          (_entries_10_io_chi_tx_req_bits_pCrdType),
+    .io_in_10_bits_memAttr_allocate  (1'h0),
+    .io_in_10_bits_memAttr_cacheable (1'h0),
+    .io_in_10_bits_memAttr_device    (_entries_10_io_chi_tx_req_bits_memAttr_device),
+    .io_in_10_bits_memAttr_ewa       (_entries_10_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_10_bits_snpAttr           (1'h0),
+    .io_in_10_bits_expCompAck        (1'h0),
+    .io_in_11_ready                  (_txreqArb_io_in_11_ready),
+    .io_in_11_valid                  (_entries_11_io_chi_tx_req_valid & ~block_11),
+    .io_in_11_bits_tgtID             (11'h0),
+    .io_in_11_bits_txnID             (_entries_11_io_chi_tx_req_bits_txnID),
+    .io_in_11_bits_opcode            (_entries_11_io_chi_tx_req_bits_opcode),
+    .io_in_11_bits_size              (_entries_11_io_chi_tx_req_bits_size),
+    .io_in_11_bits_addr              (_entries_11_io_chi_tx_req_bits_addr),
+    .io_in_11_bits_likelyshared      (1'h0),
+    .io_in_11_bits_allowRetry        (_entries_11_io_chi_tx_req_bits_allowRetry),
+    .io_in_11_bits_order             (_entries_11_io_chi_tx_req_bits_order),
+    .io_in_11_bits_pCrdType          (_entries_11_io_chi_tx_req_bits_pCrdType),
+    .io_in_11_bits_memAttr_allocate  (1'h0),
+    .io_in_11_bits_memAttr_cacheable (1'h0),
+    .io_in_11_bits_memAttr_device    (_entries_11_io_chi_tx_req_bits_memAttr_device),
+    .io_in_11_bits_memAttr_ewa       (_entries_11_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_11_bits_snpAttr           (1'h0),
+    .io_in_11_bits_expCompAck        (1'h0),
+    .io_in_12_ready                  (_txreqArb_io_in_12_ready),
+    .io_in_12_valid                  (_entries_12_io_chi_tx_req_valid & ~block_12),
+    .io_in_12_bits_tgtID             (11'h0),
+    .io_in_12_bits_txnID             (_entries_12_io_chi_tx_req_bits_txnID),
+    .io_in_12_bits_opcode            (_entries_12_io_chi_tx_req_bits_opcode),
+    .io_in_12_bits_size              (_entries_12_io_chi_tx_req_bits_size),
+    .io_in_12_bits_addr              (_entries_12_io_chi_tx_req_bits_addr),
+    .io_in_12_bits_likelyshared      (1'h0),
+    .io_in_12_bits_allowRetry        (_entries_12_io_chi_tx_req_bits_allowRetry),
+    .io_in_12_bits_order             (_entries_12_io_chi_tx_req_bits_order),
+    .io_in_12_bits_pCrdType          (_entries_12_io_chi_tx_req_bits_pCrdType),
+    .io_in_12_bits_memAttr_allocate  (1'h0),
+    .io_in_12_bits_memAttr_cacheable (1'h0),
+    .io_in_12_bits_memAttr_device    (_entries_12_io_chi_tx_req_bits_memAttr_device),
+    .io_in_12_bits_memAttr_ewa       (_entries_12_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_12_bits_snpAttr           (1'h0),
+    .io_in_12_bits_expCompAck        (1'h0),
+    .io_in_13_ready                  (_txreqArb_io_in_13_ready),
+    .io_in_13_valid                  (_entries_13_io_chi_tx_req_valid & ~block_13),
+    .io_in_13_bits_tgtID             (11'h0),
+    .io_in_13_bits_txnID             (_entries_13_io_chi_tx_req_bits_txnID),
+    .io_in_13_bits_opcode            (_entries_13_io_chi_tx_req_bits_opcode),
+    .io_in_13_bits_size              (_entries_13_io_chi_tx_req_bits_size),
+    .io_in_13_bits_addr              (_entries_13_io_chi_tx_req_bits_addr),
+    .io_in_13_bits_likelyshared      (1'h0),
+    .io_in_13_bits_allowRetry        (_entries_13_io_chi_tx_req_bits_allowRetry),
+    .io_in_13_bits_order             (_entries_13_io_chi_tx_req_bits_order),
+    .io_in_13_bits_pCrdType          (_entries_13_io_chi_tx_req_bits_pCrdType),
+    .io_in_13_bits_memAttr_allocate  (1'h0),
+    .io_in_13_bits_memAttr_cacheable (1'h0),
+    .io_in_13_bits_memAttr_device    (_entries_13_io_chi_tx_req_bits_memAttr_device),
+    .io_in_13_bits_memAttr_ewa       (_entries_13_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_13_bits_snpAttr           (1'h0),
+    .io_in_13_bits_expCompAck        (1'h0),
+    .io_in_14_ready                  (_txreqArb_io_in_14_ready),
+    .io_in_14_valid                  (_entries_14_io_chi_tx_req_valid & ~block_14),
+    .io_in_14_bits_tgtID             (11'h0),
+    .io_in_14_bits_txnID             (_entries_14_io_chi_tx_req_bits_txnID),
+    .io_in_14_bits_opcode            (_entries_14_io_chi_tx_req_bits_opcode),
+    .io_in_14_bits_size              (_entries_14_io_chi_tx_req_bits_size),
+    .io_in_14_bits_addr              (_entries_14_io_chi_tx_req_bits_addr),
+    .io_in_14_bits_likelyshared      (1'h0),
+    .io_in_14_bits_allowRetry        (_entries_14_io_chi_tx_req_bits_allowRetry),
+    .io_in_14_bits_order             (_entries_14_io_chi_tx_req_bits_order),
+    .io_in_14_bits_pCrdType          (_entries_14_io_chi_tx_req_bits_pCrdType),
+    .io_in_14_bits_memAttr_allocate  (1'h0),
+    .io_in_14_bits_memAttr_cacheable (1'h0),
+    .io_in_14_bits_memAttr_device    (_entries_14_io_chi_tx_req_bits_memAttr_device),
+    .io_in_14_bits_memAttr_ewa       (_entries_14_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_14_bits_snpAttr           (1'h0),
+    .io_in_14_bits_expCompAck        (1'h0),
+    .io_in_15_ready                  (_txreqArb_io_in_15_ready),
+    .io_in_15_valid                  (_entries_15_io_chi_tx_req_valid & ~block_15),
+    .io_in_15_bits_tgtID             (11'h0),
+    .io_in_15_bits_txnID             (_entries_15_io_chi_tx_req_bits_txnID),
+    .io_in_15_bits_opcode            (_entries_15_io_chi_tx_req_bits_opcode),
+    .io_in_15_bits_size              (_entries_15_io_chi_tx_req_bits_size),
+    .io_in_15_bits_addr              (_entries_15_io_chi_tx_req_bits_addr),
+    .io_in_15_bits_likelyshared      (1'h0),
+    .io_in_15_bits_allowRetry        (_entries_15_io_chi_tx_req_bits_allowRetry),
+    .io_in_15_bits_order             (_entries_15_io_chi_tx_req_bits_order),
+    .io_in_15_bits_pCrdType          (_entries_15_io_chi_tx_req_bits_pCrdType),
+    .io_in_15_bits_memAttr_allocate  (1'h0),
+    .io_in_15_bits_memAttr_cacheable (1'h0),
+    .io_in_15_bits_memAttr_device    (_entries_15_io_chi_tx_req_bits_memAttr_device),
+    .io_in_15_bits_memAttr_ewa       (_entries_15_io_chi_tx_req_bits_memAttr_ewa),
+    .io_in_15_bits_snpAttr           (1'h0),
+    .io_in_15_bits_expCompAck        (1'h0),
+    .io_out_ready                    (io_tx_req_ready),
+    .io_out_valid                    (io_tx_req_valid),
+    .io_out_bits_qos                 (io_tx_req_bits_qos),
+    .io_out_bits_tgtID               (io_tx_req_bits_tgtID),
+    .io_out_bits_txnID               (io_tx_req_bits_txnID),
+    .io_out_bits_opcode              (io_tx_req_bits_opcode),
+    .io_out_bits_size                (io_tx_req_bits_size),
+    .io_out_bits_addr                (io_tx_req_bits_addr),
+    .io_out_bits_likelyshared        (io_tx_req_bits_likelyshared),
+    .io_out_bits_allowRetry          (io_tx_req_bits_allowRetry),
+    .io_out_bits_order               (io_tx_req_bits_order),
+    .io_out_bits_pCrdType            (io_tx_req_bits_pCrdType),
+    .io_out_bits_memAttr_allocate    (io_tx_req_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable   (io_tx_req_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device      (io_tx_req_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa         (io_tx_req_bits_memAttr_ewa),
+    .io_out_bits_snpAttr             (io_tx_req_bits_snpAttr),
+    .io_out_bits_expCompAck          (io_tx_req_bits_expCompAck)
+  );
+  Arbiter16_CHIDAT mmio_txdat_arb (
+    .io_in_0_ready           (_mmio_txdat_arb_io_in_0_ready),
+    .io_in_0_valid           (_entries_0_io_chi_tx_dat_valid),
+    .io_in_0_bits_tgtID      (_entries_0_io_chi_tx_dat_bits_tgtID),
+    .io_in_0_bits_txnID      (_entries_0_io_chi_tx_dat_bits_txnID),
+    .io_in_0_bits_respErr    (_entries_0_io_chi_tx_dat_bits_respErr),
+    .io_in_0_bits_ccID       (_entries_0_io_chi_tx_dat_bits_ccID),
+    .io_in_0_bits_dataID     (_entries_0_io_chi_tx_dat_bits_dataID),
+    .io_in_0_bits_traceTag   (_entries_0_io_chi_tx_dat_bits_traceTag),
+    .io_in_0_bits_be         (_entries_0_io_chi_tx_dat_bits_be),
+    .io_in_0_bits_data       (_entries_0_io_chi_tx_dat_bits_data),
+    .io_in_0_bits_dataCheck  (_entries_0_io_chi_tx_dat_bits_dataCheck),
+    .io_in_0_bits_poison     (_entries_0_io_chi_tx_dat_bits_poison),
+    .io_in_1_ready           (_mmio_txdat_arb_io_in_1_ready),
+    .io_in_1_valid           (_entries_1_io_chi_tx_dat_valid),
+    .io_in_1_bits_tgtID      (_entries_1_io_chi_tx_dat_bits_tgtID),
+    .io_in_1_bits_txnID      (_entries_1_io_chi_tx_dat_bits_txnID),
+    .io_in_1_bits_respErr    (_entries_1_io_chi_tx_dat_bits_respErr),
+    .io_in_1_bits_ccID       (_entries_1_io_chi_tx_dat_bits_ccID),
+    .io_in_1_bits_dataID     (_entries_1_io_chi_tx_dat_bits_dataID),
+    .io_in_1_bits_traceTag   (_entries_1_io_chi_tx_dat_bits_traceTag),
+    .io_in_1_bits_be         (_entries_1_io_chi_tx_dat_bits_be),
+    .io_in_1_bits_data       (_entries_1_io_chi_tx_dat_bits_data),
+    .io_in_1_bits_dataCheck  (_entries_1_io_chi_tx_dat_bits_dataCheck),
+    .io_in_1_bits_poison     (_entries_1_io_chi_tx_dat_bits_poison),
+    .io_in_2_ready           (_mmio_txdat_arb_io_in_2_ready),
+    .io_in_2_valid           (_entries_2_io_chi_tx_dat_valid),
+    .io_in_2_bits_tgtID      (_entries_2_io_chi_tx_dat_bits_tgtID),
+    .io_in_2_bits_txnID      (_entries_2_io_chi_tx_dat_bits_txnID),
+    .io_in_2_bits_respErr    (_entries_2_io_chi_tx_dat_bits_respErr),
+    .io_in_2_bits_ccID       (_entries_2_io_chi_tx_dat_bits_ccID),
+    .io_in_2_bits_dataID     (_entries_2_io_chi_tx_dat_bits_dataID),
+    .io_in_2_bits_traceTag   (_entries_2_io_chi_tx_dat_bits_traceTag),
+    .io_in_2_bits_be         (_entries_2_io_chi_tx_dat_bits_be),
+    .io_in_2_bits_data       (_entries_2_io_chi_tx_dat_bits_data),
+    .io_in_2_bits_dataCheck  (_entries_2_io_chi_tx_dat_bits_dataCheck),
+    .io_in_2_bits_poison     (_entries_2_io_chi_tx_dat_bits_poison),
+    .io_in_3_ready           (_mmio_txdat_arb_io_in_3_ready),
+    .io_in_3_valid           (_entries_3_io_chi_tx_dat_valid),
+    .io_in_3_bits_tgtID      (_entries_3_io_chi_tx_dat_bits_tgtID),
+    .io_in_3_bits_txnID      (_entries_3_io_chi_tx_dat_bits_txnID),
+    .io_in_3_bits_respErr    (_entries_3_io_chi_tx_dat_bits_respErr),
+    .io_in_3_bits_ccID       (_entries_3_io_chi_tx_dat_bits_ccID),
+    .io_in_3_bits_dataID     (_entries_3_io_chi_tx_dat_bits_dataID),
+    .io_in_3_bits_traceTag   (_entries_3_io_chi_tx_dat_bits_traceTag),
+    .io_in_3_bits_be         (_entries_3_io_chi_tx_dat_bits_be),
+    .io_in_3_bits_data       (_entries_3_io_chi_tx_dat_bits_data),
+    .io_in_3_bits_dataCheck  (_entries_3_io_chi_tx_dat_bits_dataCheck),
+    .io_in_3_bits_poison     (_entries_3_io_chi_tx_dat_bits_poison),
+    .io_in_4_ready           (_mmio_txdat_arb_io_in_4_ready),
+    .io_in_4_valid           (_entries_4_io_chi_tx_dat_valid),
+    .io_in_4_bits_tgtID      (_entries_4_io_chi_tx_dat_bits_tgtID),
+    .io_in_4_bits_txnID      (_entries_4_io_chi_tx_dat_bits_txnID),
+    .io_in_4_bits_respErr    (_entries_4_io_chi_tx_dat_bits_respErr),
+    .io_in_4_bits_ccID       (_entries_4_io_chi_tx_dat_bits_ccID),
+    .io_in_4_bits_dataID     (_entries_4_io_chi_tx_dat_bits_dataID),
+    .io_in_4_bits_traceTag   (_entries_4_io_chi_tx_dat_bits_traceTag),
+    .io_in_4_bits_be         (_entries_4_io_chi_tx_dat_bits_be),
+    .io_in_4_bits_data       (_entries_4_io_chi_tx_dat_bits_data),
+    .io_in_4_bits_dataCheck  (_entries_4_io_chi_tx_dat_bits_dataCheck),
+    .io_in_4_bits_poison     (_entries_4_io_chi_tx_dat_bits_poison),
+    .io_in_5_ready           (_mmio_txdat_arb_io_in_5_ready),
+    .io_in_5_valid           (_entries_5_io_chi_tx_dat_valid),
+    .io_in_5_bits_tgtID      (_entries_5_io_chi_tx_dat_bits_tgtID),
+    .io_in_5_bits_txnID      (_entries_5_io_chi_tx_dat_bits_txnID),
+    .io_in_5_bits_respErr    (_entries_5_io_chi_tx_dat_bits_respErr),
+    .io_in_5_bits_ccID       (_entries_5_io_chi_tx_dat_bits_ccID),
+    .io_in_5_bits_dataID     (_entries_5_io_chi_tx_dat_bits_dataID),
+    .io_in_5_bits_traceTag   (_entries_5_io_chi_tx_dat_bits_traceTag),
+    .io_in_5_bits_be         (_entries_5_io_chi_tx_dat_bits_be),
+    .io_in_5_bits_data       (_entries_5_io_chi_tx_dat_bits_data),
+    .io_in_5_bits_dataCheck  (_entries_5_io_chi_tx_dat_bits_dataCheck),
+    .io_in_5_bits_poison     (_entries_5_io_chi_tx_dat_bits_poison),
+    .io_in_6_ready           (_mmio_txdat_arb_io_in_6_ready),
+    .io_in_6_valid           (_entries_6_io_chi_tx_dat_valid),
+    .io_in_6_bits_tgtID      (_entries_6_io_chi_tx_dat_bits_tgtID),
+    .io_in_6_bits_txnID      (_entries_6_io_chi_tx_dat_bits_txnID),
+    .io_in_6_bits_respErr    (_entries_6_io_chi_tx_dat_bits_respErr),
+    .io_in_6_bits_ccID       (_entries_6_io_chi_tx_dat_bits_ccID),
+    .io_in_6_bits_dataID     (_entries_6_io_chi_tx_dat_bits_dataID),
+    .io_in_6_bits_traceTag   (_entries_6_io_chi_tx_dat_bits_traceTag),
+    .io_in_6_bits_be         (_entries_6_io_chi_tx_dat_bits_be),
+    .io_in_6_bits_data       (_entries_6_io_chi_tx_dat_bits_data),
+    .io_in_6_bits_dataCheck  (_entries_6_io_chi_tx_dat_bits_dataCheck),
+    .io_in_6_bits_poison     (_entries_6_io_chi_tx_dat_bits_poison),
+    .io_in_7_ready           (_mmio_txdat_arb_io_in_7_ready),
+    .io_in_7_valid           (_entries_7_io_chi_tx_dat_valid),
+    .io_in_7_bits_tgtID      (_entries_7_io_chi_tx_dat_bits_tgtID),
+    .io_in_7_bits_txnID      (_entries_7_io_chi_tx_dat_bits_txnID),
+    .io_in_7_bits_respErr    (_entries_7_io_chi_tx_dat_bits_respErr),
+    .io_in_7_bits_ccID       (_entries_7_io_chi_tx_dat_bits_ccID),
+    .io_in_7_bits_dataID     (_entries_7_io_chi_tx_dat_bits_dataID),
+    .io_in_7_bits_traceTag   (_entries_7_io_chi_tx_dat_bits_traceTag),
+    .io_in_7_bits_be         (_entries_7_io_chi_tx_dat_bits_be),
+    .io_in_7_bits_data       (_entries_7_io_chi_tx_dat_bits_data),
+    .io_in_7_bits_dataCheck  (_entries_7_io_chi_tx_dat_bits_dataCheck),
+    .io_in_7_bits_poison     (_entries_7_io_chi_tx_dat_bits_poison),
+    .io_in_8_ready           (_mmio_txdat_arb_io_in_8_ready),
+    .io_in_8_valid           (_entries_8_io_chi_tx_dat_valid),
+    .io_in_8_bits_tgtID      (_entries_8_io_chi_tx_dat_bits_tgtID),
+    .io_in_8_bits_txnID      (_entries_8_io_chi_tx_dat_bits_txnID),
+    .io_in_8_bits_respErr    (_entries_8_io_chi_tx_dat_bits_respErr),
+    .io_in_8_bits_ccID       (_entries_8_io_chi_tx_dat_bits_ccID),
+    .io_in_8_bits_dataID     (_entries_8_io_chi_tx_dat_bits_dataID),
+    .io_in_8_bits_traceTag   (_entries_8_io_chi_tx_dat_bits_traceTag),
+    .io_in_8_bits_be         (_entries_8_io_chi_tx_dat_bits_be),
+    .io_in_8_bits_data       (_entries_8_io_chi_tx_dat_bits_data),
+    .io_in_8_bits_dataCheck  (_entries_8_io_chi_tx_dat_bits_dataCheck),
+    .io_in_8_bits_poison     (_entries_8_io_chi_tx_dat_bits_poison),
+    .io_in_9_ready           (_mmio_txdat_arb_io_in_9_ready),
+    .io_in_9_valid           (_entries_9_io_chi_tx_dat_valid),
+    .io_in_9_bits_tgtID      (_entries_9_io_chi_tx_dat_bits_tgtID),
+    .io_in_9_bits_txnID      (_entries_9_io_chi_tx_dat_bits_txnID),
+    .io_in_9_bits_respErr    (_entries_9_io_chi_tx_dat_bits_respErr),
+    .io_in_9_bits_ccID       (_entries_9_io_chi_tx_dat_bits_ccID),
+    .io_in_9_bits_dataID     (_entries_9_io_chi_tx_dat_bits_dataID),
+    .io_in_9_bits_traceTag   (_entries_9_io_chi_tx_dat_bits_traceTag),
+    .io_in_9_bits_be         (_entries_9_io_chi_tx_dat_bits_be),
+    .io_in_9_bits_data       (_entries_9_io_chi_tx_dat_bits_data),
+    .io_in_9_bits_dataCheck  (_entries_9_io_chi_tx_dat_bits_dataCheck),
+    .io_in_9_bits_poison     (_entries_9_io_chi_tx_dat_bits_poison),
+    .io_in_10_ready          (_mmio_txdat_arb_io_in_10_ready),
+    .io_in_10_valid          (_entries_10_io_chi_tx_dat_valid),
+    .io_in_10_bits_tgtID     (_entries_10_io_chi_tx_dat_bits_tgtID),
+    .io_in_10_bits_txnID     (_entries_10_io_chi_tx_dat_bits_txnID),
+    .io_in_10_bits_respErr   (_entries_10_io_chi_tx_dat_bits_respErr),
+    .io_in_10_bits_ccID      (_entries_10_io_chi_tx_dat_bits_ccID),
+    .io_in_10_bits_dataID    (_entries_10_io_chi_tx_dat_bits_dataID),
+    .io_in_10_bits_traceTag  (_entries_10_io_chi_tx_dat_bits_traceTag),
+    .io_in_10_bits_be        (_entries_10_io_chi_tx_dat_bits_be),
+    .io_in_10_bits_data      (_entries_10_io_chi_tx_dat_bits_data),
+    .io_in_10_bits_dataCheck (_entries_10_io_chi_tx_dat_bits_dataCheck),
+    .io_in_10_bits_poison    (_entries_10_io_chi_tx_dat_bits_poison),
+    .io_in_11_ready          (_mmio_txdat_arb_io_in_11_ready),
+    .io_in_11_valid          (_entries_11_io_chi_tx_dat_valid),
+    .io_in_11_bits_tgtID     (_entries_11_io_chi_tx_dat_bits_tgtID),
+    .io_in_11_bits_txnID     (_entries_11_io_chi_tx_dat_bits_txnID),
+    .io_in_11_bits_respErr   (_entries_11_io_chi_tx_dat_bits_respErr),
+    .io_in_11_bits_ccID      (_entries_11_io_chi_tx_dat_bits_ccID),
+    .io_in_11_bits_dataID    (_entries_11_io_chi_tx_dat_bits_dataID),
+    .io_in_11_bits_traceTag  (_entries_11_io_chi_tx_dat_bits_traceTag),
+    .io_in_11_bits_be        (_entries_11_io_chi_tx_dat_bits_be),
+    .io_in_11_bits_data      (_entries_11_io_chi_tx_dat_bits_data),
+    .io_in_11_bits_dataCheck (_entries_11_io_chi_tx_dat_bits_dataCheck),
+    .io_in_11_bits_poison    (_entries_11_io_chi_tx_dat_bits_poison),
+    .io_in_12_ready          (_mmio_txdat_arb_io_in_12_ready),
+    .io_in_12_valid          (_entries_12_io_chi_tx_dat_valid),
+    .io_in_12_bits_tgtID     (_entries_12_io_chi_tx_dat_bits_tgtID),
+    .io_in_12_bits_txnID     (_entries_12_io_chi_tx_dat_bits_txnID),
+    .io_in_12_bits_respErr   (_entries_12_io_chi_tx_dat_bits_respErr),
+    .io_in_12_bits_ccID      (_entries_12_io_chi_tx_dat_bits_ccID),
+    .io_in_12_bits_dataID    (_entries_12_io_chi_tx_dat_bits_dataID),
+    .io_in_12_bits_traceTag  (_entries_12_io_chi_tx_dat_bits_traceTag),
+    .io_in_12_bits_be        (_entries_12_io_chi_tx_dat_bits_be),
+    .io_in_12_bits_data      (_entries_12_io_chi_tx_dat_bits_data),
+    .io_in_12_bits_dataCheck (_entries_12_io_chi_tx_dat_bits_dataCheck),
+    .io_in_12_bits_poison    (_entries_12_io_chi_tx_dat_bits_poison),
+    .io_in_13_ready          (_mmio_txdat_arb_io_in_13_ready),
+    .io_in_13_valid          (_entries_13_io_chi_tx_dat_valid),
+    .io_in_13_bits_tgtID     (_entries_13_io_chi_tx_dat_bits_tgtID),
+    .io_in_13_bits_txnID     (_entries_13_io_chi_tx_dat_bits_txnID),
+    .io_in_13_bits_respErr   (_entries_13_io_chi_tx_dat_bits_respErr),
+    .io_in_13_bits_ccID      (_entries_13_io_chi_tx_dat_bits_ccID),
+    .io_in_13_bits_dataID    (_entries_13_io_chi_tx_dat_bits_dataID),
+    .io_in_13_bits_traceTag  (_entries_13_io_chi_tx_dat_bits_traceTag),
+    .io_in_13_bits_be        (_entries_13_io_chi_tx_dat_bits_be),
+    .io_in_13_bits_data      (_entries_13_io_chi_tx_dat_bits_data),
+    .io_in_13_bits_dataCheck (_entries_13_io_chi_tx_dat_bits_dataCheck),
+    .io_in_13_bits_poison    (_entries_13_io_chi_tx_dat_bits_poison),
+    .io_in_14_ready          (_mmio_txdat_arb_io_in_14_ready),
+    .io_in_14_valid          (_entries_14_io_chi_tx_dat_valid),
+    .io_in_14_bits_tgtID     (_entries_14_io_chi_tx_dat_bits_tgtID),
+    .io_in_14_bits_txnID     (_entries_14_io_chi_tx_dat_bits_txnID),
+    .io_in_14_bits_respErr   (_entries_14_io_chi_tx_dat_bits_respErr),
+    .io_in_14_bits_ccID      (_entries_14_io_chi_tx_dat_bits_ccID),
+    .io_in_14_bits_dataID    (_entries_14_io_chi_tx_dat_bits_dataID),
+    .io_in_14_bits_traceTag  (_entries_14_io_chi_tx_dat_bits_traceTag),
+    .io_in_14_bits_be        (_entries_14_io_chi_tx_dat_bits_be),
+    .io_in_14_bits_data      (_entries_14_io_chi_tx_dat_bits_data),
+    .io_in_14_bits_dataCheck (_entries_14_io_chi_tx_dat_bits_dataCheck),
+    .io_in_14_bits_poison    (_entries_14_io_chi_tx_dat_bits_poison),
+    .io_in_15_ready          (_mmio_txdat_arb_io_in_15_ready),
+    .io_in_15_valid          (_entries_15_io_chi_tx_dat_valid),
+    .io_in_15_bits_tgtID     (_entries_15_io_chi_tx_dat_bits_tgtID),
+    .io_in_15_bits_txnID     (_entries_15_io_chi_tx_dat_bits_txnID),
+    .io_in_15_bits_respErr   (_entries_15_io_chi_tx_dat_bits_respErr),
+    .io_in_15_bits_ccID      (_entries_15_io_chi_tx_dat_bits_ccID),
+    .io_in_15_bits_dataID    (_entries_15_io_chi_tx_dat_bits_dataID),
+    .io_in_15_bits_traceTag  (_entries_15_io_chi_tx_dat_bits_traceTag),
+    .io_in_15_bits_be        (_entries_15_io_chi_tx_dat_bits_be),
+    .io_in_15_bits_data      (_entries_15_io_chi_tx_dat_bits_data),
+    .io_in_15_bits_dataCheck (_entries_15_io_chi_tx_dat_bits_dataCheck),
+    .io_in_15_bits_poison    (_entries_15_io_chi_tx_dat_bits_poison),
+    .io_out_ready            (io_tx_dat_ready),
+    .io_out_valid            (io_tx_dat_valid),
+    .io_out_bits_tgtID       (io_tx_dat_bits_tgtID),
+    .io_out_bits_txnID       (io_tx_dat_bits_txnID),
+    .io_out_bits_respErr     (io_tx_dat_bits_respErr),
+    .io_out_bits_ccID        (io_tx_dat_bits_ccID),
+    .io_out_bits_dataID      (io_tx_dat_bits_dataID),
+    .io_out_bits_traceTag    (io_tx_dat_bits_traceTag),
+    .io_out_bits_be          (io_tx_dat_bits_be),
+    .io_out_bits_data        (io_tx_dat_bits_data),
+    .io_out_bits_dataCheck   (io_tx_dat_bits_dataCheck),
+    .io_out_bits_poison      (io_tx_dat_bits_poison)
+  );
+  Arbiter16_TLBundleD mmio_channel_D_arb (
+    .io_in_0_ready         (_mmio_channel_D_arb_io_in_0_ready),
+    .io_in_0_valid         (_entries_0_io_resp_valid),
+    .io_in_0_bits_opcode   (_entries_0_io_resp_bits_opcode),
+    .io_in_0_bits_size     (_entries_0_io_resp_bits_size),
+    .io_in_0_bits_source   (_entries_0_io_resp_bits_source),
+    .io_in_0_bits_denied   (_entries_0_io_resp_bits_denied),
+    .io_in_0_bits_data     (_entries_0_io_resp_bits_data),
+    .io_in_0_bits_corrupt  (_entries_0_io_resp_bits_corrupt),
+    .io_in_1_ready         (_mmio_channel_D_arb_io_in_1_ready),
+    .io_in_1_valid         (_entries_1_io_resp_valid),
+    .io_in_1_bits_opcode   (_entries_1_io_resp_bits_opcode),
+    .io_in_1_bits_size     (_entries_1_io_resp_bits_size),
+    .io_in_1_bits_source   (_entries_1_io_resp_bits_source),
+    .io_in_1_bits_denied   (_entries_1_io_resp_bits_denied),
+    .io_in_1_bits_data     (_entries_1_io_resp_bits_data),
+    .io_in_1_bits_corrupt  (_entries_1_io_resp_bits_corrupt),
+    .io_in_2_ready         (_mmio_channel_D_arb_io_in_2_ready),
+    .io_in_2_valid         (_entries_2_io_resp_valid),
+    .io_in_2_bits_opcode   (_entries_2_io_resp_bits_opcode),
+    .io_in_2_bits_size     (_entries_2_io_resp_bits_size),
+    .io_in_2_bits_source   (_entries_2_io_resp_bits_source),
+    .io_in_2_bits_denied   (_entries_2_io_resp_bits_denied),
+    .io_in_2_bits_data     (_entries_2_io_resp_bits_data),
+    .io_in_2_bits_corrupt  (_entries_2_io_resp_bits_corrupt),
+    .io_in_3_ready         (_mmio_channel_D_arb_io_in_3_ready),
+    .io_in_3_valid         (_entries_3_io_resp_valid),
+    .io_in_3_bits_opcode   (_entries_3_io_resp_bits_opcode),
+    .io_in_3_bits_size     (_entries_3_io_resp_bits_size),
+    .io_in_3_bits_source   (_entries_3_io_resp_bits_source),
+    .io_in_3_bits_denied   (_entries_3_io_resp_bits_denied),
+    .io_in_3_bits_data     (_entries_3_io_resp_bits_data),
+    .io_in_3_bits_corrupt  (_entries_3_io_resp_bits_corrupt),
+    .io_in_4_ready         (_mmio_channel_D_arb_io_in_4_ready),
+    .io_in_4_valid         (_entries_4_io_resp_valid),
+    .io_in_4_bits_opcode   (_entries_4_io_resp_bits_opcode),
+    .io_in_4_bits_size     (_entries_4_io_resp_bits_size),
+    .io_in_4_bits_source   (_entries_4_io_resp_bits_source),
+    .io_in_4_bits_denied   (_entries_4_io_resp_bits_denied),
+    .io_in_4_bits_data     (_entries_4_io_resp_bits_data),
+    .io_in_4_bits_corrupt  (_entries_4_io_resp_bits_corrupt),
+    .io_in_5_ready         (_mmio_channel_D_arb_io_in_5_ready),
+    .io_in_5_valid         (_entries_5_io_resp_valid),
+    .io_in_5_bits_opcode   (_entries_5_io_resp_bits_opcode),
+    .io_in_5_bits_size     (_entries_5_io_resp_bits_size),
+    .io_in_5_bits_source   (_entries_5_io_resp_bits_source),
+    .io_in_5_bits_denied   (_entries_5_io_resp_bits_denied),
+    .io_in_5_bits_data     (_entries_5_io_resp_bits_data),
+    .io_in_5_bits_corrupt  (_entries_5_io_resp_bits_corrupt),
+    .io_in_6_ready         (_mmio_channel_D_arb_io_in_6_ready),
+    .io_in_6_valid         (_entries_6_io_resp_valid),
+    .io_in_6_bits_opcode   (_entries_6_io_resp_bits_opcode),
+    .io_in_6_bits_size     (_entries_6_io_resp_bits_size),
+    .io_in_6_bits_source   (_entries_6_io_resp_bits_source),
+    .io_in_6_bits_denied   (_entries_6_io_resp_bits_denied),
+    .io_in_6_bits_data     (_entries_6_io_resp_bits_data),
+    .io_in_6_bits_corrupt  (_entries_6_io_resp_bits_corrupt),
+    .io_in_7_ready         (_mmio_channel_D_arb_io_in_7_ready),
+    .io_in_7_valid         (_entries_7_io_resp_valid),
+    .io_in_7_bits_opcode   (_entries_7_io_resp_bits_opcode),
+    .io_in_7_bits_size     (_entries_7_io_resp_bits_size),
+    .io_in_7_bits_source   (_entries_7_io_resp_bits_source),
+    .io_in_7_bits_denied   (_entries_7_io_resp_bits_denied),
+    .io_in_7_bits_data     (_entries_7_io_resp_bits_data),
+    .io_in_7_bits_corrupt  (_entries_7_io_resp_bits_corrupt),
+    .io_in_8_ready         (_mmio_channel_D_arb_io_in_8_ready),
+    .io_in_8_valid         (_entries_8_io_resp_valid),
+    .io_in_8_bits_opcode   (_entries_8_io_resp_bits_opcode),
+    .io_in_8_bits_size     (_entries_8_io_resp_bits_size),
+    .io_in_8_bits_source   (_entries_8_io_resp_bits_source),
+    .io_in_8_bits_denied   (_entries_8_io_resp_bits_denied),
+    .io_in_8_bits_data     (_entries_8_io_resp_bits_data),
+    .io_in_8_bits_corrupt  (_entries_8_io_resp_bits_corrupt),
+    .io_in_9_ready         (_mmio_channel_D_arb_io_in_9_ready),
+    .io_in_9_valid         (_entries_9_io_resp_valid),
+    .io_in_9_bits_opcode   (_entries_9_io_resp_bits_opcode),
+    .io_in_9_bits_size     (_entries_9_io_resp_bits_size),
+    .io_in_9_bits_source   (_entries_9_io_resp_bits_source),
+    .io_in_9_bits_denied   (_entries_9_io_resp_bits_denied),
+    .io_in_9_bits_data     (_entries_9_io_resp_bits_data),
+    .io_in_9_bits_corrupt  (_entries_9_io_resp_bits_corrupt),
+    .io_in_10_ready        (_mmio_channel_D_arb_io_in_10_ready),
+    .io_in_10_valid        (_entries_10_io_resp_valid),
+    .io_in_10_bits_opcode  (_entries_10_io_resp_bits_opcode),
+    .io_in_10_bits_size    (_entries_10_io_resp_bits_size),
+    .io_in_10_bits_source  (_entries_10_io_resp_bits_source),
+    .io_in_10_bits_denied  (_entries_10_io_resp_bits_denied),
+    .io_in_10_bits_data    (_entries_10_io_resp_bits_data),
+    .io_in_10_bits_corrupt (_entries_10_io_resp_bits_corrupt),
+    .io_in_11_ready        (_mmio_channel_D_arb_io_in_11_ready),
+    .io_in_11_valid        (_entries_11_io_resp_valid),
+    .io_in_11_bits_opcode  (_entries_11_io_resp_bits_opcode),
+    .io_in_11_bits_size    (_entries_11_io_resp_bits_size),
+    .io_in_11_bits_source  (_entries_11_io_resp_bits_source),
+    .io_in_11_bits_denied  (_entries_11_io_resp_bits_denied),
+    .io_in_11_bits_data    (_entries_11_io_resp_bits_data),
+    .io_in_11_bits_corrupt (_entries_11_io_resp_bits_corrupt),
+    .io_in_12_ready        (_mmio_channel_D_arb_io_in_12_ready),
+    .io_in_12_valid        (_entries_12_io_resp_valid),
+    .io_in_12_bits_opcode  (_entries_12_io_resp_bits_opcode),
+    .io_in_12_bits_size    (_entries_12_io_resp_bits_size),
+    .io_in_12_bits_source  (_entries_12_io_resp_bits_source),
+    .io_in_12_bits_denied  (_entries_12_io_resp_bits_denied),
+    .io_in_12_bits_data    (_entries_12_io_resp_bits_data),
+    .io_in_12_bits_corrupt (_entries_12_io_resp_bits_corrupt),
+    .io_in_13_ready        (_mmio_channel_D_arb_io_in_13_ready),
+    .io_in_13_valid        (_entries_13_io_resp_valid),
+    .io_in_13_bits_opcode  (_entries_13_io_resp_bits_opcode),
+    .io_in_13_bits_size    (_entries_13_io_resp_bits_size),
+    .io_in_13_bits_source  (_entries_13_io_resp_bits_source),
+    .io_in_13_bits_denied  (_entries_13_io_resp_bits_denied),
+    .io_in_13_bits_data    (_entries_13_io_resp_bits_data),
+    .io_in_13_bits_corrupt (_entries_13_io_resp_bits_corrupt),
+    .io_in_14_ready        (_mmio_channel_D_arb_io_in_14_ready),
+    .io_in_14_valid        (_entries_14_io_resp_valid),
+    .io_in_14_bits_opcode  (_entries_14_io_resp_bits_opcode),
+    .io_in_14_bits_size    (_entries_14_io_resp_bits_size),
+    .io_in_14_bits_source  (_entries_14_io_resp_bits_source),
+    .io_in_14_bits_denied  (_entries_14_io_resp_bits_denied),
+    .io_in_14_bits_data    (_entries_14_io_resp_bits_data),
+    .io_in_14_bits_corrupt (_entries_14_io_resp_bits_corrupt),
+    .io_in_15_ready        (_mmio_channel_D_arb_io_in_15_ready),
+    .io_in_15_valid        (_entries_15_io_resp_valid),
+    .io_in_15_bits_opcode  (_entries_15_io_resp_bits_opcode),
+    .io_in_15_bits_size    (_entries_15_io_resp_bits_size),
+    .io_in_15_bits_source  (_entries_15_io_resp_bits_source),
+    .io_in_15_bits_denied  (_entries_15_io_resp_bits_denied),
+    .io_in_15_bits_data    (_entries_15_io_resp_bits_data),
+    .io_in_15_bits_corrupt (_entries_15_io_resp_bits_corrupt),
+    .io_out_ready          (mmioNodeIn_d_ready),
+    .io_out_valid          (mmioNodeIn_d_valid),
+    .io_out_bits_opcode    (mmioNodeIn_d_bits_opcode),
+    .io_out_bits_size      (mmioNodeIn_d_bits_size),
+    .io_out_bits_source    (mmioNodeIn_d_bits_source),
+    .io_out_bits_denied    (mmioNodeIn_d_bits_denied),
+    .io_out_bits_data      (mmioNodeIn_d_bits_data),
+    .io_out_bits_corrupt   (mmioNodeIn_d_bits_corrupt)
+  );
+  assign auto_mmio_in_a_ready = mmioNodeIn_a_ready;
+  assign auto_mmio_in_d_valid = mmioNodeIn_d_valid;
+  assign auto_mmio_in_d_bits_opcode = mmioNodeIn_d_bits_opcode;
+  assign auto_mmio_in_d_bits_param = mmioNodeIn_d_bits_param;
+  assign auto_mmio_in_d_bits_size = mmioNodeIn_d_bits_size;
+  assign auto_mmio_in_d_bits_source = mmioNodeIn_d_bits_source;
+  assign auto_mmio_in_d_bits_sink = mmioNodeIn_d_bits_sink;
+  assign auto_mmio_in_d_bits_denied = mmioNodeIn_d_bits_denied;
+  assign auto_mmio_in_d_bits_data = mmioNodeIn_d_bits_data;
+  assign auto_mmio_in_d_bits_corrupt = mmioNodeIn_d_bits_corrupt;
+  assign io_tx_req_bits_srcID = 11'h0;
+  assign io_tx_req_bits_returnNID = 11'h0;
+  assign io_tx_req_bits_stashNIDValid = 1'h0;
+  assign io_tx_req_bits_returnTxnID = 12'h0;
+  assign io_tx_req_bits_ns = 1'h0;
+  assign io_tx_req_bits_lpIDWithPadding = 8'h0;
+  assign io_tx_req_bits_snoopMe = 1'h0;
+  assign io_tx_req_bits_tagOp = 2'h0;
+  assign io_tx_req_bits_traceTag = 1'h0;
+  assign io_tx_req_bits_mpam_perfMonGroup = 1'h0;
+  assign io_tx_req_bits_mpam_partID = 9'h0;
+  assign io_tx_req_bits_mpam_mpamNS = 1'h0;
+  assign io_tx_req_bits_rsvdc = 4'h0;
+  assign io_tx_dat_bits_qos = 4'h0;
+  assign io_tx_dat_bits_srcID = 11'h0;
+  assign io_tx_dat_bits_homeNID = 11'h0;
+  assign io_tx_dat_bits_opcode = 4'h3;
+  assign io_tx_dat_bits_resp = 3'h0;
+  assign io_tx_dat_bits_dataSource = 4'h0;
+  assign io_tx_dat_bits_cBusy = 3'h0;
+  assign io_tx_dat_bits_dbID = 12'h0;
+  assign io_tx_dat_bits_tagOp = 2'h0;
+  assign io_tx_dat_bits_tag = 8'h0;
+  assign io_tx_dat_bits_tu = 2'h0;
+  assign io_tx_dat_bits_rsvdc = 4'h0;
+  assign io_rx_rsp_ready = 1'h1;
+  assign io_rx_dat_ready =
+    |{_entries_0_io_chi_rx_dat_ready & _io_rx_dat_ready_T,
+      _entries_1_io_chi_rx_dat_ready & _io_rx_dat_ready_T_2,
+      _entries_2_io_chi_rx_dat_ready & _io_rx_dat_ready_T_4,
+      _entries_3_io_chi_rx_dat_ready & _io_rx_dat_ready_T_6,
+      _entries_4_io_chi_rx_dat_ready & _io_rx_dat_ready_T_8,
+      _entries_5_io_chi_rx_dat_ready & _io_rx_dat_ready_T_10,
+      _entries_6_io_chi_rx_dat_ready & _io_rx_dat_ready_T_12,
+      _entries_7_io_chi_rx_dat_ready & _io_rx_dat_ready_T_14,
+      _entries_8_io_chi_rx_dat_ready & _io_rx_dat_ready_T_16,
+      _entries_9_io_chi_rx_dat_ready & _io_rx_dat_ready_T_18,
+      _entries_10_io_chi_rx_dat_ready & _io_rx_dat_ready_T_20,
+      _entries_11_io_chi_rx_dat_ready & _io_rx_dat_ready_T_22,
+      _entries_12_io_chi_rx_dat_ready & _io_rx_dat_ready_T_24,
+      _entries_13_io_chi_rx_dat_ready & _io_rx_dat_ready_T_26,
+      _entries_14_io_chi_rx_dat_ready & _io_rx_dat_ready_T_28,
+      _entries_15_io_chi_rx_dat_ready & _io_rx_dat_ready_T_30};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry.sv b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry.sv
new file mode 100644
index 0000000000..30d22efe15
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry.sv
@@ -0,0 +1,436 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MMIOBridgeEntry(
+  input          clock,
+  input          reset,
+  output         io_req_ready,
+  input          io_req_valid,
+  input  [3:0]   io_req_bits_opcode,
+  input  [1:0]   io_req_bits_size,
+  input  [4:0]   io_req_bits_source,
+  input  [47:0]  io_req_bits_address,
+  input          io_req_bits_user_memBackType_MM,
+  input          io_req_bits_user_memPageType_NC,
+  input  [7:0]   io_req_bits_mask,
+  input  [63:0]  io_req_bits_data,
+  input          io_req_bits_corrupt,
+  input          io_resp_ready,
+  output         io_resp_valid,
+  output [3:0]   io_resp_bits_opcode,
+  output [1:0]   io_resp_bits_size,
+  output [4:0]   io_resp_bits_source,
+  output         io_resp_bits_denied,
+  output [63:0]  io_resp_bits_data,
+  output         io_resp_bits_corrupt,
+  input          io_chi_tx_req_ready,
+  output         io_chi_tx_req_valid,
+  output [11:0]  io_chi_tx_req_bits_txnID,
+  output [6:0]   io_chi_tx_req_bits_opcode,
+  output [2:0]   io_chi_tx_req_bits_size,
+  output [47:0]  io_chi_tx_req_bits_addr,
+  output         io_chi_tx_req_bits_allowRetry,
+  output [1:0]   io_chi_tx_req_bits_order,
+  output [3:0]   io_chi_tx_req_bits_pCrdType,
+  output         io_chi_tx_req_bits_memAttr_device,
+  output         io_chi_tx_req_bits_memAttr_ewa,
+  input          io_chi_tx_dat_ready,
+  output         io_chi_tx_dat_valid,
+  output [10:0]  io_chi_tx_dat_bits_tgtID,
+  output [11:0]  io_chi_tx_dat_bits_txnID,
+  output [1:0]   io_chi_tx_dat_bits_respErr,
+  output [1:0]   io_chi_tx_dat_bits_ccID,
+  output [1:0]   io_chi_tx_dat_bits_dataID,
+  output         io_chi_tx_dat_bits_traceTag,
+  output [31:0]  io_chi_tx_dat_bits_be,
+  output [255:0] io_chi_tx_dat_bits_data,
+  output [31:0]  io_chi_tx_dat_bits_dataCheck,
+  output [3:0]   io_chi_tx_dat_bits_poison,
+  input          io_chi_rx_rsp_valid,
+  input  [10:0]  io_chi_rx_rsp_bits_srcID,
+  input  [4:0]   io_chi_rx_rsp_bits_opcode,
+  input  [1:0]   io_chi_rx_rsp_bits_respErr,
+  input  [11:0]  io_chi_rx_rsp_bits_dbID,
+  input  [3:0]   io_chi_rx_rsp_bits_pCrdType,
+  input          io_chi_rx_rsp_bits_traceTag,
+  output         io_chi_rx_dat_ready,
+  input          io_chi_rx_dat_valid,
+  input  [1:0]   io_chi_rx_dat_bits_respErr,
+  input  [255:0] io_chi_rx_dat_bits_data,
+  input  [31:0]  io_chi_rx_dat_bits_dataCheck,
+  input  [3:0]   io_chi_rx_dat_bits_poison,
+  input          io_id,
+  output         io_pCrd_query_valid,
+  output [3:0]   io_pCrd_query_bits_pCrdType,
+  output [10:0]  io_pCrd_query_bits_srcID,
+  input          io_pCrd_grant,
+  output         io_waitOnReadReceipt,
+  output         io_isRead
+);
+
+  wire         io_chi_rx_dat_ready_0;
+  wire         _io_chi_rx_rsp_ready_T_4;
+  wire         io_req_ready_0;
+  reg          s_txreq;
+  reg          s_ncbwrdata;
+  reg          s_resp;
+  reg          w_comp;
+  reg          w_dbidresp;
+  reg          w_compdata;
+  reg          w_pcrdgrant;
+  reg          w_readreceipt;
+  wire         _io_resp_valid_T_1 = w_comp & w_dbidresp;
+  wire         _isRead_T_1 = io_req_ready_0 & io_req_valid;
+  reg  [1:0]   req_size;
+  reg  [4:0]   req_source;
+  reg  [47:0]  req_address;
+  reg          req_user_memBackType_MM;
+  reg          req_user_memPageType_NC;
+  reg  [7:0]   req_mask;
+  reg  [63:0]  req_data;
+  reg          req_corrupt;
+  reg  [255:0] rdata;
+  reg  [10:0]  srcID;
+  reg  [11:0]  dbID;
+  reg          allowRetry;
+  reg  [3:0]   pCrdType;
+  reg          denied;
+  reg          corrupt;
+  reg          traceTag;
+  reg          isRead;
+  wire         _GEN = io_chi_rx_dat_ready_0 & io_chi_rx_dat_valid;
+  wire         _GEN_0 = _io_chi_rx_rsp_ready_T_4 & s_txreq & io_chi_rx_rsp_valid;
+  wire         _GEN_1 = io_chi_rx_rsp_bits_opcode == 5'h5;
+  wire         _GEN_2 = _GEN_0 & (_GEN_1 | io_chi_rx_rsp_bits_opcode == 5'h4);
+  wire         _GEN_3 =
+    _GEN_1 | io_chi_rx_rsp_bits_opcode == 5'h6 | io_chi_rx_rsp_bits_opcode == 5'hE;
+  wire         _GEN_4 = _GEN_0 & _GEN_3;
+  wire         _GEN_5 = io_chi_rx_rsp_bits_opcode == 5'h3;
+  wire         _GEN_6 = _GEN_0 & _GEN_5;
+  assign io_req_ready_0 =
+    s_txreq & s_ncbwrdata & s_resp & _io_resp_valid_T_1 & w_compdata & w_pcrdgrant
+    & w_readreceipt;
+  wire         io_chi_tx_req_valid_0 = ~s_txreq & w_pcrdgrant;
+  wire         io_resp_valid_0 =
+    ~s_resp & (isRead ? w_compdata : _io_resp_valid_T_1 & s_ncbwrdata);
+  wire         _io_chi_tx_dat_bits_be_T_8 = req_address[4:3] == 2'h0;
+  wire         _io_chi_tx_dat_bits_be_T_9 = req_address[4:3] == 2'h1;
+  wire         _io_chi_tx_dat_bits_be_T_10 = req_address[4:3] == 2'h2;
+  wire         io_chi_tx_dat_valid_0 = ~s_ncbwrdata & w_dbidresp;
+  wire [31:0]  io_chi_tx_dat_bits_be_0 =
+    (_io_chi_tx_dat_bits_be_T_8 ? {24'h0, req_mask} : 32'h0)
+    | (_io_chi_tx_dat_bits_be_T_9 ? {16'h0, req_mask, 8'h0} : 32'h0)
+    | (_io_chi_tx_dat_bits_be_T_10 ? {8'h0, req_mask, 16'h0} : 32'h0)
+    | ((&(req_address[4:3])) ? {req_mask, 24'h0} : 32'h0);
+  wire [255:0] io_chi_tx_dat_bits_data_0 =
+    {4{req_data}}
+    & {{8{io_chi_tx_dat_bits_be_0[31]}},
+       {8{io_chi_tx_dat_bits_be_0[30]}},
+       {8{io_chi_tx_dat_bits_be_0[29]}},
+       {8{io_chi_tx_dat_bits_be_0[28]}},
+       {8{io_chi_tx_dat_bits_be_0[27]}},
+       {8{io_chi_tx_dat_bits_be_0[26]}},
+       {8{io_chi_tx_dat_bits_be_0[25]}},
+       {8{io_chi_tx_dat_bits_be_0[24]}},
+       {8{io_chi_tx_dat_bits_be_0[23]}},
+       {8{io_chi_tx_dat_bits_be_0[22]}},
+       {8{io_chi_tx_dat_bits_be_0[21]}},
+       {8{io_chi_tx_dat_bits_be_0[20]}},
+       {8{io_chi_tx_dat_bits_be_0[19]}},
+       {8{io_chi_tx_dat_bits_be_0[18]}},
+       {8{io_chi_tx_dat_bits_be_0[17]}},
+       {8{io_chi_tx_dat_bits_be_0[16]}},
+       {8{io_chi_tx_dat_bits_be_0[15]}},
+       {8{io_chi_tx_dat_bits_be_0[14]}},
+       {8{io_chi_tx_dat_bits_be_0[13]}},
+       {8{io_chi_tx_dat_bits_be_0[12]}},
+       {8{io_chi_tx_dat_bits_be_0[11]}},
+       {8{io_chi_tx_dat_bits_be_0[10]}},
+       {8{io_chi_tx_dat_bits_be_0[9]}},
+       {8{io_chi_tx_dat_bits_be_0[8]}},
+       {8{io_chi_tx_dat_bits_be_0[7]}},
+       {8{io_chi_tx_dat_bits_be_0[6]}},
+       {8{io_chi_tx_dat_bits_be_0[5]}},
+       {8{io_chi_tx_dat_bits_be_0[4]}},
+       {8{io_chi_tx_dat_bits_be_0[3]}},
+       {8{io_chi_tx_dat_bits_be_0[2]}},
+       {8{io_chi_tx_dat_bits_be_0[1]}},
+       {8{io_chi_tx_dat_bits_be_0[0]}}};
+  assign _io_chi_rx_rsp_ready_T_4 = ~w_comp | ~w_dbidresp | ~w_readreceipt;
+  assign io_chi_rx_dat_ready_0 = ~w_compdata & s_txreq;
+  wire         _isRead_T = io_req_bits_opcode == 4'h4;
+  wire         _GEN_7 = _isRead_T_1 & _isRead_T;
+  wire         _GEN_8 =
+    ~_isRead_T_1 | _isRead_T | ~(io_req_bits_opcode == 4'h0 | io_req_bits_opcode == 4'h1);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      s_txreq <= 1'h1;
+      s_ncbwrdata <= 1'h1;
+      s_resp <= 1'h1;
+      w_comp <= 1'h1;
+      w_dbidresp <= 1'h1;
+      w_compdata <= 1'h1;
+      w_pcrdgrant <= 1'h1;
+      w_readreceipt <= 1'h1;
+      allowRetry <= 1'h1;
+      isRead <= 1'h0;
+    end
+    else begin
+      s_txreq <=
+        ~_GEN_6 & (io_chi_tx_req_ready & io_chi_tx_req_valid_0 | ~_isRead_T_1 & s_txreq);
+      s_ncbwrdata <= io_chi_tx_dat_ready & io_chi_tx_dat_valid_0 | _GEN_8 & s_ncbwrdata;
+      s_resp <= io_resp_ready & io_resp_valid_0 | ~_isRead_T_1 & s_resp;
+      w_comp <= _GEN_2 | _GEN_8 & w_comp;
+      w_dbidresp <= _GEN_4 | _GEN_8 & w_dbidresp;
+      w_compdata <= _GEN | ~_GEN_7 & w_compdata;
+      w_pcrdgrant <= io_pCrd_grant | ~_GEN_6 & w_pcrdgrant;
+      w_readreceipt <=
+        _GEN_0 & io_chi_rx_rsp_bits_opcode == 5'h8 | ~_GEN_7 & w_readreceipt;
+      allowRetry <= ~_GEN_6 & (_isRead_T_1 | allowRetry);
+      if (_isRead_T_1)
+        isRead <= _isRead_T;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (_isRead_T_1) begin
+      req_size <= io_req_bits_size;
+      req_source <= io_req_bits_source;
+      req_address <= io_req_bits_address;
+      req_user_memBackType_MM <= io_req_bits_user_memBackType_MM;
+      req_user_memPageType_NC <= io_req_bits_user_memPageType_NC;
+      req_mask <= io_req_bits_mask;
+      req_data <= io_req_bits_data;
+      req_corrupt <= io_req_bits_corrupt;
+    end
+    if (_GEN)
+      rdata <= io_chi_rx_dat_bits_data;
+    if (_GEN_0 & (_GEN_5 | _GEN_3))
+      srcID <= io_chi_rx_rsp_bits_srcID;
+    if (_GEN_4)
+      dbID <= io_chi_rx_rsp_bits_dbID;
+    if (_GEN_6)
+      pCrdType <= io_chi_rx_rsp_bits_pCrdType;
+    denied <=
+      _GEN_2
+        ? denied | (&io_chi_rx_rsp_bits_respErr) | io_chi_rx_rsp_bits_respErr == 2'h2
+        : _GEN ? denied | (&io_chi_rx_dat_bits_respErr) : ~_isRead_T_1 & denied;
+    corrupt <=
+      _GEN
+        ? (|{corrupt | io_chi_rx_dat_bits_respErr == 2'h2 | (&io_chi_rx_dat_bits_respErr)
+               | io_chi_rx_dat_bits_dataCheck[0] ^ ~(^(io_chi_rx_dat_bits_data[7:0]))
+               | io_chi_rx_dat_bits_dataCheck[1] ^ ~(^(io_chi_rx_dat_bits_data[15:8]))
+               | io_chi_rx_dat_bits_dataCheck[2] ^ ~(^(io_chi_rx_dat_bits_data[23:16]))
+               | io_chi_rx_dat_bits_dataCheck[3] ^ ~(^(io_chi_rx_dat_bits_data[31:24]))
+               | io_chi_rx_dat_bits_dataCheck[4] ^ ~(^(io_chi_rx_dat_bits_data[39:32]))
+               | io_chi_rx_dat_bits_dataCheck[5] ^ ~(^(io_chi_rx_dat_bits_data[47:40]))
+               | io_chi_rx_dat_bits_dataCheck[6] ^ ~(^(io_chi_rx_dat_bits_data[55:48]))
+               | io_chi_rx_dat_bits_dataCheck[7] ^ ~(^(io_chi_rx_dat_bits_data[63:56]))
+               | io_chi_rx_dat_bits_dataCheck[8] ^ ~(^(io_chi_rx_dat_bits_data[71:64]))
+               | io_chi_rx_dat_bits_dataCheck[9] ^ ~(^(io_chi_rx_dat_bits_data[79:72]))
+               | io_chi_rx_dat_bits_dataCheck[10] ^ ~(^(io_chi_rx_dat_bits_data[87:80]))
+               | io_chi_rx_dat_bits_dataCheck[11] ^ ~(^(io_chi_rx_dat_bits_data[95:88]))
+               | io_chi_rx_dat_bits_dataCheck[12] ^ ~(^(io_chi_rx_dat_bits_data[103:96]))
+               | io_chi_rx_dat_bits_dataCheck[13] ^ ~(^(io_chi_rx_dat_bits_data[111:104]))
+               | io_chi_rx_dat_bits_dataCheck[14] ^ ~(^(io_chi_rx_dat_bits_data[119:112]))
+               | io_chi_rx_dat_bits_dataCheck[15] ^ ~(^(io_chi_rx_dat_bits_data[127:120]))
+               | io_chi_rx_dat_bits_dataCheck[16] ^ ~(^(io_chi_rx_dat_bits_data[135:128]))
+               | io_chi_rx_dat_bits_dataCheck[17] ^ ~(^(io_chi_rx_dat_bits_data[143:136]))
+               | io_chi_rx_dat_bits_dataCheck[18] ^ ~(^(io_chi_rx_dat_bits_data[151:144]))
+               | io_chi_rx_dat_bits_dataCheck[19] ^ ~(^(io_chi_rx_dat_bits_data[159:152]))
+               | io_chi_rx_dat_bits_dataCheck[20] ^ ~(^(io_chi_rx_dat_bits_data[167:160]))
+               | io_chi_rx_dat_bits_dataCheck[21] ^ ~(^(io_chi_rx_dat_bits_data[175:168]))
+               | io_chi_rx_dat_bits_dataCheck[22] ^ ~(^(io_chi_rx_dat_bits_data[183:176]))
+               | io_chi_rx_dat_bits_dataCheck[23] ^ ~(^(io_chi_rx_dat_bits_data[191:184]))
+               | io_chi_rx_dat_bits_dataCheck[24] ^ ~(^(io_chi_rx_dat_bits_data[199:192]))
+               | io_chi_rx_dat_bits_dataCheck[25] ^ ~(^(io_chi_rx_dat_bits_data[207:200]))
+               | io_chi_rx_dat_bits_dataCheck[26] ^ ~(^(io_chi_rx_dat_bits_data[215:208]))
+               | io_chi_rx_dat_bits_dataCheck[27] ^ ~(^(io_chi_rx_dat_bits_data[223:216]))
+               | io_chi_rx_dat_bits_dataCheck[28] ^ ~(^(io_chi_rx_dat_bits_data[231:224]))
+               | io_chi_rx_dat_bits_dataCheck[29] ^ ~(^(io_chi_rx_dat_bits_data[239:232]))
+               | io_chi_rx_dat_bits_dataCheck[30] ^ ~(^(io_chi_rx_dat_bits_data[247:240]))
+               | io_chi_rx_dat_bits_dataCheck[31]
+               ^ ~(^(io_chi_rx_dat_bits_data[255:248])),
+             io_chi_rx_dat_bits_poison})
+        : ~_isRead_T_1 & corrupt;
+    traceTag <= _GEN_4 ? io_chi_rx_rsp_bits_traceTag : ~_isRead_T_1 & traceTag;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:13];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hE; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        s_txreq = _RANDOM[4'h0][0];
+        s_ncbwrdata = _RANDOM[4'h0][1];
+        s_resp = _RANDOM[4'h0][2];
+        w_comp = _RANDOM[4'h0][3];
+        w_dbidresp = _RANDOM[4'h0][4];
+        w_compdata = _RANDOM[4'h0][5];
+        w_pcrdgrant = _RANDOM[4'h0][6];
+        w_readreceipt = _RANDOM[4'h0][7];
+        req_size = _RANDOM[4'h0][16:15];
+        req_source = _RANDOM[4'h0][21:17];
+        req_address = {_RANDOM[4'h0][31:22], _RANDOM[4'h1], _RANDOM[4'h2][5:0]};
+        req_user_memBackType_MM = _RANDOM[4'h2][6];
+        req_user_memPageType_NC = _RANDOM[4'h2][7];
+        req_mask = _RANDOM[4'h2][15:8];
+        req_data = {_RANDOM[4'h2][31:16], _RANDOM[4'h3], _RANDOM[4'h4][15:0]};
+        req_corrupt = _RANDOM[4'h4][16];
+        rdata =
+          {_RANDOM[4'h4][31:17],
+           _RANDOM[4'h5],
+           _RANDOM[4'h6],
+           _RANDOM[4'h7],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB],
+           _RANDOM[4'hC][16:0]};
+        srcID = _RANDOM[4'hC][27:17];
+        dbID = {_RANDOM[4'hC][31:28], _RANDOM[4'hD][7:0]};
+        allowRetry = _RANDOM[4'hD][8];
+        pCrdType = _RANDOM[4'hD][12:9];
+        denied = _RANDOM[4'hD][13];
+        corrupt = _RANDOM[4'hD][14];
+        traceTag = _RANDOM[4'hD][15];
+        isRead = _RANDOM[4'hD][16];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        s_txreq = 1'h1;
+        s_ncbwrdata = 1'h1;
+        s_resp = 1'h1;
+        w_comp = 1'h1;
+        w_dbidresp = 1'h1;
+        w_compdata = 1'h1;
+        w_pcrdgrant = 1'h1;
+        w_readreceipt = 1'h1;
+        allowRetry = 1'h1;
+        isRead = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_req_ready = io_req_ready_0;
+  assign io_resp_valid = io_resp_valid_0;
+  assign io_resp_bits_opcode = {3'h0, isRead};
+  assign io_resp_bits_size = req_size;
+  assign io_resp_bits_source = req_source;
+  assign io_resp_bits_denied = denied;
+  assign io_resp_bits_data =
+    (_io_chi_tx_dat_bits_be_T_8 ? rdata[63:0] : 64'h0)
+    | (_io_chi_tx_dat_bits_be_T_9 ? rdata[127:64] : 64'h0)
+    | (_io_chi_tx_dat_bits_be_T_10 ? rdata[191:128] : 64'h0)
+    | ((&(req_address[4:3])) ? rdata[255:192] : 64'h0);
+  assign io_resp_bits_corrupt = isRead & corrupt;
+  assign io_chi_tx_req_valid = io_chi_tx_req_valid_0;
+  assign io_chi_tx_req_bits_txnID = {11'h0, io_id};
+  assign io_chi_tx_req_bits_opcode = isRead ? 7'h4 : 7'h1C;
+  assign io_chi_tx_req_bits_size = {1'h0, req_size};
+  assign io_chi_tx_req_bits_addr = req_address;
+  assign io_chi_tx_req_bits_allowRetry = allowRetry;
+  assign io_chi_tx_req_bits_order = {1'h1, ~req_user_memBackType_MM};
+  assign io_chi_tx_req_bits_pCrdType = allowRetry ? 4'h0 : pCrdType;
+  assign io_chi_tx_req_bits_memAttr_device = ~req_user_memBackType_MM;
+  assign io_chi_tx_req_bits_memAttr_ewa =
+    req_user_memPageType_NC | req_user_memBackType_MM;
+  assign io_chi_tx_dat_valid = io_chi_tx_dat_valid_0;
+  assign io_chi_tx_dat_bits_tgtID = srcID;
+  assign io_chi_tx_dat_bits_txnID = dbID;
+  assign io_chi_tx_dat_bits_respErr = {req_corrupt, 1'h0};
+  assign io_chi_tx_dat_bits_ccID = req_address[5:4];
+  assign io_chi_tx_dat_bits_dataID = {req_address[5], 1'h0};
+  assign io_chi_tx_dat_bits_traceTag = traceTag;
+  assign io_chi_tx_dat_bits_be = io_chi_tx_dat_bits_be_0;
+  assign io_chi_tx_dat_bits_data = io_chi_tx_dat_bits_data_0;
+  assign io_chi_tx_dat_bits_dataCheck =
+    {~(^(io_chi_tx_dat_bits_data_0[255:248])),
+     ~(^(io_chi_tx_dat_bits_data_0[247:240])),
+     ~(^(io_chi_tx_dat_bits_data_0[239:232])),
+     ~(^(io_chi_tx_dat_bits_data_0[231:224])),
+     ~(^(io_chi_tx_dat_bits_data_0[223:216])),
+     ~(^(io_chi_tx_dat_bits_data_0[215:208])),
+     ~(^(io_chi_tx_dat_bits_data_0[207:200])),
+     ~(^(io_chi_tx_dat_bits_data_0[199:192])),
+     ~(^(io_chi_tx_dat_bits_data_0[191:184])),
+     ~(^(io_chi_tx_dat_bits_data_0[183:176])),
+     ~(^(io_chi_tx_dat_bits_data_0[175:168])),
+     ~(^(io_chi_tx_dat_bits_data_0[167:160])),
+     ~(^(io_chi_tx_dat_bits_data_0[159:152])),
+     ~(^(io_chi_tx_dat_bits_data_0[151:144])),
+     ~(^(io_chi_tx_dat_bits_data_0[143:136])),
+     ~(^(io_chi_tx_dat_bits_data_0[135:128])),
+     ~(^(io_chi_tx_dat_bits_data_0[127:120])),
+     ~(^(io_chi_tx_dat_bits_data_0[119:112])),
+     ~(^(io_chi_tx_dat_bits_data_0[111:104])),
+     ~(^(io_chi_tx_dat_bits_data_0[103:96])),
+     ~(^(io_chi_tx_dat_bits_data_0[95:88])),
+     ~(^(io_chi_tx_dat_bits_data_0[87:80])),
+     ~(^(io_chi_tx_dat_bits_data_0[79:72])),
+     ~(^(io_chi_tx_dat_bits_data_0[71:64])),
+     ~(^(io_chi_tx_dat_bits_data_0[63:56])),
+     ~(^(io_chi_tx_dat_bits_data_0[55:48])),
+     ~(^(io_chi_tx_dat_bits_data_0[47:40])),
+     ~(^(io_chi_tx_dat_bits_data_0[39:32])),
+     ~(^(io_chi_tx_dat_bits_data_0[31:24])),
+     ~(^(io_chi_tx_dat_bits_data_0[23:16])),
+     ~(^(io_chi_tx_dat_bits_data_0[15:8])),
+     ~(^(io_chi_tx_dat_bits_data_0[7:0]))};
+  assign io_chi_tx_dat_bits_poison = {4{req_corrupt}};
+  assign io_chi_rx_dat_ready = io_chi_rx_dat_ready_0;
+  assign io_pCrd_query_valid = ~w_pcrdgrant;
+  assign io_pCrd_query_bits_pCrdType = pCrdType;
+  assign io_pCrd_query_bits_srcID = srcID;
+  assign io_waitOnReadReceipt = ~w_readreceipt & s_txreq;
+  assign io_isRead = isRead;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_2.sv b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_2.sv
new file mode 100644
index 0000000000..ca6fa15f31
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_2.sv
@@ -0,0 +1,436 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MMIOBridgeEntry_2(
+  input          clock,
+  input          reset,
+  output         io_req_ready,
+  input          io_req_valid,
+  input  [3:0]   io_req_bits_opcode,
+  input  [1:0]   io_req_bits_size,
+  input  [4:0]   io_req_bits_source,
+  input  [47:0]  io_req_bits_address,
+  input          io_req_bits_user_memBackType_MM,
+  input          io_req_bits_user_memPageType_NC,
+  input  [7:0]   io_req_bits_mask,
+  input  [63:0]  io_req_bits_data,
+  input          io_req_bits_corrupt,
+  input          io_resp_ready,
+  output         io_resp_valid,
+  output [3:0]   io_resp_bits_opcode,
+  output [1:0]   io_resp_bits_size,
+  output [4:0]   io_resp_bits_source,
+  output         io_resp_bits_denied,
+  output [63:0]  io_resp_bits_data,
+  output         io_resp_bits_corrupt,
+  input          io_chi_tx_req_ready,
+  output         io_chi_tx_req_valid,
+  output [11:0]  io_chi_tx_req_bits_txnID,
+  output [6:0]   io_chi_tx_req_bits_opcode,
+  output [2:0]   io_chi_tx_req_bits_size,
+  output [47:0]  io_chi_tx_req_bits_addr,
+  output         io_chi_tx_req_bits_allowRetry,
+  output [1:0]   io_chi_tx_req_bits_order,
+  output [3:0]   io_chi_tx_req_bits_pCrdType,
+  output         io_chi_tx_req_bits_memAttr_device,
+  output         io_chi_tx_req_bits_memAttr_ewa,
+  input          io_chi_tx_dat_ready,
+  output         io_chi_tx_dat_valid,
+  output [10:0]  io_chi_tx_dat_bits_tgtID,
+  output [11:0]  io_chi_tx_dat_bits_txnID,
+  output [1:0]   io_chi_tx_dat_bits_respErr,
+  output [1:0]   io_chi_tx_dat_bits_ccID,
+  output [1:0]   io_chi_tx_dat_bits_dataID,
+  output         io_chi_tx_dat_bits_traceTag,
+  output [31:0]  io_chi_tx_dat_bits_be,
+  output [255:0] io_chi_tx_dat_bits_data,
+  output [31:0]  io_chi_tx_dat_bits_dataCheck,
+  output [3:0]   io_chi_tx_dat_bits_poison,
+  input          io_chi_rx_rsp_valid,
+  input  [10:0]  io_chi_rx_rsp_bits_srcID,
+  input  [4:0]   io_chi_rx_rsp_bits_opcode,
+  input  [1:0]   io_chi_rx_rsp_bits_respErr,
+  input  [11:0]  io_chi_rx_rsp_bits_dbID,
+  input  [3:0]   io_chi_rx_rsp_bits_pCrdType,
+  input          io_chi_rx_rsp_bits_traceTag,
+  output         io_chi_rx_dat_ready,
+  input          io_chi_rx_dat_valid,
+  input  [1:0]   io_chi_rx_dat_bits_respErr,
+  input  [255:0] io_chi_rx_dat_bits_data,
+  input  [31:0]  io_chi_rx_dat_bits_dataCheck,
+  input  [3:0]   io_chi_rx_dat_bits_poison,
+  input  [1:0]   io_id,
+  output         io_pCrd_query_valid,
+  output [3:0]   io_pCrd_query_bits_pCrdType,
+  output [10:0]  io_pCrd_query_bits_srcID,
+  input          io_pCrd_grant,
+  output         io_waitOnReadReceipt,
+  output         io_isRead
+);
+
+  wire         io_chi_rx_dat_ready_0;
+  wire         _io_chi_rx_rsp_ready_T_4;
+  wire         io_req_ready_0;
+  reg          s_txreq;
+  reg          s_ncbwrdata;
+  reg          s_resp;
+  reg          w_comp;
+  reg          w_dbidresp;
+  reg          w_compdata;
+  reg          w_pcrdgrant;
+  reg          w_readreceipt;
+  wire         _io_resp_valid_T_1 = w_comp & w_dbidresp;
+  wire         _isRead_T_1 = io_req_ready_0 & io_req_valid;
+  reg  [1:0]   req_size;
+  reg  [4:0]   req_source;
+  reg  [47:0]  req_address;
+  reg          req_user_memBackType_MM;
+  reg          req_user_memPageType_NC;
+  reg  [7:0]   req_mask;
+  reg  [63:0]  req_data;
+  reg          req_corrupt;
+  reg  [255:0] rdata;
+  reg  [10:0]  srcID;
+  reg  [11:0]  dbID;
+  reg          allowRetry;
+  reg  [3:0]   pCrdType;
+  reg          denied;
+  reg          corrupt;
+  reg          traceTag;
+  reg          isRead;
+  wire         _GEN = io_chi_rx_dat_ready_0 & io_chi_rx_dat_valid;
+  wire         _GEN_0 = _io_chi_rx_rsp_ready_T_4 & s_txreq & io_chi_rx_rsp_valid;
+  wire         _GEN_1 = io_chi_rx_rsp_bits_opcode == 5'h5;
+  wire         _GEN_2 = _GEN_0 & (_GEN_1 | io_chi_rx_rsp_bits_opcode == 5'h4);
+  wire         _GEN_3 =
+    _GEN_1 | io_chi_rx_rsp_bits_opcode == 5'h6 | io_chi_rx_rsp_bits_opcode == 5'hE;
+  wire         _GEN_4 = _GEN_0 & _GEN_3;
+  wire         _GEN_5 = io_chi_rx_rsp_bits_opcode == 5'h3;
+  wire         _GEN_6 = _GEN_0 & _GEN_5;
+  assign io_req_ready_0 =
+    s_txreq & s_ncbwrdata & s_resp & _io_resp_valid_T_1 & w_compdata & w_pcrdgrant
+    & w_readreceipt;
+  wire         io_chi_tx_req_valid_0 = ~s_txreq & w_pcrdgrant;
+  wire         io_resp_valid_0 =
+    ~s_resp & (isRead ? w_compdata : _io_resp_valid_T_1 & s_ncbwrdata);
+  wire         _io_chi_tx_dat_bits_be_T_8 = req_address[4:3] == 2'h0;
+  wire         _io_chi_tx_dat_bits_be_T_9 = req_address[4:3] == 2'h1;
+  wire         _io_chi_tx_dat_bits_be_T_10 = req_address[4:3] == 2'h2;
+  wire         io_chi_tx_dat_valid_0 = ~s_ncbwrdata & w_dbidresp;
+  wire [31:0]  io_chi_tx_dat_bits_be_0 =
+    (_io_chi_tx_dat_bits_be_T_8 ? {24'h0, req_mask} : 32'h0)
+    | (_io_chi_tx_dat_bits_be_T_9 ? {16'h0, req_mask, 8'h0} : 32'h0)
+    | (_io_chi_tx_dat_bits_be_T_10 ? {8'h0, req_mask, 16'h0} : 32'h0)
+    | ((&(req_address[4:3])) ? {req_mask, 24'h0} : 32'h0);
+  wire [255:0] io_chi_tx_dat_bits_data_0 =
+    {4{req_data}}
+    & {{8{io_chi_tx_dat_bits_be_0[31]}},
+       {8{io_chi_tx_dat_bits_be_0[30]}},
+       {8{io_chi_tx_dat_bits_be_0[29]}},
+       {8{io_chi_tx_dat_bits_be_0[28]}},
+       {8{io_chi_tx_dat_bits_be_0[27]}},
+       {8{io_chi_tx_dat_bits_be_0[26]}},
+       {8{io_chi_tx_dat_bits_be_0[25]}},
+       {8{io_chi_tx_dat_bits_be_0[24]}},
+       {8{io_chi_tx_dat_bits_be_0[23]}},
+       {8{io_chi_tx_dat_bits_be_0[22]}},
+       {8{io_chi_tx_dat_bits_be_0[21]}},
+       {8{io_chi_tx_dat_bits_be_0[20]}},
+       {8{io_chi_tx_dat_bits_be_0[19]}},
+       {8{io_chi_tx_dat_bits_be_0[18]}},
+       {8{io_chi_tx_dat_bits_be_0[17]}},
+       {8{io_chi_tx_dat_bits_be_0[16]}},
+       {8{io_chi_tx_dat_bits_be_0[15]}},
+       {8{io_chi_tx_dat_bits_be_0[14]}},
+       {8{io_chi_tx_dat_bits_be_0[13]}},
+       {8{io_chi_tx_dat_bits_be_0[12]}},
+       {8{io_chi_tx_dat_bits_be_0[11]}},
+       {8{io_chi_tx_dat_bits_be_0[10]}},
+       {8{io_chi_tx_dat_bits_be_0[9]}},
+       {8{io_chi_tx_dat_bits_be_0[8]}},
+       {8{io_chi_tx_dat_bits_be_0[7]}},
+       {8{io_chi_tx_dat_bits_be_0[6]}},
+       {8{io_chi_tx_dat_bits_be_0[5]}},
+       {8{io_chi_tx_dat_bits_be_0[4]}},
+       {8{io_chi_tx_dat_bits_be_0[3]}},
+       {8{io_chi_tx_dat_bits_be_0[2]}},
+       {8{io_chi_tx_dat_bits_be_0[1]}},
+       {8{io_chi_tx_dat_bits_be_0[0]}}};
+  assign _io_chi_rx_rsp_ready_T_4 = ~w_comp | ~w_dbidresp | ~w_readreceipt;
+  assign io_chi_rx_dat_ready_0 = ~w_compdata & s_txreq;
+  wire         _isRead_T = io_req_bits_opcode == 4'h4;
+  wire         _GEN_7 = _isRead_T_1 & _isRead_T;
+  wire         _GEN_8 =
+    ~_isRead_T_1 | _isRead_T | ~(io_req_bits_opcode == 4'h0 | io_req_bits_opcode == 4'h1);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      s_txreq <= 1'h1;
+      s_ncbwrdata <= 1'h1;
+      s_resp <= 1'h1;
+      w_comp <= 1'h1;
+      w_dbidresp <= 1'h1;
+      w_compdata <= 1'h1;
+      w_pcrdgrant <= 1'h1;
+      w_readreceipt <= 1'h1;
+      allowRetry <= 1'h1;
+      isRead <= 1'h0;
+    end
+    else begin
+      s_txreq <=
+        ~_GEN_6 & (io_chi_tx_req_ready & io_chi_tx_req_valid_0 | ~_isRead_T_1 & s_txreq);
+      s_ncbwrdata <= io_chi_tx_dat_ready & io_chi_tx_dat_valid_0 | _GEN_8 & s_ncbwrdata;
+      s_resp <= io_resp_ready & io_resp_valid_0 | ~_isRead_T_1 & s_resp;
+      w_comp <= _GEN_2 | _GEN_8 & w_comp;
+      w_dbidresp <= _GEN_4 | _GEN_8 & w_dbidresp;
+      w_compdata <= _GEN | ~_GEN_7 & w_compdata;
+      w_pcrdgrant <= io_pCrd_grant | ~_GEN_6 & w_pcrdgrant;
+      w_readreceipt <=
+        _GEN_0 & io_chi_rx_rsp_bits_opcode == 5'h8 | ~_GEN_7 & w_readreceipt;
+      allowRetry <= ~_GEN_6 & (_isRead_T_1 | allowRetry);
+      if (_isRead_T_1)
+        isRead <= _isRead_T;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (_isRead_T_1) begin
+      req_size <= io_req_bits_size;
+      req_source <= io_req_bits_source;
+      req_address <= io_req_bits_address;
+      req_user_memBackType_MM <= io_req_bits_user_memBackType_MM;
+      req_user_memPageType_NC <= io_req_bits_user_memPageType_NC;
+      req_mask <= io_req_bits_mask;
+      req_data <= io_req_bits_data;
+      req_corrupt <= io_req_bits_corrupt;
+    end
+    if (_GEN)
+      rdata <= io_chi_rx_dat_bits_data;
+    if (_GEN_0 & (_GEN_5 | _GEN_3))
+      srcID <= io_chi_rx_rsp_bits_srcID;
+    if (_GEN_4)
+      dbID <= io_chi_rx_rsp_bits_dbID;
+    if (_GEN_6)
+      pCrdType <= io_chi_rx_rsp_bits_pCrdType;
+    denied <=
+      _GEN_2
+        ? denied | (&io_chi_rx_rsp_bits_respErr) | io_chi_rx_rsp_bits_respErr == 2'h2
+        : _GEN ? denied | (&io_chi_rx_dat_bits_respErr) : ~_isRead_T_1 & denied;
+    corrupt <=
+      _GEN
+        ? (|{corrupt | io_chi_rx_dat_bits_respErr == 2'h2 | (&io_chi_rx_dat_bits_respErr)
+               | io_chi_rx_dat_bits_dataCheck[0] ^ ~(^(io_chi_rx_dat_bits_data[7:0]))
+               | io_chi_rx_dat_bits_dataCheck[1] ^ ~(^(io_chi_rx_dat_bits_data[15:8]))
+               | io_chi_rx_dat_bits_dataCheck[2] ^ ~(^(io_chi_rx_dat_bits_data[23:16]))
+               | io_chi_rx_dat_bits_dataCheck[3] ^ ~(^(io_chi_rx_dat_bits_data[31:24]))
+               | io_chi_rx_dat_bits_dataCheck[4] ^ ~(^(io_chi_rx_dat_bits_data[39:32]))
+               | io_chi_rx_dat_bits_dataCheck[5] ^ ~(^(io_chi_rx_dat_bits_data[47:40]))
+               | io_chi_rx_dat_bits_dataCheck[6] ^ ~(^(io_chi_rx_dat_bits_data[55:48]))
+               | io_chi_rx_dat_bits_dataCheck[7] ^ ~(^(io_chi_rx_dat_bits_data[63:56]))
+               | io_chi_rx_dat_bits_dataCheck[8] ^ ~(^(io_chi_rx_dat_bits_data[71:64]))
+               | io_chi_rx_dat_bits_dataCheck[9] ^ ~(^(io_chi_rx_dat_bits_data[79:72]))
+               | io_chi_rx_dat_bits_dataCheck[10] ^ ~(^(io_chi_rx_dat_bits_data[87:80]))
+               | io_chi_rx_dat_bits_dataCheck[11] ^ ~(^(io_chi_rx_dat_bits_data[95:88]))
+               | io_chi_rx_dat_bits_dataCheck[12] ^ ~(^(io_chi_rx_dat_bits_data[103:96]))
+               | io_chi_rx_dat_bits_dataCheck[13] ^ ~(^(io_chi_rx_dat_bits_data[111:104]))
+               | io_chi_rx_dat_bits_dataCheck[14] ^ ~(^(io_chi_rx_dat_bits_data[119:112]))
+               | io_chi_rx_dat_bits_dataCheck[15] ^ ~(^(io_chi_rx_dat_bits_data[127:120]))
+               | io_chi_rx_dat_bits_dataCheck[16] ^ ~(^(io_chi_rx_dat_bits_data[135:128]))
+               | io_chi_rx_dat_bits_dataCheck[17] ^ ~(^(io_chi_rx_dat_bits_data[143:136]))
+               | io_chi_rx_dat_bits_dataCheck[18] ^ ~(^(io_chi_rx_dat_bits_data[151:144]))
+               | io_chi_rx_dat_bits_dataCheck[19] ^ ~(^(io_chi_rx_dat_bits_data[159:152]))
+               | io_chi_rx_dat_bits_dataCheck[20] ^ ~(^(io_chi_rx_dat_bits_data[167:160]))
+               | io_chi_rx_dat_bits_dataCheck[21] ^ ~(^(io_chi_rx_dat_bits_data[175:168]))
+               | io_chi_rx_dat_bits_dataCheck[22] ^ ~(^(io_chi_rx_dat_bits_data[183:176]))
+               | io_chi_rx_dat_bits_dataCheck[23] ^ ~(^(io_chi_rx_dat_bits_data[191:184]))
+               | io_chi_rx_dat_bits_dataCheck[24] ^ ~(^(io_chi_rx_dat_bits_data[199:192]))
+               | io_chi_rx_dat_bits_dataCheck[25] ^ ~(^(io_chi_rx_dat_bits_data[207:200]))
+               | io_chi_rx_dat_bits_dataCheck[26] ^ ~(^(io_chi_rx_dat_bits_data[215:208]))
+               | io_chi_rx_dat_bits_dataCheck[27] ^ ~(^(io_chi_rx_dat_bits_data[223:216]))
+               | io_chi_rx_dat_bits_dataCheck[28] ^ ~(^(io_chi_rx_dat_bits_data[231:224]))
+               | io_chi_rx_dat_bits_dataCheck[29] ^ ~(^(io_chi_rx_dat_bits_data[239:232]))
+               | io_chi_rx_dat_bits_dataCheck[30] ^ ~(^(io_chi_rx_dat_bits_data[247:240]))
+               | io_chi_rx_dat_bits_dataCheck[31]
+               ^ ~(^(io_chi_rx_dat_bits_data[255:248])),
+             io_chi_rx_dat_bits_poison})
+        : ~_isRead_T_1 & corrupt;
+    traceTag <= _GEN_4 ? io_chi_rx_rsp_bits_traceTag : ~_isRead_T_1 & traceTag;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:13];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hE; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        s_txreq = _RANDOM[4'h0][0];
+        s_ncbwrdata = _RANDOM[4'h0][1];
+        s_resp = _RANDOM[4'h0][2];
+        w_comp = _RANDOM[4'h0][3];
+        w_dbidresp = _RANDOM[4'h0][4];
+        w_compdata = _RANDOM[4'h0][5];
+        w_pcrdgrant = _RANDOM[4'h0][6];
+        w_readreceipt = _RANDOM[4'h0][7];
+        req_size = _RANDOM[4'h0][16:15];
+        req_source = _RANDOM[4'h0][21:17];
+        req_address = {_RANDOM[4'h0][31:22], _RANDOM[4'h1], _RANDOM[4'h2][5:0]};
+        req_user_memBackType_MM = _RANDOM[4'h2][6];
+        req_user_memPageType_NC = _RANDOM[4'h2][7];
+        req_mask = _RANDOM[4'h2][15:8];
+        req_data = {_RANDOM[4'h2][31:16], _RANDOM[4'h3], _RANDOM[4'h4][15:0]};
+        req_corrupt = _RANDOM[4'h4][16];
+        rdata =
+          {_RANDOM[4'h4][31:17],
+           _RANDOM[4'h5],
+           _RANDOM[4'h6],
+           _RANDOM[4'h7],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB],
+           _RANDOM[4'hC][16:0]};
+        srcID = _RANDOM[4'hC][27:17];
+        dbID = {_RANDOM[4'hC][31:28], _RANDOM[4'hD][7:0]};
+        allowRetry = _RANDOM[4'hD][8];
+        pCrdType = _RANDOM[4'hD][12:9];
+        denied = _RANDOM[4'hD][13];
+        corrupt = _RANDOM[4'hD][14];
+        traceTag = _RANDOM[4'hD][15];
+        isRead = _RANDOM[4'hD][16];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        s_txreq = 1'h1;
+        s_ncbwrdata = 1'h1;
+        s_resp = 1'h1;
+        w_comp = 1'h1;
+        w_dbidresp = 1'h1;
+        w_compdata = 1'h1;
+        w_pcrdgrant = 1'h1;
+        w_readreceipt = 1'h1;
+        allowRetry = 1'h1;
+        isRead = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_req_ready = io_req_ready_0;
+  assign io_resp_valid = io_resp_valid_0;
+  assign io_resp_bits_opcode = {3'h0, isRead};
+  assign io_resp_bits_size = req_size;
+  assign io_resp_bits_source = req_source;
+  assign io_resp_bits_denied = denied;
+  assign io_resp_bits_data =
+    (_io_chi_tx_dat_bits_be_T_8 ? rdata[63:0] : 64'h0)
+    | (_io_chi_tx_dat_bits_be_T_9 ? rdata[127:64] : 64'h0)
+    | (_io_chi_tx_dat_bits_be_T_10 ? rdata[191:128] : 64'h0)
+    | ((&(req_address[4:3])) ? rdata[255:192] : 64'h0);
+  assign io_resp_bits_corrupt = isRead & corrupt;
+  assign io_chi_tx_req_valid = io_chi_tx_req_valid_0;
+  assign io_chi_tx_req_bits_txnID = {10'h0, io_id};
+  assign io_chi_tx_req_bits_opcode = isRead ? 7'h4 : 7'h1C;
+  assign io_chi_tx_req_bits_size = {1'h0, req_size};
+  assign io_chi_tx_req_bits_addr = req_address;
+  assign io_chi_tx_req_bits_allowRetry = allowRetry;
+  assign io_chi_tx_req_bits_order = {1'h1, ~req_user_memBackType_MM};
+  assign io_chi_tx_req_bits_pCrdType = allowRetry ? 4'h0 : pCrdType;
+  assign io_chi_tx_req_bits_memAttr_device = ~req_user_memBackType_MM;
+  assign io_chi_tx_req_bits_memAttr_ewa =
+    req_user_memPageType_NC | req_user_memBackType_MM;
+  assign io_chi_tx_dat_valid = io_chi_tx_dat_valid_0;
+  assign io_chi_tx_dat_bits_tgtID = srcID;
+  assign io_chi_tx_dat_bits_txnID = dbID;
+  assign io_chi_tx_dat_bits_respErr = {req_corrupt, 1'h0};
+  assign io_chi_tx_dat_bits_ccID = req_address[5:4];
+  assign io_chi_tx_dat_bits_dataID = {req_address[5], 1'h0};
+  assign io_chi_tx_dat_bits_traceTag = traceTag;
+  assign io_chi_tx_dat_bits_be = io_chi_tx_dat_bits_be_0;
+  assign io_chi_tx_dat_bits_data = io_chi_tx_dat_bits_data_0;
+  assign io_chi_tx_dat_bits_dataCheck =
+    {~(^(io_chi_tx_dat_bits_data_0[255:248])),
+     ~(^(io_chi_tx_dat_bits_data_0[247:240])),
+     ~(^(io_chi_tx_dat_bits_data_0[239:232])),
+     ~(^(io_chi_tx_dat_bits_data_0[231:224])),
+     ~(^(io_chi_tx_dat_bits_data_0[223:216])),
+     ~(^(io_chi_tx_dat_bits_data_0[215:208])),
+     ~(^(io_chi_tx_dat_bits_data_0[207:200])),
+     ~(^(io_chi_tx_dat_bits_data_0[199:192])),
+     ~(^(io_chi_tx_dat_bits_data_0[191:184])),
+     ~(^(io_chi_tx_dat_bits_data_0[183:176])),
+     ~(^(io_chi_tx_dat_bits_data_0[175:168])),
+     ~(^(io_chi_tx_dat_bits_data_0[167:160])),
+     ~(^(io_chi_tx_dat_bits_data_0[159:152])),
+     ~(^(io_chi_tx_dat_bits_data_0[151:144])),
+     ~(^(io_chi_tx_dat_bits_data_0[143:136])),
+     ~(^(io_chi_tx_dat_bits_data_0[135:128])),
+     ~(^(io_chi_tx_dat_bits_data_0[127:120])),
+     ~(^(io_chi_tx_dat_bits_data_0[119:112])),
+     ~(^(io_chi_tx_dat_bits_data_0[111:104])),
+     ~(^(io_chi_tx_dat_bits_data_0[103:96])),
+     ~(^(io_chi_tx_dat_bits_data_0[95:88])),
+     ~(^(io_chi_tx_dat_bits_data_0[87:80])),
+     ~(^(io_chi_tx_dat_bits_data_0[79:72])),
+     ~(^(io_chi_tx_dat_bits_data_0[71:64])),
+     ~(^(io_chi_tx_dat_bits_data_0[63:56])),
+     ~(^(io_chi_tx_dat_bits_data_0[55:48])),
+     ~(^(io_chi_tx_dat_bits_data_0[47:40])),
+     ~(^(io_chi_tx_dat_bits_data_0[39:32])),
+     ~(^(io_chi_tx_dat_bits_data_0[31:24])),
+     ~(^(io_chi_tx_dat_bits_data_0[23:16])),
+     ~(^(io_chi_tx_dat_bits_data_0[15:8])),
+     ~(^(io_chi_tx_dat_bits_data_0[7:0]))};
+  assign io_chi_tx_dat_bits_poison = {4{req_corrupt}};
+  assign io_chi_rx_dat_ready = io_chi_rx_dat_ready_0;
+  assign io_pCrd_query_valid = ~w_pcrdgrant;
+  assign io_pCrd_query_bits_pCrdType = pCrdType;
+  assign io_pCrd_query_bits_srcID = srcID;
+  assign io_waitOnReadReceipt = ~w_readreceipt & s_txreq;
+  assign io_isRead = isRead;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_4.sv b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_4.sv
new file mode 100644
index 0000000000..39d8591070
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_4.sv
@@ -0,0 +1,436 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MMIOBridgeEntry_4(
+  input          clock,
+  input          reset,
+  output         io_req_ready,
+  input          io_req_valid,
+  input  [3:0]   io_req_bits_opcode,
+  input  [1:0]   io_req_bits_size,
+  input  [4:0]   io_req_bits_source,
+  input  [47:0]  io_req_bits_address,
+  input          io_req_bits_user_memBackType_MM,
+  input          io_req_bits_user_memPageType_NC,
+  input  [7:0]   io_req_bits_mask,
+  input  [63:0]  io_req_bits_data,
+  input          io_req_bits_corrupt,
+  input          io_resp_ready,
+  output         io_resp_valid,
+  output [3:0]   io_resp_bits_opcode,
+  output [1:0]   io_resp_bits_size,
+  output [4:0]   io_resp_bits_source,
+  output         io_resp_bits_denied,
+  output [63:0]  io_resp_bits_data,
+  output         io_resp_bits_corrupt,
+  input          io_chi_tx_req_ready,
+  output         io_chi_tx_req_valid,
+  output [11:0]  io_chi_tx_req_bits_txnID,
+  output [6:0]   io_chi_tx_req_bits_opcode,
+  output [2:0]   io_chi_tx_req_bits_size,
+  output [47:0]  io_chi_tx_req_bits_addr,
+  output         io_chi_tx_req_bits_allowRetry,
+  output [1:0]   io_chi_tx_req_bits_order,
+  output [3:0]   io_chi_tx_req_bits_pCrdType,
+  output         io_chi_tx_req_bits_memAttr_device,
+  output         io_chi_tx_req_bits_memAttr_ewa,
+  input          io_chi_tx_dat_ready,
+  output         io_chi_tx_dat_valid,
+  output [10:0]  io_chi_tx_dat_bits_tgtID,
+  output [11:0]  io_chi_tx_dat_bits_txnID,
+  output [1:0]   io_chi_tx_dat_bits_respErr,
+  output [1:0]   io_chi_tx_dat_bits_ccID,
+  output [1:0]   io_chi_tx_dat_bits_dataID,
+  output         io_chi_tx_dat_bits_traceTag,
+  output [31:0]  io_chi_tx_dat_bits_be,
+  output [255:0] io_chi_tx_dat_bits_data,
+  output [31:0]  io_chi_tx_dat_bits_dataCheck,
+  output [3:0]   io_chi_tx_dat_bits_poison,
+  input          io_chi_rx_rsp_valid,
+  input  [10:0]  io_chi_rx_rsp_bits_srcID,
+  input  [4:0]   io_chi_rx_rsp_bits_opcode,
+  input  [1:0]   io_chi_rx_rsp_bits_respErr,
+  input  [11:0]  io_chi_rx_rsp_bits_dbID,
+  input  [3:0]   io_chi_rx_rsp_bits_pCrdType,
+  input          io_chi_rx_rsp_bits_traceTag,
+  output         io_chi_rx_dat_ready,
+  input          io_chi_rx_dat_valid,
+  input  [1:0]   io_chi_rx_dat_bits_respErr,
+  input  [255:0] io_chi_rx_dat_bits_data,
+  input  [31:0]  io_chi_rx_dat_bits_dataCheck,
+  input  [3:0]   io_chi_rx_dat_bits_poison,
+  input  [2:0]   io_id,
+  output         io_pCrd_query_valid,
+  output [3:0]   io_pCrd_query_bits_pCrdType,
+  output [10:0]  io_pCrd_query_bits_srcID,
+  input          io_pCrd_grant,
+  output         io_waitOnReadReceipt,
+  output         io_isRead
+);
+
+  wire         io_chi_rx_dat_ready_0;
+  wire         _io_chi_rx_rsp_ready_T_4;
+  wire         io_req_ready_0;
+  reg          s_txreq;
+  reg          s_ncbwrdata;
+  reg          s_resp;
+  reg          w_comp;
+  reg          w_dbidresp;
+  reg          w_compdata;
+  reg          w_pcrdgrant;
+  reg          w_readreceipt;
+  wire         _io_resp_valid_T_1 = w_comp & w_dbidresp;
+  wire         _isRead_T_1 = io_req_ready_0 & io_req_valid;
+  reg  [1:0]   req_size;
+  reg  [4:0]   req_source;
+  reg  [47:0]  req_address;
+  reg          req_user_memBackType_MM;
+  reg          req_user_memPageType_NC;
+  reg  [7:0]   req_mask;
+  reg  [63:0]  req_data;
+  reg          req_corrupt;
+  reg  [255:0] rdata;
+  reg  [10:0]  srcID;
+  reg  [11:0]  dbID;
+  reg          allowRetry;
+  reg  [3:0]   pCrdType;
+  reg          denied;
+  reg          corrupt;
+  reg          traceTag;
+  reg          isRead;
+  wire         _GEN = io_chi_rx_dat_ready_0 & io_chi_rx_dat_valid;
+  wire         _GEN_0 = _io_chi_rx_rsp_ready_T_4 & s_txreq & io_chi_rx_rsp_valid;
+  wire         _GEN_1 = io_chi_rx_rsp_bits_opcode == 5'h5;
+  wire         _GEN_2 = _GEN_0 & (_GEN_1 | io_chi_rx_rsp_bits_opcode == 5'h4);
+  wire         _GEN_3 =
+    _GEN_1 | io_chi_rx_rsp_bits_opcode == 5'h6 | io_chi_rx_rsp_bits_opcode == 5'hE;
+  wire         _GEN_4 = _GEN_0 & _GEN_3;
+  wire         _GEN_5 = io_chi_rx_rsp_bits_opcode == 5'h3;
+  wire         _GEN_6 = _GEN_0 & _GEN_5;
+  assign io_req_ready_0 =
+    s_txreq & s_ncbwrdata & s_resp & _io_resp_valid_T_1 & w_compdata & w_pcrdgrant
+    & w_readreceipt;
+  wire         io_chi_tx_req_valid_0 = ~s_txreq & w_pcrdgrant;
+  wire         io_resp_valid_0 =
+    ~s_resp & (isRead ? w_compdata : _io_resp_valid_T_1 & s_ncbwrdata);
+  wire         _io_chi_tx_dat_bits_be_T_8 = req_address[4:3] == 2'h0;
+  wire         _io_chi_tx_dat_bits_be_T_9 = req_address[4:3] == 2'h1;
+  wire         _io_chi_tx_dat_bits_be_T_10 = req_address[4:3] == 2'h2;
+  wire         io_chi_tx_dat_valid_0 = ~s_ncbwrdata & w_dbidresp;
+  wire [31:0]  io_chi_tx_dat_bits_be_0 =
+    (_io_chi_tx_dat_bits_be_T_8 ? {24'h0, req_mask} : 32'h0)
+    | (_io_chi_tx_dat_bits_be_T_9 ? {16'h0, req_mask, 8'h0} : 32'h0)
+    | (_io_chi_tx_dat_bits_be_T_10 ? {8'h0, req_mask, 16'h0} : 32'h0)
+    | ((&(req_address[4:3])) ? {req_mask, 24'h0} : 32'h0);
+  wire [255:0] io_chi_tx_dat_bits_data_0 =
+    {4{req_data}}
+    & {{8{io_chi_tx_dat_bits_be_0[31]}},
+       {8{io_chi_tx_dat_bits_be_0[30]}},
+       {8{io_chi_tx_dat_bits_be_0[29]}},
+       {8{io_chi_tx_dat_bits_be_0[28]}},
+       {8{io_chi_tx_dat_bits_be_0[27]}},
+       {8{io_chi_tx_dat_bits_be_0[26]}},
+       {8{io_chi_tx_dat_bits_be_0[25]}},
+       {8{io_chi_tx_dat_bits_be_0[24]}},
+       {8{io_chi_tx_dat_bits_be_0[23]}},
+       {8{io_chi_tx_dat_bits_be_0[22]}},
+       {8{io_chi_tx_dat_bits_be_0[21]}},
+       {8{io_chi_tx_dat_bits_be_0[20]}},
+       {8{io_chi_tx_dat_bits_be_0[19]}},
+       {8{io_chi_tx_dat_bits_be_0[18]}},
+       {8{io_chi_tx_dat_bits_be_0[17]}},
+       {8{io_chi_tx_dat_bits_be_0[16]}},
+       {8{io_chi_tx_dat_bits_be_0[15]}},
+       {8{io_chi_tx_dat_bits_be_0[14]}},
+       {8{io_chi_tx_dat_bits_be_0[13]}},
+       {8{io_chi_tx_dat_bits_be_0[12]}},
+       {8{io_chi_tx_dat_bits_be_0[11]}},
+       {8{io_chi_tx_dat_bits_be_0[10]}},
+       {8{io_chi_tx_dat_bits_be_0[9]}},
+       {8{io_chi_tx_dat_bits_be_0[8]}},
+       {8{io_chi_tx_dat_bits_be_0[7]}},
+       {8{io_chi_tx_dat_bits_be_0[6]}},
+       {8{io_chi_tx_dat_bits_be_0[5]}},
+       {8{io_chi_tx_dat_bits_be_0[4]}},
+       {8{io_chi_tx_dat_bits_be_0[3]}},
+       {8{io_chi_tx_dat_bits_be_0[2]}},
+       {8{io_chi_tx_dat_bits_be_0[1]}},
+       {8{io_chi_tx_dat_bits_be_0[0]}}};
+  assign _io_chi_rx_rsp_ready_T_4 = ~w_comp | ~w_dbidresp | ~w_readreceipt;
+  assign io_chi_rx_dat_ready_0 = ~w_compdata & s_txreq;
+  wire         _isRead_T = io_req_bits_opcode == 4'h4;
+  wire         _GEN_7 = _isRead_T_1 & _isRead_T;
+  wire         _GEN_8 =
+    ~_isRead_T_1 | _isRead_T | ~(io_req_bits_opcode == 4'h0 | io_req_bits_opcode == 4'h1);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      s_txreq <= 1'h1;
+      s_ncbwrdata <= 1'h1;
+      s_resp <= 1'h1;
+      w_comp <= 1'h1;
+      w_dbidresp <= 1'h1;
+      w_compdata <= 1'h1;
+      w_pcrdgrant <= 1'h1;
+      w_readreceipt <= 1'h1;
+      allowRetry <= 1'h1;
+      isRead <= 1'h0;
+    end
+    else begin
+      s_txreq <=
+        ~_GEN_6 & (io_chi_tx_req_ready & io_chi_tx_req_valid_0 | ~_isRead_T_1 & s_txreq);
+      s_ncbwrdata <= io_chi_tx_dat_ready & io_chi_tx_dat_valid_0 | _GEN_8 & s_ncbwrdata;
+      s_resp <= io_resp_ready & io_resp_valid_0 | ~_isRead_T_1 & s_resp;
+      w_comp <= _GEN_2 | _GEN_8 & w_comp;
+      w_dbidresp <= _GEN_4 | _GEN_8 & w_dbidresp;
+      w_compdata <= _GEN | ~_GEN_7 & w_compdata;
+      w_pcrdgrant <= io_pCrd_grant | ~_GEN_6 & w_pcrdgrant;
+      w_readreceipt <=
+        _GEN_0 & io_chi_rx_rsp_bits_opcode == 5'h8 | ~_GEN_7 & w_readreceipt;
+      allowRetry <= ~_GEN_6 & (_isRead_T_1 | allowRetry);
+      if (_isRead_T_1)
+        isRead <= _isRead_T;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (_isRead_T_1) begin
+      req_size <= io_req_bits_size;
+      req_source <= io_req_bits_source;
+      req_address <= io_req_bits_address;
+      req_user_memBackType_MM <= io_req_bits_user_memBackType_MM;
+      req_user_memPageType_NC <= io_req_bits_user_memPageType_NC;
+      req_mask <= io_req_bits_mask;
+      req_data <= io_req_bits_data;
+      req_corrupt <= io_req_bits_corrupt;
+    end
+    if (_GEN)
+      rdata <= io_chi_rx_dat_bits_data;
+    if (_GEN_0 & (_GEN_5 | _GEN_3))
+      srcID <= io_chi_rx_rsp_bits_srcID;
+    if (_GEN_4)
+      dbID <= io_chi_rx_rsp_bits_dbID;
+    if (_GEN_6)
+      pCrdType <= io_chi_rx_rsp_bits_pCrdType;
+    denied <=
+      _GEN_2
+        ? denied | (&io_chi_rx_rsp_bits_respErr) | io_chi_rx_rsp_bits_respErr == 2'h2
+        : _GEN ? denied | (&io_chi_rx_dat_bits_respErr) : ~_isRead_T_1 & denied;
+    corrupt <=
+      _GEN
+        ? (|{corrupt | io_chi_rx_dat_bits_respErr == 2'h2 | (&io_chi_rx_dat_bits_respErr)
+               | io_chi_rx_dat_bits_dataCheck[0] ^ ~(^(io_chi_rx_dat_bits_data[7:0]))
+               | io_chi_rx_dat_bits_dataCheck[1] ^ ~(^(io_chi_rx_dat_bits_data[15:8]))
+               | io_chi_rx_dat_bits_dataCheck[2] ^ ~(^(io_chi_rx_dat_bits_data[23:16]))
+               | io_chi_rx_dat_bits_dataCheck[3] ^ ~(^(io_chi_rx_dat_bits_data[31:24]))
+               | io_chi_rx_dat_bits_dataCheck[4] ^ ~(^(io_chi_rx_dat_bits_data[39:32]))
+               | io_chi_rx_dat_bits_dataCheck[5] ^ ~(^(io_chi_rx_dat_bits_data[47:40]))
+               | io_chi_rx_dat_bits_dataCheck[6] ^ ~(^(io_chi_rx_dat_bits_data[55:48]))
+               | io_chi_rx_dat_bits_dataCheck[7] ^ ~(^(io_chi_rx_dat_bits_data[63:56]))
+               | io_chi_rx_dat_bits_dataCheck[8] ^ ~(^(io_chi_rx_dat_bits_data[71:64]))
+               | io_chi_rx_dat_bits_dataCheck[9] ^ ~(^(io_chi_rx_dat_bits_data[79:72]))
+               | io_chi_rx_dat_bits_dataCheck[10] ^ ~(^(io_chi_rx_dat_bits_data[87:80]))
+               | io_chi_rx_dat_bits_dataCheck[11] ^ ~(^(io_chi_rx_dat_bits_data[95:88]))
+               | io_chi_rx_dat_bits_dataCheck[12] ^ ~(^(io_chi_rx_dat_bits_data[103:96]))
+               | io_chi_rx_dat_bits_dataCheck[13] ^ ~(^(io_chi_rx_dat_bits_data[111:104]))
+               | io_chi_rx_dat_bits_dataCheck[14] ^ ~(^(io_chi_rx_dat_bits_data[119:112]))
+               | io_chi_rx_dat_bits_dataCheck[15] ^ ~(^(io_chi_rx_dat_bits_data[127:120]))
+               | io_chi_rx_dat_bits_dataCheck[16] ^ ~(^(io_chi_rx_dat_bits_data[135:128]))
+               | io_chi_rx_dat_bits_dataCheck[17] ^ ~(^(io_chi_rx_dat_bits_data[143:136]))
+               | io_chi_rx_dat_bits_dataCheck[18] ^ ~(^(io_chi_rx_dat_bits_data[151:144]))
+               | io_chi_rx_dat_bits_dataCheck[19] ^ ~(^(io_chi_rx_dat_bits_data[159:152]))
+               | io_chi_rx_dat_bits_dataCheck[20] ^ ~(^(io_chi_rx_dat_bits_data[167:160]))
+               | io_chi_rx_dat_bits_dataCheck[21] ^ ~(^(io_chi_rx_dat_bits_data[175:168]))
+               | io_chi_rx_dat_bits_dataCheck[22] ^ ~(^(io_chi_rx_dat_bits_data[183:176]))
+               | io_chi_rx_dat_bits_dataCheck[23] ^ ~(^(io_chi_rx_dat_bits_data[191:184]))
+               | io_chi_rx_dat_bits_dataCheck[24] ^ ~(^(io_chi_rx_dat_bits_data[199:192]))
+               | io_chi_rx_dat_bits_dataCheck[25] ^ ~(^(io_chi_rx_dat_bits_data[207:200]))
+               | io_chi_rx_dat_bits_dataCheck[26] ^ ~(^(io_chi_rx_dat_bits_data[215:208]))
+               | io_chi_rx_dat_bits_dataCheck[27] ^ ~(^(io_chi_rx_dat_bits_data[223:216]))
+               | io_chi_rx_dat_bits_dataCheck[28] ^ ~(^(io_chi_rx_dat_bits_data[231:224]))
+               | io_chi_rx_dat_bits_dataCheck[29] ^ ~(^(io_chi_rx_dat_bits_data[239:232]))
+               | io_chi_rx_dat_bits_dataCheck[30] ^ ~(^(io_chi_rx_dat_bits_data[247:240]))
+               | io_chi_rx_dat_bits_dataCheck[31]
+               ^ ~(^(io_chi_rx_dat_bits_data[255:248])),
+             io_chi_rx_dat_bits_poison})
+        : ~_isRead_T_1 & corrupt;
+    traceTag <= _GEN_4 ? io_chi_rx_rsp_bits_traceTag : ~_isRead_T_1 & traceTag;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:13];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hE; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        s_txreq = _RANDOM[4'h0][0];
+        s_ncbwrdata = _RANDOM[4'h0][1];
+        s_resp = _RANDOM[4'h0][2];
+        w_comp = _RANDOM[4'h0][3];
+        w_dbidresp = _RANDOM[4'h0][4];
+        w_compdata = _RANDOM[4'h0][5];
+        w_pcrdgrant = _RANDOM[4'h0][6];
+        w_readreceipt = _RANDOM[4'h0][7];
+        req_size = _RANDOM[4'h0][16:15];
+        req_source = _RANDOM[4'h0][21:17];
+        req_address = {_RANDOM[4'h0][31:22], _RANDOM[4'h1], _RANDOM[4'h2][5:0]};
+        req_user_memBackType_MM = _RANDOM[4'h2][6];
+        req_user_memPageType_NC = _RANDOM[4'h2][7];
+        req_mask = _RANDOM[4'h2][15:8];
+        req_data = {_RANDOM[4'h2][31:16], _RANDOM[4'h3], _RANDOM[4'h4][15:0]};
+        req_corrupt = _RANDOM[4'h4][16];
+        rdata =
+          {_RANDOM[4'h4][31:17],
+           _RANDOM[4'h5],
+           _RANDOM[4'h6],
+           _RANDOM[4'h7],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB],
+           _RANDOM[4'hC][16:0]};
+        srcID = _RANDOM[4'hC][27:17];
+        dbID = {_RANDOM[4'hC][31:28], _RANDOM[4'hD][7:0]};
+        allowRetry = _RANDOM[4'hD][8];
+        pCrdType = _RANDOM[4'hD][12:9];
+        denied = _RANDOM[4'hD][13];
+        corrupt = _RANDOM[4'hD][14];
+        traceTag = _RANDOM[4'hD][15];
+        isRead = _RANDOM[4'hD][16];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        s_txreq = 1'h1;
+        s_ncbwrdata = 1'h1;
+        s_resp = 1'h1;
+        w_comp = 1'h1;
+        w_dbidresp = 1'h1;
+        w_compdata = 1'h1;
+        w_pcrdgrant = 1'h1;
+        w_readreceipt = 1'h1;
+        allowRetry = 1'h1;
+        isRead = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_req_ready = io_req_ready_0;
+  assign io_resp_valid = io_resp_valid_0;
+  assign io_resp_bits_opcode = {3'h0, isRead};
+  assign io_resp_bits_size = req_size;
+  assign io_resp_bits_source = req_source;
+  assign io_resp_bits_denied = denied;
+  assign io_resp_bits_data =
+    (_io_chi_tx_dat_bits_be_T_8 ? rdata[63:0] : 64'h0)
+    | (_io_chi_tx_dat_bits_be_T_9 ? rdata[127:64] : 64'h0)
+    | (_io_chi_tx_dat_bits_be_T_10 ? rdata[191:128] : 64'h0)
+    | ((&(req_address[4:3])) ? rdata[255:192] : 64'h0);
+  assign io_resp_bits_corrupt = isRead & corrupt;
+  assign io_chi_tx_req_valid = io_chi_tx_req_valid_0;
+  assign io_chi_tx_req_bits_txnID = {9'h0, io_id};
+  assign io_chi_tx_req_bits_opcode = isRead ? 7'h4 : 7'h1C;
+  assign io_chi_tx_req_bits_size = {1'h0, req_size};
+  assign io_chi_tx_req_bits_addr = req_address;
+  assign io_chi_tx_req_bits_allowRetry = allowRetry;
+  assign io_chi_tx_req_bits_order = {1'h1, ~req_user_memBackType_MM};
+  assign io_chi_tx_req_bits_pCrdType = allowRetry ? 4'h0 : pCrdType;
+  assign io_chi_tx_req_bits_memAttr_device = ~req_user_memBackType_MM;
+  assign io_chi_tx_req_bits_memAttr_ewa =
+    req_user_memPageType_NC | req_user_memBackType_MM;
+  assign io_chi_tx_dat_valid = io_chi_tx_dat_valid_0;
+  assign io_chi_tx_dat_bits_tgtID = srcID;
+  assign io_chi_tx_dat_bits_txnID = dbID;
+  assign io_chi_tx_dat_bits_respErr = {req_corrupt, 1'h0};
+  assign io_chi_tx_dat_bits_ccID = req_address[5:4];
+  assign io_chi_tx_dat_bits_dataID = {req_address[5], 1'h0};
+  assign io_chi_tx_dat_bits_traceTag = traceTag;
+  assign io_chi_tx_dat_bits_be = io_chi_tx_dat_bits_be_0;
+  assign io_chi_tx_dat_bits_data = io_chi_tx_dat_bits_data_0;
+  assign io_chi_tx_dat_bits_dataCheck =
+    {~(^(io_chi_tx_dat_bits_data_0[255:248])),
+     ~(^(io_chi_tx_dat_bits_data_0[247:240])),
+     ~(^(io_chi_tx_dat_bits_data_0[239:232])),
+     ~(^(io_chi_tx_dat_bits_data_0[231:224])),
+     ~(^(io_chi_tx_dat_bits_data_0[223:216])),
+     ~(^(io_chi_tx_dat_bits_data_0[215:208])),
+     ~(^(io_chi_tx_dat_bits_data_0[207:200])),
+     ~(^(io_chi_tx_dat_bits_data_0[199:192])),
+     ~(^(io_chi_tx_dat_bits_data_0[191:184])),
+     ~(^(io_chi_tx_dat_bits_data_0[183:176])),
+     ~(^(io_chi_tx_dat_bits_data_0[175:168])),
+     ~(^(io_chi_tx_dat_bits_data_0[167:160])),
+     ~(^(io_chi_tx_dat_bits_data_0[159:152])),
+     ~(^(io_chi_tx_dat_bits_data_0[151:144])),
+     ~(^(io_chi_tx_dat_bits_data_0[143:136])),
+     ~(^(io_chi_tx_dat_bits_data_0[135:128])),
+     ~(^(io_chi_tx_dat_bits_data_0[127:120])),
+     ~(^(io_chi_tx_dat_bits_data_0[119:112])),
+     ~(^(io_chi_tx_dat_bits_data_0[111:104])),
+     ~(^(io_chi_tx_dat_bits_data_0[103:96])),
+     ~(^(io_chi_tx_dat_bits_data_0[95:88])),
+     ~(^(io_chi_tx_dat_bits_data_0[87:80])),
+     ~(^(io_chi_tx_dat_bits_data_0[79:72])),
+     ~(^(io_chi_tx_dat_bits_data_0[71:64])),
+     ~(^(io_chi_tx_dat_bits_data_0[63:56])),
+     ~(^(io_chi_tx_dat_bits_data_0[55:48])),
+     ~(^(io_chi_tx_dat_bits_data_0[47:40])),
+     ~(^(io_chi_tx_dat_bits_data_0[39:32])),
+     ~(^(io_chi_tx_dat_bits_data_0[31:24])),
+     ~(^(io_chi_tx_dat_bits_data_0[23:16])),
+     ~(^(io_chi_tx_dat_bits_data_0[15:8])),
+     ~(^(io_chi_tx_dat_bits_data_0[7:0]))};
+  assign io_chi_tx_dat_bits_poison = {4{req_corrupt}};
+  assign io_chi_rx_dat_ready = io_chi_rx_dat_ready_0;
+  assign io_pCrd_query_valid = ~w_pcrdgrant;
+  assign io_pCrd_query_bits_pCrdType = pCrdType;
+  assign io_pCrd_query_bits_srcID = srcID;
+  assign io_waitOnReadReceipt = ~w_readreceipt & s_txreq;
+  assign io_isRead = isRead;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_8.sv b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_8.sv
new file mode 100644
index 0000000000..fb5e233cfb
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MMIOBridgeEntry_8.sv
@@ -0,0 +1,436 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MMIOBridgeEntry_8(
+  input          clock,
+  input          reset,
+  output         io_req_ready,
+  input          io_req_valid,
+  input  [3:0]   io_req_bits_opcode,
+  input  [1:0]   io_req_bits_size,
+  input  [4:0]   io_req_bits_source,
+  input  [47:0]  io_req_bits_address,
+  input          io_req_bits_user_memBackType_MM,
+  input          io_req_bits_user_memPageType_NC,
+  input  [7:0]   io_req_bits_mask,
+  input  [63:0]  io_req_bits_data,
+  input          io_req_bits_corrupt,
+  input          io_resp_ready,
+  output         io_resp_valid,
+  output [3:0]   io_resp_bits_opcode,
+  output [1:0]   io_resp_bits_size,
+  output [4:0]   io_resp_bits_source,
+  output         io_resp_bits_denied,
+  output [63:0]  io_resp_bits_data,
+  output         io_resp_bits_corrupt,
+  input          io_chi_tx_req_ready,
+  output         io_chi_tx_req_valid,
+  output [11:0]  io_chi_tx_req_bits_txnID,
+  output [6:0]   io_chi_tx_req_bits_opcode,
+  output [2:0]   io_chi_tx_req_bits_size,
+  output [47:0]  io_chi_tx_req_bits_addr,
+  output         io_chi_tx_req_bits_allowRetry,
+  output [1:0]   io_chi_tx_req_bits_order,
+  output [3:0]   io_chi_tx_req_bits_pCrdType,
+  output         io_chi_tx_req_bits_memAttr_device,
+  output         io_chi_tx_req_bits_memAttr_ewa,
+  input          io_chi_tx_dat_ready,
+  output         io_chi_tx_dat_valid,
+  output [10:0]  io_chi_tx_dat_bits_tgtID,
+  output [11:0]  io_chi_tx_dat_bits_txnID,
+  output [1:0]   io_chi_tx_dat_bits_respErr,
+  output [1:0]   io_chi_tx_dat_bits_ccID,
+  output [1:0]   io_chi_tx_dat_bits_dataID,
+  output         io_chi_tx_dat_bits_traceTag,
+  output [31:0]  io_chi_tx_dat_bits_be,
+  output [255:0] io_chi_tx_dat_bits_data,
+  output [31:0]  io_chi_tx_dat_bits_dataCheck,
+  output [3:0]   io_chi_tx_dat_bits_poison,
+  input          io_chi_rx_rsp_valid,
+  input  [10:0]  io_chi_rx_rsp_bits_srcID,
+  input  [4:0]   io_chi_rx_rsp_bits_opcode,
+  input  [1:0]   io_chi_rx_rsp_bits_respErr,
+  input  [11:0]  io_chi_rx_rsp_bits_dbID,
+  input  [3:0]   io_chi_rx_rsp_bits_pCrdType,
+  input          io_chi_rx_rsp_bits_traceTag,
+  output         io_chi_rx_dat_ready,
+  input          io_chi_rx_dat_valid,
+  input  [1:0]   io_chi_rx_dat_bits_respErr,
+  input  [255:0] io_chi_rx_dat_bits_data,
+  input  [31:0]  io_chi_rx_dat_bits_dataCheck,
+  input  [3:0]   io_chi_rx_dat_bits_poison,
+  input  [3:0]   io_id,
+  output         io_pCrd_query_valid,
+  output [3:0]   io_pCrd_query_bits_pCrdType,
+  output [10:0]  io_pCrd_query_bits_srcID,
+  input          io_pCrd_grant,
+  output         io_waitOnReadReceipt,
+  output         io_isRead
+);
+
+  wire         io_chi_rx_dat_ready_0;
+  wire         _io_chi_rx_rsp_ready_T_4;
+  wire         io_req_ready_0;
+  reg          s_txreq;
+  reg          s_ncbwrdata;
+  reg          s_resp;
+  reg          w_comp;
+  reg          w_dbidresp;
+  reg          w_compdata;
+  reg          w_pcrdgrant;
+  reg          w_readreceipt;
+  wire         _io_resp_valid_T_1 = w_comp & w_dbidresp;
+  wire         _isRead_T_1 = io_req_ready_0 & io_req_valid;
+  reg  [1:0]   req_size;
+  reg  [4:0]   req_source;
+  reg  [47:0]  req_address;
+  reg          req_user_memBackType_MM;
+  reg          req_user_memPageType_NC;
+  reg  [7:0]   req_mask;
+  reg  [63:0]  req_data;
+  reg          req_corrupt;
+  reg  [255:0] rdata;
+  reg  [10:0]  srcID;
+  reg  [11:0]  dbID;
+  reg          allowRetry;
+  reg  [3:0]   pCrdType;
+  reg          denied;
+  reg          corrupt;
+  reg          traceTag;
+  reg          isRead;
+  wire         _GEN = io_chi_rx_dat_ready_0 & io_chi_rx_dat_valid;
+  wire         _GEN_0 = _io_chi_rx_rsp_ready_T_4 & s_txreq & io_chi_rx_rsp_valid;
+  wire         _GEN_1 = io_chi_rx_rsp_bits_opcode == 5'h5;
+  wire         _GEN_2 = _GEN_0 & (_GEN_1 | io_chi_rx_rsp_bits_opcode == 5'h4);
+  wire         _GEN_3 =
+    _GEN_1 | io_chi_rx_rsp_bits_opcode == 5'h6 | io_chi_rx_rsp_bits_opcode == 5'hE;
+  wire         _GEN_4 = _GEN_0 & _GEN_3;
+  wire         _GEN_5 = io_chi_rx_rsp_bits_opcode == 5'h3;
+  wire         _GEN_6 = _GEN_0 & _GEN_5;
+  assign io_req_ready_0 =
+    s_txreq & s_ncbwrdata & s_resp & _io_resp_valid_T_1 & w_compdata & w_pcrdgrant
+    & w_readreceipt;
+  wire         io_chi_tx_req_valid_0 = ~s_txreq & w_pcrdgrant;
+  wire         io_resp_valid_0 =
+    ~s_resp & (isRead ? w_compdata : _io_resp_valid_T_1 & s_ncbwrdata);
+  wire         _io_chi_tx_dat_bits_be_T_8 = req_address[4:3] == 2'h0;
+  wire         _io_chi_tx_dat_bits_be_T_9 = req_address[4:3] == 2'h1;
+  wire         _io_chi_tx_dat_bits_be_T_10 = req_address[4:3] == 2'h2;
+  wire         io_chi_tx_dat_valid_0 = ~s_ncbwrdata & w_dbidresp;
+  wire [31:0]  io_chi_tx_dat_bits_be_0 =
+    (_io_chi_tx_dat_bits_be_T_8 ? {24'h0, req_mask} : 32'h0)
+    | (_io_chi_tx_dat_bits_be_T_9 ? {16'h0, req_mask, 8'h0} : 32'h0)
+    | (_io_chi_tx_dat_bits_be_T_10 ? {8'h0, req_mask, 16'h0} : 32'h0)
+    | ((&(req_address[4:3])) ? {req_mask, 24'h0} : 32'h0);
+  wire [255:0] io_chi_tx_dat_bits_data_0 =
+    {4{req_data}}
+    & {{8{io_chi_tx_dat_bits_be_0[31]}},
+       {8{io_chi_tx_dat_bits_be_0[30]}},
+       {8{io_chi_tx_dat_bits_be_0[29]}},
+       {8{io_chi_tx_dat_bits_be_0[28]}},
+       {8{io_chi_tx_dat_bits_be_0[27]}},
+       {8{io_chi_tx_dat_bits_be_0[26]}},
+       {8{io_chi_tx_dat_bits_be_0[25]}},
+       {8{io_chi_tx_dat_bits_be_0[24]}},
+       {8{io_chi_tx_dat_bits_be_0[23]}},
+       {8{io_chi_tx_dat_bits_be_0[22]}},
+       {8{io_chi_tx_dat_bits_be_0[21]}},
+       {8{io_chi_tx_dat_bits_be_0[20]}},
+       {8{io_chi_tx_dat_bits_be_0[19]}},
+       {8{io_chi_tx_dat_bits_be_0[18]}},
+       {8{io_chi_tx_dat_bits_be_0[17]}},
+       {8{io_chi_tx_dat_bits_be_0[16]}},
+       {8{io_chi_tx_dat_bits_be_0[15]}},
+       {8{io_chi_tx_dat_bits_be_0[14]}},
+       {8{io_chi_tx_dat_bits_be_0[13]}},
+       {8{io_chi_tx_dat_bits_be_0[12]}},
+       {8{io_chi_tx_dat_bits_be_0[11]}},
+       {8{io_chi_tx_dat_bits_be_0[10]}},
+       {8{io_chi_tx_dat_bits_be_0[9]}},
+       {8{io_chi_tx_dat_bits_be_0[8]}},
+       {8{io_chi_tx_dat_bits_be_0[7]}},
+       {8{io_chi_tx_dat_bits_be_0[6]}},
+       {8{io_chi_tx_dat_bits_be_0[5]}},
+       {8{io_chi_tx_dat_bits_be_0[4]}},
+       {8{io_chi_tx_dat_bits_be_0[3]}},
+       {8{io_chi_tx_dat_bits_be_0[2]}},
+       {8{io_chi_tx_dat_bits_be_0[1]}},
+       {8{io_chi_tx_dat_bits_be_0[0]}}};
+  assign _io_chi_rx_rsp_ready_T_4 = ~w_comp | ~w_dbidresp | ~w_readreceipt;
+  assign io_chi_rx_dat_ready_0 = ~w_compdata & s_txreq;
+  wire         _isRead_T = io_req_bits_opcode == 4'h4;
+  wire         _GEN_7 = _isRead_T_1 & _isRead_T;
+  wire         _GEN_8 =
+    ~_isRead_T_1 | _isRead_T | ~(io_req_bits_opcode == 4'h0 | io_req_bits_opcode == 4'h1);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      s_txreq <= 1'h1;
+      s_ncbwrdata <= 1'h1;
+      s_resp <= 1'h1;
+      w_comp <= 1'h1;
+      w_dbidresp <= 1'h1;
+      w_compdata <= 1'h1;
+      w_pcrdgrant <= 1'h1;
+      w_readreceipt <= 1'h1;
+      allowRetry <= 1'h1;
+      isRead <= 1'h0;
+    end
+    else begin
+      s_txreq <=
+        ~_GEN_6 & (io_chi_tx_req_ready & io_chi_tx_req_valid_0 | ~_isRead_T_1 & s_txreq);
+      s_ncbwrdata <= io_chi_tx_dat_ready & io_chi_tx_dat_valid_0 | _GEN_8 & s_ncbwrdata;
+      s_resp <= io_resp_ready & io_resp_valid_0 | ~_isRead_T_1 & s_resp;
+      w_comp <= _GEN_2 | _GEN_8 & w_comp;
+      w_dbidresp <= _GEN_4 | _GEN_8 & w_dbidresp;
+      w_compdata <= _GEN | ~_GEN_7 & w_compdata;
+      w_pcrdgrant <= io_pCrd_grant | ~_GEN_6 & w_pcrdgrant;
+      w_readreceipt <=
+        _GEN_0 & io_chi_rx_rsp_bits_opcode == 5'h8 | ~_GEN_7 & w_readreceipt;
+      allowRetry <= ~_GEN_6 & (_isRead_T_1 | allowRetry);
+      if (_isRead_T_1)
+        isRead <= _isRead_T;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (_isRead_T_1) begin
+      req_size <= io_req_bits_size;
+      req_source <= io_req_bits_source;
+      req_address <= io_req_bits_address;
+      req_user_memBackType_MM <= io_req_bits_user_memBackType_MM;
+      req_user_memPageType_NC <= io_req_bits_user_memPageType_NC;
+      req_mask <= io_req_bits_mask;
+      req_data <= io_req_bits_data;
+      req_corrupt <= io_req_bits_corrupt;
+    end
+    if (_GEN)
+      rdata <= io_chi_rx_dat_bits_data;
+    if (_GEN_0 & (_GEN_5 | _GEN_3))
+      srcID <= io_chi_rx_rsp_bits_srcID;
+    if (_GEN_4)
+      dbID <= io_chi_rx_rsp_bits_dbID;
+    if (_GEN_6)
+      pCrdType <= io_chi_rx_rsp_bits_pCrdType;
+    denied <=
+      _GEN_2
+        ? denied | (&io_chi_rx_rsp_bits_respErr) | io_chi_rx_rsp_bits_respErr == 2'h2
+        : _GEN ? denied | (&io_chi_rx_dat_bits_respErr) : ~_isRead_T_1 & denied;
+    corrupt <=
+      _GEN
+        ? (|{corrupt | io_chi_rx_dat_bits_respErr == 2'h2 | (&io_chi_rx_dat_bits_respErr)
+               | io_chi_rx_dat_bits_dataCheck[0] ^ ~(^(io_chi_rx_dat_bits_data[7:0]))
+               | io_chi_rx_dat_bits_dataCheck[1] ^ ~(^(io_chi_rx_dat_bits_data[15:8]))
+               | io_chi_rx_dat_bits_dataCheck[2] ^ ~(^(io_chi_rx_dat_bits_data[23:16]))
+               | io_chi_rx_dat_bits_dataCheck[3] ^ ~(^(io_chi_rx_dat_bits_data[31:24]))
+               | io_chi_rx_dat_bits_dataCheck[4] ^ ~(^(io_chi_rx_dat_bits_data[39:32]))
+               | io_chi_rx_dat_bits_dataCheck[5] ^ ~(^(io_chi_rx_dat_bits_data[47:40]))
+               | io_chi_rx_dat_bits_dataCheck[6] ^ ~(^(io_chi_rx_dat_bits_data[55:48]))
+               | io_chi_rx_dat_bits_dataCheck[7] ^ ~(^(io_chi_rx_dat_bits_data[63:56]))
+               | io_chi_rx_dat_bits_dataCheck[8] ^ ~(^(io_chi_rx_dat_bits_data[71:64]))
+               | io_chi_rx_dat_bits_dataCheck[9] ^ ~(^(io_chi_rx_dat_bits_data[79:72]))
+               | io_chi_rx_dat_bits_dataCheck[10] ^ ~(^(io_chi_rx_dat_bits_data[87:80]))
+               | io_chi_rx_dat_bits_dataCheck[11] ^ ~(^(io_chi_rx_dat_bits_data[95:88]))
+               | io_chi_rx_dat_bits_dataCheck[12] ^ ~(^(io_chi_rx_dat_bits_data[103:96]))
+               | io_chi_rx_dat_bits_dataCheck[13] ^ ~(^(io_chi_rx_dat_bits_data[111:104]))
+               | io_chi_rx_dat_bits_dataCheck[14] ^ ~(^(io_chi_rx_dat_bits_data[119:112]))
+               | io_chi_rx_dat_bits_dataCheck[15] ^ ~(^(io_chi_rx_dat_bits_data[127:120]))
+               | io_chi_rx_dat_bits_dataCheck[16] ^ ~(^(io_chi_rx_dat_bits_data[135:128]))
+               | io_chi_rx_dat_bits_dataCheck[17] ^ ~(^(io_chi_rx_dat_bits_data[143:136]))
+               | io_chi_rx_dat_bits_dataCheck[18] ^ ~(^(io_chi_rx_dat_bits_data[151:144]))
+               | io_chi_rx_dat_bits_dataCheck[19] ^ ~(^(io_chi_rx_dat_bits_data[159:152]))
+               | io_chi_rx_dat_bits_dataCheck[20] ^ ~(^(io_chi_rx_dat_bits_data[167:160]))
+               | io_chi_rx_dat_bits_dataCheck[21] ^ ~(^(io_chi_rx_dat_bits_data[175:168]))
+               | io_chi_rx_dat_bits_dataCheck[22] ^ ~(^(io_chi_rx_dat_bits_data[183:176]))
+               | io_chi_rx_dat_bits_dataCheck[23] ^ ~(^(io_chi_rx_dat_bits_data[191:184]))
+               | io_chi_rx_dat_bits_dataCheck[24] ^ ~(^(io_chi_rx_dat_bits_data[199:192]))
+               | io_chi_rx_dat_bits_dataCheck[25] ^ ~(^(io_chi_rx_dat_bits_data[207:200]))
+               | io_chi_rx_dat_bits_dataCheck[26] ^ ~(^(io_chi_rx_dat_bits_data[215:208]))
+               | io_chi_rx_dat_bits_dataCheck[27] ^ ~(^(io_chi_rx_dat_bits_data[223:216]))
+               | io_chi_rx_dat_bits_dataCheck[28] ^ ~(^(io_chi_rx_dat_bits_data[231:224]))
+               | io_chi_rx_dat_bits_dataCheck[29] ^ ~(^(io_chi_rx_dat_bits_data[239:232]))
+               | io_chi_rx_dat_bits_dataCheck[30] ^ ~(^(io_chi_rx_dat_bits_data[247:240]))
+               | io_chi_rx_dat_bits_dataCheck[31]
+               ^ ~(^(io_chi_rx_dat_bits_data[255:248])),
+             io_chi_rx_dat_bits_poison})
+        : ~_isRead_T_1 & corrupt;
+    traceTag <= _GEN_4 ? io_chi_rx_rsp_bits_traceTag : ~_isRead_T_1 & traceTag;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:13];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hE; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        s_txreq = _RANDOM[4'h0][0];
+        s_ncbwrdata = _RANDOM[4'h0][1];
+        s_resp = _RANDOM[4'h0][2];
+        w_comp = _RANDOM[4'h0][3];
+        w_dbidresp = _RANDOM[4'h0][4];
+        w_compdata = _RANDOM[4'h0][5];
+        w_pcrdgrant = _RANDOM[4'h0][6];
+        w_readreceipt = _RANDOM[4'h0][7];
+        req_size = _RANDOM[4'h0][16:15];
+        req_source = _RANDOM[4'h0][21:17];
+        req_address = {_RANDOM[4'h0][31:22], _RANDOM[4'h1], _RANDOM[4'h2][5:0]};
+        req_user_memBackType_MM = _RANDOM[4'h2][6];
+        req_user_memPageType_NC = _RANDOM[4'h2][7];
+        req_mask = _RANDOM[4'h2][15:8];
+        req_data = {_RANDOM[4'h2][31:16], _RANDOM[4'h3], _RANDOM[4'h4][15:0]};
+        req_corrupt = _RANDOM[4'h4][16];
+        rdata =
+          {_RANDOM[4'h4][31:17],
+           _RANDOM[4'h5],
+           _RANDOM[4'h6],
+           _RANDOM[4'h7],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB],
+           _RANDOM[4'hC][16:0]};
+        srcID = _RANDOM[4'hC][27:17];
+        dbID = {_RANDOM[4'hC][31:28], _RANDOM[4'hD][7:0]};
+        allowRetry = _RANDOM[4'hD][8];
+        pCrdType = _RANDOM[4'hD][12:9];
+        denied = _RANDOM[4'hD][13];
+        corrupt = _RANDOM[4'hD][14];
+        traceTag = _RANDOM[4'hD][15];
+        isRead = _RANDOM[4'hD][16];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        s_txreq = 1'h1;
+        s_ncbwrdata = 1'h1;
+        s_resp = 1'h1;
+        w_comp = 1'h1;
+        w_dbidresp = 1'h1;
+        w_compdata = 1'h1;
+        w_pcrdgrant = 1'h1;
+        w_readreceipt = 1'h1;
+        allowRetry = 1'h1;
+        isRead = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_req_ready = io_req_ready_0;
+  assign io_resp_valid = io_resp_valid_0;
+  assign io_resp_bits_opcode = {3'h0, isRead};
+  assign io_resp_bits_size = req_size;
+  assign io_resp_bits_source = req_source;
+  assign io_resp_bits_denied = denied;
+  assign io_resp_bits_data =
+    (_io_chi_tx_dat_bits_be_T_8 ? rdata[63:0] : 64'h0)
+    | (_io_chi_tx_dat_bits_be_T_9 ? rdata[127:64] : 64'h0)
+    | (_io_chi_tx_dat_bits_be_T_10 ? rdata[191:128] : 64'h0)
+    | ((&(req_address[4:3])) ? rdata[255:192] : 64'h0);
+  assign io_resp_bits_corrupt = isRead & corrupt;
+  assign io_chi_tx_req_valid = io_chi_tx_req_valid_0;
+  assign io_chi_tx_req_bits_txnID = {8'h0, io_id};
+  assign io_chi_tx_req_bits_opcode = isRead ? 7'h4 : 7'h1C;
+  assign io_chi_tx_req_bits_size = {1'h0, req_size};
+  assign io_chi_tx_req_bits_addr = req_address;
+  assign io_chi_tx_req_bits_allowRetry = allowRetry;
+  assign io_chi_tx_req_bits_order = {1'h1, ~req_user_memBackType_MM};
+  assign io_chi_tx_req_bits_pCrdType = allowRetry ? 4'h0 : pCrdType;
+  assign io_chi_tx_req_bits_memAttr_device = ~req_user_memBackType_MM;
+  assign io_chi_tx_req_bits_memAttr_ewa =
+    req_user_memPageType_NC | req_user_memBackType_MM;
+  assign io_chi_tx_dat_valid = io_chi_tx_dat_valid_0;
+  assign io_chi_tx_dat_bits_tgtID = srcID;
+  assign io_chi_tx_dat_bits_txnID = dbID;
+  assign io_chi_tx_dat_bits_respErr = {req_corrupt, 1'h0};
+  assign io_chi_tx_dat_bits_ccID = req_address[5:4];
+  assign io_chi_tx_dat_bits_dataID = {req_address[5], 1'h0};
+  assign io_chi_tx_dat_bits_traceTag = traceTag;
+  assign io_chi_tx_dat_bits_be = io_chi_tx_dat_bits_be_0;
+  assign io_chi_tx_dat_bits_data = io_chi_tx_dat_bits_data_0;
+  assign io_chi_tx_dat_bits_dataCheck =
+    {~(^(io_chi_tx_dat_bits_data_0[255:248])),
+     ~(^(io_chi_tx_dat_bits_data_0[247:240])),
+     ~(^(io_chi_tx_dat_bits_data_0[239:232])),
+     ~(^(io_chi_tx_dat_bits_data_0[231:224])),
+     ~(^(io_chi_tx_dat_bits_data_0[223:216])),
+     ~(^(io_chi_tx_dat_bits_data_0[215:208])),
+     ~(^(io_chi_tx_dat_bits_data_0[207:200])),
+     ~(^(io_chi_tx_dat_bits_data_0[199:192])),
+     ~(^(io_chi_tx_dat_bits_data_0[191:184])),
+     ~(^(io_chi_tx_dat_bits_data_0[183:176])),
+     ~(^(io_chi_tx_dat_bits_data_0[175:168])),
+     ~(^(io_chi_tx_dat_bits_data_0[167:160])),
+     ~(^(io_chi_tx_dat_bits_data_0[159:152])),
+     ~(^(io_chi_tx_dat_bits_data_0[151:144])),
+     ~(^(io_chi_tx_dat_bits_data_0[143:136])),
+     ~(^(io_chi_tx_dat_bits_data_0[135:128])),
+     ~(^(io_chi_tx_dat_bits_data_0[127:120])),
+     ~(^(io_chi_tx_dat_bits_data_0[119:112])),
+     ~(^(io_chi_tx_dat_bits_data_0[111:104])),
+     ~(^(io_chi_tx_dat_bits_data_0[103:96])),
+     ~(^(io_chi_tx_dat_bits_data_0[95:88])),
+     ~(^(io_chi_tx_dat_bits_data_0[87:80])),
+     ~(^(io_chi_tx_dat_bits_data_0[79:72])),
+     ~(^(io_chi_tx_dat_bits_data_0[71:64])),
+     ~(^(io_chi_tx_dat_bits_data_0[63:56])),
+     ~(^(io_chi_tx_dat_bits_data_0[55:48])),
+     ~(^(io_chi_tx_dat_bits_data_0[47:40])),
+     ~(^(io_chi_tx_dat_bits_data_0[39:32])),
+     ~(^(io_chi_tx_dat_bits_data_0[31:24])),
+     ~(^(io_chi_tx_dat_bits_data_0[23:16])),
+     ~(^(io_chi_tx_dat_bits_data_0[15:8])),
+     ~(^(io_chi_tx_dat_bits_data_0[7:0]))};
+  assign io_chi_tx_dat_bits_poison = {4{req_corrupt}};
+  assign io_chi_rx_dat_ready = io_chi_rx_dat_ready_0;
+  assign io_pCrd_query_valid = ~w_pcrdgrant;
+  assign io_pCrd_query_bits_pCrdType = pCrdType;
+  assign io_pCrd_query_bits_srcID = srcID;
+  assign io_waitOnReadReceipt = ~w_readreceipt & s_txreq;
+  assign io_isRead = isRead;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MSHR.sv b/flow/designs/src/xiangshan_coupledl2/deps/MSHR.sv
new file mode 100644
index 0000000000..8b1ff5715d
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MSHR.sv
@@ -0,0 +1,1781 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MSHR(
+  input         clock,
+  input         reset,
+  input  [7:0]  io_id,
+  output        io_status_valid,
+  output [2:0]  io_status_bits_channel,
+  output [7:0]  io_status_bits_set,
+  output [33:0] io_status_bits_reqTag,
+  output [33:0] io_status_bits_metaTag,
+  output        io_status_bits_needsRepl,
+  output        io_status_bits_w_c_resp,
+  output        io_status_bits_will_free,
+  output [4:0]  io_status_bits_reqSource,
+  output        io_msInfo_valid,
+  output [2:0]  io_msInfo_bits_channel,
+  output [7:0]  io_msInfo_bits_set,
+  output [2:0]  io_msInfo_bits_way,
+  output [33:0] io_msInfo_bits_reqTag,
+  output [4:0]  io_msInfo_bits_reqSource,
+  output        io_msInfo_bits_willFree,
+  output        io_msInfo_bits_aliasTask,
+  output        io_msInfo_bits_needRelease,
+  output        io_msInfo_bits_blockRefill,
+  output        io_msInfo_bits_meta_dirty,
+  output [1:0]  io_msInfo_bits_meta_state,
+  output        io_msInfo_bits_meta_clients,
+  output        io_msInfo_bits_meta_alias,
+  output        io_msInfo_bits_meta_prefetch,
+  output [3:0]  io_msInfo_bits_meta_prefetchSrc,
+  output        io_msInfo_bits_meta_accessed,
+  output        io_msInfo_bits_meta_tagErr,
+  output        io_msInfo_bits_meta_dataErr,
+  output [33:0] io_msInfo_bits_metaTag,
+  output        io_msInfo_bits_dirHit,
+  output        io_msInfo_bits_isAcqOrPrefetch,
+  output        io_msInfo_bits_isPrefetch,
+  output [2:0]  io_msInfo_bits_param,
+  output        io_msInfo_bits_mergeA,
+  output        io_msInfo_bits_w_grantfirst,
+  output        io_msInfo_bits_w_grantlast,
+  output        io_msInfo_bits_w_grant,
+  output        io_msInfo_bits_s_release,
+  output        io_msInfo_bits_s_refill,
+  output        io_msInfo_bits_s_cmoresp,
+  output        io_msInfo_bits_s_cmometaw,
+  output        io_msInfo_bits_w_releaseack,
+  output        io_msInfo_bits_w_replResp,
+  output        io_msInfo_bits_w_rprobeacklast,
+  output        io_msInfo_bits_replaceData,
+  output        io_msInfo_bits_releaseToClean,
+  input         io_alloc_valid,
+  input         io_alloc_bits_dirResult_hit,
+  input  [33:0] io_alloc_bits_dirResult_tag,
+  input  [7:0]  io_alloc_bits_dirResult_set,
+  input  [2:0]  io_alloc_bits_dirResult_way,
+  input         io_alloc_bits_dirResult_meta_dirty,
+  input  [1:0]  io_alloc_bits_dirResult_meta_state,
+  input         io_alloc_bits_dirResult_meta_clients,
+  input         io_alloc_bits_dirResult_meta_alias,
+  input         io_alloc_bits_dirResult_meta_prefetch,
+  input  [3:0]  io_alloc_bits_dirResult_meta_prefetchSrc,
+  input         io_alloc_bits_dirResult_meta_accessed,
+  input         io_alloc_bits_dirResult_meta_tagErr,
+  input         io_alloc_bits_dirResult_meta_dataErr,
+  input         io_alloc_bits_dirResult_error,
+  input         io_alloc_bits_state_s_acquire,
+  input         io_alloc_bits_state_s_rprobe,
+  input         io_alloc_bits_state_s_pprobe,
+  input         io_alloc_bits_state_s_release,
+  input         io_alloc_bits_state_s_probeack,
+  input         io_alloc_bits_state_s_refill,
+  input         io_alloc_bits_state_s_cmoresp,
+  input         io_alloc_bits_state_w_rprobeackfirst,
+  input         io_alloc_bits_state_w_rprobeacklast,
+  input         io_alloc_bits_state_w_pprobeackfirst,
+  input         io_alloc_bits_state_w_pprobeacklast,
+  input         io_alloc_bits_state_w_grantfirst,
+  input         io_alloc_bits_state_w_grantlast,
+  input         io_alloc_bits_state_w_grant,
+  input         io_alloc_bits_state_w_releaseack,
+  input         io_alloc_bits_state_w_replResp,
+  input         io_alloc_bits_state_s_rcompack,
+  input         io_alloc_bits_state_s_dct,
+  input  [2:0]  io_alloc_bits_task_channel,
+  input  [7:0]  io_alloc_bits_task_set,
+  input  [33:0] io_alloc_bits_task_tag,
+  input  [5:0]  io_alloc_bits_task_off,
+  input         io_alloc_bits_task_alias,
+  input         io_alloc_bits_task_isKeyword,
+  input  [3:0]  io_alloc_bits_task_opcode,
+  input  [2:0]  io_alloc_bits_task_param,
+  input  [6:0]  io_alloc_bits_task_sourceId,
+  input         io_alloc_bits_task_aliasTask,
+  input         io_alloc_bits_task_fromL2pft,
+  input  [4:0]  io_alloc_bits_task_reqSource,
+  input         io_alloc_bits_task_snpHitRelease,
+  input         io_alloc_bits_task_snpHitReleaseToInval,
+  input         io_alloc_bits_task_snpHitReleaseToClean,
+  input         io_alloc_bits_task_snpHitReleaseWithData,
+  input  [7:0]  io_alloc_bits_task_snpHitReleaseIdx,
+  input         io_alloc_bits_task_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_alloc_bits_task_snpHitReleaseMeta_state,
+  input         io_alloc_bits_task_snpHitReleaseMeta_clients,
+  input         io_alloc_bits_task_snpHitReleaseMeta_alias,
+  input         io_alloc_bits_task_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc,
+  input         io_alloc_bits_task_snpHitReleaseMeta_accessed,
+  input         io_alloc_bits_task_snpHitReleaseMeta_tagErr,
+  input         io_alloc_bits_task_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_alloc_bits_task_srcID,
+  input  [11:0] io_alloc_bits_task_txnID,
+  input  [10:0] io_alloc_bits_task_fwdNID,
+  input  [11:0] io_alloc_bits_task_fwdTxnID,
+  input  [6:0]  io_alloc_bits_task_chiOpcode,
+  input         io_alloc_bits_task_retToSrc,
+  input         io_alloc_bits_task_traceTag,
+  input         io_tasks_txreq_ready,
+  output        io_tasks_txreq_valid,
+  output [10:0] io_tasks_txreq_bits_tgtID,
+  output [11:0] io_tasks_txreq_bits_txnID,
+  output [6:0]  io_tasks_txreq_bits_opcode,
+  output [47:0] io_tasks_txreq_bits_addr,
+  output        io_tasks_txreq_bits_likelyshared,
+  output        io_tasks_txreq_bits_allowRetry,
+  output [3:0]  io_tasks_txreq_bits_pCrdType,
+  output        io_tasks_txreq_bits_memAttr_allocate,
+  output        io_tasks_txreq_bits_expCompAck,
+  input         io_tasks_txrsp_ready,
+  output        io_tasks_txrsp_valid,
+  output [10:0] io_tasks_txrsp_bits_tgtID,
+  output [11:0] io_tasks_txrsp_bits_txnID,
+  output        io_tasks_txrsp_bits_traceTag,
+  input         io_tasks_source_b_ready,
+  output        io_tasks_source_b_valid,
+  output [33:0] io_tasks_source_b_bits_tag,
+  output [7:0]  io_tasks_source_b_bits_set,
+  output [1:0]  io_tasks_source_b_bits_param,
+  output        io_tasks_source_b_bits_alias,
+  input         io_tasks_mainpipe_ready,
+  output        io_tasks_mainpipe_valid,
+  output [2:0]  io_tasks_mainpipe_bits_channel,
+  output [2:0]  io_tasks_mainpipe_bits_txChannel,
+  output [7:0]  io_tasks_mainpipe_bits_set,
+  output [33:0] io_tasks_mainpipe_bits_tag,
+  output [5:0]  io_tasks_mainpipe_bits_off,
+  output        io_tasks_mainpipe_bits_alias,
+  output        io_tasks_mainpipe_bits_isKeyword,
+  output [3:0]  io_tasks_mainpipe_bits_opcode,
+  output [2:0]  io_tasks_mainpipe_bits_param,
+  output [2:0]  io_tasks_mainpipe_bits_size,
+  output [6:0]  io_tasks_mainpipe_bits_sourceId,
+  output        io_tasks_mainpipe_bits_denied,
+  output        io_tasks_mainpipe_bits_corrupt,
+  output        io_tasks_mainpipe_bits_aliasTask,
+  output        io_tasks_mainpipe_bits_useProbeData,
+  output        io_tasks_mainpipe_bits_mshrRetry,
+  output        io_tasks_mainpipe_bits_readProbeDataDown,
+  output        io_tasks_mainpipe_bits_fromL2pft,
+  output        io_tasks_mainpipe_bits_dirty,
+  output [2:0]  io_tasks_mainpipe_bits_way,
+  output        io_tasks_mainpipe_bits_meta_dirty,
+  output [1:0]  io_tasks_mainpipe_bits_meta_state,
+  output        io_tasks_mainpipe_bits_meta_clients,
+  output        io_tasks_mainpipe_bits_meta_alias,
+  output        io_tasks_mainpipe_bits_meta_prefetch,
+  output [3:0]  io_tasks_mainpipe_bits_meta_prefetchSrc,
+  output        io_tasks_mainpipe_bits_meta_accessed,
+  output        io_tasks_mainpipe_bits_meta_tagErr,
+  output        io_tasks_mainpipe_bits_meta_dataErr,
+  output        io_tasks_mainpipe_bits_metaWen,
+  output        io_tasks_mainpipe_bits_tagWen,
+  output        io_tasks_mainpipe_bits_dsWen,
+  output        io_tasks_mainpipe_bits_replTask,
+  output        io_tasks_mainpipe_bits_cmoTask,
+  output [4:0]  io_tasks_mainpipe_bits_reqSource,
+  output        io_tasks_mainpipe_bits_mergeA,
+  output [5:0]  io_tasks_mainpipe_bits_aMergeTask_off,
+  output        io_tasks_mainpipe_bits_aMergeTask_alias,
+  output [43:0] io_tasks_mainpipe_bits_aMergeTask_vaddr,
+  output        io_tasks_mainpipe_bits_aMergeTask_isKeyword,
+  output [2:0]  io_tasks_mainpipe_bits_aMergeTask_opcode,
+  output [2:0]  io_tasks_mainpipe_bits_aMergeTask_param,
+  output [6:0]  io_tasks_mainpipe_bits_aMergeTask_sourceId,
+  output        io_tasks_mainpipe_bits_aMergeTask_meta_dirty,
+  output [1:0]  io_tasks_mainpipe_bits_aMergeTask_meta_state,
+  output        io_tasks_mainpipe_bits_aMergeTask_meta_clients,
+  output        io_tasks_mainpipe_bits_aMergeTask_meta_alias,
+  output        io_tasks_mainpipe_bits_aMergeTask_meta_accessed,
+  output        io_tasks_mainpipe_bits_snpHitRelease,
+  output        io_tasks_mainpipe_bits_snpHitReleaseToInval,
+  output        io_tasks_mainpipe_bits_snpHitReleaseToClean,
+  output        io_tasks_mainpipe_bits_snpHitReleaseWithData,
+  output [7:0]  io_tasks_mainpipe_bits_snpHitReleaseIdx,
+  output        io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_tasks_mainpipe_bits_snpHitReleaseMeta_state,
+  output        io_tasks_mainpipe_bits_snpHitReleaseMeta_clients,
+  output        io_tasks_mainpipe_bits_snpHitReleaseMeta_alias,
+  output        io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed,
+  output        io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr,
+  output        io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_tasks_mainpipe_bits_tgtID,
+  output [11:0] io_tasks_mainpipe_bits_txnID,
+  output [10:0] io_tasks_mainpipe_bits_homeNID,
+  output [11:0] io_tasks_mainpipe_bits_dbID,
+  output [6:0]  io_tasks_mainpipe_bits_chiOpcode,
+  output [2:0]  io_tasks_mainpipe_bits_resp,
+  output [2:0]  io_tasks_mainpipe_bits_fwdState,
+  output        io_tasks_mainpipe_bits_retToSrc,
+  output        io_tasks_mainpipe_bits_likelyshared,
+  output        io_tasks_mainpipe_bits_expCompAck,
+  output        io_tasks_mainpipe_bits_allowRetry,
+  output        io_tasks_mainpipe_bits_memAttr_allocate,
+  output        io_tasks_mainpipe_bits_memAttr_cacheable,
+  output        io_tasks_mainpipe_bits_memAttr_ewa,
+  output        io_tasks_mainpipe_bits_traceTag,
+  input         io_resps_sinkC_valid,
+  input  [2:0]  io_resps_sinkC_bits_opcode,
+  input  [2:0]  io_resps_sinkC_bits_param,
+  input         io_resps_sinkC_bits_last,
+  input         io_resps_sinkC_bits_denied,
+  input         io_resps_sinkC_bits_corrupt,
+  input         io_resps_rxrsp_valid,
+  input  [6:0]  io_resps_rxrsp_bits_chiOpcode,
+  input  [10:0] io_resps_rxrsp_bits_srcID,
+  input  [11:0] io_resps_rxrsp_bits_dbID,
+  input  [2:0]  io_resps_rxrsp_bits_resp,
+  input  [3:0]  io_resps_rxrsp_bits_pCrdType,
+  input  [1:0]  io_resps_rxrsp_bits_respErr,
+  input         io_resps_rxrsp_bits_traceTag,
+  input         io_resps_rxdat_valid,
+  input         io_resps_rxdat_bits_corrupt,
+  input  [6:0]  io_resps_rxdat_bits_chiOpcode,
+  input  [10:0] io_resps_rxdat_bits_homeNID,
+  input  [11:0] io_resps_rxdat_bits_dbID,
+  input  [2:0]  io_resps_rxdat_bits_resp,
+  input  [1:0]  io_resps_rxdat_bits_respErr,
+  input         io_resps_rxdat_bits_traceTag,
+  input  [7:0]  io_nestedwb_set,
+  input  [33:0] io_nestedwb_tag,
+  input         io_nestedwb_c_set_dirty,
+  input         io_nestedwb_c_set_tip,
+  input         io_nestedwb_b_inv_dirty,
+  input         io_nestedwb_b_toB,
+  input         io_nestedwb_b_toN,
+  input         io_nestedwb_b_toClean,
+  output        io_nestedwbData,
+  input         io_aMergeTask_valid,
+  input  [5:0]  io_aMergeTask_bits_off,
+  input         io_aMergeTask_bits_alias,
+  input  [43:0] io_aMergeTask_bits_vaddr,
+  input         io_aMergeTask_bits_isKeyword,
+  input  [3:0]  io_aMergeTask_bits_opcode,
+  input  [2:0]  io_aMergeTask_bits_param,
+  input  [6:0]  io_aMergeTask_bits_sourceId,
+  input         io_replResp_valid,
+  input  [33:0] io_replResp_bits_tag,
+  input  [2:0]  io_replResp_bits_way,
+  input         io_replResp_bits_meta_dirty,
+  input  [1:0]  io_replResp_bits_meta_state,
+  input         io_replResp_bits_meta_clients,
+  input         io_replResp_bits_meta_alias,
+  input         io_replResp_bits_meta_prefetch,
+  input  [3:0]  io_replResp_bits_meta_prefetchSrc,
+  input         io_replResp_bits_meta_accessed,
+  input         io_replResp_bits_meta_tagErr,
+  input         io_replResp_bits_meta_dataErr,
+  input         io_replResp_bits_retry,
+  output        io_pCrd_query_valid,
+  output [3:0]  io_pCrd_query_bits_pCrdType,
+  output [10:0] io_pCrd_query_bits_srcID,
+  input         io_pCrd_grant
+);
+
+  wire             mp_probeack_dsWen;
+  wire [15:0][3:0] _GEN =
+    '{4'h0,
+      4'h8,
+      4'h8,
+      4'h8,
+      4'h0,
+      4'h0,
+      4'h0,
+      4'h0,
+      4'h4,
+      4'h5,
+      4'h2,
+      4'h1,
+      4'h1,
+      4'h1,
+      4'h0,
+      4'h0};
+  reg              gotT;
+  reg              gotDirty;
+  reg              gotGrantData;
+  reg              probeDirty;
+  reg              releaseDirty;
+  reg              beatCnt;
+  reg              req_valid;
+  reg  [2:0]       req_channel;
+  reg  [7:0]       req_set;
+  reg  [33:0]      req_tag;
+  reg  [5:0]       req_off;
+  reg              req_alias;
+  reg              req_isKeyword;
+  reg  [3:0]       req_opcode;
+  reg  [2:0]       req_param;
+  reg  [6:0]       req_sourceId;
+  reg              req_aliasTask;
+  reg              req_fromL2pft;
+  reg  [4:0]       req_reqSource;
+  reg              req_snpHitRelease;
+  reg              req_snpHitReleaseToInval;
+  reg              req_snpHitReleaseToClean;
+  reg              req_snpHitReleaseWithData;
+  reg  [7:0]       req_snpHitReleaseIdx;
+  reg              req_snpHitReleaseMeta_dirty;
+  reg  [1:0]       req_snpHitReleaseMeta_state;
+  reg              req_snpHitReleaseMeta_clients;
+  reg              req_snpHitReleaseMeta_alias;
+  reg              req_snpHitReleaseMeta_prefetch;
+  reg  [3:0]       req_snpHitReleaseMeta_prefetchSrc;
+  reg              req_snpHitReleaseMeta_accessed;
+  reg              req_snpHitReleaseMeta_tagErr;
+  reg              req_snpHitReleaseMeta_dataErr;
+  reg  [10:0]      req_srcID;
+  reg  [11:0]      req_txnID;
+  reg  [10:0]      req_fwdNID;
+  reg  [11:0]      req_fwdTxnID;
+  reg  [6:0]       req_chiOpcode;
+  reg              req_retToSrc;
+  reg              req_traceTag;
+  reg              dirResult_hit;
+  reg  [33:0]      dirResult_tag;
+  reg  [7:0]       dirResult_set;
+  reg  [2:0]       dirResult_way;
+  reg              dirResult_meta_dirty;
+  reg  [1:0]       dirResult_meta_state;
+  reg              dirResult_meta_clients;
+  reg              dirResult_meta_alias;
+  reg              dirResult_meta_prefetch;
+  reg  [3:0]       dirResult_meta_prefetchSrc;
+  reg              dirResult_meta_accessed;
+  reg              dirResult_meta_tagErr;
+  reg              dirResult_meta_dataErr;
+  reg              state_s_acquire;
+  reg              state_s_rprobe;
+  reg              state_s_pprobe;
+  reg              state_s_release;
+  reg              state_s_probeack;
+  reg              state_s_refill;
+  reg              state_s_retry;
+  reg              state_s_cmoresp;
+  reg              state_s_cmometaw;
+  reg              state_w_rprobeackfirst;
+  reg              state_w_rprobeacklast;
+  reg              state_w_pprobeackfirst;
+  reg              state_w_pprobeacklast;
+  reg              state_w_grantfirst;
+  reg              state_w_grantlast;
+  reg              state_w_grant;
+  reg              state_w_releaseack;
+  reg              state_w_replResp;
+  reg              state_s_rcompack;
+  reg              state_s_wcompack;
+  reg              state_s_cbwrdata;
+  reg              state_s_reissue;
+  reg              state_s_dct;
+  reg  [6:0]       req_released_chiOpcode;
+  reg              req_released_likelyShared;
+  reg  [1:0]       retryTimes;
+  reg  [4:0]       backoffTimer;
+  reg  [10:0]      tgtid_rcompack;
+  reg  [11:0]      txnid_rcompack;
+  reg  [10:0]      tgtid_wcompack;
+  reg  [11:0]      txnid_wcompack;
+  reg  [10:0]      srcid_retryack;
+  reg  [3:0]       pcrdtype;
+  reg              gotRetryAck;
+  reg              gotPCrdGrant;
+  reg              tagErr;
+  reg              denied;
+  reg              corrupt;
+  reg              cbWrDataTraceTag;
+  wire [2:0]       _metaChi_T = {dirResult_meta_dirty, dirResult_meta_state};
+  wire [2:0]       metaChi =
+    {2'h0, _metaChi_T == 3'h1} | {1'h0, _metaChi_T == 3'h2, 1'h0}
+    | {1'h0, _metaChi_T == 3'h3, 1'h0} | {1'h0, _metaChi_T == 3'h6, 1'h0}
+    | {1'h0, &_metaChi_T, 1'h0};
+  wire             req_prefetch = req_opcode == 4'h5;
+  wire             _req_acquire_T = req_opcode == 4'h6;
+  wire             req_acquirePerm = req_opcode == 4'h7;
+  wire             req_needT =
+    ~(req_opcode[2]) | req_prefetch & req_param == 3'h1
+    | (_req_acquire_T | req_acquirePerm) & (|req_param);
+  wire             req_get = req_opcode == 4'h4;
+  wire             req_acquire = _req_acquire_T & req_channel[0] | req_acquirePerm;
+  wire             mp_grant_meta_accessed = req_acquire | req_get;
+  wire             _respPassDirty_T_2 = req_chiOpcode == 7'h7;
+  wire             _fwdPassDirty_T = req_chiOpcode == 7'h17;
+  wire             _respPassDirty_T_4 = req_chiOpcode == 7'h5;
+  wire             _respPassDirty_T_10 = req_chiOpcode == 7'h15;
+  wire             _fwdPassDirty_T_1 = req_chiOpcode == 7'h16;
+  wire             _respPassDirty_T_8 = req_chiOpcode == 7'h9;
+  wire             snpToN =
+    _respPassDirty_T_2 | _fwdPassDirty_T | _respPassDirty_T_4 | _respPassDirty_T_10
+    | _fwdPassDirty_T_1 | _respPassDirty_T_8 | req_chiOpcode == 7'hA
+    | req_chiOpcode == 7'h6;
+  wire             _doRespData_retToSrc_nonFwd_T_2 = req_chiOpcode == 7'h2;
+  wire             _fwdCacheState_T = req_chiOpcode == 7'h12;
+  wire             _doRespData_retToSrc_nonFwd_T_5 = req_chiOpcode == 7'h1;
+  wire             _fwdCacheState_T_3 = req_chiOpcode == 7'h11;
+  wire             _doRespData_retToSrc_nonFwd_T_3 = req_chiOpcode == 7'h4;
+  wire             _fwdCacheState_T_1 = req_chiOpcode == 7'h14;
+  wire             snpToB =
+    _doRespData_retToSrc_nonFwd_T_2 | _fwdCacheState_T | _doRespData_retToSrc_nonFwd_T_5
+    | _fwdCacheState_T_3 | _doRespData_retToSrc_nonFwd_T_3 | _fwdCacheState_T_1;
+  wire             req_cboClean = req_channel[0] & req_opcode == 4'hC;
+  wire             req_cboFlush = req_channel[0] & req_opcode == 4'hD;
+  wire             req_cboInval = req_channel[0] & req_opcode == 4'hE;
+  wire             _a_task_io_tasks_txreq_bits_opcode_T = req_cboClean | req_cboFlush;
+  wire             cmo_cbo = _a_task_io_tasks_txreq_bits_opcode_T | req_cboInval;
+  wire             hitDirty = dirResult_hit & dirResult_meta_dirty;
+  wire             _hitWriteEvict_T = req_snpHitRelease & req_snpHitReleaseWithData;
+  wire             hitWriteClean =
+    _hitWriteEvict_T & req_snpHitReleaseMeta_dirty & req_snpHitReleaseToClean;
+  wire             hitWriteEvict = _hitWriteEvict_T & ~req_snpHitReleaseMeta_dirty;
+  wire             hitWriteDirty =
+    _hitWriteEvict_T & req_snpHitReleaseMeta_dirty & req_snpHitReleaseToInval
+    | hitWriteClean;
+  wire             hitDirtyOrWriteDirty = hitDirty | hitWriteDirty;
+  wire             _mp_probeack_task_mp_probeack_meta_x5_T_14 = req_chiOpcode == 7'h3;
+  wire             _mp_probeack_task_mp_probeack_meta_x5_T_6 = req_chiOpcode == 7'h8;
+  wire             doRespData_dirty =
+    hitDirtyOrWriteDirty
+    & (_mp_probeack_task_mp_probeack_meta_x5_T_14 | snpToB | _respPassDirty_T_2
+       | _respPassDirty_T_4 | _mp_probeack_task_mp_probeack_meta_x5_T_6
+       | _respPassDirty_T_8 | _respPassDirty_T_10);
+  wire             doRespData_retToSrc_fwd =
+    req_retToSrc & (_fwdCacheState_T | _fwdCacheState_T_1 | _fwdCacheState_T_3);
+  wire             _mp_grant_task_mp_grant_useProbeData_T_1 =
+    dirResult_meta_state == 2'h1;
+  wire             doRespData_retToSrc_nonFwd =
+    req_retToSrc & dirResult_hit & _mp_grant_task_mp_grant_useProbeData_T_1
+    & (_doRespData_retToSrc_nonFwd_T_2 | _doRespData_retToSrc_nonFwd_T_3
+       | _doRespData_retToSrc_nonFwd_T_5 | _respPassDirty_T_2 | _respPassDirty_T_4
+       | _respPassDirty_T_10 | _mp_probeack_task_mp_probeack_meta_x5_T_14);
+  wire             _mp_probeack_task_mp_probeack_meta_x6_T_1 = req_chiOpcode == 7'h13;
+  wire             doRespData =
+    (doRespData_dirty | doRespData_retToSrc_fwd | doRespData_retToSrc_nonFwd
+     | hitWriteDirty & _mp_probeack_task_mp_probeack_meta_x6_T_1
+     | (dirResult_hit & ~dirResult_meta_dirty & dirResult_meta_state != 2'h1
+        | hitWriteEvict) & _mp_probeack_task_mp_probeack_meta_x5_T_14) & ~tagErr;
+  wire             _mp_release_task_mp_release_meta_state_T =
+    dirResult_meta_state == 2'h2;
+  wire             req_promoteT =
+    (mp_grant_meta_accessed | req_prefetch)
+    & (dirResult_hit & ~dirResult_meta_clients & (&dirResult_meta_state) | ~dirResult_hit
+       & gotT | dirResult_hit & req_aliasTask
+       & (_mp_release_task_mp_release_meta_state_T | (&dirResult_meta_state)));
+  wire             release_valid1 =
+    ~state_s_release & state_w_rprobeacklast & state_w_grantlast & state_w_grant
+    & state_w_replResp | ~state_s_release & state_w_rprobeacklast & cmo_cbo;
+  wire             release_valid2 =
+    ~state_s_reissue & ~state_w_releaseack & gotRetryAck & gotPCrdGrant;
+  wire             io_tasks_txreq_valid_0 =
+    ~state_s_acquire
+    & ~(cmo_cbo
+        & (~state_w_rprobeacklast | ~state_w_releaseack | ~state_s_cmometaw
+           | ~state_s_cbwrdata)) | ~state_s_reissue & ~state_w_grant & gotRetryAck
+    & gotPCrdGrant | release_valid2;
+  wire             rcompack_valid =
+    ~state_s_rcompack & state_w_grant & state_w_grantfirst;
+  wire             wcompack_valid = ~state_s_wcompack & state_s_rcompack;
+  wire             io_tasks_txrsp_valid_0 = rcompack_valid | wcompack_valid;
+  wire             io_tasks_source_b_valid_0 = ~state_s_pprobe | ~state_s_rprobe;
+  wire             mp_cbwrdata_valid = ~state_s_cbwrdata & state_w_releaseack;
+  wire             mp_probeack_valid = ~state_s_probeack & state_w_pprobeacklast;
+  wire             pending_grant_valid =
+    (~state_s_refill | ~state_s_cmoresp & state_w_releaseack & state_s_cbwrdata)
+    & state_w_grantlast & state_w_grant & state_w_rprobeacklast;
+  wire             _mp_grant_valid_T = retryTimes != 2'h3;
+  wire             mp_grant_valid =
+    pending_grant_valid & (_mp_grant_valid_T | backoffTimer == 5'h14);
+  wire             mp_dct_valid = ~state_s_dct & state_s_probeack;
+  wire             _mp_probeack_task_mp_probeack_dsWen_T = snpToN | tagErr;
+  wire [2:0]       fwdCacheState =
+    tagErr
+      ? 3'h0
+      : _fwdCacheState_T | _fwdCacheState_T_1 | _fwdCacheState_T_3
+          ? 3'h1
+          : {1'h0, _fwdPassDirty_T | _fwdPassDirty_T_1, 1'h0};
+  wire             isWriteBackFull =
+    ~req_cboClean & ~req_cboInval & dirResult_meta_state[1] & dirResult_meta_dirty;
+  wire             isWriteEvictOrEvict =
+    ~req_cboFlush & ~req_cboInval & ~req_cboClean & ~isWriteBackFull;
+  wire             isEvict = ~req_cboClean & ~isWriteBackFull & ~isWriteEvictOrEvict;
+  wire [11:0]      io_tasks_txreq_bits_txnID_0 = {4'h0, io_id};
+  wire [6:0]       mp_release_chiOpcode =
+    cmo_cbo
+      ? (req_cboClean ? 7'h17 : req_cboFlush & isWriteBackFull ? 7'h1B : 7'hD)
+      : isWriteBackFull ? 7'h1B : isWriteEvictOrEvict ? 7'h42 : 7'hD;
+  wire             mp_release_likelyshared =
+    ~cmo_cbo & isWriteEvictOrEvict & _mp_grant_task_mp_grant_useProbeData_T_1;
+  assign mp_probeack_dsWen =
+    ~_mp_probeack_task_mp_probeack_dsWen_T & probeDirty & ~releaseDirty;
+  wire [1:0]       _mp_probeack_task_mp_probeack_chiOpcode_T_1 =
+    {(_fwdCacheState_T_3 | _fwdCacheState_T | _mp_probeack_task_mp_probeack_meta_x6_T_1
+      | _fwdCacheState_T_1 | _fwdPassDirty_T | _fwdPassDirty_T_1) & dirResult_hit
+       | (_fwdCacheState_T_3 | _fwdCacheState_T
+          | _mp_probeack_task_mp_probeack_meta_x6_T_1 | _fwdCacheState_T_1
+          | _fwdPassDirty_T | _fwdPassDirty_T_1) & (hitWriteDirty | hitWriteEvict),
+     doRespData};
+  wire [2:0]       _mp_dct_task_mp_dct_resp_T =
+    {(_fwdPassDirty_T | _fwdPassDirty_T_1) & hitDirtyOrWriteDirty & ~tagErr, 2'h0};
+  reg              mergeA;
+  wire [3:0]       _GEN_0 = _GEN[req_opcode];
+  wire             _mp_grant_task_aliasFinal_T = req_get | req_prefetch;
+  wire [2:0]       _GEN_1 = {2'h0, ~req_promoteT};
+  wire             mp_grant_alias =
+    _mp_grant_task_aliasFinal_T ? dirResult_meta_alias : req_alias;
+  reg  [5:0]       mp_grant_task_merge_task_off;
+  reg              mp_grant_task_merge_task_alias;
+  reg  [43:0]      mp_grant_task_merge_task_vaddr;
+  reg              mp_grant_task_merge_task_isKeyword;
+  reg  [3:0]       mp_grant_task_merge_task_opcode;
+  reg  [2:0]       mp_grant_task_merge_task_param;
+  reg  [6:0]       mp_grant_task_merge_task_sourceId;
+  wire             _GEN_2 = release_valid1 & cmo_cbo & req_cboClean;
+  wire             _io_tasks_mainpipe_bits_T_2 =
+    mp_grant_valid | release_valid1 | mp_cbwrdata_valid;
+  wire             _GEN_3 = mp_grant_valid | release_valid1;
+  wire             _GEN_4 = mp_probeack_valid | mp_dct_valid;
+  wire             _GEN_5 = ~_io_tasks_mainpipe_bits_T_2 | mp_grant_valid;
+  wire             _GEN_6 = _io_tasks_mainpipe_bits_T_2 & mp_grant_valid;
+  wire             _GEN_7 = _io_tasks_mainpipe_bits_T_2 | mp_probeack_valid;
+  wire             _GEN_8 = io_resps_rxdat_bits_chiOpcode == 7'h4;
+  wire             _GEN_9 = io_resps_rxdat_valid & _GEN_8;
+  wire             _GEN_10 = io_resps_rxrsp_bits_chiOpcode == 7'hB;
+  wire             _GEN_11 = io_resps_rxrsp_bits_chiOpcode == 7'h4;
+  wire             _GEN_12 = ~state_w_grant & (state_s_cmoresp | state_w_releaseack);
+  wire             _GEN_13 = _GEN_11 & ~state_w_releaseack & isWriteEvictOrEvict;
+  wire             _GEN_14 = io_resps_rxrsp_bits_chiOpcode == 7'h5;
+  wire             _GEN_15 = io_resps_rxrsp_valid & io_resps_rxrsp_bits_chiOpcode == 7'h3;
+  wire             will_free =
+    state_s_refill & state_s_probeack & state_s_release & state_s_rcompack
+    & state_s_wcompack & state_s_cbwrdata & state_s_reissue & state_s_dct
+    & state_s_cmoresp & state_s_cmometaw & state_w_rprobeacklast & state_w_pprobeacklast
+    & state_w_grantlast & state_w_grant & state_w_releaseack & state_w_replResp;
+  reg              io_msInfo_bits_blockRefill_REG;
+  reg              io_msInfo_bits_blockRefill_REG_1;
+  reg              io_msInfo_bits_blockRefill_REG_2;
+  wire             _nestedwb_hit_match_T_1 = dirResult_set == io_nestedwb_set;
+  wire             _nestedwb_hit_match_T_3 = dirResult_tag == io_nestedwb_tag;
+  wire             nestedwb_match =
+    req_valid & (|dirResult_meta_state) & _nestedwb_hit_match_T_1
+    & _nestedwb_hit_match_T_3 & state_w_replResp & (state_s_cmoresp | dirResult_hit)
+    & (mp_grant_meta_accessed | req_prefetch | dirResult_hit);
+  wire             _GEN_16 =
+    io_alloc_valid ? io_alloc_bits_state_w_grantfirst : state_w_grantfirst;
+  wire             _GEN_17 =
+    io_alloc_valid ? io_alloc_bits_state_w_grantlast : state_w_grantlast;
+  wire             _GEN_18 = io_alloc_valid ? io_alloc_bits_state_w_grant : state_w_grant;
+  wire             _GEN_19 =
+    io_alloc_valid ? io_alloc_bits_state_w_releaseack : state_w_releaseack;
+  wire             _GEN_20 =
+    io_alloc_valid ? io_alloc_bits_state_w_replResp : state_w_replResp;
+  wire             _GEN_21 =
+    io_alloc_valid ? io_alloc_bits_dirResult_meta_dirty : dirResult_meta_dirty;
+  wire             _GEN_22 = ~io_alloc_valid & gotT;
+  wire             _GEN_23 = ~io_alloc_valid & gotDirty;
+  wire             _weFire_T = io_tasks_txreq_ready & io_tasks_txreq_valid_0;
+  wire             _GEN_24 = ~state_s_reissue | io_alloc_valid;
+  wire             _GEN_25 = io_tasks_txrsp_ready & io_tasks_txrsp_valid_0;
+  wire             _GEN_26 = io_tasks_source_b_ready & io_tasks_source_b_valid_0;
+  wire             _GEN_27 = io_tasks_mainpipe_ready & mp_grant_valid;
+  wire             _GEN_28 =
+    io_tasks_mainpipe_ready & ~mp_grant_valid & release_valid1
+    | (io_alloc_valid ? io_alloc_bits_state_s_release : state_s_release);
+  wire             _GEN_29 = ~io_tasks_mainpipe_ready | mp_grant_valid;
+  wire             _GEN_30 =
+    ~io_tasks_mainpipe_ready | mp_grant_valid
+    | ~(release_valid1 ? isEvict : mp_cbwrdata_valid);
+  wire             _GEN_31 = io_resps_sinkC_bits_opcode == 3'h4;
+  wire             _GEN_32 = io_resps_sinkC_bits_opcode == 3'h5;
+  wire             _GEN_33 = io_resps_sinkC_valid & (_GEN_31 | _GEN_32);
+  wire             _GEN_34 = io_resps_sinkC_valid & _GEN_32;
+  wire             _GEN_35 = _GEN_34 | ~io_alloc_valid & probeDirty;
+  wire             _GEN_36 = io_resps_sinkC_bits_param == 3'h1;
+  wire             _GEN_37 =
+    _GEN_36 | io_resps_sinkC_bits_param == 3'h2 | io_resps_sinkC_bits_param == 3'h5;
+  wire             _GEN_38 = io_resps_sinkC_bits_param == 3'h0;
+  wire             _GEN_39 = _GEN_38 | io_resps_sinkC_bits_param == 3'h4;
+  wire             _GEN_40 =
+    io_resps_sinkC_valid & (_GEN_36 | _GEN_38 | io_resps_sinkC_bits_param == 3'h3);
+  wire             _GEN_41 =
+    _GEN_40 ? denied | io_resps_sinkC_bits_denied : ~io_alloc_valid & denied;
+  wire             _GEN_42 =
+    _GEN_40 ? corrupt | io_resps_sinkC_bits_corrupt : ~io_alloc_valid & corrupt;
+  wire             _GEN_43 = _GEN_32 & state_w_rprobeackfirst;
+  wire             _GEN_44 = dirResult_meta_dirty | _GEN_43;
+  wire             _GEN_45 = io_resps_sinkC_valid & req_cboClean;
+  wire             rxdatIsU = io_resps_rxdat_bits_resp == 3'h2;
+  wire             rxdatIsU_PD = io_resps_rxdat_bits_resp == 3'h6;
+  wire             derr = io_resps_rxdat_bits_respErr == 2'h2;
+  wire             _GEN_46 = io_resps_rxdat_bits_chiOpcode == 7'hB;
+  wire             _GEN_47 = io_resps_rxdat_valid & (_GEN_8 | _GEN_46);
+  wire             _GEN_48 =
+    io_resps_rxdat_valid
+      ? (_GEN_8
+           ? denied | (&io_resps_rxdat_bits_respErr)
+           : _GEN_46 ? denied | (&io_resps_rxdat_bits_respErr) : _GEN_41)
+      : _GEN_41;
+  wire             _GEN_49 = _GEN_10 | _GEN_9;
+  wire             _GEN_50 = _GEN_11 & _GEN_12;
+  wire             _GEN_51 = io_resps_rxrsp_valid & _GEN_50;
+  wire             _GEN_52 = io_resps_rxrsp_valid & _GEN_13;
+  wire             _GEN_53 = io_replResp_valid & io_replResp_bits_retry;
+  wire             _GEN_54 = io_replResp_valid & ~io_replResp_bits_retry;
+  wire             _GEN_55 =
+    _GEN_54
+      ? io_replResp_bits_meta_dirty
+      : _GEN_34
+        | (_GEN_29
+             ? _GEN_21
+             : release_valid1 ? ~isEvict & _GEN_21 : ~mp_cbwrdata_valid & _GEN_21);
+  wire             _GEN_56 =
+    _GEN_54
+      ? io_replResp_bits_meta_clients
+      : ~(io_resps_sinkC_valid & _GEN_37)
+        & (io_alloc_valid
+             ? io_alloc_bits_dirResult_meta_clients
+             : dirResult_meta_clients);
+  wire             _GEN_57 = _GEN_54 & (|io_replResp_bits_meta_state);
+  wire             _GEN_58 =
+    _GEN_54 & (|io_replResp_bits_meta_state) & io_replResp_bits_meta_clients;
+  wire             nestedwb_hit_match =
+    req_valid & dirResult_hit & _nestedwb_hit_match_T_1 & _nestedwb_hit_match_T_3;
+  wire             _GEN_59 = io_nestedwb_c_set_tip | io_nestedwb_c_set_dirty;
+  wire             _GEN_60 = nestedwb_match & _GEN_59;
+  wire             _GEN_61 = io_nestedwb_b_inv_dirty & req_channel[0];
+  wire             _GEN_62 = nestedwb_match & _GEN_61;
+  wire             _GEN_63 = io_nestedwb_b_toClean & req_channel[0];
+  wire             _GEN_64 = io_nestedwb_b_toN & req_channel[0];
+  wire             _GEN_65 = nestedwb_hit_match & _GEN_64;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      gotT <= 1'h0;
+      gotDirty <= 1'h0;
+      gotGrantData <= 1'h0;
+      probeDirty <= 1'h0;
+      releaseDirty <= 1'h0;
+      beatCnt <= 1'h0;
+      req_valid <= 1'h0;
+      req_channel <= 3'h0;
+      req_set <= 8'h0;
+      req_tag <= 34'h0;
+      req_off <= 6'h0;
+      req_alias <= 1'h0;
+      req_isKeyword <= 1'h0;
+      req_opcode <= 4'h0;
+      req_param <= 3'h0;
+      req_sourceId <= 7'h0;
+      req_aliasTask <= 1'h0;
+      req_fromL2pft <= 1'h0;
+      req_reqSource <= 5'h0;
+      req_snpHitRelease <= 1'h0;
+      req_snpHitReleaseToInval <= 1'h0;
+      req_snpHitReleaseToClean <= 1'h0;
+      req_snpHitReleaseWithData <= 1'h0;
+      req_snpHitReleaseIdx <= 8'h0;
+      req_snpHitReleaseMeta_dirty <= 1'h0;
+      req_snpHitReleaseMeta_state <= 2'h0;
+      req_snpHitReleaseMeta_clients <= 1'h0;
+      req_snpHitReleaseMeta_alias <= 1'h0;
+      req_snpHitReleaseMeta_prefetch <= 1'h0;
+      req_snpHitReleaseMeta_prefetchSrc <= 4'h0;
+      req_snpHitReleaseMeta_accessed <= 1'h0;
+      req_snpHitReleaseMeta_tagErr <= 1'h0;
+      req_snpHitReleaseMeta_dataErr <= 1'h0;
+      req_srcID <= 11'h0;
+      req_txnID <= 12'h0;
+      req_fwdNID <= 11'h0;
+      req_fwdTxnID <= 12'h0;
+      req_chiOpcode <= 7'h0;
+      req_retToSrc <= 1'h0;
+      req_traceTag <= 1'h0;
+      dirResult_hit <= 1'h0;
+      dirResult_tag <= 34'h0;
+      dirResult_set <= 8'h0;
+      dirResult_way <= 3'h0;
+      dirResult_meta_dirty <= 1'h0;
+      dirResult_meta_state <= 2'h0;
+      dirResult_meta_clients <= 1'h0;
+      dirResult_meta_alias <= 1'h0;
+      dirResult_meta_prefetch <= 1'h0;
+      dirResult_meta_prefetchSrc <= 4'h0;
+      dirResult_meta_accessed <= 1'h0;
+      dirResult_meta_tagErr <= 1'h0;
+      dirResult_meta_dataErr <= 1'h0;
+      state_s_acquire <= 1'h1;
+      state_s_rprobe <= 1'h1;
+      state_s_pprobe <= 1'h1;
+      state_s_release <= 1'h1;
+      state_s_probeack <= 1'h1;
+      state_s_refill <= 1'h1;
+      state_s_retry <= 1'h1;
+      state_s_cmoresp <= 1'h1;
+      state_s_cmometaw <= 1'h1;
+      state_w_rprobeackfirst <= 1'h1;
+      state_w_rprobeacklast <= 1'h1;
+      state_w_pprobeackfirst <= 1'h1;
+      state_w_pprobeacklast <= 1'h1;
+      state_w_grantfirst <= 1'h1;
+      state_w_grantlast <= 1'h1;
+      state_w_grant <= 1'h1;
+      state_w_releaseack <= 1'h1;
+      state_w_replResp <= 1'h1;
+      state_s_rcompack <= 1'h1;
+      state_s_wcompack <= 1'h1;
+      state_s_cbwrdata <= 1'h1;
+      state_s_reissue <= 1'h1;
+      state_s_dct <= 1'h1;
+      req_released_chiOpcode <= 7'h0;
+      req_released_likelyShared <= 1'h0;
+      retryTimes <= 2'h0;
+      backoffTimer <= 5'h0;
+      pcrdtype <= 4'h0;
+      gotRetryAck <= 1'h0;
+      gotPCrdGrant <= 1'h0;
+      tagErr <= 1'h0;
+      denied <= 1'h0;
+      corrupt <= 1'h0;
+      cbWrDataTraceTag <= 1'h0;
+      mergeA <= 1'h0;
+      mp_grant_task_merge_task_off <= 6'h0;
+      mp_grant_task_merge_task_alias <= 1'h0;
+      mp_grant_task_merge_task_vaddr <= 44'h0;
+      mp_grant_task_merge_task_isKeyword <= 1'h0;
+      mp_grant_task_merge_task_opcode <= 4'h0;
+      mp_grant_task_merge_task_param <= 3'h0;
+      mp_grant_task_merge_task_sourceId <= 7'h0;
+      io_msInfo_bits_blockRefill_REG <= 1'h0;
+      io_msInfo_bits_blockRefill_REG_1 <= 1'h0;
+      io_msInfo_bits_blockRefill_REG_2 <= 1'h0;
+    end
+    else begin
+      gotT <=
+        _GEN_51
+          ? io_resps_rxrsp_bits_resp == 3'h2
+          : io_resps_rxdat_valid
+              ? (_GEN_8
+                   ? rxdatIsU | rxdatIsU_PD
+                   : _GEN_46 ? rxdatIsU | rxdatIsU_PD : _GEN_22)
+              : _GEN_22;
+      gotDirty <=
+        ~_GEN_51
+        & (io_resps_rxdat_valid
+             ? (_GEN_8
+                  ? gotDirty | rxdatIsU_PD
+                  : _GEN_46 ? gotDirty | rxdatIsU_PD : _GEN_23)
+             : _GEN_23);
+      gotGrantData <= _GEN_47 | ~io_alloc_valid & gotGrantData;
+      probeDirty <=
+        nestedwb_hit_match ? ~(_GEN_63 | _GEN_62) & _GEN_35 : ~_GEN_62 & _GEN_35;
+      releaseDirty <=
+        nestedwb_match & io_nestedwb_c_set_dirty | ~io_alloc_valid & releaseDirty;
+      beatCnt <=
+        io_resps_rxdat_valid & _GEN_46 ? 1'(beatCnt - 1'h1) : ~io_alloc_valid & beatCnt;
+      req_valid <= ~(will_free & req_valid) & (io_alloc_valid | req_valid);
+      if (io_alloc_valid) begin
+        req_channel <= io_alloc_bits_task_channel;
+        req_set <= io_alloc_bits_task_set;
+        req_tag <= io_alloc_bits_task_tag;
+        req_off <= io_alloc_bits_task_off;
+        req_alias <= io_alloc_bits_task_alias;
+        req_isKeyword <= io_alloc_bits_task_isKeyword;
+        req_opcode <= io_alloc_bits_task_opcode;
+        req_param <= io_alloc_bits_task_param;
+        req_sourceId <= io_alloc_bits_task_sourceId;
+        req_fromL2pft <= io_alloc_bits_task_fromL2pft;
+        req_reqSource <= io_alloc_bits_task_reqSource;
+        req_snpHitRelease <= io_alloc_bits_task_snpHitRelease;
+        req_snpHitReleaseToInval <= io_alloc_bits_task_snpHitReleaseToInval;
+        req_snpHitReleaseToClean <= io_alloc_bits_task_snpHitReleaseToClean;
+        req_snpHitReleaseWithData <= io_alloc_bits_task_snpHitReleaseWithData;
+        req_snpHitReleaseIdx <= io_alloc_bits_task_snpHitReleaseIdx;
+        req_snpHitReleaseMeta_dirty <= io_alloc_bits_task_snpHitReleaseMeta_dirty;
+        req_snpHitReleaseMeta_state <= io_alloc_bits_task_snpHitReleaseMeta_state;
+        req_snpHitReleaseMeta_clients <= io_alloc_bits_task_snpHitReleaseMeta_clients;
+        req_snpHitReleaseMeta_alias <= io_alloc_bits_task_snpHitReleaseMeta_alias;
+        req_snpHitReleaseMeta_prefetch <= io_alloc_bits_task_snpHitReleaseMeta_prefetch;
+        req_snpHitReleaseMeta_prefetchSrc <=
+          io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc;
+        req_snpHitReleaseMeta_accessed <= io_alloc_bits_task_snpHitReleaseMeta_accessed;
+        req_snpHitReleaseMeta_tagErr <= io_alloc_bits_task_snpHitReleaseMeta_tagErr;
+        req_snpHitReleaseMeta_dataErr <= io_alloc_bits_task_snpHitReleaseMeta_dataErr;
+        req_srcID <= io_alloc_bits_task_srcID;
+        req_txnID <= io_alloc_bits_task_txnID;
+        req_fwdNID <= io_alloc_bits_task_fwdNID;
+        req_fwdTxnID <= io_alloc_bits_task_fwdTxnID;
+        req_chiOpcode <= io_alloc_bits_task_chiOpcode;
+        req_retToSrc <= io_alloc_bits_task_retToSrc;
+        dirResult_set <= io_alloc_bits_dirResult_set;
+        tagErr <=
+          io_alloc_bits_dirResult_hit
+          & (io_alloc_bits_dirResult_meta_tagErr | io_alloc_bits_dirResult_error);
+      end
+      req_aliasTask <=
+        ~_GEN_65 & (io_alloc_valid ? io_alloc_bits_task_aliasTask : req_aliasTask);
+      if (io_resps_rxrsp_valid
+          & (_GEN_11 & (~state_w_releaseack & isWriteEvictOrEvict | _GEN_12) | _GEN_10))
+        req_traceTag <= io_resps_rxrsp_bits_traceTag;
+      else if (_GEN_9)
+        req_traceTag <= req_traceTag | io_resps_rxdat_bits_traceTag;
+      else if (io_alloc_valid)
+        req_traceTag <= io_alloc_bits_task_traceTag;
+      dirResult_hit <=
+        ~_GEN_65 & (io_alloc_valid ? io_alloc_bits_dirResult_hit : dirResult_hit);
+      if (_GEN_54) begin
+        dirResult_tag <= io_replResp_bits_tag;
+        dirResult_meta_alias <= io_replResp_bits_meta_alias;
+        dirResult_meta_prefetch <= io_replResp_bits_meta_prefetch;
+        dirResult_meta_prefetchSrc <= io_replResp_bits_meta_prefetchSrc;
+        dirResult_meta_accessed <= io_replResp_bits_meta_accessed;
+        dirResult_meta_tagErr <= io_replResp_bits_meta_tagErr;
+        dirResult_meta_dataErr <= io_replResp_bits_meta_dataErr;
+      end
+      else begin
+        if (io_alloc_valid) begin
+          dirResult_tag <= io_alloc_bits_dirResult_tag;
+          dirResult_meta_alias <= io_alloc_bits_dirResult_meta_alias;
+          dirResult_meta_prefetch <= io_alloc_bits_dirResult_meta_prefetch;
+          dirResult_meta_prefetchSrc <= io_alloc_bits_dirResult_meta_prefetchSrc;
+          dirResult_meta_accessed <= io_alloc_bits_dirResult_meta_accessed;
+        end
+        if (_GEN_40) begin
+          dirResult_meta_tagErr <= io_resps_sinkC_bits_denied;
+          dirResult_meta_dataErr <= io_resps_sinkC_bits_corrupt;
+        end
+        else if (io_alloc_valid) begin
+          dirResult_meta_tagErr <= io_alloc_bits_dirResult_meta_tagErr;
+          dirResult_meta_dataErr <= io_alloc_bits_dirResult_meta_dataErr;
+        end
+      end
+      if (_GEN_54 | _GEN_53)
+        dirResult_way <= io_replResp_bits_way;
+      else if (io_alloc_valid)
+        dirResult_way <= io_alloc_bits_dirResult_way;
+      dirResult_meta_dirty <=
+        ~(nestedwb_hit_match & _GEN_63)
+        & (nestedwb_match ? ~_GEN_61 & (io_nestedwb_c_set_dirty | _GEN_55) : _GEN_55);
+      if (nestedwb_hit_match) begin
+        if (_GEN_64)
+          dirResult_meta_state <= 2'h0;
+        else if (io_nestedwb_b_toB & req_channel[0])
+          dirResult_meta_state <= {1'h0, |dirResult_meta_state};
+        else if (nestedwb_match) begin
+          if (_GEN_61)
+            dirResult_meta_state <= 2'h0;
+          else if (_GEN_59)
+            dirResult_meta_state <= 2'h3;
+          else if (_GEN_54)
+            dirResult_meta_state <= io_replResp_bits_meta_state;
+          else if (io_resps_sinkC_valid) begin
+            if (_GEN_39) begin
+              if (dirResult_meta_state[1])
+                dirResult_meta_state <= 2'h3;
+            end
+            else if (_GEN_37) begin
+              if (dirResult_meta_state[1])
+                dirResult_meta_state <= 2'h3;
+            end
+            else if (_GEN_30) begin
+              if (io_alloc_valid)
+                dirResult_meta_state <= io_alloc_bits_dirResult_meta_state;
+            end
+            else
+              dirResult_meta_state <= 2'h0;
+          end
+          else if (_GEN_30) begin
+            if (io_alloc_valid)
+              dirResult_meta_state <= io_alloc_bits_dirResult_meta_state;
+          end
+          else
+            dirResult_meta_state <= 2'h0;
+        end
+        else if (_GEN_54)
+          dirResult_meta_state <= io_replResp_bits_meta_state;
+        else if (io_resps_sinkC_valid) begin
+          if (_GEN_39) begin
+            if (dirResult_meta_state[1])
+              dirResult_meta_state <= 2'h3;
+          end
+          else if (_GEN_37) begin
+            if (dirResult_meta_state[1])
+              dirResult_meta_state <= 2'h3;
+          end
+          else if (_GEN_30) begin
+            if (io_alloc_valid)
+              dirResult_meta_state <= io_alloc_bits_dirResult_meta_state;
+          end
+          else
+            dirResult_meta_state <= 2'h0;
+        end
+        else if (_GEN_30) begin
+          if (io_alloc_valid)
+            dirResult_meta_state <= io_alloc_bits_dirResult_meta_state;
+        end
+        else
+          dirResult_meta_state <= 2'h0;
+      end
+      else if (nestedwb_match) begin
+        if (_GEN_61)
+          dirResult_meta_state <= 2'h0;
+        else if (_GEN_59)
+          dirResult_meta_state <= 2'h3;
+        else if (_GEN_54)
+          dirResult_meta_state <= io_replResp_bits_meta_state;
+        else if (io_resps_sinkC_valid) begin
+          if (_GEN_39) begin
+            if (dirResult_meta_state[1])
+              dirResult_meta_state <= 2'h3;
+          end
+          else if (_GEN_37) begin
+            if (dirResult_meta_state[1])
+              dirResult_meta_state <= 2'h3;
+          end
+          else if (_GEN_30) begin
+            if (io_alloc_valid)
+              dirResult_meta_state <= io_alloc_bits_dirResult_meta_state;
+          end
+          else
+            dirResult_meta_state <= 2'h0;
+        end
+        else if (_GEN_30) begin
+          if (io_alloc_valid)
+            dirResult_meta_state <= io_alloc_bits_dirResult_meta_state;
+        end
+        else
+          dirResult_meta_state <= 2'h0;
+      end
+      else if (_GEN_54)
+        dirResult_meta_state <= io_replResp_bits_meta_state;
+      else if (io_resps_sinkC_valid) begin
+        if (_GEN_39) begin
+          if (dirResult_meta_state[1])
+            dirResult_meta_state <= 2'h3;
+        end
+        else if (_GEN_37) begin
+          if (dirResult_meta_state[1])
+            dirResult_meta_state <= 2'h3;
+        end
+        else if (_GEN_30) begin
+          if (io_alloc_valid)
+            dirResult_meta_state <= io_alloc_bits_dirResult_meta_state;
+        end
+        else
+          dirResult_meta_state <= 2'h0;
+      end
+      else if (_GEN_30) begin
+        if (io_alloc_valid)
+          dirResult_meta_state <= io_alloc_bits_dirResult_meta_state;
+      end
+      else
+        dirResult_meta_state <= 2'h0;
+      dirResult_meta_clients <=
+        nestedwb_hit_match ? ~(_GEN_64 | _GEN_60) & _GEN_56 : ~_GEN_60 & _GEN_56;
+      if (_weFire_T)
+        state_s_acquire <= ~cmo_cbo | state_s_acquire | state_w_releaseack;
+      else if (io_alloc_valid)
+        state_s_acquire <= io_alloc_bits_state_s_acquire;
+      state_s_rprobe <=
+        ~_GEN_58
+        & (_GEN_26 | (io_alloc_valid ? io_alloc_bits_state_s_rprobe : state_s_rprobe));
+      state_s_pprobe <=
+        _GEN_26 | (io_alloc_valid ? io_alloc_bits_state_s_pprobe : state_s_pprobe);
+      state_s_release <=
+        ~_GEN_57
+        & (_GEN_45 ? (_GEN_31 ? ~_GEN_44 & _GEN_28 : ~_GEN_43 & _GEN_28) : _GEN_28);
+      state_s_probeack <=
+        io_tasks_mainpipe_ready & ~(mp_grant_valid | release_valid1 | mp_cbwrdata_valid)
+        & mp_probeack_valid
+        | (io_alloc_valid ? io_alloc_bits_state_s_probeack : state_s_probeack);
+      state_s_refill <=
+        ~_GEN_53
+        & (_GEN_27 | (io_alloc_valid ? io_alloc_bits_state_s_refill : state_s_refill));
+      state_s_retry <= ~_GEN_53 & (_GEN_27 | io_alloc_valid | state_s_retry);
+      state_s_cmoresp <=
+        io_tasks_mainpipe_ready & mp_grant_valid & _GEN_0 == 4'h8
+        | (io_alloc_valid ? io_alloc_bits_state_s_cmoresp : state_s_cmoresp);
+      state_s_cmometaw <=
+        (~(io_resps_sinkC_valid & req_cboClean & _GEN_31) | dirResult_meta_dirty)
+        & (io_tasks_mainpipe_ready
+           & ~(mp_grant_valid | release_valid1 | mp_cbwrdata_valid | _GEN_4)
+           | io_alloc_valid | state_s_cmometaw);
+      state_w_rprobeackfirst <=
+        ~_GEN_58
+        & (_GEN_33
+           | (io_alloc_valid
+                ? io_alloc_bits_state_w_rprobeackfirst
+                : state_w_rprobeackfirst));
+      state_w_rprobeacklast <=
+        ~_GEN_58
+        & (_GEN_33
+             ? state_w_rprobeacklast | io_resps_sinkC_bits_last
+             : io_alloc_valid
+                 ? io_alloc_bits_state_w_rprobeacklast
+                 : state_w_rprobeacklast);
+      state_w_pprobeackfirst <=
+        _GEN_33
+        | (io_alloc_valid
+             ? io_alloc_bits_state_w_pprobeackfirst
+             : state_w_pprobeackfirst);
+      if (_GEN_33)
+        state_w_pprobeacklast <= state_w_pprobeacklast | io_resps_sinkC_bits_last;
+      else if (io_alloc_valid)
+        state_w_pprobeacklast <= io_alloc_bits_state_w_pprobeacklast;
+      state_w_grantfirst <=
+        io_resps_rxrsp_valid & _GEN_11 ? _GEN_12 | _GEN_47 | _GEN_16 : _GEN_47 | _GEN_16;
+      state_w_grantlast <=
+        _GEN_51
+        | (io_resps_rxdat_valid
+             ? (_GEN_8
+                  ? state_w_grantfirst
+                  : _GEN_46 ? state_w_grantfirst & beatCnt : _GEN_17)
+             : _GEN_17);
+      state_w_grant <=
+        io_resps_rxrsp_valid
+          ? (_GEN_11 ? _GEN_12 | _GEN_49 | _GEN_18 : _GEN_49 | _GEN_18)
+          : _GEN_9 | _GEN_18;
+      state_w_releaseack <=
+        ~_GEN_57
+        & (io_resps_rxrsp_valid & (_GEN_14 | _GEN_11 & ~state_w_releaseack)
+           | (_GEN_45 ? (_GEN_31 ? ~_GEN_44 & _GEN_19 : ~_GEN_43 & _GEN_19) : _GEN_19));
+      state_w_replResp <=
+        _GEN_65
+          ? cmo_cbo
+          : _GEN_54
+            | (io_resps_rxrsp_valid & _GEN_10
+                 ? state_w_replResp | (&io_resps_rxrsp_bits_respErr)
+                 : io_resps_rxdat_valid
+                     ? (_GEN_8
+                          ? state_w_replResp | (&io_resps_rxdat_bits_respErr)
+                          : _GEN_46
+                              ? state_w_replResp | (&io_resps_rxdat_bits_respErr)
+                              : _GEN_20)
+                     : _GEN_20);
+      state_s_rcompack <=
+        _GEN_25 & rcompack_valid
+        | (io_alloc_valid ? io_alloc_bits_state_s_rcompack : state_s_rcompack);
+      state_s_wcompack <=
+        ~_GEN_52 & (_GEN_25 & wcompack_valid | io_alloc_valid | state_s_wcompack);
+      state_s_cbwrdata <=
+        _GEN_52
+        | (_GEN_29
+             ? io_alloc_valid | state_s_cbwrdata
+             : release_valid1
+                 ? isEvict
+                 : mp_cbwrdata_valid | io_alloc_valid | state_s_cbwrdata);
+      state_s_reissue <=
+        ~io_pCrd_grant
+        & (_weFire_T & ~state_s_reissue | io_alloc_valid | state_s_reissue);
+      state_s_dct <=
+        io_tasks_mainpipe_ready
+        & ~(mp_grant_valid | release_valid1 | mp_cbwrdata_valid | mp_probeack_valid)
+        & mp_dct_valid | (io_alloc_valid ? io_alloc_bits_state_s_dct : state_s_dct);
+      if (~io_tasks_mainpipe_ready | mp_grant_valid | ~release_valid1) begin
+      end
+      else begin
+        req_released_chiOpcode <= mp_release_chiOpcode;
+        req_released_likelyShared <= mp_release_likelyshared;
+      end
+      if (_GEN_53 & _mp_grant_valid_T)
+        retryTimes <= 2'(retryTimes + 2'h1);
+      else if (io_alloc_valid)
+        retryTimes <= 2'h0;
+      if (_GEN_53)
+        backoffTimer <= 5'h0;
+      else if (pending_grant_valid & backoffTimer < 5'h14 & (&retryTimes))
+        backoffTimer <= 5'(backoffTimer + 5'h1);
+      else if (io_alloc_valid)
+        backoffTimer <= 5'h0;
+      if (_GEN_15)
+        pcrdtype <= io_resps_rxrsp_bits_pCrdType;
+      else if (io_alloc_valid)
+        pcrdtype <= 4'h0;
+      gotRetryAck <=
+        _GEN_15 | (_weFire_T ? ~_GEN_24 & gotRetryAck : ~io_alloc_valid & gotRetryAck);
+      gotPCrdGrant <=
+        io_pCrd_grant
+        | (_weFire_T ? ~_GEN_24 & gotPCrdGrant : ~io_alloc_valid & gotPCrdGrant);
+      denied <=
+        io_resps_rxrsp_valid
+          ? (_GEN_50
+               ? denied | (&io_resps_rxrsp_bits_respErr)
+               : _GEN_10 ? denied | (&io_resps_rxrsp_bits_respErr) : _GEN_48)
+          : _GEN_48;
+      corrupt <=
+        io_resps_rxdat_valid
+          ? (_GEN_8
+               ? corrupt | derr | (&io_resps_rxdat_bits_respErr)
+                 | io_resps_rxdat_bits_corrupt
+               : _GEN_46
+                   ? corrupt | derr | (&io_resps_rxdat_bits_respErr)
+                     | io_resps_rxdat_bits_corrupt
+                   : _GEN_42)
+          : _GEN_42;
+      cbWrDataTraceTag <=
+        io_resps_rxrsp_valid & _GEN_14
+          ? io_resps_rxrsp_bits_traceTag
+          : ~io_alloc_valid & cbWrDataTraceTag;
+      mergeA <= io_aMergeTask_valid | ~io_alloc_valid & mergeA;
+      if (io_aMergeTask_valid) begin
+        mp_grant_task_merge_task_off <= io_aMergeTask_bits_off;
+        mp_grant_task_merge_task_alias <= io_aMergeTask_bits_alias;
+        mp_grant_task_merge_task_vaddr <= io_aMergeTask_bits_vaddr;
+        mp_grant_task_merge_task_isKeyword <= io_aMergeTask_bits_isKeyword;
+        mp_grant_task_merge_task_opcode <= io_aMergeTask_bits_opcode;
+        mp_grant_task_merge_task_param <= io_aMergeTask_bits_param;
+        mp_grant_task_merge_task_sourceId <= io_aMergeTask_bits_sourceId;
+      end
+      io_msInfo_bits_blockRefill_REG <= ~state_s_release;
+      io_msInfo_bits_blockRefill_REG_1 <= ~state_s_release;
+      io_msInfo_bits_blockRefill_REG_2 <= io_msInfo_bits_blockRefill_REG_1;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (io_resps_rxrsp_valid & (_GEN_11 & _GEN_12 | _GEN_10)) begin
+      tgtid_rcompack <= io_resps_rxrsp_bits_srcID;
+      txnid_rcompack <= io_resps_rxrsp_bits_dbID;
+    end
+    else if (_GEN_9) begin
+      tgtid_rcompack <= io_resps_rxdat_bits_homeNID;
+      txnid_rcompack <= io_resps_rxdat_bits_dbID;
+    end
+    if (io_resps_rxrsp_valid & (_GEN_14 | _GEN_13)) begin
+      tgtid_wcompack <= io_resps_rxrsp_bits_srcID;
+      txnid_wcompack <= io_resps_rxrsp_bits_dbID;
+    end
+    if (_GEN_15)
+      srcid_retryack <= io_resps_rxrsp_bits_srcID;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:31];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [5:0] i = 6'h0; i < 6'h20; i += 6'h1) begin
+          _RANDOM[i[4:0]] = `RANDOM;
+        end
+        gotT = _RANDOM[5'h0][0];
+        gotDirty = _RANDOM[5'h0][1];
+        gotGrantData = _RANDOM[5'h0][2];
+        probeDirty = _RANDOM[5'h0][3];
+        releaseDirty = _RANDOM[5'h0][4];
+        beatCnt = _RANDOM[5'h2][5];
+        req_valid = _RANDOM[5'h2][6];
+        req_channel = _RANDOM[5'h2][9:7];
+        req_set = _RANDOM[5'h2][20:13];
+        req_tag = {_RANDOM[5'h2][31:21], _RANDOM[5'h3][22:0]};
+        req_off = _RANDOM[5'h3][28:23];
+        req_alias = _RANDOM[5'h3][29];
+        req_isKeyword = _RANDOM[5'h5][10];
+        req_opcode = _RANDOM[5'h5][14:11];
+        req_param = _RANDOM[5'h5][17:15];
+        req_sourceId = _RANDOM[5'h5][27:21];
+        req_aliasTask = _RANDOM[5'h6][10];
+        req_fromL2pft = _RANDOM[5'h6][14];
+        req_reqSource = _RANDOM[5'h7][19:15];
+        req_snpHitRelease = _RANDOM[5'hA][3];
+        req_snpHitReleaseToInval = _RANDOM[5'hA][4];
+        req_snpHitReleaseToClean = _RANDOM[5'hA][5];
+        req_snpHitReleaseWithData = _RANDOM[5'hA][6];
+        req_snpHitReleaseIdx = _RANDOM[5'hA][14:7];
+        req_snpHitReleaseMeta_dirty = _RANDOM[5'hA][15];
+        req_snpHitReleaseMeta_state = _RANDOM[5'hA][17:16];
+        req_snpHitReleaseMeta_clients = _RANDOM[5'hA][18];
+        req_snpHitReleaseMeta_alias = _RANDOM[5'hA][19];
+        req_snpHitReleaseMeta_prefetch = _RANDOM[5'hA][20];
+        req_snpHitReleaseMeta_prefetchSrc = _RANDOM[5'hA][24:21];
+        req_snpHitReleaseMeta_accessed = _RANDOM[5'hA][25];
+        req_snpHitReleaseMeta_tagErr = _RANDOM[5'hA][26];
+        req_snpHitReleaseMeta_dataErr = _RANDOM[5'hA][27];
+        req_srcID = _RANDOM[5'hB][17:7];
+        req_txnID = _RANDOM[5'hB][29:18];
+        req_fwdNID = _RANDOM[5'hC][31:21];
+        req_fwdTxnID = _RANDOM[5'hD][11:0];
+        req_chiOpcode = _RANDOM[5'hD][18:12];
+        req_retToSrc = _RANDOM[5'hD][29];
+        req_traceTag = _RANDOM[5'hE][5];
+        dirResult_hit = _RANDOM[5'hE][6];
+        dirResult_tag = {_RANDOM[5'hE][31:7], _RANDOM[5'hF][8:0]};
+        dirResult_set = _RANDOM[5'hF][16:9];
+        dirResult_way = _RANDOM[5'hF][19:17];
+        dirResult_meta_dirty = _RANDOM[5'hF][20];
+        dirResult_meta_state = _RANDOM[5'hF][22:21];
+        dirResult_meta_clients = _RANDOM[5'hF][23];
+        dirResult_meta_alias = _RANDOM[5'hF][24];
+        dirResult_meta_prefetch = _RANDOM[5'hF][25];
+        dirResult_meta_prefetchSrc = _RANDOM[5'hF][29:26];
+        dirResult_meta_accessed = _RANDOM[5'hF][30];
+        dirResult_meta_tagErr = _RANDOM[5'hF][31];
+        dirResult_meta_dataErr = _RANDOM[5'h10][0];
+        state_s_acquire = _RANDOM[5'h10][14];
+        state_s_rprobe = _RANDOM[5'h10][15];
+        state_s_pprobe = _RANDOM[5'h10][16];
+        state_s_release = _RANDOM[5'h10][17];
+        state_s_probeack = _RANDOM[5'h10][18];
+        state_s_refill = _RANDOM[5'h10][19];
+        state_s_retry = _RANDOM[5'h10][20];
+        state_s_cmoresp = _RANDOM[5'h10][21];
+        state_s_cmometaw = _RANDOM[5'h10][22];
+        state_w_rprobeackfirst = _RANDOM[5'h10][23];
+        state_w_rprobeacklast = _RANDOM[5'h10][24];
+        state_w_pprobeackfirst = _RANDOM[5'h10][25];
+        state_w_pprobeacklast = _RANDOM[5'h10][26];
+        state_w_grantfirst = _RANDOM[5'h10][27];
+        state_w_grantlast = _RANDOM[5'h10][28];
+        state_w_grant = _RANDOM[5'h10][29];
+        state_w_releaseack = _RANDOM[5'h10][30];
+        state_w_replResp = _RANDOM[5'h10][31];
+        state_s_rcompack = _RANDOM[5'h11][0];
+        state_s_wcompack = _RANDOM[5'h11][1];
+        state_s_cbwrdata = _RANDOM[5'h11][2];
+        state_s_reissue = _RANDOM[5'h11][3];
+        state_s_dct = _RANDOM[5'h11][4];
+        req_released_chiOpcode = _RANDOM[5'h11][11:5];
+        req_released_likelyShared = _RANDOM[5'h11][12];
+        retryTimes = _RANDOM[5'h11][14:13];
+        backoffTimer = _RANDOM[5'h11][19:15];
+        tgtid_rcompack = _RANDOM[5'h11][30:20];
+        txnid_rcompack = {_RANDOM[5'h11][31], _RANDOM[5'h12][10:0]};
+        tgtid_wcompack = _RANDOM[5'h12][21:11];
+        txnid_wcompack = {_RANDOM[5'h12][31:22], _RANDOM[5'h13][1:0]};
+        srcid_retryack = _RANDOM[5'h13][12:2];
+        pcrdtype = _RANDOM[5'h13][16:13];
+        gotRetryAck = _RANDOM[5'h13][17];
+        gotPCrdGrant = _RANDOM[5'h13][18];
+        tagErr = _RANDOM[5'h13][19];
+        denied = _RANDOM[5'h13][20];
+        corrupt = _RANDOM[5'h13][21];
+        cbWrDataTraceTag = _RANDOM[5'h13][22];
+        mergeA = _RANDOM[5'h13][23];
+        mp_grant_task_merge_task_off = _RANDOM[5'h15][13:8];
+        mp_grant_task_merge_task_alias = _RANDOM[5'h15][14];
+        mp_grant_task_merge_task_vaddr = {_RANDOM[5'h15][31:15], _RANDOM[5'h16][26:0]};
+        mp_grant_task_merge_task_isKeyword = _RANDOM[5'h16][27];
+        mp_grant_task_merge_task_opcode = _RANDOM[5'h16][31:28];
+        mp_grant_task_merge_task_param = _RANDOM[5'h17][2:0];
+        mp_grant_task_merge_task_sourceId = _RANDOM[5'h17][12:6];
+        io_msInfo_bits_blockRefill_REG = _RANDOM[5'h1F][23];
+        io_msInfo_bits_blockRefill_REG_1 = _RANDOM[5'h1F][24];
+        io_msInfo_bits_blockRefill_REG_2 = _RANDOM[5'h1F][25];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        gotT = 1'h0;
+        gotDirty = 1'h0;
+        gotGrantData = 1'h0;
+        probeDirty = 1'h0;
+        releaseDirty = 1'h0;
+        beatCnt = 1'h0;
+        req_valid = 1'h0;
+        req_channel = 3'h0;
+        req_set = 8'h0;
+        req_tag = 34'h0;
+        req_off = 6'h0;
+        req_alias = 1'h0;
+        req_isKeyword = 1'h0;
+        req_opcode = 4'h0;
+        req_param = 3'h0;
+        req_sourceId = 7'h0;
+        req_aliasTask = 1'h0;
+        req_fromL2pft = 1'h0;
+        req_reqSource = 5'h0;
+        req_snpHitRelease = 1'h0;
+        req_snpHitReleaseToInval = 1'h0;
+        req_snpHitReleaseToClean = 1'h0;
+        req_snpHitReleaseWithData = 1'h0;
+        req_snpHitReleaseIdx = 8'h0;
+        req_snpHitReleaseMeta_dirty = 1'h0;
+        req_snpHitReleaseMeta_state = 2'h0;
+        req_snpHitReleaseMeta_clients = 1'h0;
+        req_snpHitReleaseMeta_alias = 1'h0;
+        req_snpHitReleaseMeta_prefetch = 1'h0;
+        req_snpHitReleaseMeta_prefetchSrc = 4'h0;
+        req_snpHitReleaseMeta_accessed = 1'h0;
+        req_snpHitReleaseMeta_tagErr = 1'h0;
+        req_snpHitReleaseMeta_dataErr = 1'h0;
+        req_srcID = 11'h0;
+        req_txnID = 12'h0;
+        req_fwdNID = 11'h0;
+        req_fwdTxnID = 12'h0;
+        req_chiOpcode = 7'h0;
+        req_retToSrc = 1'h0;
+        req_traceTag = 1'h0;
+        dirResult_hit = 1'h0;
+        dirResult_tag = 34'h0;
+        dirResult_set = 8'h0;
+        dirResult_way = 3'h0;
+        dirResult_meta_dirty = 1'h0;
+        dirResult_meta_state = 2'h0;
+        dirResult_meta_clients = 1'h0;
+        dirResult_meta_alias = 1'h0;
+        dirResult_meta_prefetch = 1'h0;
+        dirResult_meta_prefetchSrc = 4'h0;
+        dirResult_meta_accessed = 1'h0;
+        dirResult_meta_tagErr = 1'h0;
+        dirResult_meta_dataErr = 1'h0;
+        state_s_acquire = 1'h1;
+        state_s_rprobe = 1'h1;
+        state_s_pprobe = 1'h1;
+        state_s_release = 1'h1;
+        state_s_probeack = 1'h1;
+        state_s_refill = 1'h1;
+        state_s_retry = 1'h1;
+        state_s_cmoresp = 1'h1;
+        state_s_cmometaw = 1'h1;
+        state_w_rprobeackfirst = 1'h1;
+        state_w_rprobeacklast = 1'h1;
+        state_w_pprobeackfirst = 1'h1;
+        state_w_pprobeacklast = 1'h1;
+        state_w_grantfirst = 1'h1;
+        state_w_grantlast = 1'h1;
+        state_w_grant = 1'h1;
+        state_w_releaseack = 1'h1;
+        state_w_replResp = 1'h1;
+        state_s_rcompack = 1'h1;
+        state_s_wcompack = 1'h1;
+        state_s_cbwrdata = 1'h1;
+        state_s_reissue = 1'h1;
+        state_s_dct = 1'h1;
+        req_released_chiOpcode = 7'h0;
+        req_released_likelyShared = 1'h0;
+        retryTimes = 2'h0;
+        backoffTimer = 5'h0;
+        pcrdtype = 4'h0;
+        gotRetryAck = 1'h0;
+        gotPCrdGrant = 1'h0;
+        tagErr = 1'h0;
+        denied = 1'h0;
+        corrupt = 1'h0;
+        cbWrDataTraceTag = 1'h0;
+        mergeA = 1'h0;
+        mp_grant_task_merge_task_off = 6'h0;
+        mp_grant_task_merge_task_alias = 1'h0;
+        mp_grant_task_merge_task_vaddr = 44'h0;
+        mp_grant_task_merge_task_isKeyword = 1'h0;
+        mp_grant_task_merge_task_opcode = 4'h0;
+        mp_grant_task_merge_task_param = 3'h0;
+        mp_grant_task_merge_task_sourceId = 7'h0;
+        io_msInfo_bits_blockRefill_REG = 1'h0;
+        io_msInfo_bits_blockRefill_REG_1 = 1'h0;
+        io_msInfo_bits_blockRefill_REG_2 = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_status_valid = req_valid;
+  assign io_status_bits_channel = req_channel;
+  assign io_status_bits_set = req_set;
+  assign io_status_bits_reqTag = req_tag;
+  assign io_status_bits_metaTag = dirResult_tag;
+  assign io_status_bits_needsRepl = ~state_s_release;
+  assign io_status_bits_w_c_resp = ~state_w_rprobeacklast | ~state_w_pprobeacklast;
+  assign io_status_bits_will_free = will_free;
+  assign io_status_bits_reqSource = req_reqSource;
+  assign io_msInfo_valid = req_valid;
+  assign io_msInfo_bits_channel = req_channel;
+  assign io_msInfo_bits_set = req_set;
+  assign io_msInfo_bits_way = dirResult_way;
+  assign io_msInfo_bits_reqTag = req_tag;
+  assign io_msInfo_bits_reqSource = req_reqSource;
+  assign io_msInfo_bits_willFree = will_free;
+  assign io_msInfo_bits_aliasTask = req_aliasTask;
+  assign io_msInfo_bits_needRelease = ~state_w_releaseack;
+  assign io_msInfo_bits_blockRefill =
+    ~state_s_release | io_msInfo_bits_blockRefill_REG | io_msInfo_bits_blockRefill_REG_2;
+  assign io_msInfo_bits_meta_dirty = dirResult_meta_dirty;
+  assign io_msInfo_bits_meta_state = dirResult_meta_state;
+  assign io_msInfo_bits_meta_clients = dirResult_meta_clients;
+  assign io_msInfo_bits_meta_alias = dirResult_meta_alias;
+  assign io_msInfo_bits_meta_prefetch = dirResult_meta_prefetch;
+  assign io_msInfo_bits_meta_prefetchSrc = dirResult_meta_prefetchSrc;
+  assign io_msInfo_bits_meta_accessed = dirResult_meta_accessed;
+  assign io_msInfo_bits_meta_tagErr = dirResult_meta_tagErr;
+  assign io_msInfo_bits_meta_dataErr = dirResult_meta_dataErr;
+  assign io_msInfo_bits_metaTag = dirResult_tag;
+  assign io_msInfo_bits_dirHit = dirResult_hit;
+  assign io_msInfo_bits_isAcqOrPrefetch = req_acquire | req_prefetch;
+  assign io_msInfo_bits_isPrefetch = req_prefetch;
+  assign io_msInfo_bits_param = req_param;
+  assign io_msInfo_bits_mergeA = mergeA;
+  assign io_msInfo_bits_w_grantfirst = state_w_grantfirst;
+  assign io_msInfo_bits_w_grantlast = state_w_grantlast;
+  assign io_msInfo_bits_w_grant = state_w_grant;
+  assign io_msInfo_bits_s_release = state_s_release;
+  assign io_msInfo_bits_s_refill = state_s_refill;
+  assign io_msInfo_bits_s_cmoresp = state_s_cmoresp;
+  assign io_msInfo_bits_s_cmometaw = state_s_cmometaw;
+  assign io_msInfo_bits_w_releaseack = state_w_releaseack;
+  assign io_msInfo_bits_w_replResp = state_w_replResp;
+  assign io_msInfo_bits_w_rprobeacklast = state_w_rprobeacklast;
+  assign io_msInfo_bits_replaceData =
+    dirResult_meta_state[1] & dirResult_meta_dirty | isWriteEvictOrEvict;
+  assign io_msInfo_bits_releaseToClean = req_cboClean;
+  assign io_tasks_txreq_valid = io_tasks_txreq_valid_0;
+  assign io_tasks_txreq_bits_tgtID = state_s_reissue ? 11'h0 : srcid_retryack;
+  assign io_tasks_txreq_bits_txnID = io_tasks_txreq_bits_txnID_0;
+  assign io_tasks_txreq_bits_opcode =
+    release_valid2 | _a_task_io_tasks_txreq_bits_opcode_T
+      ? (release_valid2 ? req_released_chiOpcode : {6'h4, ~req_cboClean})
+      : req_cboInval | req_acquirePerm
+          ? (req_cboInval ? 7'hA : 7'hC)
+          : req_needT ? 7'h7 : 7'h26;
+  assign io_tasks_txreq_bits_addr =
+    {release_valid2 ? dirResult_tag : req_tag, req_set, 6'h0};
+  assign io_tasks_txreq_bits_likelyshared = release_valid2 & req_released_likelyShared;
+  assign io_tasks_txreq_bits_allowRetry = state_s_reissue;
+  assign io_tasks_txreq_bits_pCrdType = state_s_reissue ? 4'h0 : pcrdtype;
+  assign io_tasks_txreq_bits_memAttr_allocate = ~release_valid2 | ~isEvict & ~cmo_cbo;
+  assign io_tasks_txreq_bits_expCompAck =
+    release_valid2 ? req_released_chiOpcode == 7'h42 : ~cmo_cbo;
+  assign io_tasks_txrsp_valid = io_tasks_txrsp_valid_0;
+  assign io_tasks_txrsp_bits_tgtID = wcompack_valid ? tgtid_wcompack : tgtid_rcompack;
+  assign io_tasks_txrsp_bits_txnID = wcompack_valid ? txnid_wcompack : txnid_rcompack;
+  assign io_tasks_txrsp_bits_traceTag = req_traceTag;
+  assign io_tasks_source_b_valid = io_tasks_source_b_valid_0;
+  assign io_tasks_source_b_bits_tag = dirResult_tag;
+  assign io_tasks_source_b_bits_set = dirResult_set;
+  assign io_tasks_source_b_bits_param =
+    state_s_pprobe
+      ? ((req_get | req_cboClean) & dirResult_hit
+         & _mp_release_task_mp_release_meta_state_T
+           ? 2'h1
+           : 2'h2)
+      : snpToB ? 2'h1 : {snpToN, 1'h0};
+  assign io_tasks_source_b_bits_alias = dirResult_meta_alias;
+  assign io_tasks_mainpipe_valid =
+    release_valid1 | mp_probeack_valid | mp_grant_valid | mp_cbwrdata_valid | mp_dct_valid
+    | ~state_s_cmometaw;
+  assign io_tasks_mainpipe_bits_channel =
+    _io_tasks_mainpipe_bits_T_2 | _GEN_4 ? req_channel : 3'h0;
+  assign io_tasks_mainpipe_bits_txChannel =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid ? 3'h0 : release_valid1 ? 3'h1 : 3'h4)
+      : mp_probeack_valid ? (doRespData ? 3'h4 : 3'h2) : {mp_dct_valid, 2'h0};
+  assign io_tasks_mainpipe_bits_set = req_set;
+  assign io_tasks_mainpipe_bits_tag = _GEN_5 ? req_tag : dirResult_tag;
+  assign io_tasks_mainpipe_bits_off = _GEN_5 ? req_off : 6'h0;
+  assign io_tasks_mainpipe_bits_alias = _GEN_6 & mp_grant_alias;
+  assign io_tasks_mainpipe_bits_isKeyword = req_isKeyword;
+  assign io_tasks_mainpipe_bits_opcode = _GEN_6 ? _GEN_0 : 4'h0;
+  assign io_tasks_mainpipe_bits_param =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid
+           ? (_mp_grant_task_aliasFinal_T | req_param == 3'h1 | req_param == 3'h2
+                ? 3'h0
+                : req_param == 3'h0 ? _GEN_1 : req_param)
+           : release_valid1
+               ? (cmo_cbo
+                    ? (req_cboClean ? 3'h0 : dirResult_meta_state[1] ? 3'h1 : 3'h2)
+                    : dirResult_meta_state[1] ? 3'h1 : 3'h2)
+               : 3'h0)
+      : 3'h0;
+  assign io_tasks_mainpipe_bits_size = _GEN_6 ? 3'h0 : 3'h6;
+  assign io_tasks_mainpipe_bits_sourceId = _GEN_6 ? req_sourceId : 7'h0;
+  assign io_tasks_mainpipe_bits_denied = _io_tasks_mainpipe_bits_T_2 & denied;
+  assign io_tasks_mainpipe_bits_corrupt = _io_tasks_mainpipe_bits_T_2 & corrupt;
+  assign io_tasks_mainpipe_bits_aliasTask = _GEN_6 & req_aliasTask;
+  assign io_tasks_mainpipe_bits_useProbeData =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid
+           ? dirResult_hit & req_get | req_aliasTask
+             & ~(_mp_grant_task_mp_grant_useProbeData_T_1 & req_needT)
+           : release_valid1 & cmo_cbo)
+      : mp_probeack_valid | mp_dct_valid;
+  assign io_tasks_mainpipe_bits_mshrRetry = _GEN_6 & ~state_s_retry;
+  assign io_tasks_mainpipe_bits_readProbeDataDown =
+    _io_tasks_mainpipe_bits_T_2
+      ? ~mp_grant_valid
+        & (~release_valid1 | cmo_cbo & (req_cboClean | req_cboFlush & isWriteBackFull))
+      : mp_probeack_valid ? doRespData | mp_probeack_dsWen : mp_dct_valid;
+  assign io_tasks_mainpipe_bits_fromL2pft = _GEN_6 & req_fromL2pft;
+  assign io_tasks_mainpipe_bits_dirty = ~_io_tasks_mainpipe_bits_T_2 & hitDirty;
+  assign io_tasks_mainpipe_bits_way = dirResult_way;
+  assign io_tasks_mainpipe_bits_meta_dirty =
+    _io_tasks_mainpipe_bits_T_2
+      ? mp_grant_valid & (gotDirty | hitDirty)
+      : mp_probeack_valid & ~tagErr
+        & (~(~dirResult_hit | ~dirResult_meta_dirty | snpToN | snpToB
+             | _mp_probeack_task_mp_probeack_meta_x5_T_6
+             | (_mp_probeack_task_mp_probeack_meta_x5_T_14
+                | _mp_probeack_task_mp_probeack_meta_x6_T_1) & req_snpHitReleaseToClean)
+           | (_mp_probeack_task_mp_probeack_meta_x5_T_14
+              | _mp_probeack_task_mp_probeack_meta_x6_T_1) & probeDirty);
+  assign io_tasks_mainpipe_bits_meta_state =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid
+           ? (req_get
+                ? {dirResult_hit ? dirResult_meta_state[1] : req_promoteT, 1'h1}
+                : req_promoteT | req_needT ? {1'h1, req_prefetch} : 2'h1)
+           : _GEN_2
+               ? (_mp_release_task_mp_release_meta_state_T ? 2'h3 : dirResult_meta_state)
+               : 2'h0)
+      : mp_probeack_valid
+          ? (_mp_probeack_task_mp_probeack_dsWen_T
+               ? 2'h0
+               : snpToB | _mp_probeack_task_mp_probeack_meta_x6_T_1 & hitWriteClean
+                   ? 2'h1
+                   : dirResult_meta_state)
+          : mp_dct_valid ? 2'h0 : 2'h3;
+  assign io_tasks_mainpipe_bits_meta_clients =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid
+           ? (req_prefetch
+                ? dirResult_hit & dirResult_meta_clients
+                : ~(req_get & (~dirResult_hit | ~dirResult_meta_clients)))
+           : _GEN_2 & dirResult_meta_clients)
+      : mp_probeack_valid
+          ? dirResult_meta_clients & ~snpToN
+          : ~mp_dct_valid & dirResult_meta_clients;
+  assign io_tasks_mainpipe_bits_meta_alias =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid ? mp_grant_alias : _GEN_2 & dirResult_meta_alias)
+      : (mp_probeack_valid | ~mp_dct_valid) & dirResult_meta_alias;
+  assign io_tasks_mainpipe_bits_meta_prefetch =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid
+           ? req_prefetch | dirResult_hit & dirResult_meta_prefetch
+           : _GEN_2 & dirResult_meta_prefetch)
+      : mp_probeack_valid
+          ? ~snpToN & dirResult_meta_prefetch
+          : ~mp_dct_valid & dirResult_meta_prefetch;
+  assign io_tasks_mainpipe_bits_meta_prefetchSrc =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid
+           ? (req_reqSource == 5'h8
+                ? 4'h2
+                : req_reqSource == 5'h9
+                    ? 4'h3
+                    : req_reqSource == 5'hA
+                        ? 4'h1
+                        : req_reqSource == 5'hD
+                            ? 4'h6
+                            : req_reqSource == 5'hB
+                                ? 4'h4
+                                : req_reqSource == 5'hC
+                                    ? 4'h5
+                                    : req_reqSource == 5'hE
+                                        ? 4'h7
+                                        : {req_reqSource == 5'hF, 3'h0})
+           : _GEN_2 ? dirResult_meta_prefetchSrc : 4'h0)
+      : _GEN_4 ? 4'h0 : dirResult_meta_prefetchSrc;
+  assign io_tasks_mainpipe_bits_meta_accessed =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid ? mp_grant_meta_accessed : _GEN_2 & dirResult_meta_accessed)
+      : mp_probeack_valid
+          ? ~snpToN & dirResult_meta_accessed
+          : ~mp_dct_valid & dirResult_meta_accessed;
+  assign io_tasks_mainpipe_bits_meta_tagErr =
+    _io_tasks_mainpipe_bits_T_2
+      ? ~mp_grant_valid & _GEN_2 & dirResult_meta_tagErr
+      : ~_GEN_4 & dirResult_meta_tagErr;
+  assign io_tasks_mainpipe_bits_meta_dataErr =
+    _io_tasks_mainpipe_bits_T_2
+      ? ~mp_grant_valid & _GEN_2 & dirResult_meta_dataErr
+      : ~_GEN_4 & dirResult_meta_dataErr;
+  assign io_tasks_mainpipe_bits_metaWen =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid ? ~cmo_cbo & ~denied : release_valid1 & cmo_cbo)
+      : mp_probeack_valid ? ~req_snpHitReleaseToInval : ~mp_dct_valid;
+  assign io_tasks_mainpipe_bits_tagWen = _GEN_6 & ~cmo_cbo & ~dirResult_hit & ~denied;
+  assign io_tasks_mainpipe_bits_dsWen =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid
+           ? (gotGrantData | probeDirty & (req_get | req_aliasTask)) & ~denied
+           : release_valid1 & (cmo_cbo ? probeDirty : req_opcode != 4'h7))
+      : mp_probeack_valid & mp_probeack_dsWen;
+  assign io_tasks_mainpipe_bits_replTask =
+    _io_tasks_mainpipe_bits_T_2
+    & (mp_grant_valid
+         ? ~dirResult_hit & ~state_w_replResp & ~denied
+         : release_valid1 & ~cmo_cbo);
+  assign io_tasks_mainpipe_bits_cmoTask = cmo_cbo;
+  assign io_tasks_mainpipe_bits_reqSource = req_reqSource;
+  assign io_tasks_mainpipe_bits_mergeA = _GEN_6 & mergeA;
+  assign io_tasks_mainpipe_bits_aMergeTask_off =
+    _GEN_6 ? mp_grant_task_merge_task_off : 6'h0;
+  assign io_tasks_mainpipe_bits_aMergeTask_alias =
+    _GEN_6 & mp_grant_task_merge_task_alias;
+  assign io_tasks_mainpipe_bits_aMergeTask_vaddr =
+    _GEN_6 ? mp_grant_task_merge_task_vaddr : 44'h0;
+  assign io_tasks_mainpipe_bits_aMergeTask_isKeyword =
+    _GEN_6 & mp_grant_task_merge_task_isKeyword;
+  assign io_tasks_mainpipe_bits_aMergeTask_opcode =
+    _GEN_6 ? _GEN[mp_grant_task_merge_task_opcode][2:0] : 3'h0;
+  assign io_tasks_mainpipe_bits_aMergeTask_param =
+    ~_GEN_6 | mp_grant_task_merge_task_param == 3'h1
+    | mp_grant_task_merge_task_param == 3'h2
+      ? 3'h0
+      : mp_grant_task_merge_task_param == 3'h0 ? _GEN_1 : mp_grant_task_merge_task_param;
+  assign io_tasks_mainpipe_bits_aMergeTask_sourceId =
+    _GEN_6 ? mp_grant_task_merge_task_sourceId : 7'h0;
+  assign io_tasks_mainpipe_bits_aMergeTask_meta_dirty = _GEN_6 & (gotDirty | hitDirty);
+  assign io_tasks_mainpipe_bits_aMergeTask_meta_state =
+    _GEN_6
+      ? (req_promoteT | ~(mp_grant_task_merge_task_opcode[2])
+         | mp_grant_task_merge_task_opcode == 4'h5
+         & mp_grant_task_merge_task_param == 3'h1
+         | (mp_grant_task_merge_task_opcode == 4'h6
+            | mp_grant_task_merge_task_opcode == 4'h7) & (|mp_grant_task_merge_task_param)
+           ? 2'h2
+           : 2'h1)
+      : 2'h0;
+  assign io_tasks_mainpipe_bits_aMergeTask_meta_clients =
+    _io_tasks_mainpipe_bits_T_2 & mp_grant_valid;
+  assign io_tasks_mainpipe_bits_aMergeTask_meta_alias =
+    _GEN_6 & mp_grant_task_merge_task_alias;
+  assign io_tasks_mainpipe_bits_aMergeTask_meta_accessed =
+    _io_tasks_mainpipe_bits_T_2 & mp_grant_valid;
+  assign io_tasks_mainpipe_bits_snpHitRelease =
+    ~_io_tasks_mainpipe_bits_T_2 & req_snpHitRelease;
+  assign io_tasks_mainpipe_bits_snpHitReleaseToInval =
+    ~_io_tasks_mainpipe_bits_T_2 & req_snpHitReleaseToInval;
+  assign io_tasks_mainpipe_bits_snpHitReleaseToClean =
+    ~_io_tasks_mainpipe_bits_T_2 & req_snpHitReleaseToClean;
+  assign io_tasks_mainpipe_bits_snpHitReleaseWithData =
+    ~_io_tasks_mainpipe_bits_T_2 & req_snpHitReleaseWithData;
+  assign io_tasks_mainpipe_bits_snpHitReleaseIdx =
+    _io_tasks_mainpipe_bits_T_2 ? 8'h0 : req_snpHitReleaseIdx;
+  assign io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty =
+    ~_GEN_7 & req_snpHitReleaseMeta_dirty;
+  assign io_tasks_mainpipe_bits_snpHitReleaseMeta_state =
+    _GEN_7 ? 2'h0 : req_snpHitReleaseMeta_state;
+  assign io_tasks_mainpipe_bits_snpHitReleaseMeta_clients =
+    ~_GEN_7 & req_snpHitReleaseMeta_clients;
+  assign io_tasks_mainpipe_bits_snpHitReleaseMeta_alias =
+    ~_GEN_7 & req_snpHitReleaseMeta_alias;
+  assign io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch =
+    ~_GEN_7 & req_snpHitReleaseMeta_prefetch;
+  assign io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc =
+    _GEN_7 ? 4'h0 : req_snpHitReleaseMeta_prefetchSrc;
+  assign io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed =
+    ~_GEN_7 & req_snpHitReleaseMeta_accessed;
+  assign io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr =
+    ~_GEN_7 & req_snpHitReleaseMeta_tagErr;
+  assign io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr =
+    ~_GEN_7 & req_snpHitReleaseMeta_dataErr;
+  assign io_tasks_mainpipe_bits_tgtID =
+    _io_tasks_mainpipe_bits_T_2
+      ? (_GEN_3 ? 11'h0 : tgtid_wcompack)
+      : mp_probeack_valid ? req_srcID : mp_dct_valid ? req_fwdNID : 11'h0;
+  assign io_tasks_mainpipe_bits_txnID =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid
+           ? 12'h0
+           : release_valid1 ? io_tasks_txreq_bits_txnID_0 : txnid_wcompack)
+      : mp_probeack_valid ? req_txnID : mp_dct_valid ? req_fwdTxnID : 12'h0;
+  assign io_tasks_mainpipe_bits_homeNID = _GEN_7 | ~mp_dct_valid ? 11'h0 : req_srcID;
+  assign io_tasks_mainpipe_bits_dbID =
+    _io_tasks_mainpipe_bits_T_2 | ~_GEN_4 ? 12'h0 : req_txnID;
+  assign io_tasks_mainpipe_bits_chiOpcode =
+    _io_tasks_mainpipe_bits_T_2
+      ? (mp_grant_valid ? 7'h0 : release_valid1 ? mp_release_chiOpcode : 7'h2)
+      : mp_probeack_valid
+          ? {2'h0,
+             (&_mp_probeack_task_mp_probeack_chiOpcode_T_1)
+               ? 5'h6
+               : _mp_probeack_task_mp_probeack_chiOpcode_T_1 == 2'h1
+                   ? 5'h1
+                   : {1'h0, _mp_probeack_task_mp_probeack_chiOpcode_T_1 == 2'h2, 3'h1}}
+          : {4'h0, mp_dct_valid, 2'h0};
+  assign io_tasks_mainpipe_bits_resp =
+    _io_tasks_mainpipe_bits_T_2
+      ? (_GEN_3 ? 3'h0 : metaChi | {dirResult_meta_dirty, 2'h0})
+      : mp_probeack_valid
+          ? (_mp_probeack_task_mp_probeack_dsWen_T | snpToB
+               ? {2'h0,
+                  ~(_mp_probeack_task_mp_probeack_dsWen_T | req_snpHitReleaseToInval)}
+               : _mp_probeack_task_mp_probeack_meta_x5_T_14
+                 | _mp_probeack_task_mp_probeack_meta_x6_T_1
+                   ? (req_snpHitReleaseToInval
+                        ? 3'h0
+                        : req_snpHitReleaseToClean
+                            ? (req_snpHitReleaseMeta_dirty ? 3'h1 : metaChi)
+                            : dirResult_meta_dirty ? 3'h2 : metaChi)
+                   : (req_chiOpcode == 7'hB | req_chiOpcode == 7'hC
+                      | req_chiOpcode == 7'h10
+                        ? dirResult_meta_dirty
+                        : dirResult_meta_state[1])
+                       ? 3'h2
+                       : metaChi)
+            | {hitDirtyOrWriteDirty & ~tagErr
+                 & (snpToB | _respPassDirty_T_2 | _respPassDirty_T_4
+                    | _mp_probeack_task_mp_probeack_meta_x5_T_6 | _respPassDirty_T_8
+                    | _respPassDirty_T_10) | hitWriteDirty
+                 & _mp_probeack_task_mp_probeack_meta_x6_T_1,
+               2'h0}
+          : mp_dct_valid ? fwdCacheState | _mp_dct_task_mp_dct_resp_T : 3'h0;
+  assign io_tasks_mainpipe_bits_fwdState =
+    _io_tasks_mainpipe_bits_T_2 | ~mp_probeack_valid
+      ? 3'h0
+      : fwdCacheState | _mp_dct_task_mp_dct_resp_T;
+  assign io_tasks_mainpipe_bits_retToSrc =
+    _io_tasks_mainpipe_bits_T_2
+      ? ~mp_grant_valid & req_retToSrc
+      : mp_probeack_valid & req_retToSrc;
+  assign io_tasks_mainpipe_bits_likelyshared =
+    _io_tasks_mainpipe_bits_T_2 & ~mp_grant_valid & release_valid1
+    & mp_release_likelyshared;
+  assign io_tasks_mainpipe_bits_expCompAck =
+    _io_tasks_mainpipe_bits_T_2 & ~mp_grant_valid & release_valid1 & isWriteEvictOrEvict;
+  assign io_tasks_mainpipe_bits_allowRetry =
+    _io_tasks_mainpipe_bits_T_2 & ~mp_grant_valid & release_valid1 & state_s_reissue;
+  assign io_tasks_mainpipe_bits_memAttr_allocate =
+    _io_tasks_mainpipe_bits_T_2 & ~mp_grant_valid & release_valid1 & ~cmo_cbo & ~isEvict;
+  assign io_tasks_mainpipe_bits_memAttr_cacheable =
+    _io_tasks_mainpipe_bits_T_2 & ~mp_grant_valid & release_valid1;
+  assign io_tasks_mainpipe_bits_memAttr_ewa =
+    _io_tasks_mainpipe_bits_T_2 & ~mp_grant_valid & release_valid1;
+  assign io_tasks_mainpipe_bits_traceTag =
+    _io_tasks_mainpipe_bits_T_2 ? ~_GEN_3 & cbWrDataTraceTag : _GEN_4 & req_traceTag;
+  assign io_nestedwbData = nestedwb_match & io_nestedwb_c_set_dirty;
+  assign io_pCrd_query_valid = gotRetryAck & ~gotPCrdGrant;
+  assign io_pCrd_query_bits_pCrdType = pcrdtype;
+  assign io_pCrd_query_bits_srcID = srcid_retryack;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MSHRBuffer.sv b/flow/designs/src/xiangshan_coupledl2/deps/MSHRBuffer.sv
new file mode 100644
index 0000000000..0336ef6084
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MSHRBuffer.sv
@@ -0,0 +1,607 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MSHRBuffer(
+  input          clock,
+  input          reset,
+  input          io_r_valid,
+  input  [7:0]   io_r_bits_id,
+  output [511:0] io_resp_data_data,
+  input          io_w_0_valid,
+  input  [7:0]   io_w_0_bits_id,
+  input  [511:0] io_w_0_bits_data_data,
+  input  [1:0]   io_w_0_bits_beatMask,
+  input          io_w_1_valid,
+  input  [7:0]   io_w_1_bits_id,
+  input  [511:0] io_w_1_bits_data_data
+);
+
+  reg  [255:0]       buffer_0_0;
+  reg  [255:0]       buffer_0_1;
+  reg  [255:0]       buffer_1_0;
+  reg  [255:0]       buffer_1_1;
+  reg  [255:0]       buffer_2_0;
+  reg  [255:0]       buffer_2_1;
+  reg  [255:0]       buffer_3_0;
+  reg  [255:0]       buffer_3_1;
+  reg  [255:0]       buffer_4_0;
+  reg  [255:0]       buffer_4_1;
+  reg  [255:0]       buffer_5_0;
+  reg  [255:0]       buffer_5_1;
+  reg  [255:0]       buffer_6_0;
+  reg  [255:0]       buffer_6_1;
+  reg  [255:0]       buffer_7_0;
+  reg  [255:0]       buffer_7_1;
+  reg  [255:0]       buffer_8_0;
+  reg  [255:0]       buffer_8_1;
+  reg  [255:0]       buffer_9_0;
+  reg  [255:0]       buffer_9_1;
+  reg  [255:0]       buffer_10_0;
+  reg  [255:0]       buffer_10_1;
+  reg  [255:0]       buffer_11_0;
+  reg  [255:0]       buffer_11_1;
+  reg  [255:0]       buffer_12_0;
+  reg  [255:0]       buffer_12_1;
+  reg  [255:0]       buffer_13_0;
+  reg  [255:0]       buffer_13_1;
+  reg  [255:0]       buffer_14_0;
+  reg  [255:0]       buffer_14_1;
+  reg  [255:0]       buffer_15_0;
+  reg  [255:0]       buffer_15_1;
+  reg  [511:0]       io_resp_data_data_r;
+  wire               _w_beatSel_T = io_w_0_valid & io_w_0_bits_id == 8'h0;
+  wire [1:0]         wens = {io_w_1_valid & io_w_1_bits_id == 8'h0, _w_beatSel_T};
+  wire [511:0]       w_data_data =
+    _w_beatSel_T ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel = _w_beatSel_T ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_2 = io_w_0_valid & io_w_0_bits_id == 8'h1;
+  wire [1:0]         wens_1 = {io_w_1_valid & io_w_1_bits_id == 8'h1, _w_beatSel_T_2};
+  wire [511:0]       w_data_1_data =
+    _w_beatSel_T_2 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_1 = _w_beatSel_T_2 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_4 = io_w_0_valid & io_w_0_bits_id == 8'h2;
+  wire [1:0]         wens_2 = {io_w_1_valid & io_w_1_bits_id == 8'h2, _w_beatSel_T_4};
+  wire [511:0]       w_data_2_data =
+    _w_beatSel_T_4 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_2 = _w_beatSel_T_4 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_6 = io_w_0_valid & io_w_0_bits_id == 8'h3;
+  wire [1:0]         wens_3 = {io_w_1_valid & io_w_1_bits_id == 8'h3, _w_beatSel_T_6};
+  wire [511:0]       w_data_3_data =
+    _w_beatSel_T_6 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_3 = _w_beatSel_T_6 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_8 = io_w_0_valid & io_w_0_bits_id == 8'h4;
+  wire [1:0]         wens_4 = {io_w_1_valid & io_w_1_bits_id == 8'h4, _w_beatSel_T_8};
+  wire [511:0]       w_data_4_data =
+    _w_beatSel_T_8 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_4 = _w_beatSel_T_8 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_10 = io_w_0_valid & io_w_0_bits_id == 8'h5;
+  wire [1:0]         wens_5 = {io_w_1_valid & io_w_1_bits_id == 8'h5, _w_beatSel_T_10};
+  wire [511:0]       w_data_5_data =
+    _w_beatSel_T_10 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_5 = _w_beatSel_T_10 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_12 = io_w_0_valid & io_w_0_bits_id == 8'h6;
+  wire [1:0]         wens_6 = {io_w_1_valid & io_w_1_bits_id == 8'h6, _w_beatSel_T_12};
+  wire [511:0]       w_data_6_data =
+    _w_beatSel_T_12 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_6 = _w_beatSel_T_12 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_14 = io_w_0_valid & io_w_0_bits_id == 8'h7;
+  wire [1:0]         wens_7 = {io_w_1_valid & io_w_1_bits_id == 8'h7, _w_beatSel_T_14};
+  wire [511:0]       w_data_7_data =
+    _w_beatSel_T_14 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_7 = _w_beatSel_T_14 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_16 = io_w_0_valid & io_w_0_bits_id == 8'h8;
+  wire [1:0]         wens_8 = {io_w_1_valid & io_w_1_bits_id == 8'h8, _w_beatSel_T_16};
+  wire [511:0]       w_data_8_data =
+    _w_beatSel_T_16 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_8 = _w_beatSel_T_16 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_18 = io_w_0_valid & io_w_0_bits_id == 8'h9;
+  wire [1:0]         wens_9 = {io_w_1_valid & io_w_1_bits_id == 8'h9, _w_beatSel_T_18};
+  wire [511:0]       w_data_9_data =
+    _w_beatSel_T_18 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_9 = _w_beatSel_T_18 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_20 = io_w_0_valid & io_w_0_bits_id == 8'hA;
+  wire [1:0]         wens_10 = {io_w_1_valid & io_w_1_bits_id == 8'hA, _w_beatSel_T_20};
+  wire [511:0]       w_data_10_data =
+    _w_beatSel_T_20 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_10 = _w_beatSel_T_20 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_22 = io_w_0_valid & io_w_0_bits_id == 8'hB;
+  wire [1:0]         wens_11 = {io_w_1_valid & io_w_1_bits_id == 8'hB, _w_beatSel_T_22};
+  wire [511:0]       w_data_11_data =
+    _w_beatSel_T_22 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_11 = _w_beatSel_T_22 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_24 = io_w_0_valid & io_w_0_bits_id == 8'hC;
+  wire [1:0]         wens_12 = {io_w_1_valid & io_w_1_bits_id == 8'hC, _w_beatSel_T_24};
+  wire [511:0]       w_data_12_data =
+    _w_beatSel_T_24 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_12 = _w_beatSel_T_24 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_26 = io_w_0_valid & io_w_0_bits_id == 8'hD;
+  wire [1:0]         wens_13 = {io_w_1_valid & io_w_1_bits_id == 8'hD, _w_beatSel_T_26};
+  wire [511:0]       w_data_13_data =
+    _w_beatSel_T_26 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_13 = _w_beatSel_T_26 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_28 = io_w_0_valid & io_w_0_bits_id == 8'hE;
+  wire [1:0]         wens_14 = {io_w_1_valid & io_w_1_bits_id == 8'hE, _w_beatSel_T_28};
+  wire [511:0]       w_data_14_data =
+    _w_beatSel_T_28 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_14 = _w_beatSel_T_28 ? io_w_0_bits_beatMask : 2'h3;
+  wire               _w_beatSel_T_30 = io_w_0_valid & io_w_0_bits_id == 8'hF;
+  wire [1:0]         wens_15 = {io_w_1_valid & io_w_1_bits_id == 8'hF, _w_beatSel_T_30};
+  wire [511:0]       w_data_15_data =
+    _w_beatSel_T_30 ? io_w_0_bits_data_data : io_w_1_bits_data_data;
+  wire [1:0]         w_beatSel_15 = _w_beatSel_T_30 ? io_w_0_bits_beatMask : 2'h3;
+  always @(posedge clock) begin
+    if ((|wens) & w_beatSel[0])
+      buffer_0_0 <= w_data_data[255:0];
+    if ((|wens) & w_beatSel[1])
+      buffer_0_1 <= w_data_data[511:256];
+    if ((|wens_1) & w_beatSel_1[0])
+      buffer_1_0 <= w_data_1_data[255:0];
+    if ((|wens_1) & w_beatSel_1[1])
+      buffer_1_1 <= w_data_1_data[511:256];
+    if ((|wens_2) & w_beatSel_2[0])
+      buffer_2_0 <= w_data_2_data[255:0];
+    if ((|wens_2) & w_beatSel_2[1])
+      buffer_2_1 <= w_data_2_data[511:256];
+    if ((|wens_3) & w_beatSel_3[0])
+      buffer_3_0 <= w_data_3_data[255:0];
+    if ((|wens_3) & w_beatSel_3[1])
+      buffer_3_1 <= w_data_3_data[511:256];
+    if ((|wens_4) & w_beatSel_4[0])
+      buffer_4_0 <= w_data_4_data[255:0];
+    if ((|wens_4) & w_beatSel_4[1])
+      buffer_4_1 <= w_data_4_data[511:256];
+    if ((|wens_5) & w_beatSel_5[0])
+      buffer_5_0 <= w_data_5_data[255:0];
+    if ((|wens_5) & w_beatSel_5[1])
+      buffer_5_1 <= w_data_5_data[511:256];
+    if ((|wens_6) & w_beatSel_6[0])
+      buffer_6_0 <= w_data_6_data[255:0];
+    if ((|wens_6) & w_beatSel_6[1])
+      buffer_6_1 <= w_data_6_data[511:256];
+    if ((|wens_7) & w_beatSel_7[0])
+      buffer_7_0 <= w_data_7_data[255:0];
+    if ((|wens_7) & w_beatSel_7[1])
+      buffer_7_1 <= w_data_7_data[511:256];
+    if ((|wens_8) & w_beatSel_8[0])
+      buffer_8_0 <= w_data_8_data[255:0];
+    if ((|wens_8) & w_beatSel_8[1])
+      buffer_8_1 <= w_data_8_data[511:256];
+    if ((|wens_9) & w_beatSel_9[0])
+      buffer_9_0 <= w_data_9_data[255:0];
+    if ((|wens_9) & w_beatSel_9[1])
+      buffer_9_1 <= w_data_9_data[511:256];
+    if ((|wens_10) & w_beatSel_10[0])
+      buffer_10_0 <= w_data_10_data[255:0];
+    if ((|wens_10) & w_beatSel_10[1])
+      buffer_10_1 <= w_data_10_data[511:256];
+    if ((|wens_11) & w_beatSel_11[0])
+      buffer_11_0 <= w_data_11_data[255:0];
+    if ((|wens_11) & w_beatSel_11[1])
+      buffer_11_1 <= w_data_11_data[511:256];
+    if ((|wens_12) & w_beatSel_12[0])
+      buffer_12_0 <= w_data_12_data[255:0];
+    if ((|wens_12) & w_beatSel_12[1])
+      buffer_12_1 <= w_data_12_data[511:256];
+    if ((|wens_13) & w_beatSel_13[0])
+      buffer_13_0 <= w_data_13_data[255:0];
+    if ((|wens_13) & w_beatSel_13[1])
+      buffer_13_1 <= w_data_13_data[511:256];
+    if ((|wens_14) & w_beatSel_14[0])
+      buffer_14_0 <= w_data_14_data[255:0];
+    if ((|wens_14) & w_beatSel_14[1])
+      buffer_14_1 <= w_data_14_data[511:256];
+    if ((|wens_15) & w_beatSel_15[0])
+      buffer_15_0 <= w_data_15_data[255:0];
+    if ((|wens_15) & w_beatSel_15[1])
+      buffer_15_1 <= w_data_15_data[511:256];
+  end // always @(posedge)
+  wire [15:0][255:0] _GEN =
+    {{buffer_15_1},
+     {buffer_14_1},
+     {buffer_13_1},
+     {buffer_12_1},
+     {buffer_11_1},
+     {buffer_10_1},
+     {buffer_9_1},
+     {buffer_8_1},
+     {buffer_7_1},
+     {buffer_6_1},
+     {buffer_5_1},
+     {buffer_4_1},
+     {buffer_3_1},
+     {buffer_2_1},
+     {buffer_1_1},
+     {buffer_0_1}};
+  wire [15:0][255:0] _GEN_0 =
+    {{buffer_15_0},
+     {buffer_14_0},
+     {buffer_13_0},
+     {buffer_12_0},
+     {buffer_11_0},
+     {buffer_10_0},
+     {buffer_9_0},
+     {buffer_8_0},
+     {buffer_7_0},
+     {buffer_6_0},
+     {buffer_5_0},
+     {buffer_4_0},
+     {buffer_3_0},
+     {buffer_2_0},
+     {buffer_1_0},
+     {buffer_0_0}};
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      io_resp_data_data_r <= 512'h0;
+    else if (io_r_valid)
+      io_resp_data_data_r <= {_GEN[io_r_bits_id[3:0]], _GEN_0[io_r_bits_id[3:0]]};
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:271];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [8:0] i = 9'h0; i < 9'h110; i += 9'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        buffer_0_0 =
+          {_RANDOM[9'h0],
+           _RANDOM[9'h1],
+           _RANDOM[9'h2],
+           _RANDOM[9'h3],
+           _RANDOM[9'h4],
+           _RANDOM[9'h5],
+           _RANDOM[9'h6],
+           _RANDOM[9'h7]};
+        buffer_0_1 =
+          {_RANDOM[9'h8],
+           _RANDOM[9'h9],
+           _RANDOM[9'hA],
+           _RANDOM[9'hB],
+           _RANDOM[9'hC],
+           _RANDOM[9'hD],
+           _RANDOM[9'hE],
+           _RANDOM[9'hF]};
+        buffer_1_0 =
+          {_RANDOM[9'h10],
+           _RANDOM[9'h11],
+           _RANDOM[9'h12],
+           _RANDOM[9'h13],
+           _RANDOM[9'h14],
+           _RANDOM[9'h15],
+           _RANDOM[9'h16],
+           _RANDOM[9'h17]};
+        buffer_1_1 =
+          {_RANDOM[9'h18],
+           _RANDOM[9'h19],
+           _RANDOM[9'h1A],
+           _RANDOM[9'h1B],
+           _RANDOM[9'h1C],
+           _RANDOM[9'h1D],
+           _RANDOM[9'h1E],
+           _RANDOM[9'h1F]};
+        buffer_2_0 =
+          {_RANDOM[9'h20],
+           _RANDOM[9'h21],
+           _RANDOM[9'h22],
+           _RANDOM[9'h23],
+           _RANDOM[9'h24],
+           _RANDOM[9'h25],
+           _RANDOM[9'h26],
+           _RANDOM[9'h27]};
+        buffer_2_1 =
+          {_RANDOM[9'h28],
+           _RANDOM[9'h29],
+           _RANDOM[9'h2A],
+           _RANDOM[9'h2B],
+           _RANDOM[9'h2C],
+           _RANDOM[9'h2D],
+           _RANDOM[9'h2E],
+           _RANDOM[9'h2F]};
+        buffer_3_0 =
+          {_RANDOM[9'h30],
+           _RANDOM[9'h31],
+           _RANDOM[9'h32],
+           _RANDOM[9'h33],
+           _RANDOM[9'h34],
+           _RANDOM[9'h35],
+           _RANDOM[9'h36],
+           _RANDOM[9'h37]};
+        buffer_3_1 =
+          {_RANDOM[9'h38],
+           _RANDOM[9'h39],
+           _RANDOM[9'h3A],
+           _RANDOM[9'h3B],
+           _RANDOM[9'h3C],
+           _RANDOM[9'h3D],
+           _RANDOM[9'h3E],
+           _RANDOM[9'h3F]};
+        buffer_4_0 =
+          {_RANDOM[9'h40],
+           _RANDOM[9'h41],
+           _RANDOM[9'h42],
+           _RANDOM[9'h43],
+           _RANDOM[9'h44],
+           _RANDOM[9'h45],
+           _RANDOM[9'h46],
+           _RANDOM[9'h47]};
+        buffer_4_1 =
+          {_RANDOM[9'h48],
+           _RANDOM[9'h49],
+           _RANDOM[9'h4A],
+           _RANDOM[9'h4B],
+           _RANDOM[9'h4C],
+           _RANDOM[9'h4D],
+           _RANDOM[9'h4E],
+           _RANDOM[9'h4F]};
+        buffer_5_0 =
+          {_RANDOM[9'h50],
+           _RANDOM[9'h51],
+           _RANDOM[9'h52],
+           _RANDOM[9'h53],
+           _RANDOM[9'h54],
+           _RANDOM[9'h55],
+           _RANDOM[9'h56],
+           _RANDOM[9'h57]};
+        buffer_5_1 =
+          {_RANDOM[9'h58],
+           _RANDOM[9'h59],
+           _RANDOM[9'h5A],
+           _RANDOM[9'h5B],
+           _RANDOM[9'h5C],
+           _RANDOM[9'h5D],
+           _RANDOM[9'h5E],
+           _RANDOM[9'h5F]};
+        buffer_6_0 =
+          {_RANDOM[9'h60],
+           _RANDOM[9'h61],
+           _RANDOM[9'h62],
+           _RANDOM[9'h63],
+           _RANDOM[9'h64],
+           _RANDOM[9'h65],
+           _RANDOM[9'h66],
+           _RANDOM[9'h67]};
+        buffer_6_1 =
+          {_RANDOM[9'h68],
+           _RANDOM[9'h69],
+           _RANDOM[9'h6A],
+           _RANDOM[9'h6B],
+           _RANDOM[9'h6C],
+           _RANDOM[9'h6D],
+           _RANDOM[9'h6E],
+           _RANDOM[9'h6F]};
+        buffer_7_0 =
+          {_RANDOM[9'h70],
+           _RANDOM[9'h71],
+           _RANDOM[9'h72],
+           _RANDOM[9'h73],
+           _RANDOM[9'h74],
+           _RANDOM[9'h75],
+           _RANDOM[9'h76],
+           _RANDOM[9'h77]};
+        buffer_7_1 =
+          {_RANDOM[9'h78],
+           _RANDOM[9'h79],
+           _RANDOM[9'h7A],
+           _RANDOM[9'h7B],
+           _RANDOM[9'h7C],
+           _RANDOM[9'h7D],
+           _RANDOM[9'h7E],
+           _RANDOM[9'h7F]};
+        buffer_8_0 =
+          {_RANDOM[9'h80],
+           _RANDOM[9'h81],
+           _RANDOM[9'h82],
+           _RANDOM[9'h83],
+           _RANDOM[9'h84],
+           _RANDOM[9'h85],
+           _RANDOM[9'h86],
+           _RANDOM[9'h87]};
+        buffer_8_1 =
+          {_RANDOM[9'h88],
+           _RANDOM[9'h89],
+           _RANDOM[9'h8A],
+           _RANDOM[9'h8B],
+           _RANDOM[9'h8C],
+           _RANDOM[9'h8D],
+           _RANDOM[9'h8E],
+           _RANDOM[9'h8F]};
+        buffer_9_0 =
+          {_RANDOM[9'h90],
+           _RANDOM[9'h91],
+           _RANDOM[9'h92],
+           _RANDOM[9'h93],
+           _RANDOM[9'h94],
+           _RANDOM[9'h95],
+           _RANDOM[9'h96],
+           _RANDOM[9'h97]};
+        buffer_9_1 =
+          {_RANDOM[9'h98],
+           _RANDOM[9'h99],
+           _RANDOM[9'h9A],
+           _RANDOM[9'h9B],
+           _RANDOM[9'h9C],
+           _RANDOM[9'h9D],
+           _RANDOM[9'h9E],
+           _RANDOM[9'h9F]};
+        buffer_10_0 =
+          {_RANDOM[9'hA0],
+           _RANDOM[9'hA1],
+           _RANDOM[9'hA2],
+           _RANDOM[9'hA3],
+           _RANDOM[9'hA4],
+           _RANDOM[9'hA5],
+           _RANDOM[9'hA6],
+           _RANDOM[9'hA7]};
+        buffer_10_1 =
+          {_RANDOM[9'hA8],
+           _RANDOM[9'hA9],
+           _RANDOM[9'hAA],
+           _RANDOM[9'hAB],
+           _RANDOM[9'hAC],
+           _RANDOM[9'hAD],
+           _RANDOM[9'hAE],
+           _RANDOM[9'hAF]};
+        buffer_11_0 =
+          {_RANDOM[9'hB0],
+           _RANDOM[9'hB1],
+           _RANDOM[9'hB2],
+           _RANDOM[9'hB3],
+           _RANDOM[9'hB4],
+           _RANDOM[9'hB5],
+           _RANDOM[9'hB6],
+           _RANDOM[9'hB7]};
+        buffer_11_1 =
+          {_RANDOM[9'hB8],
+           _RANDOM[9'hB9],
+           _RANDOM[9'hBA],
+           _RANDOM[9'hBB],
+           _RANDOM[9'hBC],
+           _RANDOM[9'hBD],
+           _RANDOM[9'hBE],
+           _RANDOM[9'hBF]};
+        buffer_12_0 =
+          {_RANDOM[9'hC0],
+           _RANDOM[9'hC1],
+           _RANDOM[9'hC2],
+           _RANDOM[9'hC3],
+           _RANDOM[9'hC4],
+           _RANDOM[9'hC5],
+           _RANDOM[9'hC6],
+           _RANDOM[9'hC7]};
+        buffer_12_1 =
+          {_RANDOM[9'hC8],
+           _RANDOM[9'hC9],
+           _RANDOM[9'hCA],
+           _RANDOM[9'hCB],
+           _RANDOM[9'hCC],
+           _RANDOM[9'hCD],
+           _RANDOM[9'hCE],
+           _RANDOM[9'hCF]};
+        buffer_13_0 =
+          {_RANDOM[9'hD0],
+           _RANDOM[9'hD1],
+           _RANDOM[9'hD2],
+           _RANDOM[9'hD3],
+           _RANDOM[9'hD4],
+           _RANDOM[9'hD5],
+           _RANDOM[9'hD6],
+           _RANDOM[9'hD7]};
+        buffer_13_1 =
+          {_RANDOM[9'hD8],
+           _RANDOM[9'hD9],
+           _RANDOM[9'hDA],
+           _RANDOM[9'hDB],
+           _RANDOM[9'hDC],
+           _RANDOM[9'hDD],
+           _RANDOM[9'hDE],
+           _RANDOM[9'hDF]};
+        buffer_14_0 =
+          {_RANDOM[9'hE0],
+           _RANDOM[9'hE1],
+           _RANDOM[9'hE2],
+           _RANDOM[9'hE3],
+           _RANDOM[9'hE4],
+           _RANDOM[9'hE5],
+           _RANDOM[9'hE6],
+           _RANDOM[9'hE7]};
+        buffer_14_1 =
+          {_RANDOM[9'hE8],
+           _RANDOM[9'hE9],
+           _RANDOM[9'hEA],
+           _RANDOM[9'hEB],
+           _RANDOM[9'hEC],
+           _RANDOM[9'hED],
+           _RANDOM[9'hEE],
+           _RANDOM[9'hEF]};
+        buffer_15_0 =
+          {_RANDOM[9'hF0],
+           _RANDOM[9'hF1],
+           _RANDOM[9'hF2],
+           _RANDOM[9'hF3],
+           _RANDOM[9'hF4],
+           _RANDOM[9'hF5],
+           _RANDOM[9'hF6],
+           _RANDOM[9'hF7]};
+        buffer_15_1 =
+          {_RANDOM[9'hF8],
+           _RANDOM[9'hF9],
+           _RANDOM[9'hFA],
+           _RANDOM[9'hFB],
+           _RANDOM[9'hFC],
+           _RANDOM[9'hFD],
+           _RANDOM[9'hFE],
+           _RANDOM[9'hFF]};
+        io_resp_data_data_r =
+          {_RANDOM[9'h100],
+           _RANDOM[9'h101],
+           _RANDOM[9'h102],
+           _RANDOM[9'h103],
+           _RANDOM[9'h104],
+           _RANDOM[9'h105],
+           _RANDOM[9'h106],
+           _RANDOM[9'h107],
+           _RANDOM[9'h108],
+           _RANDOM[9'h109],
+           _RANDOM[9'h10A],
+           _RANDOM[9'h10B],
+           _RANDOM[9'h10C],
+           _RANDOM[9'h10D],
+           _RANDOM[9'h10E],
+           _RANDOM[9'h10F]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        io_resp_data_data_r = 512'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_resp_data_data = io_resp_data_data_r;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MSHRBuffer_1.sv b/flow/designs/src/xiangshan_coupledl2/deps/MSHRBuffer_1.sv
new file mode 100644
index 0000000000..f83f22e3b2
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MSHRBuffer_1.sv
@@ -0,0 +1,625 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MSHRBuffer_1(
+  input          clock,
+  input          reset,
+  input          io_r_valid,
+  input  [7:0]   io_r_bits_id,
+  output [511:0] io_resp_data_data,
+  input          io_w_0_valid,
+  input  [7:0]   io_w_0_bits_id,
+  input  [511:0] io_w_0_bits_data_data,
+  input          io_w_1_valid,
+  input  [7:0]   io_w_1_bits_id,
+  input  [511:0] io_w_1_bits_data_data,
+  input          io_w_2_valid,
+  input  [7:0]   io_w_2_bits_id,
+  input  [511:0] io_w_2_bits_data_data
+);
+
+  reg  [255:0]       buffer_0_0;
+  reg  [255:0]       buffer_0_1;
+  reg  [255:0]       buffer_1_0;
+  reg  [255:0]       buffer_1_1;
+  reg  [255:0]       buffer_2_0;
+  reg  [255:0]       buffer_2_1;
+  reg  [255:0]       buffer_3_0;
+  reg  [255:0]       buffer_3_1;
+  reg  [255:0]       buffer_4_0;
+  reg  [255:0]       buffer_4_1;
+  reg  [255:0]       buffer_5_0;
+  reg  [255:0]       buffer_5_1;
+  reg  [255:0]       buffer_6_0;
+  reg  [255:0]       buffer_6_1;
+  reg  [255:0]       buffer_7_0;
+  reg  [255:0]       buffer_7_1;
+  reg  [255:0]       buffer_8_0;
+  reg  [255:0]       buffer_8_1;
+  reg  [255:0]       buffer_9_0;
+  reg  [255:0]       buffer_9_1;
+  reg  [255:0]       buffer_10_0;
+  reg  [255:0]       buffer_10_1;
+  reg  [255:0]       buffer_11_0;
+  reg  [255:0]       buffer_11_1;
+  reg  [255:0]       buffer_12_0;
+  reg  [255:0]       buffer_12_1;
+  reg  [255:0]       buffer_13_0;
+  reg  [255:0]       buffer_13_1;
+  reg  [255:0]       buffer_14_0;
+  reg  [255:0]       buffer_14_1;
+  reg  [255:0]       buffer_15_0;
+  reg  [255:0]       buffer_15_1;
+  reg  [511:0]       io_resp_data_data_r;
+  wire               _w_beatSel_T = io_w_0_valid & io_w_0_bits_id == 8'h0;
+  wire               _w_beatSel_T_1 = io_w_1_valid & io_w_1_bits_id == 8'h0;
+  wire               _w_beatSel_T_4 = io_w_0_valid & io_w_0_bits_id == 8'h1;
+  wire               _w_beatSel_T_5 = io_w_1_valid & io_w_1_bits_id == 8'h1;
+  wire               _w_beatSel_T_8 = io_w_0_valid & io_w_0_bits_id == 8'h2;
+  wire               _w_beatSel_T_9 = io_w_1_valid & io_w_1_bits_id == 8'h2;
+  wire               _w_beatSel_T_12 = io_w_0_valid & io_w_0_bits_id == 8'h3;
+  wire               _w_beatSel_T_13 = io_w_1_valid & io_w_1_bits_id == 8'h3;
+  wire               _w_beatSel_T_16 = io_w_0_valid & io_w_0_bits_id == 8'h4;
+  wire               _w_beatSel_T_17 = io_w_1_valid & io_w_1_bits_id == 8'h4;
+  wire               _w_beatSel_T_20 = io_w_0_valid & io_w_0_bits_id == 8'h5;
+  wire               _w_beatSel_T_21 = io_w_1_valid & io_w_1_bits_id == 8'h5;
+  wire               _w_beatSel_T_24 = io_w_0_valid & io_w_0_bits_id == 8'h6;
+  wire               _w_beatSel_T_25 = io_w_1_valid & io_w_1_bits_id == 8'h6;
+  wire               _w_beatSel_T_28 = io_w_0_valid & io_w_0_bits_id == 8'h7;
+  wire               _w_beatSel_T_29 = io_w_1_valid & io_w_1_bits_id == 8'h7;
+  wire               _w_beatSel_T_32 = io_w_0_valid & io_w_0_bits_id == 8'h8;
+  wire               _w_beatSel_T_33 = io_w_1_valid & io_w_1_bits_id == 8'h8;
+  wire               _w_beatSel_T_36 = io_w_0_valid & io_w_0_bits_id == 8'h9;
+  wire               _w_beatSel_T_37 = io_w_1_valid & io_w_1_bits_id == 8'h9;
+  wire               _w_beatSel_T_40 = io_w_0_valid & io_w_0_bits_id == 8'hA;
+  wire               _w_beatSel_T_41 = io_w_1_valid & io_w_1_bits_id == 8'hA;
+  wire               _w_beatSel_T_44 = io_w_0_valid & io_w_0_bits_id == 8'hB;
+  wire               _w_beatSel_T_45 = io_w_1_valid & io_w_1_bits_id == 8'hB;
+  wire               _w_beatSel_T_48 = io_w_0_valid & io_w_0_bits_id == 8'hC;
+  wire               _w_beatSel_T_49 = io_w_1_valid & io_w_1_bits_id == 8'hC;
+  wire               _w_beatSel_T_52 = io_w_0_valid & io_w_0_bits_id == 8'hD;
+  wire               _w_beatSel_T_53 = io_w_1_valid & io_w_1_bits_id == 8'hD;
+  wire               _w_beatSel_T_56 = io_w_0_valid & io_w_0_bits_id == 8'hE;
+  wire               _w_beatSel_T_57 = io_w_1_valid & io_w_1_bits_id == 8'hE;
+  wire               _w_beatSel_T_60 = io_w_0_valid & io_w_0_bits_id == 8'hF;
+  wire               _w_beatSel_T_61 = io_w_1_valid & io_w_1_bits_id == 8'hF;
+  wire [511:0]       w_data_data =
+    _w_beatSel_T
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_1 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_1_data =
+    _w_beatSel_T_4
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_5 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_2_data =
+    _w_beatSel_T_8
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_9 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_3_data =
+    _w_beatSel_T_12
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_13 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_4_data =
+    _w_beatSel_T_16
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_17 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_5_data =
+    _w_beatSel_T_20
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_21 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_6_data =
+    _w_beatSel_T_24
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_25 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_7_data =
+    _w_beatSel_T_28
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_29 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_8_data =
+    _w_beatSel_T_32
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_33 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_9_data =
+    _w_beatSel_T_36
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_37 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_10_data =
+    _w_beatSel_T_40
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_41 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_11_data =
+    _w_beatSel_T_44
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_45 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_12_data =
+    _w_beatSel_T_48
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_49 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_13_data =
+    _w_beatSel_T_52
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_53 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_14_data =
+    _w_beatSel_T_56
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_57 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  wire [511:0]       w_data_15_data =
+    _w_beatSel_T_60
+      ? io_w_0_bits_data_data
+      : _w_beatSel_T_61 ? io_w_1_bits_data_data : io_w_2_bits_data_data;
+  always @(posedge clock) begin
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h0, _w_beatSel_T_1, _w_beatSel_T}) begin
+      buffer_0_0 <= w_data_data[255:0];
+      buffer_0_1 <= w_data_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h1, _w_beatSel_T_5, _w_beatSel_T_4}) begin
+      buffer_1_0 <= w_data_1_data[255:0];
+      buffer_1_1 <= w_data_1_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h2, _w_beatSel_T_9, _w_beatSel_T_8}) begin
+      buffer_2_0 <= w_data_2_data[255:0];
+      buffer_2_1 <= w_data_2_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h3, _w_beatSel_T_13, _w_beatSel_T_12}) begin
+      buffer_3_0 <= w_data_3_data[255:0];
+      buffer_3_1 <= w_data_3_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h4, _w_beatSel_T_17, _w_beatSel_T_16}) begin
+      buffer_4_0 <= w_data_4_data[255:0];
+      buffer_4_1 <= w_data_4_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h5, _w_beatSel_T_21, _w_beatSel_T_20}) begin
+      buffer_5_0 <= w_data_5_data[255:0];
+      buffer_5_1 <= w_data_5_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h6, _w_beatSel_T_25, _w_beatSel_T_24}) begin
+      buffer_6_0 <= w_data_6_data[255:0];
+      buffer_6_1 <= w_data_6_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h7, _w_beatSel_T_29, _w_beatSel_T_28}) begin
+      buffer_7_0 <= w_data_7_data[255:0];
+      buffer_7_1 <= w_data_7_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h8, _w_beatSel_T_33, _w_beatSel_T_32}) begin
+      buffer_8_0 <= w_data_8_data[255:0];
+      buffer_8_1 <= w_data_8_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'h9, _w_beatSel_T_37, _w_beatSel_T_36}) begin
+      buffer_9_0 <= w_data_9_data[255:0];
+      buffer_9_1 <= w_data_9_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'hA, _w_beatSel_T_41, _w_beatSel_T_40}) begin
+      buffer_10_0 <= w_data_10_data[255:0];
+      buffer_10_1 <= w_data_10_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'hB, _w_beatSel_T_45, _w_beatSel_T_44}) begin
+      buffer_11_0 <= w_data_11_data[255:0];
+      buffer_11_1 <= w_data_11_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'hC, _w_beatSel_T_49, _w_beatSel_T_48}) begin
+      buffer_12_0 <= w_data_12_data[255:0];
+      buffer_12_1 <= w_data_12_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'hD, _w_beatSel_T_53, _w_beatSel_T_52}) begin
+      buffer_13_0 <= w_data_13_data[255:0];
+      buffer_13_1 <= w_data_13_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'hE, _w_beatSel_T_57, _w_beatSel_T_56}) begin
+      buffer_14_0 <= w_data_14_data[255:0];
+      buffer_14_1 <= w_data_14_data[511:256];
+    end
+    if (|{io_w_2_valid & io_w_2_bits_id == 8'hF, _w_beatSel_T_61, _w_beatSel_T_60}) begin
+      buffer_15_0 <= w_data_15_data[255:0];
+      buffer_15_1 <= w_data_15_data[511:256];
+    end
+  end // always @(posedge)
+  wire [15:0][255:0] _GEN =
+    {{buffer_15_1},
+     {buffer_14_1},
+     {buffer_13_1},
+     {buffer_12_1},
+     {buffer_11_1},
+     {buffer_10_1},
+     {buffer_9_1},
+     {buffer_8_1},
+     {buffer_7_1},
+     {buffer_6_1},
+     {buffer_5_1},
+     {buffer_4_1},
+     {buffer_3_1},
+     {buffer_2_1},
+     {buffer_1_1},
+     {buffer_0_1}};
+  wire [15:0][255:0] _GEN_0 =
+    {{buffer_15_0},
+     {buffer_14_0},
+     {buffer_13_0},
+     {buffer_12_0},
+     {buffer_11_0},
+     {buffer_10_0},
+     {buffer_9_0},
+     {buffer_8_0},
+     {buffer_7_0},
+     {buffer_6_0},
+     {buffer_5_0},
+     {buffer_4_0},
+     {buffer_3_0},
+     {buffer_2_0},
+     {buffer_1_0},
+     {buffer_0_0}};
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      io_resp_data_data_r <= 512'h0;
+    else if (io_r_valid)
+      io_resp_data_data_r <= {_GEN[io_r_bits_id[3:0]], _GEN_0[io_r_bits_id[3:0]]};
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:271];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [8:0] i = 9'h0; i < 9'h110; i += 9'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        buffer_0_0 =
+          {_RANDOM[9'h0],
+           _RANDOM[9'h1],
+           _RANDOM[9'h2],
+           _RANDOM[9'h3],
+           _RANDOM[9'h4],
+           _RANDOM[9'h5],
+           _RANDOM[9'h6],
+           _RANDOM[9'h7]};
+        buffer_0_1 =
+          {_RANDOM[9'h8],
+           _RANDOM[9'h9],
+           _RANDOM[9'hA],
+           _RANDOM[9'hB],
+           _RANDOM[9'hC],
+           _RANDOM[9'hD],
+           _RANDOM[9'hE],
+           _RANDOM[9'hF]};
+        buffer_1_0 =
+          {_RANDOM[9'h10],
+           _RANDOM[9'h11],
+           _RANDOM[9'h12],
+           _RANDOM[9'h13],
+           _RANDOM[9'h14],
+           _RANDOM[9'h15],
+           _RANDOM[9'h16],
+           _RANDOM[9'h17]};
+        buffer_1_1 =
+          {_RANDOM[9'h18],
+           _RANDOM[9'h19],
+           _RANDOM[9'h1A],
+           _RANDOM[9'h1B],
+           _RANDOM[9'h1C],
+           _RANDOM[9'h1D],
+           _RANDOM[9'h1E],
+           _RANDOM[9'h1F]};
+        buffer_2_0 =
+          {_RANDOM[9'h20],
+           _RANDOM[9'h21],
+           _RANDOM[9'h22],
+           _RANDOM[9'h23],
+           _RANDOM[9'h24],
+           _RANDOM[9'h25],
+           _RANDOM[9'h26],
+           _RANDOM[9'h27]};
+        buffer_2_1 =
+          {_RANDOM[9'h28],
+           _RANDOM[9'h29],
+           _RANDOM[9'h2A],
+           _RANDOM[9'h2B],
+           _RANDOM[9'h2C],
+           _RANDOM[9'h2D],
+           _RANDOM[9'h2E],
+           _RANDOM[9'h2F]};
+        buffer_3_0 =
+          {_RANDOM[9'h30],
+           _RANDOM[9'h31],
+           _RANDOM[9'h32],
+           _RANDOM[9'h33],
+           _RANDOM[9'h34],
+           _RANDOM[9'h35],
+           _RANDOM[9'h36],
+           _RANDOM[9'h37]};
+        buffer_3_1 =
+          {_RANDOM[9'h38],
+           _RANDOM[9'h39],
+           _RANDOM[9'h3A],
+           _RANDOM[9'h3B],
+           _RANDOM[9'h3C],
+           _RANDOM[9'h3D],
+           _RANDOM[9'h3E],
+           _RANDOM[9'h3F]};
+        buffer_4_0 =
+          {_RANDOM[9'h40],
+           _RANDOM[9'h41],
+           _RANDOM[9'h42],
+           _RANDOM[9'h43],
+           _RANDOM[9'h44],
+           _RANDOM[9'h45],
+           _RANDOM[9'h46],
+           _RANDOM[9'h47]};
+        buffer_4_1 =
+          {_RANDOM[9'h48],
+           _RANDOM[9'h49],
+           _RANDOM[9'h4A],
+           _RANDOM[9'h4B],
+           _RANDOM[9'h4C],
+           _RANDOM[9'h4D],
+           _RANDOM[9'h4E],
+           _RANDOM[9'h4F]};
+        buffer_5_0 =
+          {_RANDOM[9'h50],
+           _RANDOM[9'h51],
+           _RANDOM[9'h52],
+           _RANDOM[9'h53],
+           _RANDOM[9'h54],
+           _RANDOM[9'h55],
+           _RANDOM[9'h56],
+           _RANDOM[9'h57]};
+        buffer_5_1 =
+          {_RANDOM[9'h58],
+           _RANDOM[9'h59],
+           _RANDOM[9'h5A],
+           _RANDOM[9'h5B],
+           _RANDOM[9'h5C],
+           _RANDOM[9'h5D],
+           _RANDOM[9'h5E],
+           _RANDOM[9'h5F]};
+        buffer_6_0 =
+          {_RANDOM[9'h60],
+           _RANDOM[9'h61],
+           _RANDOM[9'h62],
+           _RANDOM[9'h63],
+           _RANDOM[9'h64],
+           _RANDOM[9'h65],
+           _RANDOM[9'h66],
+           _RANDOM[9'h67]};
+        buffer_6_1 =
+          {_RANDOM[9'h68],
+           _RANDOM[9'h69],
+           _RANDOM[9'h6A],
+           _RANDOM[9'h6B],
+           _RANDOM[9'h6C],
+           _RANDOM[9'h6D],
+           _RANDOM[9'h6E],
+           _RANDOM[9'h6F]};
+        buffer_7_0 =
+          {_RANDOM[9'h70],
+           _RANDOM[9'h71],
+           _RANDOM[9'h72],
+           _RANDOM[9'h73],
+           _RANDOM[9'h74],
+           _RANDOM[9'h75],
+           _RANDOM[9'h76],
+           _RANDOM[9'h77]};
+        buffer_7_1 =
+          {_RANDOM[9'h78],
+           _RANDOM[9'h79],
+           _RANDOM[9'h7A],
+           _RANDOM[9'h7B],
+           _RANDOM[9'h7C],
+           _RANDOM[9'h7D],
+           _RANDOM[9'h7E],
+           _RANDOM[9'h7F]};
+        buffer_8_0 =
+          {_RANDOM[9'h80],
+           _RANDOM[9'h81],
+           _RANDOM[9'h82],
+           _RANDOM[9'h83],
+           _RANDOM[9'h84],
+           _RANDOM[9'h85],
+           _RANDOM[9'h86],
+           _RANDOM[9'h87]};
+        buffer_8_1 =
+          {_RANDOM[9'h88],
+           _RANDOM[9'h89],
+           _RANDOM[9'h8A],
+           _RANDOM[9'h8B],
+           _RANDOM[9'h8C],
+           _RANDOM[9'h8D],
+           _RANDOM[9'h8E],
+           _RANDOM[9'h8F]};
+        buffer_9_0 =
+          {_RANDOM[9'h90],
+           _RANDOM[9'h91],
+           _RANDOM[9'h92],
+           _RANDOM[9'h93],
+           _RANDOM[9'h94],
+           _RANDOM[9'h95],
+           _RANDOM[9'h96],
+           _RANDOM[9'h97]};
+        buffer_9_1 =
+          {_RANDOM[9'h98],
+           _RANDOM[9'h99],
+           _RANDOM[9'h9A],
+           _RANDOM[9'h9B],
+           _RANDOM[9'h9C],
+           _RANDOM[9'h9D],
+           _RANDOM[9'h9E],
+           _RANDOM[9'h9F]};
+        buffer_10_0 =
+          {_RANDOM[9'hA0],
+           _RANDOM[9'hA1],
+           _RANDOM[9'hA2],
+           _RANDOM[9'hA3],
+           _RANDOM[9'hA4],
+           _RANDOM[9'hA5],
+           _RANDOM[9'hA6],
+           _RANDOM[9'hA7]};
+        buffer_10_1 =
+          {_RANDOM[9'hA8],
+           _RANDOM[9'hA9],
+           _RANDOM[9'hAA],
+           _RANDOM[9'hAB],
+           _RANDOM[9'hAC],
+           _RANDOM[9'hAD],
+           _RANDOM[9'hAE],
+           _RANDOM[9'hAF]};
+        buffer_11_0 =
+          {_RANDOM[9'hB0],
+           _RANDOM[9'hB1],
+           _RANDOM[9'hB2],
+           _RANDOM[9'hB3],
+           _RANDOM[9'hB4],
+           _RANDOM[9'hB5],
+           _RANDOM[9'hB6],
+           _RANDOM[9'hB7]};
+        buffer_11_1 =
+          {_RANDOM[9'hB8],
+           _RANDOM[9'hB9],
+           _RANDOM[9'hBA],
+           _RANDOM[9'hBB],
+           _RANDOM[9'hBC],
+           _RANDOM[9'hBD],
+           _RANDOM[9'hBE],
+           _RANDOM[9'hBF]};
+        buffer_12_0 =
+          {_RANDOM[9'hC0],
+           _RANDOM[9'hC1],
+           _RANDOM[9'hC2],
+           _RANDOM[9'hC3],
+           _RANDOM[9'hC4],
+           _RANDOM[9'hC5],
+           _RANDOM[9'hC6],
+           _RANDOM[9'hC7]};
+        buffer_12_1 =
+          {_RANDOM[9'hC8],
+           _RANDOM[9'hC9],
+           _RANDOM[9'hCA],
+           _RANDOM[9'hCB],
+           _RANDOM[9'hCC],
+           _RANDOM[9'hCD],
+           _RANDOM[9'hCE],
+           _RANDOM[9'hCF]};
+        buffer_13_0 =
+          {_RANDOM[9'hD0],
+           _RANDOM[9'hD1],
+           _RANDOM[9'hD2],
+           _RANDOM[9'hD3],
+           _RANDOM[9'hD4],
+           _RANDOM[9'hD5],
+           _RANDOM[9'hD6],
+           _RANDOM[9'hD7]};
+        buffer_13_1 =
+          {_RANDOM[9'hD8],
+           _RANDOM[9'hD9],
+           _RANDOM[9'hDA],
+           _RANDOM[9'hDB],
+           _RANDOM[9'hDC],
+           _RANDOM[9'hDD],
+           _RANDOM[9'hDE],
+           _RANDOM[9'hDF]};
+        buffer_14_0 =
+          {_RANDOM[9'hE0],
+           _RANDOM[9'hE1],
+           _RANDOM[9'hE2],
+           _RANDOM[9'hE3],
+           _RANDOM[9'hE4],
+           _RANDOM[9'hE5],
+           _RANDOM[9'hE6],
+           _RANDOM[9'hE7]};
+        buffer_14_1 =
+          {_RANDOM[9'hE8],
+           _RANDOM[9'hE9],
+           _RANDOM[9'hEA],
+           _RANDOM[9'hEB],
+           _RANDOM[9'hEC],
+           _RANDOM[9'hED],
+           _RANDOM[9'hEE],
+           _RANDOM[9'hEF]};
+        buffer_15_0 =
+          {_RANDOM[9'hF0],
+           _RANDOM[9'hF1],
+           _RANDOM[9'hF2],
+           _RANDOM[9'hF3],
+           _RANDOM[9'hF4],
+           _RANDOM[9'hF5],
+           _RANDOM[9'hF6],
+           _RANDOM[9'hF7]};
+        buffer_15_1 =
+          {_RANDOM[9'hF8],
+           _RANDOM[9'hF9],
+           _RANDOM[9'hFA],
+           _RANDOM[9'hFB],
+           _RANDOM[9'hFC],
+           _RANDOM[9'hFD],
+           _RANDOM[9'hFE],
+           _RANDOM[9'hFF]};
+        io_resp_data_data_r =
+          {_RANDOM[9'h100],
+           _RANDOM[9'h101],
+           _RANDOM[9'h102],
+           _RANDOM[9'h103],
+           _RANDOM[9'h104],
+           _RANDOM[9'h105],
+           _RANDOM[9'h106],
+           _RANDOM[9'h107],
+           _RANDOM[9'h108],
+           _RANDOM[9'h109],
+           _RANDOM[9'h10A],
+           _RANDOM[9'h10B],
+           _RANDOM[9'h10C],
+           _RANDOM[9'h10D],
+           _RANDOM[9'h10E],
+           _RANDOM[9'h10F]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        io_resp_data_data_r = 512'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_resp_data_data = io_resp_data_data_r;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MSHRCtl.sv b/flow/designs/src/xiangshan_coupledl2/deps/MSHRCtl.sv
new file mode 100644
index 0000000000..4167a4332f
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MSHRCtl.sv
@@ -0,0 +1,13739 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MSHRCtl(
+  input          clock,
+  input          reset,
+  output         io_toReqArb_blockA_s1,
+  output         io_toReqArb_blockB_s1,
+  input          io_fromMainPipe_mshr_alloc_s3_valid,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit,
+  input  [33:0]  io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag,
+  input  [7:0]   io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set,
+  input  [2:0]   io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty,
+  input  [1:0]   io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch,
+  input  [3:0]   io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_s_release,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct,
+  input  [2:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_channel,
+  input  [7:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_set,
+  input  [33:0]  io_fromMainPipe_mshr_alloc_s3_bits_task_tag,
+  input  [5:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_off,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_alias,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword,
+  input  [3:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_opcode,
+  input  [2:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_param,
+  input  [6:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft,
+  input  [4:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData,
+  input  [7:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty,
+  input  [1:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch,
+  input  [3:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr,
+  input  [10:0]  io_fromMainPipe_mshr_alloc_s3_bits_task_srcID,
+  input  [11:0]  io_fromMainPipe_mshr_alloc_s3_bits_task_txnID,
+  input  [10:0]  io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID,
+  input  [11:0]  io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID,
+  input  [6:0]   io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc,
+  input          io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag,
+  output [7:0]   io_toMainPipe_mshr_alloc_ptr,
+  input          io_mshrTask_ready,
+  output         io_mshrTask_valid,
+  output [2:0]   io_mshrTask_bits_channel,
+  output [2:0]   io_mshrTask_bits_txChannel,
+  output [7:0]   io_mshrTask_bits_set,
+  output [33:0]  io_mshrTask_bits_tag,
+  output [5:0]   io_mshrTask_bits_off,
+  output         io_mshrTask_bits_alias,
+  output         io_mshrTask_bits_isKeyword,
+  output [3:0]   io_mshrTask_bits_opcode,
+  output [2:0]   io_mshrTask_bits_param,
+  output [2:0]   io_mshrTask_bits_size,
+  output [6:0]   io_mshrTask_bits_sourceId,
+  output         io_mshrTask_bits_denied,
+  output         io_mshrTask_bits_corrupt,
+  output         io_mshrTask_bits_mshrTask,
+  output [7:0]   io_mshrTask_bits_mshrId,
+  output         io_mshrTask_bits_aliasTask,
+  output         io_mshrTask_bits_useProbeData,
+  output         io_mshrTask_bits_mshrRetry,
+  output         io_mshrTask_bits_readProbeDataDown,
+  output         io_mshrTask_bits_fromL2pft,
+  output         io_mshrTask_bits_dirty,
+  output [2:0]   io_mshrTask_bits_way,
+  output         io_mshrTask_bits_meta_dirty,
+  output [1:0]   io_mshrTask_bits_meta_state,
+  output         io_mshrTask_bits_meta_clients,
+  output         io_mshrTask_bits_meta_alias,
+  output         io_mshrTask_bits_meta_prefetch,
+  output [3:0]   io_mshrTask_bits_meta_prefetchSrc,
+  output         io_mshrTask_bits_meta_accessed,
+  output         io_mshrTask_bits_meta_tagErr,
+  output         io_mshrTask_bits_meta_dataErr,
+  output         io_mshrTask_bits_metaWen,
+  output         io_mshrTask_bits_tagWen,
+  output         io_mshrTask_bits_dsWen,
+  output         io_mshrTask_bits_replTask,
+  output         io_mshrTask_bits_cmoTask,
+  output [4:0]   io_mshrTask_bits_reqSource,
+  output         io_mshrTask_bits_mergeA,
+  output [5:0]   io_mshrTask_bits_aMergeTask_off,
+  output         io_mshrTask_bits_aMergeTask_alias,
+  output [43:0]  io_mshrTask_bits_aMergeTask_vaddr,
+  output         io_mshrTask_bits_aMergeTask_isKeyword,
+  output [2:0]   io_mshrTask_bits_aMergeTask_opcode,
+  output [2:0]   io_mshrTask_bits_aMergeTask_param,
+  output [6:0]   io_mshrTask_bits_aMergeTask_sourceId,
+  output         io_mshrTask_bits_aMergeTask_meta_dirty,
+  output [1:0]   io_mshrTask_bits_aMergeTask_meta_state,
+  output         io_mshrTask_bits_aMergeTask_meta_clients,
+  output         io_mshrTask_bits_aMergeTask_meta_alias,
+  output         io_mshrTask_bits_aMergeTask_meta_accessed,
+  output         io_mshrTask_bits_snpHitRelease,
+  output         io_mshrTask_bits_snpHitReleaseToInval,
+  output         io_mshrTask_bits_snpHitReleaseToClean,
+  output         io_mshrTask_bits_snpHitReleaseWithData,
+  output [7:0]   io_mshrTask_bits_snpHitReleaseIdx,
+  output         io_mshrTask_bits_snpHitReleaseMeta_dirty,
+  output [1:0]   io_mshrTask_bits_snpHitReleaseMeta_state,
+  output         io_mshrTask_bits_snpHitReleaseMeta_clients,
+  output         io_mshrTask_bits_snpHitReleaseMeta_alias,
+  output         io_mshrTask_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]   io_mshrTask_bits_snpHitReleaseMeta_prefetchSrc,
+  output         io_mshrTask_bits_snpHitReleaseMeta_accessed,
+  output         io_mshrTask_bits_snpHitReleaseMeta_tagErr,
+  output         io_mshrTask_bits_snpHitReleaseMeta_dataErr,
+  output [10:0]  io_mshrTask_bits_tgtID,
+  output [11:0]  io_mshrTask_bits_txnID,
+  output [10:0]  io_mshrTask_bits_homeNID,
+  output [11:0]  io_mshrTask_bits_dbID,
+  output [6:0]   io_mshrTask_bits_chiOpcode,
+  output [2:0]   io_mshrTask_bits_resp,
+  output [2:0]   io_mshrTask_bits_fwdState,
+  output         io_mshrTask_bits_retToSrc,
+  output         io_mshrTask_bits_likelyshared,
+  output         io_mshrTask_bits_expCompAck,
+  output         io_mshrTask_bits_allowRetry,
+  output         io_mshrTask_bits_memAttr_allocate,
+  output         io_mshrTask_bits_memAttr_cacheable,
+  output         io_mshrTask_bits_memAttr_ewa,
+  output         io_mshrTask_bits_traceTag,
+  input          io_pipeStatusVec_0_valid,
+  input          io_pipeStatusVec_1_valid,
+  input          io_toTXREQ_ready,
+  output         io_toTXREQ_valid,
+  output [3:0]   io_toTXREQ_bits_qos,
+  output [10:0]  io_toTXREQ_bits_tgtID,
+  output [11:0]  io_toTXREQ_bits_txnID,
+  output [6:0]   io_toTXREQ_bits_opcode,
+  output [2:0]   io_toTXREQ_bits_size,
+  output [47:0]  io_toTXREQ_bits_addr,
+  output         io_toTXREQ_bits_likelyshared,
+  output         io_toTXREQ_bits_allowRetry,
+  output [1:0]   io_toTXREQ_bits_order,
+  output [3:0]   io_toTXREQ_bits_pCrdType,
+  output         io_toTXREQ_bits_memAttr_allocate,
+  output         io_toTXREQ_bits_memAttr_cacheable,
+  output         io_toTXREQ_bits_memAttr_device,
+  output         io_toTXREQ_bits_memAttr_ewa,
+  output         io_toTXREQ_bits_snpAttr,
+  output         io_toTXREQ_bits_expCompAck,
+  input          io_toTXRSP_ready,
+  output         io_toTXRSP_valid,
+  output [10:0]  io_toTXRSP_bits_tgtID,
+  output [11:0]  io_toTXRSP_bits_txnID,
+  output [4:0]   io_toTXRSP_bits_opcode,
+  output         io_toTXRSP_bits_traceTag,
+  input          io_toSourceB_ready,
+  output         io_toSourceB_valid,
+  output [2:0]   io_toSourceB_bits_opcode,
+  output [1:0]   io_toSourceB_bits_param,
+  output [47:0]  io_toSourceB_bits_address,
+  output [255:0] io_toSourceB_bits_data,
+  input          io_grantStatus_0_valid,
+  input  [7:0]   io_grantStatus_0_set,
+  input  [33:0]  io_grantStatus_0_tag,
+  input          io_grantStatus_1_valid,
+  input  [7:0]   io_grantStatus_1_set,
+  input  [33:0]  io_grantStatus_1_tag,
+  input          io_grantStatus_2_valid,
+  input  [7:0]   io_grantStatus_2_set,
+  input  [33:0]  io_grantStatus_2_tag,
+  input          io_grantStatus_3_valid,
+  input  [7:0]   io_grantStatus_3_set,
+  input  [33:0]  io_grantStatus_3_tag,
+  input          io_grantStatus_4_valid,
+  input  [7:0]   io_grantStatus_4_set,
+  input  [33:0]  io_grantStatus_4_tag,
+  input          io_grantStatus_5_valid,
+  input  [7:0]   io_grantStatus_5_set,
+  input  [33:0]  io_grantStatus_5_tag,
+  input          io_grantStatus_6_valid,
+  input  [7:0]   io_grantStatus_6_set,
+  input  [33:0]  io_grantStatus_6_tag,
+  input          io_grantStatus_7_valid,
+  input  [7:0]   io_grantStatus_7_set,
+  input  [33:0]  io_grantStatus_7_tag,
+  input          io_grantStatus_8_valid,
+  input  [7:0]   io_grantStatus_8_set,
+  input  [33:0]  io_grantStatus_8_tag,
+  input          io_grantStatus_9_valid,
+  input  [7:0]   io_grantStatus_9_set,
+  input  [33:0]  io_grantStatus_9_tag,
+  input          io_grantStatus_10_valid,
+  input  [7:0]   io_grantStatus_10_set,
+  input  [33:0]  io_grantStatus_10_tag,
+  input          io_grantStatus_11_valid,
+  input  [7:0]   io_grantStatus_11_set,
+  input  [33:0]  io_grantStatus_11_tag,
+  input          io_grantStatus_12_valid,
+  input  [7:0]   io_grantStatus_12_set,
+  input  [33:0]  io_grantStatus_12_tag,
+  input          io_grantStatus_13_valid,
+  input  [7:0]   io_grantStatus_13_set,
+  input  [33:0]  io_grantStatus_13_tag,
+  input          io_grantStatus_14_valid,
+  input  [7:0]   io_grantStatus_14_set,
+  input  [33:0]  io_grantStatus_14_tag,
+  input          io_grantStatus_15_valid,
+  input  [7:0]   io_grantStatus_15_set,
+  input  [33:0]  io_grantStatus_15_tag,
+  input          io_resps_sinkC_valid,
+  input  [7:0]   io_resps_sinkC_set,
+  input  [33:0]  io_resps_sinkC_tag,
+  input  [2:0]   io_resps_sinkC_respInfo_opcode,
+  input  [2:0]   io_resps_sinkC_respInfo_param,
+  input          io_resps_sinkC_respInfo_last,
+  input          io_resps_sinkC_respInfo_denied,
+  input          io_resps_sinkC_respInfo_corrupt,
+  input          io_resps_rxrsp_valid,
+  input  [7:0]   io_resps_rxrsp_mshrId,
+  input  [6:0]   io_resps_rxrsp_respInfo_chiOpcode,
+  input  [10:0]  io_resps_rxrsp_respInfo_srcID,
+  input  [11:0]  io_resps_rxrsp_respInfo_dbID,
+  input  [2:0]   io_resps_rxrsp_respInfo_resp,
+  input  [3:0]   io_resps_rxrsp_respInfo_pCrdType,
+  input  [1:0]   io_resps_rxrsp_respInfo_respErr,
+  input          io_resps_rxrsp_respInfo_traceTag,
+  input          io_resps_rxdat_valid,
+  input  [7:0]   io_resps_rxdat_mshrId,
+  input          io_resps_rxdat_respInfo_last,
+  input          io_resps_rxdat_respInfo_corrupt,
+  input  [6:0]   io_resps_rxdat_respInfo_chiOpcode,
+  input  [10:0]  io_resps_rxdat_respInfo_homeNID,
+  input  [11:0]  io_resps_rxdat_respInfo_dbID,
+  input  [2:0]   io_resps_rxdat_respInfo_resp,
+  input  [1:0]   io_resps_rxdat_respInfo_respErr,
+  input          io_resps_rxdat_respInfo_traceTag,
+  output [7:0]   io_releaseBufWriteId,
+  input  [7:0]   io_nestedwb_set,
+  input  [33:0]  io_nestedwb_tag,
+  input          io_nestedwb_c_set_dirty,
+  input          io_nestedwb_c_set_tip,
+  input          io_nestedwb_b_inv_dirty,
+  input          io_nestedwb_b_toB,
+  input          io_nestedwb_b_toN,
+  input          io_nestedwb_b_toClean,
+  output         io_nestedwbDataId_valid,
+  output [7:0]   io_nestedwbDataId_bits,
+  output         io_msInfo_0_valid,
+  output [2:0]   io_msInfo_0_bits_channel,
+  output [7:0]   io_msInfo_0_bits_set,
+  output [2:0]   io_msInfo_0_bits_way,
+  output [33:0]  io_msInfo_0_bits_reqTag,
+  output [4:0]   io_msInfo_0_bits_reqSource,
+  output         io_msInfo_0_bits_willFree,
+  output         io_msInfo_0_bits_aliasTask,
+  output         io_msInfo_0_bits_needRelease,
+  output         io_msInfo_0_bits_blockRefill,
+  output         io_msInfo_0_bits_meta_dirty,
+  output [1:0]   io_msInfo_0_bits_meta_state,
+  output         io_msInfo_0_bits_meta_clients,
+  output         io_msInfo_0_bits_meta_alias,
+  output         io_msInfo_0_bits_meta_prefetch,
+  output [3:0]   io_msInfo_0_bits_meta_prefetchSrc,
+  output         io_msInfo_0_bits_meta_accessed,
+  output         io_msInfo_0_bits_meta_tagErr,
+  output         io_msInfo_0_bits_meta_dataErr,
+  output [33:0]  io_msInfo_0_bits_metaTag,
+  output         io_msInfo_0_bits_dirHit,
+  output         io_msInfo_0_bits_isAcqOrPrefetch,
+  output         io_msInfo_0_bits_isPrefetch,
+  output [2:0]   io_msInfo_0_bits_param,
+  output         io_msInfo_0_bits_mergeA,
+  output         io_msInfo_0_bits_w_grantfirst,
+  output         io_msInfo_0_bits_w_grantlast,
+  output         io_msInfo_0_bits_w_grant,
+  output         io_msInfo_0_bits_s_release,
+  output         io_msInfo_0_bits_s_refill,
+  output         io_msInfo_0_bits_s_cmoresp,
+  output         io_msInfo_0_bits_s_cmometaw,
+  output         io_msInfo_0_bits_w_releaseack,
+  output         io_msInfo_0_bits_w_replResp,
+  output         io_msInfo_0_bits_w_rprobeacklast,
+  output         io_msInfo_0_bits_replaceData,
+  output         io_msInfo_0_bits_releaseToClean,
+  output         io_msInfo_1_valid,
+  output [2:0]   io_msInfo_1_bits_channel,
+  output [7:0]   io_msInfo_1_bits_set,
+  output [2:0]   io_msInfo_1_bits_way,
+  output [33:0]  io_msInfo_1_bits_reqTag,
+  output [4:0]   io_msInfo_1_bits_reqSource,
+  output         io_msInfo_1_bits_willFree,
+  output         io_msInfo_1_bits_aliasTask,
+  output         io_msInfo_1_bits_needRelease,
+  output         io_msInfo_1_bits_blockRefill,
+  output         io_msInfo_1_bits_meta_dirty,
+  output [1:0]   io_msInfo_1_bits_meta_state,
+  output         io_msInfo_1_bits_meta_clients,
+  output         io_msInfo_1_bits_meta_alias,
+  output         io_msInfo_1_bits_meta_prefetch,
+  output [3:0]   io_msInfo_1_bits_meta_prefetchSrc,
+  output         io_msInfo_1_bits_meta_accessed,
+  output         io_msInfo_1_bits_meta_tagErr,
+  output         io_msInfo_1_bits_meta_dataErr,
+  output [33:0]  io_msInfo_1_bits_metaTag,
+  output         io_msInfo_1_bits_dirHit,
+  output         io_msInfo_1_bits_isAcqOrPrefetch,
+  output         io_msInfo_1_bits_isPrefetch,
+  output [2:0]   io_msInfo_1_bits_param,
+  output         io_msInfo_1_bits_mergeA,
+  output         io_msInfo_1_bits_w_grantfirst,
+  output         io_msInfo_1_bits_w_grantlast,
+  output         io_msInfo_1_bits_w_grant,
+  output         io_msInfo_1_bits_s_release,
+  output         io_msInfo_1_bits_s_refill,
+  output         io_msInfo_1_bits_s_cmoresp,
+  output         io_msInfo_1_bits_s_cmometaw,
+  output         io_msInfo_1_bits_w_releaseack,
+  output         io_msInfo_1_bits_w_replResp,
+  output         io_msInfo_1_bits_w_rprobeacklast,
+  output         io_msInfo_1_bits_replaceData,
+  output         io_msInfo_1_bits_releaseToClean,
+  output         io_msInfo_2_valid,
+  output [2:0]   io_msInfo_2_bits_channel,
+  output [7:0]   io_msInfo_2_bits_set,
+  output [2:0]   io_msInfo_2_bits_way,
+  output [33:0]  io_msInfo_2_bits_reqTag,
+  output [4:0]   io_msInfo_2_bits_reqSource,
+  output         io_msInfo_2_bits_willFree,
+  output         io_msInfo_2_bits_aliasTask,
+  output         io_msInfo_2_bits_needRelease,
+  output         io_msInfo_2_bits_blockRefill,
+  output         io_msInfo_2_bits_meta_dirty,
+  output [1:0]   io_msInfo_2_bits_meta_state,
+  output         io_msInfo_2_bits_meta_clients,
+  output         io_msInfo_2_bits_meta_alias,
+  output         io_msInfo_2_bits_meta_prefetch,
+  output [3:0]   io_msInfo_2_bits_meta_prefetchSrc,
+  output         io_msInfo_2_bits_meta_accessed,
+  output         io_msInfo_2_bits_meta_tagErr,
+  output         io_msInfo_2_bits_meta_dataErr,
+  output [33:0]  io_msInfo_2_bits_metaTag,
+  output         io_msInfo_2_bits_dirHit,
+  output         io_msInfo_2_bits_isAcqOrPrefetch,
+  output         io_msInfo_2_bits_isPrefetch,
+  output [2:0]   io_msInfo_2_bits_param,
+  output         io_msInfo_2_bits_mergeA,
+  output         io_msInfo_2_bits_w_grantfirst,
+  output         io_msInfo_2_bits_w_grantlast,
+  output         io_msInfo_2_bits_w_grant,
+  output         io_msInfo_2_bits_s_release,
+  output         io_msInfo_2_bits_s_refill,
+  output         io_msInfo_2_bits_s_cmoresp,
+  output         io_msInfo_2_bits_s_cmometaw,
+  output         io_msInfo_2_bits_w_releaseack,
+  output         io_msInfo_2_bits_w_replResp,
+  output         io_msInfo_2_bits_w_rprobeacklast,
+  output         io_msInfo_2_bits_replaceData,
+  output         io_msInfo_2_bits_releaseToClean,
+  output         io_msInfo_3_valid,
+  output [2:0]   io_msInfo_3_bits_channel,
+  output [7:0]   io_msInfo_3_bits_set,
+  output [2:0]   io_msInfo_3_bits_way,
+  output [33:0]  io_msInfo_3_bits_reqTag,
+  output [4:0]   io_msInfo_3_bits_reqSource,
+  output         io_msInfo_3_bits_willFree,
+  output         io_msInfo_3_bits_aliasTask,
+  output         io_msInfo_3_bits_needRelease,
+  output         io_msInfo_3_bits_blockRefill,
+  output         io_msInfo_3_bits_meta_dirty,
+  output [1:0]   io_msInfo_3_bits_meta_state,
+  output         io_msInfo_3_bits_meta_clients,
+  output         io_msInfo_3_bits_meta_alias,
+  output         io_msInfo_3_bits_meta_prefetch,
+  output [3:0]   io_msInfo_3_bits_meta_prefetchSrc,
+  output         io_msInfo_3_bits_meta_accessed,
+  output         io_msInfo_3_bits_meta_tagErr,
+  output         io_msInfo_3_bits_meta_dataErr,
+  output [33:0]  io_msInfo_3_bits_metaTag,
+  output         io_msInfo_3_bits_dirHit,
+  output         io_msInfo_3_bits_isAcqOrPrefetch,
+  output         io_msInfo_3_bits_isPrefetch,
+  output [2:0]   io_msInfo_3_bits_param,
+  output         io_msInfo_3_bits_mergeA,
+  output         io_msInfo_3_bits_w_grantfirst,
+  output         io_msInfo_3_bits_w_grantlast,
+  output         io_msInfo_3_bits_w_grant,
+  output         io_msInfo_3_bits_s_release,
+  output         io_msInfo_3_bits_s_refill,
+  output         io_msInfo_3_bits_s_cmoresp,
+  output         io_msInfo_3_bits_s_cmometaw,
+  output         io_msInfo_3_bits_w_releaseack,
+  output         io_msInfo_3_bits_w_replResp,
+  output         io_msInfo_3_bits_w_rprobeacklast,
+  output         io_msInfo_3_bits_replaceData,
+  output         io_msInfo_3_bits_releaseToClean,
+  output         io_msInfo_4_valid,
+  output [2:0]   io_msInfo_4_bits_channel,
+  output [7:0]   io_msInfo_4_bits_set,
+  output [2:0]   io_msInfo_4_bits_way,
+  output [33:0]  io_msInfo_4_bits_reqTag,
+  output [4:0]   io_msInfo_4_bits_reqSource,
+  output         io_msInfo_4_bits_willFree,
+  output         io_msInfo_4_bits_aliasTask,
+  output         io_msInfo_4_bits_needRelease,
+  output         io_msInfo_4_bits_blockRefill,
+  output         io_msInfo_4_bits_meta_dirty,
+  output [1:0]   io_msInfo_4_bits_meta_state,
+  output         io_msInfo_4_bits_meta_clients,
+  output         io_msInfo_4_bits_meta_alias,
+  output         io_msInfo_4_bits_meta_prefetch,
+  output [3:0]   io_msInfo_4_bits_meta_prefetchSrc,
+  output         io_msInfo_4_bits_meta_accessed,
+  output         io_msInfo_4_bits_meta_tagErr,
+  output         io_msInfo_4_bits_meta_dataErr,
+  output [33:0]  io_msInfo_4_bits_metaTag,
+  output         io_msInfo_4_bits_dirHit,
+  output         io_msInfo_4_bits_isAcqOrPrefetch,
+  output         io_msInfo_4_bits_isPrefetch,
+  output [2:0]   io_msInfo_4_bits_param,
+  output         io_msInfo_4_bits_mergeA,
+  output         io_msInfo_4_bits_w_grantfirst,
+  output         io_msInfo_4_bits_w_grantlast,
+  output         io_msInfo_4_bits_w_grant,
+  output         io_msInfo_4_bits_s_release,
+  output         io_msInfo_4_bits_s_refill,
+  output         io_msInfo_4_bits_s_cmoresp,
+  output         io_msInfo_4_bits_s_cmometaw,
+  output         io_msInfo_4_bits_w_releaseack,
+  output         io_msInfo_4_bits_w_replResp,
+  output         io_msInfo_4_bits_w_rprobeacklast,
+  output         io_msInfo_4_bits_replaceData,
+  output         io_msInfo_4_bits_releaseToClean,
+  output         io_msInfo_5_valid,
+  output [2:0]   io_msInfo_5_bits_channel,
+  output [7:0]   io_msInfo_5_bits_set,
+  output [2:0]   io_msInfo_5_bits_way,
+  output [33:0]  io_msInfo_5_bits_reqTag,
+  output [4:0]   io_msInfo_5_bits_reqSource,
+  output         io_msInfo_5_bits_willFree,
+  output         io_msInfo_5_bits_aliasTask,
+  output         io_msInfo_5_bits_needRelease,
+  output         io_msInfo_5_bits_blockRefill,
+  output         io_msInfo_5_bits_meta_dirty,
+  output [1:0]   io_msInfo_5_bits_meta_state,
+  output         io_msInfo_5_bits_meta_clients,
+  output         io_msInfo_5_bits_meta_alias,
+  output         io_msInfo_5_bits_meta_prefetch,
+  output [3:0]   io_msInfo_5_bits_meta_prefetchSrc,
+  output         io_msInfo_5_bits_meta_accessed,
+  output         io_msInfo_5_bits_meta_tagErr,
+  output         io_msInfo_5_bits_meta_dataErr,
+  output [33:0]  io_msInfo_5_bits_metaTag,
+  output         io_msInfo_5_bits_dirHit,
+  output         io_msInfo_5_bits_isAcqOrPrefetch,
+  output         io_msInfo_5_bits_isPrefetch,
+  output [2:0]   io_msInfo_5_bits_param,
+  output         io_msInfo_5_bits_mergeA,
+  output         io_msInfo_5_bits_w_grantfirst,
+  output         io_msInfo_5_bits_w_grantlast,
+  output         io_msInfo_5_bits_w_grant,
+  output         io_msInfo_5_bits_s_release,
+  output         io_msInfo_5_bits_s_refill,
+  output         io_msInfo_5_bits_s_cmoresp,
+  output         io_msInfo_5_bits_s_cmometaw,
+  output         io_msInfo_5_bits_w_releaseack,
+  output         io_msInfo_5_bits_w_replResp,
+  output         io_msInfo_5_bits_w_rprobeacklast,
+  output         io_msInfo_5_bits_replaceData,
+  output         io_msInfo_5_bits_releaseToClean,
+  output         io_msInfo_6_valid,
+  output [2:0]   io_msInfo_6_bits_channel,
+  output [7:0]   io_msInfo_6_bits_set,
+  output [2:0]   io_msInfo_6_bits_way,
+  output [33:0]  io_msInfo_6_bits_reqTag,
+  output [4:0]   io_msInfo_6_bits_reqSource,
+  output         io_msInfo_6_bits_willFree,
+  output         io_msInfo_6_bits_aliasTask,
+  output         io_msInfo_6_bits_needRelease,
+  output         io_msInfo_6_bits_blockRefill,
+  output         io_msInfo_6_bits_meta_dirty,
+  output [1:0]   io_msInfo_6_bits_meta_state,
+  output         io_msInfo_6_bits_meta_clients,
+  output         io_msInfo_6_bits_meta_alias,
+  output         io_msInfo_6_bits_meta_prefetch,
+  output [3:0]   io_msInfo_6_bits_meta_prefetchSrc,
+  output         io_msInfo_6_bits_meta_accessed,
+  output         io_msInfo_6_bits_meta_tagErr,
+  output         io_msInfo_6_bits_meta_dataErr,
+  output [33:0]  io_msInfo_6_bits_metaTag,
+  output         io_msInfo_6_bits_dirHit,
+  output         io_msInfo_6_bits_isAcqOrPrefetch,
+  output         io_msInfo_6_bits_isPrefetch,
+  output [2:0]   io_msInfo_6_bits_param,
+  output         io_msInfo_6_bits_mergeA,
+  output         io_msInfo_6_bits_w_grantfirst,
+  output         io_msInfo_6_bits_w_grantlast,
+  output         io_msInfo_6_bits_w_grant,
+  output         io_msInfo_6_bits_s_release,
+  output         io_msInfo_6_bits_s_refill,
+  output         io_msInfo_6_bits_s_cmoresp,
+  output         io_msInfo_6_bits_s_cmometaw,
+  output         io_msInfo_6_bits_w_releaseack,
+  output         io_msInfo_6_bits_w_replResp,
+  output         io_msInfo_6_bits_w_rprobeacklast,
+  output         io_msInfo_6_bits_replaceData,
+  output         io_msInfo_6_bits_releaseToClean,
+  output         io_msInfo_7_valid,
+  output [2:0]   io_msInfo_7_bits_channel,
+  output [7:0]   io_msInfo_7_bits_set,
+  output [2:0]   io_msInfo_7_bits_way,
+  output [33:0]  io_msInfo_7_bits_reqTag,
+  output [4:0]   io_msInfo_7_bits_reqSource,
+  output         io_msInfo_7_bits_willFree,
+  output         io_msInfo_7_bits_aliasTask,
+  output         io_msInfo_7_bits_needRelease,
+  output         io_msInfo_7_bits_blockRefill,
+  output         io_msInfo_7_bits_meta_dirty,
+  output [1:0]   io_msInfo_7_bits_meta_state,
+  output         io_msInfo_7_bits_meta_clients,
+  output         io_msInfo_7_bits_meta_alias,
+  output         io_msInfo_7_bits_meta_prefetch,
+  output [3:0]   io_msInfo_7_bits_meta_prefetchSrc,
+  output         io_msInfo_7_bits_meta_accessed,
+  output         io_msInfo_7_bits_meta_tagErr,
+  output         io_msInfo_7_bits_meta_dataErr,
+  output [33:0]  io_msInfo_7_bits_metaTag,
+  output         io_msInfo_7_bits_dirHit,
+  output         io_msInfo_7_bits_isAcqOrPrefetch,
+  output         io_msInfo_7_bits_isPrefetch,
+  output [2:0]   io_msInfo_7_bits_param,
+  output         io_msInfo_7_bits_mergeA,
+  output         io_msInfo_7_bits_w_grantfirst,
+  output         io_msInfo_7_bits_w_grantlast,
+  output         io_msInfo_7_bits_w_grant,
+  output         io_msInfo_7_bits_s_release,
+  output         io_msInfo_7_bits_s_refill,
+  output         io_msInfo_7_bits_s_cmoresp,
+  output         io_msInfo_7_bits_s_cmometaw,
+  output         io_msInfo_7_bits_w_releaseack,
+  output         io_msInfo_7_bits_w_replResp,
+  output         io_msInfo_7_bits_w_rprobeacklast,
+  output         io_msInfo_7_bits_replaceData,
+  output         io_msInfo_7_bits_releaseToClean,
+  output         io_msInfo_8_valid,
+  output [2:0]   io_msInfo_8_bits_channel,
+  output [7:0]   io_msInfo_8_bits_set,
+  output [2:0]   io_msInfo_8_bits_way,
+  output [33:0]  io_msInfo_8_bits_reqTag,
+  output [4:0]   io_msInfo_8_bits_reqSource,
+  output         io_msInfo_8_bits_willFree,
+  output         io_msInfo_8_bits_aliasTask,
+  output         io_msInfo_8_bits_needRelease,
+  output         io_msInfo_8_bits_blockRefill,
+  output         io_msInfo_8_bits_meta_dirty,
+  output [1:0]   io_msInfo_8_bits_meta_state,
+  output         io_msInfo_8_bits_meta_clients,
+  output         io_msInfo_8_bits_meta_alias,
+  output         io_msInfo_8_bits_meta_prefetch,
+  output [3:0]   io_msInfo_8_bits_meta_prefetchSrc,
+  output         io_msInfo_8_bits_meta_accessed,
+  output         io_msInfo_8_bits_meta_tagErr,
+  output         io_msInfo_8_bits_meta_dataErr,
+  output [33:0]  io_msInfo_8_bits_metaTag,
+  output         io_msInfo_8_bits_dirHit,
+  output         io_msInfo_8_bits_isAcqOrPrefetch,
+  output         io_msInfo_8_bits_isPrefetch,
+  output [2:0]   io_msInfo_8_bits_param,
+  output         io_msInfo_8_bits_mergeA,
+  output         io_msInfo_8_bits_w_grantfirst,
+  output         io_msInfo_8_bits_w_grantlast,
+  output         io_msInfo_8_bits_w_grant,
+  output         io_msInfo_8_bits_s_release,
+  output         io_msInfo_8_bits_s_refill,
+  output         io_msInfo_8_bits_s_cmoresp,
+  output         io_msInfo_8_bits_s_cmometaw,
+  output         io_msInfo_8_bits_w_releaseack,
+  output         io_msInfo_8_bits_w_replResp,
+  output         io_msInfo_8_bits_w_rprobeacklast,
+  output         io_msInfo_8_bits_replaceData,
+  output         io_msInfo_8_bits_releaseToClean,
+  output         io_msInfo_9_valid,
+  output [2:0]   io_msInfo_9_bits_channel,
+  output [7:0]   io_msInfo_9_bits_set,
+  output [2:0]   io_msInfo_9_bits_way,
+  output [33:0]  io_msInfo_9_bits_reqTag,
+  output [4:0]   io_msInfo_9_bits_reqSource,
+  output         io_msInfo_9_bits_willFree,
+  output         io_msInfo_9_bits_aliasTask,
+  output         io_msInfo_9_bits_needRelease,
+  output         io_msInfo_9_bits_blockRefill,
+  output         io_msInfo_9_bits_meta_dirty,
+  output [1:0]   io_msInfo_9_bits_meta_state,
+  output         io_msInfo_9_bits_meta_clients,
+  output         io_msInfo_9_bits_meta_alias,
+  output         io_msInfo_9_bits_meta_prefetch,
+  output [3:0]   io_msInfo_9_bits_meta_prefetchSrc,
+  output         io_msInfo_9_bits_meta_accessed,
+  output         io_msInfo_9_bits_meta_tagErr,
+  output         io_msInfo_9_bits_meta_dataErr,
+  output [33:0]  io_msInfo_9_bits_metaTag,
+  output         io_msInfo_9_bits_dirHit,
+  output         io_msInfo_9_bits_isAcqOrPrefetch,
+  output         io_msInfo_9_bits_isPrefetch,
+  output [2:0]   io_msInfo_9_bits_param,
+  output         io_msInfo_9_bits_mergeA,
+  output         io_msInfo_9_bits_w_grantfirst,
+  output         io_msInfo_9_bits_w_grantlast,
+  output         io_msInfo_9_bits_w_grant,
+  output         io_msInfo_9_bits_s_release,
+  output         io_msInfo_9_bits_s_refill,
+  output         io_msInfo_9_bits_s_cmoresp,
+  output         io_msInfo_9_bits_s_cmometaw,
+  output         io_msInfo_9_bits_w_releaseack,
+  output         io_msInfo_9_bits_w_replResp,
+  output         io_msInfo_9_bits_w_rprobeacklast,
+  output         io_msInfo_9_bits_replaceData,
+  output         io_msInfo_9_bits_releaseToClean,
+  output         io_msInfo_10_valid,
+  output [2:0]   io_msInfo_10_bits_channel,
+  output [7:0]   io_msInfo_10_bits_set,
+  output [2:0]   io_msInfo_10_bits_way,
+  output [33:0]  io_msInfo_10_bits_reqTag,
+  output [4:0]   io_msInfo_10_bits_reqSource,
+  output         io_msInfo_10_bits_willFree,
+  output         io_msInfo_10_bits_aliasTask,
+  output         io_msInfo_10_bits_needRelease,
+  output         io_msInfo_10_bits_blockRefill,
+  output         io_msInfo_10_bits_meta_dirty,
+  output [1:0]   io_msInfo_10_bits_meta_state,
+  output         io_msInfo_10_bits_meta_clients,
+  output         io_msInfo_10_bits_meta_alias,
+  output         io_msInfo_10_bits_meta_prefetch,
+  output [3:0]   io_msInfo_10_bits_meta_prefetchSrc,
+  output         io_msInfo_10_bits_meta_accessed,
+  output         io_msInfo_10_bits_meta_tagErr,
+  output         io_msInfo_10_bits_meta_dataErr,
+  output [33:0]  io_msInfo_10_bits_metaTag,
+  output         io_msInfo_10_bits_dirHit,
+  output         io_msInfo_10_bits_isAcqOrPrefetch,
+  output         io_msInfo_10_bits_isPrefetch,
+  output [2:0]   io_msInfo_10_bits_param,
+  output         io_msInfo_10_bits_mergeA,
+  output         io_msInfo_10_bits_w_grantfirst,
+  output         io_msInfo_10_bits_w_grantlast,
+  output         io_msInfo_10_bits_w_grant,
+  output         io_msInfo_10_bits_s_release,
+  output         io_msInfo_10_bits_s_refill,
+  output         io_msInfo_10_bits_s_cmoresp,
+  output         io_msInfo_10_bits_s_cmometaw,
+  output         io_msInfo_10_bits_w_releaseack,
+  output         io_msInfo_10_bits_w_replResp,
+  output         io_msInfo_10_bits_w_rprobeacklast,
+  output         io_msInfo_10_bits_replaceData,
+  output         io_msInfo_10_bits_releaseToClean,
+  output         io_msInfo_11_valid,
+  output [2:0]   io_msInfo_11_bits_channel,
+  output [7:0]   io_msInfo_11_bits_set,
+  output [2:0]   io_msInfo_11_bits_way,
+  output [33:0]  io_msInfo_11_bits_reqTag,
+  output [4:0]   io_msInfo_11_bits_reqSource,
+  output         io_msInfo_11_bits_willFree,
+  output         io_msInfo_11_bits_aliasTask,
+  output         io_msInfo_11_bits_needRelease,
+  output         io_msInfo_11_bits_blockRefill,
+  output         io_msInfo_11_bits_meta_dirty,
+  output [1:0]   io_msInfo_11_bits_meta_state,
+  output         io_msInfo_11_bits_meta_clients,
+  output         io_msInfo_11_bits_meta_alias,
+  output         io_msInfo_11_bits_meta_prefetch,
+  output [3:0]   io_msInfo_11_bits_meta_prefetchSrc,
+  output         io_msInfo_11_bits_meta_accessed,
+  output         io_msInfo_11_bits_meta_tagErr,
+  output         io_msInfo_11_bits_meta_dataErr,
+  output [33:0]  io_msInfo_11_bits_metaTag,
+  output         io_msInfo_11_bits_dirHit,
+  output         io_msInfo_11_bits_isAcqOrPrefetch,
+  output         io_msInfo_11_bits_isPrefetch,
+  output [2:0]   io_msInfo_11_bits_param,
+  output         io_msInfo_11_bits_mergeA,
+  output         io_msInfo_11_bits_w_grantfirst,
+  output         io_msInfo_11_bits_w_grantlast,
+  output         io_msInfo_11_bits_w_grant,
+  output         io_msInfo_11_bits_s_release,
+  output         io_msInfo_11_bits_s_refill,
+  output         io_msInfo_11_bits_s_cmoresp,
+  output         io_msInfo_11_bits_s_cmometaw,
+  output         io_msInfo_11_bits_w_releaseack,
+  output         io_msInfo_11_bits_w_replResp,
+  output         io_msInfo_11_bits_w_rprobeacklast,
+  output         io_msInfo_11_bits_replaceData,
+  output         io_msInfo_11_bits_releaseToClean,
+  output         io_msInfo_12_valid,
+  output [2:0]   io_msInfo_12_bits_channel,
+  output [7:0]   io_msInfo_12_bits_set,
+  output [2:0]   io_msInfo_12_bits_way,
+  output [33:0]  io_msInfo_12_bits_reqTag,
+  output [4:0]   io_msInfo_12_bits_reqSource,
+  output         io_msInfo_12_bits_willFree,
+  output         io_msInfo_12_bits_aliasTask,
+  output         io_msInfo_12_bits_needRelease,
+  output         io_msInfo_12_bits_blockRefill,
+  output         io_msInfo_12_bits_meta_dirty,
+  output [1:0]   io_msInfo_12_bits_meta_state,
+  output         io_msInfo_12_bits_meta_clients,
+  output         io_msInfo_12_bits_meta_alias,
+  output         io_msInfo_12_bits_meta_prefetch,
+  output [3:0]   io_msInfo_12_bits_meta_prefetchSrc,
+  output         io_msInfo_12_bits_meta_accessed,
+  output         io_msInfo_12_bits_meta_tagErr,
+  output         io_msInfo_12_bits_meta_dataErr,
+  output [33:0]  io_msInfo_12_bits_metaTag,
+  output         io_msInfo_12_bits_dirHit,
+  output         io_msInfo_12_bits_isAcqOrPrefetch,
+  output         io_msInfo_12_bits_isPrefetch,
+  output [2:0]   io_msInfo_12_bits_param,
+  output         io_msInfo_12_bits_mergeA,
+  output         io_msInfo_12_bits_w_grantfirst,
+  output         io_msInfo_12_bits_w_grantlast,
+  output         io_msInfo_12_bits_w_grant,
+  output         io_msInfo_12_bits_s_release,
+  output         io_msInfo_12_bits_s_refill,
+  output         io_msInfo_12_bits_s_cmoresp,
+  output         io_msInfo_12_bits_s_cmometaw,
+  output         io_msInfo_12_bits_w_releaseack,
+  output         io_msInfo_12_bits_w_replResp,
+  output         io_msInfo_12_bits_w_rprobeacklast,
+  output         io_msInfo_12_bits_replaceData,
+  output         io_msInfo_12_bits_releaseToClean,
+  output         io_msInfo_13_valid,
+  output [2:0]   io_msInfo_13_bits_channel,
+  output [7:0]   io_msInfo_13_bits_set,
+  output [2:0]   io_msInfo_13_bits_way,
+  output [33:0]  io_msInfo_13_bits_reqTag,
+  output [4:0]   io_msInfo_13_bits_reqSource,
+  output         io_msInfo_13_bits_willFree,
+  output         io_msInfo_13_bits_aliasTask,
+  output         io_msInfo_13_bits_needRelease,
+  output         io_msInfo_13_bits_blockRefill,
+  output         io_msInfo_13_bits_meta_dirty,
+  output [1:0]   io_msInfo_13_bits_meta_state,
+  output         io_msInfo_13_bits_meta_clients,
+  output         io_msInfo_13_bits_meta_alias,
+  output         io_msInfo_13_bits_meta_prefetch,
+  output [3:0]   io_msInfo_13_bits_meta_prefetchSrc,
+  output         io_msInfo_13_bits_meta_accessed,
+  output         io_msInfo_13_bits_meta_tagErr,
+  output         io_msInfo_13_bits_meta_dataErr,
+  output [33:0]  io_msInfo_13_bits_metaTag,
+  output         io_msInfo_13_bits_dirHit,
+  output         io_msInfo_13_bits_isAcqOrPrefetch,
+  output         io_msInfo_13_bits_isPrefetch,
+  output [2:0]   io_msInfo_13_bits_param,
+  output         io_msInfo_13_bits_mergeA,
+  output         io_msInfo_13_bits_w_grantfirst,
+  output         io_msInfo_13_bits_w_grantlast,
+  output         io_msInfo_13_bits_w_grant,
+  output         io_msInfo_13_bits_s_release,
+  output         io_msInfo_13_bits_s_refill,
+  output         io_msInfo_13_bits_s_cmoresp,
+  output         io_msInfo_13_bits_s_cmometaw,
+  output         io_msInfo_13_bits_w_releaseack,
+  output         io_msInfo_13_bits_w_replResp,
+  output         io_msInfo_13_bits_w_rprobeacklast,
+  output         io_msInfo_13_bits_replaceData,
+  output         io_msInfo_13_bits_releaseToClean,
+  output         io_msInfo_14_valid,
+  output [2:0]   io_msInfo_14_bits_channel,
+  output [7:0]   io_msInfo_14_bits_set,
+  output [2:0]   io_msInfo_14_bits_way,
+  output [33:0]  io_msInfo_14_bits_reqTag,
+  output [4:0]   io_msInfo_14_bits_reqSource,
+  output         io_msInfo_14_bits_willFree,
+  output         io_msInfo_14_bits_aliasTask,
+  output         io_msInfo_14_bits_needRelease,
+  output         io_msInfo_14_bits_blockRefill,
+  output         io_msInfo_14_bits_meta_dirty,
+  output [1:0]   io_msInfo_14_bits_meta_state,
+  output         io_msInfo_14_bits_meta_clients,
+  output         io_msInfo_14_bits_meta_alias,
+  output         io_msInfo_14_bits_meta_prefetch,
+  output [3:0]   io_msInfo_14_bits_meta_prefetchSrc,
+  output         io_msInfo_14_bits_meta_accessed,
+  output         io_msInfo_14_bits_meta_tagErr,
+  output         io_msInfo_14_bits_meta_dataErr,
+  output [33:0]  io_msInfo_14_bits_metaTag,
+  output         io_msInfo_14_bits_dirHit,
+  output         io_msInfo_14_bits_isAcqOrPrefetch,
+  output         io_msInfo_14_bits_isPrefetch,
+  output [2:0]   io_msInfo_14_bits_param,
+  output         io_msInfo_14_bits_mergeA,
+  output         io_msInfo_14_bits_w_grantfirst,
+  output         io_msInfo_14_bits_w_grantlast,
+  output         io_msInfo_14_bits_w_grant,
+  output         io_msInfo_14_bits_s_release,
+  output         io_msInfo_14_bits_s_refill,
+  output         io_msInfo_14_bits_s_cmoresp,
+  output         io_msInfo_14_bits_s_cmometaw,
+  output         io_msInfo_14_bits_w_releaseack,
+  output         io_msInfo_14_bits_w_replResp,
+  output         io_msInfo_14_bits_w_rprobeacklast,
+  output         io_msInfo_14_bits_replaceData,
+  output         io_msInfo_14_bits_releaseToClean,
+  output         io_msInfo_15_valid,
+  output [2:0]   io_msInfo_15_bits_channel,
+  output [7:0]   io_msInfo_15_bits_set,
+  output [2:0]   io_msInfo_15_bits_way,
+  output [33:0]  io_msInfo_15_bits_reqTag,
+  output [4:0]   io_msInfo_15_bits_reqSource,
+  output         io_msInfo_15_bits_willFree,
+  output         io_msInfo_15_bits_aliasTask,
+  output         io_msInfo_15_bits_needRelease,
+  output         io_msInfo_15_bits_blockRefill,
+  output         io_msInfo_15_bits_meta_dirty,
+  output [1:0]   io_msInfo_15_bits_meta_state,
+  output         io_msInfo_15_bits_meta_clients,
+  output         io_msInfo_15_bits_meta_alias,
+  output         io_msInfo_15_bits_meta_prefetch,
+  output [3:0]   io_msInfo_15_bits_meta_prefetchSrc,
+  output         io_msInfo_15_bits_meta_accessed,
+  output         io_msInfo_15_bits_meta_tagErr,
+  output         io_msInfo_15_bits_meta_dataErr,
+  output [33:0]  io_msInfo_15_bits_metaTag,
+  output         io_msInfo_15_bits_dirHit,
+  output         io_msInfo_15_bits_isAcqOrPrefetch,
+  output         io_msInfo_15_bits_isPrefetch,
+  output [2:0]   io_msInfo_15_bits_param,
+  output         io_msInfo_15_bits_mergeA,
+  output         io_msInfo_15_bits_w_grantfirst,
+  output         io_msInfo_15_bits_w_grantlast,
+  output         io_msInfo_15_bits_w_grant,
+  output         io_msInfo_15_bits_s_release,
+  output         io_msInfo_15_bits_s_refill,
+  output         io_msInfo_15_bits_s_cmoresp,
+  output         io_msInfo_15_bits_s_cmometaw,
+  output         io_msInfo_15_bits_w_releaseack,
+  output         io_msInfo_15_bits_w_replResp,
+  output         io_msInfo_15_bits_w_rprobeacklast,
+  output         io_msInfo_15_bits_replaceData,
+  output         io_msInfo_15_bits_releaseToClean,
+  input          io_aMergeTask_valid,
+  input  [15:0]  io_aMergeTask_bits_idOH,
+  input  [5:0]   io_aMergeTask_bits_task_off,
+  input          io_aMergeTask_bits_task_alias,
+  input  [43:0]  io_aMergeTask_bits_task_vaddr,
+  input          io_aMergeTask_bits_task_isKeyword,
+  input  [3:0]   io_aMergeTask_bits_task_opcode,
+  input  [2:0]   io_aMergeTask_bits_task_param,
+  input  [6:0]   io_aMergeTask_bits_task_sourceId,
+  input          io_replResp_valid,
+  input  [33:0]  io_replResp_bits_tag,
+  input  [2:0]   io_replResp_bits_way,
+  input          io_replResp_bits_meta_dirty,
+  input  [1:0]   io_replResp_bits_meta_state,
+  input          io_replResp_bits_meta_clients,
+  input          io_replResp_bits_meta_alias,
+  input          io_replResp_bits_meta_prefetch,
+  input  [3:0]   io_replResp_bits_meta_prefetchSrc,
+  input          io_replResp_bits_meta_accessed,
+  input          io_replResp_bits_meta_tagErr,
+  input          io_replResp_bits_meta_dataErr,
+  input  [7:0]   io_replResp_bits_mshrId,
+  input          io_replResp_bits_retry,
+  output         io_pCrd_0_query_valid,
+  output [3:0]   io_pCrd_0_query_bits_pCrdType,
+  output [10:0]  io_pCrd_0_query_bits_srcID,
+  input          io_pCrd_0_grant,
+  output         io_pCrd_1_query_valid,
+  output [3:0]   io_pCrd_1_query_bits_pCrdType,
+  output [10:0]  io_pCrd_1_query_bits_srcID,
+  input          io_pCrd_1_grant,
+  output         io_pCrd_2_query_valid,
+  output [3:0]   io_pCrd_2_query_bits_pCrdType,
+  output [10:0]  io_pCrd_2_query_bits_srcID,
+  input          io_pCrd_2_grant,
+  output         io_pCrd_3_query_valid,
+  output [3:0]   io_pCrd_3_query_bits_pCrdType,
+  output [10:0]  io_pCrd_3_query_bits_srcID,
+  input          io_pCrd_3_grant,
+  output         io_pCrd_4_query_valid,
+  output [3:0]   io_pCrd_4_query_bits_pCrdType,
+  output [10:0]  io_pCrd_4_query_bits_srcID,
+  input          io_pCrd_4_grant,
+  output         io_pCrd_5_query_valid,
+  output [3:0]   io_pCrd_5_query_bits_pCrdType,
+  output [10:0]  io_pCrd_5_query_bits_srcID,
+  input          io_pCrd_5_grant,
+  output         io_pCrd_6_query_valid,
+  output [3:0]   io_pCrd_6_query_bits_pCrdType,
+  output [10:0]  io_pCrd_6_query_bits_srcID,
+  input          io_pCrd_6_grant,
+  output         io_pCrd_7_query_valid,
+  output [3:0]   io_pCrd_7_query_bits_pCrdType,
+  output [10:0]  io_pCrd_7_query_bits_srcID,
+  input          io_pCrd_7_grant,
+  output         io_pCrd_8_query_valid,
+  output [3:0]   io_pCrd_8_query_bits_pCrdType,
+  output [10:0]  io_pCrd_8_query_bits_srcID,
+  input          io_pCrd_8_grant,
+  output         io_pCrd_9_query_valid,
+  output [3:0]   io_pCrd_9_query_bits_pCrdType,
+  output [10:0]  io_pCrd_9_query_bits_srcID,
+  input          io_pCrd_9_grant,
+  output         io_pCrd_10_query_valid,
+  output [3:0]   io_pCrd_10_query_bits_pCrdType,
+  output [10:0]  io_pCrd_10_query_bits_srcID,
+  input          io_pCrd_10_grant,
+  output         io_pCrd_11_query_valid,
+  output [3:0]   io_pCrd_11_query_bits_pCrdType,
+  output [10:0]  io_pCrd_11_query_bits_srcID,
+  input          io_pCrd_11_grant,
+  output         io_pCrd_12_query_valid,
+  output [3:0]   io_pCrd_12_query_bits_pCrdType,
+  output [10:0]  io_pCrd_12_query_bits_srcID,
+  input          io_pCrd_12_grant,
+  output         io_pCrd_13_query_valid,
+  output [3:0]   io_pCrd_13_query_bits_pCrdType,
+  output [10:0]  io_pCrd_13_query_bits_srcID,
+  input          io_pCrd_13_grant,
+  output         io_pCrd_14_query_valid,
+  output [3:0]   io_pCrd_14_query_bits_pCrdType,
+  output [10:0]  io_pCrd_14_query_bits_srcID,
+  input          io_pCrd_14_grant,
+  output         io_pCrd_15_query_valid,
+  output [3:0]   io_pCrd_15_query_bits_pCrdType,
+  output [10:0]  io_pCrd_15_query_bits_srcID,
+  input          io_pCrd_15_grant,
+  output         io_l2Miss,
+  output [5:0]   io_perf_0_value,
+  output [5:0]   io_perf_1_value,
+  output [5:0]   io_perf_3_value
+);
+
+  wire        _mshr_task_arb_io_in_0_ready;
+  wire        _mshr_task_arb_io_in_1_ready;
+  wire        _mshr_task_arb_io_in_2_ready;
+  wire        _mshr_task_arb_io_in_3_ready;
+  wire        _mshr_task_arb_io_in_4_ready;
+  wire        _mshr_task_arb_io_in_5_ready;
+  wire        _mshr_task_arb_io_in_6_ready;
+  wire        _mshr_task_arb_io_in_7_ready;
+  wire        _mshr_task_arb_io_in_8_ready;
+  wire        _mshr_task_arb_io_in_9_ready;
+  wire        _mshr_task_arb_io_in_10_ready;
+  wire        _mshr_task_arb_io_in_11_ready;
+  wire        _mshr_task_arb_io_in_12_ready;
+  wire        _mshr_task_arb_io_in_13_ready;
+  wire        _mshr_task_arb_io_in_14_ready;
+  wire        _mshr_task_arb_io_in_15_ready;
+  wire [3:0]  _mshr_task_arb_io_chosen;
+  wire        _source_b_arb_io_in_0_ready;
+  wire        _source_b_arb_io_in_1_ready;
+  wire        _source_b_arb_io_in_2_ready;
+  wire        _source_b_arb_io_in_3_ready;
+  wire        _source_b_arb_io_in_4_ready;
+  wire        _source_b_arb_io_in_5_ready;
+  wire        _source_b_arb_io_in_6_ready;
+  wire        _source_b_arb_io_in_7_ready;
+  wire        _source_b_arb_io_in_8_ready;
+  wire        _source_b_arb_io_in_9_ready;
+  wire        _source_b_arb_io_in_10_ready;
+  wire        _source_b_arb_io_in_11_ready;
+  wire        _source_b_arb_io_in_12_ready;
+  wire        _source_b_arb_io_in_13_ready;
+  wire        _source_b_arb_io_in_14_ready;
+  wire        _source_b_arb_io_in_15_ready;
+  wire        _source_b_arb_io_out_valid;
+  wire [33:0] _source_b_arb_io_out_bits_tag;
+  wire [7:0]  _source_b_arb_io_out_bits_set;
+  wire [2:0]  _source_b_arb_io_out_bits_opcode;
+  wire [1:0]  _source_b_arb_io_out_bits_param;
+  wire        _source_b_arb_io_out_bits_alias;
+  wire        _sourceB_io_task_ready;
+  wire        _txrsp_arb_io_in_0_ready;
+  wire        _txrsp_arb_io_in_1_ready;
+  wire        _txrsp_arb_io_in_2_ready;
+  wire        _txrsp_arb_io_in_3_ready;
+  wire        _txrsp_arb_io_in_4_ready;
+  wire        _txrsp_arb_io_in_5_ready;
+  wire        _txrsp_arb_io_in_6_ready;
+  wire        _txrsp_arb_io_in_7_ready;
+  wire        _txrsp_arb_io_in_8_ready;
+  wire        _txrsp_arb_io_in_9_ready;
+  wire        _txrsp_arb_io_in_10_ready;
+  wire        _txrsp_arb_io_in_11_ready;
+  wire        _txrsp_arb_io_in_12_ready;
+  wire        _txrsp_arb_io_in_13_ready;
+  wire        _txrsp_arb_io_in_14_ready;
+  wire        _txrsp_arb_io_in_15_ready;
+  wire        _txreq_arb_io_in_0_ready;
+  wire        _txreq_arb_io_in_1_ready;
+  wire        _txreq_arb_io_in_2_ready;
+  wire        _txreq_arb_io_in_3_ready;
+  wire        _txreq_arb_io_in_4_ready;
+  wire        _txreq_arb_io_in_5_ready;
+  wire        _txreq_arb_io_in_6_ready;
+  wire        _txreq_arb_io_in_7_ready;
+  wire        _txreq_arb_io_in_8_ready;
+  wire        _txreq_arb_io_in_9_ready;
+  wire        _txreq_arb_io_in_10_ready;
+  wire        _txreq_arb_io_in_11_ready;
+  wire        _txreq_arb_io_in_12_ready;
+  wire        _txreq_arb_io_in_13_ready;
+  wire        _txreq_arb_io_in_14_ready;
+  wire        _txreq_arb_io_in_15_ready;
+  wire [15:0] _mshrSelector_io_out_bits;
+  wire        _mshrs_15_io_status_valid;
+  wire [2:0]  _mshrs_15_io_status_bits_channel;
+  wire [7:0]  _mshrs_15_io_status_bits_set;
+  wire [33:0] _mshrs_15_io_status_bits_reqTag;
+  wire [33:0] _mshrs_15_io_status_bits_metaTag;
+  wire        _mshrs_15_io_status_bits_needsRepl;
+  wire        _mshrs_15_io_status_bits_w_c_resp;
+  wire        _mshrs_15_io_status_bits_will_free;
+  wire [4:0]  _mshrs_15_io_status_bits_reqSource;
+  wire        _mshrs_15_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_15_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_15_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_15_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_15_io_tasks_txreq_bits_addr;
+  wire        _mshrs_15_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_15_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_15_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_15_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_15_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_15_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_15_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_15_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_15_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_15_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_15_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_15_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_15_io_tasks_source_b_bits_param;
+  wire        _mshrs_15_io_tasks_source_b_bits_alias;
+  wire        _mshrs_15_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_15_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_15_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_15_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_15_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_15_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_15_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_15_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_15_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_15_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_15_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_15_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_15_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_15_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_15_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_15_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_15_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_15_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_15_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_15_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_15_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_15_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_15_io_nestedwbData;
+  wire        _mshrs_14_io_status_valid;
+  wire [2:0]  _mshrs_14_io_status_bits_channel;
+  wire [7:0]  _mshrs_14_io_status_bits_set;
+  wire [33:0] _mshrs_14_io_status_bits_reqTag;
+  wire [33:0] _mshrs_14_io_status_bits_metaTag;
+  wire        _mshrs_14_io_status_bits_needsRepl;
+  wire        _mshrs_14_io_status_bits_w_c_resp;
+  wire        _mshrs_14_io_status_bits_will_free;
+  wire [4:0]  _mshrs_14_io_status_bits_reqSource;
+  wire        _mshrs_14_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_14_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_14_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_14_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_14_io_tasks_txreq_bits_addr;
+  wire        _mshrs_14_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_14_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_14_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_14_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_14_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_14_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_14_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_14_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_14_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_14_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_14_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_14_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_14_io_tasks_source_b_bits_param;
+  wire        _mshrs_14_io_tasks_source_b_bits_alias;
+  wire        _mshrs_14_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_14_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_14_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_14_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_14_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_14_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_14_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_14_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_14_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_14_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_14_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_14_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_14_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_14_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_14_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_14_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_14_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_14_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_14_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_14_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_14_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_14_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_14_io_nestedwbData;
+  wire        _mshrs_13_io_status_valid;
+  wire [2:0]  _mshrs_13_io_status_bits_channel;
+  wire [7:0]  _mshrs_13_io_status_bits_set;
+  wire [33:0] _mshrs_13_io_status_bits_reqTag;
+  wire [33:0] _mshrs_13_io_status_bits_metaTag;
+  wire        _mshrs_13_io_status_bits_needsRepl;
+  wire        _mshrs_13_io_status_bits_w_c_resp;
+  wire        _mshrs_13_io_status_bits_will_free;
+  wire [4:0]  _mshrs_13_io_status_bits_reqSource;
+  wire        _mshrs_13_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_13_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_13_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_13_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_13_io_tasks_txreq_bits_addr;
+  wire        _mshrs_13_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_13_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_13_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_13_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_13_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_13_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_13_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_13_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_13_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_13_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_13_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_13_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_13_io_tasks_source_b_bits_param;
+  wire        _mshrs_13_io_tasks_source_b_bits_alias;
+  wire        _mshrs_13_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_13_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_13_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_13_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_13_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_13_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_13_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_13_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_13_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_13_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_13_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_13_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_13_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_13_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_13_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_13_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_13_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_13_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_13_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_13_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_13_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_13_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_13_io_nestedwbData;
+  wire        _mshrs_12_io_status_valid;
+  wire [2:0]  _mshrs_12_io_status_bits_channel;
+  wire [7:0]  _mshrs_12_io_status_bits_set;
+  wire [33:0] _mshrs_12_io_status_bits_reqTag;
+  wire [33:0] _mshrs_12_io_status_bits_metaTag;
+  wire        _mshrs_12_io_status_bits_needsRepl;
+  wire        _mshrs_12_io_status_bits_w_c_resp;
+  wire        _mshrs_12_io_status_bits_will_free;
+  wire [4:0]  _mshrs_12_io_status_bits_reqSource;
+  wire        _mshrs_12_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_12_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_12_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_12_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_12_io_tasks_txreq_bits_addr;
+  wire        _mshrs_12_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_12_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_12_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_12_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_12_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_12_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_12_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_12_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_12_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_12_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_12_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_12_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_12_io_tasks_source_b_bits_param;
+  wire        _mshrs_12_io_tasks_source_b_bits_alias;
+  wire        _mshrs_12_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_12_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_12_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_12_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_12_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_12_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_12_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_12_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_12_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_12_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_12_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_12_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_12_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_12_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_12_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_12_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_12_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_12_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_12_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_12_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_12_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_12_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_12_io_nestedwbData;
+  wire        _mshrs_11_io_status_valid;
+  wire [2:0]  _mshrs_11_io_status_bits_channel;
+  wire [7:0]  _mshrs_11_io_status_bits_set;
+  wire [33:0] _mshrs_11_io_status_bits_reqTag;
+  wire [33:0] _mshrs_11_io_status_bits_metaTag;
+  wire        _mshrs_11_io_status_bits_needsRepl;
+  wire        _mshrs_11_io_status_bits_w_c_resp;
+  wire        _mshrs_11_io_status_bits_will_free;
+  wire [4:0]  _mshrs_11_io_status_bits_reqSource;
+  wire        _mshrs_11_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_11_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_11_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_11_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_11_io_tasks_txreq_bits_addr;
+  wire        _mshrs_11_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_11_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_11_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_11_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_11_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_11_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_11_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_11_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_11_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_11_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_11_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_11_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_11_io_tasks_source_b_bits_param;
+  wire        _mshrs_11_io_tasks_source_b_bits_alias;
+  wire        _mshrs_11_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_11_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_11_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_11_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_11_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_11_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_11_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_11_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_11_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_11_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_11_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_11_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_11_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_11_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_11_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_11_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_11_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_11_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_11_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_11_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_11_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_11_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_11_io_nestedwbData;
+  wire        _mshrs_10_io_status_valid;
+  wire [2:0]  _mshrs_10_io_status_bits_channel;
+  wire [7:0]  _mshrs_10_io_status_bits_set;
+  wire [33:0] _mshrs_10_io_status_bits_reqTag;
+  wire [33:0] _mshrs_10_io_status_bits_metaTag;
+  wire        _mshrs_10_io_status_bits_needsRepl;
+  wire        _mshrs_10_io_status_bits_w_c_resp;
+  wire        _mshrs_10_io_status_bits_will_free;
+  wire [4:0]  _mshrs_10_io_status_bits_reqSource;
+  wire        _mshrs_10_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_10_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_10_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_10_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_10_io_tasks_txreq_bits_addr;
+  wire        _mshrs_10_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_10_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_10_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_10_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_10_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_10_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_10_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_10_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_10_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_10_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_10_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_10_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_10_io_tasks_source_b_bits_param;
+  wire        _mshrs_10_io_tasks_source_b_bits_alias;
+  wire        _mshrs_10_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_10_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_10_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_10_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_10_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_10_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_10_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_10_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_10_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_10_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_10_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_10_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_10_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_10_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_10_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_10_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_10_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_10_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_10_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_10_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_10_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_10_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_10_io_nestedwbData;
+  wire        _mshrs_9_io_status_valid;
+  wire [2:0]  _mshrs_9_io_status_bits_channel;
+  wire [7:0]  _mshrs_9_io_status_bits_set;
+  wire [33:0] _mshrs_9_io_status_bits_reqTag;
+  wire [33:0] _mshrs_9_io_status_bits_metaTag;
+  wire        _mshrs_9_io_status_bits_needsRepl;
+  wire        _mshrs_9_io_status_bits_w_c_resp;
+  wire        _mshrs_9_io_status_bits_will_free;
+  wire [4:0]  _mshrs_9_io_status_bits_reqSource;
+  wire        _mshrs_9_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_9_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_9_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_9_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_9_io_tasks_txreq_bits_addr;
+  wire        _mshrs_9_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_9_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_9_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_9_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_9_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_9_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_9_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_9_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_9_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_9_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_9_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_9_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_9_io_tasks_source_b_bits_param;
+  wire        _mshrs_9_io_tasks_source_b_bits_alias;
+  wire        _mshrs_9_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_9_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_9_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_9_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_9_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_9_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_9_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_9_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_9_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_9_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_9_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_9_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_9_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_9_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_9_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_9_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_9_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_9_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_9_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_9_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_9_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_9_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_9_io_nestedwbData;
+  wire        _mshrs_8_io_status_valid;
+  wire [2:0]  _mshrs_8_io_status_bits_channel;
+  wire [7:0]  _mshrs_8_io_status_bits_set;
+  wire [33:0] _mshrs_8_io_status_bits_reqTag;
+  wire [33:0] _mshrs_8_io_status_bits_metaTag;
+  wire        _mshrs_8_io_status_bits_needsRepl;
+  wire        _mshrs_8_io_status_bits_w_c_resp;
+  wire        _mshrs_8_io_status_bits_will_free;
+  wire [4:0]  _mshrs_8_io_status_bits_reqSource;
+  wire        _mshrs_8_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_8_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_8_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_8_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_8_io_tasks_txreq_bits_addr;
+  wire        _mshrs_8_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_8_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_8_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_8_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_8_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_8_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_8_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_8_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_8_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_8_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_8_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_8_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_8_io_tasks_source_b_bits_param;
+  wire        _mshrs_8_io_tasks_source_b_bits_alias;
+  wire        _mshrs_8_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_8_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_8_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_8_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_8_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_8_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_8_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_8_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_8_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_8_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_8_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_8_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_8_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_8_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_8_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_8_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_8_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_8_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_8_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_8_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_8_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_8_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_8_io_nestedwbData;
+  wire        _mshrs_7_io_status_valid;
+  wire [2:0]  _mshrs_7_io_status_bits_channel;
+  wire [7:0]  _mshrs_7_io_status_bits_set;
+  wire [33:0] _mshrs_7_io_status_bits_reqTag;
+  wire [33:0] _mshrs_7_io_status_bits_metaTag;
+  wire        _mshrs_7_io_status_bits_needsRepl;
+  wire        _mshrs_7_io_status_bits_w_c_resp;
+  wire        _mshrs_7_io_status_bits_will_free;
+  wire [4:0]  _mshrs_7_io_status_bits_reqSource;
+  wire        _mshrs_7_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_7_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_7_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_7_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_7_io_tasks_txreq_bits_addr;
+  wire        _mshrs_7_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_7_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_7_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_7_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_7_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_7_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_7_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_7_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_7_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_7_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_7_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_7_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_7_io_tasks_source_b_bits_param;
+  wire        _mshrs_7_io_tasks_source_b_bits_alias;
+  wire        _mshrs_7_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_7_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_7_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_7_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_7_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_7_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_7_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_7_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_7_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_7_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_7_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_7_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_7_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_7_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_7_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_7_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_7_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_7_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_7_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_7_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_7_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_7_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_7_io_nestedwbData;
+  wire        _mshrs_6_io_status_valid;
+  wire [2:0]  _mshrs_6_io_status_bits_channel;
+  wire [7:0]  _mshrs_6_io_status_bits_set;
+  wire [33:0] _mshrs_6_io_status_bits_reqTag;
+  wire [33:0] _mshrs_6_io_status_bits_metaTag;
+  wire        _mshrs_6_io_status_bits_needsRepl;
+  wire        _mshrs_6_io_status_bits_w_c_resp;
+  wire        _mshrs_6_io_status_bits_will_free;
+  wire [4:0]  _mshrs_6_io_status_bits_reqSource;
+  wire        _mshrs_6_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_6_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_6_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_6_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_6_io_tasks_txreq_bits_addr;
+  wire        _mshrs_6_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_6_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_6_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_6_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_6_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_6_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_6_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_6_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_6_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_6_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_6_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_6_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_6_io_tasks_source_b_bits_param;
+  wire        _mshrs_6_io_tasks_source_b_bits_alias;
+  wire        _mshrs_6_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_6_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_6_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_6_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_6_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_6_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_6_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_6_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_6_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_6_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_6_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_6_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_6_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_6_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_6_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_6_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_6_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_6_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_6_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_6_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_6_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_6_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_6_io_nestedwbData;
+  wire        _mshrs_5_io_status_valid;
+  wire [2:0]  _mshrs_5_io_status_bits_channel;
+  wire [7:0]  _mshrs_5_io_status_bits_set;
+  wire [33:0] _mshrs_5_io_status_bits_reqTag;
+  wire [33:0] _mshrs_5_io_status_bits_metaTag;
+  wire        _mshrs_5_io_status_bits_needsRepl;
+  wire        _mshrs_5_io_status_bits_w_c_resp;
+  wire        _mshrs_5_io_status_bits_will_free;
+  wire [4:0]  _mshrs_5_io_status_bits_reqSource;
+  wire        _mshrs_5_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_5_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_5_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_5_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_5_io_tasks_txreq_bits_addr;
+  wire        _mshrs_5_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_5_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_5_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_5_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_5_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_5_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_5_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_5_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_5_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_5_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_5_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_5_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_5_io_tasks_source_b_bits_param;
+  wire        _mshrs_5_io_tasks_source_b_bits_alias;
+  wire        _mshrs_5_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_5_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_5_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_5_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_5_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_5_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_5_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_5_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_5_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_5_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_5_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_5_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_5_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_5_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_5_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_5_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_5_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_5_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_5_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_5_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_5_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_5_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_5_io_nestedwbData;
+  wire        _mshrs_4_io_status_valid;
+  wire [2:0]  _mshrs_4_io_status_bits_channel;
+  wire [7:0]  _mshrs_4_io_status_bits_set;
+  wire [33:0] _mshrs_4_io_status_bits_reqTag;
+  wire [33:0] _mshrs_4_io_status_bits_metaTag;
+  wire        _mshrs_4_io_status_bits_needsRepl;
+  wire        _mshrs_4_io_status_bits_w_c_resp;
+  wire        _mshrs_4_io_status_bits_will_free;
+  wire [4:0]  _mshrs_4_io_status_bits_reqSource;
+  wire        _mshrs_4_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_4_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_4_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_4_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_4_io_tasks_txreq_bits_addr;
+  wire        _mshrs_4_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_4_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_4_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_4_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_4_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_4_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_4_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_4_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_4_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_4_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_4_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_4_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_4_io_tasks_source_b_bits_param;
+  wire        _mshrs_4_io_tasks_source_b_bits_alias;
+  wire        _mshrs_4_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_4_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_4_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_4_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_4_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_4_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_4_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_4_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_4_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_4_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_4_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_4_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_4_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_4_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_4_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_4_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_4_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_4_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_4_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_4_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_4_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_4_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_4_io_nestedwbData;
+  wire        _mshrs_3_io_status_valid;
+  wire [2:0]  _mshrs_3_io_status_bits_channel;
+  wire [7:0]  _mshrs_3_io_status_bits_set;
+  wire [33:0] _mshrs_3_io_status_bits_reqTag;
+  wire [33:0] _mshrs_3_io_status_bits_metaTag;
+  wire        _mshrs_3_io_status_bits_needsRepl;
+  wire        _mshrs_3_io_status_bits_w_c_resp;
+  wire        _mshrs_3_io_status_bits_will_free;
+  wire [4:0]  _mshrs_3_io_status_bits_reqSource;
+  wire        _mshrs_3_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_3_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_3_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_3_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_3_io_tasks_txreq_bits_addr;
+  wire        _mshrs_3_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_3_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_3_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_3_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_3_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_3_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_3_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_3_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_3_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_3_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_3_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_3_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_3_io_tasks_source_b_bits_param;
+  wire        _mshrs_3_io_tasks_source_b_bits_alias;
+  wire        _mshrs_3_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_3_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_3_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_3_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_3_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_3_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_3_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_3_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_3_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_3_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_3_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_3_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_3_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_3_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_3_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_3_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_3_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_3_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_3_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_3_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_3_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_3_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_3_io_nestedwbData;
+  wire        _mshrs_2_io_status_valid;
+  wire [2:0]  _mshrs_2_io_status_bits_channel;
+  wire [7:0]  _mshrs_2_io_status_bits_set;
+  wire [33:0] _mshrs_2_io_status_bits_reqTag;
+  wire [33:0] _mshrs_2_io_status_bits_metaTag;
+  wire        _mshrs_2_io_status_bits_needsRepl;
+  wire        _mshrs_2_io_status_bits_w_c_resp;
+  wire        _mshrs_2_io_status_bits_will_free;
+  wire [4:0]  _mshrs_2_io_status_bits_reqSource;
+  wire        _mshrs_2_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_2_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_2_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_2_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_2_io_tasks_txreq_bits_addr;
+  wire        _mshrs_2_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_2_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_2_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_2_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_2_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_2_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_2_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_2_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_2_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_2_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_2_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_2_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_2_io_tasks_source_b_bits_param;
+  wire        _mshrs_2_io_tasks_source_b_bits_alias;
+  wire        _mshrs_2_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_2_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_2_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_2_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_2_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_2_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_2_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_2_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_2_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_2_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_2_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_2_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_2_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_2_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_2_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_2_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_2_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_2_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_2_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_2_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_2_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_2_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_2_io_nestedwbData;
+  wire        _mshrs_1_io_status_valid;
+  wire [2:0]  _mshrs_1_io_status_bits_channel;
+  wire [7:0]  _mshrs_1_io_status_bits_set;
+  wire [33:0] _mshrs_1_io_status_bits_reqTag;
+  wire [33:0] _mshrs_1_io_status_bits_metaTag;
+  wire        _mshrs_1_io_status_bits_needsRepl;
+  wire        _mshrs_1_io_status_bits_w_c_resp;
+  wire        _mshrs_1_io_status_bits_will_free;
+  wire [4:0]  _mshrs_1_io_status_bits_reqSource;
+  wire        _mshrs_1_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_1_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_1_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_1_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_1_io_tasks_txreq_bits_addr;
+  wire        _mshrs_1_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_1_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_1_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_1_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_1_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_1_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_1_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_1_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_1_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_1_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_1_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_1_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_1_io_tasks_source_b_bits_param;
+  wire        _mshrs_1_io_tasks_source_b_bits_alias;
+  wire        _mshrs_1_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_1_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_1_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_1_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_1_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_1_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_1_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_1_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_1_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_1_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_1_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_1_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_1_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_1_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_1_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_1_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_1_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_1_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_1_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_1_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_1_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_1_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_1_io_nestedwbData;
+  wire        _mshrs_0_io_status_valid;
+  wire [2:0]  _mshrs_0_io_status_bits_channel;
+  wire [7:0]  _mshrs_0_io_status_bits_set;
+  wire [33:0] _mshrs_0_io_status_bits_reqTag;
+  wire [33:0] _mshrs_0_io_status_bits_metaTag;
+  wire        _mshrs_0_io_status_bits_needsRepl;
+  wire        _mshrs_0_io_status_bits_w_c_resp;
+  wire        _mshrs_0_io_status_bits_will_free;
+  wire [4:0]  _mshrs_0_io_status_bits_reqSource;
+  wire        _mshrs_0_io_tasks_txreq_valid;
+  wire [10:0] _mshrs_0_io_tasks_txreq_bits_tgtID;
+  wire [11:0] _mshrs_0_io_tasks_txreq_bits_txnID;
+  wire [6:0]  _mshrs_0_io_tasks_txreq_bits_opcode;
+  wire [47:0] _mshrs_0_io_tasks_txreq_bits_addr;
+  wire        _mshrs_0_io_tasks_txreq_bits_likelyshared;
+  wire        _mshrs_0_io_tasks_txreq_bits_allowRetry;
+  wire [3:0]  _mshrs_0_io_tasks_txreq_bits_pCrdType;
+  wire        _mshrs_0_io_tasks_txreq_bits_memAttr_allocate;
+  wire        _mshrs_0_io_tasks_txreq_bits_expCompAck;
+  wire        _mshrs_0_io_tasks_txrsp_valid;
+  wire [10:0] _mshrs_0_io_tasks_txrsp_bits_tgtID;
+  wire [11:0] _mshrs_0_io_tasks_txrsp_bits_txnID;
+  wire        _mshrs_0_io_tasks_txrsp_bits_traceTag;
+  wire        _mshrs_0_io_tasks_source_b_valid;
+  wire [33:0] _mshrs_0_io_tasks_source_b_bits_tag;
+  wire [7:0]  _mshrs_0_io_tasks_source_b_bits_set;
+  wire [1:0]  _mshrs_0_io_tasks_source_b_bits_param;
+  wire        _mshrs_0_io_tasks_source_b_bits_alias;
+  wire        _mshrs_0_io_tasks_mainpipe_valid;
+  wire [2:0]  _mshrs_0_io_tasks_mainpipe_bits_channel;
+  wire [2:0]  _mshrs_0_io_tasks_mainpipe_bits_txChannel;
+  wire [7:0]  _mshrs_0_io_tasks_mainpipe_bits_set;
+  wire [33:0] _mshrs_0_io_tasks_mainpipe_bits_tag;
+  wire [5:0]  _mshrs_0_io_tasks_mainpipe_bits_off;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_alias;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_isKeyword;
+  wire [3:0]  _mshrs_0_io_tasks_mainpipe_bits_opcode;
+  wire [2:0]  _mshrs_0_io_tasks_mainpipe_bits_param;
+  wire [2:0]  _mshrs_0_io_tasks_mainpipe_bits_size;
+  wire [6:0]  _mshrs_0_io_tasks_mainpipe_bits_sourceId;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_denied;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_corrupt;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_aliasTask;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_useProbeData;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_mshrRetry;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_readProbeDataDown;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_fromL2pft;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_dirty;
+  wire [2:0]  _mshrs_0_io_tasks_mainpipe_bits_way;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_meta_dirty;
+  wire [1:0]  _mshrs_0_io_tasks_mainpipe_bits_meta_state;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_meta_clients;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_meta_alias;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_meta_prefetch;
+  wire [3:0]  _mshrs_0_io_tasks_mainpipe_bits_meta_prefetchSrc;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_meta_accessed;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_meta_tagErr;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_meta_dataErr;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_metaWen;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_tagWen;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_dsWen;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_replTask;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_cmoTask;
+  wire [4:0]  _mshrs_0_io_tasks_mainpipe_bits_reqSource;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_mergeA;
+  wire [5:0]  _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_off;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_alias;
+  wire [43:0] _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_vaddr;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_isKeyword;
+  wire [2:0]  _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_opcode;
+  wire [2:0]  _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_param;
+  wire [6:0]  _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_sourceId;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_state;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_clients;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_alias;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_accessed;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitRelease;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseToInval;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseToClean;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseWithData;
+  wire [7:0]  _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseIdx;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_state;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _mshrs_0_io_tasks_mainpipe_bits_tgtID;
+  wire [11:0] _mshrs_0_io_tasks_mainpipe_bits_txnID;
+  wire [10:0] _mshrs_0_io_tasks_mainpipe_bits_homeNID;
+  wire [11:0] _mshrs_0_io_tasks_mainpipe_bits_dbID;
+  wire [6:0]  _mshrs_0_io_tasks_mainpipe_bits_chiOpcode;
+  wire [2:0]  _mshrs_0_io_tasks_mainpipe_bits_resp;
+  wire [2:0]  _mshrs_0_io_tasks_mainpipe_bits_fwdState;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_retToSrc;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_likelyshared;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_expCompAck;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_allowRetry;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_memAttr_allocate;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_memAttr_cacheable;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_memAttr_ewa;
+  wire        _mshrs_0_io_tasks_mainpipe_bits_traceTag;
+  wire        _mshrs_0_io_nestedwbData;
+  wire [4:0]  _a_mshrFull_T =
+    5'({3'h0, 2'({1'h0, io_pipeStatusVec_1_valid} + {1'h0, io_pipeStatusVec_0_valid})}
+       + 5'({1'h0,
+             4'({1'h0,
+                 3'({1'h0,
+                     2'({1'h0, _mshrs_15_io_status_valid}
+                        + {1'h0, _mshrs_14_io_status_valid})}
+                    + {1'h0,
+                       2'({1'h0, _mshrs_13_io_status_valid}
+                          + {1'h0, _mshrs_12_io_status_valid})})}
+                + {1'h0,
+                   3'({1'h0,
+                       2'({1'h0, _mshrs_11_io_status_valid}
+                          + {1'h0, _mshrs_10_io_status_valid})}
+                      + {1'h0,
+                         2'({1'h0, _mshrs_9_io_status_valid}
+                            + {1'h0, _mshrs_8_io_status_valid})})})}
+            + {1'h0,
+               4'({1'h0,
+                   3'({1'h0,
+                       2'({1'h0, _mshrs_7_io_status_valid}
+                          + {1'h0, _mshrs_6_io_status_valid})}
+                      + {1'h0,
+                         2'({1'h0, _mshrs_5_io_status_valid}
+                            + {1'h0, _mshrs_4_io_status_valid})})}
+                  + {1'h0,
+                     3'({1'h0,
+                         2'({1'h0, _mshrs_3_io_status_valid}
+                            + {1'h0, _mshrs_2_io_status_valid})}
+                        + {1'h0,
+                           2'({1'h0, _mshrs_1_io_status_valid}
+                              + {1'h0, _mshrs_0_io_status_valid})})})}));
+  wire [6:0]  _io_toMainPipe_mshr_alloc_ptr_T_1 =
+    _mshrSelector_io_out_bits[15:9] | _mshrSelector_io_out_bits[7:1];
+  wire [2:0]  _io_toMainPipe_mshr_alloc_ptr_T_3 =
+    _io_toMainPipe_mshr_alloc_ptr_T_1[6:4] | _io_toMainPipe_mshr_alloc_ptr_T_1[2:0];
+  wire        resp_sinkC_match_vec_0 =
+    _mshrs_0_io_status_valid & _mshrs_0_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_0_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_0_io_status_bits_needsRepl
+                               ? _mshrs_0_io_status_bits_metaTag
+                               : _mshrs_0_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_1 =
+    _mshrs_1_io_status_valid & _mshrs_1_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_1_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_1_io_status_bits_needsRepl
+                               ? _mshrs_1_io_status_bits_metaTag
+                               : _mshrs_1_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_2 =
+    _mshrs_2_io_status_valid & _mshrs_2_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_2_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_2_io_status_bits_needsRepl
+                               ? _mshrs_2_io_status_bits_metaTag
+                               : _mshrs_2_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_3 =
+    _mshrs_3_io_status_valid & _mshrs_3_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_3_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_3_io_status_bits_needsRepl
+                               ? _mshrs_3_io_status_bits_metaTag
+                               : _mshrs_3_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_4 =
+    _mshrs_4_io_status_valid & _mshrs_4_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_4_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_4_io_status_bits_needsRepl
+                               ? _mshrs_4_io_status_bits_metaTag
+                               : _mshrs_4_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_5 =
+    _mshrs_5_io_status_valid & _mshrs_5_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_5_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_5_io_status_bits_needsRepl
+                               ? _mshrs_5_io_status_bits_metaTag
+                               : _mshrs_5_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_6 =
+    _mshrs_6_io_status_valid & _mshrs_6_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_6_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_6_io_status_bits_needsRepl
+                               ? _mshrs_6_io_status_bits_metaTag
+                               : _mshrs_6_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_7 =
+    _mshrs_7_io_status_valid & _mshrs_7_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_7_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_7_io_status_bits_needsRepl
+                               ? _mshrs_7_io_status_bits_metaTag
+                               : _mshrs_7_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_8 =
+    _mshrs_8_io_status_valid & _mshrs_8_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_8_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_8_io_status_bits_needsRepl
+                               ? _mshrs_8_io_status_bits_metaTag
+                               : _mshrs_8_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_9 =
+    _mshrs_9_io_status_valid & _mshrs_9_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_9_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_9_io_status_bits_needsRepl
+                               ? _mshrs_9_io_status_bits_metaTag
+                               : _mshrs_9_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_10 =
+    _mshrs_10_io_status_valid & _mshrs_10_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_10_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_10_io_status_bits_needsRepl
+                               ? _mshrs_10_io_status_bits_metaTag
+                               : _mshrs_10_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_11 =
+    _mshrs_11_io_status_valid & _mshrs_11_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_11_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_11_io_status_bits_needsRepl
+                               ? _mshrs_11_io_status_bits_metaTag
+                               : _mshrs_11_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_12 =
+    _mshrs_12_io_status_valid & _mshrs_12_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_12_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_12_io_status_bits_needsRepl
+                               ? _mshrs_12_io_status_bits_metaTag
+                               : _mshrs_12_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_13 =
+    _mshrs_13_io_status_valid & _mshrs_13_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_13_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_13_io_status_bits_needsRepl
+                               ? _mshrs_13_io_status_bits_metaTag
+                               : _mshrs_13_io_status_bits_reqTag);
+  wire        resp_sinkC_match_vec_14 =
+    _mshrs_14_io_status_valid & _mshrs_14_io_status_bits_w_c_resp
+    & io_resps_sinkC_set == _mshrs_14_io_status_bits_set
+    & io_resps_sinkC_tag == (_mshrs_14_io_status_bits_needsRepl
+                               ? _mshrs_14_io_status_bits_metaTag
+                               : _mshrs_14_io_status_bits_reqTag);
+  wire        mshrs_0_io_alloc_valid =
+    _mshrSelector_io_out_bits[0] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_1_io_alloc_valid =
+    _mshrSelector_io_out_bits[1] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_2_io_alloc_valid =
+    _mshrSelector_io_out_bits[2] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_3_io_alloc_valid =
+    _mshrSelector_io_out_bits[3] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_4_io_alloc_valid =
+    _mshrSelector_io_out_bits[4] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_5_io_alloc_valid =
+    _mshrSelector_io_out_bits[5] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_6_io_alloc_valid =
+    _mshrSelector_io_out_bits[6] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_7_io_alloc_valid =
+    _mshrSelector_io_out_bits[7] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_8_io_alloc_valid =
+    _mshrSelector_io_out_bits[8] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_9_io_alloc_valid =
+    _mshrSelector_io_out_bits[9] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_10_io_alloc_valid =
+    _mshrSelector_io_out_bits[10] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_11_io_alloc_valid =
+    _mshrSelector_io_out_bits[11] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_12_io_alloc_valid =
+    _mshrSelector_io_out_bits[12] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_13_io_alloc_valid =
+    _mshrSelector_io_out_bits[13] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_14_io_alloc_valid =
+    _mshrSelector_io_out_bits[14] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        mshrs_15_io_alloc_valid =
+    _mshrSelector_io_out_bits[15] & io_fromMainPipe_mshr_alloc_s3_valid;
+  wire        _io_releaseBufWriteId_T = resp_sinkC_match_vec_0 | resp_sinkC_match_vec_1;
+  wire        _io_releaseBufWriteId_T_4 =
+    _io_releaseBufWriteId_T | resp_sinkC_match_vec_2 | resp_sinkC_match_vec_3;
+  wire        _io_releaseBufWriteId_T_6 = resp_sinkC_match_vec_4 | resp_sinkC_match_vec_5;
+  wire        _io_releaseBufWriteId_T_14 =
+    resp_sinkC_match_vec_8 | resp_sinkC_match_vec_9;
+  wire        _io_nestedwbDataId_bits_T =
+    _mshrs_0_io_nestedwbData | _mshrs_1_io_nestedwbData;
+  wire        _io_nestedwbDataId_bits_T_4 =
+    _io_nestedwbDataId_bits_T | _mshrs_2_io_nestedwbData | _mshrs_3_io_nestedwbData;
+  wire        _io_nestedwbDataId_bits_T_6 =
+    _mshrs_4_io_nestedwbData | _mshrs_5_io_nestedwbData;
+  wire        _io_nestedwbDataId_bits_T_14 =
+    _mshrs_8_io_nestedwbData | _mshrs_9_io_nestedwbData;
+  reg  [9:0]  hpm_timers_0;
+  reg  [9:0]  hpm_timers_1;
+  reg  [9:0]  hpm_timers_2;
+  reg  [9:0]  hpm_timers_3;
+  reg  [9:0]  hpm_timers_4;
+  reg  [9:0]  hpm_timers_5;
+  reg  [9:0]  hpm_timers_6;
+  reg  [9:0]  hpm_timers_7;
+  reg  [9:0]  hpm_timers_8;
+  reg  [9:0]  hpm_timers_9;
+  reg  [9:0]  hpm_timers_10;
+  reg  [9:0]  hpm_timers_11;
+  reg  [9:0]  hpm_timers_12;
+  reg  [9:0]  hpm_timers_13;
+  reg  [9:0]  hpm_timers_14;
+  reg  [9:0]  hpm_timers_15;
+  reg         io_perf_0_value_REG;
+  reg         io_perf_0_value_REG_1;
+  reg         io_perf_1_value_REG;
+  reg         io_perf_1_value_REG_1;
+  reg  [3:0]  io_perf_3_value_REG;
+  reg  [3:0]  io_perf_3_value_REG_1;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      hpm_timers_0 <= 10'h0;
+      hpm_timers_1 <= 10'h0;
+      hpm_timers_2 <= 10'h0;
+      hpm_timers_3 <= 10'h0;
+      hpm_timers_4 <= 10'h0;
+      hpm_timers_5 <= 10'h0;
+      hpm_timers_6 <= 10'h0;
+      hpm_timers_7 <= 10'h0;
+      hpm_timers_8 <= 10'h0;
+      hpm_timers_9 <= 10'h0;
+      hpm_timers_10 <= 10'h0;
+      hpm_timers_11 <= 10'h0;
+      hpm_timers_12 <= 10'h0;
+      hpm_timers_13 <= 10'h0;
+      hpm_timers_14 <= 10'h0;
+      hpm_timers_15 <= 10'h0;
+    end
+    else begin
+      hpm_timers_0 <= mshrs_0_io_alloc_valid ? 10'h1 : 10'(hpm_timers_0 + 10'h1);
+      hpm_timers_1 <= mshrs_1_io_alloc_valid ? 10'h1 : 10'(hpm_timers_1 + 10'h1);
+      hpm_timers_2 <= mshrs_2_io_alloc_valid ? 10'h1 : 10'(hpm_timers_2 + 10'h1);
+      hpm_timers_3 <= mshrs_3_io_alloc_valid ? 10'h1 : 10'(hpm_timers_3 + 10'h1);
+      hpm_timers_4 <= mshrs_4_io_alloc_valid ? 10'h1 : 10'(hpm_timers_4 + 10'h1);
+      hpm_timers_5 <= mshrs_5_io_alloc_valid ? 10'h1 : 10'(hpm_timers_5 + 10'h1);
+      hpm_timers_6 <= mshrs_6_io_alloc_valid ? 10'h1 : 10'(hpm_timers_6 + 10'h1);
+      hpm_timers_7 <= mshrs_7_io_alloc_valid ? 10'h1 : 10'(hpm_timers_7 + 10'h1);
+      hpm_timers_8 <= mshrs_8_io_alloc_valid ? 10'h1 : 10'(hpm_timers_8 + 10'h1);
+      hpm_timers_9 <= mshrs_9_io_alloc_valid ? 10'h1 : 10'(hpm_timers_9 + 10'h1);
+      hpm_timers_10 <= mshrs_10_io_alloc_valid ? 10'h1 : 10'(hpm_timers_10 + 10'h1);
+      hpm_timers_11 <= mshrs_11_io_alloc_valid ? 10'h1 : 10'(hpm_timers_11 + 10'h1);
+      hpm_timers_12 <= mshrs_12_io_alloc_valid ? 10'h1 : 10'(hpm_timers_12 + 10'h1);
+      hpm_timers_13 <= mshrs_13_io_alloc_valid ? 10'h1 : 10'(hpm_timers_13 + 10'h1);
+      hpm_timers_14 <= mshrs_14_io_alloc_valid ? 10'h1 : 10'(hpm_timers_14 + 10'h1);
+      hpm_timers_15 <= mshrs_15_io_alloc_valid ? 10'h1 : 10'(hpm_timers_15 + 10'h1);
+    end
+  end // always @(posedge, posedge)
+  wire        perfEvents_0_2 = io_resps_rxdat_valid & io_resps_rxdat_respInfo_last;
+  always @(posedge clock) begin
+    io_perf_0_value_REG <= perfEvents_0_2;
+    io_perf_0_value_REG_1 <= io_perf_0_value_REG;
+    io_perf_1_value_REG <= perfEvents_0_2;
+    io_perf_1_value_REG_1 <= io_perf_1_value_REG;
+    io_perf_3_value_REG <=
+      4'(4'(4'(4'({3'h0,
+                   _mshrs_0_io_status_valid & _mshrs_0_io_status_bits_will_free
+                     & hpm_timers_0 > 10'hC8}
+                  + {3'h0,
+                     _mshrs_1_io_status_valid & _mshrs_1_io_status_bits_will_free
+                       & hpm_timers_1 > 10'hC8})
+               + 4'({3'h0,
+                     _mshrs_2_io_status_valid & _mshrs_2_io_status_bits_will_free
+                       & hpm_timers_2 > 10'hC8}
+                    + {3'h0,
+                       _mshrs_3_io_status_valid & _mshrs_3_io_status_bits_will_free
+                         & hpm_timers_3 > 10'hC8}))
+            + 4'(4'({3'h0,
+                     _mshrs_4_io_status_valid & _mshrs_4_io_status_bits_will_free
+                       & hpm_timers_4 > 10'hC8}
+                    + {3'h0,
+                       _mshrs_5_io_status_valid & _mshrs_5_io_status_bits_will_free
+                         & hpm_timers_5 > 10'hC8})
+                 + 4'({3'h0,
+                       _mshrs_6_io_status_valid & _mshrs_6_io_status_bits_will_free
+                         & hpm_timers_6 > 10'hC8}
+                      + {3'h0,
+                         _mshrs_7_io_status_valid & _mshrs_7_io_status_bits_will_free
+                           & hpm_timers_7 > 10'hC8})))
+         + 4'(4'(4'({3'h0,
+                     _mshrs_8_io_status_valid & _mshrs_8_io_status_bits_will_free
+                       & hpm_timers_8 > 10'hC8}
+                    + {3'h0,
+                       _mshrs_9_io_status_valid & _mshrs_9_io_status_bits_will_free
+                         & hpm_timers_9 > 10'hC8})
+                 + 4'({3'h0,
+                       _mshrs_10_io_status_valid & _mshrs_10_io_status_bits_will_free
+                         & hpm_timers_10 > 10'hC8}
+                      + {3'h0,
+                         _mshrs_11_io_status_valid & _mshrs_11_io_status_bits_will_free
+                           & hpm_timers_11 > 10'hC8}))
+              + 4'(4'({3'h0,
+                       _mshrs_12_io_status_valid & _mshrs_12_io_status_bits_will_free
+                         & hpm_timers_12 > 10'hC8}
+                      + {3'h0,
+                         _mshrs_13_io_status_valid & _mshrs_13_io_status_bits_will_free
+                           & hpm_timers_13 > 10'hC8})
+                   + 4'({3'h0,
+                         _mshrs_14_io_status_valid & _mshrs_14_io_status_bits_will_free
+                           & hpm_timers_14 > 10'hC8}
+                        + {3'h0,
+                           _mshrs_15_io_status_valid & _mshrs_15_io_status_bits_will_free
+                             & hpm_timers_15 > 10'hC8}))));
+    io_perf_3_value_REG_1 <= io_perf_3_value_REG;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:133];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [7:0] i = 8'h0; i < 8'h86; i += 8'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        hpm_timers_0 = _RANDOM[8'h80][10:1];
+        hpm_timers_1 = _RANDOM[8'h80][20:11];
+        hpm_timers_2 = _RANDOM[8'h80][30:21];
+        hpm_timers_3 = {_RANDOM[8'h80][31], _RANDOM[8'h81][8:0]};
+        hpm_timers_4 = _RANDOM[8'h81][18:9];
+        hpm_timers_5 = _RANDOM[8'h81][28:19];
+        hpm_timers_6 = {_RANDOM[8'h81][31:29], _RANDOM[8'h82][6:0]};
+        hpm_timers_7 = _RANDOM[8'h82][16:7];
+        hpm_timers_8 = _RANDOM[8'h82][26:17];
+        hpm_timers_9 = {_RANDOM[8'h82][31:27], _RANDOM[8'h83][4:0]};
+        hpm_timers_10 = _RANDOM[8'h83][14:5];
+        hpm_timers_11 = _RANDOM[8'h83][24:15];
+        hpm_timers_12 = {_RANDOM[8'h83][31:25], _RANDOM[8'h84][2:0]};
+        hpm_timers_13 = _RANDOM[8'h84][12:3];
+        hpm_timers_14 = _RANDOM[8'h84][22:13];
+        hpm_timers_15 = {_RANDOM[8'h84][31:23], _RANDOM[8'h85][0]};
+        io_perf_0_value_REG = _RANDOM[8'h85][1];
+        io_perf_0_value_REG_1 = _RANDOM[8'h85][2];
+        io_perf_1_value_REG = _RANDOM[8'h85][3];
+        io_perf_1_value_REG_1 = _RANDOM[8'h85][4];
+        io_perf_3_value_REG = _RANDOM[8'h85][10:7];
+        io_perf_3_value_REG_1 = _RANDOM[8'h85][14:11];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        hpm_timers_0 = 10'h0;
+        hpm_timers_1 = 10'h0;
+        hpm_timers_2 = 10'h0;
+        hpm_timers_3 = 10'h0;
+        hpm_timers_4 = 10'h0;
+        hpm_timers_5 = 10'h0;
+        hpm_timers_6 = 10'h0;
+        hpm_timers_7 = 10'h0;
+        hpm_timers_8 = 10'h0;
+        hpm_timers_9 = 10'h0;
+        hpm_timers_10 = 10'h0;
+        hpm_timers_11 = 10'h0;
+        hpm_timers_12 = 10'h0;
+        hpm_timers_13 = 10'h0;
+        hpm_timers_14 = 10'h0;
+        hpm_timers_15 = 10'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  MSHR mshrs_0 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h0),
+    .io_status_valid                                      (_mshrs_0_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_0_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_0_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_0_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_0_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_0_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_0_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_0_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_0_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_0_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_0_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_0_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_0_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_0_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_0_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_0_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_0_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_0_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_0_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_0_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_0_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_0_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_0_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_0_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_0_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_0_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_0_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_0_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_0_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_0_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_0_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_0_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_0_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_0_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_0_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_0_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_0_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_0_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_0_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_0_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_0_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_0_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_0_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_0_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_0_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_0_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_0_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_0_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_0_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_0_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_0_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_0_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_0_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_0_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_0_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_0_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_0_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_0_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_0_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_0_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_0_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_0_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_0_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_0_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_0_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_0_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_0_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_0_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_0_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_0_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_0_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_0_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_0_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_0_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_0_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_0_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_0_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_0_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_0_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_0_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_0_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_0_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_0_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_0_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_0_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_0_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_0_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_0_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_0_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_0_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_0_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_0_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_0_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_0_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_0_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_0_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_0_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_0_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_0_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_0_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_0_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_0_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_0_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_0_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_0_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_0_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_0_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_0_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_0_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_0_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_0_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_0_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_0_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_0),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_0_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h0),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_0_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h0),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_0_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[0]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h0),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_0_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_0_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_0_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_0_grant)
+  );
+  MSHR mshrs_1 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h1),
+    .io_status_valid                                      (_mshrs_1_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_1_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_1_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_1_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_1_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_1_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_1_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_1_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_1_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_1_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_1_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_1_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_1_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_1_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_1_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_1_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_1_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_1_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_1_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_1_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_1_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_1_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_1_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_1_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_1_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_1_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_1_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_1_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_1_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_1_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_1_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_1_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_1_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_1_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_1_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_1_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_1_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_1_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_1_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_1_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_1_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_1_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_1_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_1_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_1_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_1_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_1_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_1_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_1_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_1_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_1_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_1_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_1_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_1_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_1_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_1_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_1_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_1_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_1_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_1_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_1_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_1_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_1_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_1_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_1_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_1_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_1_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_1_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_1_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_1_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_1_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_1_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_1_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_1_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_1_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_1_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_1_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_1_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_1_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_1_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_1_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_1_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_1_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_1_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_1_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_1_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_1_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_1_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_1_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_1_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_1_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_1_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_1_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_1_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_1_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_1_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_1_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_1_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_1_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_1_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_1_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_1_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_1_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_1_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_1_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_1_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_1_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_1_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_1_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_1_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_1_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_1_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_1_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_1),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_1_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h1),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_1_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h1),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_1_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[1]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h1),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_1_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_1_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_1_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_1_grant)
+  );
+  MSHR mshrs_2 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h2),
+    .io_status_valid                                      (_mshrs_2_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_2_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_2_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_2_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_2_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_2_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_2_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_2_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_2_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_2_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_2_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_2_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_2_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_2_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_2_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_2_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_2_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_2_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_2_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_2_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_2_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_2_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_2_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_2_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_2_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_2_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_2_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_2_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_2_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_2_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_2_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_2_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_2_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_2_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_2_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_2_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_2_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_2_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_2_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_2_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_2_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_2_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_2_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_2_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_2_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_2_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_2_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_2_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_2_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_2_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_2_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_2_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_2_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_2_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_2_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_2_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_2_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_2_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_2_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_2_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_2_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_2_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_2_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_2_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_2_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_2_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_2_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_2_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_2_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_2_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_2_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_2_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_2_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_2_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_2_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_2_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_2_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_2_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_2_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_2_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_2_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_2_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_2_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_2_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_2_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_2_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_2_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_2_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_2_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_2_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_2_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_2_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_2_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_2_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_2_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_2_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_2_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_2_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_2_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_2_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_2_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_2_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_2_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_2_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_2_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_2_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_2_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_2_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_2_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_2_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_2_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_2_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_2_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_2),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_2_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h2),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_2_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h2),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_2_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[2]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h2),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_2_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_2_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_2_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_2_grant)
+  );
+  MSHR mshrs_3 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h3),
+    .io_status_valid                                      (_mshrs_3_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_3_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_3_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_3_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_3_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_3_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_3_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_3_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_3_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_3_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_3_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_3_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_3_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_3_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_3_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_3_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_3_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_3_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_3_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_3_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_3_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_3_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_3_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_3_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_3_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_3_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_3_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_3_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_3_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_3_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_3_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_3_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_3_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_3_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_3_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_3_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_3_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_3_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_3_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_3_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_3_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_3_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_3_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_3_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_3_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_3_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_3_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_3_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_3_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_3_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_3_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_3_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_3_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_3_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_3_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_3_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_3_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_3_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_3_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_3_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_3_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_3_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_3_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_3_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_3_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_3_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_3_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_3_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_3_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_3_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_3_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_3_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_3_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_3_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_3_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_3_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_3_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_3_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_3_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_3_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_3_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_3_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_3_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_3_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_3_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_3_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_3_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_3_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_3_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_3_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_3_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_3_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_3_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_3_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_3_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_3_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_3_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_3_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_3_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_3_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_3_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_3_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_3_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_3_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_3_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_3_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_3_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_3_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_3_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_3_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_3_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_3_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_3_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_3),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_3_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h3),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_3_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h3),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_3_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[3]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h3),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_3_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_3_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_3_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_3_grant)
+  );
+  MSHR mshrs_4 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h4),
+    .io_status_valid                                      (_mshrs_4_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_4_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_4_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_4_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_4_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_4_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_4_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_4_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_4_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_4_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_4_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_4_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_4_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_4_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_4_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_4_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_4_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_4_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_4_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_4_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_4_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_4_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_4_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_4_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_4_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_4_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_4_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_4_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_4_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_4_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_4_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_4_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_4_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_4_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_4_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_4_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_4_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_4_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_4_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_4_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_4_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_4_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_4_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_4_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_4_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_4_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_4_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_4_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_4_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_4_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_4_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_4_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_4_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_4_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_4_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_4_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_4_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_4_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_4_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_4_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_4_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_4_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_4_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_4_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_4_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_4_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_4_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_4_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_4_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_4_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_4_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_4_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_4_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_4_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_4_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_4_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_4_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_4_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_4_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_4_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_4_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_4_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_4_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_4_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_4_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_4_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_4_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_4_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_4_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_4_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_4_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_4_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_4_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_4_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_4_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_4_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_4_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_4_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_4_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_4_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_4_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_4_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_4_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_4_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_4_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_4_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_4_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_4_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_4_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_4_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_4_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_4_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_4_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_4),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_4_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h4),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_4_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h4),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_4_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[4]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h4),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_4_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_4_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_4_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_4_grant)
+  );
+  MSHR mshrs_5 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h5),
+    .io_status_valid                                      (_mshrs_5_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_5_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_5_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_5_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_5_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_5_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_5_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_5_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_5_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_5_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_5_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_5_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_5_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_5_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_5_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_5_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_5_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_5_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_5_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_5_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_5_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_5_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_5_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_5_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_5_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_5_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_5_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_5_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_5_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_5_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_5_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_5_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_5_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_5_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_5_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_5_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_5_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_5_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_5_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_5_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_5_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_5_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_5_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_5_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_5_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_5_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_5_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_5_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_5_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_5_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_5_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_5_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_5_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_5_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_5_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_5_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_5_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_5_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_5_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_5_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_5_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_5_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_5_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_5_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_5_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_5_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_5_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_5_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_5_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_5_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_5_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_5_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_5_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_5_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_5_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_5_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_5_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_5_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_5_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_5_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_5_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_5_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_5_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_5_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_5_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_5_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_5_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_5_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_5_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_5_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_5_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_5_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_5_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_5_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_5_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_5_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_5_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_5_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_5_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_5_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_5_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_5_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_5_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_5_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_5_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_5_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_5_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_5_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_5_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_5_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_5_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_5_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_5_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_5),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_5_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h5),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_5_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h5),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_5_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[5]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h5),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_5_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_5_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_5_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_5_grant)
+  );
+  MSHR mshrs_6 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h6),
+    .io_status_valid                                      (_mshrs_6_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_6_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_6_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_6_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_6_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_6_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_6_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_6_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_6_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_6_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_6_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_6_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_6_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_6_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_6_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_6_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_6_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_6_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_6_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_6_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_6_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_6_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_6_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_6_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_6_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_6_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_6_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_6_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_6_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_6_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_6_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_6_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_6_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_6_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_6_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_6_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_6_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_6_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_6_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_6_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_6_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_6_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_6_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_6_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_6_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_6_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_6_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_6_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_6_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_6_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_6_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_6_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_6_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_6_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_6_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_6_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_6_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_6_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_6_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_6_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_6_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_6_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_6_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_6_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_6_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_6_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_6_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_6_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_6_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_6_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_6_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_6_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_6_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_6_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_6_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_6_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_6_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_6_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_6_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_6_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_6_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_6_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_6_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_6_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_6_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_6_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_6_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_6_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_6_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_6_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_6_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_6_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_6_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_6_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_6_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_6_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_6_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_6_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_6_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_6_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_6_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_6_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_6_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_6_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_6_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_6_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_6_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_6_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_6_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_6_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_6_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_6_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_6_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_6),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_6_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h6),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_6_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h6),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_6_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[6]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h6),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_6_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_6_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_6_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_6_grant)
+  );
+  MSHR mshrs_7 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h7),
+    .io_status_valid                                      (_mshrs_7_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_7_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_7_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_7_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_7_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_7_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_7_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_7_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_7_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_7_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_7_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_7_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_7_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_7_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_7_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_7_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_7_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_7_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_7_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_7_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_7_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_7_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_7_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_7_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_7_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_7_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_7_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_7_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_7_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_7_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_7_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_7_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_7_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_7_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_7_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_7_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_7_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_7_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_7_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_7_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_7_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_7_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_7_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_7_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_7_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_7_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_7_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_7_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_7_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_7_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_7_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_7_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_7_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_7_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_7_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_7_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_7_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_7_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_7_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_7_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_7_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_7_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_7_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_7_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_7_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_7_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_7_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_7_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_7_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_7_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_7_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_7_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_7_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_7_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_7_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_7_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_7_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_7_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_7_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_7_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_7_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_7_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_7_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_7_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_7_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_7_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_7_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_7_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_7_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_7_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_7_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_7_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_7_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_7_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_7_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_7_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_7_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_7_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_7_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_7_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_7_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_7_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_7_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_7_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_7_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_7_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_7_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_7_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_7_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_7_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_7_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_7_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_7_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_7),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_7_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h7),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_7_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h7),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_7_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[7]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h7),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_7_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_7_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_7_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_7_grant)
+  );
+  MSHR mshrs_8 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h8),
+    .io_status_valid                                      (_mshrs_8_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_8_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_8_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_8_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_8_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_8_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_8_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_8_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_8_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_8_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_8_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_8_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_8_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_8_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_8_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_8_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_8_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_8_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_8_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_8_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_8_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_8_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_8_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_8_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_8_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_8_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_8_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_8_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_8_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_8_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_8_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_8_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_8_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_8_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_8_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_8_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_8_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_8_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_8_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_8_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_8_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_8_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_8_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_8_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_8_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_8_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_8_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_8_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_8_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_8_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_8_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_8_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_8_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_8_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_8_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_8_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_8_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_8_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_8_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_8_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_8_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_8_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_8_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_8_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_8_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_8_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_8_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_8_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_8_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_8_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_8_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_8_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_8_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_8_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_8_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_8_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_8_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_8_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_8_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_8_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_8_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_8_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_8_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_8_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_8_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_8_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_8_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_8_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_8_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_8_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_8_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_8_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_8_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_8_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_8_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_8_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_8_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_8_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_8_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_8_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_8_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_8_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_8_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_8_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_8_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_8_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_8_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_8_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_8_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_8_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_8_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_8_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_8_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_8),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_8_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h8),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_8_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h8),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_8_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[8]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h8),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_8_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_8_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_8_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_8_grant)
+  );
+  MSHR mshrs_9 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'h9),
+    .io_status_valid                                      (_mshrs_9_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_9_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_9_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_9_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_9_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_9_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_9_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_9_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_9_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_9_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_9_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_9_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_9_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_9_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_9_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_9_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_9_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_9_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_9_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_9_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_9_bits_meta_state),
+    .io_msInfo_bits_meta_clients                          (io_msInfo_9_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_9_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_9_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_9_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_9_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_9_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr                          (io_msInfo_9_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_9_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_9_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_9_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_9_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_9_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_9_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst                          (io_msInfo_9_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_9_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_9_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_9_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_9_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_9_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_9_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack                          (io_msInfo_9_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_9_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_9_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_9_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_9_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_9_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_9_ready),
+    .io_tasks_txreq_valid                                 (_mshrs_9_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_9_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_9_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_9_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_9_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_9_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_9_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_9_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_9_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_9_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_9_ready),
+    .io_tasks_txrsp_valid                                 (_mshrs_9_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_9_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_9_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_9_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_9_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_9_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_9_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_9_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_9_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_9_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_9_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_9_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_9_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_9_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_9_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_9_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_9_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_9_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_9_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_9_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_9_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_9_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_9_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_9_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_9_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_9_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_9_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_9_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_9_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_9_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_9_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_9_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_9_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_9_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_9_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_9_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_9_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_9_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_9_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_9_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_9_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_9_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_9_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_9_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_9_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_9_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_9_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_9_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_9_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_9_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_9_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_9_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_9_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_9_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_9),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_9_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'h9),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_9_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'h9),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_9_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[9]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'h9),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_9_query_valid),
+    .io_pCrd_query_bits_pCrdType                          (io_pCrd_9_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_9_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_9_grant)
+  );
+  MSHR mshrs_10 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'hA),
+    .io_status_valid                                      (_mshrs_10_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_10_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_10_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_10_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_10_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_10_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_10_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_10_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_10_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_10_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_10_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_10_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_10_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_10_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_10_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_10_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_10_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_10_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_10_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_10_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_10_bits_meta_state),
+    .io_msInfo_bits_meta_clients
+      (io_msInfo_10_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_10_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_10_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_10_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_10_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_10_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr
+      (io_msInfo_10_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_10_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_10_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_10_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_10_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_10_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_10_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst
+      (io_msInfo_10_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_10_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_10_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_10_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_10_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_10_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_10_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack
+      (io_msInfo_10_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_10_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_10_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_10_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_10_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_10_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_10_ready),
+    .io_tasks_txreq_valid
+      (_mshrs_10_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_10_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_10_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_10_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_10_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_10_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_10_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_10_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_10_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_10_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_10_ready),
+    .io_tasks_txrsp_valid
+      (_mshrs_10_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_10_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_10_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_10_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_10_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_10_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_10_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_10_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_10_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_10_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_10_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_10_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_10_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_10_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_10_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_10_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_10_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_10_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_10_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_10_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_10_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_10_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_10_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_10_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_10_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_10_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_10_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_10_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_10_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_10_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_10_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_10_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_10_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_10_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_10_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_10_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_10_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_10_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_10_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_10_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_10_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_10_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_10_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_10_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_10_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_10_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_10_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_10_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_10_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_10_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_10_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_10_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_10_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_10_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_10),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_10_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'hA),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_10_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'hA),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_10_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[10]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'hA),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_10_query_valid),
+    .io_pCrd_query_bits_pCrdType
+      (io_pCrd_10_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_10_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_10_grant)
+  );
+  MSHR mshrs_11 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'hB),
+    .io_status_valid                                      (_mshrs_11_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_11_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_11_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_11_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_11_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_11_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_11_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_11_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_11_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_11_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_11_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_11_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_11_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_11_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_11_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_11_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_11_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_11_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_11_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_11_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_11_bits_meta_state),
+    .io_msInfo_bits_meta_clients
+      (io_msInfo_11_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_11_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_11_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_11_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_11_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_11_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr
+      (io_msInfo_11_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_11_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_11_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_11_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_11_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_11_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_11_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst
+      (io_msInfo_11_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_11_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_11_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_11_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_11_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_11_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_11_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack
+      (io_msInfo_11_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_11_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_11_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_11_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_11_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_11_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_11_ready),
+    .io_tasks_txreq_valid
+      (_mshrs_11_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_11_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_11_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_11_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_11_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_11_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_11_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_11_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_11_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_11_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_11_ready),
+    .io_tasks_txrsp_valid
+      (_mshrs_11_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_11_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_11_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_11_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_11_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_11_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_11_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_11_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_11_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_11_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_11_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_11_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_11_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_11_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_11_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_11_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_11_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_11_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_11_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_11_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_11_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_11_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_11_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_11_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_11_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_11_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_11_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_11_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_11_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_11_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_11_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_11_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_11_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_11_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_11_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_11_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_11_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_11_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_11_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_11_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_11_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_11_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_11_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_11_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_11_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_11_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_11_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_11_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_11_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_11_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_11_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_11_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_11_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_11_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_11),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_11_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'hB),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_11_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'hB),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_11_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[11]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'hB),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_11_query_valid),
+    .io_pCrd_query_bits_pCrdType
+      (io_pCrd_11_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_11_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_11_grant)
+  );
+  MSHR mshrs_12 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'hC),
+    .io_status_valid                                      (_mshrs_12_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_12_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_12_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_12_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_12_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_12_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_12_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_12_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_12_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_12_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_12_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_12_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_12_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_12_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_12_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_12_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_12_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_12_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_12_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_12_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_12_bits_meta_state),
+    .io_msInfo_bits_meta_clients
+      (io_msInfo_12_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_12_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_12_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_12_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_12_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_12_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr
+      (io_msInfo_12_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_12_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_12_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_12_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_12_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_12_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_12_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst
+      (io_msInfo_12_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_12_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_12_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_12_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_12_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_12_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_12_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack
+      (io_msInfo_12_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_12_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_12_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_12_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_12_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_12_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_12_ready),
+    .io_tasks_txreq_valid
+      (_mshrs_12_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_12_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_12_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_12_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_12_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_12_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_12_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_12_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_12_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_12_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_12_ready),
+    .io_tasks_txrsp_valid
+      (_mshrs_12_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_12_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_12_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_12_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_12_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_12_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_12_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_12_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_12_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_12_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_12_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_12_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_12_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_12_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_12_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_12_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_12_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_12_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_12_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_12_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_12_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_12_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_12_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_12_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_12_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_12_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_12_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_12_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_12_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_12_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_12_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_12_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_12_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_12_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_12_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_12_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_12_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_12_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_12_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_12_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_12_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_12_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_12_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_12_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_12_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_12_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_12_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_12_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_12_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_12_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_12_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_12_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_12_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_12_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_12),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_12_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'hC),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_12_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'hC),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_12_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[12]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'hC),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_12_query_valid),
+    .io_pCrd_query_bits_pCrdType
+      (io_pCrd_12_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_12_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_12_grant)
+  );
+  MSHR mshrs_13 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'hD),
+    .io_status_valid                                      (_mshrs_13_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_13_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_13_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_13_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_13_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_13_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_13_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_13_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_13_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_13_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_13_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_13_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_13_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_13_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_13_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_13_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_13_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_13_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_13_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_13_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_13_bits_meta_state),
+    .io_msInfo_bits_meta_clients
+      (io_msInfo_13_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_13_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_13_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_13_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_13_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_13_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr
+      (io_msInfo_13_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_13_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_13_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_13_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_13_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_13_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_13_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst
+      (io_msInfo_13_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_13_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_13_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_13_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_13_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_13_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_13_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack
+      (io_msInfo_13_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_13_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_13_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_13_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_13_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_13_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_13_ready),
+    .io_tasks_txreq_valid
+      (_mshrs_13_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_13_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_13_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_13_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_13_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_13_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_13_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_13_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_13_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_13_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_13_ready),
+    .io_tasks_txrsp_valid
+      (_mshrs_13_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_13_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_13_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_13_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_13_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_13_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_13_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_13_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_13_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_13_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_13_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_13_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_13_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_13_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_13_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_13_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_13_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_13_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_13_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_13_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_13_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_13_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_13_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_13_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_13_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_13_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_13_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_13_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_13_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_13_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_13_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_13_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_13_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_13_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_13_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_13_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_13_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_13_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_13_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_13_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_13_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_13_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_13_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_13_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_13_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_13_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_13_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_13_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_13_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_13_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_13_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_13_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_13_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_13_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_13),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_13_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'hD),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_13_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'hD),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_13_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[13]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'hD),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_13_query_valid),
+    .io_pCrd_query_bits_pCrdType
+      (io_pCrd_13_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_13_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_13_grant)
+  );
+  MSHR mshrs_14 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'hE),
+    .io_status_valid                                      (_mshrs_14_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_14_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_14_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_14_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_14_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_14_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_14_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_14_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_14_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_14_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_14_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_14_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_14_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_14_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_14_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_14_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_14_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_14_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_14_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_14_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_14_bits_meta_state),
+    .io_msInfo_bits_meta_clients
+      (io_msInfo_14_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_14_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_14_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_14_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_14_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_14_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr
+      (io_msInfo_14_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_14_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_14_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_14_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_14_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_14_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_14_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst
+      (io_msInfo_14_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_14_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_14_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_14_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_14_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_14_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_14_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack
+      (io_msInfo_14_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_14_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_14_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_14_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_14_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_14_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_14_ready),
+    .io_tasks_txreq_valid
+      (_mshrs_14_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_14_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_14_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_14_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_14_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_14_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_14_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_14_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_14_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_14_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_14_ready),
+    .io_tasks_txrsp_valid
+      (_mshrs_14_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_14_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_14_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_14_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_14_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_14_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_14_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_14_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_14_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_14_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_14_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_14_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_14_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_14_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_14_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_14_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_14_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_14_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_14_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_14_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_14_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_14_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_14_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_14_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_14_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_14_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_14_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_14_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_14_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_14_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_14_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_14_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_14_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_14_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_14_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_14_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_14_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_14_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_14_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_14_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_14_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_14_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_14_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_14_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_14_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_14_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_14_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_14_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_14_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_14_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_14_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_14_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_14_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_14_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & resp_sinkC_match_vec_14),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_14_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'hE),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_14_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'hE),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_14_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[14]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'hE),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_14_query_valid),
+    .io_pCrd_query_bits_pCrdType
+      (io_pCrd_14_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_14_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_14_grant)
+  );
+  MSHR mshrs_15 (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_id                                                (8'hF),
+    .io_status_valid                                      (_mshrs_15_io_status_valid),
+    .io_status_bits_channel
+      (_mshrs_15_io_status_bits_channel),
+    .io_status_bits_set                                   (_mshrs_15_io_status_bits_set),
+    .io_status_bits_reqTag
+      (_mshrs_15_io_status_bits_reqTag),
+    .io_status_bits_metaTag
+      (_mshrs_15_io_status_bits_metaTag),
+    .io_status_bits_needsRepl
+      (_mshrs_15_io_status_bits_needsRepl),
+    .io_status_bits_w_c_resp
+      (_mshrs_15_io_status_bits_w_c_resp),
+    .io_status_bits_will_free
+      (_mshrs_15_io_status_bits_will_free),
+    .io_status_bits_reqSource
+      (_mshrs_15_io_status_bits_reqSource),
+    .io_msInfo_valid                                      (io_msInfo_15_valid),
+    .io_msInfo_bits_channel                               (io_msInfo_15_bits_channel),
+    .io_msInfo_bits_set                                   (io_msInfo_15_bits_set),
+    .io_msInfo_bits_way                                   (io_msInfo_15_bits_way),
+    .io_msInfo_bits_reqTag                                (io_msInfo_15_bits_reqTag),
+    .io_msInfo_bits_reqSource                             (io_msInfo_15_bits_reqSource),
+    .io_msInfo_bits_willFree                              (io_msInfo_15_bits_willFree),
+    .io_msInfo_bits_aliasTask                             (io_msInfo_15_bits_aliasTask),
+    .io_msInfo_bits_needRelease                           (io_msInfo_15_bits_needRelease),
+    .io_msInfo_bits_blockRefill                           (io_msInfo_15_bits_blockRefill),
+    .io_msInfo_bits_meta_dirty                            (io_msInfo_15_bits_meta_dirty),
+    .io_msInfo_bits_meta_state                            (io_msInfo_15_bits_meta_state),
+    .io_msInfo_bits_meta_clients
+      (io_msInfo_15_bits_meta_clients),
+    .io_msInfo_bits_meta_alias                            (io_msInfo_15_bits_meta_alias),
+    .io_msInfo_bits_meta_prefetch
+      (io_msInfo_15_bits_meta_prefetch),
+    .io_msInfo_bits_meta_prefetchSrc
+      (io_msInfo_15_bits_meta_prefetchSrc),
+    .io_msInfo_bits_meta_accessed
+      (io_msInfo_15_bits_meta_accessed),
+    .io_msInfo_bits_meta_tagErr                           (io_msInfo_15_bits_meta_tagErr),
+    .io_msInfo_bits_meta_dataErr
+      (io_msInfo_15_bits_meta_dataErr),
+    .io_msInfo_bits_metaTag                               (io_msInfo_15_bits_metaTag),
+    .io_msInfo_bits_dirHit                                (io_msInfo_15_bits_dirHit),
+    .io_msInfo_bits_isAcqOrPrefetch
+      (io_msInfo_15_bits_isAcqOrPrefetch),
+    .io_msInfo_bits_isPrefetch                            (io_msInfo_15_bits_isPrefetch),
+    .io_msInfo_bits_param                                 (io_msInfo_15_bits_param),
+    .io_msInfo_bits_mergeA                                (io_msInfo_15_bits_mergeA),
+    .io_msInfo_bits_w_grantfirst
+      (io_msInfo_15_bits_w_grantfirst),
+    .io_msInfo_bits_w_grantlast                           (io_msInfo_15_bits_w_grantlast),
+    .io_msInfo_bits_w_grant                               (io_msInfo_15_bits_w_grant),
+    .io_msInfo_bits_s_release                             (io_msInfo_15_bits_s_release),
+    .io_msInfo_bits_s_refill                              (io_msInfo_15_bits_s_refill),
+    .io_msInfo_bits_s_cmoresp                             (io_msInfo_15_bits_s_cmoresp),
+    .io_msInfo_bits_s_cmometaw                            (io_msInfo_15_bits_s_cmometaw),
+    .io_msInfo_bits_w_releaseack
+      (io_msInfo_15_bits_w_releaseack),
+    .io_msInfo_bits_w_replResp                            (io_msInfo_15_bits_w_replResp),
+    .io_msInfo_bits_w_rprobeacklast
+      (io_msInfo_15_bits_w_rprobeacklast),
+    .io_msInfo_bits_replaceData                           (io_msInfo_15_bits_replaceData),
+    .io_msInfo_bits_releaseToClean
+      (io_msInfo_15_bits_releaseToClean),
+    .io_alloc_valid                                       (mshrs_15_io_alloc_valid),
+    .io_alloc_bits_dirResult_hit
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit),
+    .io_alloc_bits_dirResult_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag),
+    .io_alloc_bits_dirResult_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set),
+    .io_alloc_bits_dirResult_way
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way),
+    .io_alloc_bits_dirResult_meta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_alloc_bits_dirResult_meta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_alloc_bits_dirResult_meta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_alloc_bits_dirResult_meta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_alloc_bits_dirResult_meta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_alloc_bits_dirResult_meta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_alloc_bits_dirResult_meta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_alloc_bits_dirResult_meta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_alloc_bits_dirResult_meta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_alloc_bits_dirResult_error
+      (io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error),
+    .io_alloc_bits_state_s_acquire
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire),
+    .io_alloc_bits_state_s_rprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_alloc_bits_state_s_pprobe
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_alloc_bits_state_s_release
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_release),
+    .io_alloc_bits_state_s_probeack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack),
+    .io_alloc_bits_state_s_refill
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill),
+    .io_alloc_bits_state_s_cmoresp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_alloc_bits_state_w_rprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_alloc_bits_state_w_rprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_alloc_bits_state_w_pprobeackfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_alloc_bits_state_w_pprobeacklast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_alloc_bits_state_w_grantfirst
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_alloc_bits_state_w_grantlast
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_alloc_bits_state_w_grant
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant),
+    .io_alloc_bits_state_w_releaseack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_alloc_bits_state_w_replResp
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp),
+    .io_alloc_bits_state_s_rcompack
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_alloc_bits_state_s_dct
+      (io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct),
+    .io_alloc_bits_task_channel
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_channel),
+    .io_alloc_bits_task_set
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_set),
+    .io_alloc_bits_task_tag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_tag),
+    .io_alloc_bits_task_off
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_off),
+    .io_alloc_bits_task_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_alias),
+    .io_alloc_bits_task_isKeyword
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword),
+    .io_alloc_bits_task_opcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_opcode),
+    .io_alloc_bits_task_param
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_param),
+    .io_alloc_bits_task_sourceId
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId),
+    .io_alloc_bits_task_aliasTask
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask),
+    .io_alloc_bits_task_fromL2pft
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_alloc_bits_task_reqSource
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource),
+    .io_alloc_bits_task_snpHitRelease
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_alloc_bits_task_snpHitReleaseToInval
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_alloc_bits_task_snpHitReleaseToClean
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_alloc_bits_task_snpHitReleaseWithData
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_alloc_bits_task_snpHitReleaseIdx
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_alloc_bits_task_snpHitReleaseMeta_dirty
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_alloc_bits_task_snpHitReleaseMeta_state
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_alloc_bits_task_snpHitReleaseMeta_clients
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_alloc_bits_task_snpHitReleaseMeta_alias
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetch
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_alloc_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_alloc_bits_task_snpHitReleaseMeta_accessed
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_alloc_bits_task_snpHitReleaseMeta_tagErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_alloc_bits_task_snpHitReleaseMeta_dataErr
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_alloc_bits_task_srcID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_srcID),
+    .io_alloc_bits_task_txnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_txnID),
+    .io_alloc_bits_task_fwdNID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID),
+    .io_alloc_bits_task_fwdTxnID
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_alloc_bits_task_chiOpcode
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_alloc_bits_task_retToSrc
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc),
+    .io_alloc_bits_task_traceTag
+      (io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag),
+    .io_tasks_txreq_ready                                 (_txreq_arb_io_in_15_ready),
+    .io_tasks_txreq_valid
+      (_mshrs_15_io_tasks_txreq_valid),
+    .io_tasks_txreq_bits_tgtID
+      (_mshrs_15_io_tasks_txreq_bits_tgtID),
+    .io_tasks_txreq_bits_txnID
+      (_mshrs_15_io_tasks_txreq_bits_txnID),
+    .io_tasks_txreq_bits_opcode
+      (_mshrs_15_io_tasks_txreq_bits_opcode),
+    .io_tasks_txreq_bits_addr
+      (_mshrs_15_io_tasks_txreq_bits_addr),
+    .io_tasks_txreq_bits_likelyshared
+      (_mshrs_15_io_tasks_txreq_bits_likelyshared),
+    .io_tasks_txreq_bits_allowRetry
+      (_mshrs_15_io_tasks_txreq_bits_allowRetry),
+    .io_tasks_txreq_bits_pCrdType
+      (_mshrs_15_io_tasks_txreq_bits_pCrdType),
+    .io_tasks_txreq_bits_memAttr_allocate
+      (_mshrs_15_io_tasks_txreq_bits_memAttr_allocate),
+    .io_tasks_txreq_bits_expCompAck
+      (_mshrs_15_io_tasks_txreq_bits_expCompAck),
+    .io_tasks_txrsp_ready                                 (_txrsp_arb_io_in_15_ready),
+    .io_tasks_txrsp_valid
+      (_mshrs_15_io_tasks_txrsp_valid),
+    .io_tasks_txrsp_bits_tgtID
+      (_mshrs_15_io_tasks_txrsp_bits_tgtID),
+    .io_tasks_txrsp_bits_txnID
+      (_mshrs_15_io_tasks_txrsp_bits_txnID),
+    .io_tasks_txrsp_bits_traceTag
+      (_mshrs_15_io_tasks_txrsp_bits_traceTag),
+    .io_tasks_source_b_ready                              (_source_b_arb_io_in_15_ready),
+    .io_tasks_source_b_valid
+      (_mshrs_15_io_tasks_source_b_valid),
+    .io_tasks_source_b_bits_tag
+      (_mshrs_15_io_tasks_source_b_bits_tag),
+    .io_tasks_source_b_bits_set
+      (_mshrs_15_io_tasks_source_b_bits_set),
+    .io_tasks_source_b_bits_param
+      (_mshrs_15_io_tasks_source_b_bits_param),
+    .io_tasks_source_b_bits_alias
+      (_mshrs_15_io_tasks_source_b_bits_alias),
+    .io_tasks_mainpipe_ready                              (_mshr_task_arb_io_in_15_ready),
+    .io_tasks_mainpipe_valid
+      (_mshrs_15_io_tasks_mainpipe_valid),
+    .io_tasks_mainpipe_bits_channel
+      (_mshrs_15_io_tasks_mainpipe_bits_channel),
+    .io_tasks_mainpipe_bits_txChannel
+      (_mshrs_15_io_tasks_mainpipe_bits_txChannel),
+    .io_tasks_mainpipe_bits_set
+      (_mshrs_15_io_tasks_mainpipe_bits_set),
+    .io_tasks_mainpipe_bits_tag
+      (_mshrs_15_io_tasks_mainpipe_bits_tag),
+    .io_tasks_mainpipe_bits_off
+      (_mshrs_15_io_tasks_mainpipe_bits_off),
+    .io_tasks_mainpipe_bits_alias
+      (_mshrs_15_io_tasks_mainpipe_bits_alias),
+    .io_tasks_mainpipe_bits_isKeyword
+      (_mshrs_15_io_tasks_mainpipe_bits_isKeyword),
+    .io_tasks_mainpipe_bits_opcode
+      (_mshrs_15_io_tasks_mainpipe_bits_opcode),
+    .io_tasks_mainpipe_bits_param
+      (_mshrs_15_io_tasks_mainpipe_bits_param),
+    .io_tasks_mainpipe_bits_size
+      (_mshrs_15_io_tasks_mainpipe_bits_size),
+    .io_tasks_mainpipe_bits_sourceId
+      (_mshrs_15_io_tasks_mainpipe_bits_sourceId),
+    .io_tasks_mainpipe_bits_denied
+      (_mshrs_15_io_tasks_mainpipe_bits_denied),
+    .io_tasks_mainpipe_bits_corrupt
+      (_mshrs_15_io_tasks_mainpipe_bits_corrupt),
+    .io_tasks_mainpipe_bits_aliasTask
+      (_mshrs_15_io_tasks_mainpipe_bits_aliasTask),
+    .io_tasks_mainpipe_bits_useProbeData
+      (_mshrs_15_io_tasks_mainpipe_bits_useProbeData),
+    .io_tasks_mainpipe_bits_mshrRetry
+      (_mshrs_15_io_tasks_mainpipe_bits_mshrRetry),
+    .io_tasks_mainpipe_bits_readProbeDataDown
+      (_mshrs_15_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_tasks_mainpipe_bits_fromL2pft
+      (_mshrs_15_io_tasks_mainpipe_bits_fromL2pft),
+    .io_tasks_mainpipe_bits_dirty
+      (_mshrs_15_io_tasks_mainpipe_bits_dirty),
+    .io_tasks_mainpipe_bits_way
+      (_mshrs_15_io_tasks_mainpipe_bits_way),
+    .io_tasks_mainpipe_bits_meta_dirty
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_dirty),
+    .io_tasks_mainpipe_bits_meta_state
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_state),
+    .io_tasks_mainpipe_bits_meta_clients
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_clients),
+    .io_tasks_mainpipe_bits_meta_alias
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_alias),
+    .io_tasks_mainpipe_bits_meta_prefetch
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_tasks_mainpipe_bits_meta_prefetchSrc
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_tasks_mainpipe_bits_meta_accessed
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_accessed),
+    .io_tasks_mainpipe_bits_meta_tagErr
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_tasks_mainpipe_bits_meta_dataErr
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_tasks_mainpipe_bits_metaWen
+      (_mshrs_15_io_tasks_mainpipe_bits_metaWen),
+    .io_tasks_mainpipe_bits_tagWen
+      (_mshrs_15_io_tasks_mainpipe_bits_tagWen),
+    .io_tasks_mainpipe_bits_dsWen
+      (_mshrs_15_io_tasks_mainpipe_bits_dsWen),
+    .io_tasks_mainpipe_bits_replTask
+      (_mshrs_15_io_tasks_mainpipe_bits_replTask),
+    .io_tasks_mainpipe_bits_cmoTask
+      (_mshrs_15_io_tasks_mainpipe_bits_cmoTask),
+    .io_tasks_mainpipe_bits_reqSource
+      (_mshrs_15_io_tasks_mainpipe_bits_reqSource),
+    .io_tasks_mainpipe_bits_mergeA
+      (_mshrs_15_io_tasks_mainpipe_bits_mergeA),
+    .io_tasks_mainpipe_bits_aMergeTask_off
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_tasks_mainpipe_bits_aMergeTask_alias
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_vaddr
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_tasks_mainpipe_bits_aMergeTask_isKeyword
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_tasks_mainpipe_bits_aMergeTask_opcode
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_tasks_mainpipe_bits_aMergeTask_param
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_tasks_mainpipe_bits_aMergeTask_sourceId
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_dirty
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_state
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_clients
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_alias
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_tasks_mainpipe_bits_aMergeTask_meta_accessed
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_tasks_mainpipe_bits_snpHitRelease
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_tasks_mainpipe_bits_snpHitReleaseToInval
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_tasks_mainpipe_bits_snpHitReleaseToClean
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_tasks_mainpipe_bits_snpHitReleaseWithData
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_tasks_mainpipe_bits_snpHitReleaseIdx
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_state
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_clients
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_alias
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_tasks_mainpipe_bits_tgtID
+      (_mshrs_15_io_tasks_mainpipe_bits_tgtID),
+    .io_tasks_mainpipe_bits_txnID
+      (_mshrs_15_io_tasks_mainpipe_bits_txnID),
+    .io_tasks_mainpipe_bits_homeNID
+      (_mshrs_15_io_tasks_mainpipe_bits_homeNID),
+    .io_tasks_mainpipe_bits_dbID
+      (_mshrs_15_io_tasks_mainpipe_bits_dbID),
+    .io_tasks_mainpipe_bits_chiOpcode
+      (_mshrs_15_io_tasks_mainpipe_bits_chiOpcode),
+    .io_tasks_mainpipe_bits_resp
+      (_mshrs_15_io_tasks_mainpipe_bits_resp),
+    .io_tasks_mainpipe_bits_fwdState
+      (_mshrs_15_io_tasks_mainpipe_bits_fwdState),
+    .io_tasks_mainpipe_bits_retToSrc
+      (_mshrs_15_io_tasks_mainpipe_bits_retToSrc),
+    .io_tasks_mainpipe_bits_likelyshared
+      (_mshrs_15_io_tasks_mainpipe_bits_likelyshared),
+    .io_tasks_mainpipe_bits_expCompAck
+      (_mshrs_15_io_tasks_mainpipe_bits_expCompAck),
+    .io_tasks_mainpipe_bits_allowRetry
+      (_mshrs_15_io_tasks_mainpipe_bits_allowRetry),
+    .io_tasks_mainpipe_bits_memAttr_allocate
+      (_mshrs_15_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_tasks_mainpipe_bits_memAttr_cacheable
+      (_mshrs_15_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_tasks_mainpipe_bits_memAttr_ewa
+      (_mshrs_15_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_tasks_mainpipe_bits_traceTag
+      (_mshrs_15_io_tasks_mainpipe_bits_traceTag),
+    .io_resps_sinkC_valid
+      (io_resps_sinkC_valid & _mshrs_15_io_status_valid
+       & _mshrs_15_io_status_bits_w_c_resp
+       & io_resps_sinkC_set == _mshrs_15_io_status_bits_set
+       & io_resps_sinkC_tag == (_mshrs_15_io_status_bits_needsRepl
+                                  ? _mshrs_15_io_status_bits_metaTag
+                                  : _mshrs_15_io_status_bits_reqTag)),
+    .io_resps_sinkC_bits_opcode
+      (io_resps_sinkC_respInfo_opcode),
+    .io_resps_sinkC_bits_param                            (io_resps_sinkC_respInfo_param),
+    .io_resps_sinkC_bits_last                             (io_resps_sinkC_respInfo_last),
+    .io_resps_sinkC_bits_denied
+      (io_resps_sinkC_respInfo_denied),
+    .io_resps_sinkC_bits_corrupt
+      (io_resps_sinkC_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_mshrs_15_io_status_valid & io_resps_rxrsp_valid & io_resps_rxrsp_mshrId == 8'hF),
+    .io_resps_rxrsp_bits_chiOpcode
+      (io_resps_rxrsp_respInfo_chiOpcode),
+    .io_resps_rxrsp_bits_srcID                            (io_resps_rxrsp_respInfo_srcID),
+    .io_resps_rxrsp_bits_dbID                             (io_resps_rxrsp_respInfo_dbID),
+    .io_resps_rxrsp_bits_resp                             (io_resps_rxrsp_respInfo_resp),
+    .io_resps_rxrsp_bits_pCrdType
+      (io_resps_rxrsp_respInfo_pCrdType),
+    .io_resps_rxrsp_bits_respErr
+      (io_resps_rxrsp_respInfo_respErr),
+    .io_resps_rxrsp_bits_traceTag
+      (io_resps_rxrsp_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_mshrs_15_io_status_valid & io_resps_rxdat_valid & io_resps_rxdat_mshrId == 8'hF),
+    .io_resps_rxdat_bits_corrupt
+      (io_resps_rxdat_respInfo_corrupt),
+    .io_resps_rxdat_bits_chiOpcode
+      (io_resps_rxdat_respInfo_chiOpcode),
+    .io_resps_rxdat_bits_homeNID
+      (io_resps_rxdat_respInfo_homeNID),
+    .io_resps_rxdat_bits_dbID                             (io_resps_rxdat_respInfo_dbID),
+    .io_resps_rxdat_bits_resp                             (io_resps_rxdat_respInfo_resp),
+    .io_resps_rxdat_bits_respErr
+      (io_resps_rxdat_respInfo_respErr),
+    .io_resps_rxdat_bits_traceTag
+      (io_resps_rxdat_respInfo_traceTag),
+    .io_nestedwb_set                                      (io_nestedwb_set),
+    .io_nestedwb_tag                                      (io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty                              (io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip                                (io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty                              (io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB                                    (io_nestedwb_b_toB),
+    .io_nestedwb_b_toN                                    (io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean                                (io_nestedwb_b_toClean),
+    .io_nestedwbData                                      (_mshrs_15_io_nestedwbData),
+    .io_aMergeTask_valid
+      (io_aMergeTask_valid & io_aMergeTask_bits_idOH[15]),
+    .io_aMergeTask_bits_off                               (io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_alias                             (io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_vaddr                             (io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_isKeyword
+      (io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_opcode
+      (io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_param                             (io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_sourceId
+      (io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (io_replResp_valid & io_replResp_bits_mshrId == 8'hF),
+    .io_replResp_bits_tag                                 (io_replResp_bits_tag),
+    .io_replResp_bits_way                                 (io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty                          (io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state                          (io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients                        (io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias                          (io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr                         (io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr                        (io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_retry                               (io_replResp_bits_retry),
+    .io_pCrd_query_valid                                  (io_pCrd_15_query_valid),
+    .io_pCrd_query_bits_pCrdType
+      (io_pCrd_15_query_bits_pCrdType),
+    .io_pCrd_query_bits_srcID                             (io_pCrd_15_query_bits_srcID),
+    .io_pCrd_grant                                        (io_pCrd_15_grant)
+  );
+  MSHRSelector mshrSelector (
+    .io_idle_0   (~_mshrs_0_io_status_valid),
+    .io_idle_1   (~_mshrs_1_io_status_valid),
+    .io_idle_2   (~_mshrs_2_io_status_valid),
+    .io_idle_3   (~_mshrs_3_io_status_valid),
+    .io_idle_4   (~_mshrs_4_io_status_valid),
+    .io_idle_5   (~_mshrs_5_io_status_valid),
+    .io_idle_6   (~_mshrs_6_io_status_valid),
+    .io_idle_7   (~_mshrs_7_io_status_valid),
+    .io_idle_8   (~_mshrs_8_io_status_valid),
+    .io_idle_9   (~_mshrs_9_io_status_valid),
+    .io_idle_10  (~_mshrs_10_io_status_valid),
+    .io_idle_11  (~_mshrs_11_io_status_valid),
+    .io_idle_12  (~_mshrs_12_io_status_valid),
+    .io_idle_13  (~_mshrs_13_io_status_valid),
+    .io_idle_14  (~_mshrs_14_io_status_valid),
+    .io_out_bits (_mshrSelector_io_out_bits)
+  );
+  TwoLevelRRArbiter_1 txreq_arb (
+    .clock                           (clock),
+    .reset                           (reset),
+    .io_in_0_ready                   (_txreq_arb_io_in_0_ready),
+    .io_in_0_valid                   (_mshrs_0_io_tasks_txreq_valid),
+    .io_in_0_bits_tgtID              (_mshrs_0_io_tasks_txreq_bits_tgtID),
+    .io_in_0_bits_txnID              (_mshrs_0_io_tasks_txreq_bits_txnID),
+    .io_in_0_bits_opcode             (_mshrs_0_io_tasks_txreq_bits_opcode),
+    .io_in_0_bits_size               (3'h6),
+    .io_in_0_bits_addr               (_mshrs_0_io_tasks_txreq_bits_addr),
+    .io_in_0_bits_likelyshared       (_mshrs_0_io_tasks_txreq_bits_likelyshared),
+    .io_in_0_bits_allowRetry         (_mshrs_0_io_tasks_txreq_bits_allowRetry),
+    .io_in_0_bits_order              (2'h0),
+    .io_in_0_bits_pCrdType           (_mshrs_0_io_tasks_txreq_bits_pCrdType),
+    .io_in_0_bits_memAttr_allocate   (_mshrs_0_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable  (1'h1),
+    .io_in_0_bits_memAttr_device     (1'h0),
+    .io_in_0_bits_memAttr_ewa        (1'h1),
+    .io_in_0_bits_snpAttr            (1'h1),
+    .io_in_0_bits_expCompAck         (_mshrs_0_io_tasks_txreq_bits_expCompAck),
+    .io_in_1_ready                   (_txreq_arb_io_in_1_ready),
+    .io_in_1_valid                   (_mshrs_1_io_tasks_txreq_valid),
+    .io_in_1_bits_tgtID              (_mshrs_1_io_tasks_txreq_bits_tgtID),
+    .io_in_1_bits_txnID              (_mshrs_1_io_tasks_txreq_bits_txnID),
+    .io_in_1_bits_opcode             (_mshrs_1_io_tasks_txreq_bits_opcode),
+    .io_in_1_bits_size               (3'h6),
+    .io_in_1_bits_addr               (_mshrs_1_io_tasks_txreq_bits_addr),
+    .io_in_1_bits_likelyshared       (_mshrs_1_io_tasks_txreq_bits_likelyshared),
+    .io_in_1_bits_allowRetry         (_mshrs_1_io_tasks_txreq_bits_allowRetry),
+    .io_in_1_bits_order              (2'h0),
+    .io_in_1_bits_pCrdType           (_mshrs_1_io_tasks_txreq_bits_pCrdType),
+    .io_in_1_bits_memAttr_allocate   (_mshrs_1_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable  (1'h1),
+    .io_in_1_bits_memAttr_device     (1'h0),
+    .io_in_1_bits_memAttr_ewa        (1'h1),
+    .io_in_1_bits_snpAttr            (1'h1),
+    .io_in_1_bits_expCompAck         (_mshrs_1_io_tasks_txreq_bits_expCompAck),
+    .io_in_2_ready                   (_txreq_arb_io_in_2_ready),
+    .io_in_2_valid                   (_mshrs_2_io_tasks_txreq_valid),
+    .io_in_2_bits_tgtID              (_mshrs_2_io_tasks_txreq_bits_tgtID),
+    .io_in_2_bits_txnID              (_mshrs_2_io_tasks_txreq_bits_txnID),
+    .io_in_2_bits_opcode             (_mshrs_2_io_tasks_txreq_bits_opcode),
+    .io_in_2_bits_size               (3'h6),
+    .io_in_2_bits_addr               (_mshrs_2_io_tasks_txreq_bits_addr),
+    .io_in_2_bits_likelyshared       (_mshrs_2_io_tasks_txreq_bits_likelyshared),
+    .io_in_2_bits_allowRetry         (_mshrs_2_io_tasks_txreq_bits_allowRetry),
+    .io_in_2_bits_order              (2'h0),
+    .io_in_2_bits_pCrdType           (_mshrs_2_io_tasks_txreq_bits_pCrdType),
+    .io_in_2_bits_memAttr_allocate   (_mshrs_2_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_2_bits_memAttr_cacheable  (1'h1),
+    .io_in_2_bits_memAttr_device     (1'h0),
+    .io_in_2_bits_memAttr_ewa        (1'h1),
+    .io_in_2_bits_snpAttr            (1'h1),
+    .io_in_2_bits_expCompAck         (_mshrs_2_io_tasks_txreq_bits_expCompAck),
+    .io_in_3_ready                   (_txreq_arb_io_in_3_ready),
+    .io_in_3_valid                   (_mshrs_3_io_tasks_txreq_valid),
+    .io_in_3_bits_tgtID              (_mshrs_3_io_tasks_txreq_bits_tgtID),
+    .io_in_3_bits_txnID              (_mshrs_3_io_tasks_txreq_bits_txnID),
+    .io_in_3_bits_opcode             (_mshrs_3_io_tasks_txreq_bits_opcode),
+    .io_in_3_bits_size               (3'h6),
+    .io_in_3_bits_addr               (_mshrs_3_io_tasks_txreq_bits_addr),
+    .io_in_3_bits_likelyshared       (_mshrs_3_io_tasks_txreq_bits_likelyshared),
+    .io_in_3_bits_allowRetry         (_mshrs_3_io_tasks_txreq_bits_allowRetry),
+    .io_in_3_bits_order              (2'h0),
+    .io_in_3_bits_pCrdType           (_mshrs_3_io_tasks_txreq_bits_pCrdType),
+    .io_in_3_bits_memAttr_allocate   (_mshrs_3_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_3_bits_memAttr_cacheable  (1'h1),
+    .io_in_3_bits_memAttr_device     (1'h0),
+    .io_in_3_bits_memAttr_ewa        (1'h1),
+    .io_in_3_bits_snpAttr            (1'h1),
+    .io_in_3_bits_expCompAck         (_mshrs_3_io_tasks_txreq_bits_expCompAck),
+    .io_in_4_ready                   (_txreq_arb_io_in_4_ready),
+    .io_in_4_valid                   (_mshrs_4_io_tasks_txreq_valid),
+    .io_in_4_bits_tgtID              (_mshrs_4_io_tasks_txreq_bits_tgtID),
+    .io_in_4_bits_txnID              (_mshrs_4_io_tasks_txreq_bits_txnID),
+    .io_in_4_bits_opcode             (_mshrs_4_io_tasks_txreq_bits_opcode),
+    .io_in_4_bits_size               (3'h6),
+    .io_in_4_bits_addr               (_mshrs_4_io_tasks_txreq_bits_addr),
+    .io_in_4_bits_likelyshared       (_mshrs_4_io_tasks_txreq_bits_likelyshared),
+    .io_in_4_bits_allowRetry         (_mshrs_4_io_tasks_txreq_bits_allowRetry),
+    .io_in_4_bits_order              (2'h0),
+    .io_in_4_bits_pCrdType           (_mshrs_4_io_tasks_txreq_bits_pCrdType),
+    .io_in_4_bits_memAttr_allocate   (_mshrs_4_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_4_bits_memAttr_cacheable  (1'h1),
+    .io_in_4_bits_memAttr_device     (1'h0),
+    .io_in_4_bits_memAttr_ewa        (1'h1),
+    .io_in_4_bits_snpAttr            (1'h1),
+    .io_in_4_bits_expCompAck         (_mshrs_4_io_tasks_txreq_bits_expCompAck),
+    .io_in_5_ready                   (_txreq_arb_io_in_5_ready),
+    .io_in_5_valid                   (_mshrs_5_io_tasks_txreq_valid),
+    .io_in_5_bits_tgtID              (_mshrs_5_io_tasks_txreq_bits_tgtID),
+    .io_in_5_bits_txnID              (_mshrs_5_io_tasks_txreq_bits_txnID),
+    .io_in_5_bits_opcode             (_mshrs_5_io_tasks_txreq_bits_opcode),
+    .io_in_5_bits_size               (3'h6),
+    .io_in_5_bits_addr               (_mshrs_5_io_tasks_txreq_bits_addr),
+    .io_in_5_bits_likelyshared       (_mshrs_5_io_tasks_txreq_bits_likelyshared),
+    .io_in_5_bits_allowRetry         (_mshrs_5_io_tasks_txreq_bits_allowRetry),
+    .io_in_5_bits_order              (2'h0),
+    .io_in_5_bits_pCrdType           (_mshrs_5_io_tasks_txreq_bits_pCrdType),
+    .io_in_5_bits_memAttr_allocate   (_mshrs_5_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_5_bits_memAttr_cacheable  (1'h1),
+    .io_in_5_bits_memAttr_device     (1'h0),
+    .io_in_5_bits_memAttr_ewa        (1'h1),
+    .io_in_5_bits_snpAttr            (1'h1),
+    .io_in_5_bits_expCompAck         (_mshrs_5_io_tasks_txreq_bits_expCompAck),
+    .io_in_6_ready                   (_txreq_arb_io_in_6_ready),
+    .io_in_6_valid                   (_mshrs_6_io_tasks_txreq_valid),
+    .io_in_6_bits_tgtID              (_mshrs_6_io_tasks_txreq_bits_tgtID),
+    .io_in_6_bits_txnID              (_mshrs_6_io_tasks_txreq_bits_txnID),
+    .io_in_6_bits_opcode             (_mshrs_6_io_tasks_txreq_bits_opcode),
+    .io_in_6_bits_size               (3'h6),
+    .io_in_6_bits_addr               (_mshrs_6_io_tasks_txreq_bits_addr),
+    .io_in_6_bits_likelyshared       (_mshrs_6_io_tasks_txreq_bits_likelyshared),
+    .io_in_6_bits_allowRetry         (_mshrs_6_io_tasks_txreq_bits_allowRetry),
+    .io_in_6_bits_order              (2'h0),
+    .io_in_6_bits_pCrdType           (_mshrs_6_io_tasks_txreq_bits_pCrdType),
+    .io_in_6_bits_memAttr_allocate   (_mshrs_6_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_6_bits_memAttr_cacheable  (1'h1),
+    .io_in_6_bits_memAttr_device     (1'h0),
+    .io_in_6_bits_memAttr_ewa        (1'h1),
+    .io_in_6_bits_snpAttr            (1'h1),
+    .io_in_6_bits_expCompAck         (_mshrs_6_io_tasks_txreq_bits_expCompAck),
+    .io_in_7_ready                   (_txreq_arb_io_in_7_ready),
+    .io_in_7_valid                   (_mshrs_7_io_tasks_txreq_valid),
+    .io_in_7_bits_tgtID              (_mshrs_7_io_tasks_txreq_bits_tgtID),
+    .io_in_7_bits_txnID              (_mshrs_7_io_tasks_txreq_bits_txnID),
+    .io_in_7_bits_opcode             (_mshrs_7_io_tasks_txreq_bits_opcode),
+    .io_in_7_bits_size               (3'h6),
+    .io_in_7_bits_addr               (_mshrs_7_io_tasks_txreq_bits_addr),
+    .io_in_7_bits_likelyshared       (_mshrs_7_io_tasks_txreq_bits_likelyshared),
+    .io_in_7_bits_allowRetry         (_mshrs_7_io_tasks_txreq_bits_allowRetry),
+    .io_in_7_bits_order              (2'h0),
+    .io_in_7_bits_pCrdType           (_mshrs_7_io_tasks_txreq_bits_pCrdType),
+    .io_in_7_bits_memAttr_allocate   (_mshrs_7_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_7_bits_memAttr_cacheable  (1'h1),
+    .io_in_7_bits_memAttr_device     (1'h0),
+    .io_in_7_bits_memAttr_ewa        (1'h1),
+    .io_in_7_bits_snpAttr            (1'h1),
+    .io_in_7_bits_expCompAck         (_mshrs_7_io_tasks_txreq_bits_expCompAck),
+    .io_in_8_ready                   (_txreq_arb_io_in_8_ready),
+    .io_in_8_valid                   (_mshrs_8_io_tasks_txreq_valid),
+    .io_in_8_bits_tgtID              (_mshrs_8_io_tasks_txreq_bits_tgtID),
+    .io_in_8_bits_txnID              (_mshrs_8_io_tasks_txreq_bits_txnID),
+    .io_in_8_bits_opcode             (_mshrs_8_io_tasks_txreq_bits_opcode),
+    .io_in_8_bits_size               (3'h6),
+    .io_in_8_bits_addr               (_mshrs_8_io_tasks_txreq_bits_addr),
+    .io_in_8_bits_likelyshared       (_mshrs_8_io_tasks_txreq_bits_likelyshared),
+    .io_in_8_bits_allowRetry         (_mshrs_8_io_tasks_txreq_bits_allowRetry),
+    .io_in_8_bits_order              (2'h0),
+    .io_in_8_bits_pCrdType           (_mshrs_8_io_tasks_txreq_bits_pCrdType),
+    .io_in_8_bits_memAttr_allocate   (_mshrs_8_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_8_bits_memAttr_cacheable  (1'h1),
+    .io_in_8_bits_memAttr_device     (1'h0),
+    .io_in_8_bits_memAttr_ewa        (1'h1),
+    .io_in_8_bits_snpAttr            (1'h1),
+    .io_in_8_bits_expCompAck         (_mshrs_8_io_tasks_txreq_bits_expCompAck),
+    .io_in_9_ready                   (_txreq_arb_io_in_9_ready),
+    .io_in_9_valid                   (_mshrs_9_io_tasks_txreq_valid),
+    .io_in_9_bits_tgtID              (_mshrs_9_io_tasks_txreq_bits_tgtID),
+    .io_in_9_bits_txnID              (_mshrs_9_io_tasks_txreq_bits_txnID),
+    .io_in_9_bits_opcode             (_mshrs_9_io_tasks_txreq_bits_opcode),
+    .io_in_9_bits_size               (3'h6),
+    .io_in_9_bits_addr               (_mshrs_9_io_tasks_txreq_bits_addr),
+    .io_in_9_bits_likelyshared       (_mshrs_9_io_tasks_txreq_bits_likelyshared),
+    .io_in_9_bits_allowRetry         (_mshrs_9_io_tasks_txreq_bits_allowRetry),
+    .io_in_9_bits_order              (2'h0),
+    .io_in_9_bits_pCrdType           (_mshrs_9_io_tasks_txreq_bits_pCrdType),
+    .io_in_9_bits_memAttr_allocate   (_mshrs_9_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_9_bits_memAttr_cacheable  (1'h1),
+    .io_in_9_bits_memAttr_device     (1'h0),
+    .io_in_9_bits_memAttr_ewa        (1'h1),
+    .io_in_9_bits_snpAttr            (1'h1),
+    .io_in_9_bits_expCompAck         (_mshrs_9_io_tasks_txreq_bits_expCompAck),
+    .io_in_10_ready                  (_txreq_arb_io_in_10_ready),
+    .io_in_10_valid                  (_mshrs_10_io_tasks_txreq_valid),
+    .io_in_10_bits_tgtID             (_mshrs_10_io_tasks_txreq_bits_tgtID),
+    .io_in_10_bits_txnID             (_mshrs_10_io_tasks_txreq_bits_txnID),
+    .io_in_10_bits_opcode            (_mshrs_10_io_tasks_txreq_bits_opcode),
+    .io_in_10_bits_size              (3'h6),
+    .io_in_10_bits_addr              (_mshrs_10_io_tasks_txreq_bits_addr),
+    .io_in_10_bits_likelyshared      (_mshrs_10_io_tasks_txreq_bits_likelyshared),
+    .io_in_10_bits_allowRetry        (_mshrs_10_io_tasks_txreq_bits_allowRetry),
+    .io_in_10_bits_order             (2'h0),
+    .io_in_10_bits_pCrdType          (_mshrs_10_io_tasks_txreq_bits_pCrdType),
+    .io_in_10_bits_memAttr_allocate  (_mshrs_10_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_10_bits_memAttr_cacheable (1'h1),
+    .io_in_10_bits_memAttr_device    (1'h0),
+    .io_in_10_bits_memAttr_ewa       (1'h1),
+    .io_in_10_bits_snpAttr           (1'h1),
+    .io_in_10_bits_expCompAck        (_mshrs_10_io_tasks_txreq_bits_expCompAck),
+    .io_in_11_ready                  (_txreq_arb_io_in_11_ready),
+    .io_in_11_valid                  (_mshrs_11_io_tasks_txreq_valid),
+    .io_in_11_bits_tgtID             (_mshrs_11_io_tasks_txreq_bits_tgtID),
+    .io_in_11_bits_txnID             (_mshrs_11_io_tasks_txreq_bits_txnID),
+    .io_in_11_bits_opcode            (_mshrs_11_io_tasks_txreq_bits_opcode),
+    .io_in_11_bits_size              (3'h6),
+    .io_in_11_bits_addr              (_mshrs_11_io_tasks_txreq_bits_addr),
+    .io_in_11_bits_likelyshared      (_mshrs_11_io_tasks_txreq_bits_likelyshared),
+    .io_in_11_bits_allowRetry        (_mshrs_11_io_tasks_txreq_bits_allowRetry),
+    .io_in_11_bits_order             (2'h0),
+    .io_in_11_bits_pCrdType          (_mshrs_11_io_tasks_txreq_bits_pCrdType),
+    .io_in_11_bits_memAttr_allocate  (_mshrs_11_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_11_bits_memAttr_cacheable (1'h1),
+    .io_in_11_bits_memAttr_device    (1'h0),
+    .io_in_11_bits_memAttr_ewa       (1'h1),
+    .io_in_11_bits_snpAttr           (1'h1),
+    .io_in_11_bits_expCompAck        (_mshrs_11_io_tasks_txreq_bits_expCompAck),
+    .io_in_12_ready                  (_txreq_arb_io_in_12_ready),
+    .io_in_12_valid                  (_mshrs_12_io_tasks_txreq_valid),
+    .io_in_12_bits_tgtID             (_mshrs_12_io_tasks_txreq_bits_tgtID),
+    .io_in_12_bits_txnID             (_mshrs_12_io_tasks_txreq_bits_txnID),
+    .io_in_12_bits_opcode            (_mshrs_12_io_tasks_txreq_bits_opcode),
+    .io_in_12_bits_size              (3'h6),
+    .io_in_12_bits_addr              (_mshrs_12_io_tasks_txreq_bits_addr),
+    .io_in_12_bits_likelyshared      (_mshrs_12_io_tasks_txreq_bits_likelyshared),
+    .io_in_12_bits_allowRetry        (_mshrs_12_io_tasks_txreq_bits_allowRetry),
+    .io_in_12_bits_order             (2'h0),
+    .io_in_12_bits_pCrdType          (_mshrs_12_io_tasks_txreq_bits_pCrdType),
+    .io_in_12_bits_memAttr_allocate  (_mshrs_12_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_12_bits_memAttr_cacheable (1'h1),
+    .io_in_12_bits_memAttr_device    (1'h0),
+    .io_in_12_bits_memAttr_ewa       (1'h1),
+    .io_in_12_bits_snpAttr           (1'h1),
+    .io_in_12_bits_expCompAck        (_mshrs_12_io_tasks_txreq_bits_expCompAck),
+    .io_in_13_ready                  (_txreq_arb_io_in_13_ready),
+    .io_in_13_valid                  (_mshrs_13_io_tasks_txreq_valid),
+    .io_in_13_bits_tgtID             (_mshrs_13_io_tasks_txreq_bits_tgtID),
+    .io_in_13_bits_txnID             (_mshrs_13_io_tasks_txreq_bits_txnID),
+    .io_in_13_bits_opcode            (_mshrs_13_io_tasks_txreq_bits_opcode),
+    .io_in_13_bits_size              (3'h6),
+    .io_in_13_bits_addr              (_mshrs_13_io_tasks_txreq_bits_addr),
+    .io_in_13_bits_likelyshared      (_mshrs_13_io_tasks_txreq_bits_likelyshared),
+    .io_in_13_bits_allowRetry        (_mshrs_13_io_tasks_txreq_bits_allowRetry),
+    .io_in_13_bits_order             (2'h0),
+    .io_in_13_bits_pCrdType          (_mshrs_13_io_tasks_txreq_bits_pCrdType),
+    .io_in_13_bits_memAttr_allocate  (_mshrs_13_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_13_bits_memAttr_cacheable (1'h1),
+    .io_in_13_bits_memAttr_device    (1'h0),
+    .io_in_13_bits_memAttr_ewa       (1'h1),
+    .io_in_13_bits_snpAttr           (1'h1),
+    .io_in_13_bits_expCompAck        (_mshrs_13_io_tasks_txreq_bits_expCompAck),
+    .io_in_14_ready                  (_txreq_arb_io_in_14_ready),
+    .io_in_14_valid                  (_mshrs_14_io_tasks_txreq_valid),
+    .io_in_14_bits_tgtID             (_mshrs_14_io_tasks_txreq_bits_tgtID),
+    .io_in_14_bits_txnID             (_mshrs_14_io_tasks_txreq_bits_txnID),
+    .io_in_14_bits_opcode            (_mshrs_14_io_tasks_txreq_bits_opcode),
+    .io_in_14_bits_size              (3'h6),
+    .io_in_14_bits_addr              (_mshrs_14_io_tasks_txreq_bits_addr),
+    .io_in_14_bits_likelyshared      (_mshrs_14_io_tasks_txreq_bits_likelyshared),
+    .io_in_14_bits_allowRetry        (_mshrs_14_io_tasks_txreq_bits_allowRetry),
+    .io_in_14_bits_order             (2'h0),
+    .io_in_14_bits_pCrdType          (_mshrs_14_io_tasks_txreq_bits_pCrdType),
+    .io_in_14_bits_memAttr_allocate  (_mshrs_14_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_14_bits_memAttr_cacheable (1'h1),
+    .io_in_14_bits_memAttr_device    (1'h0),
+    .io_in_14_bits_memAttr_ewa       (1'h1),
+    .io_in_14_bits_snpAttr           (1'h1),
+    .io_in_14_bits_expCompAck        (_mshrs_14_io_tasks_txreq_bits_expCompAck),
+    .io_in_15_ready                  (_txreq_arb_io_in_15_ready),
+    .io_in_15_valid                  (_mshrs_15_io_tasks_txreq_valid),
+    .io_in_15_bits_tgtID             (_mshrs_15_io_tasks_txreq_bits_tgtID),
+    .io_in_15_bits_txnID             (_mshrs_15_io_tasks_txreq_bits_txnID),
+    .io_in_15_bits_opcode            (_mshrs_15_io_tasks_txreq_bits_opcode),
+    .io_in_15_bits_size              (3'h6),
+    .io_in_15_bits_addr              (_mshrs_15_io_tasks_txreq_bits_addr),
+    .io_in_15_bits_likelyshared      (_mshrs_15_io_tasks_txreq_bits_likelyshared),
+    .io_in_15_bits_allowRetry        (_mshrs_15_io_tasks_txreq_bits_allowRetry),
+    .io_in_15_bits_order             (2'h0),
+    .io_in_15_bits_pCrdType          (_mshrs_15_io_tasks_txreq_bits_pCrdType),
+    .io_in_15_bits_memAttr_allocate  (_mshrs_15_io_tasks_txreq_bits_memAttr_allocate),
+    .io_in_15_bits_memAttr_cacheable (1'h1),
+    .io_in_15_bits_memAttr_device    (1'h0),
+    .io_in_15_bits_memAttr_ewa       (1'h1),
+    .io_in_15_bits_snpAttr           (1'h1),
+    .io_in_15_bits_expCompAck        (_mshrs_15_io_tasks_txreq_bits_expCompAck),
+    .io_out_ready                    (io_toTXREQ_ready),
+    .io_out_valid                    (io_toTXREQ_valid),
+    .io_out_bits_qos                 (io_toTXREQ_bits_qos),
+    .io_out_bits_tgtID               (io_toTXREQ_bits_tgtID),
+    .io_out_bits_txnID               (io_toTXREQ_bits_txnID),
+    .io_out_bits_opcode              (io_toTXREQ_bits_opcode),
+    .io_out_bits_size                (io_toTXREQ_bits_size),
+    .io_out_bits_addr                (io_toTXREQ_bits_addr),
+    .io_out_bits_likelyshared        (io_toTXREQ_bits_likelyshared),
+    .io_out_bits_allowRetry          (io_toTXREQ_bits_allowRetry),
+    .io_out_bits_order               (io_toTXREQ_bits_order),
+    .io_out_bits_pCrdType            (io_toTXREQ_bits_pCrdType),
+    .io_out_bits_memAttr_allocate    (io_toTXREQ_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable   (io_toTXREQ_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device      (io_toTXREQ_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa         (io_toTXREQ_bits_memAttr_ewa),
+    .io_out_bits_snpAttr             (io_toTXREQ_bits_snpAttr),
+    .io_out_bits_expCompAck          (io_toTXREQ_bits_expCompAck)
+  );
+  TwoLevelRRArbiter_7 txrsp_arb (
+    .clock                  (clock),
+    .reset                  (reset),
+    .io_in_0_ready          (_txrsp_arb_io_in_0_ready),
+    .io_in_0_valid          (_mshrs_0_io_tasks_txrsp_valid),
+    .io_in_0_bits_tgtID     (_mshrs_0_io_tasks_txrsp_bits_tgtID),
+    .io_in_0_bits_txnID     (_mshrs_0_io_tasks_txrsp_bits_txnID),
+    .io_in_0_bits_traceTag  (_mshrs_0_io_tasks_txrsp_bits_traceTag),
+    .io_in_1_ready          (_txrsp_arb_io_in_1_ready),
+    .io_in_1_valid          (_mshrs_1_io_tasks_txrsp_valid),
+    .io_in_1_bits_tgtID     (_mshrs_1_io_tasks_txrsp_bits_tgtID),
+    .io_in_1_bits_txnID     (_mshrs_1_io_tasks_txrsp_bits_txnID),
+    .io_in_1_bits_traceTag  (_mshrs_1_io_tasks_txrsp_bits_traceTag),
+    .io_in_2_ready          (_txrsp_arb_io_in_2_ready),
+    .io_in_2_valid          (_mshrs_2_io_tasks_txrsp_valid),
+    .io_in_2_bits_tgtID     (_mshrs_2_io_tasks_txrsp_bits_tgtID),
+    .io_in_2_bits_txnID     (_mshrs_2_io_tasks_txrsp_bits_txnID),
+    .io_in_2_bits_traceTag  (_mshrs_2_io_tasks_txrsp_bits_traceTag),
+    .io_in_3_ready          (_txrsp_arb_io_in_3_ready),
+    .io_in_3_valid          (_mshrs_3_io_tasks_txrsp_valid),
+    .io_in_3_bits_tgtID     (_mshrs_3_io_tasks_txrsp_bits_tgtID),
+    .io_in_3_bits_txnID     (_mshrs_3_io_tasks_txrsp_bits_txnID),
+    .io_in_3_bits_traceTag  (_mshrs_3_io_tasks_txrsp_bits_traceTag),
+    .io_in_4_ready          (_txrsp_arb_io_in_4_ready),
+    .io_in_4_valid          (_mshrs_4_io_tasks_txrsp_valid),
+    .io_in_4_bits_tgtID     (_mshrs_4_io_tasks_txrsp_bits_tgtID),
+    .io_in_4_bits_txnID     (_mshrs_4_io_tasks_txrsp_bits_txnID),
+    .io_in_4_bits_traceTag  (_mshrs_4_io_tasks_txrsp_bits_traceTag),
+    .io_in_5_ready          (_txrsp_arb_io_in_5_ready),
+    .io_in_5_valid          (_mshrs_5_io_tasks_txrsp_valid),
+    .io_in_5_bits_tgtID     (_mshrs_5_io_tasks_txrsp_bits_tgtID),
+    .io_in_5_bits_txnID     (_mshrs_5_io_tasks_txrsp_bits_txnID),
+    .io_in_5_bits_traceTag  (_mshrs_5_io_tasks_txrsp_bits_traceTag),
+    .io_in_6_ready          (_txrsp_arb_io_in_6_ready),
+    .io_in_6_valid          (_mshrs_6_io_tasks_txrsp_valid),
+    .io_in_6_bits_tgtID     (_mshrs_6_io_tasks_txrsp_bits_tgtID),
+    .io_in_6_bits_txnID     (_mshrs_6_io_tasks_txrsp_bits_txnID),
+    .io_in_6_bits_traceTag  (_mshrs_6_io_tasks_txrsp_bits_traceTag),
+    .io_in_7_ready          (_txrsp_arb_io_in_7_ready),
+    .io_in_7_valid          (_mshrs_7_io_tasks_txrsp_valid),
+    .io_in_7_bits_tgtID     (_mshrs_7_io_tasks_txrsp_bits_tgtID),
+    .io_in_7_bits_txnID     (_mshrs_7_io_tasks_txrsp_bits_txnID),
+    .io_in_7_bits_traceTag  (_mshrs_7_io_tasks_txrsp_bits_traceTag),
+    .io_in_8_ready          (_txrsp_arb_io_in_8_ready),
+    .io_in_8_valid          (_mshrs_8_io_tasks_txrsp_valid),
+    .io_in_8_bits_tgtID     (_mshrs_8_io_tasks_txrsp_bits_tgtID),
+    .io_in_8_bits_txnID     (_mshrs_8_io_tasks_txrsp_bits_txnID),
+    .io_in_8_bits_traceTag  (_mshrs_8_io_tasks_txrsp_bits_traceTag),
+    .io_in_9_ready          (_txrsp_arb_io_in_9_ready),
+    .io_in_9_valid          (_mshrs_9_io_tasks_txrsp_valid),
+    .io_in_9_bits_tgtID     (_mshrs_9_io_tasks_txrsp_bits_tgtID),
+    .io_in_9_bits_txnID     (_mshrs_9_io_tasks_txrsp_bits_txnID),
+    .io_in_9_bits_traceTag  (_mshrs_9_io_tasks_txrsp_bits_traceTag),
+    .io_in_10_ready         (_txrsp_arb_io_in_10_ready),
+    .io_in_10_valid         (_mshrs_10_io_tasks_txrsp_valid),
+    .io_in_10_bits_tgtID    (_mshrs_10_io_tasks_txrsp_bits_tgtID),
+    .io_in_10_bits_txnID    (_mshrs_10_io_tasks_txrsp_bits_txnID),
+    .io_in_10_bits_traceTag (_mshrs_10_io_tasks_txrsp_bits_traceTag),
+    .io_in_11_ready         (_txrsp_arb_io_in_11_ready),
+    .io_in_11_valid         (_mshrs_11_io_tasks_txrsp_valid),
+    .io_in_11_bits_tgtID    (_mshrs_11_io_tasks_txrsp_bits_tgtID),
+    .io_in_11_bits_txnID    (_mshrs_11_io_tasks_txrsp_bits_txnID),
+    .io_in_11_bits_traceTag (_mshrs_11_io_tasks_txrsp_bits_traceTag),
+    .io_in_12_ready         (_txrsp_arb_io_in_12_ready),
+    .io_in_12_valid         (_mshrs_12_io_tasks_txrsp_valid),
+    .io_in_12_bits_tgtID    (_mshrs_12_io_tasks_txrsp_bits_tgtID),
+    .io_in_12_bits_txnID    (_mshrs_12_io_tasks_txrsp_bits_txnID),
+    .io_in_12_bits_traceTag (_mshrs_12_io_tasks_txrsp_bits_traceTag),
+    .io_in_13_ready         (_txrsp_arb_io_in_13_ready),
+    .io_in_13_valid         (_mshrs_13_io_tasks_txrsp_valid),
+    .io_in_13_bits_tgtID    (_mshrs_13_io_tasks_txrsp_bits_tgtID),
+    .io_in_13_bits_txnID    (_mshrs_13_io_tasks_txrsp_bits_txnID),
+    .io_in_13_bits_traceTag (_mshrs_13_io_tasks_txrsp_bits_traceTag),
+    .io_in_14_ready         (_txrsp_arb_io_in_14_ready),
+    .io_in_14_valid         (_mshrs_14_io_tasks_txrsp_valid),
+    .io_in_14_bits_tgtID    (_mshrs_14_io_tasks_txrsp_bits_tgtID),
+    .io_in_14_bits_txnID    (_mshrs_14_io_tasks_txrsp_bits_txnID),
+    .io_in_14_bits_traceTag (_mshrs_14_io_tasks_txrsp_bits_traceTag),
+    .io_in_15_ready         (_txrsp_arb_io_in_15_ready),
+    .io_in_15_valid         (_mshrs_15_io_tasks_txrsp_valid),
+    .io_in_15_bits_tgtID    (_mshrs_15_io_tasks_txrsp_bits_tgtID),
+    .io_in_15_bits_txnID    (_mshrs_15_io_tasks_txrsp_bits_txnID),
+    .io_in_15_bits_traceTag (_mshrs_15_io_tasks_txrsp_bits_traceTag),
+    .io_out_ready           (io_toTXRSP_ready),
+    .io_out_valid           (io_toTXRSP_valid),
+    .io_out_bits_tgtID      (io_toTXRSP_bits_tgtID),
+    .io_out_bits_txnID      (io_toTXRSP_bits_txnID),
+    .io_out_bits_opcode     (io_toTXRSP_bits_opcode),
+    .io_out_bits_traceTag   (io_toTXRSP_bits_traceTag)
+  );
+  SourceB sourceB (
+    .clock                   (clock),
+    .reset                   (reset),
+    .io_sourceB_ready        (io_toSourceB_ready),
+    .io_sourceB_valid        (io_toSourceB_valid),
+    .io_sourceB_bits_opcode  (io_toSourceB_bits_opcode),
+    .io_sourceB_bits_param   (io_toSourceB_bits_param),
+    .io_sourceB_bits_address (io_toSourceB_bits_address),
+    .io_sourceB_bits_data    (io_toSourceB_bits_data),
+    .io_task_ready           (_sourceB_io_task_ready),
+    .io_task_valid           (_source_b_arb_io_out_valid),
+    .io_task_bits_tag        (_source_b_arb_io_out_bits_tag),
+    .io_task_bits_set        (_source_b_arb_io_out_bits_set),
+    .io_task_bits_opcode     (_source_b_arb_io_out_bits_opcode),
+    .io_task_bits_param      (_source_b_arb_io_out_bits_param),
+    .io_task_bits_alias      (_source_b_arb_io_out_bits_alias),
+    .io_grantStatus_0_valid  (io_grantStatus_0_valid),
+    .io_grantStatus_0_set    (io_grantStatus_0_set),
+    .io_grantStatus_0_tag    (io_grantStatus_0_tag),
+    .io_grantStatus_1_valid  (io_grantStatus_1_valid),
+    .io_grantStatus_1_set    (io_grantStatus_1_set),
+    .io_grantStatus_1_tag    (io_grantStatus_1_tag),
+    .io_grantStatus_2_valid  (io_grantStatus_2_valid),
+    .io_grantStatus_2_set    (io_grantStatus_2_set),
+    .io_grantStatus_2_tag    (io_grantStatus_2_tag),
+    .io_grantStatus_3_valid  (io_grantStatus_3_valid),
+    .io_grantStatus_3_set    (io_grantStatus_3_set),
+    .io_grantStatus_3_tag    (io_grantStatus_3_tag),
+    .io_grantStatus_4_valid  (io_grantStatus_4_valid),
+    .io_grantStatus_4_set    (io_grantStatus_4_set),
+    .io_grantStatus_4_tag    (io_grantStatus_4_tag),
+    .io_grantStatus_5_valid  (io_grantStatus_5_valid),
+    .io_grantStatus_5_set    (io_grantStatus_5_set),
+    .io_grantStatus_5_tag    (io_grantStatus_5_tag),
+    .io_grantStatus_6_valid  (io_grantStatus_6_valid),
+    .io_grantStatus_6_set    (io_grantStatus_6_set),
+    .io_grantStatus_6_tag    (io_grantStatus_6_tag),
+    .io_grantStatus_7_valid  (io_grantStatus_7_valid),
+    .io_grantStatus_7_set    (io_grantStatus_7_set),
+    .io_grantStatus_7_tag    (io_grantStatus_7_tag),
+    .io_grantStatus_8_valid  (io_grantStatus_8_valid),
+    .io_grantStatus_8_set    (io_grantStatus_8_set),
+    .io_grantStatus_8_tag    (io_grantStatus_8_tag),
+    .io_grantStatus_9_valid  (io_grantStatus_9_valid),
+    .io_grantStatus_9_set    (io_grantStatus_9_set),
+    .io_grantStatus_9_tag    (io_grantStatus_9_tag),
+    .io_grantStatus_10_valid (io_grantStatus_10_valid),
+    .io_grantStatus_10_set   (io_grantStatus_10_set),
+    .io_grantStatus_10_tag   (io_grantStatus_10_tag),
+    .io_grantStatus_11_valid (io_grantStatus_11_valid),
+    .io_grantStatus_11_set   (io_grantStatus_11_set),
+    .io_grantStatus_11_tag   (io_grantStatus_11_tag),
+    .io_grantStatus_12_valid (io_grantStatus_12_valid),
+    .io_grantStatus_12_set   (io_grantStatus_12_set),
+    .io_grantStatus_12_tag   (io_grantStatus_12_tag),
+    .io_grantStatus_13_valid (io_grantStatus_13_valid),
+    .io_grantStatus_13_set   (io_grantStatus_13_set),
+    .io_grantStatus_13_tag   (io_grantStatus_13_tag),
+    .io_grantStatus_14_valid (io_grantStatus_14_valid),
+    .io_grantStatus_14_set   (io_grantStatus_14_set),
+    .io_grantStatus_14_tag   (io_grantStatus_14_tag),
+    .io_grantStatus_15_valid (io_grantStatus_15_valid),
+    .io_grantStatus_15_set   (io_grantStatus_15_set),
+    .io_grantStatus_15_tag   (io_grantStatus_15_tag)
+  );
+  TwoLevelRRArbiter_9 source_b_arb (
+    .clock               (clock),
+    .reset               (reset),
+    .io_in_0_ready       (_source_b_arb_io_in_0_ready),
+    .io_in_0_valid       (_mshrs_0_io_tasks_source_b_valid),
+    .io_in_0_bits_tag    (_mshrs_0_io_tasks_source_b_bits_tag),
+    .io_in_0_bits_set    (_mshrs_0_io_tasks_source_b_bits_set),
+    .io_in_0_bits_param  (_mshrs_0_io_tasks_source_b_bits_param),
+    .io_in_0_bits_alias  (_mshrs_0_io_tasks_source_b_bits_alias),
+    .io_in_1_ready       (_source_b_arb_io_in_1_ready),
+    .io_in_1_valid       (_mshrs_1_io_tasks_source_b_valid),
+    .io_in_1_bits_tag    (_mshrs_1_io_tasks_source_b_bits_tag),
+    .io_in_1_bits_set    (_mshrs_1_io_tasks_source_b_bits_set),
+    .io_in_1_bits_param  (_mshrs_1_io_tasks_source_b_bits_param),
+    .io_in_1_bits_alias  (_mshrs_1_io_tasks_source_b_bits_alias),
+    .io_in_2_ready       (_source_b_arb_io_in_2_ready),
+    .io_in_2_valid       (_mshrs_2_io_tasks_source_b_valid),
+    .io_in_2_bits_tag    (_mshrs_2_io_tasks_source_b_bits_tag),
+    .io_in_2_bits_set    (_mshrs_2_io_tasks_source_b_bits_set),
+    .io_in_2_bits_param  (_mshrs_2_io_tasks_source_b_bits_param),
+    .io_in_2_bits_alias  (_mshrs_2_io_tasks_source_b_bits_alias),
+    .io_in_3_ready       (_source_b_arb_io_in_3_ready),
+    .io_in_3_valid       (_mshrs_3_io_tasks_source_b_valid),
+    .io_in_3_bits_tag    (_mshrs_3_io_tasks_source_b_bits_tag),
+    .io_in_3_bits_set    (_mshrs_3_io_tasks_source_b_bits_set),
+    .io_in_3_bits_param  (_mshrs_3_io_tasks_source_b_bits_param),
+    .io_in_3_bits_alias  (_mshrs_3_io_tasks_source_b_bits_alias),
+    .io_in_4_ready       (_source_b_arb_io_in_4_ready),
+    .io_in_4_valid       (_mshrs_4_io_tasks_source_b_valid),
+    .io_in_4_bits_tag    (_mshrs_4_io_tasks_source_b_bits_tag),
+    .io_in_4_bits_set    (_mshrs_4_io_tasks_source_b_bits_set),
+    .io_in_4_bits_param  (_mshrs_4_io_tasks_source_b_bits_param),
+    .io_in_4_bits_alias  (_mshrs_4_io_tasks_source_b_bits_alias),
+    .io_in_5_ready       (_source_b_arb_io_in_5_ready),
+    .io_in_5_valid       (_mshrs_5_io_tasks_source_b_valid),
+    .io_in_5_bits_tag    (_mshrs_5_io_tasks_source_b_bits_tag),
+    .io_in_5_bits_set    (_mshrs_5_io_tasks_source_b_bits_set),
+    .io_in_5_bits_param  (_mshrs_5_io_tasks_source_b_bits_param),
+    .io_in_5_bits_alias  (_mshrs_5_io_tasks_source_b_bits_alias),
+    .io_in_6_ready       (_source_b_arb_io_in_6_ready),
+    .io_in_6_valid       (_mshrs_6_io_tasks_source_b_valid),
+    .io_in_6_bits_tag    (_mshrs_6_io_tasks_source_b_bits_tag),
+    .io_in_6_bits_set    (_mshrs_6_io_tasks_source_b_bits_set),
+    .io_in_6_bits_param  (_mshrs_6_io_tasks_source_b_bits_param),
+    .io_in_6_bits_alias  (_mshrs_6_io_tasks_source_b_bits_alias),
+    .io_in_7_ready       (_source_b_arb_io_in_7_ready),
+    .io_in_7_valid       (_mshrs_7_io_tasks_source_b_valid),
+    .io_in_7_bits_tag    (_mshrs_7_io_tasks_source_b_bits_tag),
+    .io_in_7_bits_set    (_mshrs_7_io_tasks_source_b_bits_set),
+    .io_in_7_bits_param  (_mshrs_7_io_tasks_source_b_bits_param),
+    .io_in_7_bits_alias  (_mshrs_7_io_tasks_source_b_bits_alias),
+    .io_in_8_ready       (_source_b_arb_io_in_8_ready),
+    .io_in_8_valid       (_mshrs_8_io_tasks_source_b_valid),
+    .io_in_8_bits_tag    (_mshrs_8_io_tasks_source_b_bits_tag),
+    .io_in_8_bits_set    (_mshrs_8_io_tasks_source_b_bits_set),
+    .io_in_8_bits_param  (_mshrs_8_io_tasks_source_b_bits_param),
+    .io_in_8_bits_alias  (_mshrs_8_io_tasks_source_b_bits_alias),
+    .io_in_9_ready       (_source_b_arb_io_in_9_ready),
+    .io_in_9_valid       (_mshrs_9_io_tasks_source_b_valid),
+    .io_in_9_bits_tag    (_mshrs_9_io_tasks_source_b_bits_tag),
+    .io_in_9_bits_set    (_mshrs_9_io_tasks_source_b_bits_set),
+    .io_in_9_bits_param  (_mshrs_9_io_tasks_source_b_bits_param),
+    .io_in_9_bits_alias  (_mshrs_9_io_tasks_source_b_bits_alias),
+    .io_in_10_ready      (_source_b_arb_io_in_10_ready),
+    .io_in_10_valid      (_mshrs_10_io_tasks_source_b_valid),
+    .io_in_10_bits_tag   (_mshrs_10_io_tasks_source_b_bits_tag),
+    .io_in_10_bits_set   (_mshrs_10_io_tasks_source_b_bits_set),
+    .io_in_10_bits_param (_mshrs_10_io_tasks_source_b_bits_param),
+    .io_in_10_bits_alias (_mshrs_10_io_tasks_source_b_bits_alias),
+    .io_in_11_ready      (_source_b_arb_io_in_11_ready),
+    .io_in_11_valid      (_mshrs_11_io_tasks_source_b_valid),
+    .io_in_11_bits_tag   (_mshrs_11_io_tasks_source_b_bits_tag),
+    .io_in_11_bits_set   (_mshrs_11_io_tasks_source_b_bits_set),
+    .io_in_11_bits_param (_mshrs_11_io_tasks_source_b_bits_param),
+    .io_in_11_bits_alias (_mshrs_11_io_tasks_source_b_bits_alias),
+    .io_in_12_ready      (_source_b_arb_io_in_12_ready),
+    .io_in_12_valid      (_mshrs_12_io_tasks_source_b_valid),
+    .io_in_12_bits_tag   (_mshrs_12_io_tasks_source_b_bits_tag),
+    .io_in_12_bits_set   (_mshrs_12_io_tasks_source_b_bits_set),
+    .io_in_12_bits_param (_mshrs_12_io_tasks_source_b_bits_param),
+    .io_in_12_bits_alias (_mshrs_12_io_tasks_source_b_bits_alias),
+    .io_in_13_ready      (_source_b_arb_io_in_13_ready),
+    .io_in_13_valid      (_mshrs_13_io_tasks_source_b_valid),
+    .io_in_13_bits_tag   (_mshrs_13_io_tasks_source_b_bits_tag),
+    .io_in_13_bits_set   (_mshrs_13_io_tasks_source_b_bits_set),
+    .io_in_13_bits_param (_mshrs_13_io_tasks_source_b_bits_param),
+    .io_in_13_bits_alias (_mshrs_13_io_tasks_source_b_bits_alias),
+    .io_in_14_ready      (_source_b_arb_io_in_14_ready),
+    .io_in_14_valid      (_mshrs_14_io_tasks_source_b_valid),
+    .io_in_14_bits_tag   (_mshrs_14_io_tasks_source_b_bits_tag),
+    .io_in_14_bits_set   (_mshrs_14_io_tasks_source_b_bits_set),
+    .io_in_14_bits_param (_mshrs_14_io_tasks_source_b_bits_param),
+    .io_in_14_bits_alias (_mshrs_14_io_tasks_source_b_bits_alias),
+    .io_in_15_ready      (_source_b_arb_io_in_15_ready),
+    .io_in_15_valid      (_mshrs_15_io_tasks_source_b_valid),
+    .io_in_15_bits_tag   (_mshrs_15_io_tasks_source_b_bits_tag),
+    .io_in_15_bits_set   (_mshrs_15_io_tasks_source_b_bits_set),
+    .io_in_15_bits_param (_mshrs_15_io_tasks_source_b_bits_param),
+    .io_in_15_bits_alias (_mshrs_15_io_tasks_source_b_bits_alias),
+    .io_out_ready        (_sourceB_io_task_ready),
+    .io_out_valid        (_source_b_arb_io_out_valid),
+    .io_out_bits_tag     (_source_b_arb_io_out_bits_tag),
+    .io_out_bits_set     (_source_b_arb_io_out_bits_set),
+    .io_out_bits_opcode  (_source_b_arb_io_out_bits_opcode),
+    .io_out_bits_param   (_source_b_arb_io_out_bits_param),
+    .io_out_bits_alias   (_source_b_arb_io_out_bits_alias)
+  );
+  TwoLevelRRArbiter_10 mshr_task_arb (
+    .clock                                       (clock),
+    .reset                                       (reset),
+    .io_in_0_ready                               (_mshr_task_arb_io_in_0_ready),
+    .io_in_0_valid                               (_mshrs_0_io_tasks_mainpipe_valid),
+    .io_in_0_bits_channel
+      (_mshrs_0_io_tasks_mainpipe_bits_channel),
+    .io_in_0_bits_txChannel
+      (_mshrs_0_io_tasks_mainpipe_bits_txChannel),
+    .io_in_0_bits_set                            (_mshrs_0_io_tasks_mainpipe_bits_set),
+    .io_in_0_bits_tag                            (_mshrs_0_io_tasks_mainpipe_bits_tag),
+    .io_in_0_bits_off                            (_mshrs_0_io_tasks_mainpipe_bits_off),
+    .io_in_0_bits_alias                          (_mshrs_0_io_tasks_mainpipe_bits_alias),
+    .io_in_0_bits_isKeyword
+      (_mshrs_0_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_0_bits_opcode                         (_mshrs_0_io_tasks_mainpipe_bits_opcode),
+    .io_in_0_bits_param                          (_mshrs_0_io_tasks_mainpipe_bits_param),
+    .io_in_0_bits_size                           (_mshrs_0_io_tasks_mainpipe_bits_size),
+    .io_in_0_bits_sourceId
+      (_mshrs_0_io_tasks_mainpipe_bits_sourceId),
+    .io_in_0_bits_denied                         (_mshrs_0_io_tasks_mainpipe_bits_denied),
+    .io_in_0_bits_corrupt
+      (_mshrs_0_io_tasks_mainpipe_bits_corrupt),
+    .io_in_0_bits_aliasTask
+      (_mshrs_0_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_0_bits_useProbeData
+      (_mshrs_0_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_0_bits_mshrRetry
+      (_mshrs_0_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_0_bits_readProbeDataDown
+      (_mshrs_0_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_0_bits_fromL2pft
+      (_mshrs_0_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_0_bits_dirty                          (_mshrs_0_io_tasks_mainpipe_bits_dirty),
+    .io_in_0_bits_way                            (_mshrs_0_io_tasks_mainpipe_bits_way),
+    .io_in_0_bits_meta_dirty
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_0_bits_meta_state
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_state),
+    .io_in_0_bits_meta_clients
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_0_bits_meta_alias
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_0_bits_meta_prefetch
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_0_bits_meta_prefetchSrc
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_0_bits_meta_accessed
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_0_bits_meta_tagErr
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_0_bits_meta_dataErr
+      (_mshrs_0_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_0_bits_metaWen
+      (_mshrs_0_io_tasks_mainpipe_bits_metaWen),
+    .io_in_0_bits_tagWen                         (_mshrs_0_io_tasks_mainpipe_bits_tagWen),
+    .io_in_0_bits_dsWen                          (_mshrs_0_io_tasks_mainpipe_bits_dsWen),
+    .io_in_0_bits_replTask
+      (_mshrs_0_io_tasks_mainpipe_bits_replTask),
+    .io_in_0_bits_cmoTask
+      (_mshrs_0_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_0_bits_reqSource
+      (_mshrs_0_io_tasks_mainpipe_bits_reqSource),
+    .io_in_0_bits_mergeA                         (_mshrs_0_io_tasks_mainpipe_bits_mergeA),
+    .io_in_0_bits_aMergeTask_off
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_0_bits_aMergeTask_alias
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_0_bits_aMergeTask_vaddr
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_0_bits_aMergeTask_isKeyword
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_0_bits_aMergeTask_opcode
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_0_bits_aMergeTask_param
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_0_bits_aMergeTask_sourceId
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_0_bits_aMergeTask_meta_dirty
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_0_bits_aMergeTask_meta_state
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_0_bits_aMergeTask_meta_clients
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_0_bits_aMergeTask_meta_alias
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_0_bits_aMergeTask_meta_accessed
+      (_mshrs_0_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_0_bits_snpHitRelease
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_0_bits_snpHitReleaseToInval
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_0_bits_snpHitReleaseToClean
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_0_bits_snpHitReleaseWithData
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_0_bits_snpHitReleaseIdx
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_0_bits_snpHitReleaseMeta_dirty
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_0_bits_snpHitReleaseMeta_state
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_0_bits_snpHitReleaseMeta_clients
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_0_bits_snpHitReleaseMeta_alias
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_0_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_0_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_0_bits_snpHitReleaseMeta_accessed
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_0_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_0_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_0_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_0_bits_tgtID                          (_mshrs_0_io_tasks_mainpipe_bits_tgtID),
+    .io_in_0_bits_txnID                          (_mshrs_0_io_tasks_mainpipe_bits_txnID),
+    .io_in_0_bits_homeNID
+      (_mshrs_0_io_tasks_mainpipe_bits_homeNID),
+    .io_in_0_bits_dbID                           (_mshrs_0_io_tasks_mainpipe_bits_dbID),
+    .io_in_0_bits_chiOpcode
+      (_mshrs_0_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_0_bits_resp                           (_mshrs_0_io_tasks_mainpipe_bits_resp),
+    .io_in_0_bits_fwdState
+      (_mshrs_0_io_tasks_mainpipe_bits_fwdState),
+    .io_in_0_bits_retToSrc
+      (_mshrs_0_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_0_bits_likelyshared
+      (_mshrs_0_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_0_bits_expCompAck
+      (_mshrs_0_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_0_bits_allowRetry
+      (_mshrs_0_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_0_bits_memAttr_allocate
+      (_mshrs_0_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable
+      (_mshrs_0_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_ewa
+      (_mshrs_0_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_0_bits_traceTag
+      (_mshrs_0_io_tasks_mainpipe_bits_traceTag),
+    .io_in_1_ready                               (_mshr_task_arb_io_in_1_ready),
+    .io_in_1_valid                               (_mshrs_1_io_tasks_mainpipe_valid),
+    .io_in_1_bits_channel
+      (_mshrs_1_io_tasks_mainpipe_bits_channel),
+    .io_in_1_bits_txChannel
+      (_mshrs_1_io_tasks_mainpipe_bits_txChannel),
+    .io_in_1_bits_set                            (_mshrs_1_io_tasks_mainpipe_bits_set),
+    .io_in_1_bits_tag                            (_mshrs_1_io_tasks_mainpipe_bits_tag),
+    .io_in_1_bits_off                            (_mshrs_1_io_tasks_mainpipe_bits_off),
+    .io_in_1_bits_alias                          (_mshrs_1_io_tasks_mainpipe_bits_alias),
+    .io_in_1_bits_isKeyword
+      (_mshrs_1_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_1_bits_opcode                         (_mshrs_1_io_tasks_mainpipe_bits_opcode),
+    .io_in_1_bits_param                          (_mshrs_1_io_tasks_mainpipe_bits_param),
+    .io_in_1_bits_size                           (_mshrs_1_io_tasks_mainpipe_bits_size),
+    .io_in_1_bits_sourceId
+      (_mshrs_1_io_tasks_mainpipe_bits_sourceId),
+    .io_in_1_bits_denied                         (_mshrs_1_io_tasks_mainpipe_bits_denied),
+    .io_in_1_bits_corrupt
+      (_mshrs_1_io_tasks_mainpipe_bits_corrupt),
+    .io_in_1_bits_aliasTask
+      (_mshrs_1_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_1_bits_useProbeData
+      (_mshrs_1_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_1_bits_mshrRetry
+      (_mshrs_1_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_1_bits_readProbeDataDown
+      (_mshrs_1_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_1_bits_fromL2pft
+      (_mshrs_1_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_1_bits_dirty                          (_mshrs_1_io_tasks_mainpipe_bits_dirty),
+    .io_in_1_bits_way                            (_mshrs_1_io_tasks_mainpipe_bits_way),
+    .io_in_1_bits_meta_dirty
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_1_bits_meta_state
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_state),
+    .io_in_1_bits_meta_clients
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_1_bits_meta_alias
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_1_bits_meta_prefetch
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_1_bits_meta_prefetchSrc
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_1_bits_meta_accessed
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_1_bits_meta_tagErr
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_1_bits_meta_dataErr
+      (_mshrs_1_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_1_bits_metaWen
+      (_mshrs_1_io_tasks_mainpipe_bits_metaWen),
+    .io_in_1_bits_tagWen                         (_mshrs_1_io_tasks_mainpipe_bits_tagWen),
+    .io_in_1_bits_dsWen                          (_mshrs_1_io_tasks_mainpipe_bits_dsWen),
+    .io_in_1_bits_replTask
+      (_mshrs_1_io_tasks_mainpipe_bits_replTask),
+    .io_in_1_bits_cmoTask
+      (_mshrs_1_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_1_bits_reqSource
+      (_mshrs_1_io_tasks_mainpipe_bits_reqSource),
+    .io_in_1_bits_mergeA                         (_mshrs_1_io_tasks_mainpipe_bits_mergeA),
+    .io_in_1_bits_aMergeTask_off
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_1_bits_aMergeTask_alias
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_1_bits_aMergeTask_vaddr
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_1_bits_aMergeTask_isKeyword
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_1_bits_aMergeTask_opcode
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_1_bits_aMergeTask_param
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_1_bits_aMergeTask_sourceId
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_1_bits_aMergeTask_meta_dirty
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_1_bits_aMergeTask_meta_state
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_1_bits_aMergeTask_meta_clients
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_1_bits_aMergeTask_meta_alias
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_1_bits_aMergeTask_meta_accessed
+      (_mshrs_1_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_1_bits_snpHitRelease
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_1_bits_snpHitReleaseToInval
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_1_bits_snpHitReleaseToClean
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_1_bits_snpHitReleaseWithData
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_1_bits_snpHitReleaseIdx
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_1_bits_snpHitReleaseMeta_dirty
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_1_bits_snpHitReleaseMeta_state
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_1_bits_snpHitReleaseMeta_clients
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_1_bits_snpHitReleaseMeta_alias
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_1_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_1_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_1_bits_snpHitReleaseMeta_accessed
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_1_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_1_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_1_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_1_bits_tgtID                          (_mshrs_1_io_tasks_mainpipe_bits_tgtID),
+    .io_in_1_bits_txnID                          (_mshrs_1_io_tasks_mainpipe_bits_txnID),
+    .io_in_1_bits_homeNID
+      (_mshrs_1_io_tasks_mainpipe_bits_homeNID),
+    .io_in_1_bits_dbID                           (_mshrs_1_io_tasks_mainpipe_bits_dbID),
+    .io_in_1_bits_chiOpcode
+      (_mshrs_1_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_1_bits_resp                           (_mshrs_1_io_tasks_mainpipe_bits_resp),
+    .io_in_1_bits_fwdState
+      (_mshrs_1_io_tasks_mainpipe_bits_fwdState),
+    .io_in_1_bits_retToSrc
+      (_mshrs_1_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_1_bits_likelyshared
+      (_mshrs_1_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_1_bits_expCompAck
+      (_mshrs_1_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_1_bits_allowRetry
+      (_mshrs_1_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_1_bits_memAttr_allocate
+      (_mshrs_1_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable
+      (_mshrs_1_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_1_bits_memAttr_ewa
+      (_mshrs_1_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_1_bits_traceTag
+      (_mshrs_1_io_tasks_mainpipe_bits_traceTag),
+    .io_in_2_ready                               (_mshr_task_arb_io_in_2_ready),
+    .io_in_2_valid                               (_mshrs_2_io_tasks_mainpipe_valid),
+    .io_in_2_bits_channel
+      (_mshrs_2_io_tasks_mainpipe_bits_channel),
+    .io_in_2_bits_txChannel
+      (_mshrs_2_io_tasks_mainpipe_bits_txChannel),
+    .io_in_2_bits_set                            (_mshrs_2_io_tasks_mainpipe_bits_set),
+    .io_in_2_bits_tag                            (_mshrs_2_io_tasks_mainpipe_bits_tag),
+    .io_in_2_bits_off                            (_mshrs_2_io_tasks_mainpipe_bits_off),
+    .io_in_2_bits_alias                          (_mshrs_2_io_tasks_mainpipe_bits_alias),
+    .io_in_2_bits_isKeyword
+      (_mshrs_2_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_2_bits_opcode                         (_mshrs_2_io_tasks_mainpipe_bits_opcode),
+    .io_in_2_bits_param                          (_mshrs_2_io_tasks_mainpipe_bits_param),
+    .io_in_2_bits_size                           (_mshrs_2_io_tasks_mainpipe_bits_size),
+    .io_in_2_bits_sourceId
+      (_mshrs_2_io_tasks_mainpipe_bits_sourceId),
+    .io_in_2_bits_denied                         (_mshrs_2_io_tasks_mainpipe_bits_denied),
+    .io_in_2_bits_corrupt
+      (_mshrs_2_io_tasks_mainpipe_bits_corrupt),
+    .io_in_2_bits_aliasTask
+      (_mshrs_2_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_2_bits_useProbeData
+      (_mshrs_2_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_2_bits_mshrRetry
+      (_mshrs_2_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_2_bits_readProbeDataDown
+      (_mshrs_2_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_2_bits_fromL2pft
+      (_mshrs_2_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_2_bits_dirty                          (_mshrs_2_io_tasks_mainpipe_bits_dirty),
+    .io_in_2_bits_way                            (_mshrs_2_io_tasks_mainpipe_bits_way),
+    .io_in_2_bits_meta_dirty
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_2_bits_meta_state
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_state),
+    .io_in_2_bits_meta_clients
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_2_bits_meta_alias
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_2_bits_meta_prefetch
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_2_bits_meta_prefetchSrc
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_2_bits_meta_accessed
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_2_bits_meta_tagErr
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_2_bits_meta_dataErr
+      (_mshrs_2_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_2_bits_metaWen
+      (_mshrs_2_io_tasks_mainpipe_bits_metaWen),
+    .io_in_2_bits_tagWen                         (_mshrs_2_io_tasks_mainpipe_bits_tagWen),
+    .io_in_2_bits_dsWen                          (_mshrs_2_io_tasks_mainpipe_bits_dsWen),
+    .io_in_2_bits_replTask
+      (_mshrs_2_io_tasks_mainpipe_bits_replTask),
+    .io_in_2_bits_cmoTask
+      (_mshrs_2_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_2_bits_reqSource
+      (_mshrs_2_io_tasks_mainpipe_bits_reqSource),
+    .io_in_2_bits_mergeA                         (_mshrs_2_io_tasks_mainpipe_bits_mergeA),
+    .io_in_2_bits_aMergeTask_off
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_2_bits_aMergeTask_alias
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_2_bits_aMergeTask_vaddr
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_2_bits_aMergeTask_isKeyword
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_2_bits_aMergeTask_opcode
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_2_bits_aMergeTask_param
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_2_bits_aMergeTask_sourceId
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_2_bits_aMergeTask_meta_dirty
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_2_bits_aMergeTask_meta_state
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_2_bits_aMergeTask_meta_clients
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_2_bits_aMergeTask_meta_alias
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_2_bits_aMergeTask_meta_accessed
+      (_mshrs_2_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_2_bits_snpHitRelease
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_2_bits_snpHitReleaseToInval
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_2_bits_snpHitReleaseToClean
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_2_bits_snpHitReleaseWithData
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_2_bits_snpHitReleaseIdx
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_2_bits_snpHitReleaseMeta_dirty
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_2_bits_snpHitReleaseMeta_state
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_2_bits_snpHitReleaseMeta_clients
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_2_bits_snpHitReleaseMeta_alias
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_2_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_2_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_2_bits_snpHitReleaseMeta_accessed
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_2_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_2_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_2_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_2_bits_tgtID                          (_mshrs_2_io_tasks_mainpipe_bits_tgtID),
+    .io_in_2_bits_txnID                          (_mshrs_2_io_tasks_mainpipe_bits_txnID),
+    .io_in_2_bits_homeNID
+      (_mshrs_2_io_tasks_mainpipe_bits_homeNID),
+    .io_in_2_bits_dbID                           (_mshrs_2_io_tasks_mainpipe_bits_dbID),
+    .io_in_2_bits_chiOpcode
+      (_mshrs_2_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_2_bits_resp                           (_mshrs_2_io_tasks_mainpipe_bits_resp),
+    .io_in_2_bits_fwdState
+      (_mshrs_2_io_tasks_mainpipe_bits_fwdState),
+    .io_in_2_bits_retToSrc
+      (_mshrs_2_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_2_bits_likelyshared
+      (_mshrs_2_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_2_bits_expCompAck
+      (_mshrs_2_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_2_bits_allowRetry
+      (_mshrs_2_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_2_bits_memAttr_allocate
+      (_mshrs_2_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_2_bits_memAttr_cacheable
+      (_mshrs_2_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_2_bits_memAttr_ewa
+      (_mshrs_2_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_2_bits_traceTag
+      (_mshrs_2_io_tasks_mainpipe_bits_traceTag),
+    .io_in_3_ready                               (_mshr_task_arb_io_in_3_ready),
+    .io_in_3_valid                               (_mshrs_3_io_tasks_mainpipe_valid),
+    .io_in_3_bits_channel
+      (_mshrs_3_io_tasks_mainpipe_bits_channel),
+    .io_in_3_bits_txChannel
+      (_mshrs_3_io_tasks_mainpipe_bits_txChannel),
+    .io_in_3_bits_set                            (_mshrs_3_io_tasks_mainpipe_bits_set),
+    .io_in_3_bits_tag                            (_mshrs_3_io_tasks_mainpipe_bits_tag),
+    .io_in_3_bits_off                            (_mshrs_3_io_tasks_mainpipe_bits_off),
+    .io_in_3_bits_alias                          (_mshrs_3_io_tasks_mainpipe_bits_alias),
+    .io_in_3_bits_isKeyword
+      (_mshrs_3_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_3_bits_opcode                         (_mshrs_3_io_tasks_mainpipe_bits_opcode),
+    .io_in_3_bits_param                          (_mshrs_3_io_tasks_mainpipe_bits_param),
+    .io_in_3_bits_size                           (_mshrs_3_io_tasks_mainpipe_bits_size),
+    .io_in_3_bits_sourceId
+      (_mshrs_3_io_tasks_mainpipe_bits_sourceId),
+    .io_in_3_bits_denied                         (_mshrs_3_io_tasks_mainpipe_bits_denied),
+    .io_in_3_bits_corrupt
+      (_mshrs_3_io_tasks_mainpipe_bits_corrupt),
+    .io_in_3_bits_aliasTask
+      (_mshrs_3_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_3_bits_useProbeData
+      (_mshrs_3_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_3_bits_mshrRetry
+      (_mshrs_3_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_3_bits_readProbeDataDown
+      (_mshrs_3_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_3_bits_fromL2pft
+      (_mshrs_3_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_3_bits_dirty                          (_mshrs_3_io_tasks_mainpipe_bits_dirty),
+    .io_in_3_bits_way                            (_mshrs_3_io_tasks_mainpipe_bits_way),
+    .io_in_3_bits_meta_dirty
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_3_bits_meta_state
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_state),
+    .io_in_3_bits_meta_clients
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_3_bits_meta_alias
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_3_bits_meta_prefetch
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_3_bits_meta_prefetchSrc
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_3_bits_meta_accessed
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_3_bits_meta_tagErr
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_3_bits_meta_dataErr
+      (_mshrs_3_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_3_bits_metaWen
+      (_mshrs_3_io_tasks_mainpipe_bits_metaWen),
+    .io_in_3_bits_tagWen                         (_mshrs_3_io_tasks_mainpipe_bits_tagWen),
+    .io_in_3_bits_dsWen                          (_mshrs_3_io_tasks_mainpipe_bits_dsWen),
+    .io_in_3_bits_replTask
+      (_mshrs_3_io_tasks_mainpipe_bits_replTask),
+    .io_in_3_bits_cmoTask
+      (_mshrs_3_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_3_bits_reqSource
+      (_mshrs_3_io_tasks_mainpipe_bits_reqSource),
+    .io_in_3_bits_mergeA                         (_mshrs_3_io_tasks_mainpipe_bits_mergeA),
+    .io_in_3_bits_aMergeTask_off
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_3_bits_aMergeTask_alias
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_3_bits_aMergeTask_vaddr
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_3_bits_aMergeTask_isKeyword
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_3_bits_aMergeTask_opcode
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_3_bits_aMergeTask_param
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_3_bits_aMergeTask_sourceId
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_3_bits_aMergeTask_meta_dirty
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_3_bits_aMergeTask_meta_state
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_3_bits_aMergeTask_meta_clients
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_3_bits_aMergeTask_meta_alias
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_3_bits_aMergeTask_meta_accessed
+      (_mshrs_3_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_3_bits_snpHitRelease
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_3_bits_snpHitReleaseToInval
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_3_bits_snpHitReleaseToClean
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_3_bits_snpHitReleaseWithData
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_3_bits_snpHitReleaseIdx
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_3_bits_snpHitReleaseMeta_dirty
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_3_bits_snpHitReleaseMeta_state
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_3_bits_snpHitReleaseMeta_clients
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_3_bits_snpHitReleaseMeta_alias
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_3_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_3_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_3_bits_snpHitReleaseMeta_accessed
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_3_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_3_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_3_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_3_bits_tgtID                          (_mshrs_3_io_tasks_mainpipe_bits_tgtID),
+    .io_in_3_bits_txnID                          (_mshrs_3_io_tasks_mainpipe_bits_txnID),
+    .io_in_3_bits_homeNID
+      (_mshrs_3_io_tasks_mainpipe_bits_homeNID),
+    .io_in_3_bits_dbID                           (_mshrs_3_io_tasks_mainpipe_bits_dbID),
+    .io_in_3_bits_chiOpcode
+      (_mshrs_3_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_3_bits_resp                           (_mshrs_3_io_tasks_mainpipe_bits_resp),
+    .io_in_3_bits_fwdState
+      (_mshrs_3_io_tasks_mainpipe_bits_fwdState),
+    .io_in_3_bits_retToSrc
+      (_mshrs_3_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_3_bits_likelyshared
+      (_mshrs_3_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_3_bits_expCompAck
+      (_mshrs_3_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_3_bits_allowRetry
+      (_mshrs_3_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_3_bits_memAttr_allocate
+      (_mshrs_3_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_3_bits_memAttr_cacheable
+      (_mshrs_3_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_3_bits_memAttr_ewa
+      (_mshrs_3_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_3_bits_traceTag
+      (_mshrs_3_io_tasks_mainpipe_bits_traceTag),
+    .io_in_4_ready                               (_mshr_task_arb_io_in_4_ready),
+    .io_in_4_valid                               (_mshrs_4_io_tasks_mainpipe_valid),
+    .io_in_4_bits_channel
+      (_mshrs_4_io_tasks_mainpipe_bits_channel),
+    .io_in_4_bits_txChannel
+      (_mshrs_4_io_tasks_mainpipe_bits_txChannel),
+    .io_in_4_bits_set                            (_mshrs_4_io_tasks_mainpipe_bits_set),
+    .io_in_4_bits_tag                            (_mshrs_4_io_tasks_mainpipe_bits_tag),
+    .io_in_4_bits_off                            (_mshrs_4_io_tasks_mainpipe_bits_off),
+    .io_in_4_bits_alias                          (_mshrs_4_io_tasks_mainpipe_bits_alias),
+    .io_in_4_bits_isKeyword
+      (_mshrs_4_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_4_bits_opcode                         (_mshrs_4_io_tasks_mainpipe_bits_opcode),
+    .io_in_4_bits_param                          (_mshrs_4_io_tasks_mainpipe_bits_param),
+    .io_in_4_bits_size                           (_mshrs_4_io_tasks_mainpipe_bits_size),
+    .io_in_4_bits_sourceId
+      (_mshrs_4_io_tasks_mainpipe_bits_sourceId),
+    .io_in_4_bits_denied                         (_mshrs_4_io_tasks_mainpipe_bits_denied),
+    .io_in_4_bits_corrupt
+      (_mshrs_4_io_tasks_mainpipe_bits_corrupt),
+    .io_in_4_bits_aliasTask
+      (_mshrs_4_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_4_bits_useProbeData
+      (_mshrs_4_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_4_bits_mshrRetry
+      (_mshrs_4_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_4_bits_readProbeDataDown
+      (_mshrs_4_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_4_bits_fromL2pft
+      (_mshrs_4_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_4_bits_dirty                          (_mshrs_4_io_tasks_mainpipe_bits_dirty),
+    .io_in_4_bits_way                            (_mshrs_4_io_tasks_mainpipe_bits_way),
+    .io_in_4_bits_meta_dirty
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_4_bits_meta_state
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_state),
+    .io_in_4_bits_meta_clients
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_4_bits_meta_alias
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_4_bits_meta_prefetch
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_4_bits_meta_prefetchSrc
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_4_bits_meta_accessed
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_4_bits_meta_tagErr
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_4_bits_meta_dataErr
+      (_mshrs_4_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_4_bits_metaWen
+      (_mshrs_4_io_tasks_mainpipe_bits_metaWen),
+    .io_in_4_bits_tagWen                         (_mshrs_4_io_tasks_mainpipe_bits_tagWen),
+    .io_in_4_bits_dsWen                          (_mshrs_4_io_tasks_mainpipe_bits_dsWen),
+    .io_in_4_bits_replTask
+      (_mshrs_4_io_tasks_mainpipe_bits_replTask),
+    .io_in_4_bits_cmoTask
+      (_mshrs_4_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_4_bits_reqSource
+      (_mshrs_4_io_tasks_mainpipe_bits_reqSource),
+    .io_in_4_bits_mergeA                         (_mshrs_4_io_tasks_mainpipe_bits_mergeA),
+    .io_in_4_bits_aMergeTask_off
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_4_bits_aMergeTask_alias
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_4_bits_aMergeTask_vaddr
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_4_bits_aMergeTask_isKeyword
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_4_bits_aMergeTask_opcode
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_4_bits_aMergeTask_param
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_4_bits_aMergeTask_sourceId
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_4_bits_aMergeTask_meta_dirty
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_4_bits_aMergeTask_meta_state
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_4_bits_aMergeTask_meta_clients
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_4_bits_aMergeTask_meta_alias
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_4_bits_aMergeTask_meta_accessed
+      (_mshrs_4_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_4_bits_snpHitRelease
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_4_bits_snpHitReleaseToInval
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_4_bits_snpHitReleaseToClean
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_4_bits_snpHitReleaseWithData
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_4_bits_snpHitReleaseIdx
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_4_bits_snpHitReleaseMeta_dirty
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_4_bits_snpHitReleaseMeta_state
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_4_bits_snpHitReleaseMeta_clients
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_4_bits_snpHitReleaseMeta_alias
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_4_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_4_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_4_bits_snpHitReleaseMeta_accessed
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_4_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_4_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_4_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_4_bits_tgtID                          (_mshrs_4_io_tasks_mainpipe_bits_tgtID),
+    .io_in_4_bits_txnID                          (_mshrs_4_io_tasks_mainpipe_bits_txnID),
+    .io_in_4_bits_homeNID
+      (_mshrs_4_io_tasks_mainpipe_bits_homeNID),
+    .io_in_4_bits_dbID                           (_mshrs_4_io_tasks_mainpipe_bits_dbID),
+    .io_in_4_bits_chiOpcode
+      (_mshrs_4_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_4_bits_resp                           (_mshrs_4_io_tasks_mainpipe_bits_resp),
+    .io_in_4_bits_fwdState
+      (_mshrs_4_io_tasks_mainpipe_bits_fwdState),
+    .io_in_4_bits_retToSrc
+      (_mshrs_4_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_4_bits_likelyshared
+      (_mshrs_4_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_4_bits_expCompAck
+      (_mshrs_4_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_4_bits_allowRetry
+      (_mshrs_4_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_4_bits_memAttr_allocate
+      (_mshrs_4_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_4_bits_memAttr_cacheable
+      (_mshrs_4_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_4_bits_memAttr_ewa
+      (_mshrs_4_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_4_bits_traceTag
+      (_mshrs_4_io_tasks_mainpipe_bits_traceTag),
+    .io_in_5_ready                               (_mshr_task_arb_io_in_5_ready),
+    .io_in_5_valid                               (_mshrs_5_io_tasks_mainpipe_valid),
+    .io_in_5_bits_channel
+      (_mshrs_5_io_tasks_mainpipe_bits_channel),
+    .io_in_5_bits_txChannel
+      (_mshrs_5_io_tasks_mainpipe_bits_txChannel),
+    .io_in_5_bits_set                            (_mshrs_5_io_tasks_mainpipe_bits_set),
+    .io_in_5_bits_tag                            (_mshrs_5_io_tasks_mainpipe_bits_tag),
+    .io_in_5_bits_off                            (_mshrs_5_io_tasks_mainpipe_bits_off),
+    .io_in_5_bits_alias                          (_mshrs_5_io_tasks_mainpipe_bits_alias),
+    .io_in_5_bits_isKeyword
+      (_mshrs_5_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_5_bits_opcode                         (_mshrs_5_io_tasks_mainpipe_bits_opcode),
+    .io_in_5_bits_param                          (_mshrs_5_io_tasks_mainpipe_bits_param),
+    .io_in_5_bits_size                           (_mshrs_5_io_tasks_mainpipe_bits_size),
+    .io_in_5_bits_sourceId
+      (_mshrs_5_io_tasks_mainpipe_bits_sourceId),
+    .io_in_5_bits_denied                         (_mshrs_5_io_tasks_mainpipe_bits_denied),
+    .io_in_5_bits_corrupt
+      (_mshrs_5_io_tasks_mainpipe_bits_corrupt),
+    .io_in_5_bits_aliasTask
+      (_mshrs_5_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_5_bits_useProbeData
+      (_mshrs_5_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_5_bits_mshrRetry
+      (_mshrs_5_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_5_bits_readProbeDataDown
+      (_mshrs_5_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_5_bits_fromL2pft
+      (_mshrs_5_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_5_bits_dirty                          (_mshrs_5_io_tasks_mainpipe_bits_dirty),
+    .io_in_5_bits_way                            (_mshrs_5_io_tasks_mainpipe_bits_way),
+    .io_in_5_bits_meta_dirty
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_5_bits_meta_state
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_state),
+    .io_in_5_bits_meta_clients
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_5_bits_meta_alias
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_5_bits_meta_prefetch
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_5_bits_meta_prefetchSrc
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_5_bits_meta_accessed
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_5_bits_meta_tagErr
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_5_bits_meta_dataErr
+      (_mshrs_5_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_5_bits_metaWen
+      (_mshrs_5_io_tasks_mainpipe_bits_metaWen),
+    .io_in_5_bits_tagWen                         (_mshrs_5_io_tasks_mainpipe_bits_tagWen),
+    .io_in_5_bits_dsWen                          (_mshrs_5_io_tasks_mainpipe_bits_dsWen),
+    .io_in_5_bits_replTask
+      (_mshrs_5_io_tasks_mainpipe_bits_replTask),
+    .io_in_5_bits_cmoTask
+      (_mshrs_5_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_5_bits_reqSource
+      (_mshrs_5_io_tasks_mainpipe_bits_reqSource),
+    .io_in_5_bits_mergeA                         (_mshrs_5_io_tasks_mainpipe_bits_mergeA),
+    .io_in_5_bits_aMergeTask_off
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_5_bits_aMergeTask_alias
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_5_bits_aMergeTask_vaddr
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_5_bits_aMergeTask_isKeyword
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_5_bits_aMergeTask_opcode
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_5_bits_aMergeTask_param
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_5_bits_aMergeTask_sourceId
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_5_bits_aMergeTask_meta_dirty
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_5_bits_aMergeTask_meta_state
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_5_bits_aMergeTask_meta_clients
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_5_bits_aMergeTask_meta_alias
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_5_bits_aMergeTask_meta_accessed
+      (_mshrs_5_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_5_bits_snpHitRelease
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_5_bits_snpHitReleaseToInval
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_5_bits_snpHitReleaseToClean
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_5_bits_snpHitReleaseWithData
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_5_bits_snpHitReleaseIdx
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_5_bits_snpHitReleaseMeta_dirty
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_5_bits_snpHitReleaseMeta_state
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_5_bits_snpHitReleaseMeta_clients
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_5_bits_snpHitReleaseMeta_alias
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_5_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_5_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_5_bits_snpHitReleaseMeta_accessed
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_5_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_5_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_5_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_5_bits_tgtID                          (_mshrs_5_io_tasks_mainpipe_bits_tgtID),
+    .io_in_5_bits_txnID                          (_mshrs_5_io_tasks_mainpipe_bits_txnID),
+    .io_in_5_bits_homeNID
+      (_mshrs_5_io_tasks_mainpipe_bits_homeNID),
+    .io_in_5_bits_dbID                           (_mshrs_5_io_tasks_mainpipe_bits_dbID),
+    .io_in_5_bits_chiOpcode
+      (_mshrs_5_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_5_bits_resp                           (_mshrs_5_io_tasks_mainpipe_bits_resp),
+    .io_in_5_bits_fwdState
+      (_mshrs_5_io_tasks_mainpipe_bits_fwdState),
+    .io_in_5_bits_retToSrc
+      (_mshrs_5_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_5_bits_likelyshared
+      (_mshrs_5_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_5_bits_expCompAck
+      (_mshrs_5_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_5_bits_allowRetry
+      (_mshrs_5_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_5_bits_memAttr_allocate
+      (_mshrs_5_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_5_bits_memAttr_cacheable
+      (_mshrs_5_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_5_bits_memAttr_ewa
+      (_mshrs_5_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_5_bits_traceTag
+      (_mshrs_5_io_tasks_mainpipe_bits_traceTag),
+    .io_in_6_ready                               (_mshr_task_arb_io_in_6_ready),
+    .io_in_6_valid                               (_mshrs_6_io_tasks_mainpipe_valid),
+    .io_in_6_bits_channel
+      (_mshrs_6_io_tasks_mainpipe_bits_channel),
+    .io_in_6_bits_txChannel
+      (_mshrs_6_io_tasks_mainpipe_bits_txChannel),
+    .io_in_6_bits_set                            (_mshrs_6_io_tasks_mainpipe_bits_set),
+    .io_in_6_bits_tag                            (_mshrs_6_io_tasks_mainpipe_bits_tag),
+    .io_in_6_bits_off                            (_mshrs_6_io_tasks_mainpipe_bits_off),
+    .io_in_6_bits_alias                          (_mshrs_6_io_tasks_mainpipe_bits_alias),
+    .io_in_6_bits_isKeyword
+      (_mshrs_6_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_6_bits_opcode                         (_mshrs_6_io_tasks_mainpipe_bits_opcode),
+    .io_in_6_bits_param                          (_mshrs_6_io_tasks_mainpipe_bits_param),
+    .io_in_6_bits_size                           (_mshrs_6_io_tasks_mainpipe_bits_size),
+    .io_in_6_bits_sourceId
+      (_mshrs_6_io_tasks_mainpipe_bits_sourceId),
+    .io_in_6_bits_denied                         (_mshrs_6_io_tasks_mainpipe_bits_denied),
+    .io_in_6_bits_corrupt
+      (_mshrs_6_io_tasks_mainpipe_bits_corrupt),
+    .io_in_6_bits_aliasTask
+      (_mshrs_6_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_6_bits_useProbeData
+      (_mshrs_6_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_6_bits_mshrRetry
+      (_mshrs_6_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_6_bits_readProbeDataDown
+      (_mshrs_6_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_6_bits_fromL2pft
+      (_mshrs_6_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_6_bits_dirty                          (_mshrs_6_io_tasks_mainpipe_bits_dirty),
+    .io_in_6_bits_way                            (_mshrs_6_io_tasks_mainpipe_bits_way),
+    .io_in_6_bits_meta_dirty
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_6_bits_meta_state
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_state),
+    .io_in_6_bits_meta_clients
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_6_bits_meta_alias
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_6_bits_meta_prefetch
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_6_bits_meta_prefetchSrc
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_6_bits_meta_accessed
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_6_bits_meta_tagErr
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_6_bits_meta_dataErr
+      (_mshrs_6_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_6_bits_metaWen
+      (_mshrs_6_io_tasks_mainpipe_bits_metaWen),
+    .io_in_6_bits_tagWen                         (_mshrs_6_io_tasks_mainpipe_bits_tagWen),
+    .io_in_6_bits_dsWen                          (_mshrs_6_io_tasks_mainpipe_bits_dsWen),
+    .io_in_6_bits_replTask
+      (_mshrs_6_io_tasks_mainpipe_bits_replTask),
+    .io_in_6_bits_cmoTask
+      (_mshrs_6_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_6_bits_reqSource
+      (_mshrs_6_io_tasks_mainpipe_bits_reqSource),
+    .io_in_6_bits_mergeA                         (_mshrs_6_io_tasks_mainpipe_bits_mergeA),
+    .io_in_6_bits_aMergeTask_off
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_6_bits_aMergeTask_alias
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_6_bits_aMergeTask_vaddr
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_6_bits_aMergeTask_isKeyword
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_6_bits_aMergeTask_opcode
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_6_bits_aMergeTask_param
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_6_bits_aMergeTask_sourceId
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_6_bits_aMergeTask_meta_dirty
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_6_bits_aMergeTask_meta_state
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_6_bits_aMergeTask_meta_clients
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_6_bits_aMergeTask_meta_alias
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_6_bits_aMergeTask_meta_accessed
+      (_mshrs_6_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_6_bits_snpHitRelease
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_6_bits_snpHitReleaseToInval
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_6_bits_snpHitReleaseToClean
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_6_bits_snpHitReleaseWithData
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_6_bits_snpHitReleaseIdx
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_6_bits_snpHitReleaseMeta_dirty
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_6_bits_snpHitReleaseMeta_state
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_6_bits_snpHitReleaseMeta_clients
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_6_bits_snpHitReleaseMeta_alias
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_6_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_6_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_6_bits_snpHitReleaseMeta_accessed
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_6_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_6_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_6_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_6_bits_tgtID                          (_mshrs_6_io_tasks_mainpipe_bits_tgtID),
+    .io_in_6_bits_txnID                          (_mshrs_6_io_tasks_mainpipe_bits_txnID),
+    .io_in_6_bits_homeNID
+      (_mshrs_6_io_tasks_mainpipe_bits_homeNID),
+    .io_in_6_bits_dbID                           (_mshrs_6_io_tasks_mainpipe_bits_dbID),
+    .io_in_6_bits_chiOpcode
+      (_mshrs_6_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_6_bits_resp                           (_mshrs_6_io_tasks_mainpipe_bits_resp),
+    .io_in_6_bits_fwdState
+      (_mshrs_6_io_tasks_mainpipe_bits_fwdState),
+    .io_in_6_bits_retToSrc
+      (_mshrs_6_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_6_bits_likelyshared
+      (_mshrs_6_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_6_bits_expCompAck
+      (_mshrs_6_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_6_bits_allowRetry
+      (_mshrs_6_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_6_bits_memAttr_allocate
+      (_mshrs_6_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_6_bits_memAttr_cacheable
+      (_mshrs_6_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_6_bits_memAttr_ewa
+      (_mshrs_6_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_6_bits_traceTag
+      (_mshrs_6_io_tasks_mainpipe_bits_traceTag),
+    .io_in_7_ready                               (_mshr_task_arb_io_in_7_ready),
+    .io_in_7_valid                               (_mshrs_7_io_tasks_mainpipe_valid),
+    .io_in_7_bits_channel
+      (_mshrs_7_io_tasks_mainpipe_bits_channel),
+    .io_in_7_bits_txChannel
+      (_mshrs_7_io_tasks_mainpipe_bits_txChannel),
+    .io_in_7_bits_set                            (_mshrs_7_io_tasks_mainpipe_bits_set),
+    .io_in_7_bits_tag                            (_mshrs_7_io_tasks_mainpipe_bits_tag),
+    .io_in_7_bits_off                            (_mshrs_7_io_tasks_mainpipe_bits_off),
+    .io_in_7_bits_alias                          (_mshrs_7_io_tasks_mainpipe_bits_alias),
+    .io_in_7_bits_isKeyword
+      (_mshrs_7_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_7_bits_opcode                         (_mshrs_7_io_tasks_mainpipe_bits_opcode),
+    .io_in_7_bits_param                          (_mshrs_7_io_tasks_mainpipe_bits_param),
+    .io_in_7_bits_size                           (_mshrs_7_io_tasks_mainpipe_bits_size),
+    .io_in_7_bits_sourceId
+      (_mshrs_7_io_tasks_mainpipe_bits_sourceId),
+    .io_in_7_bits_denied                         (_mshrs_7_io_tasks_mainpipe_bits_denied),
+    .io_in_7_bits_corrupt
+      (_mshrs_7_io_tasks_mainpipe_bits_corrupt),
+    .io_in_7_bits_aliasTask
+      (_mshrs_7_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_7_bits_useProbeData
+      (_mshrs_7_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_7_bits_mshrRetry
+      (_mshrs_7_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_7_bits_readProbeDataDown
+      (_mshrs_7_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_7_bits_fromL2pft
+      (_mshrs_7_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_7_bits_dirty                          (_mshrs_7_io_tasks_mainpipe_bits_dirty),
+    .io_in_7_bits_way                            (_mshrs_7_io_tasks_mainpipe_bits_way),
+    .io_in_7_bits_meta_dirty
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_7_bits_meta_state
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_state),
+    .io_in_7_bits_meta_clients
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_7_bits_meta_alias
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_7_bits_meta_prefetch
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_7_bits_meta_prefetchSrc
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_7_bits_meta_accessed
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_7_bits_meta_tagErr
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_7_bits_meta_dataErr
+      (_mshrs_7_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_7_bits_metaWen
+      (_mshrs_7_io_tasks_mainpipe_bits_metaWen),
+    .io_in_7_bits_tagWen                         (_mshrs_7_io_tasks_mainpipe_bits_tagWen),
+    .io_in_7_bits_dsWen                          (_mshrs_7_io_tasks_mainpipe_bits_dsWen),
+    .io_in_7_bits_replTask
+      (_mshrs_7_io_tasks_mainpipe_bits_replTask),
+    .io_in_7_bits_cmoTask
+      (_mshrs_7_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_7_bits_reqSource
+      (_mshrs_7_io_tasks_mainpipe_bits_reqSource),
+    .io_in_7_bits_mergeA                         (_mshrs_7_io_tasks_mainpipe_bits_mergeA),
+    .io_in_7_bits_aMergeTask_off
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_7_bits_aMergeTask_alias
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_7_bits_aMergeTask_vaddr
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_7_bits_aMergeTask_isKeyword
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_7_bits_aMergeTask_opcode
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_7_bits_aMergeTask_param
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_7_bits_aMergeTask_sourceId
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_7_bits_aMergeTask_meta_dirty
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_7_bits_aMergeTask_meta_state
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_7_bits_aMergeTask_meta_clients
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_7_bits_aMergeTask_meta_alias
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_7_bits_aMergeTask_meta_accessed
+      (_mshrs_7_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_7_bits_snpHitRelease
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_7_bits_snpHitReleaseToInval
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_7_bits_snpHitReleaseToClean
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_7_bits_snpHitReleaseWithData
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_7_bits_snpHitReleaseIdx
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_7_bits_snpHitReleaseMeta_dirty
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_7_bits_snpHitReleaseMeta_state
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_7_bits_snpHitReleaseMeta_clients
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_7_bits_snpHitReleaseMeta_alias
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_7_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_7_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_7_bits_snpHitReleaseMeta_accessed
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_7_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_7_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_7_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_7_bits_tgtID                          (_mshrs_7_io_tasks_mainpipe_bits_tgtID),
+    .io_in_7_bits_txnID                          (_mshrs_7_io_tasks_mainpipe_bits_txnID),
+    .io_in_7_bits_homeNID
+      (_mshrs_7_io_tasks_mainpipe_bits_homeNID),
+    .io_in_7_bits_dbID                           (_mshrs_7_io_tasks_mainpipe_bits_dbID),
+    .io_in_7_bits_chiOpcode
+      (_mshrs_7_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_7_bits_resp                           (_mshrs_7_io_tasks_mainpipe_bits_resp),
+    .io_in_7_bits_fwdState
+      (_mshrs_7_io_tasks_mainpipe_bits_fwdState),
+    .io_in_7_bits_retToSrc
+      (_mshrs_7_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_7_bits_likelyshared
+      (_mshrs_7_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_7_bits_expCompAck
+      (_mshrs_7_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_7_bits_allowRetry
+      (_mshrs_7_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_7_bits_memAttr_allocate
+      (_mshrs_7_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_7_bits_memAttr_cacheable
+      (_mshrs_7_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_7_bits_memAttr_ewa
+      (_mshrs_7_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_7_bits_traceTag
+      (_mshrs_7_io_tasks_mainpipe_bits_traceTag),
+    .io_in_8_ready                               (_mshr_task_arb_io_in_8_ready),
+    .io_in_8_valid                               (_mshrs_8_io_tasks_mainpipe_valid),
+    .io_in_8_bits_channel
+      (_mshrs_8_io_tasks_mainpipe_bits_channel),
+    .io_in_8_bits_txChannel
+      (_mshrs_8_io_tasks_mainpipe_bits_txChannel),
+    .io_in_8_bits_set                            (_mshrs_8_io_tasks_mainpipe_bits_set),
+    .io_in_8_bits_tag                            (_mshrs_8_io_tasks_mainpipe_bits_tag),
+    .io_in_8_bits_off                            (_mshrs_8_io_tasks_mainpipe_bits_off),
+    .io_in_8_bits_alias                          (_mshrs_8_io_tasks_mainpipe_bits_alias),
+    .io_in_8_bits_isKeyword
+      (_mshrs_8_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_8_bits_opcode                         (_mshrs_8_io_tasks_mainpipe_bits_opcode),
+    .io_in_8_bits_param                          (_mshrs_8_io_tasks_mainpipe_bits_param),
+    .io_in_8_bits_size                           (_mshrs_8_io_tasks_mainpipe_bits_size),
+    .io_in_8_bits_sourceId
+      (_mshrs_8_io_tasks_mainpipe_bits_sourceId),
+    .io_in_8_bits_denied                         (_mshrs_8_io_tasks_mainpipe_bits_denied),
+    .io_in_8_bits_corrupt
+      (_mshrs_8_io_tasks_mainpipe_bits_corrupt),
+    .io_in_8_bits_aliasTask
+      (_mshrs_8_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_8_bits_useProbeData
+      (_mshrs_8_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_8_bits_mshrRetry
+      (_mshrs_8_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_8_bits_readProbeDataDown
+      (_mshrs_8_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_8_bits_fromL2pft
+      (_mshrs_8_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_8_bits_dirty                          (_mshrs_8_io_tasks_mainpipe_bits_dirty),
+    .io_in_8_bits_way                            (_mshrs_8_io_tasks_mainpipe_bits_way),
+    .io_in_8_bits_meta_dirty
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_8_bits_meta_state
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_state),
+    .io_in_8_bits_meta_clients
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_8_bits_meta_alias
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_8_bits_meta_prefetch
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_8_bits_meta_prefetchSrc
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_8_bits_meta_accessed
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_8_bits_meta_tagErr
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_8_bits_meta_dataErr
+      (_mshrs_8_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_8_bits_metaWen
+      (_mshrs_8_io_tasks_mainpipe_bits_metaWen),
+    .io_in_8_bits_tagWen                         (_mshrs_8_io_tasks_mainpipe_bits_tagWen),
+    .io_in_8_bits_dsWen                          (_mshrs_8_io_tasks_mainpipe_bits_dsWen),
+    .io_in_8_bits_replTask
+      (_mshrs_8_io_tasks_mainpipe_bits_replTask),
+    .io_in_8_bits_cmoTask
+      (_mshrs_8_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_8_bits_reqSource
+      (_mshrs_8_io_tasks_mainpipe_bits_reqSource),
+    .io_in_8_bits_mergeA                         (_mshrs_8_io_tasks_mainpipe_bits_mergeA),
+    .io_in_8_bits_aMergeTask_off
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_8_bits_aMergeTask_alias
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_8_bits_aMergeTask_vaddr
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_8_bits_aMergeTask_isKeyword
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_8_bits_aMergeTask_opcode
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_8_bits_aMergeTask_param
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_8_bits_aMergeTask_sourceId
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_8_bits_aMergeTask_meta_dirty
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_8_bits_aMergeTask_meta_state
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_8_bits_aMergeTask_meta_clients
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_8_bits_aMergeTask_meta_alias
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_8_bits_aMergeTask_meta_accessed
+      (_mshrs_8_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_8_bits_snpHitRelease
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_8_bits_snpHitReleaseToInval
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_8_bits_snpHitReleaseToClean
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_8_bits_snpHitReleaseWithData
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_8_bits_snpHitReleaseIdx
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_8_bits_snpHitReleaseMeta_dirty
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_8_bits_snpHitReleaseMeta_state
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_8_bits_snpHitReleaseMeta_clients
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_8_bits_snpHitReleaseMeta_alias
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_8_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_8_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_8_bits_snpHitReleaseMeta_accessed
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_8_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_8_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_8_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_8_bits_tgtID                          (_mshrs_8_io_tasks_mainpipe_bits_tgtID),
+    .io_in_8_bits_txnID                          (_mshrs_8_io_tasks_mainpipe_bits_txnID),
+    .io_in_8_bits_homeNID
+      (_mshrs_8_io_tasks_mainpipe_bits_homeNID),
+    .io_in_8_bits_dbID                           (_mshrs_8_io_tasks_mainpipe_bits_dbID),
+    .io_in_8_bits_chiOpcode
+      (_mshrs_8_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_8_bits_resp                           (_mshrs_8_io_tasks_mainpipe_bits_resp),
+    .io_in_8_bits_fwdState
+      (_mshrs_8_io_tasks_mainpipe_bits_fwdState),
+    .io_in_8_bits_retToSrc
+      (_mshrs_8_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_8_bits_likelyshared
+      (_mshrs_8_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_8_bits_expCompAck
+      (_mshrs_8_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_8_bits_allowRetry
+      (_mshrs_8_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_8_bits_memAttr_allocate
+      (_mshrs_8_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_8_bits_memAttr_cacheable
+      (_mshrs_8_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_8_bits_memAttr_ewa
+      (_mshrs_8_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_8_bits_traceTag
+      (_mshrs_8_io_tasks_mainpipe_bits_traceTag),
+    .io_in_9_ready                               (_mshr_task_arb_io_in_9_ready),
+    .io_in_9_valid                               (_mshrs_9_io_tasks_mainpipe_valid),
+    .io_in_9_bits_channel
+      (_mshrs_9_io_tasks_mainpipe_bits_channel),
+    .io_in_9_bits_txChannel
+      (_mshrs_9_io_tasks_mainpipe_bits_txChannel),
+    .io_in_9_bits_set                            (_mshrs_9_io_tasks_mainpipe_bits_set),
+    .io_in_9_bits_tag                            (_mshrs_9_io_tasks_mainpipe_bits_tag),
+    .io_in_9_bits_off                            (_mshrs_9_io_tasks_mainpipe_bits_off),
+    .io_in_9_bits_alias                          (_mshrs_9_io_tasks_mainpipe_bits_alias),
+    .io_in_9_bits_isKeyword
+      (_mshrs_9_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_9_bits_opcode                         (_mshrs_9_io_tasks_mainpipe_bits_opcode),
+    .io_in_9_bits_param                          (_mshrs_9_io_tasks_mainpipe_bits_param),
+    .io_in_9_bits_size                           (_mshrs_9_io_tasks_mainpipe_bits_size),
+    .io_in_9_bits_sourceId
+      (_mshrs_9_io_tasks_mainpipe_bits_sourceId),
+    .io_in_9_bits_denied                         (_mshrs_9_io_tasks_mainpipe_bits_denied),
+    .io_in_9_bits_corrupt
+      (_mshrs_9_io_tasks_mainpipe_bits_corrupt),
+    .io_in_9_bits_aliasTask
+      (_mshrs_9_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_9_bits_useProbeData
+      (_mshrs_9_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_9_bits_mshrRetry
+      (_mshrs_9_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_9_bits_readProbeDataDown
+      (_mshrs_9_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_9_bits_fromL2pft
+      (_mshrs_9_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_9_bits_dirty                          (_mshrs_9_io_tasks_mainpipe_bits_dirty),
+    .io_in_9_bits_way                            (_mshrs_9_io_tasks_mainpipe_bits_way),
+    .io_in_9_bits_meta_dirty
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_9_bits_meta_state
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_state),
+    .io_in_9_bits_meta_clients
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_9_bits_meta_alias
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_9_bits_meta_prefetch
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_9_bits_meta_prefetchSrc
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_9_bits_meta_accessed
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_9_bits_meta_tagErr
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_9_bits_meta_dataErr
+      (_mshrs_9_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_9_bits_metaWen
+      (_mshrs_9_io_tasks_mainpipe_bits_metaWen),
+    .io_in_9_bits_tagWen                         (_mshrs_9_io_tasks_mainpipe_bits_tagWen),
+    .io_in_9_bits_dsWen                          (_mshrs_9_io_tasks_mainpipe_bits_dsWen),
+    .io_in_9_bits_replTask
+      (_mshrs_9_io_tasks_mainpipe_bits_replTask),
+    .io_in_9_bits_cmoTask
+      (_mshrs_9_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_9_bits_reqSource
+      (_mshrs_9_io_tasks_mainpipe_bits_reqSource),
+    .io_in_9_bits_mergeA                         (_mshrs_9_io_tasks_mainpipe_bits_mergeA),
+    .io_in_9_bits_aMergeTask_off
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_9_bits_aMergeTask_alias
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_9_bits_aMergeTask_vaddr
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_9_bits_aMergeTask_isKeyword
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_9_bits_aMergeTask_opcode
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_9_bits_aMergeTask_param
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_9_bits_aMergeTask_sourceId
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_9_bits_aMergeTask_meta_dirty
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_9_bits_aMergeTask_meta_state
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_9_bits_aMergeTask_meta_clients
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_9_bits_aMergeTask_meta_alias
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_9_bits_aMergeTask_meta_accessed
+      (_mshrs_9_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_9_bits_snpHitRelease
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_9_bits_snpHitReleaseToInval
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_9_bits_snpHitReleaseToClean
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_9_bits_snpHitReleaseWithData
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_9_bits_snpHitReleaseIdx
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_9_bits_snpHitReleaseMeta_dirty
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_9_bits_snpHitReleaseMeta_state
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_9_bits_snpHitReleaseMeta_clients
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_9_bits_snpHitReleaseMeta_alias
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_9_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_9_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_9_bits_snpHitReleaseMeta_accessed
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_9_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_9_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_9_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_9_bits_tgtID                          (_mshrs_9_io_tasks_mainpipe_bits_tgtID),
+    .io_in_9_bits_txnID                          (_mshrs_9_io_tasks_mainpipe_bits_txnID),
+    .io_in_9_bits_homeNID
+      (_mshrs_9_io_tasks_mainpipe_bits_homeNID),
+    .io_in_9_bits_dbID                           (_mshrs_9_io_tasks_mainpipe_bits_dbID),
+    .io_in_9_bits_chiOpcode
+      (_mshrs_9_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_9_bits_resp                           (_mshrs_9_io_tasks_mainpipe_bits_resp),
+    .io_in_9_bits_fwdState
+      (_mshrs_9_io_tasks_mainpipe_bits_fwdState),
+    .io_in_9_bits_retToSrc
+      (_mshrs_9_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_9_bits_likelyshared
+      (_mshrs_9_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_9_bits_expCompAck
+      (_mshrs_9_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_9_bits_allowRetry
+      (_mshrs_9_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_9_bits_memAttr_allocate
+      (_mshrs_9_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_9_bits_memAttr_cacheable
+      (_mshrs_9_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_9_bits_memAttr_ewa
+      (_mshrs_9_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_9_bits_traceTag
+      (_mshrs_9_io_tasks_mainpipe_bits_traceTag),
+    .io_in_10_ready                              (_mshr_task_arb_io_in_10_ready),
+    .io_in_10_valid                              (_mshrs_10_io_tasks_mainpipe_valid),
+    .io_in_10_bits_channel
+      (_mshrs_10_io_tasks_mainpipe_bits_channel),
+    .io_in_10_bits_txChannel
+      (_mshrs_10_io_tasks_mainpipe_bits_txChannel),
+    .io_in_10_bits_set                           (_mshrs_10_io_tasks_mainpipe_bits_set),
+    .io_in_10_bits_tag                           (_mshrs_10_io_tasks_mainpipe_bits_tag),
+    .io_in_10_bits_off                           (_mshrs_10_io_tasks_mainpipe_bits_off),
+    .io_in_10_bits_alias                         (_mshrs_10_io_tasks_mainpipe_bits_alias),
+    .io_in_10_bits_isKeyword
+      (_mshrs_10_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_10_bits_opcode
+      (_mshrs_10_io_tasks_mainpipe_bits_opcode),
+    .io_in_10_bits_param                         (_mshrs_10_io_tasks_mainpipe_bits_param),
+    .io_in_10_bits_size                          (_mshrs_10_io_tasks_mainpipe_bits_size),
+    .io_in_10_bits_sourceId
+      (_mshrs_10_io_tasks_mainpipe_bits_sourceId),
+    .io_in_10_bits_denied
+      (_mshrs_10_io_tasks_mainpipe_bits_denied),
+    .io_in_10_bits_corrupt
+      (_mshrs_10_io_tasks_mainpipe_bits_corrupt),
+    .io_in_10_bits_aliasTask
+      (_mshrs_10_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_10_bits_useProbeData
+      (_mshrs_10_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_10_bits_mshrRetry
+      (_mshrs_10_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_10_bits_readProbeDataDown
+      (_mshrs_10_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_10_bits_fromL2pft
+      (_mshrs_10_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_10_bits_dirty                         (_mshrs_10_io_tasks_mainpipe_bits_dirty),
+    .io_in_10_bits_way                           (_mshrs_10_io_tasks_mainpipe_bits_way),
+    .io_in_10_bits_meta_dirty
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_10_bits_meta_state
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_state),
+    .io_in_10_bits_meta_clients
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_10_bits_meta_alias
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_10_bits_meta_prefetch
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_10_bits_meta_prefetchSrc
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_10_bits_meta_accessed
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_10_bits_meta_tagErr
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_10_bits_meta_dataErr
+      (_mshrs_10_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_10_bits_metaWen
+      (_mshrs_10_io_tasks_mainpipe_bits_metaWen),
+    .io_in_10_bits_tagWen
+      (_mshrs_10_io_tasks_mainpipe_bits_tagWen),
+    .io_in_10_bits_dsWen                         (_mshrs_10_io_tasks_mainpipe_bits_dsWen),
+    .io_in_10_bits_replTask
+      (_mshrs_10_io_tasks_mainpipe_bits_replTask),
+    .io_in_10_bits_cmoTask
+      (_mshrs_10_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_10_bits_reqSource
+      (_mshrs_10_io_tasks_mainpipe_bits_reqSource),
+    .io_in_10_bits_mergeA
+      (_mshrs_10_io_tasks_mainpipe_bits_mergeA),
+    .io_in_10_bits_aMergeTask_off
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_10_bits_aMergeTask_alias
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_10_bits_aMergeTask_vaddr
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_10_bits_aMergeTask_isKeyword
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_10_bits_aMergeTask_opcode
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_10_bits_aMergeTask_param
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_10_bits_aMergeTask_sourceId
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_10_bits_aMergeTask_meta_dirty
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_10_bits_aMergeTask_meta_state
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_10_bits_aMergeTask_meta_clients
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_10_bits_aMergeTask_meta_alias
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_10_bits_aMergeTask_meta_accessed
+      (_mshrs_10_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_10_bits_snpHitRelease
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_10_bits_snpHitReleaseToInval
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_10_bits_snpHitReleaseToClean
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_10_bits_snpHitReleaseWithData
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_10_bits_snpHitReleaseIdx
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_10_bits_snpHitReleaseMeta_dirty
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_10_bits_snpHitReleaseMeta_state
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_10_bits_snpHitReleaseMeta_clients
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_10_bits_snpHitReleaseMeta_alias
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_10_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_10_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_10_bits_snpHitReleaseMeta_accessed
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_10_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_10_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_10_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_10_bits_tgtID                         (_mshrs_10_io_tasks_mainpipe_bits_tgtID),
+    .io_in_10_bits_txnID                         (_mshrs_10_io_tasks_mainpipe_bits_txnID),
+    .io_in_10_bits_homeNID
+      (_mshrs_10_io_tasks_mainpipe_bits_homeNID),
+    .io_in_10_bits_dbID                          (_mshrs_10_io_tasks_mainpipe_bits_dbID),
+    .io_in_10_bits_chiOpcode
+      (_mshrs_10_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_10_bits_resp                          (_mshrs_10_io_tasks_mainpipe_bits_resp),
+    .io_in_10_bits_fwdState
+      (_mshrs_10_io_tasks_mainpipe_bits_fwdState),
+    .io_in_10_bits_retToSrc
+      (_mshrs_10_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_10_bits_likelyshared
+      (_mshrs_10_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_10_bits_expCompAck
+      (_mshrs_10_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_10_bits_allowRetry
+      (_mshrs_10_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_10_bits_memAttr_allocate
+      (_mshrs_10_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_10_bits_memAttr_cacheable
+      (_mshrs_10_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_10_bits_memAttr_ewa
+      (_mshrs_10_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_10_bits_traceTag
+      (_mshrs_10_io_tasks_mainpipe_bits_traceTag),
+    .io_in_11_ready                              (_mshr_task_arb_io_in_11_ready),
+    .io_in_11_valid                              (_mshrs_11_io_tasks_mainpipe_valid),
+    .io_in_11_bits_channel
+      (_mshrs_11_io_tasks_mainpipe_bits_channel),
+    .io_in_11_bits_txChannel
+      (_mshrs_11_io_tasks_mainpipe_bits_txChannel),
+    .io_in_11_bits_set                           (_mshrs_11_io_tasks_mainpipe_bits_set),
+    .io_in_11_bits_tag                           (_mshrs_11_io_tasks_mainpipe_bits_tag),
+    .io_in_11_bits_off                           (_mshrs_11_io_tasks_mainpipe_bits_off),
+    .io_in_11_bits_alias                         (_mshrs_11_io_tasks_mainpipe_bits_alias),
+    .io_in_11_bits_isKeyword
+      (_mshrs_11_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_11_bits_opcode
+      (_mshrs_11_io_tasks_mainpipe_bits_opcode),
+    .io_in_11_bits_param                         (_mshrs_11_io_tasks_mainpipe_bits_param),
+    .io_in_11_bits_size                          (_mshrs_11_io_tasks_mainpipe_bits_size),
+    .io_in_11_bits_sourceId
+      (_mshrs_11_io_tasks_mainpipe_bits_sourceId),
+    .io_in_11_bits_denied
+      (_mshrs_11_io_tasks_mainpipe_bits_denied),
+    .io_in_11_bits_corrupt
+      (_mshrs_11_io_tasks_mainpipe_bits_corrupt),
+    .io_in_11_bits_aliasTask
+      (_mshrs_11_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_11_bits_useProbeData
+      (_mshrs_11_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_11_bits_mshrRetry
+      (_mshrs_11_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_11_bits_readProbeDataDown
+      (_mshrs_11_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_11_bits_fromL2pft
+      (_mshrs_11_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_11_bits_dirty                         (_mshrs_11_io_tasks_mainpipe_bits_dirty),
+    .io_in_11_bits_way                           (_mshrs_11_io_tasks_mainpipe_bits_way),
+    .io_in_11_bits_meta_dirty
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_11_bits_meta_state
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_state),
+    .io_in_11_bits_meta_clients
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_11_bits_meta_alias
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_11_bits_meta_prefetch
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_11_bits_meta_prefetchSrc
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_11_bits_meta_accessed
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_11_bits_meta_tagErr
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_11_bits_meta_dataErr
+      (_mshrs_11_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_11_bits_metaWen
+      (_mshrs_11_io_tasks_mainpipe_bits_metaWen),
+    .io_in_11_bits_tagWen
+      (_mshrs_11_io_tasks_mainpipe_bits_tagWen),
+    .io_in_11_bits_dsWen                         (_mshrs_11_io_tasks_mainpipe_bits_dsWen),
+    .io_in_11_bits_replTask
+      (_mshrs_11_io_tasks_mainpipe_bits_replTask),
+    .io_in_11_bits_cmoTask
+      (_mshrs_11_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_11_bits_reqSource
+      (_mshrs_11_io_tasks_mainpipe_bits_reqSource),
+    .io_in_11_bits_mergeA
+      (_mshrs_11_io_tasks_mainpipe_bits_mergeA),
+    .io_in_11_bits_aMergeTask_off
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_11_bits_aMergeTask_alias
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_11_bits_aMergeTask_vaddr
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_11_bits_aMergeTask_isKeyword
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_11_bits_aMergeTask_opcode
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_11_bits_aMergeTask_param
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_11_bits_aMergeTask_sourceId
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_11_bits_aMergeTask_meta_dirty
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_11_bits_aMergeTask_meta_state
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_11_bits_aMergeTask_meta_clients
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_11_bits_aMergeTask_meta_alias
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_11_bits_aMergeTask_meta_accessed
+      (_mshrs_11_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_11_bits_snpHitRelease
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_11_bits_snpHitReleaseToInval
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_11_bits_snpHitReleaseToClean
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_11_bits_snpHitReleaseWithData
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_11_bits_snpHitReleaseIdx
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_11_bits_snpHitReleaseMeta_dirty
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_11_bits_snpHitReleaseMeta_state
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_11_bits_snpHitReleaseMeta_clients
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_11_bits_snpHitReleaseMeta_alias
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_11_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_11_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_11_bits_snpHitReleaseMeta_accessed
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_11_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_11_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_11_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_11_bits_tgtID                         (_mshrs_11_io_tasks_mainpipe_bits_tgtID),
+    .io_in_11_bits_txnID                         (_mshrs_11_io_tasks_mainpipe_bits_txnID),
+    .io_in_11_bits_homeNID
+      (_mshrs_11_io_tasks_mainpipe_bits_homeNID),
+    .io_in_11_bits_dbID                          (_mshrs_11_io_tasks_mainpipe_bits_dbID),
+    .io_in_11_bits_chiOpcode
+      (_mshrs_11_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_11_bits_resp                          (_mshrs_11_io_tasks_mainpipe_bits_resp),
+    .io_in_11_bits_fwdState
+      (_mshrs_11_io_tasks_mainpipe_bits_fwdState),
+    .io_in_11_bits_retToSrc
+      (_mshrs_11_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_11_bits_likelyshared
+      (_mshrs_11_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_11_bits_expCompAck
+      (_mshrs_11_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_11_bits_allowRetry
+      (_mshrs_11_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_11_bits_memAttr_allocate
+      (_mshrs_11_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_11_bits_memAttr_cacheable
+      (_mshrs_11_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_11_bits_memAttr_ewa
+      (_mshrs_11_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_11_bits_traceTag
+      (_mshrs_11_io_tasks_mainpipe_bits_traceTag),
+    .io_in_12_ready                              (_mshr_task_arb_io_in_12_ready),
+    .io_in_12_valid                              (_mshrs_12_io_tasks_mainpipe_valid),
+    .io_in_12_bits_channel
+      (_mshrs_12_io_tasks_mainpipe_bits_channel),
+    .io_in_12_bits_txChannel
+      (_mshrs_12_io_tasks_mainpipe_bits_txChannel),
+    .io_in_12_bits_set                           (_mshrs_12_io_tasks_mainpipe_bits_set),
+    .io_in_12_bits_tag                           (_mshrs_12_io_tasks_mainpipe_bits_tag),
+    .io_in_12_bits_off                           (_mshrs_12_io_tasks_mainpipe_bits_off),
+    .io_in_12_bits_alias                         (_mshrs_12_io_tasks_mainpipe_bits_alias),
+    .io_in_12_bits_isKeyword
+      (_mshrs_12_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_12_bits_opcode
+      (_mshrs_12_io_tasks_mainpipe_bits_opcode),
+    .io_in_12_bits_param                         (_mshrs_12_io_tasks_mainpipe_bits_param),
+    .io_in_12_bits_size                          (_mshrs_12_io_tasks_mainpipe_bits_size),
+    .io_in_12_bits_sourceId
+      (_mshrs_12_io_tasks_mainpipe_bits_sourceId),
+    .io_in_12_bits_denied
+      (_mshrs_12_io_tasks_mainpipe_bits_denied),
+    .io_in_12_bits_corrupt
+      (_mshrs_12_io_tasks_mainpipe_bits_corrupt),
+    .io_in_12_bits_aliasTask
+      (_mshrs_12_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_12_bits_useProbeData
+      (_mshrs_12_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_12_bits_mshrRetry
+      (_mshrs_12_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_12_bits_readProbeDataDown
+      (_mshrs_12_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_12_bits_fromL2pft
+      (_mshrs_12_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_12_bits_dirty                         (_mshrs_12_io_tasks_mainpipe_bits_dirty),
+    .io_in_12_bits_way                           (_mshrs_12_io_tasks_mainpipe_bits_way),
+    .io_in_12_bits_meta_dirty
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_12_bits_meta_state
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_state),
+    .io_in_12_bits_meta_clients
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_12_bits_meta_alias
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_12_bits_meta_prefetch
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_12_bits_meta_prefetchSrc
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_12_bits_meta_accessed
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_12_bits_meta_tagErr
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_12_bits_meta_dataErr
+      (_mshrs_12_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_12_bits_metaWen
+      (_mshrs_12_io_tasks_mainpipe_bits_metaWen),
+    .io_in_12_bits_tagWen
+      (_mshrs_12_io_tasks_mainpipe_bits_tagWen),
+    .io_in_12_bits_dsWen                         (_mshrs_12_io_tasks_mainpipe_bits_dsWen),
+    .io_in_12_bits_replTask
+      (_mshrs_12_io_tasks_mainpipe_bits_replTask),
+    .io_in_12_bits_cmoTask
+      (_mshrs_12_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_12_bits_reqSource
+      (_mshrs_12_io_tasks_mainpipe_bits_reqSource),
+    .io_in_12_bits_mergeA
+      (_mshrs_12_io_tasks_mainpipe_bits_mergeA),
+    .io_in_12_bits_aMergeTask_off
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_12_bits_aMergeTask_alias
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_12_bits_aMergeTask_vaddr
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_12_bits_aMergeTask_isKeyword
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_12_bits_aMergeTask_opcode
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_12_bits_aMergeTask_param
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_12_bits_aMergeTask_sourceId
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_12_bits_aMergeTask_meta_dirty
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_12_bits_aMergeTask_meta_state
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_12_bits_aMergeTask_meta_clients
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_12_bits_aMergeTask_meta_alias
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_12_bits_aMergeTask_meta_accessed
+      (_mshrs_12_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_12_bits_snpHitRelease
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_12_bits_snpHitReleaseToInval
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_12_bits_snpHitReleaseToClean
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_12_bits_snpHitReleaseWithData
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_12_bits_snpHitReleaseIdx
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_12_bits_snpHitReleaseMeta_dirty
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_12_bits_snpHitReleaseMeta_state
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_12_bits_snpHitReleaseMeta_clients
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_12_bits_snpHitReleaseMeta_alias
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_12_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_12_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_12_bits_snpHitReleaseMeta_accessed
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_12_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_12_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_12_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_12_bits_tgtID                         (_mshrs_12_io_tasks_mainpipe_bits_tgtID),
+    .io_in_12_bits_txnID                         (_mshrs_12_io_tasks_mainpipe_bits_txnID),
+    .io_in_12_bits_homeNID
+      (_mshrs_12_io_tasks_mainpipe_bits_homeNID),
+    .io_in_12_bits_dbID                          (_mshrs_12_io_tasks_mainpipe_bits_dbID),
+    .io_in_12_bits_chiOpcode
+      (_mshrs_12_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_12_bits_resp                          (_mshrs_12_io_tasks_mainpipe_bits_resp),
+    .io_in_12_bits_fwdState
+      (_mshrs_12_io_tasks_mainpipe_bits_fwdState),
+    .io_in_12_bits_retToSrc
+      (_mshrs_12_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_12_bits_likelyshared
+      (_mshrs_12_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_12_bits_expCompAck
+      (_mshrs_12_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_12_bits_allowRetry
+      (_mshrs_12_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_12_bits_memAttr_allocate
+      (_mshrs_12_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_12_bits_memAttr_cacheable
+      (_mshrs_12_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_12_bits_memAttr_ewa
+      (_mshrs_12_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_12_bits_traceTag
+      (_mshrs_12_io_tasks_mainpipe_bits_traceTag),
+    .io_in_13_ready                              (_mshr_task_arb_io_in_13_ready),
+    .io_in_13_valid                              (_mshrs_13_io_tasks_mainpipe_valid),
+    .io_in_13_bits_channel
+      (_mshrs_13_io_tasks_mainpipe_bits_channel),
+    .io_in_13_bits_txChannel
+      (_mshrs_13_io_tasks_mainpipe_bits_txChannel),
+    .io_in_13_bits_set                           (_mshrs_13_io_tasks_mainpipe_bits_set),
+    .io_in_13_bits_tag                           (_mshrs_13_io_tasks_mainpipe_bits_tag),
+    .io_in_13_bits_off                           (_mshrs_13_io_tasks_mainpipe_bits_off),
+    .io_in_13_bits_alias                         (_mshrs_13_io_tasks_mainpipe_bits_alias),
+    .io_in_13_bits_isKeyword
+      (_mshrs_13_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_13_bits_opcode
+      (_mshrs_13_io_tasks_mainpipe_bits_opcode),
+    .io_in_13_bits_param                         (_mshrs_13_io_tasks_mainpipe_bits_param),
+    .io_in_13_bits_size                          (_mshrs_13_io_tasks_mainpipe_bits_size),
+    .io_in_13_bits_sourceId
+      (_mshrs_13_io_tasks_mainpipe_bits_sourceId),
+    .io_in_13_bits_denied
+      (_mshrs_13_io_tasks_mainpipe_bits_denied),
+    .io_in_13_bits_corrupt
+      (_mshrs_13_io_tasks_mainpipe_bits_corrupt),
+    .io_in_13_bits_aliasTask
+      (_mshrs_13_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_13_bits_useProbeData
+      (_mshrs_13_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_13_bits_mshrRetry
+      (_mshrs_13_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_13_bits_readProbeDataDown
+      (_mshrs_13_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_13_bits_fromL2pft
+      (_mshrs_13_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_13_bits_dirty                         (_mshrs_13_io_tasks_mainpipe_bits_dirty),
+    .io_in_13_bits_way                           (_mshrs_13_io_tasks_mainpipe_bits_way),
+    .io_in_13_bits_meta_dirty
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_13_bits_meta_state
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_state),
+    .io_in_13_bits_meta_clients
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_13_bits_meta_alias
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_13_bits_meta_prefetch
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_13_bits_meta_prefetchSrc
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_13_bits_meta_accessed
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_13_bits_meta_tagErr
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_13_bits_meta_dataErr
+      (_mshrs_13_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_13_bits_metaWen
+      (_mshrs_13_io_tasks_mainpipe_bits_metaWen),
+    .io_in_13_bits_tagWen
+      (_mshrs_13_io_tasks_mainpipe_bits_tagWen),
+    .io_in_13_bits_dsWen                         (_mshrs_13_io_tasks_mainpipe_bits_dsWen),
+    .io_in_13_bits_replTask
+      (_mshrs_13_io_tasks_mainpipe_bits_replTask),
+    .io_in_13_bits_cmoTask
+      (_mshrs_13_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_13_bits_reqSource
+      (_mshrs_13_io_tasks_mainpipe_bits_reqSource),
+    .io_in_13_bits_mergeA
+      (_mshrs_13_io_tasks_mainpipe_bits_mergeA),
+    .io_in_13_bits_aMergeTask_off
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_13_bits_aMergeTask_alias
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_13_bits_aMergeTask_vaddr
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_13_bits_aMergeTask_isKeyword
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_13_bits_aMergeTask_opcode
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_13_bits_aMergeTask_param
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_13_bits_aMergeTask_sourceId
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_13_bits_aMergeTask_meta_dirty
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_13_bits_aMergeTask_meta_state
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_13_bits_aMergeTask_meta_clients
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_13_bits_aMergeTask_meta_alias
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_13_bits_aMergeTask_meta_accessed
+      (_mshrs_13_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_13_bits_snpHitRelease
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_13_bits_snpHitReleaseToInval
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_13_bits_snpHitReleaseToClean
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_13_bits_snpHitReleaseWithData
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_13_bits_snpHitReleaseIdx
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_13_bits_snpHitReleaseMeta_dirty
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_13_bits_snpHitReleaseMeta_state
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_13_bits_snpHitReleaseMeta_clients
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_13_bits_snpHitReleaseMeta_alias
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_13_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_13_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_13_bits_snpHitReleaseMeta_accessed
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_13_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_13_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_13_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_13_bits_tgtID                         (_mshrs_13_io_tasks_mainpipe_bits_tgtID),
+    .io_in_13_bits_txnID                         (_mshrs_13_io_tasks_mainpipe_bits_txnID),
+    .io_in_13_bits_homeNID
+      (_mshrs_13_io_tasks_mainpipe_bits_homeNID),
+    .io_in_13_bits_dbID                          (_mshrs_13_io_tasks_mainpipe_bits_dbID),
+    .io_in_13_bits_chiOpcode
+      (_mshrs_13_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_13_bits_resp                          (_mshrs_13_io_tasks_mainpipe_bits_resp),
+    .io_in_13_bits_fwdState
+      (_mshrs_13_io_tasks_mainpipe_bits_fwdState),
+    .io_in_13_bits_retToSrc
+      (_mshrs_13_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_13_bits_likelyshared
+      (_mshrs_13_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_13_bits_expCompAck
+      (_mshrs_13_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_13_bits_allowRetry
+      (_mshrs_13_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_13_bits_memAttr_allocate
+      (_mshrs_13_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_13_bits_memAttr_cacheable
+      (_mshrs_13_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_13_bits_memAttr_ewa
+      (_mshrs_13_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_13_bits_traceTag
+      (_mshrs_13_io_tasks_mainpipe_bits_traceTag),
+    .io_in_14_ready                              (_mshr_task_arb_io_in_14_ready),
+    .io_in_14_valid                              (_mshrs_14_io_tasks_mainpipe_valid),
+    .io_in_14_bits_channel
+      (_mshrs_14_io_tasks_mainpipe_bits_channel),
+    .io_in_14_bits_txChannel
+      (_mshrs_14_io_tasks_mainpipe_bits_txChannel),
+    .io_in_14_bits_set                           (_mshrs_14_io_tasks_mainpipe_bits_set),
+    .io_in_14_bits_tag                           (_mshrs_14_io_tasks_mainpipe_bits_tag),
+    .io_in_14_bits_off                           (_mshrs_14_io_tasks_mainpipe_bits_off),
+    .io_in_14_bits_alias                         (_mshrs_14_io_tasks_mainpipe_bits_alias),
+    .io_in_14_bits_isKeyword
+      (_mshrs_14_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_14_bits_opcode
+      (_mshrs_14_io_tasks_mainpipe_bits_opcode),
+    .io_in_14_bits_param                         (_mshrs_14_io_tasks_mainpipe_bits_param),
+    .io_in_14_bits_size                          (_mshrs_14_io_tasks_mainpipe_bits_size),
+    .io_in_14_bits_sourceId
+      (_mshrs_14_io_tasks_mainpipe_bits_sourceId),
+    .io_in_14_bits_denied
+      (_mshrs_14_io_tasks_mainpipe_bits_denied),
+    .io_in_14_bits_corrupt
+      (_mshrs_14_io_tasks_mainpipe_bits_corrupt),
+    .io_in_14_bits_aliasTask
+      (_mshrs_14_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_14_bits_useProbeData
+      (_mshrs_14_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_14_bits_mshrRetry
+      (_mshrs_14_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_14_bits_readProbeDataDown
+      (_mshrs_14_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_14_bits_fromL2pft
+      (_mshrs_14_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_14_bits_dirty                         (_mshrs_14_io_tasks_mainpipe_bits_dirty),
+    .io_in_14_bits_way                           (_mshrs_14_io_tasks_mainpipe_bits_way),
+    .io_in_14_bits_meta_dirty
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_14_bits_meta_state
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_state),
+    .io_in_14_bits_meta_clients
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_14_bits_meta_alias
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_14_bits_meta_prefetch
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_14_bits_meta_prefetchSrc
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_14_bits_meta_accessed
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_14_bits_meta_tagErr
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_14_bits_meta_dataErr
+      (_mshrs_14_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_14_bits_metaWen
+      (_mshrs_14_io_tasks_mainpipe_bits_metaWen),
+    .io_in_14_bits_tagWen
+      (_mshrs_14_io_tasks_mainpipe_bits_tagWen),
+    .io_in_14_bits_dsWen                         (_mshrs_14_io_tasks_mainpipe_bits_dsWen),
+    .io_in_14_bits_replTask
+      (_mshrs_14_io_tasks_mainpipe_bits_replTask),
+    .io_in_14_bits_cmoTask
+      (_mshrs_14_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_14_bits_reqSource
+      (_mshrs_14_io_tasks_mainpipe_bits_reqSource),
+    .io_in_14_bits_mergeA
+      (_mshrs_14_io_tasks_mainpipe_bits_mergeA),
+    .io_in_14_bits_aMergeTask_off
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_14_bits_aMergeTask_alias
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_14_bits_aMergeTask_vaddr
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_14_bits_aMergeTask_isKeyword
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_14_bits_aMergeTask_opcode
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_14_bits_aMergeTask_param
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_14_bits_aMergeTask_sourceId
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_14_bits_aMergeTask_meta_dirty
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_14_bits_aMergeTask_meta_state
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_14_bits_aMergeTask_meta_clients
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_14_bits_aMergeTask_meta_alias
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_14_bits_aMergeTask_meta_accessed
+      (_mshrs_14_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_14_bits_snpHitRelease
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_14_bits_snpHitReleaseToInval
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_14_bits_snpHitReleaseToClean
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_14_bits_snpHitReleaseWithData
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_14_bits_snpHitReleaseIdx
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_14_bits_snpHitReleaseMeta_dirty
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_14_bits_snpHitReleaseMeta_state
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_14_bits_snpHitReleaseMeta_clients
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_14_bits_snpHitReleaseMeta_alias
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_14_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_14_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_14_bits_snpHitReleaseMeta_accessed
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_14_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_14_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_14_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_14_bits_tgtID                         (_mshrs_14_io_tasks_mainpipe_bits_tgtID),
+    .io_in_14_bits_txnID                         (_mshrs_14_io_tasks_mainpipe_bits_txnID),
+    .io_in_14_bits_homeNID
+      (_mshrs_14_io_tasks_mainpipe_bits_homeNID),
+    .io_in_14_bits_dbID                          (_mshrs_14_io_tasks_mainpipe_bits_dbID),
+    .io_in_14_bits_chiOpcode
+      (_mshrs_14_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_14_bits_resp                          (_mshrs_14_io_tasks_mainpipe_bits_resp),
+    .io_in_14_bits_fwdState
+      (_mshrs_14_io_tasks_mainpipe_bits_fwdState),
+    .io_in_14_bits_retToSrc
+      (_mshrs_14_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_14_bits_likelyshared
+      (_mshrs_14_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_14_bits_expCompAck
+      (_mshrs_14_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_14_bits_allowRetry
+      (_mshrs_14_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_14_bits_memAttr_allocate
+      (_mshrs_14_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_14_bits_memAttr_cacheable
+      (_mshrs_14_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_14_bits_memAttr_ewa
+      (_mshrs_14_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_14_bits_traceTag
+      (_mshrs_14_io_tasks_mainpipe_bits_traceTag),
+    .io_in_15_ready                              (_mshr_task_arb_io_in_15_ready),
+    .io_in_15_valid                              (_mshrs_15_io_tasks_mainpipe_valid),
+    .io_in_15_bits_channel
+      (_mshrs_15_io_tasks_mainpipe_bits_channel),
+    .io_in_15_bits_txChannel
+      (_mshrs_15_io_tasks_mainpipe_bits_txChannel),
+    .io_in_15_bits_set                           (_mshrs_15_io_tasks_mainpipe_bits_set),
+    .io_in_15_bits_tag                           (_mshrs_15_io_tasks_mainpipe_bits_tag),
+    .io_in_15_bits_off                           (_mshrs_15_io_tasks_mainpipe_bits_off),
+    .io_in_15_bits_alias                         (_mshrs_15_io_tasks_mainpipe_bits_alias),
+    .io_in_15_bits_isKeyword
+      (_mshrs_15_io_tasks_mainpipe_bits_isKeyword),
+    .io_in_15_bits_opcode
+      (_mshrs_15_io_tasks_mainpipe_bits_opcode),
+    .io_in_15_bits_param                         (_mshrs_15_io_tasks_mainpipe_bits_param),
+    .io_in_15_bits_size                          (_mshrs_15_io_tasks_mainpipe_bits_size),
+    .io_in_15_bits_sourceId
+      (_mshrs_15_io_tasks_mainpipe_bits_sourceId),
+    .io_in_15_bits_denied
+      (_mshrs_15_io_tasks_mainpipe_bits_denied),
+    .io_in_15_bits_corrupt
+      (_mshrs_15_io_tasks_mainpipe_bits_corrupt),
+    .io_in_15_bits_aliasTask
+      (_mshrs_15_io_tasks_mainpipe_bits_aliasTask),
+    .io_in_15_bits_useProbeData
+      (_mshrs_15_io_tasks_mainpipe_bits_useProbeData),
+    .io_in_15_bits_mshrRetry
+      (_mshrs_15_io_tasks_mainpipe_bits_mshrRetry),
+    .io_in_15_bits_readProbeDataDown
+      (_mshrs_15_io_tasks_mainpipe_bits_readProbeDataDown),
+    .io_in_15_bits_fromL2pft
+      (_mshrs_15_io_tasks_mainpipe_bits_fromL2pft),
+    .io_in_15_bits_dirty                         (_mshrs_15_io_tasks_mainpipe_bits_dirty),
+    .io_in_15_bits_way                           (_mshrs_15_io_tasks_mainpipe_bits_way),
+    .io_in_15_bits_meta_dirty
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_dirty),
+    .io_in_15_bits_meta_state
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_state),
+    .io_in_15_bits_meta_clients
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_clients),
+    .io_in_15_bits_meta_alias
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_alias),
+    .io_in_15_bits_meta_prefetch
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_prefetch),
+    .io_in_15_bits_meta_prefetchSrc
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_prefetchSrc),
+    .io_in_15_bits_meta_accessed
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_accessed),
+    .io_in_15_bits_meta_tagErr
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_tagErr),
+    .io_in_15_bits_meta_dataErr
+      (_mshrs_15_io_tasks_mainpipe_bits_meta_dataErr),
+    .io_in_15_bits_metaWen
+      (_mshrs_15_io_tasks_mainpipe_bits_metaWen),
+    .io_in_15_bits_tagWen
+      (_mshrs_15_io_tasks_mainpipe_bits_tagWen),
+    .io_in_15_bits_dsWen                         (_mshrs_15_io_tasks_mainpipe_bits_dsWen),
+    .io_in_15_bits_replTask
+      (_mshrs_15_io_tasks_mainpipe_bits_replTask),
+    .io_in_15_bits_cmoTask
+      (_mshrs_15_io_tasks_mainpipe_bits_cmoTask),
+    .io_in_15_bits_reqSource
+      (_mshrs_15_io_tasks_mainpipe_bits_reqSource),
+    .io_in_15_bits_mergeA
+      (_mshrs_15_io_tasks_mainpipe_bits_mergeA),
+    .io_in_15_bits_aMergeTask_off
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_off),
+    .io_in_15_bits_aMergeTask_alias
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_alias),
+    .io_in_15_bits_aMergeTask_vaddr
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_vaddr),
+    .io_in_15_bits_aMergeTask_isKeyword
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_isKeyword),
+    .io_in_15_bits_aMergeTask_opcode
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_opcode),
+    .io_in_15_bits_aMergeTask_param
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_param),
+    .io_in_15_bits_aMergeTask_sourceId
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_sourceId),
+    .io_in_15_bits_aMergeTask_meta_dirty
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_dirty),
+    .io_in_15_bits_aMergeTask_meta_state
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_state),
+    .io_in_15_bits_aMergeTask_meta_clients
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_clients),
+    .io_in_15_bits_aMergeTask_meta_alias
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_alias),
+    .io_in_15_bits_aMergeTask_meta_accessed
+      (_mshrs_15_io_tasks_mainpipe_bits_aMergeTask_meta_accessed),
+    .io_in_15_bits_snpHitRelease
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitRelease),
+    .io_in_15_bits_snpHitReleaseToInval
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseToInval),
+    .io_in_15_bits_snpHitReleaseToClean
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseToClean),
+    .io_in_15_bits_snpHitReleaseWithData
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseWithData),
+    .io_in_15_bits_snpHitReleaseIdx
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseIdx),
+    .io_in_15_bits_snpHitReleaseMeta_dirty
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_dirty),
+    .io_in_15_bits_snpHitReleaseMeta_state
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_state),
+    .io_in_15_bits_snpHitReleaseMeta_clients
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_clients),
+    .io_in_15_bits_snpHitReleaseMeta_alias
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_alias),
+    .io_in_15_bits_snpHitReleaseMeta_prefetch
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetch),
+    .io_in_15_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_15_bits_snpHitReleaseMeta_accessed
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_accessed),
+    .io_in_15_bits_snpHitReleaseMeta_tagErr
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_tagErr),
+    .io_in_15_bits_snpHitReleaseMeta_dataErr
+      (_mshrs_15_io_tasks_mainpipe_bits_snpHitReleaseMeta_dataErr),
+    .io_in_15_bits_tgtID                         (_mshrs_15_io_tasks_mainpipe_bits_tgtID),
+    .io_in_15_bits_txnID                         (_mshrs_15_io_tasks_mainpipe_bits_txnID),
+    .io_in_15_bits_homeNID
+      (_mshrs_15_io_tasks_mainpipe_bits_homeNID),
+    .io_in_15_bits_dbID                          (_mshrs_15_io_tasks_mainpipe_bits_dbID),
+    .io_in_15_bits_chiOpcode
+      (_mshrs_15_io_tasks_mainpipe_bits_chiOpcode),
+    .io_in_15_bits_resp                          (_mshrs_15_io_tasks_mainpipe_bits_resp),
+    .io_in_15_bits_fwdState
+      (_mshrs_15_io_tasks_mainpipe_bits_fwdState),
+    .io_in_15_bits_retToSrc
+      (_mshrs_15_io_tasks_mainpipe_bits_retToSrc),
+    .io_in_15_bits_likelyshared
+      (_mshrs_15_io_tasks_mainpipe_bits_likelyshared),
+    .io_in_15_bits_expCompAck
+      (_mshrs_15_io_tasks_mainpipe_bits_expCompAck),
+    .io_in_15_bits_allowRetry
+      (_mshrs_15_io_tasks_mainpipe_bits_allowRetry),
+    .io_in_15_bits_memAttr_allocate
+      (_mshrs_15_io_tasks_mainpipe_bits_memAttr_allocate),
+    .io_in_15_bits_memAttr_cacheable
+      (_mshrs_15_io_tasks_mainpipe_bits_memAttr_cacheable),
+    .io_in_15_bits_memAttr_ewa
+      (_mshrs_15_io_tasks_mainpipe_bits_memAttr_ewa),
+    .io_in_15_bits_traceTag
+      (_mshrs_15_io_tasks_mainpipe_bits_traceTag),
+    .io_out_ready                                (io_mshrTask_ready),
+    .io_out_valid                                (io_mshrTask_valid),
+    .io_out_bits_channel                         (io_mshrTask_bits_channel),
+    .io_out_bits_txChannel                       (io_mshrTask_bits_txChannel),
+    .io_out_bits_set                             (io_mshrTask_bits_set),
+    .io_out_bits_tag                             (io_mshrTask_bits_tag),
+    .io_out_bits_off                             (io_mshrTask_bits_off),
+    .io_out_bits_alias                           (io_mshrTask_bits_alias),
+    .io_out_bits_isKeyword                       (io_mshrTask_bits_isKeyword),
+    .io_out_bits_opcode                          (io_mshrTask_bits_opcode),
+    .io_out_bits_param                           (io_mshrTask_bits_param),
+    .io_out_bits_size                            (io_mshrTask_bits_size),
+    .io_out_bits_sourceId                        (io_mshrTask_bits_sourceId),
+    .io_out_bits_denied                          (io_mshrTask_bits_denied),
+    .io_out_bits_corrupt                         (io_mshrTask_bits_corrupt),
+    .io_out_bits_mshrTask                        (io_mshrTask_bits_mshrTask),
+    .io_out_bits_aliasTask                       (io_mshrTask_bits_aliasTask),
+    .io_out_bits_useProbeData                    (io_mshrTask_bits_useProbeData),
+    .io_out_bits_mshrRetry                       (io_mshrTask_bits_mshrRetry),
+    .io_out_bits_readProbeDataDown               (io_mshrTask_bits_readProbeDataDown),
+    .io_out_bits_fromL2pft                       (io_mshrTask_bits_fromL2pft),
+    .io_out_bits_dirty                           (io_mshrTask_bits_dirty),
+    .io_out_bits_way                             (io_mshrTask_bits_way),
+    .io_out_bits_meta_dirty                      (io_mshrTask_bits_meta_dirty),
+    .io_out_bits_meta_state                      (io_mshrTask_bits_meta_state),
+    .io_out_bits_meta_clients                    (io_mshrTask_bits_meta_clients),
+    .io_out_bits_meta_alias                      (io_mshrTask_bits_meta_alias),
+    .io_out_bits_meta_prefetch                   (io_mshrTask_bits_meta_prefetch),
+    .io_out_bits_meta_prefetchSrc                (io_mshrTask_bits_meta_prefetchSrc),
+    .io_out_bits_meta_accessed                   (io_mshrTask_bits_meta_accessed),
+    .io_out_bits_meta_tagErr                     (io_mshrTask_bits_meta_tagErr),
+    .io_out_bits_meta_dataErr                    (io_mshrTask_bits_meta_dataErr),
+    .io_out_bits_metaWen                         (io_mshrTask_bits_metaWen),
+    .io_out_bits_tagWen                          (io_mshrTask_bits_tagWen),
+    .io_out_bits_dsWen                           (io_mshrTask_bits_dsWen),
+    .io_out_bits_replTask                        (io_mshrTask_bits_replTask),
+    .io_out_bits_cmoTask                         (io_mshrTask_bits_cmoTask),
+    .io_out_bits_reqSource                       (io_mshrTask_bits_reqSource),
+    .io_out_bits_mergeA                          (io_mshrTask_bits_mergeA),
+    .io_out_bits_aMergeTask_off                  (io_mshrTask_bits_aMergeTask_off),
+    .io_out_bits_aMergeTask_alias                (io_mshrTask_bits_aMergeTask_alias),
+    .io_out_bits_aMergeTask_vaddr                (io_mshrTask_bits_aMergeTask_vaddr),
+    .io_out_bits_aMergeTask_isKeyword            (io_mshrTask_bits_aMergeTask_isKeyword),
+    .io_out_bits_aMergeTask_opcode               (io_mshrTask_bits_aMergeTask_opcode),
+    .io_out_bits_aMergeTask_param                (io_mshrTask_bits_aMergeTask_param),
+    .io_out_bits_aMergeTask_sourceId             (io_mshrTask_bits_aMergeTask_sourceId),
+    .io_out_bits_aMergeTask_meta_dirty           (io_mshrTask_bits_aMergeTask_meta_dirty),
+    .io_out_bits_aMergeTask_meta_state           (io_mshrTask_bits_aMergeTask_meta_state),
+    .io_out_bits_aMergeTask_meta_clients
+      (io_mshrTask_bits_aMergeTask_meta_clients),
+    .io_out_bits_aMergeTask_meta_alias           (io_mshrTask_bits_aMergeTask_meta_alias),
+    .io_out_bits_aMergeTask_meta_accessed
+      (io_mshrTask_bits_aMergeTask_meta_accessed),
+    .io_out_bits_snpHitRelease                   (io_mshrTask_bits_snpHitRelease),
+    .io_out_bits_snpHitReleaseToInval            (io_mshrTask_bits_snpHitReleaseToInval),
+    .io_out_bits_snpHitReleaseToClean            (io_mshrTask_bits_snpHitReleaseToClean),
+    .io_out_bits_snpHitReleaseWithData           (io_mshrTask_bits_snpHitReleaseWithData),
+    .io_out_bits_snpHitReleaseIdx                (io_mshrTask_bits_snpHitReleaseIdx),
+    .io_out_bits_snpHitReleaseMeta_dirty
+      (io_mshrTask_bits_snpHitReleaseMeta_dirty),
+    .io_out_bits_snpHitReleaseMeta_state
+      (io_mshrTask_bits_snpHitReleaseMeta_state),
+    .io_out_bits_snpHitReleaseMeta_clients
+      (io_mshrTask_bits_snpHitReleaseMeta_clients),
+    .io_out_bits_snpHitReleaseMeta_alias
+      (io_mshrTask_bits_snpHitReleaseMeta_alias),
+    .io_out_bits_snpHitReleaseMeta_prefetch
+      (io_mshrTask_bits_snpHitReleaseMeta_prefetch),
+    .io_out_bits_snpHitReleaseMeta_prefetchSrc
+      (io_mshrTask_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_out_bits_snpHitReleaseMeta_accessed
+      (io_mshrTask_bits_snpHitReleaseMeta_accessed),
+    .io_out_bits_snpHitReleaseMeta_tagErr
+      (io_mshrTask_bits_snpHitReleaseMeta_tagErr),
+    .io_out_bits_snpHitReleaseMeta_dataErr
+      (io_mshrTask_bits_snpHitReleaseMeta_dataErr),
+    .io_out_bits_tgtID                           (io_mshrTask_bits_tgtID),
+    .io_out_bits_txnID                           (io_mshrTask_bits_txnID),
+    .io_out_bits_homeNID                         (io_mshrTask_bits_homeNID),
+    .io_out_bits_dbID                            (io_mshrTask_bits_dbID),
+    .io_out_bits_chiOpcode                       (io_mshrTask_bits_chiOpcode),
+    .io_out_bits_resp                            (io_mshrTask_bits_resp),
+    .io_out_bits_fwdState                        (io_mshrTask_bits_fwdState),
+    .io_out_bits_retToSrc                        (io_mshrTask_bits_retToSrc),
+    .io_out_bits_likelyshared                    (io_mshrTask_bits_likelyshared),
+    .io_out_bits_expCompAck                      (io_mshrTask_bits_expCompAck),
+    .io_out_bits_allowRetry                      (io_mshrTask_bits_allowRetry),
+    .io_out_bits_memAttr_allocate                (io_mshrTask_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable               (io_mshrTask_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_ewa                     (io_mshrTask_bits_memAttr_ewa),
+    .io_out_bits_traceTag                        (io_mshrTask_bits_traceTag),
+    .io_chosen                                   (_mshr_task_arb_io_chosen)
+  );
+  assign io_toReqArb_blockA_s1 = _a_mshrFull_T > 5'hE;
+  assign io_toReqArb_blockB_s1 = _a_mshrFull_T[4];
+  assign io_toMainPipe_mshr_alloc_ptr =
+    {4'h0,
+     |(_mshrSelector_io_out_bits[15:8]),
+     |(_io_toMainPipe_mshr_alloc_ptr_T_1[6:3]),
+     |(_io_toMainPipe_mshr_alloc_ptr_T_3[2:1]),
+     _io_toMainPipe_mshr_alloc_ptr_T_3[2] | _io_toMainPipe_mshr_alloc_ptr_T_3[0]};
+  assign io_mshrTask_bits_mshrId = {4'h0, _mshr_task_arb_io_chosen};
+  assign io_releaseBufWriteId =
+    {4'h0,
+     _io_releaseBufWriteId_T_4 | _io_releaseBufWriteId_T_6 | resp_sinkC_match_vec_6
+     | resp_sinkC_match_vec_7
+       ? {1'h0,
+          _io_releaseBufWriteId_T_4
+            ? {1'h0,
+               _io_releaseBufWriteId_T
+                 ? {1'h0, ~resp_sinkC_match_vec_0}
+                 : {1'h1, ~resp_sinkC_match_vec_2}}
+            : _io_releaseBufWriteId_T_6
+                ? {2'h2, ~resp_sinkC_match_vec_4}
+                : {2'h3, ~resp_sinkC_match_vec_6}}
+       : _io_releaseBufWriteId_T_14 | resp_sinkC_match_vec_10 | resp_sinkC_match_vec_11
+           ? (_io_releaseBufWriteId_T_14
+                ? {3'h4, ~resp_sinkC_match_vec_8}
+                : {3'h5, ~resp_sinkC_match_vec_10})
+           : resp_sinkC_match_vec_12 | resp_sinkC_match_vec_13
+               ? {3'h6, ~resp_sinkC_match_vec_12}
+               : {3'h7, ~resp_sinkC_match_vec_14}};
+  assign io_nestedwbDataId_valid =
+    |{_mshrs_0_io_nestedwbData,
+      _mshrs_1_io_nestedwbData,
+      _mshrs_2_io_nestedwbData,
+      _mshrs_3_io_nestedwbData,
+      _mshrs_4_io_nestedwbData,
+      _mshrs_5_io_nestedwbData,
+      _mshrs_6_io_nestedwbData,
+      _mshrs_7_io_nestedwbData,
+      _mshrs_8_io_nestedwbData,
+      _mshrs_9_io_nestedwbData,
+      _mshrs_10_io_nestedwbData,
+      _mshrs_11_io_nestedwbData,
+      _mshrs_12_io_nestedwbData,
+      _mshrs_13_io_nestedwbData,
+      _mshrs_14_io_nestedwbData,
+      _mshrs_15_io_nestedwbData};
+  assign io_nestedwbDataId_bits =
+    {4'h0,
+     _io_nestedwbDataId_bits_T_4 | _io_nestedwbDataId_bits_T_6 | _mshrs_6_io_nestedwbData
+     | _mshrs_7_io_nestedwbData
+       ? {1'h0,
+          _io_nestedwbDataId_bits_T_4
+            ? {1'h0,
+               _io_nestedwbDataId_bits_T
+                 ? {1'h0, ~_mshrs_0_io_nestedwbData}
+                 : {1'h1, ~_mshrs_2_io_nestedwbData}}
+            : _io_nestedwbDataId_bits_T_6
+                ? {2'h2, ~_mshrs_4_io_nestedwbData}
+                : {2'h3, ~_mshrs_6_io_nestedwbData}}
+       : _io_nestedwbDataId_bits_T_14 | _mshrs_10_io_nestedwbData
+         | _mshrs_11_io_nestedwbData
+           ? (_io_nestedwbDataId_bits_T_14
+                ? {3'h4, ~_mshrs_8_io_nestedwbData}
+                : {3'h5, ~_mshrs_10_io_nestedwbData})
+           : _mshrs_12_io_nestedwbData | _mshrs_13_io_nestedwbData
+               ? {3'h6, ~_mshrs_12_io_nestedwbData}
+               : {3'h7, ~_mshrs_14_io_nestedwbData}};
+  assign io_l2Miss =
+    |{_mshrs_0_io_status_valid & _mshrs_0_io_status_bits_channel[0]
+        & (_mshrs_0_io_status_bits_reqSource == 5'h2
+           | _mshrs_0_io_status_bits_reqSource == 5'h3),
+      _mshrs_1_io_status_valid & _mshrs_1_io_status_bits_channel[0]
+        & (_mshrs_1_io_status_bits_reqSource == 5'h2
+           | _mshrs_1_io_status_bits_reqSource == 5'h3),
+      _mshrs_2_io_status_valid & _mshrs_2_io_status_bits_channel[0]
+        & (_mshrs_2_io_status_bits_reqSource == 5'h2
+           | _mshrs_2_io_status_bits_reqSource == 5'h3),
+      _mshrs_3_io_status_valid & _mshrs_3_io_status_bits_channel[0]
+        & (_mshrs_3_io_status_bits_reqSource == 5'h2
+           | _mshrs_3_io_status_bits_reqSource == 5'h3),
+      _mshrs_4_io_status_valid & _mshrs_4_io_status_bits_channel[0]
+        & (_mshrs_4_io_status_bits_reqSource == 5'h2
+           | _mshrs_4_io_status_bits_reqSource == 5'h3),
+      _mshrs_5_io_status_valid & _mshrs_5_io_status_bits_channel[0]
+        & (_mshrs_5_io_status_bits_reqSource == 5'h2
+           | _mshrs_5_io_status_bits_reqSource == 5'h3),
+      _mshrs_6_io_status_valid & _mshrs_6_io_status_bits_channel[0]
+        & (_mshrs_6_io_status_bits_reqSource == 5'h2
+           | _mshrs_6_io_status_bits_reqSource == 5'h3),
+      _mshrs_7_io_status_valid & _mshrs_7_io_status_bits_channel[0]
+        & (_mshrs_7_io_status_bits_reqSource == 5'h2
+           | _mshrs_7_io_status_bits_reqSource == 5'h3),
+      _mshrs_8_io_status_valid & _mshrs_8_io_status_bits_channel[0]
+        & (_mshrs_8_io_status_bits_reqSource == 5'h2
+           | _mshrs_8_io_status_bits_reqSource == 5'h3),
+      _mshrs_9_io_status_valid & _mshrs_9_io_status_bits_channel[0]
+        & (_mshrs_9_io_status_bits_reqSource == 5'h2
+           | _mshrs_9_io_status_bits_reqSource == 5'h3),
+      _mshrs_10_io_status_valid & _mshrs_10_io_status_bits_channel[0]
+        & (_mshrs_10_io_status_bits_reqSource == 5'h2
+           | _mshrs_10_io_status_bits_reqSource == 5'h3),
+      _mshrs_11_io_status_valid & _mshrs_11_io_status_bits_channel[0]
+        & (_mshrs_11_io_status_bits_reqSource == 5'h2
+           | _mshrs_11_io_status_bits_reqSource == 5'h3),
+      _mshrs_12_io_status_valid & _mshrs_12_io_status_bits_channel[0]
+        & (_mshrs_12_io_status_bits_reqSource == 5'h2
+           | _mshrs_12_io_status_bits_reqSource == 5'h3),
+      _mshrs_13_io_status_valid & _mshrs_13_io_status_bits_channel[0]
+        & (_mshrs_13_io_status_bits_reqSource == 5'h2
+           | _mshrs_13_io_status_bits_reqSource == 5'h3),
+      _mshrs_14_io_status_valid & _mshrs_14_io_status_bits_channel[0]
+        & (_mshrs_14_io_status_bits_reqSource == 5'h2
+           | _mshrs_14_io_status_bits_reqSource == 5'h3),
+      _mshrs_15_io_status_valid & _mshrs_15_io_status_bits_channel[0]
+        & (_mshrs_15_io_status_bits_reqSource == 5'h2
+           | _mshrs_15_io_status_bits_reqSource == 5'h3)};
+  assign io_perf_0_value = {5'h0, io_perf_0_value_REG_1};
+  assign io_perf_1_value = {5'h0, io_perf_1_value_REG_1};
+  assign io_perf_3_value = {2'h0, io_perf_3_value_REG_1};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MSHRSelector.sv b/flow/designs/src/xiangshan_coupledl2/deps/MSHRSelector.sv
new file mode 100644
index 0000000000..97432c9d89
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MSHRSelector.sv
@@ -0,0 +1,39 @@
+// Generated by CIRCT firtool-1.135.0
+module MSHRSelector(
+  input         io_idle_0,
+  input         io_idle_1,
+  input         io_idle_2,
+  input         io_idle_3,
+  input         io_idle_4,
+  input         io_idle_5,
+  input         io_idle_6,
+  input         io_idle_7,
+  input         io_idle_8,
+  input         io_idle_9,
+  input         io_idle_10,
+  input         io_idle_11,
+  input         io_idle_12,
+  input         io_idle_13,
+  input         io_idle_14,
+  output [15:0] io_out_bits
+);
+
+  wire _io_out_bits_T_16 = io_idle_0 | io_idle_1;
+  wire _io_out_bits_T_22 = io_idle_4 | io_idle_5;
+  wire _io_out_bits_T_30 = io_idle_8 | io_idle_9;
+  wire _io_out_bits_T_20 = _io_out_bits_T_16 | io_idle_2 | io_idle_3;
+  assign io_out_bits =
+    _io_out_bits_T_20 | _io_out_bits_T_22 | io_idle_6 | io_idle_7
+      ? (_io_out_bits_T_20
+           ? (_io_out_bits_T_16 ? (io_idle_0 ? 16'h1 : 16'h2) : io_idle_2 ? 16'h4 : 16'h8)
+           : _io_out_bits_T_22
+               ? (io_idle_4 ? 16'h10 : 16'h20)
+               : io_idle_6 ? 16'h40 : 16'h80)
+      : _io_out_bits_T_30 | io_idle_10 | io_idle_11
+          ? (_io_out_bits_T_30
+               ? (io_idle_8 ? 16'h100 : 16'h200)
+               : io_idle_10 ? 16'h400 : 16'h800)
+          : io_idle_12 | io_idle_13
+              ? (io_idle_12 ? 16'h1000 : 16'h2000)
+              : io_idle_14 ? 16'h4000 : 16'h8000;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MainPipe_1.sv b/flow/designs/src/xiangshan_coupledl2/deps/MainPipe_1.sv
new file mode 100644
index 0000000000..4c1b0af278
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MainPipe_1.sv
@@ -0,0 +1,4148 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MainPipe_1(
+  input          clock,
+  input          reset,
+  input          io_taskFromArb_s2_valid,
+  input  [2:0]   io_taskFromArb_s2_bits_channel,
+  input  [2:0]   io_taskFromArb_s2_bits_txChannel,
+  input  [7:0]   io_taskFromArb_s2_bits_set,
+  input  [33:0]  io_taskFromArb_s2_bits_tag,
+  input  [5:0]   io_taskFromArb_s2_bits_off,
+  input          io_taskFromArb_s2_bits_alias,
+  input  [43:0]  io_taskFromArb_s2_bits_vaddr,
+  input          io_taskFromArb_s2_bits_isKeyword,
+  input  [3:0]   io_taskFromArb_s2_bits_opcode,
+  input  [2:0]   io_taskFromArb_s2_bits_param,
+  input  [2:0]   io_taskFromArb_s2_bits_size,
+  input  [6:0]   io_taskFromArb_s2_bits_sourceId,
+  input  [1:0]   io_taskFromArb_s2_bits_bufIdx,
+  input          io_taskFromArb_s2_bits_needProbeAckData,
+  input          io_taskFromArb_s2_bits_denied,
+  input          io_taskFromArb_s2_bits_corrupt,
+  input          io_taskFromArb_s2_bits_mshrTask,
+  input  [7:0]   io_taskFromArb_s2_bits_mshrId,
+  input          io_taskFromArb_s2_bits_aliasTask,
+  input          io_taskFromArb_s2_bits_useProbeData,
+  input          io_taskFromArb_s2_bits_mshrRetry,
+  input          io_taskFromArb_s2_bits_readProbeDataDown,
+  input          io_taskFromArb_s2_bits_fromL2pft,
+  input          io_taskFromArb_s2_bits_needHint,
+  input          io_taskFromArb_s2_bits_dirty,
+  input  [2:0]   io_taskFromArb_s2_bits_way,
+  input          io_taskFromArb_s2_bits_meta_dirty,
+  input  [1:0]   io_taskFromArb_s2_bits_meta_state,
+  input          io_taskFromArb_s2_bits_meta_clients,
+  input          io_taskFromArb_s2_bits_meta_alias,
+  input          io_taskFromArb_s2_bits_meta_prefetch,
+  input  [3:0]   io_taskFromArb_s2_bits_meta_prefetchSrc,
+  input          io_taskFromArb_s2_bits_meta_accessed,
+  input          io_taskFromArb_s2_bits_meta_tagErr,
+  input          io_taskFromArb_s2_bits_meta_dataErr,
+  input          io_taskFromArb_s2_bits_metaWen,
+  input          io_taskFromArb_s2_bits_tagWen,
+  input          io_taskFromArb_s2_bits_dsWen,
+  input  [7:0]   io_taskFromArb_s2_bits_wayMask,
+  input          io_taskFromArb_s2_bits_replTask,
+  input          io_taskFromArb_s2_bits_cmoTask,
+  input          io_taskFromArb_s2_bits_cmoAll,
+  input  [4:0]   io_taskFromArb_s2_bits_reqSource,
+  input          io_taskFromArb_s2_bits_mergeA,
+  input  [5:0]   io_taskFromArb_s2_bits_aMergeTask_off,
+  input          io_taskFromArb_s2_bits_aMergeTask_alias,
+  input  [43:0]  io_taskFromArb_s2_bits_aMergeTask_vaddr,
+  input          io_taskFromArb_s2_bits_aMergeTask_isKeyword,
+  input  [2:0]   io_taskFromArb_s2_bits_aMergeTask_opcode,
+  input  [2:0]   io_taskFromArb_s2_bits_aMergeTask_param,
+  input  [6:0]   io_taskFromArb_s2_bits_aMergeTask_sourceId,
+  input          io_taskFromArb_s2_bits_aMergeTask_meta_dirty,
+  input  [1:0]   io_taskFromArb_s2_bits_aMergeTask_meta_state,
+  input          io_taskFromArb_s2_bits_aMergeTask_meta_clients,
+  input          io_taskFromArb_s2_bits_aMergeTask_meta_alias,
+  input          io_taskFromArb_s2_bits_aMergeTask_meta_prefetch,
+  input  [3:0]   io_taskFromArb_s2_bits_aMergeTask_meta_prefetchSrc,
+  input          io_taskFromArb_s2_bits_aMergeTask_meta_accessed,
+  input          io_taskFromArb_s2_bits_aMergeTask_meta_tagErr,
+  input          io_taskFromArb_s2_bits_aMergeTask_meta_dataErr,
+  input          io_taskFromArb_s2_bits_snpHitRelease,
+  input          io_taskFromArb_s2_bits_snpHitReleaseToInval,
+  input          io_taskFromArb_s2_bits_snpHitReleaseToClean,
+  input          io_taskFromArb_s2_bits_snpHitReleaseWithData,
+  input  [7:0]   io_taskFromArb_s2_bits_snpHitReleaseIdx,
+  input          io_taskFromArb_s2_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]   io_taskFromArb_s2_bits_snpHitReleaseMeta_state,
+  input          io_taskFromArb_s2_bits_snpHitReleaseMeta_clients,
+  input          io_taskFromArb_s2_bits_snpHitReleaseMeta_alias,
+  input          io_taskFromArb_s2_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]   io_taskFromArb_s2_bits_snpHitReleaseMeta_prefetchSrc,
+  input          io_taskFromArb_s2_bits_snpHitReleaseMeta_accessed,
+  input          io_taskFromArb_s2_bits_snpHitReleaseMeta_tagErr,
+  input          io_taskFromArb_s2_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0]  io_taskFromArb_s2_bits_tgtID,
+  input  [10:0]  io_taskFromArb_s2_bits_srcID,
+  input  [11:0]  io_taskFromArb_s2_bits_txnID,
+  input  [10:0]  io_taskFromArb_s2_bits_homeNID,
+  input  [11:0]  io_taskFromArb_s2_bits_dbID,
+  input  [10:0]  io_taskFromArb_s2_bits_fwdNID,
+  input  [11:0]  io_taskFromArb_s2_bits_fwdTxnID,
+  input  [6:0]   io_taskFromArb_s2_bits_chiOpcode,
+  input  [2:0]   io_taskFromArb_s2_bits_resp,
+  input  [2:0]   io_taskFromArb_s2_bits_fwdState,
+  input  [3:0]   io_taskFromArb_s2_bits_pCrdType,
+  input          io_taskFromArb_s2_bits_retToSrc,
+  input          io_taskFromArb_s2_bits_likelyshared,
+  input          io_taskFromArb_s2_bits_expCompAck,
+  input          io_taskFromArb_s2_bits_allowRetry,
+  input          io_taskFromArb_s2_bits_memAttr_allocate,
+  input          io_taskFromArb_s2_bits_memAttr_cacheable,
+  input          io_taskFromArb_s2_bits_memAttr_device,
+  input          io_taskFromArb_s2_bits_memAttr_ewa,
+  input          io_taskFromArb_s2_bits_traceTag,
+  input          io_mshrHintQInfo_valid,
+  input  [2:0]   io_mshrHintQInfo_bits_channel,
+  input          io_mshrHintQInfo_bits_isKeyword,
+  input  [3:0]   io_mshrHintQInfo_bits_opcode,
+  input  [6:0]   io_mshrHintQInfo_bits_sourceId,
+  input          io_mshrHintQInfo_bits_mergeA,
+  input          io_mshrHintQInfo_bits_aMergeTask_isKeyword,
+  input  [2:0]   io_mshrHintQInfo_bits_aMergeTask_opcode,
+  input  [6:0]   io_mshrHintQInfo_bits_aMergeTask_sourceId,
+  input          io_sinkCHintQInfo_valid,
+  input  [6:0]   io_sinkCHintQInfo_bits_sourceId,
+  input  [33:0]  io_fromReqArb_status_s1_tags_1,
+  input  [7:0]   io_fromReqArb_status_s1_sets_0,
+  input  [7:0]   io_fromReqArb_status_s1_sets_1,
+  input  [7:0]   io_fromReqArb_status_s1_sets_2,
+  input  [7:0]   io_fromReqArb_status_s1_sets_3,
+  output         io_toReqArb_blockG_s1,
+  output         io_toReqArb_blockB_s1,
+  output         io_toReqArb_blockC_s1,
+  output         io_toReqBuf_0,
+  output         io_toReqBuf_1,
+  output         io_status_vec_toD_0_valid,
+  output [2:0]   io_status_vec_toD_0_bits_channel,
+  output         io_status_vec_toD_1_valid,
+  output [2:0]   io_status_vec_toD_1_bits_channel,
+  output         io_status_vec_toD_2_valid,
+  output [2:0]   io_status_vec_toD_2_bits_channel,
+  output         io_status_vec_toTX_0_valid,
+  output [2:0]   io_status_vec_toTX_0_bits_channel,
+  output [2:0]   io_status_vec_toTX_0_bits_txChannel,
+  output         io_status_vec_toTX_0_bits_mshrTask,
+  output         io_status_vec_toTX_1_valid,
+  output [2:0]   io_status_vec_toTX_1_bits_channel,
+  output [2:0]   io_status_vec_toTX_1_bits_txChannel,
+  output         io_status_vec_toTX_1_bits_mshrTask,
+  output         io_status_vec_toTX_2_valid,
+  output [2:0]   io_status_vec_toTX_2_bits_channel,
+  output [2:0]   io_status_vec_toTX_2_bits_txChannel,
+  output         io_status_vec_toTX_2_bits_mshrTask,
+  input          io_dirResp_s3_hit,
+  input  [33:0]  io_dirResp_s3_tag,
+  input  [7:0]   io_dirResp_s3_set,
+  input  [2:0]   io_dirResp_s3_way,
+  input          io_dirResp_s3_meta_tagErr,
+  input          io_dirResp_s3_meta_dataErr,
+  input          io_dirResp_s3_error,
+  input          io_metaOnHit_s3_dirty,
+  input  [1:0]   io_metaOnHit_s3_state,
+  input          io_metaOnHit_s3_clients,
+  input          io_metaOnHit_s3_alias,
+  input          io_metaOnHit_s3_prefetch,
+  input  [3:0]   io_metaOnHit_s3_prefetchSrc,
+  input          io_metaOnHit_s3_accessed,
+  input          io_metaOnHit_s3_tagErr,
+  input          io_metaOnHit_s3_dataErr,
+  input          io_errOnSnp_s3,
+  input  [7:0]   io_dirWayOH_s3,
+  input  [7:0]   io_dirReplWayOH_s3,
+  input  [2:0]   io_replResp_bits_way,
+  input  [1:0]   io_replResp_bits_meta_state,
+  input          io_replResp_bits_retry,
+  input          io_replResp_bits_validHold,
+  input          io_retryFastFwd_s2,
+  output         io_toMSHRCtl_mshr_alloc_s3_valid,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_hit,
+  output [33:0]  io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_tag,
+  output [7:0]   io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_set,
+  output [2:0]   io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_way,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dirty,
+  output [1:0]   io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_state,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_clients,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_alias,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetch,
+  output [3:0]   io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_accessed,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_tagErr,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dataErr,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_error,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_s_acquire,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rprobe,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_s_pprobe,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_s_release,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_s_probeack,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_s_refill,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_s_cmoresp,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeackfirst,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeacklast,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeackfirst,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeacklast,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantfirst,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantlast,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grant,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_w_releaseack,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_w_replResp,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rcompack,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_state_s_dct,
+  output [2:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_channel,
+  output [7:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_set,
+  output [33:0]  io_toMSHRCtl_mshr_alloc_s3_bits_task_tag,
+  output [5:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_off,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_alias,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_isKeyword,
+  output [3:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_opcode,
+  output [2:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_param,
+  output [6:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_sourceId,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_aliasTask,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_fromL2pft,
+  output [4:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_reqSource,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitRelease,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToInval,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToClean,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseWithData,
+  output [7:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseIdx,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty,
+  output [1:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch,
+  output [3:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr,
+  output [10:0]  io_toMSHRCtl_mshr_alloc_s3_bits_task_srcID,
+  output [11:0]  io_toMSHRCtl_mshr_alloc_s3_bits_task_txnID,
+  output [10:0]  io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdNID,
+  output [11:0]  io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdTxnID,
+  output [6:0]   io_toMSHRCtl_mshr_alloc_s3_bits_task_chiOpcode,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_retToSrc,
+  output         io_toMSHRCtl_mshr_alloc_s3_bits_task_traceTag,
+  input  [7:0]   io_fromMSHRCtl_mshr_alloc_ptr,
+  input  [255:0] io_bufResp_data_0,
+  input  [255:0] io_bufResp_data_1,
+  input  [511:0] io_refillBufResp_s3_bits_data,
+  input          io_releaseBufResp_s3_valid,
+  input  [511:0] io_releaseBufResp_s3_bits_data,
+  output         io_toDS_en_s3,
+  output         io_toDS_req_s3_valid,
+  output [2:0]   io_toDS_req_s3_bits_way,
+  output [7:0]   io_toDS_req_s3_bits_set,
+  output         io_toDS_req_s3_bits_wen,
+  input  [511:0] io_toDS_rdata_s5_data,
+  output [511:0] io_toDS_wdata_s3_data,
+  input          io_toDS_error_s5,
+  output         io_toSourceD_valid,
+  output [2:0]   io_toSourceD_bits_task_channel,
+  output [2:0]   io_toSourceD_bits_task_txChannel,
+  output [7:0]   io_toSourceD_bits_task_set,
+  output [33:0]  io_toSourceD_bits_task_tag,
+  output [5:0]   io_toSourceD_bits_task_off,
+  output         io_toSourceD_bits_task_alias,
+  output [43:0]  io_toSourceD_bits_task_vaddr,
+  output         io_toSourceD_bits_task_isKeyword,
+  output [3:0]   io_toSourceD_bits_task_opcode,
+  output [2:0]   io_toSourceD_bits_task_param,
+  output [2:0]   io_toSourceD_bits_task_size,
+  output [6:0]   io_toSourceD_bits_task_sourceId,
+  output [1:0]   io_toSourceD_bits_task_bufIdx,
+  output         io_toSourceD_bits_task_needProbeAckData,
+  output         io_toSourceD_bits_task_denied,
+  output         io_toSourceD_bits_task_corrupt,
+  output         io_toSourceD_bits_task_mshrTask,
+  output [7:0]   io_toSourceD_bits_task_mshrId,
+  output         io_toSourceD_bits_task_aliasTask,
+  output         io_toSourceD_bits_task_useProbeData,
+  output         io_toSourceD_bits_task_mshrRetry,
+  output         io_toSourceD_bits_task_readProbeDataDown,
+  output         io_toSourceD_bits_task_fromL2pft,
+  output         io_toSourceD_bits_task_needHint,
+  output         io_toSourceD_bits_task_dirty,
+  output [2:0]   io_toSourceD_bits_task_way,
+  output         io_toSourceD_bits_task_meta_dirty,
+  output [1:0]   io_toSourceD_bits_task_meta_state,
+  output         io_toSourceD_bits_task_meta_clients,
+  output         io_toSourceD_bits_task_meta_alias,
+  output         io_toSourceD_bits_task_meta_prefetch,
+  output [3:0]   io_toSourceD_bits_task_meta_prefetchSrc,
+  output         io_toSourceD_bits_task_meta_accessed,
+  output         io_toSourceD_bits_task_meta_tagErr,
+  output         io_toSourceD_bits_task_meta_dataErr,
+  output         io_toSourceD_bits_task_metaWen,
+  output         io_toSourceD_bits_task_tagWen,
+  output         io_toSourceD_bits_task_dsWen,
+  output [7:0]   io_toSourceD_bits_task_wayMask,
+  output         io_toSourceD_bits_task_replTask,
+  output         io_toSourceD_bits_task_cmoTask,
+  output         io_toSourceD_bits_task_cmoAll,
+  output [4:0]   io_toSourceD_bits_task_reqSource,
+  output         io_toSourceD_bits_task_mergeA,
+  output [5:0]   io_toSourceD_bits_task_aMergeTask_off,
+  output         io_toSourceD_bits_task_aMergeTask_alias,
+  output [43:0]  io_toSourceD_bits_task_aMergeTask_vaddr,
+  output         io_toSourceD_bits_task_aMergeTask_isKeyword,
+  output [2:0]   io_toSourceD_bits_task_aMergeTask_opcode,
+  output [2:0]   io_toSourceD_bits_task_aMergeTask_param,
+  output [6:0]   io_toSourceD_bits_task_aMergeTask_sourceId,
+  output         io_toSourceD_bits_task_aMergeTask_meta_dirty,
+  output [1:0]   io_toSourceD_bits_task_aMergeTask_meta_state,
+  output         io_toSourceD_bits_task_aMergeTask_meta_clients,
+  output         io_toSourceD_bits_task_aMergeTask_meta_alias,
+  output         io_toSourceD_bits_task_aMergeTask_meta_prefetch,
+  output [3:0]   io_toSourceD_bits_task_aMergeTask_meta_prefetchSrc,
+  output         io_toSourceD_bits_task_aMergeTask_meta_accessed,
+  output         io_toSourceD_bits_task_aMergeTask_meta_tagErr,
+  output         io_toSourceD_bits_task_aMergeTask_meta_dataErr,
+  output         io_toSourceD_bits_task_snpHitRelease,
+  output         io_toSourceD_bits_task_snpHitReleaseToInval,
+  output         io_toSourceD_bits_task_snpHitReleaseToClean,
+  output         io_toSourceD_bits_task_snpHitReleaseWithData,
+  output [7:0]   io_toSourceD_bits_task_snpHitReleaseIdx,
+  output         io_toSourceD_bits_task_snpHitReleaseMeta_dirty,
+  output [1:0]   io_toSourceD_bits_task_snpHitReleaseMeta_state,
+  output         io_toSourceD_bits_task_snpHitReleaseMeta_clients,
+  output         io_toSourceD_bits_task_snpHitReleaseMeta_alias,
+  output         io_toSourceD_bits_task_snpHitReleaseMeta_prefetch,
+  output [3:0]   io_toSourceD_bits_task_snpHitReleaseMeta_prefetchSrc,
+  output         io_toSourceD_bits_task_snpHitReleaseMeta_accessed,
+  output         io_toSourceD_bits_task_snpHitReleaseMeta_tagErr,
+  output         io_toSourceD_bits_task_snpHitReleaseMeta_dataErr,
+  output [10:0]  io_toSourceD_bits_task_tgtID,
+  output [10:0]  io_toSourceD_bits_task_srcID,
+  output [11:0]  io_toSourceD_bits_task_txnID,
+  output [10:0]  io_toSourceD_bits_task_homeNID,
+  output [11:0]  io_toSourceD_bits_task_dbID,
+  output [10:0]  io_toSourceD_bits_task_fwdNID,
+  output [11:0]  io_toSourceD_bits_task_fwdTxnID,
+  output [6:0]   io_toSourceD_bits_task_chiOpcode,
+  output [2:0]   io_toSourceD_bits_task_resp,
+  output [2:0]   io_toSourceD_bits_task_fwdState,
+  output [3:0]   io_toSourceD_bits_task_pCrdType,
+  output         io_toSourceD_bits_task_retToSrc,
+  output         io_toSourceD_bits_task_likelyshared,
+  output         io_toSourceD_bits_task_expCompAck,
+  output         io_toSourceD_bits_task_allowRetry,
+  output         io_toSourceD_bits_task_memAttr_allocate,
+  output         io_toSourceD_bits_task_memAttr_cacheable,
+  output         io_toSourceD_bits_task_memAttr_device,
+  output         io_toSourceD_bits_task_memAttr_ewa,
+  output         io_toSourceD_bits_task_traceTag,
+  output [511:0] io_toSourceD_bits_data_data,
+  output         io_toTXREQ_valid,
+  output [10:0]  io_toTXREQ_bits_tgtID,
+  output [10:0]  io_toTXREQ_bits_srcID,
+  output [11:0]  io_toTXREQ_bits_txnID,
+  output [6:0]   io_toTXREQ_bits_opcode,
+  output [47:0]  io_toTXREQ_bits_addr,
+  output         io_toTXREQ_bits_likelyshared,
+  output         io_toTXREQ_bits_allowRetry,
+  output [3:0]   io_toTXREQ_bits_pCrdType,
+  output         io_toTXREQ_bits_memAttr_allocate,
+  output         io_toTXREQ_bits_memAttr_cacheable,
+  output         io_toTXREQ_bits_memAttr_device,
+  output         io_toTXREQ_bits_memAttr_ewa,
+  output         io_toTXREQ_bits_expCompAck,
+  output         io_toTXRSP_valid,
+  output         io_toTXRSP_bits_denied,
+  output [10:0]  io_toTXRSP_bits_tgtID,
+  output [10:0]  io_toTXRSP_bits_srcID,
+  output [11:0]  io_toTXRSP_bits_txnID,
+  output [11:0]  io_toTXRSP_bits_dbID,
+  output [6:0]   io_toTXRSP_bits_chiOpcode,
+  output [2:0]   io_toTXRSP_bits_resp,
+  output [2:0]   io_toTXRSP_bits_fwdState,
+  output [3:0]   io_toTXRSP_bits_pCrdType,
+  output         io_toTXRSP_bits_traceTag,
+  input          io_toTXDAT_ready,
+  output         io_toTXDAT_valid,
+  output [2:0]   io_toTXDAT_bits_task_channel,
+  output [2:0]   io_toTXDAT_bits_task_txChannel,
+  output [7:0]   io_toTXDAT_bits_task_set,
+  output [33:0]  io_toTXDAT_bits_task_tag,
+  output [5:0]   io_toTXDAT_bits_task_off,
+  output         io_toTXDAT_bits_task_alias,
+  output [43:0]  io_toTXDAT_bits_task_vaddr,
+  output         io_toTXDAT_bits_task_isKeyword,
+  output [3:0]   io_toTXDAT_bits_task_opcode,
+  output [2:0]   io_toTXDAT_bits_task_param,
+  output [2:0]   io_toTXDAT_bits_task_size,
+  output [6:0]   io_toTXDAT_bits_task_sourceId,
+  output [1:0]   io_toTXDAT_bits_task_bufIdx,
+  output         io_toTXDAT_bits_task_needProbeAckData,
+  output         io_toTXDAT_bits_task_denied,
+  output         io_toTXDAT_bits_task_corrupt,
+  output         io_toTXDAT_bits_task_mshrTask,
+  output [7:0]   io_toTXDAT_bits_task_mshrId,
+  output         io_toTXDAT_bits_task_aliasTask,
+  output         io_toTXDAT_bits_task_useProbeData,
+  output         io_toTXDAT_bits_task_mshrRetry,
+  output         io_toTXDAT_bits_task_readProbeDataDown,
+  output         io_toTXDAT_bits_task_fromL2pft,
+  output         io_toTXDAT_bits_task_needHint,
+  output         io_toTXDAT_bits_task_dirty,
+  output [2:0]   io_toTXDAT_bits_task_way,
+  output         io_toTXDAT_bits_task_meta_dirty,
+  output [1:0]   io_toTXDAT_bits_task_meta_state,
+  output         io_toTXDAT_bits_task_meta_clients,
+  output         io_toTXDAT_bits_task_meta_alias,
+  output         io_toTXDAT_bits_task_meta_prefetch,
+  output [3:0]   io_toTXDAT_bits_task_meta_prefetchSrc,
+  output         io_toTXDAT_bits_task_meta_accessed,
+  output         io_toTXDAT_bits_task_meta_tagErr,
+  output         io_toTXDAT_bits_task_meta_dataErr,
+  output         io_toTXDAT_bits_task_metaWen,
+  output         io_toTXDAT_bits_task_tagWen,
+  output         io_toTXDAT_bits_task_dsWen,
+  output [7:0]   io_toTXDAT_bits_task_wayMask,
+  output         io_toTXDAT_bits_task_replTask,
+  output         io_toTXDAT_bits_task_cmoTask,
+  output         io_toTXDAT_bits_task_cmoAll,
+  output [4:0]   io_toTXDAT_bits_task_reqSource,
+  output         io_toTXDAT_bits_task_mergeA,
+  output [5:0]   io_toTXDAT_bits_task_aMergeTask_off,
+  output         io_toTXDAT_bits_task_aMergeTask_alias,
+  output [43:0]  io_toTXDAT_bits_task_aMergeTask_vaddr,
+  output         io_toTXDAT_bits_task_aMergeTask_isKeyword,
+  output [2:0]   io_toTXDAT_bits_task_aMergeTask_opcode,
+  output [2:0]   io_toTXDAT_bits_task_aMergeTask_param,
+  output [6:0]   io_toTXDAT_bits_task_aMergeTask_sourceId,
+  output         io_toTXDAT_bits_task_aMergeTask_meta_dirty,
+  output [1:0]   io_toTXDAT_bits_task_aMergeTask_meta_state,
+  output         io_toTXDAT_bits_task_aMergeTask_meta_clients,
+  output         io_toTXDAT_bits_task_aMergeTask_meta_alias,
+  output         io_toTXDAT_bits_task_aMergeTask_meta_prefetch,
+  output [3:0]   io_toTXDAT_bits_task_aMergeTask_meta_prefetchSrc,
+  output         io_toTXDAT_bits_task_aMergeTask_meta_accessed,
+  output         io_toTXDAT_bits_task_aMergeTask_meta_tagErr,
+  output         io_toTXDAT_bits_task_aMergeTask_meta_dataErr,
+  output         io_toTXDAT_bits_task_snpHitRelease,
+  output         io_toTXDAT_bits_task_snpHitReleaseToInval,
+  output         io_toTXDAT_bits_task_snpHitReleaseToClean,
+  output         io_toTXDAT_bits_task_snpHitReleaseWithData,
+  output [7:0]   io_toTXDAT_bits_task_snpHitReleaseIdx,
+  output         io_toTXDAT_bits_task_snpHitReleaseMeta_dirty,
+  output [1:0]   io_toTXDAT_bits_task_snpHitReleaseMeta_state,
+  output         io_toTXDAT_bits_task_snpHitReleaseMeta_clients,
+  output         io_toTXDAT_bits_task_snpHitReleaseMeta_alias,
+  output         io_toTXDAT_bits_task_snpHitReleaseMeta_prefetch,
+  output [3:0]   io_toTXDAT_bits_task_snpHitReleaseMeta_prefetchSrc,
+  output         io_toTXDAT_bits_task_snpHitReleaseMeta_accessed,
+  output         io_toTXDAT_bits_task_snpHitReleaseMeta_tagErr,
+  output         io_toTXDAT_bits_task_snpHitReleaseMeta_dataErr,
+  output [10:0]  io_toTXDAT_bits_task_tgtID,
+  output [10:0]  io_toTXDAT_bits_task_srcID,
+  output [11:0]  io_toTXDAT_bits_task_txnID,
+  output [10:0]  io_toTXDAT_bits_task_homeNID,
+  output [11:0]  io_toTXDAT_bits_task_dbID,
+  output [10:0]  io_toTXDAT_bits_task_fwdNID,
+  output [11:0]  io_toTXDAT_bits_task_fwdTxnID,
+  output [6:0]   io_toTXDAT_bits_task_chiOpcode,
+  output [2:0]   io_toTXDAT_bits_task_resp,
+  output [2:0]   io_toTXDAT_bits_task_fwdState,
+  output [3:0]   io_toTXDAT_bits_task_pCrdType,
+  output         io_toTXDAT_bits_task_retToSrc,
+  output         io_toTXDAT_bits_task_likelyshared,
+  output         io_toTXDAT_bits_task_expCompAck,
+  output         io_toTXDAT_bits_task_allowRetry,
+  output         io_toTXDAT_bits_task_memAttr_allocate,
+  output         io_toTXDAT_bits_task_memAttr_cacheable,
+  output         io_toTXDAT_bits_task_memAttr_device,
+  output         io_toTXDAT_bits_task_memAttr_ewa,
+  output         io_toTXDAT_bits_task_traceTag,
+  output [511:0] io_toTXDAT_bits_data_data,
+  output         io_metaWReq_valid,
+  output [7:0]   io_metaWReq_bits_set,
+  output [7:0]   io_metaWReq_bits_wayOH,
+  output         io_metaWReq_bits_wmeta_dirty,
+  output [1:0]   io_metaWReq_bits_wmeta_state,
+  output         io_metaWReq_bits_wmeta_clients,
+  output         io_metaWReq_bits_wmeta_alias,
+  output         io_metaWReq_bits_wmeta_prefetch,
+  output [3:0]   io_metaWReq_bits_wmeta_prefetchSrc,
+  output         io_metaWReq_bits_wmeta_accessed,
+  output         io_metaWReq_bits_wmeta_tagErr,
+  output         io_metaWReq_bits_wmeta_dataErr,
+  output         io_tagWReq_valid,
+  output [7:0]   io_tagWReq_bits_set,
+  output [7:0]   io_tagWReq_bits_wayOH,
+  output [33:0]  io_tagWReq_bits_wtag,
+  output         io_releaseBufWrite_valid,
+  output [7:0]   io_releaseBufWrite_bits_id,
+  output [511:0] io_releaseBufWrite_bits_data_data,
+  output [7:0]   io_nestedwb_set,
+  output [33:0]  io_nestedwb_tag,
+  output         io_nestedwb_c_set_dirty,
+  output         io_nestedwb_c_set_tip,
+  output         io_nestedwb_b_inv_dirty,
+  output         io_nestedwb_b_toB,
+  output         io_nestedwb_b_toN,
+  output         io_nestedwb_b_toClean,
+  output [511:0] io_nestedwbData_data,
+  input          io_l1Hint_ready,
+  output         io_l1Hint_valid,
+  output [6:0]   io_l1Hint_bits_sourceId,
+  output         io_l1Hint_bits_isKeyword,
+  output         io_l1Hint_bits_hasData,
+  output         io_prefetchTrain_valid,
+  output [33:0]  io_prefetchTrain_bits_tag,
+  output [7:0]   io_prefetchTrain_bits_set,
+  output         io_prefetchTrain_bits_needT,
+  output [6:0]   io_prefetchTrain_bits_source,
+  output [43:0]  io_prefetchTrain_bits_vaddr,
+  output         io_prefetchTrain_bits_hit,
+  output         io_prefetchTrain_bits_prefetched,
+  output [3:0]   io_prefetchTrain_bits_pfsource,
+  output [4:0]   io_prefetchTrain_bits_reqsource,
+  output         io_error_valid,
+  output         io_error_bits_valid,
+  output [47:0]  io_error_bits_address,
+  output [5:0]   io_perf_0_value,
+  output [5:0]   io_perf_1_value,
+  output [5:0]   io_perf_2_value,
+  output [5:0]   io_perf_3_value,
+  output [5:0]   io_perf_4_value,
+  output [5:0]   io_perf_5_value,
+  output [5:0]   io_perf_6_value,
+  output [5:0]   io_perf_7_value,
+  output [5:0]   io_perf_8_value,
+  output [5:0]   io_perf_9_value,
+  output [5:0]   io_perf_10_value,
+  output [5:0]   io_perf_11_value,
+  output [5:0]   io_perf_12_value
+);
+
+  wire             txdat_s4_valid;
+  wire             txrsp_s4_valid;
+  wire             txreq_s4_valid;
+  wire             d_s4_valid;
+  wire             d_s3_valid;
+  wire             txdat_s3_valid;
+  wire             txrsp_s3_valid;
+  wire             txreq_s3_valid;
+  wire             metaW_s3_b_dataErr;
+  wire             metaW_s3_b_tagErr;
+  wire             metaW_s3_b_accessed;
+  wire             metaW_s3_b_alias;
+  wire             metaW_s3_b_clients;
+  wire [1:0]       metaW_s3_b_state;
+  wire             metaW_valid_s3_b;
+  wire             _toTXDAT_arb_io_in_1_ready;
+  wire             _toTXDAT_arb_io_in_2_ready;
+  wire             _toTXRSP_arb_io_in_1_ready;
+  wire             _toTXRSP_arb_io_in_2_ready;
+  wire             _toTXREQ_arb_io_in_1_ready;
+  wire             _toTXREQ_arb_io_in_2_ready;
+  wire             _toSourceD_arb_io_in_1_ready;
+  wire             _toSourceD_arb_io_in_2_ready;
+  wire [15:0][3:0] _GEN =
+    '{4'h0,
+      4'h8,
+      4'h8,
+      4'h8,
+      4'h0,
+      4'h0,
+      4'h0,
+      4'h0,
+      4'h4,
+      4'h5,
+      4'h2,
+      4'h1,
+      4'h1,
+      4'h1,
+      4'h0,
+      4'h0};
+  reg              resetFinish;
+  reg  [7:0]       resetIdx;
+  reg              task_s3_valid;
+  reg  [2:0]       task_s3_bits_channel;
+  reg  [2:0]       task_s3_bits_txChannel;
+  reg  [7:0]       task_s3_bits_set;
+  reg  [33:0]      task_s3_bits_tag;
+  reg  [5:0]       task_s3_bits_off;
+  reg              task_s3_bits_alias;
+  reg  [43:0]      task_s3_bits_vaddr;
+  reg              task_s3_bits_isKeyword;
+  reg  [3:0]       task_s3_bits_opcode;
+  reg  [2:0]       task_s3_bits_param;
+  reg  [2:0]       task_s3_bits_size;
+  reg  [6:0]       task_s3_bits_sourceId;
+  reg  [1:0]       task_s3_bits_bufIdx;
+  reg              task_s3_bits_needProbeAckData;
+  reg              task_s3_bits_denied;
+  reg              task_s3_bits_corrupt;
+  reg              task_s3_bits_mshrTask;
+  reg  [7:0]       task_s3_bits_mshrId;
+  reg              task_s3_bits_aliasTask;
+  reg              task_s3_bits_useProbeData;
+  reg              task_s3_bits_mshrRetry;
+  reg              task_s3_bits_readProbeDataDown;
+  reg              task_s3_bits_fromL2pft;
+  reg              task_s3_bits_needHint;
+  reg              task_s3_bits_dirty;
+  reg  [2:0]       task_s3_bits_way;
+  reg              task_s3_bits_meta_dirty;
+  reg  [1:0]       task_s3_bits_meta_state;
+  reg              task_s3_bits_meta_clients;
+  reg              task_s3_bits_meta_alias;
+  reg              task_s3_bits_meta_prefetch;
+  reg  [3:0]       task_s3_bits_meta_prefetchSrc;
+  reg              task_s3_bits_meta_accessed;
+  reg              task_s3_bits_meta_tagErr;
+  reg              task_s3_bits_meta_dataErr;
+  reg              task_s3_bits_metaWen;
+  reg              task_s3_bits_tagWen;
+  reg              task_s3_bits_dsWen;
+  reg  [7:0]       task_s3_bits_wayMask;
+  reg              task_s3_bits_replTask;
+  reg              task_s3_bits_cmoTask;
+  reg              task_s3_bits_cmoAll;
+  reg  [4:0]       task_s3_bits_reqSource;
+  reg              task_s3_bits_mergeA;
+  reg  [5:0]       task_s3_bits_aMergeTask_off;
+  reg              task_s3_bits_aMergeTask_alias;
+  reg  [43:0]      task_s3_bits_aMergeTask_vaddr;
+  reg              task_s3_bits_aMergeTask_isKeyword;
+  reg  [2:0]       task_s3_bits_aMergeTask_opcode;
+  reg  [2:0]       task_s3_bits_aMergeTask_param;
+  reg  [6:0]       task_s3_bits_aMergeTask_sourceId;
+  reg              task_s3_bits_aMergeTask_meta_dirty;
+  reg  [1:0]       task_s3_bits_aMergeTask_meta_state;
+  reg              task_s3_bits_aMergeTask_meta_clients;
+  reg              task_s3_bits_aMergeTask_meta_alias;
+  reg              task_s3_bits_aMergeTask_meta_prefetch;
+  reg  [3:0]       task_s3_bits_aMergeTask_meta_prefetchSrc;
+  reg              task_s3_bits_aMergeTask_meta_accessed;
+  reg              task_s3_bits_aMergeTask_meta_tagErr;
+  reg              task_s3_bits_aMergeTask_meta_dataErr;
+  reg              task_s3_bits_snpHitRelease;
+  reg              task_s3_bits_snpHitReleaseToInval;
+  reg              task_s3_bits_snpHitReleaseToClean;
+  reg              task_s3_bits_snpHitReleaseWithData;
+  reg  [7:0]       task_s3_bits_snpHitReleaseIdx;
+  reg              task_s3_bits_snpHitReleaseMeta_dirty;
+  reg  [1:0]       task_s3_bits_snpHitReleaseMeta_state;
+  reg              task_s3_bits_snpHitReleaseMeta_clients;
+  reg              task_s3_bits_snpHitReleaseMeta_alias;
+  reg              task_s3_bits_snpHitReleaseMeta_prefetch;
+  reg  [3:0]       task_s3_bits_snpHitReleaseMeta_prefetchSrc;
+  reg              task_s3_bits_snpHitReleaseMeta_accessed;
+  reg              task_s3_bits_snpHitReleaseMeta_tagErr;
+  reg              task_s3_bits_snpHitReleaseMeta_dataErr;
+  reg  [10:0]      task_s3_bits_tgtID;
+  reg  [10:0]      task_s3_bits_srcID;
+  reg  [11:0]      task_s3_bits_txnID;
+  reg  [10:0]      task_s3_bits_homeNID;
+  reg  [11:0]      task_s3_bits_dbID;
+  reg  [10:0]      task_s3_bits_fwdNID;
+  reg  [11:0]      task_s3_bits_fwdTxnID;
+  reg  [6:0]       task_s3_bits_chiOpcode;
+  reg  [2:0]       task_s3_bits_resp;
+  reg  [2:0]       task_s3_bits_fwdState;
+  reg  [3:0]       task_s3_bits_pCrdType;
+  reg              task_s3_bits_retToSrc;
+  reg              task_s3_bits_likelyshared;
+  reg              task_s3_bits_expCompAck;
+  reg              task_s3_bits_allowRetry;
+  reg              task_s3_bits_memAttr_allocate;
+  reg              task_s3_bits_memAttr_cacheable;
+  reg              task_s3_bits_memAttr_device;
+  reg              task_s3_bits_memAttr_ewa;
+  reg              task_s3_bits_traceTag;
+  reg  [7:0]       reqWayOH_s3;
+  wire             sinkA_req_s3 = ~task_s3_bits_mshrTask & task_s3_bits_channel[0];
+  wire             sinkB_req_s3 = ~task_s3_bits_mshrTask & task_s3_bits_channel[1];
+  wire             sinkC_req_s3 = ~task_s3_bits_mshrTask & task_s3_bits_channel[2];
+  wire             _io_nestedwb_c_set_tip_T_2 = task_s3_bits_opcode == 4'h6;
+  wire             _perfEvents_T_7 = task_s3_bits_opcode == 4'h7;
+  wire             req_acquire_s3 =
+    sinkA_req_s3 & (_io_nestedwb_c_set_tip_T_2 | _perfEvents_T_7);
+  wire             _req_needT_s3_T_2 = task_s3_bits_opcode == 4'h5;
+  wire             req_prefetch_s3 = sinkA_req_s3 & _req_needT_s3_T_2;
+  wire             _mshr_grant_s3_T_2 = task_s3_bits_opcode == 4'h4;
+  wire             req_get_s3 = sinkA_req_s3 & _mshr_grant_s3_T_2;
+  wire             req_cbo_clean_s3 = sinkA_req_s3 & task_s3_bits_opcode == 4'hC;
+  wire             req_cbo_flush_s3 = sinkA_req_s3 & task_s3_bits_opcode == 4'hD;
+  wire             req_cbo_inval_s3 = sinkA_req_s3 & task_s3_bits_opcode == 4'hE;
+  wire             mshr_cmoresp_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_channel[0] & task_s3_bits_opcode == 4'h8;
+  wire             _shouldRespData_retToSrc_nonFwd_T_11 = task_s3_bits_chiOpcode == 7'h1;
+  wire             _metaW_s3_b_T_9 = task_s3_bits_chiOpcode == 7'h9;
+  wire             mshr_snpRespX_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_txChannel[1]
+    & _shouldRespData_retToSrc_nonFwd_T_11 | task_s3_bits_mshrTask
+    & task_s3_bits_txChannel[1] & _metaW_s3_b_T_9;
+  wire             mshr_snpRespDataX_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_txChannel[2] & task_s3_bits_chiOpcode == 7'h1
+    | task_s3_bits_mshrTask & task_s3_bits_txChannel[2] & task_s3_bits_chiOpcode == 7'h5
+    | task_s3_bits_mshrTask & task_s3_bits_txChannel[2] & task_s3_bits_chiOpcode == 7'h6;
+  wire             mshr_dct_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_txChannel[2] & task_s3_bits_chiOpcode == 7'h4;
+  wire             mshr_writeCleanFull_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_txChannel[0] & task_s3_bits_chiOpcode == 7'h17;
+  wire             mshr_writeBackFull_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_txChannel[0] & task_s3_bits_chiOpcode == 7'h1B;
+  wire             mshr_writeEvictFull_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_txChannel[0] & task_s3_bits_chiOpcode == 7'h15;
+  wire             mshr_writeEvictOrEvict_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_txChannel[0] & task_s3_bits_chiOpcode == 7'h42;
+  wire             mshr_evict_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_txChannel[0] & task_s3_bits_chiOpcode == 7'hD;
+  wire             mshr_cbWrData_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_txChannel[2] & task_s3_bits_chiOpcode == 7'h2;
+  wire             req_needT_s3 =
+    ~(task_s3_bits_opcode[2]) | _req_needT_s3_T_2 & task_s3_bits_param == 3'h1
+    | (_io_nestedwb_c_set_tip_T_2 | _perfEvents_T_7) & (|task_s3_bits_param);
+  wire             cmo_cbo_s3 = req_cbo_clean_s3 | req_cbo_flush_s3 | req_cbo_inval_s3;
+  wire             cache_alias =
+    req_acquire_s3 & io_dirResp_s3_hit & io_metaOnHit_s3_clients
+    & io_metaOnHit_s3_alias != task_s3_bits_alias;
+  wire             nestable_dirResult_s3_hit =
+    task_s3_bits_snpHitRelease
+      ? (|task_s3_bits_snpHitReleaseMeta_state)
+      : io_dirResp_s3_hit;
+  wire [1:0]       nestable_dirResult_s3_meta_state =
+    task_s3_bits_snpHitRelease
+      ? task_s3_bits_snpHitReleaseMeta_state
+      : io_metaOnHit_s3_state;
+  wire             nestable_dirResult_s3_meta_dirty =
+    task_s3_bits_snpHitRelease
+      ? task_s3_bits_snpHitReleaseMeta_dirty
+      : io_metaOnHit_s3_dirty;
+  wire             tagError_s3 = io_dirResp_s3_error | io_dirResp_s3_meta_tagErr;
+  wire             mshr_refill_s3 =
+    task_s3_bits_mshrTask & task_s3_bits_channel[0] & task_s3_bits_opcode == 4'h1
+    | task_s3_bits_mshrTask & task_s3_bits_channel[0] & task_s3_bits_opcode == 4'h2
+    | task_s3_bits_mshrTask & task_s3_bits_channel[0]
+    & (_mshr_grant_s3_T_2 | _req_needT_s3_T_2);
+  wire             retry = io_replResp_bits_validHold & io_replResp_bits_retry;
+  wire             need_repl =
+    io_replResp_bits_validHold & (|io_replResp_bits_meta_state) & task_s3_bits_replTask;
+  wire             _metaW_valid_s3_b_T_17 = io_metaOnHit_s3_state == 2'h1;
+  wire             need_acquire_s3_a =
+    task_s3_bits_channel[0]
+    & ((io_dirResp_s3_hit
+          ? _metaW_valid_s3_b_T_17 & req_needT_s3 & ~req_prefetch_s3
+          : req_acquire_s3 | req_prefetch_s3 | req_get_s3) | cmo_cbo_s3);
+  wire             _need_pprobe_s3_b_snpToB_T_16 = io_metaOnHit_s3_state == 2'h2;
+  wire             need_probe_s3_a =
+    io_dirResp_s3_hit & io_metaOnHit_s3_clients
+    & (req_get_s3 & _need_pprobe_s3_b_snpToB_T_16 | req_cbo_clean_s3
+       & _need_pprobe_s3_b_snpToB_T_16 | req_cbo_flush_s3 | req_cbo_inval_s3);
+  wire             need_mshr_s3_a = need_acquire_s3_a | need_probe_s3_a | cache_alias;
+  wire             _shouldRespData_retToSrc_fwd_T_1 = task_s3_bits_chiOpcode == 7'h11;
+  wire             _shouldRespData_retToSrc_fwd_T_2 = task_s3_bits_chiOpcode == 7'h12;
+  wire             _shouldRespData_retToSrc_fwd_T_4 = task_s3_bits_chiOpcode == 7'h13;
+  wire             _shouldRespData_retToSrc_fwd_T_6 = task_s3_bits_chiOpcode == 7'h14;
+  wire             _metaW_s3_b_T_1 = task_s3_bits_chiOpcode == 7'h17;
+  wire             _metaW_s3_b_T_7 = task_s3_bits_chiOpcode == 7'h16;
+  wire             doFwd =
+    (_shouldRespData_retToSrc_fwd_T_1 | _shouldRespData_retToSrc_fwd_T_2
+     | _shouldRespData_retToSrc_fwd_T_4 | _shouldRespData_retToSrc_fwd_T_6
+     | _metaW_s3_b_T_1 | _metaW_s3_b_T_7) & nestable_dirResult_s3_hit
+    & ~((task_s3_bits_snpHitRelease
+           ? task_s3_bits_snpHitReleaseMeta_tagErr
+           : io_metaOnHit_s3_tagErr) | io_errOnSnp_s3);
+  wire             _metaW_valid_s3_b_T_3 = task_s3_bits_chiOpcode == 7'h3;
+  wire             _io_nestedwb_b_inv_dirty_T_6 = task_s3_bits_chiOpcode == 7'h10;
+  wire             _io_nestedwb_b_inv_dirty_T_3 = task_s3_bits_chiOpcode == 7'hB;
+  wire             _io_nestedwb_b_inv_dirty_T_4 = task_s3_bits_chiOpcode == 7'hC;
+  wire             _shouldRespData_retToSrc_nonFwd_T_8 = task_s3_bits_chiOpcode == 7'h2;
+  wire             _shouldRespData_retToSrc_nonFwd_T_9 = task_s3_bits_chiOpcode == 7'h4;
+  wire             _metaW_s3_b_x11_T = task_s3_bits_chiOpcode == 7'h8;
+  wire             _metaW_s3_b_T = task_s3_bits_chiOpcode == 7'h7;
+  wire             _metaW_s3_b_T_3 = task_s3_bits_chiOpcode == 7'h5;
+  wire             _metaW_s3_b_T_5 = task_s3_bits_chiOpcode == 7'h15;
+  wire             _metaW_s3_b_T_11 = task_s3_bits_chiOpcode == 7'hA;
+  wire             _metaW_s3_b_T_12 = task_s3_bits_chiOpcode == 7'h6;
+  wire             need_pprobe_s3_b =
+    task_s3_bits_channel[1]
+    & (_metaW_valid_s3_b_T_3 | _shouldRespData_retToSrc_fwd_T_4
+       | _io_nestedwb_b_inv_dirty_T_6 | _io_nestedwb_b_inv_dirty_T_3
+       | _io_nestedwb_b_inv_dirty_T_4) & io_dirResp_s3_hit & _need_pprobe_s3_b_snpToB_T_16
+    & io_metaOnHit_s3_clients | task_s3_bits_channel[1]
+    & (_shouldRespData_retToSrc_nonFwd_T_8 | _shouldRespData_retToSrc_fwd_T_2
+       | _shouldRespData_retToSrc_nonFwd_T_11 | _shouldRespData_retToSrc_fwd_T_1
+       | _shouldRespData_retToSrc_nonFwd_T_9 | _shouldRespData_retToSrc_fwd_T_6
+       | _metaW_s3_b_x11_T) & io_dirResp_s3_hit & _need_pprobe_s3_b_snpToB_T_16
+    & io_metaOnHit_s3_clients | task_s3_bits_channel[1]
+    & (_metaW_s3_b_T | _metaW_s3_b_T_1 | _metaW_s3_b_T_3 | _metaW_s3_b_T_5
+       | _metaW_s3_b_T_7 | _metaW_s3_b_T_9 | _metaW_s3_b_T_11 | _metaW_s3_b_T_12)
+    & io_dirResp_s3_hit & io_metaOnHit_s3_clients | task_s3_bits_channel[1]
+    & (io_errOnSnp_s3 | io_metaOnHit_s3_tagErr) & io_dirResp_s3_hit;
+  wire             need_mshr_s3_b = need_pprobe_s3_b | doFwd;
+  wire             need_mshr_s3 = need_mshr_s3_a | need_mshr_s3_b;
+  wire             sink_resp_s3_a_promoteT = io_dirResp_s3_hit & io_metaOnHit_s3_state[1];
+  wire             neverRespData =
+    _metaW_s3_b_T_11 | _metaW_s3_b_T_12 | _io_nestedwb_b_inv_dirty_T_3
+    | _io_nestedwb_b_inv_dirty_T_4 | _io_nestedwb_b_inv_dirty_T_6
+    | _shouldRespData_retToSrc_fwd_T_4 | _metaW_s3_b_T_1 | _metaW_s3_b_T_7;
+  wire             _need_data_b_T_1 = nestable_dirResult_s3_meta_state == 2'h2;
+  wire             _shouldRespData_retToSrc_nonFwd_T =
+    nestable_dirResult_s3_hit & task_s3_bits_retToSrc;
+  wire             _respCacheState_T_1 = nestable_dirResult_s3_meta_state == 2'h1;
+  wire             shouldRespData =
+    nestable_dirResult_s3_hit & ((&nestable_dirResult_s3_meta_state) | _need_data_b_T_1)
+    & nestable_dirResult_s3_meta_dirty | nestable_dirResult_s3_hit
+    & (&nestable_dirResult_s3_meta_state) & ~nestable_dirResult_s3_meta_dirty
+    & _metaW_valid_s3_b_T_3 | _shouldRespData_retToSrc_nonFwd_T
+    & (_shouldRespData_retToSrc_fwd_T_1 | _shouldRespData_retToSrc_fwd_T_2
+       | _shouldRespData_retToSrc_fwd_T_4 | _shouldRespData_retToSrc_fwd_T_6
+       | _metaW_s3_b_T_1 | _metaW_s3_b_T_7) | _shouldRespData_retToSrc_nonFwd_T
+    & _respCacheState_T_1
+    & (_metaW_valid_s3_b_T_3 | _metaW_s3_b_T | _metaW_s3_b_T_5
+       | _shouldRespData_retToSrc_nonFwd_T_8 | _shouldRespData_retToSrc_nonFwd_T_9
+       | _shouldRespData_retToSrc_nonFwd_T_11);
+  wire             doRespData = shouldRespData & ~neverRespData;
+  wire             _GEN_0 =
+    _shouldRespData_retToSrc_nonFwd_T_8 | _shouldRespData_retToSrc_fwd_T_2
+    | _shouldRespData_retToSrc_nonFwd_T_11 | _shouldRespData_retToSrc_fwd_T_1
+    | _shouldRespData_retToSrc_nonFwd_T_9 | _shouldRespData_retToSrc_fwd_T_6;
+  wire             _GEN_1 = _metaW_valid_s3_b_T_3 | _shouldRespData_retToSrc_fwd_T_4;
+  wire             _GEN_2 =
+    _GEN_1 | _io_nestedwb_b_inv_dirty_T_3 | _io_nestedwb_b_inv_dirty_T_4
+    | _io_nestedwb_b_inv_dirty_T_6;
+  wire [2:0]       _respCacheState_T_3 = _respCacheState_T_1 ? 3'h1 : 3'h2;
+  wire             _GEN_3 = _metaW_s3_b_T_1 | _metaW_s3_b_T_7;
+  wire             sink_resp_s3_valid =
+    task_s3_valid & ~task_s3_bits_mshrTask & ~need_mshr_s3;
+  wire [1:0]       _sink_resp_s3_bits_chiOpcode_T = {doFwd, doRespData};
+  wire [3:0]       sink_resp_s3_bits_opcode =
+    task_s3_bits_channel[0]
+      ? _GEN[task_s3_bits_opcode]
+      : task_s3_bits_channel[1] ? 4'h0 : 4'h6;
+  wire             _GEN_4 =
+    ~sink_resp_s3_valid | task_s3_bits_channel[0] | ~(task_s3_bits_channel[1]);
+  wire [2:0]       source_req_s3_txChannel =
+    _GEN_4 ? task_s3_bits_txChannel : {doRespData, ~doRespData, 1'h0};
+  wire [3:0]       source_req_s3_opcode =
+    sink_resp_s3_valid ? sink_resp_s3_bits_opcode : task_s3_bits_opcode;
+  wire [2:0]       source_req_s3_param =
+    sink_resp_s3_valid
+      ? (task_s3_bits_channel[0]
+           ? {2'h0, req_acquire_s3 & ~(|task_s3_bits_param) & ~sink_resp_s3_a_promoteT}
+           : 3'h0)
+      : task_s3_bits_param;
+  wire [2:0]       source_req_s3_size = _GEN_4 ? task_s3_bits_size : 3'h6;
+  wire [7:0]       source_req_s3_mshrId =
+    sink_resp_s3_valid ? 8'({1'h0, task_s3_bits_sourceId} - 8'h80) : task_s3_bits_mshrId;
+  wire             source_req_s3_meta_dirty = _GEN_4 & task_s3_bits_meta_dirty;
+  wire [1:0]       source_req_s3_meta_state =
+    _GEN_4 ? task_s3_bits_meta_state : metaW_s3_b_state;
+  wire             source_req_s3_meta_clients =
+    _GEN_4 ? task_s3_bits_meta_clients : metaW_s3_b_clients;
+  wire             source_req_s3_meta_alias =
+    _GEN_4 ? task_s3_bits_meta_alias : metaW_s3_b_alias;
+  wire             source_req_s3_meta_prefetch = _GEN_4 & task_s3_bits_meta_prefetch;
+  wire [3:0]       source_req_s3_meta_prefetchSrc =
+    _GEN_4 ? task_s3_bits_meta_prefetchSrc : 4'h0;
+  wire             source_req_s3_meta_accessed =
+    _GEN_4 ? task_s3_bits_meta_accessed : metaW_s3_b_accessed;
+  wire             source_req_s3_meta_tagErr =
+    _GEN_4 ? task_s3_bits_meta_tagErr : metaW_s3_b_tagErr;
+  wire             source_req_s3_meta_dataErr =
+    _GEN_4 ? task_s3_bits_meta_dataErr : metaW_s3_b_dataErr;
+  wire             source_req_s3_metaWen =
+    _GEN_4 ? task_s3_bits_metaWen : metaW_valid_s3_b;
+  wire [10:0]      source_req_s3_tgtID = _GEN_4 ? task_s3_bits_tgtID : task_s3_bits_srcID;
+  wire [10:0]      source_req_s3_srcID = _GEN_4 ? task_s3_bits_srcID : task_s3_bits_tgtID;
+  wire [11:0]      source_req_s3_dbID = _GEN_4 ? task_s3_bits_dbID : 12'h0;
+  wire [6:0]       txreq_s3_bits_opcode =
+    _GEN_4
+      ? task_s3_bits_chiOpcode
+      : {2'h0,
+         (&_sink_resp_s3_bits_chiOpcode_T)
+           ? 5'h6
+           : _sink_resp_s3_bits_chiOpcode_T == 2'h1
+               ? 5'h1
+               : {1'h0, _sink_resp_s3_bits_chiOpcode_T == 2'h2, 3'h1}};
+  wire [2:0]       source_req_s3_resp =
+    _GEN_4
+      ? task_s3_bits_resp
+      : (nestable_dirResult_s3_hit & ~tagError_s3
+           ? (_metaW_s3_b_x11_T
+                ? (nestable_dirResult_s3_meta_state[1] ? 3'h2 : 3'h1)
+                : _GEN_1
+                    ? (task_s3_bits_snpHitReleaseToInval
+                         ? 3'h0
+                         : task_s3_bits_snpHitReleaseToClean
+                           & nestable_dirResult_s3_meta_dirty
+                             ? 3'h1
+                             : _GEN_2 ? _respCacheState_T_3 : {2'h0, _GEN_0})
+                    : _GEN_2
+                        ? _respCacheState_T_3
+                        : _GEN_0 ? {2'h0, ~task_s3_bits_snpHitReleaseToInval} : 3'h0)
+           : 3'h0)
+        | {doRespData & nestable_dirResult_s3_hit & nestable_dirResult_s3_meta_state[1]
+             & nestable_dirResult_s3_meta_dirty
+             & (task_s3_bits_chiOpcode != 7'h3 | task_s3_bits_snpHitRelease)
+             & ~(_io_nestedwb_b_inv_dirty_T_3 | _io_nestedwb_b_inv_dirty_T_4
+                 | _io_nestedwb_b_inv_dirty_T_6),
+           2'h0};
+  wire [2:0]       source_req_s3_fwdState =
+    _GEN_4
+      ? task_s3_bits_fwdState
+      : (nestable_dirResult_s3_hit
+           ? (_GEN_3
+                ? 3'h2
+                : _shouldRespData_retToSrc_fwd_T_2 | _shouldRespData_retToSrc_fwd_T_6
+                  | _shouldRespData_retToSrc_fwd_T_1
+                    ? {2'h0, ~task_s3_bits_snpHitReleaseToInval}
+                    : 3'h0)
+           : 3'h0)
+        | {nestable_dirResult_s3_hit & _GEN_3 & (&nestable_dirResult_s3_meta_state)
+             & nestable_dirResult_s3_meta_dirty,
+           2'h0};
+  wire [3:0]       source_req_s3_pCrdType = _GEN_4 ? task_s3_bits_pCrdType : 4'h0;
+  wire [511:0]     data_s3 =
+    io_releaseBufResp_s3_valid
+      ? io_releaseBufResp_s3_bits_data
+      : io_refillBufResp_s3_bits_data;
+  wire [511:0]     c_releaseData_s3 = {io_bufResp_data_1, io_bufResp_data_0};
+  wire             hasData_s3 = source_req_s3_opcode[0] | source_req_s3_txChannel[2];
+  wire             need_data_b =
+    sinkB_req_s3 & (doRespData | doFwd | nestable_dirResult_s3_hit & _need_data_b_T_1);
+  wire             need_data_mshr_repl = mshr_refill_s3 & need_repl & ~retry;
+  wire             need_data_cmo =
+    cmo_cbo_s3 & nestable_dirResult_s3_hit & nestable_dirResult_s3_meta_dirty;
+  wire             _io_nestedwb_c_set_tip_T_4 = task_s3_bits_param == 3'h1;
+  wire             _metaW_s3_c_x20_T_3 = task_s3_bits_param == 3'h3;
+  wire             wen_c =
+    sinkC_req_s3
+    & (_io_nestedwb_c_set_tip_T_4 | ~(|task_s3_bits_param) | _metaW_s3_c_x20_T_3)
+    & task_s3_bits_opcode[0] & io_dirResp_s3_hit;
+  wire             wen =
+    wen_c | task_s3_bits_dsWen
+    & (mshr_snpRespX_s3 | mshr_snpRespDataX_s3 | mshr_writeCleanFull_s3
+       | mshr_writeBackFull_s3 | mshr_writeEvictFull_s3 | mshr_writeEvictOrEvict_s3
+       | mshr_evict_s3 | mshr_refill_s3 & ~need_repl & ~retry);
+  reg              task_s3_valid_hold2_REG;
+  reg              task_s3_valid_hold2;
+  wire             _io_toDS_req_s3_valid_T =
+    io_dirResp_s3_hit & (req_get_s3 | sinkA_req_s3 & _io_nestedwb_c_set_tip_T_2)
+    | need_data_b | need_data_mshr_repl | need_data_cmo | wen;
+  wire             _io_tagWReq_bits_wayOH_T = mshr_refill_s3 & task_s3_bits_replTask;
+  wire             _need_write_releaseBuf_T = need_probe_s3_a | cache_alias;
+  wire             need_write_releaseBuf =
+    _need_write_releaseBuf_T | need_data_b & need_mshr_s3_b | need_data_mshr_repl
+    | need_data_cmo;
+  wire             metaW_valid_s3_a =
+    sinkA_req_s3 & ~need_mshr_s3_a & ~req_get_s3 & ~req_prefetch_s3 & ~cmo_cbo_s3;
+  assign metaW_valid_s3_b =
+    sinkB_req_s3 & ~need_mshr_s3_b & io_dirResp_s3_hit
+    & (task_s3_bits_chiOpcode != 7'h3 | task_s3_bits_snpHitReleaseToClean
+       & task_s3_bits_snpHitReleaseMeta_dirty)
+    & ~(_io_nestedwb_b_inv_dirty_T_3 | _io_nestedwb_b_inv_dirty_T_4)
+    & task_s3_bits_chiOpcode != 7'h10
+    & ((&io_metaOnHit_s3_state) | _metaW_valid_s3_b_T_17
+       & (_metaW_s3_b_T | _metaW_s3_b_T_1 | _metaW_s3_b_T_3 | _metaW_s3_b_T_5
+          | _metaW_s3_b_T_7 | _metaW_s3_b_T_9 | _metaW_s3_b_T_11 | _metaW_s3_b_T_12));
+  wire             metaW_valid_s3_c = sinkC_req_s3 & io_dirResp_s3_hit;
+  wire             _req_drop_s3_T_5 = mshr_refill_s3 & retry;
+  wire             metaW_valid_s3_mshr =
+    task_s3_bits_mshrTask & task_s3_bits_metaWen & ~_req_drop_s3_T_5;
+  wire             _metaW_s3_b_T_14 =
+    _metaW_s3_b_T | _metaW_s3_b_T_1 | _metaW_s3_b_T_3 | _metaW_s3_b_T_5 | _metaW_s3_b_T_7
+    | _metaW_s3_b_T_9 | _metaW_s3_b_T_11 | _metaW_s3_b_T_12;
+  assign metaW_s3_b_state =
+    _metaW_s3_b_T_14 ? 2'h0 : _metaW_s3_b_x11_T ? io_metaOnHit_s3_state : 2'h1;
+  assign metaW_s3_b_clients = ~_metaW_s3_b_T_14 & io_metaOnHit_s3_clients;
+  assign metaW_s3_b_alias = ~_metaW_s3_b_T_14 & io_metaOnHit_s3_alias;
+  assign metaW_s3_b_accessed = ~_metaW_s3_b_T_14 & io_metaOnHit_s3_accessed;
+  assign metaW_s3_b_tagErr = ~_metaW_s3_b_T_14 & io_metaOnHit_s3_tagErr;
+  assign metaW_s3_b_dataErr = ~_metaW_s3_b_T_14 & io_metaOnHit_s3_dataErr;
+  wire             _io_metaWReq_bits_wmeta_T = metaW_valid_s3_a | metaW_valid_s3_b;
+  wire             _GEN_5 = metaW_valid_s3_a | ~_metaW_s3_b_T_14;
+  wire             _GEN_6 = _io_metaWReq_bits_wmeta_T | metaW_valid_s3_c;
+  wire             chnl_fire_s3 =
+    _toSourceD_arb_io_in_2_ready & d_s3_valid | _toTXREQ_arb_io_in_2_ready
+    & txreq_s3_valid | _toTXRSP_arb_io_in_2_ready & txrsp_s3_valid
+    | _toTXDAT_arb_io_in_2_ready & txdat_s3_valid;
+  wire             req_drop_s3 =
+    ~need_write_releaseBuf & (~task_s3_bits_mshrTask & need_mshr_s3 | chnl_fire_s3)
+    | _req_drop_s3_T_5;
+  wire             isTXRSP_s3 =
+    task_s3_bits_mshrTask
+      ? mshr_snpRespX_s3
+      : task_s3_bits_channel[1] & ~need_mshr_s3_b & ~hasData_s3;
+  wire             _perfEvents_T_5 = mshr_snpRespDataX_s3 | mshr_cbWrData_s3;
+  wire             isTXREQ_s3 =
+    task_s3_bits_mshrTask
+    & (mshr_writeBackFull_s3 | mshr_writeCleanFull_s3 | mshr_writeEvictFull_s3
+       | mshr_writeEvictOrEvict_s3 | mshr_evict_s3);
+  assign txreq_s3_valid = task_s3_valid & isTXREQ_s3;
+  assign txrsp_s3_valid = task_s3_valid & isTXRSP_s3;
+  assign txdat_s3_valid =
+    task_s3_valid & task_s3_bits_mshrTask & (_perfEvents_T_5 | mshr_dct_s3);
+  assign d_s3_valid =
+    task_s3_valid
+    & (task_s3_bits_mshrTask
+         ? mshr_cmoresp_s3 | mshr_refill_s3 & ~retry
+         : task_s3_bits_channel[2]);
+  reg              task_s4_valid;
+  reg  [2:0]       task_s4_bits_channel;
+  reg  [2:0]       task_s4_bits_txChannel;
+  reg  [7:0]       task_s4_bits_set;
+  reg  [33:0]      task_s4_bits_tag;
+  reg  [5:0]       task_s4_bits_off;
+  reg              task_s4_bits_alias;
+  reg  [43:0]      task_s4_bits_vaddr;
+  reg              task_s4_bits_isKeyword;
+  reg  [3:0]       task_s4_bits_opcode;
+  reg  [2:0]       task_s4_bits_param;
+  reg  [2:0]       task_s4_bits_size;
+  reg  [6:0]       task_s4_bits_sourceId;
+  reg  [1:0]       task_s4_bits_bufIdx;
+  reg              task_s4_bits_needProbeAckData;
+  reg              task_s4_bits_denied;
+  reg              task_s4_bits_corrupt;
+  reg              task_s4_bits_mshrTask;
+  reg  [7:0]       task_s4_bits_mshrId;
+  reg              task_s4_bits_aliasTask;
+  reg              task_s4_bits_useProbeData;
+  reg              task_s4_bits_mshrRetry;
+  reg              task_s4_bits_readProbeDataDown;
+  reg              task_s4_bits_fromL2pft;
+  reg              task_s4_bits_needHint;
+  reg              task_s4_bits_dirty;
+  reg  [2:0]       task_s4_bits_way;
+  reg              task_s4_bits_meta_dirty;
+  reg  [1:0]       task_s4_bits_meta_state;
+  reg              task_s4_bits_meta_clients;
+  reg              task_s4_bits_meta_alias;
+  reg              task_s4_bits_meta_prefetch;
+  reg  [3:0]       task_s4_bits_meta_prefetchSrc;
+  reg              task_s4_bits_meta_accessed;
+  reg              task_s4_bits_meta_tagErr;
+  reg              task_s4_bits_meta_dataErr;
+  reg              task_s4_bits_metaWen;
+  reg              task_s4_bits_tagWen;
+  reg              task_s4_bits_dsWen;
+  reg  [7:0]       task_s4_bits_wayMask;
+  reg              task_s4_bits_replTask;
+  reg              task_s4_bits_cmoTask;
+  reg              task_s4_bits_cmoAll;
+  reg  [4:0]       task_s4_bits_reqSource;
+  reg              task_s4_bits_mergeA;
+  reg  [5:0]       task_s4_bits_aMergeTask_off;
+  reg              task_s4_bits_aMergeTask_alias;
+  reg  [43:0]      task_s4_bits_aMergeTask_vaddr;
+  reg              task_s4_bits_aMergeTask_isKeyword;
+  reg  [2:0]       task_s4_bits_aMergeTask_opcode;
+  reg  [2:0]       task_s4_bits_aMergeTask_param;
+  reg  [6:0]       task_s4_bits_aMergeTask_sourceId;
+  reg              task_s4_bits_aMergeTask_meta_dirty;
+  reg  [1:0]       task_s4_bits_aMergeTask_meta_state;
+  reg              task_s4_bits_aMergeTask_meta_clients;
+  reg              task_s4_bits_aMergeTask_meta_alias;
+  reg              task_s4_bits_aMergeTask_meta_prefetch;
+  reg  [3:0]       task_s4_bits_aMergeTask_meta_prefetchSrc;
+  reg              task_s4_bits_aMergeTask_meta_accessed;
+  reg              task_s4_bits_aMergeTask_meta_tagErr;
+  reg              task_s4_bits_aMergeTask_meta_dataErr;
+  reg              task_s4_bits_snpHitRelease;
+  reg              task_s4_bits_snpHitReleaseToInval;
+  reg              task_s4_bits_snpHitReleaseToClean;
+  reg              task_s4_bits_snpHitReleaseWithData;
+  reg  [7:0]       task_s4_bits_snpHitReleaseIdx;
+  reg              task_s4_bits_snpHitReleaseMeta_dirty;
+  reg  [1:0]       task_s4_bits_snpHitReleaseMeta_state;
+  reg              task_s4_bits_snpHitReleaseMeta_clients;
+  reg              task_s4_bits_snpHitReleaseMeta_alias;
+  reg              task_s4_bits_snpHitReleaseMeta_prefetch;
+  reg  [3:0]       task_s4_bits_snpHitReleaseMeta_prefetchSrc;
+  reg              task_s4_bits_snpHitReleaseMeta_accessed;
+  reg              task_s4_bits_snpHitReleaseMeta_tagErr;
+  reg              task_s4_bits_snpHitReleaseMeta_dataErr;
+  reg  [10:0]      task_s4_bits_tgtID;
+  reg  [10:0]      task_s4_bits_srcID;
+  reg  [11:0]      task_s4_bits_txnID;
+  reg  [10:0]      task_s4_bits_homeNID;
+  reg  [11:0]      task_s4_bits_dbID;
+  reg  [10:0]      task_s4_bits_fwdNID;
+  reg  [11:0]      task_s4_bits_fwdTxnID;
+  reg  [6:0]       task_s4_bits_chiOpcode;
+  reg  [2:0]       task_s4_bits_resp;
+  reg  [2:0]       task_s4_bits_fwdState;
+  reg  [3:0]       task_s4_bits_pCrdType;
+  reg              task_s4_bits_retToSrc;
+  reg              task_s4_bits_likelyshared;
+  reg              task_s4_bits_expCompAck;
+  reg              task_s4_bits_allowRetry;
+  reg              task_s4_bits_memAttr_allocate;
+  reg              task_s4_bits_memAttr_cacheable;
+  reg              task_s4_bits_memAttr_device;
+  reg              task_s4_bits_memAttr_ewa;
+  reg              task_s4_bits_traceTag;
+  reg  [511:0]     data_s4;
+  reg              need_write_releaseBuf_s4;
+  reg              isD_s4;
+  reg              isTXREQ_s4;
+  reg              isTXRSP_s4;
+  reg              isTXDAT_s4;
+  reg              tagError_s4;
+  reg              dataError_s4;
+  reg              l2Error_s4;
+  wire             _d_s4_valid_map_bits_T = task_s4_bits_opcode == 4'h4;
+  wire             pendingD_s4 =
+    task_s4_bits_channel[0] & ~task_s4_bits_mshrTask & ~need_write_releaseBuf_s4
+    & (task_s4_bits_opcode == 4'h5 | _d_s4_valid_map_bits_T
+       | task_s4_bits_opcode == 4'h1);
+  wire             _GEN_7 = task_s3_valid & ~req_drop_s3;
+  wire             chnl_fire_s4 =
+    _toSourceD_arb_io_in_1_ready & d_s4_valid | _toTXREQ_arb_io_in_1_ready
+    & txreq_s4_valid | _toTXRSP_arb_io_in_1_ready & txrsp_s4_valid
+    | _toTXDAT_arb_io_in_1_ready & txdat_s4_valid;
+  wire             req_drop_s4 = ~need_write_releaseBuf_s4 & chnl_fire_s4;
+  reg              chnl_valid_s4_REG;
+  wire             chnl_valid_s4 = task_s4_valid & ~chnl_valid_s4_REG;
+  assign d_s4_valid =
+    chnl_valid_s4 & isD_s4
+    & ~(_d_s4_valid_map_bits_T & task_s4_bits_channel[0] & ~task_s4_bits_mshrTask
+        & ~need_write_releaseBuf_s4);
+  assign txreq_s4_valid = chnl_valid_s4 & isTXREQ_s4;
+  assign txrsp_s4_valid = chnl_valid_s4 & isTXRSP_s4;
+  assign txdat_s4_valid = chnl_valid_s4 & isTXDAT_s4;
+  reg              task_s5_valid;
+  reg  [2:0]       task_s5_bits_channel;
+  reg  [2:0]       task_s5_bits_txChannel;
+  reg  [7:0]       task_s5_bits_set;
+  reg  [33:0]      task_s5_bits_tag;
+  reg  [5:0]       task_s5_bits_off;
+  reg              task_s5_bits_alias;
+  reg  [43:0]      task_s5_bits_vaddr;
+  reg              task_s5_bits_isKeyword;
+  reg  [3:0]       task_s5_bits_opcode;
+  reg  [2:0]       task_s5_bits_param;
+  reg  [2:0]       task_s5_bits_size;
+  reg  [6:0]       task_s5_bits_sourceId;
+  reg  [1:0]       task_s5_bits_bufIdx;
+  reg              task_s5_bits_needProbeAckData;
+  reg              task_s5_bits_denied;
+  reg              task_s5_bits_corrupt;
+  reg              task_s5_bits_mshrTask;
+  reg  [7:0]       task_s5_bits_mshrId;
+  reg              task_s5_bits_aliasTask;
+  reg              task_s5_bits_useProbeData;
+  reg              task_s5_bits_mshrRetry;
+  reg              task_s5_bits_readProbeDataDown;
+  reg              task_s5_bits_fromL2pft;
+  reg              task_s5_bits_needHint;
+  reg              task_s5_bits_dirty;
+  reg  [2:0]       task_s5_bits_way;
+  reg              task_s5_bits_meta_dirty;
+  reg  [1:0]       task_s5_bits_meta_state;
+  reg              task_s5_bits_meta_clients;
+  reg              task_s5_bits_meta_alias;
+  reg              task_s5_bits_meta_prefetch;
+  reg  [3:0]       task_s5_bits_meta_prefetchSrc;
+  reg              task_s5_bits_meta_accessed;
+  reg              task_s5_bits_meta_tagErr;
+  reg              task_s5_bits_meta_dataErr;
+  reg              task_s5_bits_metaWen;
+  reg              task_s5_bits_tagWen;
+  reg              task_s5_bits_dsWen;
+  reg  [7:0]       task_s5_bits_wayMask;
+  reg              task_s5_bits_replTask;
+  reg              task_s5_bits_cmoTask;
+  reg              task_s5_bits_cmoAll;
+  reg  [4:0]       task_s5_bits_reqSource;
+  reg              task_s5_bits_mergeA;
+  reg  [5:0]       task_s5_bits_aMergeTask_off;
+  reg              task_s5_bits_aMergeTask_alias;
+  reg  [43:0]      task_s5_bits_aMergeTask_vaddr;
+  reg              task_s5_bits_aMergeTask_isKeyword;
+  reg  [2:0]       task_s5_bits_aMergeTask_opcode;
+  reg  [2:0]       task_s5_bits_aMergeTask_param;
+  reg  [6:0]       task_s5_bits_aMergeTask_sourceId;
+  reg              task_s5_bits_aMergeTask_meta_dirty;
+  reg  [1:0]       task_s5_bits_aMergeTask_meta_state;
+  reg              task_s5_bits_aMergeTask_meta_clients;
+  reg              task_s5_bits_aMergeTask_meta_alias;
+  reg              task_s5_bits_aMergeTask_meta_prefetch;
+  reg  [3:0]       task_s5_bits_aMergeTask_meta_prefetchSrc;
+  reg              task_s5_bits_aMergeTask_meta_accessed;
+  reg              task_s5_bits_aMergeTask_meta_tagErr;
+  reg              task_s5_bits_aMergeTask_meta_dataErr;
+  reg              task_s5_bits_snpHitRelease;
+  reg              task_s5_bits_snpHitReleaseToInval;
+  reg              task_s5_bits_snpHitReleaseToClean;
+  reg              task_s5_bits_snpHitReleaseWithData;
+  reg  [7:0]       task_s5_bits_snpHitReleaseIdx;
+  reg              task_s5_bits_snpHitReleaseMeta_dirty;
+  reg  [1:0]       task_s5_bits_snpHitReleaseMeta_state;
+  reg              task_s5_bits_snpHitReleaseMeta_clients;
+  reg              task_s5_bits_snpHitReleaseMeta_alias;
+  reg              task_s5_bits_snpHitReleaseMeta_prefetch;
+  reg  [3:0]       task_s5_bits_snpHitReleaseMeta_prefetchSrc;
+  reg              task_s5_bits_snpHitReleaseMeta_accessed;
+  reg              task_s5_bits_snpHitReleaseMeta_tagErr;
+  reg              task_s5_bits_snpHitReleaseMeta_dataErr;
+  reg  [10:0]      task_s5_bits_tgtID;
+  reg  [10:0]      task_s5_bits_srcID;
+  reg  [11:0]      task_s5_bits_txnID;
+  reg  [10:0]      task_s5_bits_homeNID;
+  reg  [11:0]      task_s5_bits_dbID;
+  reg  [10:0]      task_s5_bits_fwdNID;
+  reg  [11:0]      task_s5_bits_fwdTxnID;
+  reg  [6:0]       task_s5_bits_chiOpcode;
+  reg  [2:0]       task_s5_bits_resp;
+  reg  [2:0]       task_s5_bits_fwdState;
+  reg  [3:0]       task_s5_bits_pCrdType;
+  reg              task_s5_bits_retToSrc;
+  reg              task_s5_bits_likelyshared;
+  reg              task_s5_bits_expCompAck;
+  reg              task_s5_bits_allowRetry;
+  reg              task_s5_bits_memAttr_allocate;
+  reg              task_s5_bits_memAttr_cacheable;
+  reg              task_s5_bits_memAttr_device;
+  reg              task_s5_bits_memAttr_ewa;
+  reg              task_s5_bits_traceTag;
+  reg  [511:0]     data_s5;
+  reg              need_write_releaseBuf_s5;
+  reg              isD_s5;
+  reg              isTXREQ_s5;
+  reg              isTXRSP_s5;
+  reg              isTXDAT_s5;
+  reg              tagError_s5;
+  reg              dataMetaError_s5;
+  reg              l2TagError_s5;
+  wire             _GEN_8 = task_s4_valid & ~req_drop_s4;
+  wire             dataError_s5 = io_toDS_error_s5 | dataMetaError_s5;
+  wire             _d_s5_bits_task_corrupt_T =
+    task_s5_bits_mshrTask | task_s5_bits_snpHitReleaseWithData;
+  wire [511:0]     out_data_s5 =
+    _d_s5_bits_task_corrupt_T ? data_s5 : io_toDS_rdata_s5_data;
+  reg              chnl_valid_s5_REG;
+  reg              chnl_valid_s5_REG_1;
+  reg              chnl_valid_s5_REG_2;
+  wire             chnl_valid_s5 =
+    task_s5_valid & ~chnl_valid_s5_REG & ~chnl_valid_s5_REG_2;
+  wire             d_s5_valid = chnl_valid_s5 & isD_s5;
+  wire             alloc_state_w_grant = ~(task_s3_bits_channel[0]) | ~need_acquire_s3_a;
+  wire             alloc_state_s_rprobe =
+    ~(task_s3_bits_channel[0]) | ~_need_write_releaseBuf_T;
+  wire             alloc_state_s_release =
+    ~(task_s3_bits_channel[0])
+    | ~(io_dirResp_s3_hit
+        & (req_cbo_clean_s3 & ~need_probe_s3_a & io_metaOnHit_s3_dirty | req_cbo_flush_s3
+           & (|io_metaOnHit_s3_state) | req_cbo_inval_s3 & (|io_metaOnHit_s3_state)));
+  wire             alloc_state_s_pprobe = ~(task_s3_bits_channel[1]) | ~need_pprobe_s3_b;
+  reg              io_perf_0_value_REG;
+  reg              io_perf_0_value_REG_1;
+  reg              io_perf_1_value_REG;
+  reg              io_perf_1_value_REG_1;
+  reg              io_perf_2_value_REG;
+  reg              io_perf_2_value_REG_1;
+  reg              io_perf_3_value_REG;
+  reg              io_perf_3_value_REG_1;
+  reg              io_perf_4_value_REG;
+  reg              io_perf_4_value_REG_1;
+  reg              io_perf_5_value_REG;
+  reg              io_perf_5_value_REG_1;
+  reg              io_perf_6_value_REG;
+  reg              io_perf_6_value_REG_1;
+  reg              io_perf_7_value_REG;
+  reg              io_perf_7_value_REG_1;
+  reg              io_perf_8_value_REG;
+  reg              io_perf_8_value_REG_1;
+  reg              io_perf_9_value_REG;
+  reg              io_perf_9_value_REG_1;
+  reg              io_perf_10_value_REG;
+  reg              io_perf_10_value_REG_1;
+  reg              io_perf_11_value_REG;
+  reg              io_perf_11_value_REG_1;
+  reg              io_perf_12_value_REG;
+  reg              io_perf_12_value_REG_1;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      resetFinish <= 1'h0;
+      resetIdx <= 8'hFF;
+      task_s3_valid <= 1'h0;
+      task_s3_bits_channel <= 3'h0;
+      task_s3_bits_txChannel <= 3'h0;
+      task_s3_bits_set <= 8'h0;
+      task_s3_bits_tag <= 34'h0;
+      task_s3_bits_off <= 6'h0;
+      task_s3_bits_alias <= 1'h0;
+      task_s3_bits_vaddr <= 44'h0;
+      task_s3_bits_isKeyword <= 1'h0;
+      task_s3_bits_opcode <= 4'h0;
+      task_s3_bits_param <= 3'h0;
+      task_s3_bits_size <= 3'h0;
+      task_s3_bits_sourceId <= 7'h0;
+      task_s3_bits_bufIdx <= 2'h0;
+      task_s3_bits_needProbeAckData <= 1'h0;
+      task_s3_bits_denied <= 1'h0;
+      task_s3_bits_corrupt <= 1'h0;
+      task_s3_bits_mshrTask <= 1'h0;
+      task_s3_bits_mshrId <= 8'h0;
+      task_s3_bits_aliasTask <= 1'h0;
+      task_s3_bits_useProbeData <= 1'h0;
+      task_s3_bits_mshrRetry <= 1'h0;
+      task_s3_bits_readProbeDataDown <= 1'h0;
+      task_s3_bits_fromL2pft <= 1'h0;
+      task_s3_bits_needHint <= 1'h0;
+      task_s3_bits_dirty <= 1'h0;
+      task_s3_bits_way <= 3'h0;
+      task_s3_bits_meta_dirty <= 1'h0;
+      task_s3_bits_meta_state <= 2'h0;
+      task_s3_bits_meta_clients <= 1'h0;
+      task_s3_bits_meta_alias <= 1'h0;
+      task_s3_bits_meta_prefetch <= 1'h0;
+      task_s3_bits_meta_prefetchSrc <= 4'h0;
+      task_s3_bits_meta_accessed <= 1'h0;
+      task_s3_bits_meta_tagErr <= 1'h0;
+      task_s3_bits_meta_dataErr <= 1'h0;
+      task_s3_bits_metaWen <= 1'h0;
+      task_s3_bits_tagWen <= 1'h0;
+      task_s3_bits_dsWen <= 1'h0;
+      task_s3_bits_wayMask <= 8'h0;
+      task_s3_bits_replTask <= 1'h0;
+      task_s3_bits_cmoTask <= 1'h0;
+      task_s3_bits_cmoAll <= 1'h0;
+      task_s3_bits_reqSource <= 5'h0;
+      task_s3_bits_mergeA <= 1'h0;
+      task_s3_bits_aMergeTask_off <= 6'h0;
+      task_s3_bits_aMergeTask_alias <= 1'h0;
+      task_s3_bits_aMergeTask_vaddr <= 44'h0;
+      task_s3_bits_aMergeTask_isKeyword <= 1'h0;
+      task_s3_bits_aMergeTask_opcode <= 3'h0;
+      task_s3_bits_aMergeTask_param <= 3'h0;
+      task_s3_bits_aMergeTask_sourceId <= 7'h0;
+      task_s3_bits_aMergeTask_meta_dirty <= 1'h0;
+      task_s3_bits_aMergeTask_meta_state <= 2'h0;
+      task_s3_bits_aMergeTask_meta_clients <= 1'h0;
+      task_s3_bits_aMergeTask_meta_alias <= 1'h0;
+      task_s3_bits_aMergeTask_meta_prefetch <= 1'h0;
+      task_s3_bits_aMergeTask_meta_prefetchSrc <= 4'h0;
+      task_s3_bits_aMergeTask_meta_accessed <= 1'h0;
+      task_s3_bits_aMergeTask_meta_tagErr <= 1'h0;
+      task_s3_bits_aMergeTask_meta_dataErr <= 1'h0;
+      task_s3_bits_snpHitRelease <= 1'h0;
+      task_s3_bits_snpHitReleaseToInval <= 1'h0;
+      task_s3_bits_snpHitReleaseToClean <= 1'h0;
+      task_s3_bits_snpHitReleaseWithData <= 1'h0;
+      task_s3_bits_snpHitReleaseIdx <= 8'h0;
+      task_s3_bits_snpHitReleaseMeta_dirty <= 1'h0;
+      task_s3_bits_snpHitReleaseMeta_state <= 2'h0;
+      task_s3_bits_snpHitReleaseMeta_clients <= 1'h0;
+      task_s3_bits_snpHitReleaseMeta_alias <= 1'h0;
+      task_s3_bits_snpHitReleaseMeta_prefetch <= 1'h0;
+      task_s3_bits_snpHitReleaseMeta_prefetchSrc <= 4'h0;
+      task_s3_bits_snpHitReleaseMeta_accessed <= 1'h0;
+      task_s3_bits_snpHitReleaseMeta_tagErr <= 1'h0;
+      task_s3_bits_snpHitReleaseMeta_dataErr <= 1'h0;
+      task_s3_bits_tgtID <= 11'h0;
+      task_s3_bits_srcID <= 11'h0;
+      task_s3_bits_txnID <= 12'h0;
+      task_s3_bits_homeNID <= 11'h0;
+      task_s3_bits_dbID <= 12'h0;
+      task_s3_bits_fwdNID <= 11'h0;
+      task_s3_bits_fwdTxnID <= 12'h0;
+      task_s3_bits_chiOpcode <= 7'h0;
+      task_s3_bits_resp <= 3'h0;
+      task_s3_bits_fwdState <= 3'h0;
+      task_s3_bits_pCrdType <= 4'h0;
+      task_s3_bits_retToSrc <= 1'h0;
+      task_s3_bits_likelyshared <= 1'h0;
+      task_s3_bits_expCompAck <= 1'h0;
+      task_s3_bits_allowRetry <= 1'h0;
+      task_s3_bits_memAttr_allocate <= 1'h0;
+      task_s3_bits_memAttr_cacheable <= 1'h0;
+      task_s3_bits_memAttr_device <= 1'h0;
+      task_s3_bits_memAttr_ewa <= 1'h0;
+      task_s3_bits_traceTag <= 1'h0;
+      task_s3_valid_hold2_REG <= 1'h0;
+      task_s3_valid_hold2 <= 1'h0;
+      task_s4_valid <= 1'h0;
+      task_s4_bits_channel <= 3'h0;
+      task_s4_bits_txChannel <= 3'h0;
+      task_s4_bits_set <= 8'h0;
+      task_s4_bits_tag <= 34'h0;
+      task_s4_bits_off <= 6'h0;
+      task_s4_bits_alias <= 1'h0;
+      task_s4_bits_vaddr <= 44'h0;
+      task_s4_bits_isKeyword <= 1'h0;
+      task_s4_bits_opcode <= 4'h0;
+      task_s4_bits_param <= 3'h0;
+      task_s4_bits_size <= 3'h0;
+      task_s4_bits_sourceId <= 7'h0;
+      task_s4_bits_bufIdx <= 2'h0;
+      task_s4_bits_needProbeAckData <= 1'h0;
+      task_s4_bits_denied <= 1'h0;
+      task_s4_bits_corrupt <= 1'h0;
+      task_s4_bits_mshrTask <= 1'h0;
+      task_s4_bits_mshrId <= 8'h0;
+      task_s4_bits_aliasTask <= 1'h0;
+      task_s4_bits_useProbeData <= 1'h0;
+      task_s4_bits_mshrRetry <= 1'h0;
+      task_s4_bits_readProbeDataDown <= 1'h0;
+      task_s4_bits_fromL2pft <= 1'h0;
+      task_s4_bits_needHint <= 1'h0;
+      task_s4_bits_dirty <= 1'h0;
+      task_s4_bits_way <= 3'h0;
+      task_s4_bits_meta_dirty <= 1'h0;
+      task_s4_bits_meta_state <= 2'h0;
+      task_s4_bits_meta_clients <= 1'h0;
+      task_s4_bits_meta_alias <= 1'h0;
+      task_s4_bits_meta_prefetch <= 1'h0;
+      task_s4_bits_meta_prefetchSrc <= 4'h0;
+      task_s4_bits_meta_accessed <= 1'h0;
+      task_s4_bits_meta_tagErr <= 1'h0;
+      task_s4_bits_meta_dataErr <= 1'h0;
+      task_s4_bits_metaWen <= 1'h0;
+      task_s4_bits_tagWen <= 1'h0;
+      task_s4_bits_dsWen <= 1'h0;
+      task_s4_bits_wayMask <= 8'h0;
+      task_s4_bits_replTask <= 1'h0;
+      task_s4_bits_cmoTask <= 1'h0;
+      task_s4_bits_cmoAll <= 1'h0;
+      task_s4_bits_reqSource <= 5'h0;
+      task_s4_bits_mergeA <= 1'h0;
+      task_s4_bits_aMergeTask_off <= 6'h0;
+      task_s4_bits_aMergeTask_alias <= 1'h0;
+      task_s4_bits_aMergeTask_vaddr <= 44'h0;
+      task_s4_bits_aMergeTask_isKeyword <= 1'h0;
+      task_s4_bits_aMergeTask_opcode <= 3'h0;
+      task_s4_bits_aMergeTask_param <= 3'h0;
+      task_s4_bits_aMergeTask_sourceId <= 7'h0;
+      task_s4_bits_aMergeTask_meta_dirty <= 1'h0;
+      task_s4_bits_aMergeTask_meta_state <= 2'h0;
+      task_s4_bits_aMergeTask_meta_clients <= 1'h0;
+      task_s4_bits_aMergeTask_meta_alias <= 1'h0;
+      task_s4_bits_aMergeTask_meta_prefetch <= 1'h0;
+      task_s4_bits_aMergeTask_meta_prefetchSrc <= 4'h0;
+      task_s4_bits_aMergeTask_meta_accessed <= 1'h0;
+      task_s4_bits_aMergeTask_meta_tagErr <= 1'h0;
+      task_s4_bits_aMergeTask_meta_dataErr <= 1'h0;
+      task_s4_bits_snpHitRelease <= 1'h0;
+      task_s4_bits_snpHitReleaseToInval <= 1'h0;
+      task_s4_bits_snpHitReleaseToClean <= 1'h0;
+      task_s4_bits_snpHitReleaseWithData <= 1'h0;
+      task_s4_bits_snpHitReleaseIdx <= 8'h0;
+      task_s4_bits_snpHitReleaseMeta_dirty <= 1'h0;
+      task_s4_bits_snpHitReleaseMeta_state <= 2'h0;
+      task_s4_bits_snpHitReleaseMeta_clients <= 1'h0;
+      task_s4_bits_snpHitReleaseMeta_alias <= 1'h0;
+      task_s4_bits_snpHitReleaseMeta_prefetch <= 1'h0;
+      task_s4_bits_snpHitReleaseMeta_prefetchSrc <= 4'h0;
+      task_s4_bits_snpHitReleaseMeta_accessed <= 1'h0;
+      task_s4_bits_snpHitReleaseMeta_tagErr <= 1'h0;
+      task_s4_bits_snpHitReleaseMeta_dataErr <= 1'h0;
+      task_s4_bits_tgtID <= 11'h0;
+      task_s4_bits_srcID <= 11'h0;
+      task_s4_bits_txnID <= 12'h0;
+      task_s4_bits_homeNID <= 11'h0;
+      task_s4_bits_dbID <= 12'h0;
+      task_s4_bits_fwdNID <= 11'h0;
+      task_s4_bits_fwdTxnID <= 12'h0;
+      task_s4_bits_chiOpcode <= 7'h0;
+      task_s4_bits_resp <= 3'h0;
+      task_s4_bits_fwdState <= 3'h0;
+      task_s4_bits_pCrdType <= 4'h0;
+      task_s4_bits_retToSrc <= 1'h0;
+      task_s4_bits_likelyshared <= 1'h0;
+      task_s4_bits_expCompAck <= 1'h0;
+      task_s4_bits_allowRetry <= 1'h0;
+      task_s4_bits_memAttr_allocate <= 1'h0;
+      task_s4_bits_memAttr_cacheable <= 1'h0;
+      task_s4_bits_memAttr_device <= 1'h0;
+      task_s4_bits_memAttr_ewa <= 1'h0;
+      task_s4_bits_traceTag <= 1'h0;
+      need_write_releaseBuf_s4 <= 1'h0;
+      isD_s4 <= 1'h0;
+      isTXREQ_s4 <= 1'h0;
+      isTXRSP_s4 <= 1'h0;
+      isTXDAT_s4 <= 1'h0;
+      tagError_s4 <= 1'h0;
+      dataError_s4 <= 1'h0;
+      l2Error_s4 <= 1'h0;
+      chnl_valid_s4_REG <= 1'h0;
+      task_s5_valid <= 1'h0;
+      task_s5_bits_channel <= 3'h0;
+      task_s5_bits_txChannel <= 3'h0;
+      task_s5_bits_set <= 8'h0;
+      task_s5_bits_tag <= 34'h0;
+      task_s5_bits_off <= 6'h0;
+      task_s5_bits_alias <= 1'h0;
+      task_s5_bits_vaddr <= 44'h0;
+      task_s5_bits_isKeyword <= 1'h0;
+      task_s5_bits_opcode <= 4'h0;
+      task_s5_bits_param <= 3'h0;
+      task_s5_bits_size <= 3'h0;
+      task_s5_bits_sourceId <= 7'h0;
+      task_s5_bits_bufIdx <= 2'h0;
+      task_s5_bits_needProbeAckData <= 1'h0;
+      task_s5_bits_denied <= 1'h0;
+      task_s5_bits_corrupt <= 1'h0;
+      task_s5_bits_mshrTask <= 1'h0;
+      task_s5_bits_mshrId <= 8'h0;
+      task_s5_bits_aliasTask <= 1'h0;
+      task_s5_bits_useProbeData <= 1'h0;
+      task_s5_bits_mshrRetry <= 1'h0;
+      task_s5_bits_readProbeDataDown <= 1'h0;
+      task_s5_bits_fromL2pft <= 1'h0;
+      task_s5_bits_needHint <= 1'h0;
+      task_s5_bits_dirty <= 1'h0;
+      task_s5_bits_way <= 3'h0;
+      task_s5_bits_meta_dirty <= 1'h0;
+      task_s5_bits_meta_state <= 2'h0;
+      task_s5_bits_meta_clients <= 1'h0;
+      task_s5_bits_meta_alias <= 1'h0;
+      task_s5_bits_meta_prefetch <= 1'h0;
+      task_s5_bits_meta_prefetchSrc <= 4'h0;
+      task_s5_bits_meta_accessed <= 1'h0;
+      task_s5_bits_meta_tagErr <= 1'h0;
+      task_s5_bits_meta_dataErr <= 1'h0;
+      task_s5_bits_metaWen <= 1'h0;
+      task_s5_bits_tagWen <= 1'h0;
+      task_s5_bits_dsWen <= 1'h0;
+      task_s5_bits_wayMask <= 8'h0;
+      task_s5_bits_replTask <= 1'h0;
+      task_s5_bits_cmoTask <= 1'h0;
+      task_s5_bits_cmoAll <= 1'h0;
+      task_s5_bits_reqSource <= 5'h0;
+      task_s5_bits_mergeA <= 1'h0;
+      task_s5_bits_aMergeTask_off <= 6'h0;
+      task_s5_bits_aMergeTask_alias <= 1'h0;
+      task_s5_bits_aMergeTask_vaddr <= 44'h0;
+      task_s5_bits_aMergeTask_isKeyword <= 1'h0;
+      task_s5_bits_aMergeTask_opcode <= 3'h0;
+      task_s5_bits_aMergeTask_param <= 3'h0;
+      task_s5_bits_aMergeTask_sourceId <= 7'h0;
+      task_s5_bits_aMergeTask_meta_dirty <= 1'h0;
+      task_s5_bits_aMergeTask_meta_state <= 2'h0;
+      task_s5_bits_aMergeTask_meta_clients <= 1'h0;
+      task_s5_bits_aMergeTask_meta_alias <= 1'h0;
+      task_s5_bits_aMergeTask_meta_prefetch <= 1'h0;
+      task_s5_bits_aMergeTask_meta_prefetchSrc <= 4'h0;
+      task_s5_bits_aMergeTask_meta_accessed <= 1'h0;
+      task_s5_bits_aMergeTask_meta_tagErr <= 1'h0;
+      task_s5_bits_aMergeTask_meta_dataErr <= 1'h0;
+      task_s5_bits_snpHitRelease <= 1'h0;
+      task_s5_bits_snpHitReleaseToInval <= 1'h0;
+      task_s5_bits_snpHitReleaseToClean <= 1'h0;
+      task_s5_bits_snpHitReleaseWithData <= 1'h0;
+      task_s5_bits_snpHitReleaseIdx <= 8'h0;
+      task_s5_bits_snpHitReleaseMeta_dirty <= 1'h0;
+      task_s5_bits_snpHitReleaseMeta_state <= 2'h0;
+      task_s5_bits_snpHitReleaseMeta_clients <= 1'h0;
+      task_s5_bits_snpHitReleaseMeta_alias <= 1'h0;
+      task_s5_bits_snpHitReleaseMeta_prefetch <= 1'h0;
+      task_s5_bits_snpHitReleaseMeta_prefetchSrc <= 4'h0;
+      task_s5_bits_snpHitReleaseMeta_accessed <= 1'h0;
+      task_s5_bits_snpHitReleaseMeta_tagErr <= 1'h0;
+      task_s5_bits_snpHitReleaseMeta_dataErr <= 1'h0;
+      task_s5_bits_tgtID <= 11'h0;
+      task_s5_bits_srcID <= 11'h0;
+      task_s5_bits_txnID <= 12'h0;
+      task_s5_bits_homeNID <= 11'h0;
+      task_s5_bits_dbID <= 12'h0;
+      task_s5_bits_fwdNID <= 11'h0;
+      task_s5_bits_fwdTxnID <= 12'h0;
+      task_s5_bits_chiOpcode <= 7'h0;
+      task_s5_bits_resp <= 3'h0;
+      task_s5_bits_fwdState <= 3'h0;
+      task_s5_bits_pCrdType <= 4'h0;
+      task_s5_bits_retToSrc <= 1'h0;
+      task_s5_bits_likelyshared <= 1'h0;
+      task_s5_bits_expCompAck <= 1'h0;
+      task_s5_bits_allowRetry <= 1'h0;
+      task_s5_bits_memAttr_allocate <= 1'h0;
+      task_s5_bits_memAttr_cacheable <= 1'h0;
+      task_s5_bits_memAttr_device <= 1'h0;
+      task_s5_bits_memAttr_ewa <= 1'h0;
+      task_s5_bits_traceTag <= 1'h0;
+      need_write_releaseBuf_s5 <= 1'h0;
+      isD_s5 <= 1'h0;
+      isTXREQ_s5 <= 1'h0;
+      isTXRSP_s5 <= 1'h0;
+      isTXDAT_s5 <= 1'h0;
+      tagError_s5 <= 1'h0;
+      dataMetaError_s5 <= 1'h0;
+      l2TagError_s5 <= 1'h0;
+      chnl_valid_s5_REG <= 1'h0;
+      chnl_valid_s5_REG_1 <= 1'h0;
+      chnl_valid_s5_REG_2 <= 1'h0;
+    end
+    else begin
+      resetFinish <= resetIdx == 8'h0 | resetFinish;
+      if (resetFinish) begin
+      end
+      else
+        resetIdx <= 8'(resetIdx - 8'h1);
+      task_s3_valid <= io_taskFromArb_s2_valid;
+      if (io_taskFromArb_s2_valid) begin
+        task_s3_bits_channel <= io_taskFromArb_s2_bits_channel;
+        task_s3_bits_txChannel <= io_taskFromArb_s2_bits_txChannel;
+        task_s3_bits_set <= io_taskFromArb_s2_bits_set;
+        task_s3_bits_tag <= io_taskFromArb_s2_bits_tag;
+        task_s3_bits_off <= io_taskFromArb_s2_bits_off;
+        task_s3_bits_alias <= io_taskFromArb_s2_bits_alias;
+        task_s3_bits_vaddr <= io_taskFromArb_s2_bits_vaddr;
+        task_s3_bits_isKeyword <= io_taskFromArb_s2_bits_isKeyword;
+        task_s3_bits_opcode <= io_taskFromArb_s2_bits_opcode;
+        task_s3_bits_param <= io_taskFromArb_s2_bits_param;
+        task_s3_bits_size <= io_taskFromArb_s2_bits_size;
+        task_s3_bits_sourceId <= io_taskFromArb_s2_bits_sourceId;
+        task_s3_bits_bufIdx <= io_taskFromArb_s2_bits_bufIdx;
+        task_s3_bits_needProbeAckData <= io_taskFromArb_s2_bits_needProbeAckData;
+        task_s3_bits_denied <= io_taskFromArb_s2_bits_denied;
+        task_s3_bits_corrupt <= io_taskFromArb_s2_bits_corrupt;
+        task_s3_bits_mshrTask <= io_taskFromArb_s2_bits_mshrTask;
+        task_s3_bits_mshrId <= io_taskFromArb_s2_bits_mshrId;
+        task_s3_bits_aliasTask <= io_taskFromArb_s2_bits_aliasTask;
+        task_s3_bits_useProbeData <= io_taskFromArb_s2_bits_useProbeData;
+        task_s3_bits_mshrRetry <= io_taskFromArb_s2_bits_mshrRetry;
+        task_s3_bits_readProbeDataDown <= io_taskFromArb_s2_bits_readProbeDataDown;
+        task_s3_bits_fromL2pft <= io_taskFromArb_s2_bits_fromL2pft;
+        task_s3_bits_needHint <= io_taskFromArb_s2_bits_needHint;
+        task_s3_bits_dirty <= io_taskFromArb_s2_bits_dirty;
+        task_s3_bits_way <= io_taskFromArb_s2_bits_way;
+        task_s3_bits_meta_dirty <= io_taskFromArb_s2_bits_meta_dirty;
+        task_s3_bits_meta_state <= io_taskFromArb_s2_bits_meta_state;
+        task_s3_bits_meta_clients <= io_taskFromArb_s2_bits_meta_clients;
+        task_s3_bits_meta_alias <= io_taskFromArb_s2_bits_meta_alias;
+        task_s3_bits_meta_prefetch <= io_taskFromArb_s2_bits_meta_prefetch;
+        task_s3_bits_meta_prefetchSrc <= io_taskFromArb_s2_bits_meta_prefetchSrc;
+        task_s3_bits_meta_accessed <= io_taskFromArb_s2_bits_meta_accessed;
+        task_s3_bits_meta_tagErr <= io_taskFromArb_s2_bits_meta_tagErr;
+        task_s3_bits_meta_dataErr <= io_taskFromArb_s2_bits_meta_dataErr;
+        task_s3_bits_metaWen <= io_taskFromArb_s2_bits_metaWen;
+        task_s3_bits_tagWen <= io_taskFromArb_s2_bits_tagWen;
+        task_s3_bits_dsWen <= io_taskFromArb_s2_bits_dsWen;
+        task_s3_bits_wayMask <= io_taskFromArb_s2_bits_wayMask;
+        task_s3_bits_replTask <= io_taskFromArb_s2_bits_replTask;
+        task_s3_bits_cmoTask <= io_taskFromArb_s2_bits_cmoTask;
+        task_s3_bits_cmoAll <= io_taskFromArb_s2_bits_cmoAll;
+        task_s3_bits_reqSource <= io_taskFromArb_s2_bits_reqSource;
+        task_s3_bits_mergeA <= io_taskFromArb_s2_bits_mergeA;
+        task_s3_bits_aMergeTask_off <= io_taskFromArb_s2_bits_aMergeTask_off;
+        task_s3_bits_aMergeTask_alias <= io_taskFromArb_s2_bits_aMergeTask_alias;
+        task_s3_bits_aMergeTask_vaddr <= io_taskFromArb_s2_bits_aMergeTask_vaddr;
+        task_s3_bits_aMergeTask_isKeyword <= io_taskFromArb_s2_bits_aMergeTask_isKeyword;
+        task_s3_bits_aMergeTask_opcode <= io_taskFromArb_s2_bits_aMergeTask_opcode;
+        task_s3_bits_aMergeTask_param <= io_taskFromArb_s2_bits_aMergeTask_param;
+        task_s3_bits_aMergeTask_sourceId <= io_taskFromArb_s2_bits_aMergeTask_sourceId;
+        task_s3_bits_aMergeTask_meta_dirty <=
+          io_taskFromArb_s2_bits_aMergeTask_meta_dirty;
+        task_s3_bits_aMergeTask_meta_state <=
+          io_taskFromArb_s2_bits_aMergeTask_meta_state;
+        task_s3_bits_aMergeTask_meta_clients <=
+          io_taskFromArb_s2_bits_aMergeTask_meta_clients;
+        task_s3_bits_aMergeTask_meta_alias <=
+          io_taskFromArb_s2_bits_aMergeTask_meta_alias;
+        task_s3_bits_aMergeTask_meta_prefetch <=
+          io_taskFromArb_s2_bits_aMergeTask_meta_prefetch;
+        task_s3_bits_aMergeTask_meta_prefetchSrc <=
+          io_taskFromArb_s2_bits_aMergeTask_meta_prefetchSrc;
+        task_s3_bits_aMergeTask_meta_accessed <=
+          io_taskFromArb_s2_bits_aMergeTask_meta_accessed;
+        task_s3_bits_aMergeTask_meta_tagErr <=
+          io_taskFromArb_s2_bits_aMergeTask_meta_tagErr;
+        task_s3_bits_aMergeTask_meta_dataErr <=
+          io_taskFromArb_s2_bits_aMergeTask_meta_dataErr;
+        task_s3_bits_snpHitRelease <= io_taskFromArb_s2_bits_snpHitRelease;
+        task_s3_bits_snpHitReleaseToInval <= io_taskFromArb_s2_bits_snpHitReleaseToInval;
+        task_s3_bits_snpHitReleaseToClean <= io_taskFromArb_s2_bits_snpHitReleaseToClean;
+        task_s3_bits_snpHitReleaseWithData <=
+          io_taskFromArb_s2_bits_snpHitReleaseWithData;
+        task_s3_bits_snpHitReleaseIdx <= io_taskFromArb_s2_bits_snpHitReleaseIdx;
+        task_s3_bits_snpHitReleaseMeta_dirty <=
+          io_taskFromArb_s2_bits_snpHitReleaseMeta_dirty;
+        task_s3_bits_snpHitReleaseMeta_state <=
+          io_taskFromArb_s2_bits_snpHitReleaseMeta_state;
+        task_s3_bits_snpHitReleaseMeta_clients <=
+          io_taskFromArb_s2_bits_snpHitReleaseMeta_clients;
+        task_s3_bits_snpHitReleaseMeta_alias <=
+          io_taskFromArb_s2_bits_snpHitReleaseMeta_alias;
+        task_s3_bits_snpHitReleaseMeta_prefetch <=
+          io_taskFromArb_s2_bits_snpHitReleaseMeta_prefetch;
+        task_s3_bits_snpHitReleaseMeta_prefetchSrc <=
+          io_taskFromArb_s2_bits_snpHitReleaseMeta_prefetchSrc;
+        task_s3_bits_snpHitReleaseMeta_accessed <=
+          io_taskFromArb_s2_bits_snpHitReleaseMeta_accessed;
+        task_s3_bits_snpHitReleaseMeta_tagErr <=
+          io_taskFromArb_s2_bits_snpHitReleaseMeta_tagErr;
+        task_s3_bits_snpHitReleaseMeta_dataErr <=
+          io_taskFromArb_s2_bits_snpHitReleaseMeta_dataErr;
+        task_s3_bits_tgtID <= io_taskFromArb_s2_bits_tgtID;
+        task_s3_bits_srcID <= io_taskFromArb_s2_bits_srcID;
+        task_s3_bits_txnID <= io_taskFromArb_s2_bits_txnID;
+        task_s3_bits_homeNID <= io_taskFromArb_s2_bits_homeNID;
+        task_s3_bits_dbID <= io_taskFromArb_s2_bits_dbID;
+        task_s3_bits_fwdNID <= io_taskFromArb_s2_bits_fwdNID;
+        task_s3_bits_fwdTxnID <= io_taskFromArb_s2_bits_fwdTxnID;
+        task_s3_bits_chiOpcode <= io_taskFromArb_s2_bits_chiOpcode;
+        task_s3_bits_resp <= io_taskFromArb_s2_bits_resp;
+        task_s3_bits_fwdState <= io_taskFromArb_s2_bits_fwdState;
+        task_s3_bits_pCrdType <= io_taskFromArb_s2_bits_pCrdType;
+        task_s3_bits_retToSrc <= io_taskFromArb_s2_bits_retToSrc;
+        task_s3_bits_likelyshared <= io_taskFromArb_s2_bits_likelyshared;
+        task_s3_bits_expCompAck <= io_taskFromArb_s2_bits_expCompAck;
+        task_s3_bits_allowRetry <= io_taskFromArb_s2_bits_allowRetry;
+        task_s3_bits_memAttr_allocate <= io_taskFromArb_s2_bits_memAttr_allocate;
+        task_s3_bits_memAttr_cacheable <= io_taskFromArb_s2_bits_memAttr_cacheable;
+        task_s3_bits_memAttr_device <= io_taskFromArb_s2_bits_memAttr_device;
+        task_s3_bits_memAttr_ewa <= io_taskFromArb_s2_bits_memAttr_ewa;
+        task_s3_bits_traceTag <= io_taskFromArb_s2_bits_traceTag;
+      end
+      task_s3_valid_hold2_REG <= io_taskFromArb_s2_valid;
+      if (task_s3_valid_hold2_REG) begin
+      end
+      else
+        task_s3_valid_hold2 <= io_taskFromArb_s2_valid;
+      task_s4_valid <= task_s3_valid & ~req_drop_s3;
+      if (_GEN_7) begin
+        task_s4_bits_channel <= task_s3_bits_channel;
+        task_s4_bits_txChannel <= source_req_s3_txChannel;
+        task_s4_bits_set <= task_s3_bits_set;
+        task_s4_bits_tag <= task_s3_bits_tag;
+        task_s4_bits_off <= task_s3_bits_off;
+        task_s4_bits_alias <= task_s3_bits_alias;
+        task_s4_bits_vaddr <= task_s3_bits_vaddr;
+        task_s4_bits_isKeyword <= task_s3_bits_isKeyword;
+        task_s4_bits_opcode <= source_req_s3_opcode;
+        task_s4_bits_param <= source_req_s3_param;
+        task_s4_bits_size <= source_req_s3_size;
+        task_s4_bits_sourceId <= task_s3_bits_sourceId;
+        task_s4_bits_bufIdx <= task_s3_bits_bufIdx;
+        task_s4_bits_needProbeAckData <= task_s3_bits_needProbeAckData;
+        task_s4_bits_denied <= task_s3_bits_denied;
+        task_s4_bits_corrupt <= task_s3_bits_corrupt;
+        task_s4_bits_mshrTask <= task_s3_bits_mshrTask;
+        task_s4_bits_mshrId <=
+          ~task_s3_bits_mshrTask & need_mshr_s3
+            ? io_fromMSHRCtl_mshr_alloc_ptr
+            : source_req_s3_mshrId;
+        task_s4_bits_aliasTask <= task_s3_bits_aliasTask;
+        task_s4_bits_useProbeData <= task_s3_bits_useProbeData;
+        task_s4_bits_mshrRetry <= task_s3_bits_mshrRetry;
+        task_s4_bits_readProbeDataDown <= task_s3_bits_readProbeDataDown;
+        task_s4_bits_fromL2pft <= task_s3_bits_fromL2pft;
+        task_s4_bits_needHint <= task_s3_bits_needHint;
+        task_s4_bits_dirty <= task_s3_bits_dirty;
+        task_s4_bits_way <= task_s3_bits_way;
+        task_s4_bits_meta_dirty <= source_req_s3_meta_dirty;
+        task_s4_bits_meta_state <= source_req_s3_meta_state;
+        task_s4_bits_meta_clients <= source_req_s3_meta_clients;
+        task_s4_bits_meta_alias <= source_req_s3_meta_alias;
+        task_s4_bits_meta_prefetch <= source_req_s3_meta_prefetch;
+        task_s4_bits_meta_prefetchSrc <= source_req_s3_meta_prefetchSrc;
+        task_s4_bits_meta_accessed <= source_req_s3_meta_accessed;
+        task_s4_bits_meta_tagErr <= source_req_s3_meta_tagErr;
+        task_s4_bits_meta_dataErr <= source_req_s3_meta_dataErr;
+        task_s4_bits_metaWen <= source_req_s3_metaWen;
+        task_s4_bits_tagWen <= task_s3_bits_tagWen;
+        task_s4_bits_dsWen <= task_s3_bits_dsWen;
+        task_s4_bits_wayMask <= task_s3_bits_wayMask;
+        task_s4_bits_replTask <= task_s3_bits_replTask;
+        task_s4_bits_cmoTask <= task_s3_bits_cmoTask;
+        task_s4_bits_cmoAll <= task_s3_bits_cmoAll;
+        task_s4_bits_reqSource <= task_s3_bits_reqSource;
+        task_s4_bits_mergeA <= task_s3_bits_mergeA;
+        task_s4_bits_aMergeTask_off <= task_s3_bits_aMergeTask_off;
+        task_s4_bits_aMergeTask_alias <= task_s3_bits_aMergeTask_alias;
+        task_s4_bits_aMergeTask_vaddr <= task_s3_bits_aMergeTask_vaddr;
+        task_s4_bits_aMergeTask_isKeyword <= task_s3_bits_aMergeTask_isKeyword;
+        task_s4_bits_aMergeTask_opcode <= task_s3_bits_aMergeTask_opcode;
+        task_s4_bits_aMergeTask_param <= task_s3_bits_aMergeTask_param;
+        task_s4_bits_aMergeTask_sourceId <= task_s3_bits_aMergeTask_sourceId;
+        task_s4_bits_aMergeTask_meta_dirty <= task_s3_bits_aMergeTask_meta_dirty;
+        task_s4_bits_aMergeTask_meta_state <= task_s3_bits_aMergeTask_meta_state;
+        task_s4_bits_aMergeTask_meta_clients <= task_s3_bits_aMergeTask_meta_clients;
+        task_s4_bits_aMergeTask_meta_alias <= task_s3_bits_aMergeTask_meta_alias;
+        task_s4_bits_aMergeTask_meta_prefetch <= task_s3_bits_aMergeTask_meta_prefetch;
+        task_s4_bits_aMergeTask_meta_prefetchSrc <=
+          task_s3_bits_aMergeTask_meta_prefetchSrc;
+        task_s4_bits_aMergeTask_meta_accessed <= task_s3_bits_aMergeTask_meta_accessed;
+        task_s4_bits_aMergeTask_meta_tagErr <= task_s3_bits_aMergeTask_meta_tagErr;
+        task_s4_bits_aMergeTask_meta_dataErr <= task_s3_bits_aMergeTask_meta_dataErr;
+        task_s4_bits_snpHitRelease <= task_s3_bits_snpHitRelease;
+        task_s4_bits_snpHitReleaseToInval <= task_s3_bits_snpHitReleaseToInval;
+        task_s4_bits_snpHitReleaseToClean <= task_s3_bits_snpHitReleaseToClean;
+        task_s4_bits_snpHitReleaseWithData <= task_s3_bits_snpHitReleaseWithData;
+        task_s4_bits_snpHitReleaseIdx <= task_s3_bits_snpHitReleaseIdx;
+        task_s4_bits_snpHitReleaseMeta_dirty <= task_s3_bits_snpHitReleaseMeta_dirty;
+        task_s4_bits_snpHitReleaseMeta_state <= task_s3_bits_snpHitReleaseMeta_state;
+        task_s4_bits_snpHitReleaseMeta_clients <= task_s3_bits_snpHitReleaseMeta_clients;
+        task_s4_bits_snpHitReleaseMeta_alias <= task_s3_bits_snpHitReleaseMeta_alias;
+        task_s4_bits_snpHitReleaseMeta_prefetch <=
+          task_s3_bits_snpHitReleaseMeta_prefetch;
+        task_s4_bits_snpHitReleaseMeta_prefetchSrc <=
+          task_s3_bits_snpHitReleaseMeta_prefetchSrc;
+        task_s4_bits_snpHitReleaseMeta_accessed <=
+          task_s3_bits_snpHitReleaseMeta_accessed;
+        task_s4_bits_snpHitReleaseMeta_tagErr <= task_s3_bits_snpHitReleaseMeta_tagErr;
+        task_s4_bits_snpHitReleaseMeta_dataErr <= task_s3_bits_snpHitReleaseMeta_dataErr;
+        task_s4_bits_tgtID <= source_req_s3_tgtID;
+        task_s4_bits_srcID <= source_req_s3_srcID;
+        task_s4_bits_txnID <= task_s3_bits_txnID;
+        task_s4_bits_homeNID <= task_s3_bits_homeNID;
+        task_s4_bits_dbID <= source_req_s3_dbID;
+        task_s4_bits_fwdNID <= task_s3_bits_fwdNID;
+        task_s4_bits_fwdTxnID <= task_s3_bits_fwdTxnID;
+        task_s4_bits_chiOpcode <= txreq_s3_bits_opcode;
+        task_s4_bits_resp <= source_req_s3_resp;
+        task_s4_bits_fwdState <= source_req_s3_fwdState;
+        task_s4_bits_pCrdType <= source_req_s3_pCrdType;
+        task_s4_bits_retToSrc <= task_s3_bits_retToSrc;
+        task_s4_bits_likelyshared <= task_s3_bits_likelyshared;
+        task_s4_bits_expCompAck <= task_s3_bits_expCompAck;
+        task_s4_bits_allowRetry <= task_s3_bits_allowRetry;
+        task_s4_bits_memAttr_allocate <= task_s3_bits_memAttr_allocate;
+        task_s4_bits_memAttr_cacheable <= task_s3_bits_memAttr_cacheable;
+        task_s4_bits_memAttr_device <= task_s3_bits_memAttr_device;
+        task_s4_bits_memAttr_ewa <= task_s3_bits_memAttr_ewa;
+        task_s4_bits_traceTag <= task_s3_bits_traceTag;
+        need_write_releaseBuf_s4 <= need_write_releaseBuf;
+        isD_s4 <=
+          task_s3_bits_mshrTask
+            ? mshr_cmoresp_s3 | mshr_refill_s3 & ~retry
+            : task_s3_bits_channel[2] | task_s3_bits_channel[0] & ~need_mshr_s3_a
+              & ~(source_req_s3_opcode[0] & ~task_s3_bits_mshrTask)
+              & task_s3_bits_opcode != 4'h5;
+        isTXREQ_s4 <= isTXREQ_s3;
+        isTXRSP_s4 <= isTXRSP_s3;
+        isTXDAT_s4 <=
+          task_s3_bits_mshrTask
+            ? _perfEvents_T_5 | mshr_dct_s3
+            : task_s3_bits_channel[1] & ~need_mshr_s3_b & doRespData
+              & (~(hasData_s3 & ~task_s3_bits_mshrTask) | task_s3_bits_snpHitRelease
+                 & task_s3_bits_snpHitReleaseWithData);
+        tagError_s4 <= tagError_s3;
+        dataError_s4 <= io_dirResp_s3_meta_dataErr;
+        l2Error_s4 <= io_dirResp_s3_error;
+      end
+      chnl_valid_s4_REG <= chnl_fire_s3;
+      task_s5_valid <= task_s4_valid & ~req_drop_s4;
+      if (_GEN_8) begin
+        task_s5_bits_channel <= task_s4_bits_channel;
+        task_s5_bits_txChannel <= task_s4_bits_txChannel;
+        task_s5_bits_set <= task_s4_bits_set;
+        task_s5_bits_tag <= task_s4_bits_tag;
+        task_s5_bits_off <= task_s4_bits_off;
+        task_s5_bits_alias <= task_s4_bits_alias;
+        task_s5_bits_vaddr <= task_s4_bits_vaddr;
+        task_s5_bits_isKeyword <= task_s4_bits_isKeyword;
+        task_s5_bits_opcode <= task_s4_bits_opcode;
+        task_s5_bits_param <= task_s4_bits_param;
+        task_s5_bits_size <= task_s4_bits_size;
+        task_s5_bits_sourceId <= task_s4_bits_sourceId;
+        task_s5_bits_bufIdx <= task_s4_bits_bufIdx;
+        task_s5_bits_needProbeAckData <= task_s4_bits_needProbeAckData;
+        task_s5_bits_denied <= task_s4_bits_denied;
+        task_s5_bits_corrupt <= task_s4_bits_corrupt;
+        task_s5_bits_mshrTask <= task_s4_bits_mshrTask;
+        task_s5_bits_mshrId <= task_s4_bits_mshrId;
+        task_s5_bits_aliasTask <= task_s4_bits_aliasTask;
+        task_s5_bits_useProbeData <= task_s4_bits_useProbeData;
+        task_s5_bits_mshrRetry <= task_s4_bits_mshrRetry;
+        task_s5_bits_readProbeDataDown <= task_s4_bits_readProbeDataDown;
+        task_s5_bits_fromL2pft <= task_s4_bits_fromL2pft;
+        task_s5_bits_needHint <= task_s4_bits_needHint;
+        task_s5_bits_dirty <= task_s4_bits_dirty;
+        task_s5_bits_way <= task_s4_bits_way;
+        task_s5_bits_meta_dirty <= task_s4_bits_meta_dirty;
+        task_s5_bits_meta_state <= task_s4_bits_meta_state;
+        task_s5_bits_meta_clients <= task_s4_bits_meta_clients;
+        task_s5_bits_meta_alias <= task_s4_bits_meta_alias;
+        task_s5_bits_meta_prefetch <= task_s4_bits_meta_prefetch;
+        task_s5_bits_meta_prefetchSrc <= task_s4_bits_meta_prefetchSrc;
+        task_s5_bits_meta_accessed <= task_s4_bits_meta_accessed;
+        task_s5_bits_meta_tagErr <= task_s4_bits_meta_tagErr;
+        task_s5_bits_meta_dataErr <= task_s4_bits_meta_dataErr;
+        task_s5_bits_metaWen <= task_s4_bits_metaWen;
+        task_s5_bits_tagWen <= task_s4_bits_tagWen;
+        task_s5_bits_dsWen <= task_s4_bits_dsWen;
+        task_s5_bits_wayMask <= task_s4_bits_wayMask;
+        task_s5_bits_replTask <= task_s4_bits_replTask;
+        task_s5_bits_cmoTask <= task_s4_bits_cmoTask;
+        task_s5_bits_cmoAll <= task_s4_bits_cmoAll;
+        task_s5_bits_reqSource <= task_s4_bits_reqSource;
+        task_s5_bits_mergeA <= task_s4_bits_mergeA;
+        task_s5_bits_aMergeTask_off <= task_s4_bits_aMergeTask_off;
+        task_s5_bits_aMergeTask_alias <= task_s4_bits_aMergeTask_alias;
+        task_s5_bits_aMergeTask_vaddr <= task_s4_bits_aMergeTask_vaddr;
+        task_s5_bits_aMergeTask_isKeyword <= task_s4_bits_aMergeTask_isKeyword;
+        task_s5_bits_aMergeTask_opcode <= task_s4_bits_aMergeTask_opcode;
+        task_s5_bits_aMergeTask_param <= task_s4_bits_aMergeTask_param;
+        task_s5_bits_aMergeTask_sourceId <= task_s4_bits_aMergeTask_sourceId;
+        task_s5_bits_aMergeTask_meta_dirty <= task_s4_bits_aMergeTask_meta_dirty;
+        task_s5_bits_aMergeTask_meta_state <= task_s4_bits_aMergeTask_meta_state;
+        task_s5_bits_aMergeTask_meta_clients <= task_s4_bits_aMergeTask_meta_clients;
+        task_s5_bits_aMergeTask_meta_alias <= task_s4_bits_aMergeTask_meta_alias;
+        task_s5_bits_aMergeTask_meta_prefetch <= task_s4_bits_aMergeTask_meta_prefetch;
+        task_s5_bits_aMergeTask_meta_prefetchSrc <=
+          task_s4_bits_aMergeTask_meta_prefetchSrc;
+        task_s5_bits_aMergeTask_meta_accessed <= task_s4_bits_aMergeTask_meta_accessed;
+        task_s5_bits_aMergeTask_meta_tagErr <= task_s4_bits_aMergeTask_meta_tagErr;
+        task_s5_bits_aMergeTask_meta_dataErr <= task_s4_bits_aMergeTask_meta_dataErr;
+        task_s5_bits_snpHitRelease <= task_s4_bits_snpHitRelease;
+        task_s5_bits_snpHitReleaseToInval <= task_s4_bits_snpHitReleaseToInval;
+        task_s5_bits_snpHitReleaseToClean <= task_s4_bits_snpHitReleaseToClean;
+        task_s5_bits_snpHitReleaseWithData <= task_s4_bits_snpHitReleaseWithData;
+        task_s5_bits_snpHitReleaseIdx <= task_s4_bits_snpHitReleaseIdx;
+        task_s5_bits_snpHitReleaseMeta_dirty <= task_s4_bits_snpHitReleaseMeta_dirty;
+        task_s5_bits_snpHitReleaseMeta_state <= task_s4_bits_snpHitReleaseMeta_state;
+        task_s5_bits_snpHitReleaseMeta_clients <= task_s4_bits_snpHitReleaseMeta_clients;
+        task_s5_bits_snpHitReleaseMeta_alias <= task_s4_bits_snpHitReleaseMeta_alias;
+        task_s5_bits_snpHitReleaseMeta_prefetch <=
+          task_s4_bits_snpHitReleaseMeta_prefetch;
+        task_s5_bits_snpHitReleaseMeta_prefetchSrc <=
+          task_s4_bits_snpHitReleaseMeta_prefetchSrc;
+        task_s5_bits_snpHitReleaseMeta_accessed <=
+          task_s4_bits_snpHitReleaseMeta_accessed;
+        task_s5_bits_snpHitReleaseMeta_tagErr <= task_s4_bits_snpHitReleaseMeta_tagErr;
+        task_s5_bits_snpHitReleaseMeta_dataErr <= task_s4_bits_snpHitReleaseMeta_dataErr;
+        task_s5_bits_tgtID <= task_s4_bits_tgtID;
+        task_s5_bits_srcID <= task_s4_bits_srcID;
+        task_s5_bits_txnID <= task_s4_bits_txnID;
+        task_s5_bits_homeNID <= task_s4_bits_homeNID;
+        task_s5_bits_dbID <= task_s4_bits_dbID;
+        task_s5_bits_fwdNID <= task_s4_bits_fwdNID;
+        task_s5_bits_fwdTxnID <= task_s4_bits_fwdTxnID;
+        task_s5_bits_chiOpcode <= task_s4_bits_chiOpcode;
+        task_s5_bits_resp <= task_s4_bits_resp;
+        task_s5_bits_fwdState <= task_s4_bits_fwdState;
+        task_s5_bits_pCrdType <= task_s4_bits_pCrdType;
+        task_s5_bits_retToSrc <= task_s4_bits_retToSrc;
+        task_s5_bits_likelyshared <= task_s4_bits_likelyshared;
+        task_s5_bits_expCompAck <= task_s4_bits_expCompAck;
+        task_s5_bits_allowRetry <= task_s4_bits_allowRetry;
+        task_s5_bits_memAttr_allocate <= task_s4_bits_memAttr_allocate;
+        task_s5_bits_memAttr_cacheable <= task_s4_bits_memAttr_cacheable;
+        task_s5_bits_memAttr_device <= task_s4_bits_memAttr_device;
+        task_s5_bits_memAttr_ewa <= task_s4_bits_memAttr_ewa;
+        task_s5_bits_traceTag <= task_s4_bits_traceTag;
+        need_write_releaseBuf_s5 <= need_write_releaseBuf_s4;
+        isD_s5 <= isD_s4 | pendingD_s4;
+        isTXREQ_s5 <= isTXREQ_s4;
+        isTXRSP_s5 <= isTXRSP_s4;
+        isTXDAT_s5 <=
+          isTXDAT_s4 | task_s4_bits_channel[1] & ~task_s4_bits_mshrTask
+          & task_s4_bits_txChannel[2];
+        tagError_s5 <= tagError_s4;
+        dataMetaError_s5 <= dataError_s4;
+        l2TagError_s5 <= l2Error_s4;
+      end
+      chnl_valid_s5_REG <= chnl_fire_s4;
+      chnl_valid_s5_REG_1 <= chnl_fire_s3;
+      chnl_valid_s5_REG_2 <= chnl_valid_s5_REG_1;
+    end
+  end // always @(posedge, posedge)
+  wire             _perfEvents_T_13 = task_s3_valid & sinkA_req_s3;
+  wire             miss_s3 = task_s3_valid & ~task_s3_bits_mshrTask & ~io_dirResp_s3_hit;
+  wire             perfEvents_10_2 = task_s3_valid & sinkC_req_s3;
+  always @(posedge clock) begin
+    if (io_taskFromArb_s2_valid)
+      reqWayOH_s3 <= 8'h1 << io_taskFromArb_s2_bits_way;
+    if (_GEN_7)
+      data_s4 <= data_s3;
+    if (_GEN_8)
+      data_s5 <= data_s4;
+    io_perf_0_value_REG <=
+      task_s3_valid & ~task_s3_bits_mshrTask & io_dirResp_s3_hit
+      & task_s3_bits_channel[0];
+    io_perf_0_value_REG_1 <= io_perf_0_value_REG;
+    io_perf_1_value_REG <= miss_s3 & task_s3_bits_channel[0];
+    io_perf_1_value_REG_1 <= io_perf_1_value_REG;
+    io_perf_2_value_REG <=
+      task_s3_valid & (sinkA_req_s3 & ~req_prefetch_s3 | sinkC_req_s3);
+    io_perf_2_value_REG_1 <= io_perf_2_value_REG;
+    io_perf_3_value_REG <= task_s3_valid & _perfEvents_T_5;
+    io_perf_3_value_REG_1 <= io_perf_3_value_REG;
+    io_perf_4_value_REG <= perfEvents_10_2 & _perfEvents_T_7;
+    io_perf_4_value_REG_1 <= io_perf_4_value_REG;
+    io_perf_5_value_REG <= task_s3_valid & mshr_cbWrData_s3;
+    io_perf_5_value_REG_1 <= io_perf_5_value_REG;
+    io_perf_6_value_REG <= task_s3_valid & mshr_snpRespDataX_s3;
+    io_perf_6_value_REG_1 <= io_perf_6_value_REG;
+    io_perf_7_value_REG <= _perfEvents_T_13 & req_prefetch_s3;
+    io_perf_7_value_REG_1 <= io_perf_7_value_REG;
+    io_perf_8_value_REG <= _perfEvents_T_13 & req_prefetch_s3 & miss_s3;
+    io_perf_8_value_REG_1 <= io_perf_8_value_REG;
+    io_perf_9_value_REG <= _perfEvents_T_13 & ~req_prefetch_s3;
+    io_perf_9_value_REG_1 <= io_perf_9_value_REG;
+    io_perf_10_value_REG <= perfEvents_10_2;
+    io_perf_10_value_REG_1 <= io_perf_10_value_REG;
+    io_perf_11_value_REG <= _perfEvents_T_13 & ~req_prefetch_s3 & miss_s3;
+    io_perf_11_value_REG_1 <= io_perf_11_value_REG;
+    io_perf_12_value_REG <= task_s3_valid & sinkB_req_s3 & task_s3_bits_param == 3'h2;
+    io_perf_12_value_REG_1 <= io_perf_12_value_REG;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:70];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [6:0] i = 7'h0; i < 7'h47; i += 7'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        resetFinish = _RANDOM[7'h0][0];
+        resetIdx = _RANDOM[7'h0][8:1];
+        task_s3_valid = _RANDOM[7'h0][9];
+        task_s3_bits_channel = _RANDOM[7'h0][12:10];
+        task_s3_bits_txChannel = _RANDOM[7'h0][15:13];
+        task_s3_bits_set = _RANDOM[7'h0][23:16];
+        task_s3_bits_tag = {_RANDOM[7'h0][31:24], _RANDOM[7'h1][25:0]};
+        task_s3_bits_off = _RANDOM[7'h1][31:26];
+        task_s3_bits_alias = _RANDOM[7'h2][0];
+        task_s3_bits_vaddr = {_RANDOM[7'h2][31:1], _RANDOM[7'h3][12:0]};
+        task_s3_bits_isKeyword = _RANDOM[7'h3][13];
+        task_s3_bits_opcode = _RANDOM[7'h3][17:14];
+        task_s3_bits_param = _RANDOM[7'h3][20:18];
+        task_s3_bits_size = _RANDOM[7'h3][23:21];
+        task_s3_bits_sourceId = _RANDOM[7'h3][30:24];
+        task_s3_bits_bufIdx = {_RANDOM[7'h3][31], _RANDOM[7'h4][0]};
+        task_s3_bits_needProbeAckData = _RANDOM[7'h4][1];
+        task_s3_bits_denied = _RANDOM[7'h4][2];
+        task_s3_bits_corrupt = _RANDOM[7'h4][3];
+        task_s3_bits_mshrTask = _RANDOM[7'h4][4];
+        task_s3_bits_mshrId = _RANDOM[7'h4][12:5];
+        task_s3_bits_aliasTask = _RANDOM[7'h4][13];
+        task_s3_bits_useProbeData = _RANDOM[7'h4][14];
+        task_s3_bits_mshrRetry = _RANDOM[7'h4][15];
+        task_s3_bits_readProbeDataDown = _RANDOM[7'h4][16];
+        task_s3_bits_fromL2pft = _RANDOM[7'h4][17];
+        task_s3_bits_needHint = _RANDOM[7'h4][18];
+        task_s3_bits_dirty = _RANDOM[7'h4][19];
+        task_s3_bits_way = _RANDOM[7'h4][22:20];
+        task_s3_bits_meta_dirty = _RANDOM[7'h4][23];
+        task_s3_bits_meta_state = _RANDOM[7'h4][25:24];
+        task_s3_bits_meta_clients = _RANDOM[7'h4][26];
+        task_s3_bits_meta_alias = _RANDOM[7'h4][27];
+        task_s3_bits_meta_prefetch = _RANDOM[7'h4][28];
+        task_s3_bits_meta_prefetchSrc = {_RANDOM[7'h4][31:29], _RANDOM[7'h5][0]};
+        task_s3_bits_meta_accessed = _RANDOM[7'h5][1];
+        task_s3_bits_meta_tagErr = _RANDOM[7'h5][2];
+        task_s3_bits_meta_dataErr = _RANDOM[7'h5][3];
+        task_s3_bits_metaWen = _RANDOM[7'h5][4];
+        task_s3_bits_tagWen = _RANDOM[7'h5][5];
+        task_s3_bits_dsWen = _RANDOM[7'h5][6];
+        task_s3_bits_wayMask = _RANDOM[7'h5][14:7];
+        task_s3_bits_replTask = _RANDOM[7'h5][15];
+        task_s3_bits_cmoTask = _RANDOM[7'h5][16];
+        task_s3_bits_cmoAll = _RANDOM[7'h5][17];
+        task_s3_bits_reqSource = _RANDOM[7'h5][22:18];
+        task_s3_bits_mergeA = _RANDOM[7'h5][23];
+        task_s3_bits_aMergeTask_off = _RANDOM[7'h5][29:24];
+        task_s3_bits_aMergeTask_alias = _RANDOM[7'h5][30];
+        task_s3_bits_aMergeTask_vaddr =
+          {_RANDOM[7'h5][31], _RANDOM[7'h6], _RANDOM[7'h7][10:0]};
+        task_s3_bits_aMergeTask_isKeyword = _RANDOM[7'h7][11];
+        task_s3_bits_aMergeTask_opcode = _RANDOM[7'h7][14:12];
+        task_s3_bits_aMergeTask_param = _RANDOM[7'h7][17:15];
+        task_s3_bits_aMergeTask_sourceId = _RANDOM[7'h7][24:18];
+        task_s3_bits_aMergeTask_meta_dirty = _RANDOM[7'h7][25];
+        task_s3_bits_aMergeTask_meta_state = _RANDOM[7'h7][27:26];
+        task_s3_bits_aMergeTask_meta_clients = _RANDOM[7'h7][28];
+        task_s3_bits_aMergeTask_meta_alias = _RANDOM[7'h7][29];
+        task_s3_bits_aMergeTask_meta_prefetch = _RANDOM[7'h7][30];
+        task_s3_bits_aMergeTask_meta_prefetchSrc =
+          {_RANDOM[7'h7][31], _RANDOM[7'h8][2:0]};
+        task_s3_bits_aMergeTask_meta_accessed = _RANDOM[7'h8][3];
+        task_s3_bits_aMergeTask_meta_tagErr = _RANDOM[7'h8][4];
+        task_s3_bits_aMergeTask_meta_dataErr = _RANDOM[7'h8][5];
+        task_s3_bits_snpHitRelease = _RANDOM[7'h8][6];
+        task_s3_bits_snpHitReleaseToInval = _RANDOM[7'h8][7];
+        task_s3_bits_snpHitReleaseToClean = _RANDOM[7'h8][8];
+        task_s3_bits_snpHitReleaseWithData = _RANDOM[7'h8][9];
+        task_s3_bits_snpHitReleaseIdx = _RANDOM[7'h8][17:10];
+        task_s3_bits_snpHitReleaseMeta_dirty = _RANDOM[7'h8][18];
+        task_s3_bits_snpHitReleaseMeta_state = _RANDOM[7'h8][20:19];
+        task_s3_bits_snpHitReleaseMeta_clients = _RANDOM[7'h8][21];
+        task_s3_bits_snpHitReleaseMeta_alias = _RANDOM[7'h8][22];
+        task_s3_bits_snpHitReleaseMeta_prefetch = _RANDOM[7'h8][23];
+        task_s3_bits_snpHitReleaseMeta_prefetchSrc = _RANDOM[7'h8][27:24];
+        task_s3_bits_snpHitReleaseMeta_accessed = _RANDOM[7'h8][28];
+        task_s3_bits_snpHitReleaseMeta_tagErr = _RANDOM[7'h8][29];
+        task_s3_bits_snpHitReleaseMeta_dataErr = _RANDOM[7'h8][30];
+        task_s3_bits_tgtID = {_RANDOM[7'h8][31], _RANDOM[7'h9][9:0]};
+        task_s3_bits_srcID = _RANDOM[7'h9][20:10];
+        task_s3_bits_txnID = {_RANDOM[7'h9][31:21], _RANDOM[7'hA][0]};
+        task_s3_bits_homeNID = _RANDOM[7'hA][11:1];
+        task_s3_bits_dbID = _RANDOM[7'hA][23:12];
+        task_s3_bits_fwdNID = {_RANDOM[7'hA][31:24], _RANDOM[7'hB][2:0]};
+        task_s3_bits_fwdTxnID = _RANDOM[7'hB][14:3];
+        task_s3_bits_chiOpcode = _RANDOM[7'hB][21:15];
+        task_s3_bits_resp = _RANDOM[7'hB][24:22];
+        task_s3_bits_fwdState = _RANDOM[7'hB][27:25];
+        task_s3_bits_pCrdType = _RANDOM[7'hB][31:28];
+        task_s3_bits_retToSrc = _RANDOM[7'hC][0];
+        task_s3_bits_likelyshared = _RANDOM[7'hC][1];
+        task_s3_bits_expCompAck = _RANDOM[7'hC][2];
+        task_s3_bits_allowRetry = _RANDOM[7'hC][3];
+        task_s3_bits_memAttr_allocate = _RANDOM[7'hC][4];
+        task_s3_bits_memAttr_cacheable = _RANDOM[7'hC][5];
+        task_s3_bits_memAttr_device = _RANDOM[7'hC][6];
+        task_s3_bits_memAttr_ewa = _RANDOM[7'hC][7];
+        task_s3_bits_traceTag = _RANDOM[7'hC][8];
+        reqWayOH_s3 = _RANDOM[7'hC][16:9];
+        task_s3_valid_hold2_REG = _RANDOM[7'hC][17];
+        task_s3_valid_hold2 = _RANDOM[7'hC][18];
+        task_s4_valid = _RANDOM[7'hC][19];
+        task_s4_bits_channel = _RANDOM[7'hC][22:20];
+        task_s4_bits_txChannel = _RANDOM[7'hC][25:23];
+        task_s4_bits_set = {_RANDOM[7'hC][31:26], _RANDOM[7'hD][1:0]};
+        task_s4_bits_tag = {_RANDOM[7'hD][31:2], _RANDOM[7'hE][3:0]};
+        task_s4_bits_off = _RANDOM[7'hE][9:4];
+        task_s4_bits_alias = _RANDOM[7'hE][10];
+        task_s4_bits_vaddr = {_RANDOM[7'hE][31:11], _RANDOM[7'hF][22:0]};
+        task_s4_bits_isKeyword = _RANDOM[7'hF][23];
+        task_s4_bits_opcode = _RANDOM[7'hF][27:24];
+        task_s4_bits_param = _RANDOM[7'hF][30:28];
+        task_s4_bits_size = {_RANDOM[7'hF][31], _RANDOM[7'h10][1:0]};
+        task_s4_bits_sourceId = _RANDOM[7'h10][8:2];
+        task_s4_bits_bufIdx = _RANDOM[7'h10][10:9];
+        task_s4_bits_needProbeAckData = _RANDOM[7'h10][11];
+        task_s4_bits_denied = _RANDOM[7'h10][12];
+        task_s4_bits_corrupt = _RANDOM[7'h10][13];
+        task_s4_bits_mshrTask = _RANDOM[7'h10][14];
+        task_s4_bits_mshrId = _RANDOM[7'h10][22:15];
+        task_s4_bits_aliasTask = _RANDOM[7'h10][23];
+        task_s4_bits_useProbeData = _RANDOM[7'h10][24];
+        task_s4_bits_mshrRetry = _RANDOM[7'h10][25];
+        task_s4_bits_readProbeDataDown = _RANDOM[7'h10][26];
+        task_s4_bits_fromL2pft = _RANDOM[7'h10][27];
+        task_s4_bits_needHint = _RANDOM[7'h10][28];
+        task_s4_bits_dirty = _RANDOM[7'h10][29];
+        task_s4_bits_way = {_RANDOM[7'h10][31:30], _RANDOM[7'h11][0]};
+        task_s4_bits_meta_dirty = _RANDOM[7'h11][1];
+        task_s4_bits_meta_state = _RANDOM[7'h11][3:2];
+        task_s4_bits_meta_clients = _RANDOM[7'h11][4];
+        task_s4_bits_meta_alias = _RANDOM[7'h11][5];
+        task_s4_bits_meta_prefetch = _RANDOM[7'h11][6];
+        task_s4_bits_meta_prefetchSrc = _RANDOM[7'h11][10:7];
+        task_s4_bits_meta_accessed = _RANDOM[7'h11][11];
+        task_s4_bits_meta_tagErr = _RANDOM[7'h11][12];
+        task_s4_bits_meta_dataErr = _RANDOM[7'h11][13];
+        task_s4_bits_metaWen = _RANDOM[7'h11][14];
+        task_s4_bits_tagWen = _RANDOM[7'h11][15];
+        task_s4_bits_dsWen = _RANDOM[7'h11][16];
+        task_s4_bits_wayMask = _RANDOM[7'h11][24:17];
+        task_s4_bits_replTask = _RANDOM[7'h11][25];
+        task_s4_bits_cmoTask = _RANDOM[7'h11][26];
+        task_s4_bits_cmoAll = _RANDOM[7'h11][27];
+        task_s4_bits_reqSource = {_RANDOM[7'h11][31:28], _RANDOM[7'h12][0]};
+        task_s4_bits_mergeA = _RANDOM[7'h12][1];
+        task_s4_bits_aMergeTask_off = _RANDOM[7'h12][7:2];
+        task_s4_bits_aMergeTask_alias = _RANDOM[7'h12][8];
+        task_s4_bits_aMergeTask_vaddr = {_RANDOM[7'h12][31:9], _RANDOM[7'h13][20:0]};
+        task_s4_bits_aMergeTask_isKeyword = _RANDOM[7'h13][21];
+        task_s4_bits_aMergeTask_opcode = _RANDOM[7'h13][24:22];
+        task_s4_bits_aMergeTask_param = _RANDOM[7'h13][27:25];
+        task_s4_bits_aMergeTask_sourceId = {_RANDOM[7'h13][31:28], _RANDOM[7'h14][2:0]};
+        task_s4_bits_aMergeTask_meta_dirty = _RANDOM[7'h14][3];
+        task_s4_bits_aMergeTask_meta_state = _RANDOM[7'h14][5:4];
+        task_s4_bits_aMergeTask_meta_clients = _RANDOM[7'h14][6];
+        task_s4_bits_aMergeTask_meta_alias = _RANDOM[7'h14][7];
+        task_s4_bits_aMergeTask_meta_prefetch = _RANDOM[7'h14][8];
+        task_s4_bits_aMergeTask_meta_prefetchSrc = _RANDOM[7'h14][12:9];
+        task_s4_bits_aMergeTask_meta_accessed = _RANDOM[7'h14][13];
+        task_s4_bits_aMergeTask_meta_tagErr = _RANDOM[7'h14][14];
+        task_s4_bits_aMergeTask_meta_dataErr = _RANDOM[7'h14][15];
+        task_s4_bits_snpHitRelease = _RANDOM[7'h14][16];
+        task_s4_bits_snpHitReleaseToInval = _RANDOM[7'h14][17];
+        task_s4_bits_snpHitReleaseToClean = _RANDOM[7'h14][18];
+        task_s4_bits_snpHitReleaseWithData = _RANDOM[7'h14][19];
+        task_s4_bits_snpHitReleaseIdx = _RANDOM[7'h14][27:20];
+        task_s4_bits_snpHitReleaseMeta_dirty = _RANDOM[7'h14][28];
+        task_s4_bits_snpHitReleaseMeta_state = _RANDOM[7'h14][30:29];
+        task_s4_bits_snpHitReleaseMeta_clients = _RANDOM[7'h14][31];
+        task_s4_bits_snpHitReleaseMeta_alias = _RANDOM[7'h15][0];
+        task_s4_bits_snpHitReleaseMeta_prefetch = _RANDOM[7'h15][1];
+        task_s4_bits_snpHitReleaseMeta_prefetchSrc = _RANDOM[7'h15][5:2];
+        task_s4_bits_snpHitReleaseMeta_accessed = _RANDOM[7'h15][6];
+        task_s4_bits_snpHitReleaseMeta_tagErr = _RANDOM[7'h15][7];
+        task_s4_bits_snpHitReleaseMeta_dataErr = _RANDOM[7'h15][8];
+        task_s4_bits_tgtID = _RANDOM[7'h15][19:9];
+        task_s4_bits_srcID = _RANDOM[7'h15][30:20];
+        task_s4_bits_txnID = {_RANDOM[7'h15][31], _RANDOM[7'h16][10:0]};
+        task_s4_bits_homeNID = _RANDOM[7'h16][21:11];
+        task_s4_bits_dbID = {_RANDOM[7'h16][31:22], _RANDOM[7'h17][1:0]};
+        task_s4_bits_fwdNID = _RANDOM[7'h17][12:2];
+        task_s4_bits_fwdTxnID = _RANDOM[7'h17][24:13];
+        task_s4_bits_chiOpcode = _RANDOM[7'h17][31:25];
+        task_s4_bits_resp = _RANDOM[7'h18][2:0];
+        task_s4_bits_fwdState = _RANDOM[7'h18][5:3];
+        task_s4_bits_pCrdType = _RANDOM[7'h18][9:6];
+        task_s4_bits_retToSrc = _RANDOM[7'h18][10];
+        task_s4_bits_likelyshared = _RANDOM[7'h18][11];
+        task_s4_bits_expCompAck = _RANDOM[7'h18][12];
+        task_s4_bits_allowRetry = _RANDOM[7'h18][13];
+        task_s4_bits_memAttr_allocate = _RANDOM[7'h18][14];
+        task_s4_bits_memAttr_cacheable = _RANDOM[7'h18][15];
+        task_s4_bits_memAttr_device = _RANDOM[7'h18][16];
+        task_s4_bits_memAttr_ewa = _RANDOM[7'h18][17];
+        task_s4_bits_traceTag = _RANDOM[7'h18][18];
+        data_s4 =
+          {_RANDOM[7'h18][31:20],
+           _RANDOM[7'h19],
+           _RANDOM[7'h1A],
+           _RANDOM[7'h1B],
+           _RANDOM[7'h1C],
+           _RANDOM[7'h1D],
+           _RANDOM[7'h1E],
+           _RANDOM[7'h1F],
+           _RANDOM[7'h20],
+           _RANDOM[7'h21],
+           _RANDOM[7'h22],
+           _RANDOM[7'h23],
+           _RANDOM[7'h24],
+           _RANDOM[7'h25],
+           _RANDOM[7'h26],
+           _RANDOM[7'h27],
+           _RANDOM[7'h28][19:0]};
+        need_write_releaseBuf_s4 = _RANDOM[7'h28][21];
+        isD_s4 = _RANDOM[7'h28][22];
+        isTXREQ_s4 = _RANDOM[7'h28][23];
+        isTXRSP_s4 = _RANDOM[7'h28][24];
+        isTXDAT_s4 = _RANDOM[7'h28][25];
+        tagError_s4 = _RANDOM[7'h28][26];
+        dataError_s4 = _RANDOM[7'h28][27];
+        l2Error_s4 = _RANDOM[7'h28][28];
+        chnl_valid_s4_REG = _RANDOM[7'h28][29];
+        task_s5_valid = _RANDOM[7'h28][30];
+        task_s5_bits_channel = {_RANDOM[7'h28][31], _RANDOM[7'h29][1:0]};
+        task_s5_bits_txChannel = _RANDOM[7'h29][4:2];
+        task_s5_bits_set = _RANDOM[7'h29][12:5];
+        task_s5_bits_tag = {_RANDOM[7'h29][31:13], _RANDOM[7'h2A][14:0]};
+        task_s5_bits_off = _RANDOM[7'h2A][20:15];
+        task_s5_bits_alias = _RANDOM[7'h2A][21];
+        task_s5_bits_vaddr = {_RANDOM[7'h2A][31:22], _RANDOM[7'h2B], _RANDOM[7'h2C][1:0]};
+        task_s5_bits_isKeyword = _RANDOM[7'h2C][2];
+        task_s5_bits_opcode = _RANDOM[7'h2C][6:3];
+        task_s5_bits_param = _RANDOM[7'h2C][9:7];
+        task_s5_bits_size = _RANDOM[7'h2C][12:10];
+        task_s5_bits_sourceId = _RANDOM[7'h2C][19:13];
+        task_s5_bits_bufIdx = _RANDOM[7'h2C][21:20];
+        task_s5_bits_needProbeAckData = _RANDOM[7'h2C][22];
+        task_s5_bits_denied = _RANDOM[7'h2C][23];
+        task_s5_bits_corrupt = _RANDOM[7'h2C][24];
+        task_s5_bits_mshrTask = _RANDOM[7'h2C][25];
+        task_s5_bits_mshrId = {_RANDOM[7'h2C][31:26], _RANDOM[7'h2D][1:0]};
+        task_s5_bits_aliasTask = _RANDOM[7'h2D][2];
+        task_s5_bits_useProbeData = _RANDOM[7'h2D][3];
+        task_s5_bits_mshrRetry = _RANDOM[7'h2D][4];
+        task_s5_bits_readProbeDataDown = _RANDOM[7'h2D][5];
+        task_s5_bits_fromL2pft = _RANDOM[7'h2D][6];
+        task_s5_bits_needHint = _RANDOM[7'h2D][7];
+        task_s5_bits_dirty = _RANDOM[7'h2D][8];
+        task_s5_bits_way = _RANDOM[7'h2D][11:9];
+        task_s5_bits_meta_dirty = _RANDOM[7'h2D][12];
+        task_s5_bits_meta_state = _RANDOM[7'h2D][14:13];
+        task_s5_bits_meta_clients = _RANDOM[7'h2D][15];
+        task_s5_bits_meta_alias = _RANDOM[7'h2D][16];
+        task_s5_bits_meta_prefetch = _RANDOM[7'h2D][17];
+        task_s5_bits_meta_prefetchSrc = _RANDOM[7'h2D][21:18];
+        task_s5_bits_meta_accessed = _RANDOM[7'h2D][22];
+        task_s5_bits_meta_tagErr = _RANDOM[7'h2D][23];
+        task_s5_bits_meta_dataErr = _RANDOM[7'h2D][24];
+        task_s5_bits_metaWen = _RANDOM[7'h2D][25];
+        task_s5_bits_tagWen = _RANDOM[7'h2D][26];
+        task_s5_bits_dsWen = _RANDOM[7'h2D][27];
+        task_s5_bits_wayMask = {_RANDOM[7'h2D][31:28], _RANDOM[7'h2E][3:0]};
+        task_s5_bits_replTask = _RANDOM[7'h2E][4];
+        task_s5_bits_cmoTask = _RANDOM[7'h2E][5];
+        task_s5_bits_cmoAll = _RANDOM[7'h2E][6];
+        task_s5_bits_reqSource = _RANDOM[7'h2E][11:7];
+        task_s5_bits_mergeA = _RANDOM[7'h2E][12];
+        task_s5_bits_aMergeTask_off = _RANDOM[7'h2E][18:13];
+        task_s5_bits_aMergeTask_alias = _RANDOM[7'h2E][19];
+        task_s5_bits_aMergeTask_vaddr = {_RANDOM[7'h2E][31:20], _RANDOM[7'h2F]};
+        task_s5_bits_aMergeTask_isKeyword = _RANDOM[7'h30][0];
+        task_s5_bits_aMergeTask_opcode = _RANDOM[7'h30][3:1];
+        task_s5_bits_aMergeTask_param = _RANDOM[7'h30][6:4];
+        task_s5_bits_aMergeTask_sourceId = _RANDOM[7'h30][13:7];
+        task_s5_bits_aMergeTask_meta_dirty = _RANDOM[7'h30][14];
+        task_s5_bits_aMergeTask_meta_state = _RANDOM[7'h30][16:15];
+        task_s5_bits_aMergeTask_meta_clients = _RANDOM[7'h30][17];
+        task_s5_bits_aMergeTask_meta_alias = _RANDOM[7'h30][18];
+        task_s5_bits_aMergeTask_meta_prefetch = _RANDOM[7'h30][19];
+        task_s5_bits_aMergeTask_meta_prefetchSrc = _RANDOM[7'h30][23:20];
+        task_s5_bits_aMergeTask_meta_accessed = _RANDOM[7'h30][24];
+        task_s5_bits_aMergeTask_meta_tagErr = _RANDOM[7'h30][25];
+        task_s5_bits_aMergeTask_meta_dataErr = _RANDOM[7'h30][26];
+        task_s5_bits_snpHitRelease = _RANDOM[7'h30][27];
+        task_s5_bits_snpHitReleaseToInval = _RANDOM[7'h30][28];
+        task_s5_bits_snpHitReleaseToClean = _RANDOM[7'h30][29];
+        task_s5_bits_snpHitReleaseWithData = _RANDOM[7'h30][30];
+        task_s5_bits_snpHitReleaseIdx = {_RANDOM[7'h30][31], _RANDOM[7'h31][6:0]};
+        task_s5_bits_snpHitReleaseMeta_dirty = _RANDOM[7'h31][7];
+        task_s5_bits_snpHitReleaseMeta_state = _RANDOM[7'h31][9:8];
+        task_s5_bits_snpHitReleaseMeta_clients = _RANDOM[7'h31][10];
+        task_s5_bits_snpHitReleaseMeta_alias = _RANDOM[7'h31][11];
+        task_s5_bits_snpHitReleaseMeta_prefetch = _RANDOM[7'h31][12];
+        task_s5_bits_snpHitReleaseMeta_prefetchSrc = _RANDOM[7'h31][16:13];
+        task_s5_bits_snpHitReleaseMeta_accessed = _RANDOM[7'h31][17];
+        task_s5_bits_snpHitReleaseMeta_tagErr = _RANDOM[7'h31][18];
+        task_s5_bits_snpHitReleaseMeta_dataErr = _RANDOM[7'h31][19];
+        task_s5_bits_tgtID = _RANDOM[7'h31][30:20];
+        task_s5_bits_srcID = {_RANDOM[7'h31][31], _RANDOM[7'h32][9:0]};
+        task_s5_bits_txnID = _RANDOM[7'h32][21:10];
+        task_s5_bits_homeNID = {_RANDOM[7'h32][31:22], _RANDOM[7'h33][0]};
+        task_s5_bits_dbID = _RANDOM[7'h33][12:1];
+        task_s5_bits_fwdNID = _RANDOM[7'h33][23:13];
+        task_s5_bits_fwdTxnID = {_RANDOM[7'h33][31:24], _RANDOM[7'h34][3:0]};
+        task_s5_bits_chiOpcode = _RANDOM[7'h34][10:4];
+        task_s5_bits_resp = _RANDOM[7'h34][13:11];
+        task_s5_bits_fwdState = _RANDOM[7'h34][16:14];
+        task_s5_bits_pCrdType = _RANDOM[7'h34][20:17];
+        task_s5_bits_retToSrc = _RANDOM[7'h34][21];
+        task_s5_bits_likelyshared = _RANDOM[7'h34][22];
+        task_s5_bits_expCompAck = _RANDOM[7'h34][23];
+        task_s5_bits_allowRetry = _RANDOM[7'h34][24];
+        task_s5_bits_memAttr_allocate = _RANDOM[7'h34][25];
+        task_s5_bits_memAttr_cacheable = _RANDOM[7'h34][26];
+        task_s5_bits_memAttr_device = _RANDOM[7'h34][27];
+        task_s5_bits_memAttr_ewa = _RANDOM[7'h34][28];
+        task_s5_bits_traceTag = _RANDOM[7'h34][29];
+        data_s5 =
+          {_RANDOM[7'h34][31],
+           _RANDOM[7'h35],
+           _RANDOM[7'h36],
+           _RANDOM[7'h37],
+           _RANDOM[7'h38],
+           _RANDOM[7'h39],
+           _RANDOM[7'h3A],
+           _RANDOM[7'h3B],
+           _RANDOM[7'h3C],
+           _RANDOM[7'h3D],
+           _RANDOM[7'h3E],
+           _RANDOM[7'h3F],
+           _RANDOM[7'h40],
+           _RANDOM[7'h41],
+           _RANDOM[7'h42],
+           _RANDOM[7'h43],
+           _RANDOM[7'h44][30:0]};
+        need_write_releaseBuf_s5 = _RANDOM[7'h44][31];
+        isD_s5 = _RANDOM[7'h45][0];
+        isTXREQ_s5 = _RANDOM[7'h45][1];
+        isTXRSP_s5 = _RANDOM[7'h45][2];
+        isTXDAT_s5 = _RANDOM[7'h45][3];
+        tagError_s5 = _RANDOM[7'h45][4];
+        dataMetaError_s5 = _RANDOM[7'h45][5];
+        l2TagError_s5 = _RANDOM[7'h45][6];
+        chnl_valid_s5_REG = _RANDOM[7'h45][7];
+        chnl_valid_s5_REG_1 = _RANDOM[7'h45][8];
+        chnl_valid_s5_REG_2 = _RANDOM[7'h45][9];
+        io_perf_0_value_REG = _RANDOM[7'h45][10];
+        io_perf_0_value_REG_1 = _RANDOM[7'h45][11];
+        io_perf_1_value_REG = _RANDOM[7'h45][12];
+        io_perf_1_value_REG_1 = _RANDOM[7'h45][13];
+        io_perf_2_value_REG = _RANDOM[7'h45][14];
+        io_perf_2_value_REG_1 = _RANDOM[7'h45][15];
+        io_perf_3_value_REG = _RANDOM[7'h45][16];
+        io_perf_3_value_REG_1 = _RANDOM[7'h45][17];
+        io_perf_4_value_REG = _RANDOM[7'h45][18];
+        io_perf_4_value_REG_1 = _RANDOM[7'h45][19];
+        io_perf_5_value_REG = _RANDOM[7'h45][20];
+        io_perf_5_value_REG_1 = _RANDOM[7'h45][21];
+        io_perf_6_value_REG = _RANDOM[7'h45][22];
+        io_perf_6_value_REG_1 = _RANDOM[7'h45][23];
+        io_perf_7_value_REG = _RANDOM[7'h45][24];
+        io_perf_7_value_REG_1 = _RANDOM[7'h45][25];
+        io_perf_8_value_REG = _RANDOM[7'h45][26];
+        io_perf_8_value_REG_1 = _RANDOM[7'h45][27];
+        io_perf_9_value_REG = _RANDOM[7'h45][28];
+        io_perf_9_value_REG_1 = _RANDOM[7'h45][29];
+        io_perf_10_value_REG = _RANDOM[7'h45][30];
+        io_perf_10_value_REG_1 = _RANDOM[7'h45][31];
+        io_perf_11_value_REG = _RANDOM[7'h46][0];
+        io_perf_11_value_REG_1 = _RANDOM[7'h46][1];
+        io_perf_12_value_REG = _RANDOM[7'h46][2];
+        io_perf_12_value_REG_1 = _RANDOM[7'h46][3];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        resetFinish = 1'h0;
+        resetIdx = 8'hFF;
+        task_s3_valid = 1'h0;
+        task_s3_bits_channel = 3'h0;
+        task_s3_bits_txChannel = 3'h0;
+        task_s3_bits_set = 8'h0;
+        task_s3_bits_tag = 34'h0;
+        task_s3_bits_off = 6'h0;
+        task_s3_bits_alias = 1'h0;
+        task_s3_bits_vaddr = 44'h0;
+        task_s3_bits_isKeyword = 1'h0;
+        task_s3_bits_opcode = 4'h0;
+        task_s3_bits_param = 3'h0;
+        task_s3_bits_size = 3'h0;
+        task_s3_bits_sourceId = 7'h0;
+        task_s3_bits_bufIdx = 2'h0;
+        task_s3_bits_needProbeAckData = 1'h0;
+        task_s3_bits_denied = 1'h0;
+        task_s3_bits_corrupt = 1'h0;
+        task_s3_bits_mshrTask = 1'h0;
+        task_s3_bits_mshrId = 8'h0;
+        task_s3_bits_aliasTask = 1'h0;
+        task_s3_bits_useProbeData = 1'h0;
+        task_s3_bits_mshrRetry = 1'h0;
+        task_s3_bits_readProbeDataDown = 1'h0;
+        task_s3_bits_fromL2pft = 1'h0;
+        task_s3_bits_needHint = 1'h0;
+        task_s3_bits_dirty = 1'h0;
+        task_s3_bits_way = 3'h0;
+        task_s3_bits_meta_dirty = 1'h0;
+        task_s3_bits_meta_state = 2'h0;
+        task_s3_bits_meta_clients = 1'h0;
+        task_s3_bits_meta_alias = 1'h0;
+        task_s3_bits_meta_prefetch = 1'h0;
+        task_s3_bits_meta_prefetchSrc = 4'h0;
+        task_s3_bits_meta_accessed = 1'h0;
+        task_s3_bits_meta_tagErr = 1'h0;
+        task_s3_bits_meta_dataErr = 1'h0;
+        task_s3_bits_metaWen = 1'h0;
+        task_s3_bits_tagWen = 1'h0;
+        task_s3_bits_dsWen = 1'h0;
+        task_s3_bits_wayMask = 8'h0;
+        task_s3_bits_replTask = 1'h0;
+        task_s3_bits_cmoTask = 1'h0;
+        task_s3_bits_cmoAll = 1'h0;
+        task_s3_bits_reqSource = 5'h0;
+        task_s3_bits_mergeA = 1'h0;
+        task_s3_bits_aMergeTask_off = 6'h0;
+        task_s3_bits_aMergeTask_alias = 1'h0;
+        task_s3_bits_aMergeTask_vaddr = 44'h0;
+        task_s3_bits_aMergeTask_isKeyword = 1'h0;
+        task_s3_bits_aMergeTask_opcode = 3'h0;
+        task_s3_bits_aMergeTask_param = 3'h0;
+        task_s3_bits_aMergeTask_sourceId = 7'h0;
+        task_s3_bits_aMergeTask_meta_dirty = 1'h0;
+        task_s3_bits_aMergeTask_meta_state = 2'h0;
+        task_s3_bits_aMergeTask_meta_clients = 1'h0;
+        task_s3_bits_aMergeTask_meta_alias = 1'h0;
+        task_s3_bits_aMergeTask_meta_prefetch = 1'h0;
+        task_s3_bits_aMergeTask_meta_prefetchSrc = 4'h0;
+        task_s3_bits_aMergeTask_meta_accessed = 1'h0;
+        task_s3_bits_aMergeTask_meta_tagErr = 1'h0;
+        task_s3_bits_aMergeTask_meta_dataErr = 1'h0;
+        task_s3_bits_snpHitRelease = 1'h0;
+        task_s3_bits_snpHitReleaseToInval = 1'h0;
+        task_s3_bits_snpHitReleaseToClean = 1'h0;
+        task_s3_bits_snpHitReleaseWithData = 1'h0;
+        task_s3_bits_snpHitReleaseIdx = 8'h0;
+        task_s3_bits_snpHitReleaseMeta_dirty = 1'h0;
+        task_s3_bits_snpHitReleaseMeta_state = 2'h0;
+        task_s3_bits_snpHitReleaseMeta_clients = 1'h0;
+        task_s3_bits_snpHitReleaseMeta_alias = 1'h0;
+        task_s3_bits_snpHitReleaseMeta_prefetch = 1'h0;
+        task_s3_bits_snpHitReleaseMeta_prefetchSrc = 4'h0;
+        task_s3_bits_snpHitReleaseMeta_accessed = 1'h0;
+        task_s3_bits_snpHitReleaseMeta_tagErr = 1'h0;
+        task_s3_bits_snpHitReleaseMeta_dataErr = 1'h0;
+        task_s3_bits_tgtID = 11'h0;
+        task_s3_bits_srcID = 11'h0;
+        task_s3_bits_txnID = 12'h0;
+        task_s3_bits_homeNID = 11'h0;
+        task_s3_bits_dbID = 12'h0;
+        task_s3_bits_fwdNID = 11'h0;
+        task_s3_bits_fwdTxnID = 12'h0;
+        task_s3_bits_chiOpcode = 7'h0;
+        task_s3_bits_resp = 3'h0;
+        task_s3_bits_fwdState = 3'h0;
+        task_s3_bits_pCrdType = 4'h0;
+        task_s3_bits_retToSrc = 1'h0;
+        task_s3_bits_likelyshared = 1'h0;
+        task_s3_bits_expCompAck = 1'h0;
+        task_s3_bits_allowRetry = 1'h0;
+        task_s3_bits_memAttr_allocate = 1'h0;
+        task_s3_bits_memAttr_cacheable = 1'h0;
+        task_s3_bits_memAttr_device = 1'h0;
+        task_s3_bits_memAttr_ewa = 1'h0;
+        task_s3_bits_traceTag = 1'h0;
+        task_s3_valid_hold2_REG = 1'h0;
+        task_s3_valid_hold2 = 1'h0;
+        task_s4_valid = 1'h0;
+        task_s4_bits_channel = 3'h0;
+        task_s4_bits_txChannel = 3'h0;
+        task_s4_bits_set = 8'h0;
+        task_s4_bits_tag = 34'h0;
+        task_s4_bits_off = 6'h0;
+        task_s4_bits_alias = 1'h0;
+        task_s4_bits_vaddr = 44'h0;
+        task_s4_bits_isKeyword = 1'h0;
+        task_s4_bits_opcode = 4'h0;
+        task_s4_bits_param = 3'h0;
+        task_s4_bits_size = 3'h0;
+        task_s4_bits_sourceId = 7'h0;
+        task_s4_bits_bufIdx = 2'h0;
+        task_s4_bits_needProbeAckData = 1'h0;
+        task_s4_bits_denied = 1'h0;
+        task_s4_bits_corrupt = 1'h0;
+        task_s4_bits_mshrTask = 1'h0;
+        task_s4_bits_mshrId = 8'h0;
+        task_s4_bits_aliasTask = 1'h0;
+        task_s4_bits_useProbeData = 1'h0;
+        task_s4_bits_mshrRetry = 1'h0;
+        task_s4_bits_readProbeDataDown = 1'h0;
+        task_s4_bits_fromL2pft = 1'h0;
+        task_s4_bits_needHint = 1'h0;
+        task_s4_bits_dirty = 1'h0;
+        task_s4_bits_way = 3'h0;
+        task_s4_bits_meta_dirty = 1'h0;
+        task_s4_bits_meta_state = 2'h0;
+        task_s4_bits_meta_clients = 1'h0;
+        task_s4_bits_meta_alias = 1'h0;
+        task_s4_bits_meta_prefetch = 1'h0;
+        task_s4_bits_meta_prefetchSrc = 4'h0;
+        task_s4_bits_meta_accessed = 1'h0;
+        task_s4_bits_meta_tagErr = 1'h0;
+        task_s4_bits_meta_dataErr = 1'h0;
+        task_s4_bits_metaWen = 1'h0;
+        task_s4_bits_tagWen = 1'h0;
+        task_s4_bits_dsWen = 1'h0;
+        task_s4_bits_wayMask = 8'h0;
+        task_s4_bits_replTask = 1'h0;
+        task_s4_bits_cmoTask = 1'h0;
+        task_s4_bits_cmoAll = 1'h0;
+        task_s4_bits_reqSource = 5'h0;
+        task_s4_bits_mergeA = 1'h0;
+        task_s4_bits_aMergeTask_off = 6'h0;
+        task_s4_bits_aMergeTask_alias = 1'h0;
+        task_s4_bits_aMergeTask_vaddr = 44'h0;
+        task_s4_bits_aMergeTask_isKeyword = 1'h0;
+        task_s4_bits_aMergeTask_opcode = 3'h0;
+        task_s4_bits_aMergeTask_param = 3'h0;
+        task_s4_bits_aMergeTask_sourceId = 7'h0;
+        task_s4_bits_aMergeTask_meta_dirty = 1'h0;
+        task_s4_bits_aMergeTask_meta_state = 2'h0;
+        task_s4_bits_aMergeTask_meta_clients = 1'h0;
+        task_s4_bits_aMergeTask_meta_alias = 1'h0;
+        task_s4_bits_aMergeTask_meta_prefetch = 1'h0;
+        task_s4_bits_aMergeTask_meta_prefetchSrc = 4'h0;
+        task_s4_bits_aMergeTask_meta_accessed = 1'h0;
+        task_s4_bits_aMergeTask_meta_tagErr = 1'h0;
+        task_s4_bits_aMergeTask_meta_dataErr = 1'h0;
+        task_s4_bits_snpHitRelease = 1'h0;
+        task_s4_bits_snpHitReleaseToInval = 1'h0;
+        task_s4_bits_snpHitReleaseToClean = 1'h0;
+        task_s4_bits_snpHitReleaseWithData = 1'h0;
+        task_s4_bits_snpHitReleaseIdx = 8'h0;
+        task_s4_bits_snpHitReleaseMeta_dirty = 1'h0;
+        task_s4_bits_snpHitReleaseMeta_state = 2'h0;
+        task_s4_bits_snpHitReleaseMeta_clients = 1'h0;
+        task_s4_bits_snpHitReleaseMeta_alias = 1'h0;
+        task_s4_bits_snpHitReleaseMeta_prefetch = 1'h0;
+        task_s4_bits_snpHitReleaseMeta_prefetchSrc = 4'h0;
+        task_s4_bits_snpHitReleaseMeta_accessed = 1'h0;
+        task_s4_bits_snpHitReleaseMeta_tagErr = 1'h0;
+        task_s4_bits_snpHitReleaseMeta_dataErr = 1'h0;
+        task_s4_bits_tgtID = 11'h0;
+        task_s4_bits_srcID = 11'h0;
+        task_s4_bits_txnID = 12'h0;
+        task_s4_bits_homeNID = 11'h0;
+        task_s4_bits_dbID = 12'h0;
+        task_s4_bits_fwdNID = 11'h0;
+        task_s4_bits_fwdTxnID = 12'h0;
+        task_s4_bits_chiOpcode = 7'h0;
+        task_s4_bits_resp = 3'h0;
+        task_s4_bits_fwdState = 3'h0;
+        task_s4_bits_pCrdType = 4'h0;
+        task_s4_bits_retToSrc = 1'h0;
+        task_s4_bits_likelyshared = 1'h0;
+        task_s4_bits_expCompAck = 1'h0;
+        task_s4_bits_allowRetry = 1'h0;
+        task_s4_bits_memAttr_allocate = 1'h0;
+        task_s4_bits_memAttr_cacheable = 1'h0;
+        task_s4_bits_memAttr_device = 1'h0;
+        task_s4_bits_memAttr_ewa = 1'h0;
+        task_s4_bits_traceTag = 1'h0;
+        need_write_releaseBuf_s4 = 1'h0;
+        isD_s4 = 1'h0;
+        isTXREQ_s4 = 1'h0;
+        isTXRSP_s4 = 1'h0;
+        isTXDAT_s4 = 1'h0;
+        tagError_s4 = 1'h0;
+        dataError_s4 = 1'h0;
+        l2Error_s4 = 1'h0;
+        chnl_valid_s4_REG = 1'h0;
+        task_s5_valid = 1'h0;
+        task_s5_bits_channel = 3'h0;
+        task_s5_bits_txChannel = 3'h0;
+        task_s5_bits_set = 8'h0;
+        task_s5_bits_tag = 34'h0;
+        task_s5_bits_off = 6'h0;
+        task_s5_bits_alias = 1'h0;
+        task_s5_bits_vaddr = 44'h0;
+        task_s5_bits_isKeyword = 1'h0;
+        task_s5_bits_opcode = 4'h0;
+        task_s5_bits_param = 3'h0;
+        task_s5_bits_size = 3'h0;
+        task_s5_bits_sourceId = 7'h0;
+        task_s5_bits_bufIdx = 2'h0;
+        task_s5_bits_needProbeAckData = 1'h0;
+        task_s5_bits_denied = 1'h0;
+        task_s5_bits_corrupt = 1'h0;
+        task_s5_bits_mshrTask = 1'h0;
+        task_s5_bits_mshrId = 8'h0;
+        task_s5_bits_aliasTask = 1'h0;
+        task_s5_bits_useProbeData = 1'h0;
+        task_s5_bits_mshrRetry = 1'h0;
+        task_s5_bits_readProbeDataDown = 1'h0;
+        task_s5_bits_fromL2pft = 1'h0;
+        task_s5_bits_needHint = 1'h0;
+        task_s5_bits_dirty = 1'h0;
+        task_s5_bits_way = 3'h0;
+        task_s5_bits_meta_dirty = 1'h0;
+        task_s5_bits_meta_state = 2'h0;
+        task_s5_bits_meta_clients = 1'h0;
+        task_s5_bits_meta_alias = 1'h0;
+        task_s5_bits_meta_prefetch = 1'h0;
+        task_s5_bits_meta_prefetchSrc = 4'h0;
+        task_s5_bits_meta_accessed = 1'h0;
+        task_s5_bits_meta_tagErr = 1'h0;
+        task_s5_bits_meta_dataErr = 1'h0;
+        task_s5_bits_metaWen = 1'h0;
+        task_s5_bits_tagWen = 1'h0;
+        task_s5_bits_dsWen = 1'h0;
+        task_s5_bits_wayMask = 8'h0;
+        task_s5_bits_replTask = 1'h0;
+        task_s5_bits_cmoTask = 1'h0;
+        task_s5_bits_cmoAll = 1'h0;
+        task_s5_bits_reqSource = 5'h0;
+        task_s5_bits_mergeA = 1'h0;
+        task_s5_bits_aMergeTask_off = 6'h0;
+        task_s5_bits_aMergeTask_alias = 1'h0;
+        task_s5_bits_aMergeTask_vaddr = 44'h0;
+        task_s5_bits_aMergeTask_isKeyword = 1'h0;
+        task_s5_bits_aMergeTask_opcode = 3'h0;
+        task_s5_bits_aMergeTask_param = 3'h0;
+        task_s5_bits_aMergeTask_sourceId = 7'h0;
+        task_s5_bits_aMergeTask_meta_dirty = 1'h0;
+        task_s5_bits_aMergeTask_meta_state = 2'h0;
+        task_s5_bits_aMergeTask_meta_clients = 1'h0;
+        task_s5_bits_aMergeTask_meta_alias = 1'h0;
+        task_s5_bits_aMergeTask_meta_prefetch = 1'h0;
+        task_s5_bits_aMergeTask_meta_prefetchSrc = 4'h0;
+        task_s5_bits_aMergeTask_meta_accessed = 1'h0;
+        task_s5_bits_aMergeTask_meta_tagErr = 1'h0;
+        task_s5_bits_aMergeTask_meta_dataErr = 1'h0;
+        task_s5_bits_snpHitRelease = 1'h0;
+        task_s5_bits_snpHitReleaseToInval = 1'h0;
+        task_s5_bits_snpHitReleaseToClean = 1'h0;
+        task_s5_bits_snpHitReleaseWithData = 1'h0;
+        task_s5_bits_snpHitReleaseIdx = 8'h0;
+        task_s5_bits_snpHitReleaseMeta_dirty = 1'h0;
+        task_s5_bits_snpHitReleaseMeta_state = 2'h0;
+        task_s5_bits_snpHitReleaseMeta_clients = 1'h0;
+        task_s5_bits_snpHitReleaseMeta_alias = 1'h0;
+        task_s5_bits_snpHitReleaseMeta_prefetch = 1'h0;
+        task_s5_bits_snpHitReleaseMeta_prefetchSrc = 4'h0;
+        task_s5_bits_snpHitReleaseMeta_accessed = 1'h0;
+        task_s5_bits_snpHitReleaseMeta_tagErr = 1'h0;
+        task_s5_bits_snpHitReleaseMeta_dataErr = 1'h0;
+        task_s5_bits_tgtID = 11'h0;
+        task_s5_bits_srcID = 11'h0;
+        task_s5_bits_txnID = 12'h0;
+        task_s5_bits_homeNID = 11'h0;
+        task_s5_bits_dbID = 12'h0;
+        task_s5_bits_fwdNID = 11'h0;
+        task_s5_bits_fwdTxnID = 12'h0;
+        task_s5_bits_chiOpcode = 7'h0;
+        task_s5_bits_resp = 3'h0;
+        task_s5_bits_fwdState = 3'h0;
+        task_s5_bits_pCrdType = 4'h0;
+        task_s5_bits_retToSrc = 1'h0;
+        task_s5_bits_likelyshared = 1'h0;
+        task_s5_bits_expCompAck = 1'h0;
+        task_s5_bits_allowRetry = 1'h0;
+        task_s5_bits_memAttr_allocate = 1'h0;
+        task_s5_bits_memAttr_cacheable = 1'h0;
+        task_s5_bits_memAttr_device = 1'h0;
+        task_s5_bits_memAttr_ewa = 1'h0;
+        task_s5_bits_traceTag = 1'h0;
+        need_write_releaseBuf_s5 = 1'h0;
+        isD_s5 = 1'h0;
+        isTXREQ_s5 = 1'h0;
+        isTXRSP_s5 = 1'h0;
+        isTXDAT_s5 = 1'h0;
+        tagError_s5 = 1'h0;
+        dataMetaError_s5 = 1'h0;
+        l2TagError_s5 = 1'h0;
+        chnl_valid_s5_REG = 1'h0;
+        chnl_valid_s5_REG_1 = 1'h0;
+        chnl_valid_s5_REG_2 = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  CustomL1Hint customL1Hint (
+    .clock                                      (clock),
+    .reset                                      (reset),
+    .io_mshrHintQInfo_valid                     (io_mshrHintQInfo_valid),
+    .io_mshrHintQInfo_bits_channel              (io_mshrHintQInfo_bits_channel),
+    .io_mshrHintQInfo_bits_isKeyword            (io_mshrHintQInfo_bits_isKeyword),
+    .io_mshrHintQInfo_bits_opcode               (io_mshrHintQInfo_bits_opcode),
+    .io_mshrHintQInfo_bits_sourceId             (io_mshrHintQInfo_bits_sourceId),
+    .io_mshrHintQInfo_bits_mergeA               (io_mshrHintQInfo_bits_mergeA),
+    .io_mshrHintQInfo_bits_aMergeTask_isKeyword
+      (io_mshrHintQInfo_bits_aMergeTask_isKeyword),
+    .io_mshrHintQInfo_bits_aMergeTask_opcode    (io_mshrHintQInfo_bits_aMergeTask_opcode),
+    .io_mshrHintQInfo_bits_aMergeTask_sourceId
+      (io_mshrHintQInfo_bits_aMergeTask_sourceId),
+    .io_sinkCHintQInfo_valid                    (io_sinkCHintQInfo_valid),
+    .io_sinkCHintQInfo_bits_sourceId            (io_sinkCHintQInfo_bits_sourceId),
+    .io_retry_s2
+      (io_retryFastFwd_s2 & io_taskFromArb_s2_valid),
+    .io_s3_task_valid                           (task_s3_valid),
+    .io_s3_task_bits_channel                    (task_s3_bits_channel),
+    .io_s3_task_bits_isKeyword                  (task_s3_bits_isKeyword),
+    .io_s3_task_bits_opcode
+      (sink_resp_s3_valid ? sink_resp_s3_bits_opcode : task_s3_bits_opcode),
+    .io_s3_task_bits_sourceId                   (task_s3_bits_sourceId),
+    .io_s3_task_bits_mshrTask                   (task_s3_bits_mshrTask),
+    .io_s3_need_mshr                            (need_mshr_s3_a),
+    .io_l1Hint_ready                            (io_l1Hint_ready),
+    .io_l1Hint_valid                            (io_l1Hint_valid),
+    .io_l1Hint_bits_sourceId                    (io_l1Hint_bits_sourceId),
+    .io_l1Hint_bits_isKeyword                   (io_l1Hint_bits_isKeyword),
+    .io_l1Hint_bits_hasData                     (io_l1Hint_bits_hasData)
+  );
+  Arbiter3_TaskWithData toSourceD_arb (
+    .io_in_0_valid                                   (d_s5_valid),
+    .io_in_0_bits_task_channel                       (task_s5_bits_channel),
+    .io_in_0_bits_task_txChannel                     (task_s5_bits_txChannel),
+    .io_in_0_bits_task_set                           (task_s5_bits_set),
+    .io_in_0_bits_task_tag                           (task_s5_bits_tag),
+    .io_in_0_bits_task_off                           (task_s5_bits_off),
+    .io_in_0_bits_task_alias                         (task_s5_bits_alias),
+    .io_in_0_bits_task_vaddr                         (task_s5_bits_vaddr),
+    .io_in_0_bits_task_isKeyword                     (task_s5_bits_isKeyword),
+    .io_in_0_bits_task_opcode                        (task_s5_bits_opcode),
+    .io_in_0_bits_task_param                         (task_s5_bits_param),
+    .io_in_0_bits_task_size                          (task_s5_bits_size),
+    .io_in_0_bits_task_sourceId                      (task_s5_bits_sourceId),
+    .io_in_0_bits_task_bufIdx                        (task_s5_bits_bufIdx),
+    .io_in_0_bits_task_needProbeAckData              (task_s5_bits_needProbeAckData),
+    .io_in_0_bits_task_denied
+      (_d_s5_bits_task_corrupt_T ? task_s5_bits_denied : tagError_s5),
+    .io_in_0_bits_task_corrupt
+      (_d_s5_bits_task_corrupt_T ? task_s5_bits_corrupt : dataError_s5),
+    .io_in_0_bits_task_mshrTask                      (task_s5_bits_mshrTask),
+    .io_in_0_bits_task_mshrId                        (task_s5_bits_mshrId),
+    .io_in_0_bits_task_aliasTask                     (task_s5_bits_aliasTask),
+    .io_in_0_bits_task_useProbeData                  (task_s5_bits_useProbeData),
+    .io_in_0_bits_task_mshrRetry                     (task_s5_bits_mshrRetry),
+    .io_in_0_bits_task_readProbeDataDown             (task_s5_bits_readProbeDataDown),
+    .io_in_0_bits_task_fromL2pft                     (task_s5_bits_fromL2pft),
+    .io_in_0_bits_task_needHint                      (task_s5_bits_needHint),
+    .io_in_0_bits_task_dirty                         (task_s5_bits_dirty),
+    .io_in_0_bits_task_way                           (task_s5_bits_way),
+    .io_in_0_bits_task_meta_dirty                    (task_s5_bits_meta_dirty),
+    .io_in_0_bits_task_meta_state                    (task_s5_bits_meta_state),
+    .io_in_0_bits_task_meta_clients                  (task_s5_bits_meta_clients),
+    .io_in_0_bits_task_meta_alias                    (task_s5_bits_meta_alias),
+    .io_in_0_bits_task_meta_prefetch                 (task_s5_bits_meta_prefetch),
+    .io_in_0_bits_task_meta_prefetchSrc              (task_s5_bits_meta_prefetchSrc),
+    .io_in_0_bits_task_meta_accessed                 (task_s5_bits_meta_accessed),
+    .io_in_0_bits_task_meta_tagErr                   (task_s5_bits_meta_tagErr),
+    .io_in_0_bits_task_meta_dataErr                  (task_s5_bits_meta_dataErr),
+    .io_in_0_bits_task_metaWen                       (task_s5_bits_metaWen),
+    .io_in_0_bits_task_tagWen                        (task_s5_bits_tagWen),
+    .io_in_0_bits_task_dsWen                         (task_s5_bits_dsWen),
+    .io_in_0_bits_task_wayMask                       (task_s5_bits_wayMask),
+    .io_in_0_bits_task_replTask                      (task_s5_bits_replTask),
+    .io_in_0_bits_task_cmoTask                       (task_s5_bits_cmoTask),
+    .io_in_0_bits_task_cmoAll                        (task_s5_bits_cmoAll),
+    .io_in_0_bits_task_reqSource                     (task_s5_bits_reqSource),
+    .io_in_0_bits_task_mergeA                        (task_s5_bits_mergeA),
+    .io_in_0_bits_task_aMergeTask_off                (task_s5_bits_aMergeTask_off),
+    .io_in_0_bits_task_aMergeTask_alias              (task_s5_bits_aMergeTask_alias),
+    .io_in_0_bits_task_aMergeTask_vaddr              (task_s5_bits_aMergeTask_vaddr),
+    .io_in_0_bits_task_aMergeTask_isKeyword          (task_s5_bits_aMergeTask_isKeyword),
+    .io_in_0_bits_task_aMergeTask_opcode             (task_s5_bits_aMergeTask_opcode),
+    .io_in_0_bits_task_aMergeTask_param              (task_s5_bits_aMergeTask_param),
+    .io_in_0_bits_task_aMergeTask_sourceId           (task_s5_bits_aMergeTask_sourceId),
+    .io_in_0_bits_task_aMergeTask_meta_dirty         (task_s5_bits_aMergeTask_meta_dirty),
+    .io_in_0_bits_task_aMergeTask_meta_state         (task_s5_bits_aMergeTask_meta_state),
+    .io_in_0_bits_task_aMergeTask_meta_clients
+      (task_s5_bits_aMergeTask_meta_clients),
+    .io_in_0_bits_task_aMergeTask_meta_alias         (task_s5_bits_aMergeTask_meta_alias),
+    .io_in_0_bits_task_aMergeTask_meta_prefetch
+      (task_s5_bits_aMergeTask_meta_prefetch),
+    .io_in_0_bits_task_aMergeTask_meta_prefetchSrc
+      (task_s5_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_0_bits_task_aMergeTask_meta_accessed
+      (task_s5_bits_aMergeTask_meta_accessed),
+    .io_in_0_bits_task_aMergeTask_meta_tagErr
+      (task_s5_bits_aMergeTask_meta_tagErr),
+    .io_in_0_bits_task_aMergeTask_meta_dataErr
+      (task_s5_bits_aMergeTask_meta_dataErr),
+    .io_in_0_bits_task_snpHitRelease                 (task_s5_bits_snpHitRelease),
+    .io_in_0_bits_task_snpHitReleaseToInval          (task_s5_bits_snpHitReleaseToInval),
+    .io_in_0_bits_task_snpHitReleaseToClean          (task_s5_bits_snpHitReleaseToClean),
+    .io_in_0_bits_task_snpHitReleaseWithData         (task_s5_bits_snpHitReleaseWithData),
+    .io_in_0_bits_task_snpHitReleaseIdx              (task_s5_bits_snpHitReleaseIdx),
+    .io_in_0_bits_task_snpHitReleaseMeta_dirty
+      (task_s5_bits_snpHitReleaseMeta_dirty),
+    .io_in_0_bits_task_snpHitReleaseMeta_state
+      (task_s5_bits_snpHitReleaseMeta_state),
+    .io_in_0_bits_task_snpHitReleaseMeta_clients
+      (task_s5_bits_snpHitReleaseMeta_clients),
+    .io_in_0_bits_task_snpHitReleaseMeta_alias
+      (task_s5_bits_snpHitReleaseMeta_alias),
+    .io_in_0_bits_task_snpHitReleaseMeta_prefetch
+      (task_s5_bits_snpHitReleaseMeta_prefetch),
+    .io_in_0_bits_task_snpHitReleaseMeta_prefetchSrc
+      (task_s5_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_0_bits_task_snpHitReleaseMeta_accessed
+      (task_s5_bits_snpHitReleaseMeta_accessed),
+    .io_in_0_bits_task_snpHitReleaseMeta_tagErr
+      (task_s5_bits_snpHitReleaseMeta_tagErr),
+    .io_in_0_bits_task_snpHitReleaseMeta_dataErr
+      (task_s5_bits_snpHitReleaseMeta_dataErr),
+    .io_in_0_bits_task_tgtID                         (task_s5_bits_tgtID),
+    .io_in_0_bits_task_srcID                         (task_s5_bits_srcID),
+    .io_in_0_bits_task_txnID                         (task_s5_bits_txnID),
+    .io_in_0_bits_task_homeNID                       (task_s5_bits_homeNID),
+    .io_in_0_bits_task_dbID                          (task_s5_bits_dbID),
+    .io_in_0_bits_task_fwdNID                        (task_s5_bits_fwdNID),
+    .io_in_0_bits_task_fwdTxnID                      (task_s5_bits_fwdTxnID),
+    .io_in_0_bits_task_chiOpcode                     (task_s5_bits_chiOpcode),
+    .io_in_0_bits_task_resp                          (task_s5_bits_resp),
+    .io_in_0_bits_task_fwdState                      (task_s5_bits_fwdState),
+    .io_in_0_bits_task_pCrdType                      (task_s5_bits_pCrdType),
+    .io_in_0_bits_task_retToSrc                      (task_s5_bits_retToSrc),
+    .io_in_0_bits_task_likelyshared                  (task_s5_bits_likelyshared),
+    .io_in_0_bits_task_expCompAck                    (task_s5_bits_expCompAck),
+    .io_in_0_bits_task_allowRetry                    (task_s5_bits_allowRetry),
+    .io_in_0_bits_task_memAttr_allocate              (task_s5_bits_memAttr_allocate),
+    .io_in_0_bits_task_memAttr_cacheable             (task_s5_bits_memAttr_cacheable),
+    .io_in_0_bits_task_memAttr_device                (task_s5_bits_memAttr_device),
+    .io_in_0_bits_task_memAttr_ewa                   (task_s5_bits_memAttr_ewa),
+    .io_in_0_bits_task_traceTag                      (task_s5_bits_traceTag),
+    .io_in_0_bits_data_data                          (out_data_s5),
+    .io_in_1_ready                                   (_toSourceD_arb_io_in_1_ready),
+    .io_in_1_valid                                   (d_s4_valid),
+    .io_in_1_bits_task_channel                       (task_s4_bits_channel),
+    .io_in_1_bits_task_txChannel                     (task_s4_bits_txChannel),
+    .io_in_1_bits_task_set                           (task_s4_bits_set),
+    .io_in_1_bits_task_tag                           (task_s4_bits_tag),
+    .io_in_1_bits_task_off                           (task_s4_bits_off),
+    .io_in_1_bits_task_alias                         (task_s4_bits_alias),
+    .io_in_1_bits_task_vaddr                         (task_s4_bits_vaddr),
+    .io_in_1_bits_task_isKeyword                     (task_s4_bits_isKeyword),
+    .io_in_1_bits_task_opcode                        (task_s4_bits_opcode),
+    .io_in_1_bits_task_param                         (task_s4_bits_param),
+    .io_in_1_bits_task_size                          (task_s4_bits_size),
+    .io_in_1_bits_task_sourceId                      (task_s4_bits_sourceId),
+    .io_in_1_bits_task_bufIdx                        (task_s4_bits_bufIdx),
+    .io_in_1_bits_task_needProbeAckData              (task_s4_bits_needProbeAckData),
+    .io_in_1_bits_task_denied                        (task_s4_bits_denied),
+    .io_in_1_bits_task_corrupt                       (task_s4_bits_corrupt),
+    .io_in_1_bits_task_mshrTask                      (task_s4_bits_mshrTask),
+    .io_in_1_bits_task_mshrId                        (task_s4_bits_mshrId),
+    .io_in_1_bits_task_aliasTask                     (task_s4_bits_aliasTask),
+    .io_in_1_bits_task_useProbeData                  (task_s4_bits_useProbeData),
+    .io_in_1_bits_task_mshrRetry                     (task_s4_bits_mshrRetry),
+    .io_in_1_bits_task_readProbeDataDown             (task_s4_bits_readProbeDataDown),
+    .io_in_1_bits_task_fromL2pft                     (task_s4_bits_fromL2pft),
+    .io_in_1_bits_task_needHint                      (task_s4_bits_needHint),
+    .io_in_1_bits_task_dirty                         (task_s4_bits_dirty),
+    .io_in_1_bits_task_way                           (task_s4_bits_way),
+    .io_in_1_bits_task_meta_dirty                    (task_s4_bits_meta_dirty),
+    .io_in_1_bits_task_meta_state                    (task_s4_bits_meta_state),
+    .io_in_1_bits_task_meta_clients                  (task_s4_bits_meta_clients),
+    .io_in_1_bits_task_meta_alias                    (task_s4_bits_meta_alias),
+    .io_in_1_bits_task_meta_prefetch                 (task_s4_bits_meta_prefetch),
+    .io_in_1_bits_task_meta_prefetchSrc              (task_s4_bits_meta_prefetchSrc),
+    .io_in_1_bits_task_meta_accessed                 (task_s4_bits_meta_accessed),
+    .io_in_1_bits_task_meta_tagErr                   (task_s4_bits_meta_tagErr),
+    .io_in_1_bits_task_meta_dataErr                  (task_s4_bits_meta_dataErr),
+    .io_in_1_bits_task_metaWen                       (task_s4_bits_metaWen),
+    .io_in_1_bits_task_tagWen                        (task_s4_bits_tagWen),
+    .io_in_1_bits_task_dsWen                         (task_s4_bits_dsWen),
+    .io_in_1_bits_task_wayMask                       (task_s4_bits_wayMask),
+    .io_in_1_bits_task_replTask                      (task_s4_bits_replTask),
+    .io_in_1_bits_task_cmoTask                       (task_s4_bits_cmoTask),
+    .io_in_1_bits_task_cmoAll                        (task_s4_bits_cmoAll),
+    .io_in_1_bits_task_reqSource                     (task_s4_bits_reqSource),
+    .io_in_1_bits_task_mergeA                        (task_s4_bits_mergeA),
+    .io_in_1_bits_task_aMergeTask_off                (task_s4_bits_aMergeTask_off),
+    .io_in_1_bits_task_aMergeTask_alias              (task_s4_bits_aMergeTask_alias),
+    .io_in_1_bits_task_aMergeTask_vaddr              (task_s4_bits_aMergeTask_vaddr),
+    .io_in_1_bits_task_aMergeTask_isKeyword          (task_s4_bits_aMergeTask_isKeyword),
+    .io_in_1_bits_task_aMergeTask_opcode             (task_s4_bits_aMergeTask_opcode),
+    .io_in_1_bits_task_aMergeTask_param              (task_s4_bits_aMergeTask_param),
+    .io_in_1_bits_task_aMergeTask_sourceId           (task_s4_bits_aMergeTask_sourceId),
+    .io_in_1_bits_task_aMergeTask_meta_dirty         (task_s4_bits_aMergeTask_meta_dirty),
+    .io_in_1_bits_task_aMergeTask_meta_state         (task_s4_bits_aMergeTask_meta_state),
+    .io_in_1_bits_task_aMergeTask_meta_clients
+      (task_s4_bits_aMergeTask_meta_clients),
+    .io_in_1_bits_task_aMergeTask_meta_alias         (task_s4_bits_aMergeTask_meta_alias),
+    .io_in_1_bits_task_aMergeTask_meta_prefetch
+      (task_s4_bits_aMergeTask_meta_prefetch),
+    .io_in_1_bits_task_aMergeTask_meta_prefetchSrc
+      (task_s4_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_1_bits_task_aMergeTask_meta_accessed
+      (task_s4_bits_aMergeTask_meta_accessed),
+    .io_in_1_bits_task_aMergeTask_meta_tagErr
+      (task_s4_bits_aMergeTask_meta_tagErr),
+    .io_in_1_bits_task_aMergeTask_meta_dataErr
+      (task_s4_bits_aMergeTask_meta_dataErr),
+    .io_in_1_bits_task_snpHitRelease                 (task_s4_bits_snpHitRelease),
+    .io_in_1_bits_task_snpHitReleaseToInval          (task_s4_bits_snpHitReleaseToInval),
+    .io_in_1_bits_task_snpHitReleaseToClean          (task_s4_bits_snpHitReleaseToClean),
+    .io_in_1_bits_task_snpHitReleaseWithData         (task_s4_bits_snpHitReleaseWithData),
+    .io_in_1_bits_task_snpHitReleaseIdx              (task_s4_bits_snpHitReleaseIdx),
+    .io_in_1_bits_task_snpHitReleaseMeta_dirty
+      (task_s4_bits_snpHitReleaseMeta_dirty),
+    .io_in_1_bits_task_snpHitReleaseMeta_state
+      (task_s4_bits_snpHitReleaseMeta_state),
+    .io_in_1_bits_task_snpHitReleaseMeta_clients
+      (task_s4_bits_snpHitReleaseMeta_clients),
+    .io_in_1_bits_task_snpHitReleaseMeta_alias
+      (task_s4_bits_snpHitReleaseMeta_alias),
+    .io_in_1_bits_task_snpHitReleaseMeta_prefetch
+      (task_s4_bits_snpHitReleaseMeta_prefetch),
+    .io_in_1_bits_task_snpHitReleaseMeta_prefetchSrc
+      (task_s4_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_1_bits_task_snpHitReleaseMeta_accessed
+      (task_s4_bits_snpHitReleaseMeta_accessed),
+    .io_in_1_bits_task_snpHitReleaseMeta_tagErr
+      (task_s4_bits_snpHitReleaseMeta_tagErr),
+    .io_in_1_bits_task_snpHitReleaseMeta_dataErr
+      (task_s4_bits_snpHitReleaseMeta_dataErr),
+    .io_in_1_bits_task_tgtID                         (task_s4_bits_tgtID),
+    .io_in_1_bits_task_srcID                         (task_s4_bits_srcID),
+    .io_in_1_bits_task_txnID                         (task_s4_bits_txnID),
+    .io_in_1_bits_task_homeNID                       (task_s4_bits_homeNID),
+    .io_in_1_bits_task_dbID                          (task_s4_bits_dbID),
+    .io_in_1_bits_task_fwdNID                        (task_s4_bits_fwdNID),
+    .io_in_1_bits_task_fwdTxnID                      (task_s4_bits_fwdTxnID),
+    .io_in_1_bits_task_chiOpcode                     (task_s4_bits_chiOpcode),
+    .io_in_1_bits_task_resp                          (task_s4_bits_resp),
+    .io_in_1_bits_task_fwdState                      (task_s4_bits_fwdState),
+    .io_in_1_bits_task_pCrdType                      (task_s4_bits_pCrdType),
+    .io_in_1_bits_task_retToSrc                      (task_s4_bits_retToSrc),
+    .io_in_1_bits_task_likelyshared                  (task_s4_bits_likelyshared),
+    .io_in_1_bits_task_expCompAck                    (task_s4_bits_expCompAck),
+    .io_in_1_bits_task_allowRetry                    (task_s4_bits_allowRetry),
+    .io_in_1_bits_task_memAttr_allocate              (task_s4_bits_memAttr_allocate),
+    .io_in_1_bits_task_memAttr_cacheable             (task_s4_bits_memAttr_cacheable),
+    .io_in_1_bits_task_memAttr_device                (task_s4_bits_memAttr_device),
+    .io_in_1_bits_task_memAttr_ewa                   (task_s4_bits_memAttr_ewa),
+    .io_in_1_bits_task_traceTag                      (task_s4_bits_traceTag),
+    .io_in_1_bits_data_data                          (data_s4),
+    .io_in_2_ready                                   (_toSourceD_arb_io_in_2_ready),
+    .io_in_2_valid                                   (d_s3_valid),
+    .io_in_2_bits_task_channel                       (task_s3_bits_channel),
+    .io_in_2_bits_task_txChannel                     (source_req_s3_txChannel),
+    .io_in_2_bits_task_set                           (task_s3_bits_set),
+    .io_in_2_bits_task_tag                           (task_s3_bits_tag),
+    .io_in_2_bits_task_off                           (task_s3_bits_off),
+    .io_in_2_bits_task_alias                         (task_s3_bits_alias),
+    .io_in_2_bits_task_vaddr                         (task_s3_bits_vaddr),
+    .io_in_2_bits_task_isKeyword                     (task_s3_bits_isKeyword),
+    .io_in_2_bits_task_opcode
+      (task_s3_bits_mshrTask ? task_s3_bits_opcode : sink_resp_s3_bits_opcode),
+    .io_in_2_bits_task_param                         (source_req_s3_param),
+    .io_in_2_bits_task_size                          (source_req_s3_size),
+    .io_in_2_bits_task_sourceId                      (task_s3_bits_sourceId),
+    .io_in_2_bits_task_bufIdx                        (task_s3_bits_bufIdx),
+    .io_in_2_bits_task_needProbeAckData              (task_s3_bits_needProbeAckData),
+    .io_in_2_bits_task_denied                        (task_s3_bits_denied),
+    .io_in_2_bits_task_corrupt                       (task_s3_bits_corrupt),
+    .io_in_2_bits_task_mshrTask                      (task_s3_bits_mshrTask),
+    .io_in_2_bits_task_mshrId                        (source_req_s3_mshrId),
+    .io_in_2_bits_task_aliasTask                     (task_s3_bits_aliasTask),
+    .io_in_2_bits_task_useProbeData                  (task_s3_bits_useProbeData),
+    .io_in_2_bits_task_mshrRetry                     (task_s3_bits_mshrRetry),
+    .io_in_2_bits_task_readProbeDataDown             (task_s3_bits_readProbeDataDown),
+    .io_in_2_bits_task_fromL2pft                     (task_s3_bits_fromL2pft),
+    .io_in_2_bits_task_needHint                      (task_s3_bits_needHint),
+    .io_in_2_bits_task_dirty                         (task_s3_bits_dirty),
+    .io_in_2_bits_task_way                           (task_s3_bits_way),
+    .io_in_2_bits_task_meta_dirty                    (source_req_s3_meta_dirty),
+    .io_in_2_bits_task_meta_state                    (source_req_s3_meta_state),
+    .io_in_2_bits_task_meta_clients                  (source_req_s3_meta_clients),
+    .io_in_2_bits_task_meta_alias                    (source_req_s3_meta_alias),
+    .io_in_2_bits_task_meta_prefetch                 (source_req_s3_meta_prefetch),
+    .io_in_2_bits_task_meta_prefetchSrc              (source_req_s3_meta_prefetchSrc),
+    .io_in_2_bits_task_meta_accessed                 (source_req_s3_meta_accessed),
+    .io_in_2_bits_task_meta_tagErr                   (source_req_s3_meta_tagErr),
+    .io_in_2_bits_task_meta_dataErr                  (source_req_s3_meta_dataErr),
+    .io_in_2_bits_task_metaWen                       (source_req_s3_metaWen),
+    .io_in_2_bits_task_tagWen                        (task_s3_bits_tagWen),
+    .io_in_2_bits_task_dsWen                         (task_s3_bits_dsWen),
+    .io_in_2_bits_task_wayMask                       (task_s3_bits_wayMask),
+    .io_in_2_bits_task_replTask                      (task_s3_bits_replTask),
+    .io_in_2_bits_task_cmoTask                       (task_s3_bits_cmoTask),
+    .io_in_2_bits_task_cmoAll                        (task_s3_bits_cmoAll),
+    .io_in_2_bits_task_reqSource                     (task_s3_bits_reqSource),
+    .io_in_2_bits_task_mergeA                        (task_s3_bits_mergeA),
+    .io_in_2_bits_task_aMergeTask_off                (task_s3_bits_aMergeTask_off),
+    .io_in_2_bits_task_aMergeTask_alias              (task_s3_bits_aMergeTask_alias),
+    .io_in_2_bits_task_aMergeTask_vaddr              (task_s3_bits_aMergeTask_vaddr),
+    .io_in_2_bits_task_aMergeTask_isKeyword          (task_s3_bits_aMergeTask_isKeyword),
+    .io_in_2_bits_task_aMergeTask_opcode             (task_s3_bits_aMergeTask_opcode),
+    .io_in_2_bits_task_aMergeTask_param              (task_s3_bits_aMergeTask_param),
+    .io_in_2_bits_task_aMergeTask_sourceId           (task_s3_bits_aMergeTask_sourceId),
+    .io_in_2_bits_task_aMergeTask_meta_dirty         (task_s3_bits_aMergeTask_meta_dirty),
+    .io_in_2_bits_task_aMergeTask_meta_state         (task_s3_bits_aMergeTask_meta_state),
+    .io_in_2_bits_task_aMergeTask_meta_clients
+      (task_s3_bits_aMergeTask_meta_clients),
+    .io_in_2_bits_task_aMergeTask_meta_alias         (task_s3_bits_aMergeTask_meta_alias),
+    .io_in_2_bits_task_aMergeTask_meta_prefetch
+      (task_s3_bits_aMergeTask_meta_prefetch),
+    .io_in_2_bits_task_aMergeTask_meta_prefetchSrc
+      (task_s3_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_2_bits_task_aMergeTask_meta_accessed
+      (task_s3_bits_aMergeTask_meta_accessed),
+    .io_in_2_bits_task_aMergeTask_meta_tagErr
+      (task_s3_bits_aMergeTask_meta_tagErr),
+    .io_in_2_bits_task_aMergeTask_meta_dataErr
+      (task_s3_bits_aMergeTask_meta_dataErr),
+    .io_in_2_bits_task_snpHitRelease                 (task_s3_bits_snpHitRelease),
+    .io_in_2_bits_task_snpHitReleaseToInval          (task_s3_bits_snpHitReleaseToInval),
+    .io_in_2_bits_task_snpHitReleaseToClean          (task_s3_bits_snpHitReleaseToClean),
+    .io_in_2_bits_task_snpHitReleaseWithData         (task_s3_bits_snpHitReleaseWithData),
+    .io_in_2_bits_task_snpHitReleaseIdx              (task_s3_bits_snpHitReleaseIdx),
+    .io_in_2_bits_task_snpHitReleaseMeta_dirty
+      (task_s3_bits_snpHitReleaseMeta_dirty),
+    .io_in_2_bits_task_snpHitReleaseMeta_state
+      (task_s3_bits_snpHitReleaseMeta_state),
+    .io_in_2_bits_task_snpHitReleaseMeta_clients
+      (task_s3_bits_snpHitReleaseMeta_clients),
+    .io_in_2_bits_task_snpHitReleaseMeta_alias
+      (task_s3_bits_snpHitReleaseMeta_alias),
+    .io_in_2_bits_task_snpHitReleaseMeta_prefetch
+      (task_s3_bits_snpHitReleaseMeta_prefetch),
+    .io_in_2_bits_task_snpHitReleaseMeta_prefetchSrc
+      (task_s3_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_2_bits_task_snpHitReleaseMeta_accessed
+      (task_s3_bits_snpHitReleaseMeta_accessed),
+    .io_in_2_bits_task_snpHitReleaseMeta_tagErr
+      (task_s3_bits_snpHitReleaseMeta_tagErr),
+    .io_in_2_bits_task_snpHitReleaseMeta_dataErr
+      (task_s3_bits_snpHitReleaseMeta_dataErr),
+    .io_in_2_bits_task_tgtID                         (source_req_s3_tgtID),
+    .io_in_2_bits_task_srcID                         (source_req_s3_srcID),
+    .io_in_2_bits_task_txnID                         (task_s3_bits_txnID),
+    .io_in_2_bits_task_homeNID                       (task_s3_bits_homeNID),
+    .io_in_2_bits_task_dbID                          (source_req_s3_dbID),
+    .io_in_2_bits_task_fwdNID                        (task_s3_bits_fwdNID),
+    .io_in_2_bits_task_fwdTxnID                      (task_s3_bits_fwdTxnID),
+    .io_in_2_bits_task_chiOpcode                     (txreq_s3_bits_opcode),
+    .io_in_2_bits_task_resp                          (source_req_s3_resp),
+    .io_in_2_bits_task_fwdState                      (source_req_s3_fwdState),
+    .io_in_2_bits_task_pCrdType                      (source_req_s3_pCrdType),
+    .io_in_2_bits_task_retToSrc                      (task_s3_bits_retToSrc),
+    .io_in_2_bits_task_likelyshared                  (task_s3_bits_likelyshared),
+    .io_in_2_bits_task_expCompAck                    (task_s3_bits_expCompAck),
+    .io_in_2_bits_task_allowRetry                    (task_s3_bits_allowRetry),
+    .io_in_2_bits_task_memAttr_allocate              (task_s3_bits_memAttr_allocate),
+    .io_in_2_bits_task_memAttr_cacheable             (task_s3_bits_memAttr_cacheable),
+    .io_in_2_bits_task_memAttr_device                (task_s3_bits_memAttr_device),
+    .io_in_2_bits_task_memAttr_ewa                   (task_s3_bits_memAttr_ewa),
+    .io_in_2_bits_task_traceTag                      (task_s3_bits_traceTag),
+    .io_in_2_bits_data_data                          (data_s3),
+    .io_out_ready                                    (1'h1),
+    .io_out_valid                                    (io_toSourceD_valid),
+    .io_out_bits_task_channel                        (io_toSourceD_bits_task_channel),
+    .io_out_bits_task_txChannel                      (io_toSourceD_bits_task_txChannel),
+    .io_out_bits_task_set                            (io_toSourceD_bits_task_set),
+    .io_out_bits_task_tag                            (io_toSourceD_bits_task_tag),
+    .io_out_bits_task_off                            (io_toSourceD_bits_task_off),
+    .io_out_bits_task_alias                          (io_toSourceD_bits_task_alias),
+    .io_out_bits_task_vaddr                          (io_toSourceD_bits_task_vaddr),
+    .io_out_bits_task_isKeyword                      (io_toSourceD_bits_task_isKeyword),
+    .io_out_bits_task_opcode                         (io_toSourceD_bits_task_opcode),
+    .io_out_bits_task_param                          (io_toSourceD_bits_task_param),
+    .io_out_bits_task_size                           (io_toSourceD_bits_task_size),
+    .io_out_bits_task_sourceId                       (io_toSourceD_bits_task_sourceId),
+    .io_out_bits_task_bufIdx                         (io_toSourceD_bits_task_bufIdx),
+    .io_out_bits_task_needProbeAckData
+      (io_toSourceD_bits_task_needProbeAckData),
+    .io_out_bits_task_denied                         (io_toSourceD_bits_task_denied),
+    .io_out_bits_task_corrupt                        (io_toSourceD_bits_task_corrupt),
+    .io_out_bits_task_mshrTask                       (io_toSourceD_bits_task_mshrTask),
+    .io_out_bits_task_mshrId                         (io_toSourceD_bits_task_mshrId),
+    .io_out_bits_task_aliasTask                      (io_toSourceD_bits_task_aliasTask),
+    .io_out_bits_task_useProbeData
+      (io_toSourceD_bits_task_useProbeData),
+    .io_out_bits_task_mshrRetry                      (io_toSourceD_bits_task_mshrRetry),
+    .io_out_bits_task_readProbeDataDown
+      (io_toSourceD_bits_task_readProbeDataDown),
+    .io_out_bits_task_fromL2pft                      (io_toSourceD_bits_task_fromL2pft),
+    .io_out_bits_task_needHint                       (io_toSourceD_bits_task_needHint),
+    .io_out_bits_task_dirty                          (io_toSourceD_bits_task_dirty),
+    .io_out_bits_task_way                            (io_toSourceD_bits_task_way),
+    .io_out_bits_task_meta_dirty                     (io_toSourceD_bits_task_meta_dirty),
+    .io_out_bits_task_meta_state                     (io_toSourceD_bits_task_meta_state),
+    .io_out_bits_task_meta_clients
+      (io_toSourceD_bits_task_meta_clients),
+    .io_out_bits_task_meta_alias                     (io_toSourceD_bits_task_meta_alias),
+    .io_out_bits_task_meta_prefetch
+      (io_toSourceD_bits_task_meta_prefetch),
+    .io_out_bits_task_meta_prefetchSrc
+      (io_toSourceD_bits_task_meta_prefetchSrc),
+    .io_out_bits_task_meta_accessed
+      (io_toSourceD_bits_task_meta_accessed),
+    .io_out_bits_task_meta_tagErr                    (io_toSourceD_bits_task_meta_tagErr),
+    .io_out_bits_task_meta_dataErr
+      (io_toSourceD_bits_task_meta_dataErr),
+    .io_out_bits_task_metaWen                        (io_toSourceD_bits_task_metaWen),
+    .io_out_bits_task_tagWen                         (io_toSourceD_bits_task_tagWen),
+    .io_out_bits_task_dsWen                          (io_toSourceD_bits_task_dsWen),
+    .io_out_bits_task_wayMask                        (io_toSourceD_bits_task_wayMask),
+    .io_out_bits_task_replTask                       (io_toSourceD_bits_task_replTask),
+    .io_out_bits_task_cmoTask                        (io_toSourceD_bits_task_cmoTask),
+    .io_out_bits_task_cmoAll                         (io_toSourceD_bits_task_cmoAll),
+    .io_out_bits_task_reqSource                      (io_toSourceD_bits_task_reqSource),
+    .io_out_bits_task_mergeA                         (io_toSourceD_bits_task_mergeA),
+    .io_out_bits_task_aMergeTask_off
+      (io_toSourceD_bits_task_aMergeTask_off),
+    .io_out_bits_task_aMergeTask_alias
+      (io_toSourceD_bits_task_aMergeTask_alias),
+    .io_out_bits_task_aMergeTask_vaddr
+      (io_toSourceD_bits_task_aMergeTask_vaddr),
+    .io_out_bits_task_aMergeTask_isKeyword
+      (io_toSourceD_bits_task_aMergeTask_isKeyword),
+    .io_out_bits_task_aMergeTask_opcode
+      (io_toSourceD_bits_task_aMergeTask_opcode),
+    .io_out_bits_task_aMergeTask_param
+      (io_toSourceD_bits_task_aMergeTask_param),
+    .io_out_bits_task_aMergeTask_sourceId
+      (io_toSourceD_bits_task_aMergeTask_sourceId),
+    .io_out_bits_task_aMergeTask_meta_dirty
+      (io_toSourceD_bits_task_aMergeTask_meta_dirty),
+    .io_out_bits_task_aMergeTask_meta_state
+      (io_toSourceD_bits_task_aMergeTask_meta_state),
+    .io_out_bits_task_aMergeTask_meta_clients
+      (io_toSourceD_bits_task_aMergeTask_meta_clients),
+    .io_out_bits_task_aMergeTask_meta_alias
+      (io_toSourceD_bits_task_aMergeTask_meta_alias),
+    .io_out_bits_task_aMergeTask_meta_prefetch
+      (io_toSourceD_bits_task_aMergeTask_meta_prefetch),
+    .io_out_bits_task_aMergeTask_meta_prefetchSrc
+      (io_toSourceD_bits_task_aMergeTask_meta_prefetchSrc),
+    .io_out_bits_task_aMergeTask_meta_accessed
+      (io_toSourceD_bits_task_aMergeTask_meta_accessed),
+    .io_out_bits_task_aMergeTask_meta_tagErr
+      (io_toSourceD_bits_task_aMergeTask_meta_tagErr),
+    .io_out_bits_task_aMergeTask_meta_dataErr
+      (io_toSourceD_bits_task_aMergeTask_meta_dataErr),
+    .io_out_bits_task_snpHitRelease
+      (io_toSourceD_bits_task_snpHitRelease),
+    .io_out_bits_task_snpHitReleaseToInval
+      (io_toSourceD_bits_task_snpHitReleaseToInval),
+    .io_out_bits_task_snpHitReleaseToClean
+      (io_toSourceD_bits_task_snpHitReleaseToClean),
+    .io_out_bits_task_snpHitReleaseWithData
+      (io_toSourceD_bits_task_snpHitReleaseWithData),
+    .io_out_bits_task_snpHitReleaseIdx
+      (io_toSourceD_bits_task_snpHitReleaseIdx),
+    .io_out_bits_task_snpHitReleaseMeta_dirty
+      (io_toSourceD_bits_task_snpHitReleaseMeta_dirty),
+    .io_out_bits_task_snpHitReleaseMeta_state
+      (io_toSourceD_bits_task_snpHitReleaseMeta_state),
+    .io_out_bits_task_snpHitReleaseMeta_clients
+      (io_toSourceD_bits_task_snpHitReleaseMeta_clients),
+    .io_out_bits_task_snpHitReleaseMeta_alias
+      (io_toSourceD_bits_task_snpHitReleaseMeta_alias),
+    .io_out_bits_task_snpHitReleaseMeta_prefetch
+      (io_toSourceD_bits_task_snpHitReleaseMeta_prefetch),
+    .io_out_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_toSourceD_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_out_bits_task_snpHitReleaseMeta_accessed
+      (io_toSourceD_bits_task_snpHitReleaseMeta_accessed),
+    .io_out_bits_task_snpHitReleaseMeta_tagErr
+      (io_toSourceD_bits_task_snpHitReleaseMeta_tagErr),
+    .io_out_bits_task_snpHitReleaseMeta_dataErr
+      (io_toSourceD_bits_task_snpHitReleaseMeta_dataErr),
+    .io_out_bits_task_tgtID                          (io_toSourceD_bits_task_tgtID),
+    .io_out_bits_task_srcID                          (io_toSourceD_bits_task_srcID),
+    .io_out_bits_task_txnID                          (io_toSourceD_bits_task_txnID),
+    .io_out_bits_task_homeNID                        (io_toSourceD_bits_task_homeNID),
+    .io_out_bits_task_dbID                           (io_toSourceD_bits_task_dbID),
+    .io_out_bits_task_fwdNID                         (io_toSourceD_bits_task_fwdNID),
+    .io_out_bits_task_fwdTxnID                       (io_toSourceD_bits_task_fwdTxnID),
+    .io_out_bits_task_chiOpcode                      (io_toSourceD_bits_task_chiOpcode),
+    .io_out_bits_task_resp                           (io_toSourceD_bits_task_resp),
+    .io_out_bits_task_fwdState                       (io_toSourceD_bits_task_fwdState),
+    .io_out_bits_task_pCrdType                       (io_toSourceD_bits_task_pCrdType),
+    .io_out_bits_task_retToSrc                       (io_toSourceD_bits_task_retToSrc),
+    .io_out_bits_task_likelyshared
+      (io_toSourceD_bits_task_likelyshared),
+    .io_out_bits_task_expCompAck                     (io_toSourceD_bits_task_expCompAck),
+    .io_out_bits_task_allowRetry                     (io_toSourceD_bits_task_allowRetry),
+    .io_out_bits_task_memAttr_allocate
+      (io_toSourceD_bits_task_memAttr_allocate),
+    .io_out_bits_task_memAttr_cacheable
+      (io_toSourceD_bits_task_memAttr_cacheable),
+    .io_out_bits_task_memAttr_device
+      (io_toSourceD_bits_task_memAttr_device),
+    .io_out_bits_task_memAttr_ewa                    (io_toSourceD_bits_task_memAttr_ewa),
+    .io_out_bits_task_traceTag                       (io_toSourceD_bits_task_traceTag),
+    .io_out_bits_data_data                           (io_toSourceD_bits_data_data)
+  );
+  Arbiter3_CHIREQ toTXREQ_arb (
+    .io_in_0_valid                  (chnl_valid_s5 & isTXREQ_s5),
+    .io_in_0_bits_tgtID             (task_s5_bits_tgtID),
+    .io_in_0_bits_srcID             (task_s5_bits_srcID),
+    .io_in_0_bits_txnID             (task_s5_bits_txnID),
+    .io_in_0_bits_opcode            (task_s5_bits_chiOpcode),
+    .io_in_0_bits_addr              ({task_s5_bits_tag, task_s5_bits_set, 6'h0}),
+    .io_in_0_bits_likelyshared      (task_s5_bits_likelyshared),
+    .io_in_0_bits_allowRetry        (task_s5_bits_allowRetry),
+    .io_in_0_bits_pCrdType          (task_s5_bits_pCrdType),
+    .io_in_0_bits_memAttr_allocate  (task_s5_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable (task_s5_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_device    (task_s5_bits_memAttr_device),
+    .io_in_0_bits_memAttr_ewa       (task_s5_bits_memAttr_ewa),
+    .io_in_0_bits_expCompAck        (task_s5_bits_expCompAck),
+    .io_in_1_ready                  (_toTXREQ_arb_io_in_1_ready),
+    .io_in_1_valid                  (txreq_s4_valid),
+    .io_in_1_bits_tgtID             (task_s4_bits_tgtID),
+    .io_in_1_bits_srcID             (task_s4_bits_srcID),
+    .io_in_1_bits_txnID             (task_s4_bits_txnID),
+    .io_in_1_bits_opcode            (task_s4_bits_chiOpcode),
+    .io_in_1_bits_addr              ({task_s4_bits_tag, task_s4_bits_set, 6'h0}),
+    .io_in_1_bits_likelyshared      (task_s4_bits_likelyshared),
+    .io_in_1_bits_allowRetry        (task_s4_bits_allowRetry),
+    .io_in_1_bits_pCrdType          (task_s4_bits_pCrdType),
+    .io_in_1_bits_memAttr_allocate  (task_s4_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable (task_s4_bits_memAttr_cacheable),
+    .io_in_1_bits_memAttr_device    (task_s4_bits_memAttr_device),
+    .io_in_1_bits_memAttr_ewa       (task_s4_bits_memAttr_ewa),
+    .io_in_1_bits_expCompAck        (task_s4_bits_expCompAck),
+    .io_in_2_ready                  (_toTXREQ_arb_io_in_2_ready),
+    .io_in_2_valid                  (txreq_s3_valid),
+    .io_in_2_bits_tgtID             (source_req_s3_tgtID),
+    .io_in_2_bits_srcID             (source_req_s3_srcID),
+    .io_in_2_bits_txnID             (task_s3_bits_txnID),
+    .io_in_2_bits_opcode            (txreq_s3_bits_opcode),
+    .io_in_2_bits_addr              ({task_s3_bits_tag, task_s3_bits_set, 6'h0}),
+    .io_in_2_bits_likelyshared      (task_s3_bits_likelyshared),
+    .io_in_2_bits_allowRetry        (task_s3_bits_allowRetry),
+    .io_in_2_bits_pCrdType          (source_req_s3_pCrdType),
+    .io_in_2_bits_memAttr_allocate  (task_s3_bits_memAttr_allocate),
+    .io_in_2_bits_memAttr_cacheable (task_s3_bits_memAttr_cacheable),
+    .io_in_2_bits_memAttr_device    (task_s3_bits_memAttr_device),
+    .io_in_2_bits_memAttr_ewa       (task_s3_bits_memAttr_ewa),
+    .io_in_2_bits_expCompAck        (task_s3_bits_expCompAck),
+    .io_out_valid                   (io_toTXREQ_valid),
+    .io_out_bits_tgtID              (io_toTXREQ_bits_tgtID),
+    .io_out_bits_srcID              (io_toTXREQ_bits_srcID),
+    .io_out_bits_txnID              (io_toTXREQ_bits_txnID),
+    .io_out_bits_opcode             (io_toTXREQ_bits_opcode),
+    .io_out_bits_addr               (io_toTXREQ_bits_addr),
+    .io_out_bits_likelyshared       (io_toTXREQ_bits_likelyshared),
+    .io_out_bits_allowRetry         (io_toTXREQ_bits_allowRetry),
+    .io_out_bits_pCrdType           (io_toTXREQ_bits_pCrdType),
+    .io_out_bits_memAttr_allocate   (io_toTXREQ_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable  (io_toTXREQ_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device     (io_toTXREQ_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa        (io_toTXREQ_bits_memAttr_ewa),
+    .io_out_bits_expCompAck         (io_toTXREQ_bits_expCompAck)
+  );
+  Arbiter3_TaskBundle toTXRSP_arb (
+    .io_in_0_valid          (chnl_valid_s5 & isTXRSP_s5),
+    .io_in_0_bits_denied    (tagError_s5),
+    .io_in_0_bits_tgtID     (task_s5_bits_tgtID),
+    .io_in_0_bits_srcID     (task_s5_bits_srcID),
+    .io_in_0_bits_txnID     (task_s5_bits_txnID),
+    .io_in_0_bits_dbID      (task_s5_bits_dbID),
+    .io_in_0_bits_chiOpcode (task_s5_bits_chiOpcode),
+    .io_in_0_bits_resp      (task_s5_bits_resp),
+    .io_in_0_bits_fwdState  (task_s5_bits_fwdState),
+    .io_in_0_bits_pCrdType  (task_s5_bits_pCrdType),
+    .io_in_0_bits_traceTag  (task_s5_bits_traceTag),
+    .io_in_1_ready          (_toTXRSP_arb_io_in_1_ready),
+    .io_in_1_valid          (txrsp_s4_valid),
+    .io_in_1_bits_denied    (task_s4_bits_denied),
+    .io_in_1_bits_tgtID     (task_s4_bits_tgtID),
+    .io_in_1_bits_srcID     (task_s4_bits_srcID),
+    .io_in_1_bits_txnID     (task_s4_bits_txnID),
+    .io_in_1_bits_dbID      (task_s4_bits_dbID),
+    .io_in_1_bits_chiOpcode (task_s4_bits_chiOpcode),
+    .io_in_1_bits_resp      (task_s4_bits_resp),
+    .io_in_1_bits_fwdState  (task_s4_bits_fwdState),
+    .io_in_1_bits_pCrdType  (task_s4_bits_pCrdType),
+    .io_in_1_bits_traceTag  (task_s4_bits_traceTag),
+    .io_in_2_ready          (_toTXRSP_arb_io_in_2_ready),
+    .io_in_2_valid          (txrsp_s3_valid),
+    .io_in_2_bits_denied    (task_s3_bits_denied),
+    .io_in_2_bits_tgtID     (source_req_s3_tgtID),
+    .io_in_2_bits_srcID     (source_req_s3_srcID),
+    .io_in_2_bits_txnID     (task_s3_bits_txnID),
+    .io_in_2_bits_dbID      (source_req_s3_dbID),
+    .io_in_2_bits_chiOpcode (txreq_s3_bits_opcode),
+    .io_in_2_bits_resp      (source_req_s3_resp),
+    .io_in_2_bits_fwdState  (source_req_s3_fwdState),
+    .io_in_2_bits_pCrdType  (source_req_s3_pCrdType),
+    .io_in_2_bits_traceTag  (task_s3_bits_traceTag),
+    .io_out_valid           (io_toTXRSP_valid),
+    .io_out_bits_denied     (io_toTXRSP_bits_denied),
+    .io_out_bits_tgtID      (io_toTXRSP_bits_tgtID),
+    .io_out_bits_srcID      (io_toTXRSP_bits_srcID),
+    .io_out_bits_txnID      (io_toTXRSP_bits_txnID),
+    .io_out_bits_dbID       (io_toTXRSP_bits_dbID),
+    .io_out_bits_chiOpcode  (io_toTXRSP_bits_chiOpcode),
+    .io_out_bits_resp       (io_toTXRSP_bits_resp),
+    .io_out_bits_fwdState   (io_toTXRSP_bits_fwdState),
+    .io_out_bits_pCrdType   (io_toTXRSP_bits_pCrdType),
+    .io_out_bits_traceTag   (io_toTXRSP_bits_traceTag)
+  );
+  Arbiter3_TaskWithData toTXDAT_arb (
+    .io_in_0_valid                                   (chnl_valid_s5 & isTXDAT_s5),
+    .io_in_0_bits_task_channel                       (task_s5_bits_channel),
+    .io_in_0_bits_task_txChannel                     (task_s5_bits_txChannel),
+    .io_in_0_bits_task_set                           (task_s5_bits_set),
+    .io_in_0_bits_task_tag                           (task_s5_bits_tag),
+    .io_in_0_bits_task_off                           (task_s5_bits_off),
+    .io_in_0_bits_task_alias                         (task_s5_bits_alias),
+    .io_in_0_bits_task_vaddr                         (task_s5_bits_vaddr),
+    .io_in_0_bits_task_isKeyword                     (task_s5_bits_isKeyword),
+    .io_in_0_bits_task_opcode                        (task_s5_bits_opcode),
+    .io_in_0_bits_task_param                         (task_s5_bits_param),
+    .io_in_0_bits_task_size                          (task_s5_bits_size),
+    .io_in_0_bits_task_sourceId                      (task_s5_bits_sourceId),
+    .io_in_0_bits_task_bufIdx                        (task_s5_bits_bufIdx),
+    .io_in_0_bits_task_needProbeAckData              (task_s5_bits_needProbeAckData),
+    .io_in_0_bits_task_denied                        (tagError_s5),
+    .io_in_0_bits_task_corrupt
+      (task_s5_bits_corrupt | dataError_s5),
+    .io_in_0_bits_task_mshrTask                      (task_s5_bits_mshrTask),
+    .io_in_0_bits_task_mshrId                        (task_s5_bits_mshrId),
+    .io_in_0_bits_task_aliasTask                     (task_s5_bits_aliasTask),
+    .io_in_0_bits_task_useProbeData                  (task_s5_bits_useProbeData),
+    .io_in_0_bits_task_mshrRetry                     (task_s5_bits_mshrRetry),
+    .io_in_0_bits_task_readProbeDataDown             (task_s5_bits_readProbeDataDown),
+    .io_in_0_bits_task_fromL2pft                     (task_s5_bits_fromL2pft),
+    .io_in_0_bits_task_needHint                      (task_s5_bits_needHint),
+    .io_in_0_bits_task_dirty                         (task_s5_bits_dirty),
+    .io_in_0_bits_task_way                           (task_s5_bits_way),
+    .io_in_0_bits_task_meta_dirty                    (task_s5_bits_meta_dirty),
+    .io_in_0_bits_task_meta_state                    (task_s5_bits_meta_state),
+    .io_in_0_bits_task_meta_clients                  (task_s5_bits_meta_clients),
+    .io_in_0_bits_task_meta_alias                    (task_s5_bits_meta_alias),
+    .io_in_0_bits_task_meta_prefetch                 (task_s5_bits_meta_prefetch),
+    .io_in_0_bits_task_meta_prefetchSrc              (task_s5_bits_meta_prefetchSrc),
+    .io_in_0_bits_task_meta_accessed                 (task_s5_bits_meta_accessed),
+    .io_in_0_bits_task_meta_tagErr                   (task_s5_bits_meta_tagErr),
+    .io_in_0_bits_task_meta_dataErr                  (task_s5_bits_meta_dataErr),
+    .io_in_0_bits_task_metaWen                       (task_s5_bits_metaWen),
+    .io_in_0_bits_task_tagWen                        (task_s5_bits_tagWen),
+    .io_in_0_bits_task_dsWen                         (task_s5_bits_dsWen),
+    .io_in_0_bits_task_wayMask                       (task_s5_bits_wayMask),
+    .io_in_0_bits_task_replTask                      (task_s5_bits_replTask),
+    .io_in_0_bits_task_cmoTask                       (task_s5_bits_cmoTask),
+    .io_in_0_bits_task_cmoAll                        (task_s5_bits_cmoAll),
+    .io_in_0_bits_task_reqSource                     (task_s5_bits_reqSource),
+    .io_in_0_bits_task_mergeA                        (task_s5_bits_mergeA),
+    .io_in_0_bits_task_aMergeTask_off                (task_s5_bits_aMergeTask_off),
+    .io_in_0_bits_task_aMergeTask_alias              (task_s5_bits_aMergeTask_alias),
+    .io_in_0_bits_task_aMergeTask_vaddr              (task_s5_bits_aMergeTask_vaddr),
+    .io_in_0_bits_task_aMergeTask_isKeyword          (task_s5_bits_aMergeTask_isKeyword),
+    .io_in_0_bits_task_aMergeTask_opcode             (task_s5_bits_aMergeTask_opcode),
+    .io_in_0_bits_task_aMergeTask_param              (task_s5_bits_aMergeTask_param),
+    .io_in_0_bits_task_aMergeTask_sourceId           (task_s5_bits_aMergeTask_sourceId),
+    .io_in_0_bits_task_aMergeTask_meta_dirty         (task_s5_bits_aMergeTask_meta_dirty),
+    .io_in_0_bits_task_aMergeTask_meta_state         (task_s5_bits_aMergeTask_meta_state),
+    .io_in_0_bits_task_aMergeTask_meta_clients
+      (task_s5_bits_aMergeTask_meta_clients),
+    .io_in_0_bits_task_aMergeTask_meta_alias         (task_s5_bits_aMergeTask_meta_alias),
+    .io_in_0_bits_task_aMergeTask_meta_prefetch
+      (task_s5_bits_aMergeTask_meta_prefetch),
+    .io_in_0_bits_task_aMergeTask_meta_prefetchSrc
+      (task_s5_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_0_bits_task_aMergeTask_meta_accessed
+      (task_s5_bits_aMergeTask_meta_accessed),
+    .io_in_0_bits_task_aMergeTask_meta_tagErr
+      (task_s5_bits_aMergeTask_meta_tagErr),
+    .io_in_0_bits_task_aMergeTask_meta_dataErr
+      (task_s5_bits_aMergeTask_meta_dataErr),
+    .io_in_0_bits_task_snpHitRelease                 (task_s5_bits_snpHitRelease),
+    .io_in_0_bits_task_snpHitReleaseToInval          (task_s5_bits_snpHitReleaseToInval),
+    .io_in_0_bits_task_snpHitReleaseToClean          (task_s5_bits_snpHitReleaseToClean),
+    .io_in_0_bits_task_snpHitReleaseWithData         (task_s5_bits_snpHitReleaseWithData),
+    .io_in_0_bits_task_snpHitReleaseIdx              (task_s5_bits_snpHitReleaseIdx),
+    .io_in_0_bits_task_snpHitReleaseMeta_dirty
+      (task_s5_bits_snpHitReleaseMeta_dirty),
+    .io_in_0_bits_task_snpHitReleaseMeta_state
+      (task_s5_bits_snpHitReleaseMeta_state),
+    .io_in_0_bits_task_snpHitReleaseMeta_clients
+      (task_s5_bits_snpHitReleaseMeta_clients),
+    .io_in_0_bits_task_snpHitReleaseMeta_alias
+      (task_s5_bits_snpHitReleaseMeta_alias),
+    .io_in_0_bits_task_snpHitReleaseMeta_prefetch
+      (task_s5_bits_snpHitReleaseMeta_prefetch),
+    .io_in_0_bits_task_snpHitReleaseMeta_prefetchSrc
+      (task_s5_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_0_bits_task_snpHitReleaseMeta_accessed
+      (task_s5_bits_snpHitReleaseMeta_accessed),
+    .io_in_0_bits_task_snpHitReleaseMeta_tagErr
+      (task_s5_bits_snpHitReleaseMeta_tagErr),
+    .io_in_0_bits_task_snpHitReleaseMeta_dataErr
+      (task_s5_bits_snpHitReleaseMeta_dataErr),
+    .io_in_0_bits_task_tgtID                         (task_s5_bits_tgtID),
+    .io_in_0_bits_task_srcID                         (task_s5_bits_srcID),
+    .io_in_0_bits_task_txnID                         (task_s5_bits_txnID),
+    .io_in_0_bits_task_homeNID                       (task_s5_bits_homeNID),
+    .io_in_0_bits_task_dbID                          (task_s5_bits_dbID),
+    .io_in_0_bits_task_fwdNID                        (task_s5_bits_fwdNID),
+    .io_in_0_bits_task_fwdTxnID                      (task_s5_bits_fwdTxnID),
+    .io_in_0_bits_task_chiOpcode                     (task_s5_bits_chiOpcode),
+    .io_in_0_bits_task_resp                          (task_s5_bits_resp),
+    .io_in_0_bits_task_fwdState                      (task_s5_bits_fwdState),
+    .io_in_0_bits_task_pCrdType                      (task_s5_bits_pCrdType),
+    .io_in_0_bits_task_retToSrc                      (task_s5_bits_retToSrc),
+    .io_in_0_bits_task_likelyshared                  (task_s5_bits_likelyshared),
+    .io_in_0_bits_task_expCompAck                    (task_s5_bits_expCompAck),
+    .io_in_0_bits_task_allowRetry                    (task_s5_bits_allowRetry),
+    .io_in_0_bits_task_memAttr_allocate              (task_s5_bits_memAttr_allocate),
+    .io_in_0_bits_task_memAttr_cacheable             (task_s5_bits_memAttr_cacheable),
+    .io_in_0_bits_task_memAttr_device                (task_s5_bits_memAttr_device),
+    .io_in_0_bits_task_memAttr_ewa                   (task_s5_bits_memAttr_ewa),
+    .io_in_0_bits_task_traceTag                      (task_s5_bits_traceTag),
+    .io_in_0_bits_data_data                          (out_data_s5),
+    .io_in_1_ready                                   (_toTXDAT_arb_io_in_1_ready),
+    .io_in_1_valid                                   (txdat_s4_valid),
+    .io_in_1_bits_task_channel                       (task_s4_bits_channel),
+    .io_in_1_bits_task_txChannel                     (task_s4_bits_txChannel),
+    .io_in_1_bits_task_set                           (task_s4_bits_set),
+    .io_in_1_bits_task_tag                           (task_s4_bits_tag),
+    .io_in_1_bits_task_off                           (task_s4_bits_off),
+    .io_in_1_bits_task_alias                         (task_s4_bits_alias),
+    .io_in_1_bits_task_vaddr                         (task_s4_bits_vaddr),
+    .io_in_1_bits_task_isKeyword                     (task_s4_bits_isKeyword),
+    .io_in_1_bits_task_opcode                        (task_s4_bits_opcode),
+    .io_in_1_bits_task_param                         (task_s4_bits_param),
+    .io_in_1_bits_task_size                          (task_s4_bits_size),
+    .io_in_1_bits_task_sourceId                      (task_s4_bits_sourceId),
+    .io_in_1_bits_task_bufIdx                        (task_s4_bits_bufIdx),
+    .io_in_1_bits_task_needProbeAckData              (task_s4_bits_needProbeAckData),
+    .io_in_1_bits_task_denied                        (task_s4_bits_denied),
+    .io_in_1_bits_task_corrupt                       (task_s4_bits_corrupt),
+    .io_in_1_bits_task_mshrTask                      (task_s4_bits_mshrTask),
+    .io_in_1_bits_task_mshrId                        (task_s4_bits_mshrId),
+    .io_in_1_bits_task_aliasTask                     (task_s4_bits_aliasTask),
+    .io_in_1_bits_task_useProbeData                  (task_s4_bits_useProbeData),
+    .io_in_1_bits_task_mshrRetry                     (task_s4_bits_mshrRetry),
+    .io_in_1_bits_task_readProbeDataDown             (task_s4_bits_readProbeDataDown),
+    .io_in_1_bits_task_fromL2pft                     (task_s4_bits_fromL2pft),
+    .io_in_1_bits_task_needHint                      (task_s4_bits_needHint),
+    .io_in_1_bits_task_dirty                         (task_s4_bits_dirty),
+    .io_in_1_bits_task_way                           (task_s4_bits_way),
+    .io_in_1_bits_task_meta_dirty                    (task_s4_bits_meta_dirty),
+    .io_in_1_bits_task_meta_state                    (task_s4_bits_meta_state),
+    .io_in_1_bits_task_meta_clients                  (task_s4_bits_meta_clients),
+    .io_in_1_bits_task_meta_alias                    (task_s4_bits_meta_alias),
+    .io_in_1_bits_task_meta_prefetch                 (task_s4_bits_meta_prefetch),
+    .io_in_1_bits_task_meta_prefetchSrc              (task_s4_bits_meta_prefetchSrc),
+    .io_in_1_bits_task_meta_accessed                 (task_s4_bits_meta_accessed),
+    .io_in_1_bits_task_meta_tagErr                   (task_s4_bits_meta_tagErr),
+    .io_in_1_bits_task_meta_dataErr                  (task_s4_bits_meta_dataErr),
+    .io_in_1_bits_task_metaWen                       (task_s4_bits_metaWen),
+    .io_in_1_bits_task_tagWen                        (task_s4_bits_tagWen),
+    .io_in_1_bits_task_dsWen                         (task_s4_bits_dsWen),
+    .io_in_1_bits_task_wayMask                       (task_s4_bits_wayMask),
+    .io_in_1_bits_task_replTask                      (task_s4_bits_replTask),
+    .io_in_1_bits_task_cmoTask                       (task_s4_bits_cmoTask),
+    .io_in_1_bits_task_cmoAll                        (task_s4_bits_cmoAll),
+    .io_in_1_bits_task_reqSource                     (task_s4_bits_reqSource),
+    .io_in_1_bits_task_mergeA                        (task_s4_bits_mergeA),
+    .io_in_1_bits_task_aMergeTask_off                (task_s4_bits_aMergeTask_off),
+    .io_in_1_bits_task_aMergeTask_alias              (task_s4_bits_aMergeTask_alias),
+    .io_in_1_bits_task_aMergeTask_vaddr              (task_s4_bits_aMergeTask_vaddr),
+    .io_in_1_bits_task_aMergeTask_isKeyword          (task_s4_bits_aMergeTask_isKeyword),
+    .io_in_1_bits_task_aMergeTask_opcode             (task_s4_bits_aMergeTask_opcode),
+    .io_in_1_bits_task_aMergeTask_param              (task_s4_bits_aMergeTask_param),
+    .io_in_1_bits_task_aMergeTask_sourceId           (task_s4_bits_aMergeTask_sourceId),
+    .io_in_1_bits_task_aMergeTask_meta_dirty         (task_s4_bits_aMergeTask_meta_dirty),
+    .io_in_1_bits_task_aMergeTask_meta_state         (task_s4_bits_aMergeTask_meta_state),
+    .io_in_1_bits_task_aMergeTask_meta_clients
+      (task_s4_bits_aMergeTask_meta_clients),
+    .io_in_1_bits_task_aMergeTask_meta_alias         (task_s4_bits_aMergeTask_meta_alias),
+    .io_in_1_bits_task_aMergeTask_meta_prefetch
+      (task_s4_bits_aMergeTask_meta_prefetch),
+    .io_in_1_bits_task_aMergeTask_meta_prefetchSrc
+      (task_s4_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_1_bits_task_aMergeTask_meta_accessed
+      (task_s4_bits_aMergeTask_meta_accessed),
+    .io_in_1_bits_task_aMergeTask_meta_tagErr
+      (task_s4_bits_aMergeTask_meta_tagErr),
+    .io_in_1_bits_task_aMergeTask_meta_dataErr
+      (task_s4_bits_aMergeTask_meta_dataErr),
+    .io_in_1_bits_task_snpHitRelease                 (task_s4_bits_snpHitRelease),
+    .io_in_1_bits_task_snpHitReleaseToInval          (task_s4_bits_snpHitReleaseToInval),
+    .io_in_1_bits_task_snpHitReleaseToClean          (task_s4_bits_snpHitReleaseToClean),
+    .io_in_1_bits_task_snpHitReleaseWithData         (task_s4_bits_snpHitReleaseWithData),
+    .io_in_1_bits_task_snpHitReleaseIdx              (task_s4_bits_snpHitReleaseIdx),
+    .io_in_1_bits_task_snpHitReleaseMeta_dirty
+      (task_s4_bits_snpHitReleaseMeta_dirty),
+    .io_in_1_bits_task_snpHitReleaseMeta_state
+      (task_s4_bits_snpHitReleaseMeta_state),
+    .io_in_1_bits_task_snpHitReleaseMeta_clients
+      (task_s4_bits_snpHitReleaseMeta_clients),
+    .io_in_1_bits_task_snpHitReleaseMeta_alias
+      (task_s4_bits_snpHitReleaseMeta_alias),
+    .io_in_1_bits_task_snpHitReleaseMeta_prefetch
+      (task_s4_bits_snpHitReleaseMeta_prefetch),
+    .io_in_1_bits_task_snpHitReleaseMeta_prefetchSrc
+      (task_s4_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_1_bits_task_snpHitReleaseMeta_accessed
+      (task_s4_bits_snpHitReleaseMeta_accessed),
+    .io_in_1_bits_task_snpHitReleaseMeta_tagErr
+      (task_s4_bits_snpHitReleaseMeta_tagErr),
+    .io_in_1_bits_task_snpHitReleaseMeta_dataErr
+      (task_s4_bits_snpHitReleaseMeta_dataErr),
+    .io_in_1_bits_task_tgtID                         (task_s4_bits_tgtID),
+    .io_in_1_bits_task_srcID                         (task_s4_bits_srcID),
+    .io_in_1_bits_task_txnID                         (task_s4_bits_txnID),
+    .io_in_1_bits_task_homeNID                       (task_s4_bits_homeNID),
+    .io_in_1_bits_task_dbID                          (task_s4_bits_dbID),
+    .io_in_1_bits_task_fwdNID                        (task_s4_bits_fwdNID),
+    .io_in_1_bits_task_fwdTxnID                      (task_s4_bits_fwdTxnID),
+    .io_in_1_bits_task_chiOpcode                     (task_s4_bits_chiOpcode),
+    .io_in_1_bits_task_resp                          (task_s4_bits_resp),
+    .io_in_1_bits_task_fwdState                      (task_s4_bits_fwdState),
+    .io_in_1_bits_task_pCrdType                      (task_s4_bits_pCrdType),
+    .io_in_1_bits_task_retToSrc                      (task_s4_bits_retToSrc),
+    .io_in_1_bits_task_likelyshared                  (task_s4_bits_likelyshared),
+    .io_in_1_bits_task_expCompAck                    (task_s4_bits_expCompAck),
+    .io_in_1_bits_task_allowRetry                    (task_s4_bits_allowRetry),
+    .io_in_1_bits_task_memAttr_allocate              (task_s4_bits_memAttr_allocate),
+    .io_in_1_bits_task_memAttr_cacheable             (task_s4_bits_memAttr_cacheable),
+    .io_in_1_bits_task_memAttr_device                (task_s4_bits_memAttr_device),
+    .io_in_1_bits_task_memAttr_ewa                   (task_s4_bits_memAttr_ewa),
+    .io_in_1_bits_task_traceTag                      (task_s4_bits_traceTag),
+    .io_in_1_bits_data_data                          (data_s4),
+    .io_in_2_ready                                   (_toTXDAT_arb_io_in_2_ready),
+    .io_in_2_valid                                   (txdat_s3_valid),
+    .io_in_2_bits_task_channel                       (task_s3_bits_channel),
+    .io_in_2_bits_task_txChannel                     (source_req_s3_txChannel),
+    .io_in_2_bits_task_set                           (task_s3_bits_set),
+    .io_in_2_bits_task_tag                           (task_s3_bits_tag),
+    .io_in_2_bits_task_off                           (task_s3_bits_off),
+    .io_in_2_bits_task_alias                         (task_s3_bits_alias),
+    .io_in_2_bits_task_vaddr                         (task_s3_bits_vaddr),
+    .io_in_2_bits_task_isKeyword                     (task_s3_bits_isKeyword),
+    .io_in_2_bits_task_opcode                        (source_req_s3_opcode),
+    .io_in_2_bits_task_param                         (source_req_s3_param),
+    .io_in_2_bits_task_size                          (source_req_s3_size),
+    .io_in_2_bits_task_sourceId                      (task_s3_bits_sourceId),
+    .io_in_2_bits_task_bufIdx                        (task_s3_bits_bufIdx),
+    .io_in_2_bits_task_needProbeAckData              (task_s3_bits_needProbeAckData),
+    .io_in_2_bits_task_denied                        (task_s3_bits_denied),
+    .io_in_2_bits_task_corrupt                       (task_s3_bits_corrupt),
+    .io_in_2_bits_task_mshrTask                      (task_s3_bits_mshrTask),
+    .io_in_2_bits_task_mshrId                        (source_req_s3_mshrId),
+    .io_in_2_bits_task_aliasTask                     (task_s3_bits_aliasTask),
+    .io_in_2_bits_task_useProbeData                  (task_s3_bits_useProbeData),
+    .io_in_2_bits_task_mshrRetry                     (task_s3_bits_mshrRetry),
+    .io_in_2_bits_task_readProbeDataDown             (task_s3_bits_readProbeDataDown),
+    .io_in_2_bits_task_fromL2pft                     (task_s3_bits_fromL2pft),
+    .io_in_2_bits_task_needHint                      (task_s3_bits_needHint),
+    .io_in_2_bits_task_dirty                         (task_s3_bits_dirty),
+    .io_in_2_bits_task_way                           (task_s3_bits_way),
+    .io_in_2_bits_task_meta_dirty                    (source_req_s3_meta_dirty),
+    .io_in_2_bits_task_meta_state                    (source_req_s3_meta_state),
+    .io_in_2_bits_task_meta_clients                  (source_req_s3_meta_clients),
+    .io_in_2_bits_task_meta_alias                    (source_req_s3_meta_alias),
+    .io_in_2_bits_task_meta_prefetch                 (source_req_s3_meta_prefetch),
+    .io_in_2_bits_task_meta_prefetchSrc              (source_req_s3_meta_prefetchSrc),
+    .io_in_2_bits_task_meta_accessed                 (source_req_s3_meta_accessed),
+    .io_in_2_bits_task_meta_tagErr                   (source_req_s3_meta_tagErr),
+    .io_in_2_bits_task_meta_dataErr                  (source_req_s3_meta_dataErr),
+    .io_in_2_bits_task_metaWen                       (source_req_s3_metaWen),
+    .io_in_2_bits_task_tagWen                        (task_s3_bits_tagWen),
+    .io_in_2_bits_task_dsWen                         (task_s3_bits_dsWen),
+    .io_in_2_bits_task_wayMask                       (task_s3_bits_wayMask),
+    .io_in_2_bits_task_replTask                      (task_s3_bits_replTask),
+    .io_in_2_bits_task_cmoTask                       (task_s3_bits_cmoTask),
+    .io_in_2_bits_task_cmoAll                        (task_s3_bits_cmoAll),
+    .io_in_2_bits_task_reqSource                     (task_s3_bits_reqSource),
+    .io_in_2_bits_task_mergeA                        (task_s3_bits_mergeA),
+    .io_in_2_bits_task_aMergeTask_off                (task_s3_bits_aMergeTask_off),
+    .io_in_2_bits_task_aMergeTask_alias              (task_s3_bits_aMergeTask_alias),
+    .io_in_2_bits_task_aMergeTask_vaddr              (task_s3_bits_aMergeTask_vaddr),
+    .io_in_2_bits_task_aMergeTask_isKeyword          (task_s3_bits_aMergeTask_isKeyword),
+    .io_in_2_bits_task_aMergeTask_opcode             (task_s3_bits_aMergeTask_opcode),
+    .io_in_2_bits_task_aMergeTask_param              (task_s3_bits_aMergeTask_param),
+    .io_in_2_bits_task_aMergeTask_sourceId           (task_s3_bits_aMergeTask_sourceId),
+    .io_in_2_bits_task_aMergeTask_meta_dirty         (task_s3_bits_aMergeTask_meta_dirty),
+    .io_in_2_bits_task_aMergeTask_meta_state         (task_s3_bits_aMergeTask_meta_state),
+    .io_in_2_bits_task_aMergeTask_meta_clients
+      (task_s3_bits_aMergeTask_meta_clients),
+    .io_in_2_bits_task_aMergeTask_meta_alias         (task_s3_bits_aMergeTask_meta_alias),
+    .io_in_2_bits_task_aMergeTask_meta_prefetch
+      (task_s3_bits_aMergeTask_meta_prefetch),
+    .io_in_2_bits_task_aMergeTask_meta_prefetchSrc
+      (task_s3_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_2_bits_task_aMergeTask_meta_accessed
+      (task_s3_bits_aMergeTask_meta_accessed),
+    .io_in_2_bits_task_aMergeTask_meta_tagErr
+      (task_s3_bits_aMergeTask_meta_tagErr),
+    .io_in_2_bits_task_aMergeTask_meta_dataErr
+      (task_s3_bits_aMergeTask_meta_dataErr),
+    .io_in_2_bits_task_snpHitRelease                 (task_s3_bits_snpHitRelease),
+    .io_in_2_bits_task_snpHitReleaseToInval          (task_s3_bits_snpHitReleaseToInval),
+    .io_in_2_bits_task_snpHitReleaseToClean          (task_s3_bits_snpHitReleaseToClean),
+    .io_in_2_bits_task_snpHitReleaseWithData         (task_s3_bits_snpHitReleaseWithData),
+    .io_in_2_bits_task_snpHitReleaseIdx              (task_s3_bits_snpHitReleaseIdx),
+    .io_in_2_bits_task_snpHitReleaseMeta_dirty
+      (task_s3_bits_snpHitReleaseMeta_dirty),
+    .io_in_2_bits_task_snpHitReleaseMeta_state
+      (task_s3_bits_snpHitReleaseMeta_state),
+    .io_in_2_bits_task_snpHitReleaseMeta_clients
+      (task_s3_bits_snpHitReleaseMeta_clients),
+    .io_in_2_bits_task_snpHitReleaseMeta_alias
+      (task_s3_bits_snpHitReleaseMeta_alias),
+    .io_in_2_bits_task_snpHitReleaseMeta_prefetch
+      (task_s3_bits_snpHitReleaseMeta_prefetch),
+    .io_in_2_bits_task_snpHitReleaseMeta_prefetchSrc
+      (task_s3_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_2_bits_task_snpHitReleaseMeta_accessed
+      (task_s3_bits_snpHitReleaseMeta_accessed),
+    .io_in_2_bits_task_snpHitReleaseMeta_tagErr
+      (task_s3_bits_snpHitReleaseMeta_tagErr),
+    .io_in_2_bits_task_snpHitReleaseMeta_dataErr
+      (task_s3_bits_snpHitReleaseMeta_dataErr),
+    .io_in_2_bits_task_tgtID                         (source_req_s3_tgtID),
+    .io_in_2_bits_task_srcID                         (source_req_s3_srcID),
+    .io_in_2_bits_task_txnID                         (task_s3_bits_txnID),
+    .io_in_2_bits_task_homeNID                       (task_s3_bits_homeNID),
+    .io_in_2_bits_task_dbID                          (source_req_s3_dbID),
+    .io_in_2_bits_task_fwdNID                        (task_s3_bits_fwdNID),
+    .io_in_2_bits_task_fwdTxnID                      (task_s3_bits_fwdTxnID),
+    .io_in_2_bits_task_chiOpcode                     (txreq_s3_bits_opcode),
+    .io_in_2_bits_task_resp                          (source_req_s3_resp),
+    .io_in_2_bits_task_fwdState                      (source_req_s3_fwdState),
+    .io_in_2_bits_task_pCrdType                      (source_req_s3_pCrdType),
+    .io_in_2_bits_task_retToSrc                      (task_s3_bits_retToSrc),
+    .io_in_2_bits_task_likelyshared                  (task_s3_bits_likelyshared),
+    .io_in_2_bits_task_expCompAck                    (task_s3_bits_expCompAck),
+    .io_in_2_bits_task_allowRetry                    (task_s3_bits_allowRetry),
+    .io_in_2_bits_task_memAttr_allocate              (task_s3_bits_memAttr_allocate),
+    .io_in_2_bits_task_memAttr_cacheable             (task_s3_bits_memAttr_cacheable),
+    .io_in_2_bits_task_memAttr_device                (task_s3_bits_memAttr_device),
+    .io_in_2_bits_task_memAttr_ewa                   (task_s3_bits_memAttr_ewa),
+    .io_in_2_bits_task_traceTag                      (task_s3_bits_traceTag),
+    .io_in_2_bits_data_data                          (data_s3),
+    .io_out_ready                                    (io_toTXDAT_ready),
+    .io_out_valid                                    (io_toTXDAT_valid),
+    .io_out_bits_task_channel                        (io_toTXDAT_bits_task_channel),
+    .io_out_bits_task_txChannel                      (io_toTXDAT_bits_task_txChannel),
+    .io_out_bits_task_set                            (io_toTXDAT_bits_task_set),
+    .io_out_bits_task_tag                            (io_toTXDAT_bits_task_tag),
+    .io_out_bits_task_off                            (io_toTXDAT_bits_task_off),
+    .io_out_bits_task_alias                          (io_toTXDAT_bits_task_alias),
+    .io_out_bits_task_vaddr                          (io_toTXDAT_bits_task_vaddr),
+    .io_out_bits_task_isKeyword                      (io_toTXDAT_bits_task_isKeyword),
+    .io_out_bits_task_opcode                         (io_toTXDAT_bits_task_opcode),
+    .io_out_bits_task_param                          (io_toTXDAT_bits_task_param),
+    .io_out_bits_task_size                           (io_toTXDAT_bits_task_size),
+    .io_out_bits_task_sourceId                       (io_toTXDAT_bits_task_sourceId),
+    .io_out_bits_task_bufIdx                         (io_toTXDAT_bits_task_bufIdx),
+    .io_out_bits_task_needProbeAckData
+      (io_toTXDAT_bits_task_needProbeAckData),
+    .io_out_bits_task_denied                         (io_toTXDAT_bits_task_denied),
+    .io_out_bits_task_corrupt                        (io_toTXDAT_bits_task_corrupt),
+    .io_out_bits_task_mshrTask                       (io_toTXDAT_bits_task_mshrTask),
+    .io_out_bits_task_mshrId                         (io_toTXDAT_bits_task_mshrId),
+    .io_out_bits_task_aliasTask                      (io_toTXDAT_bits_task_aliasTask),
+    .io_out_bits_task_useProbeData                   (io_toTXDAT_bits_task_useProbeData),
+    .io_out_bits_task_mshrRetry                      (io_toTXDAT_bits_task_mshrRetry),
+    .io_out_bits_task_readProbeDataDown
+      (io_toTXDAT_bits_task_readProbeDataDown),
+    .io_out_bits_task_fromL2pft                      (io_toTXDAT_bits_task_fromL2pft),
+    .io_out_bits_task_needHint                       (io_toTXDAT_bits_task_needHint),
+    .io_out_bits_task_dirty                          (io_toTXDAT_bits_task_dirty),
+    .io_out_bits_task_way                            (io_toTXDAT_bits_task_way),
+    .io_out_bits_task_meta_dirty                     (io_toTXDAT_bits_task_meta_dirty),
+    .io_out_bits_task_meta_state                     (io_toTXDAT_bits_task_meta_state),
+    .io_out_bits_task_meta_clients                   (io_toTXDAT_bits_task_meta_clients),
+    .io_out_bits_task_meta_alias                     (io_toTXDAT_bits_task_meta_alias),
+    .io_out_bits_task_meta_prefetch                  (io_toTXDAT_bits_task_meta_prefetch),
+    .io_out_bits_task_meta_prefetchSrc
+      (io_toTXDAT_bits_task_meta_prefetchSrc),
+    .io_out_bits_task_meta_accessed                  (io_toTXDAT_bits_task_meta_accessed),
+    .io_out_bits_task_meta_tagErr                    (io_toTXDAT_bits_task_meta_tagErr),
+    .io_out_bits_task_meta_dataErr                   (io_toTXDAT_bits_task_meta_dataErr),
+    .io_out_bits_task_metaWen                        (io_toTXDAT_bits_task_metaWen),
+    .io_out_bits_task_tagWen                         (io_toTXDAT_bits_task_tagWen),
+    .io_out_bits_task_dsWen                          (io_toTXDAT_bits_task_dsWen),
+    .io_out_bits_task_wayMask                        (io_toTXDAT_bits_task_wayMask),
+    .io_out_bits_task_replTask                       (io_toTXDAT_bits_task_replTask),
+    .io_out_bits_task_cmoTask                        (io_toTXDAT_bits_task_cmoTask),
+    .io_out_bits_task_cmoAll                         (io_toTXDAT_bits_task_cmoAll),
+    .io_out_bits_task_reqSource                      (io_toTXDAT_bits_task_reqSource),
+    .io_out_bits_task_mergeA                         (io_toTXDAT_bits_task_mergeA),
+    .io_out_bits_task_aMergeTask_off
+      (io_toTXDAT_bits_task_aMergeTask_off),
+    .io_out_bits_task_aMergeTask_alias
+      (io_toTXDAT_bits_task_aMergeTask_alias),
+    .io_out_bits_task_aMergeTask_vaddr
+      (io_toTXDAT_bits_task_aMergeTask_vaddr),
+    .io_out_bits_task_aMergeTask_isKeyword
+      (io_toTXDAT_bits_task_aMergeTask_isKeyword),
+    .io_out_bits_task_aMergeTask_opcode
+      (io_toTXDAT_bits_task_aMergeTask_opcode),
+    .io_out_bits_task_aMergeTask_param
+      (io_toTXDAT_bits_task_aMergeTask_param),
+    .io_out_bits_task_aMergeTask_sourceId
+      (io_toTXDAT_bits_task_aMergeTask_sourceId),
+    .io_out_bits_task_aMergeTask_meta_dirty
+      (io_toTXDAT_bits_task_aMergeTask_meta_dirty),
+    .io_out_bits_task_aMergeTask_meta_state
+      (io_toTXDAT_bits_task_aMergeTask_meta_state),
+    .io_out_bits_task_aMergeTask_meta_clients
+      (io_toTXDAT_bits_task_aMergeTask_meta_clients),
+    .io_out_bits_task_aMergeTask_meta_alias
+      (io_toTXDAT_bits_task_aMergeTask_meta_alias),
+    .io_out_bits_task_aMergeTask_meta_prefetch
+      (io_toTXDAT_bits_task_aMergeTask_meta_prefetch),
+    .io_out_bits_task_aMergeTask_meta_prefetchSrc
+      (io_toTXDAT_bits_task_aMergeTask_meta_prefetchSrc),
+    .io_out_bits_task_aMergeTask_meta_accessed
+      (io_toTXDAT_bits_task_aMergeTask_meta_accessed),
+    .io_out_bits_task_aMergeTask_meta_tagErr
+      (io_toTXDAT_bits_task_aMergeTask_meta_tagErr),
+    .io_out_bits_task_aMergeTask_meta_dataErr
+      (io_toTXDAT_bits_task_aMergeTask_meta_dataErr),
+    .io_out_bits_task_snpHitRelease                  (io_toTXDAT_bits_task_snpHitRelease),
+    .io_out_bits_task_snpHitReleaseToInval
+      (io_toTXDAT_bits_task_snpHitReleaseToInval),
+    .io_out_bits_task_snpHitReleaseToClean
+      (io_toTXDAT_bits_task_snpHitReleaseToClean),
+    .io_out_bits_task_snpHitReleaseWithData
+      (io_toTXDAT_bits_task_snpHitReleaseWithData),
+    .io_out_bits_task_snpHitReleaseIdx
+      (io_toTXDAT_bits_task_snpHitReleaseIdx),
+    .io_out_bits_task_snpHitReleaseMeta_dirty
+      (io_toTXDAT_bits_task_snpHitReleaseMeta_dirty),
+    .io_out_bits_task_snpHitReleaseMeta_state
+      (io_toTXDAT_bits_task_snpHitReleaseMeta_state),
+    .io_out_bits_task_snpHitReleaseMeta_clients
+      (io_toTXDAT_bits_task_snpHitReleaseMeta_clients),
+    .io_out_bits_task_snpHitReleaseMeta_alias
+      (io_toTXDAT_bits_task_snpHitReleaseMeta_alias),
+    .io_out_bits_task_snpHitReleaseMeta_prefetch
+      (io_toTXDAT_bits_task_snpHitReleaseMeta_prefetch),
+    .io_out_bits_task_snpHitReleaseMeta_prefetchSrc
+      (io_toTXDAT_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_out_bits_task_snpHitReleaseMeta_accessed
+      (io_toTXDAT_bits_task_snpHitReleaseMeta_accessed),
+    .io_out_bits_task_snpHitReleaseMeta_tagErr
+      (io_toTXDAT_bits_task_snpHitReleaseMeta_tagErr),
+    .io_out_bits_task_snpHitReleaseMeta_dataErr
+      (io_toTXDAT_bits_task_snpHitReleaseMeta_dataErr),
+    .io_out_bits_task_tgtID                          (io_toTXDAT_bits_task_tgtID),
+    .io_out_bits_task_srcID                          (io_toTXDAT_bits_task_srcID),
+    .io_out_bits_task_txnID                          (io_toTXDAT_bits_task_txnID),
+    .io_out_bits_task_homeNID                        (io_toTXDAT_bits_task_homeNID),
+    .io_out_bits_task_dbID                           (io_toTXDAT_bits_task_dbID),
+    .io_out_bits_task_fwdNID                         (io_toTXDAT_bits_task_fwdNID),
+    .io_out_bits_task_fwdTxnID                       (io_toTXDAT_bits_task_fwdTxnID),
+    .io_out_bits_task_chiOpcode                      (io_toTXDAT_bits_task_chiOpcode),
+    .io_out_bits_task_resp                           (io_toTXDAT_bits_task_resp),
+    .io_out_bits_task_fwdState                       (io_toTXDAT_bits_task_fwdState),
+    .io_out_bits_task_pCrdType                       (io_toTXDAT_bits_task_pCrdType),
+    .io_out_bits_task_retToSrc                       (io_toTXDAT_bits_task_retToSrc),
+    .io_out_bits_task_likelyshared                   (io_toTXDAT_bits_task_likelyshared),
+    .io_out_bits_task_expCompAck                     (io_toTXDAT_bits_task_expCompAck),
+    .io_out_bits_task_allowRetry                     (io_toTXDAT_bits_task_allowRetry),
+    .io_out_bits_task_memAttr_allocate
+      (io_toTXDAT_bits_task_memAttr_allocate),
+    .io_out_bits_task_memAttr_cacheable
+      (io_toTXDAT_bits_task_memAttr_cacheable),
+    .io_out_bits_task_memAttr_device
+      (io_toTXDAT_bits_task_memAttr_device),
+    .io_out_bits_task_memAttr_ewa                    (io_toTXDAT_bits_task_memAttr_ewa),
+    .io_out_bits_task_traceTag                       (io_toTXDAT_bits_task_traceTag),
+    .io_out_bits_data_data                           (io_toTXDAT_bits_data_data)
+  );
+  assign io_toReqArb_blockG_s1 =
+    io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_set == io_fromReqArb_status_s1_sets_3
+    & ~(io_taskFromArb_s2_bits_mshrTask & ~io_taskFromArb_s2_bits_metaWen);
+  assign io_toReqArb_blockB_s1 =
+    io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_set == io_fromReqArb_status_s1_sets_1
+    | task_s3_valid & task_s3_bits_set == io_fromReqArb_status_s1_sets_1 | task_s4_valid
+    & task_s4_bits_set == io_fromReqArb_status_s1_sets_1
+    & task_s4_bits_tag == io_fromReqArb_status_s1_tags_1 | task_s5_valid
+    & task_s5_bits_set == io_fromReqArb_status_s1_sets_1
+    & task_s5_bits_tag == io_fromReqArb_status_s1_tags_1;
+  assign io_toReqArb_blockC_s1 =
+    io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_set == io_fromReqArb_status_s1_sets_0
+    & ~(io_taskFromArb_s2_bits_mshrTask & ~io_taskFromArb_s2_bits_metaWen);
+  assign io_toReqBuf_0 =
+    io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_set == io_fromReqArb_status_s1_sets_2
+    & ~(io_taskFromArb_s2_bits_mshrTask & ~io_taskFromArb_s2_bits_metaWen);
+  assign io_toReqBuf_1 =
+    task_s3_valid & task_s3_bits_set == io_fromReqArb_status_s1_sets_2
+    & ~(task_s3_bits_mshrTask & ~task_s3_bits_metaWen);
+  assign io_status_vec_toD_0_valid =
+    task_s3_valid & (~task_s3_bits_mshrTask | mshr_refill_s3 & ~retry);
+  assign io_status_vec_toD_0_bits_channel = task_s3_bits_channel;
+  assign io_status_vec_toD_1_valid = task_s4_valid & (isD_s4 | pendingD_s4);
+  assign io_status_vec_toD_1_bits_channel = task_s4_bits_channel;
+  assign io_status_vec_toD_2_valid = d_s5_valid;
+  assign io_status_vec_toD_2_bits_channel = task_s5_bits_channel;
+  assign io_status_vec_toTX_0_valid = task_s3_valid;
+  assign io_status_vec_toTX_0_bits_channel = task_s3_bits_channel;
+  assign io_status_vec_toTX_0_bits_txChannel = task_s3_bits_txChannel;
+  assign io_status_vec_toTX_0_bits_mshrTask = task_s3_bits_mshrTask;
+  assign io_status_vec_toTX_1_valid = task_s4_valid;
+  assign io_status_vec_toTX_1_bits_channel = task_s4_bits_channel;
+  assign io_status_vec_toTX_1_bits_txChannel = task_s4_bits_txChannel;
+  assign io_status_vec_toTX_1_bits_mshrTask = task_s4_bits_mshrTask;
+  assign io_status_vec_toTX_2_valid = task_s5_valid;
+  assign io_status_vec_toTX_2_bits_channel = task_s5_bits_channel;
+  assign io_status_vec_toTX_2_bits_txChannel = task_s5_bits_txChannel;
+  assign io_status_vec_toTX_2_bits_mshrTask = task_s5_bits_mshrTask;
+  assign io_toMSHRCtl_mshr_alloc_s3_valid =
+    task_s3_valid & ~task_s3_bits_mshrTask & need_mshr_s3;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_hit = nestable_dirResult_s3_hit;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_tag =
+    task_s3_bits_snpHitRelease ? task_s3_bits_tag : io_dirResp_s3_tag;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_set =
+    task_s3_bits_snpHitRelease ? task_s3_bits_set : io_dirResp_s3_set;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_way = io_dirResp_s3_way;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dirty =
+    nestable_dirResult_s3_meta_dirty;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_state =
+    nestable_dirResult_s3_meta_state;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_clients =
+    task_s3_bits_snpHitRelease
+      ? task_s3_bits_snpHitReleaseMeta_clients
+      : io_metaOnHit_s3_clients;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_alias =
+    task_s3_bits_snpHitRelease
+      ? task_s3_bits_snpHitReleaseMeta_alias
+      : io_metaOnHit_s3_alias;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetch =
+    task_s3_bits_snpHitRelease
+      ? task_s3_bits_snpHitReleaseMeta_prefetch
+      : io_metaOnHit_s3_prefetch;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc =
+    task_s3_bits_snpHitRelease
+      ? task_s3_bits_snpHitReleaseMeta_prefetchSrc
+      : io_metaOnHit_s3_prefetchSrc;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_accessed =
+    task_s3_bits_snpHitRelease
+      ? task_s3_bits_snpHitReleaseMeta_accessed
+      : io_metaOnHit_s3_accessed;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_tagErr =
+    task_s3_bits_snpHitRelease
+      ? task_s3_bits_snpHitReleaseMeta_tagErr
+      : io_metaOnHit_s3_tagErr;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dataErr =
+    task_s3_bits_snpHitRelease
+      ? task_s3_bits_snpHitReleaseMeta_dataErr
+      : io_metaOnHit_s3_dataErr;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_error = io_dirResp_s3_error;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_s_acquire = alloc_state_w_grant;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rprobe = alloc_state_s_rprobe;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_s_pprobe = alloc_state_s_pprobe;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_s_release = alloc_state_s_release;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_s_probeack = ~(task_s3_bits_channel[1]);
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_s_refill =
+    ~(task_s3_bits_channel[0]) | cmo_cbo_s3;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_s_cmoresp =
+    ~(task_s3_bits_channel[0]) | ~cmo_cbo_s3;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeackfirst = alloc_state_s_rprobe;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeacklast = alloc_state_s_rprobe;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeackfirst = alloc_state_s_pprobe;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeacklast = alloc_state_s_pprobe;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantfirst = alloc_state_w_grant;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantlast = alloc_state_w_grant;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grant = alloc_state_w_grant;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_w_releaseack = alloc_state_s_release;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_w_replResp =
+    ~(task_s3_bits_channel[0]) | cmo_cbo_s3 | io_dirResp_s3_hit;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rcompack =
+    ~need_acquire_s3_a | cmo_cbo_s3;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_state_s_dct =
+    ~(task_s3_bits_channel[1]) | ~doFwd;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_channel = task_s3_bits_channel;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_set = task_s3_bits_set;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_tag = task_s3_bits_tag;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_off = task_s3_bits_off;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_alias = task_s3_bits_alias;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_isKeyword = task_s3_bits_isKeyword;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_opcode = task_s3_bits_opcode;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_param = task_s3_bits_param;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_sourceId = task_s3_bits_sourceId;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_aliasTask = cache_alias;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_fromL2pft = task_s3_bits_fromL2pft;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_reqSource = task_s3_bits_reqSource;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitRelease = task_s3_bits_snpHitRelease;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToInval =
+    task_s3_bits_snpHitReleaseToInval;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToClean =
+    task_s3_bits_snpHitReleaseToClean;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseWithData =
+    task_s3_bits_snpHitReleaseWithData;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseIdx =
+    task_s3_bits_snpHitReleaseIdx;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty =
+    task_s3_bits_snpHitReleaseMeta_dirty;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state =
+    task_s3_bits_snpHitReleaseMeta_state;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients =
+    task_s3_bits_snpHitReleaseMeta_clients;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias =
+    task_s3_bits_snpHitReleaseMeta_alias;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch =
+    task_s3_bits_snpHitReleaseMeta_prefetch;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc =
+    task_s3_bits_snpHitReleaseMeta_prefetchSrc;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed =
+    task_s3_bits_snpHitReleaseMeta_accessed;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr =
+    task_s3_bits_snpHitReleaseMeta_tagErr;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr =
+    task_s3_bits_snpHitReleaseMeta_dataErr;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_srcID = task_s3_bits_srcID;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_txnID = task_s3_bits_txnID;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdNID = task_s3_bits_fwdNID;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdTxnID = task_s3_bits_fwdTxnID;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_chiOpcode = task_s3_bits_chiOpcode;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_retToSrc = task_s3_bits_retToSrc;
+  assign io_toMSHRCtl_mshr_alloc_s3_bits_task_traceTag = task_s3_bits_traceTag;
+  assign io_toDS_en_s3 = task_s3_valid & _io_toDS_req_s3_valid_T;
+  assign io_toDS_req_s3_valid = task_s3_valid_hold2 & _io_toDS_req_s3_valid_T;
+  assign io_toDS_req_s3_bits_way =
+    _io_tagWReq_bits_wayOH_T
+      ? io_replResp_bits_way
+      : task_s3_bits_mshrTask ? task_s3_bits_way : io_dirResp_s3_way;
+  assign io_toDS_req_s3_bits_set = task_s3_bits_set;
+  assign io_toDS_req_s3_bits_wen = wen;
+  assign io_toDS_wdata_s3_data =
+    task_s3_bits_mshrTask
+      ? (task_s3_bits_useProbeData
+           ? io_releaseBufResp_s3_bits_data
+           : io_refillBufResp_s3_bits_data)
+      : c_releaseData_s3;
+  assign io_metaWReq_valid =
+    ~resetFinish | task_s3_valid
+    & (_io_metaWReq_bits_wmeta_T | metaW_valid_s3_c | metaW_valid_s3_mshr
+       | req_cbo_inval_s3 & io_dirResp_s3_hit);
+  assign io_metaWReq_bits_set = resetFinish ? task_s3_bits_set : resetIdx;
+  assign io_metaWReq_bits_wayOH =
+    resetFinish
+      ? (_io_tagWReq_bits_wayOH_T
+           ? io_dirReplWayOH_s3
+           : task_s3_bits_mshrTask ? reqWayOH_s3 : io_dirWayOH_s3)
+      : 8'hFF;
+  assign io_metaWReq_bits_wmeta_dirty =
+    resetFinish
+    & (_io_metaWReq_bits_wmeta_T
+         ? metaW_valid_s3_a & io_metaOnHit_s3_dirty
+         : metaW_valid_s3_c
+             ? io_metaOnHit_s3_dirty | wen_c
+             : metaW_valid_s3_mshr
+               & (task_s3_bits_mergeA
+                    ? task_s3_bits_aMergeTask_meta_dirty
+                    : task_s3_bits_meta_dirty));
+  assign io_metaWReq_bits_wmeta_state =
+    resetFinish
+      ? (_io_metaWReq_bits_wmeta_T
+           ? (metaW_valid_s3_a
+                ? (req_needT_s3 | sink_resp_s3_a_promoteT ? 2'h2 : io_metaOnHit_s3_state)
+                : metaW_s3_b_state)
+           : metaW_valid_s3_c
+               ? (_io_nestedwb_c_set_tip_T_4 | ~(|task_s3_bits_param)
+                  | _metaW_s3_c_x20_T_3
+                    ? 2'h3
+                    : io_metaOnHit_s3_state)
+               : metaW_valid_s3_mshr
+                   ? (task_s3_bits_mergeA
+                        ? task_s3_bits_aMergeTask_meta_state
+                        : task_s3_bits_meta_state)
+                   : 2'h0)
+      : 2'h0;
+  assign io_metaWReq_bits_wmeta_clients =
+    resetFinish
+    & (_io_metaWReq_bits_wmeta_T
+         ? (metaW_valid_s3_a ? ~io_dirResp_s3_error : metaW_s3_b_clients)
+         : metaW_valid_s3_c
+             ? ~(_io_nestedwb_c_set_tip_T_4 | task_s3_bits_param == 3'h2
+                 | task_s3_bits_param == 3'h5)
+             : metaW_valid_s3_mshr
+               & (task_s3_bits_mergeA
+                    ? task_s3_bits_aMergeTask_meta_clients
+                    : task_s3_bits_meta_clients));
+  assign io_metaWReq_bits_wmeta_alias =
+    resetFinish
+    & (_io_metaWReq_bits_wmeta_T
+         ? (metaW_valid_s3_a
+              ? (req_get_s3 | req_prefetch_s3
+                   ? io_metaOnHit_s3_alias
+                   : task_s3_bits_alias)
+              : metaW_s3_b_alias)
+         : metaW_valid_s3_c
+             ? io_metaOnHit_s3_alias
+             : metaW_valid_s3_mshr
+               & (task_s3_bits_mergeA
+                    ? task_s3_bits_aMergeTask_meta_alias
+                    : task_s3_bits_meta_alias));
+  assign io_metaWReq_bits_wmeta_prefetch =
+    resetFinish & ~_GEN_6 & metaW_valid_s3_mshr
+    & (task_s3_bits_mergeA
+         ? task_s3_bits_aMergeTask_meta_prefetch
+         : task_s3_bits_meta_prefetch);
+  assign io_metaWReq_bits_wmeta_prefetchSrc =
+    ~resetFinish | _GEN_6 | ~metaW_valid_s3_mshr
+      ? 4'h0
+      : task_s3_bits_mergeA
+          ? task_s3_bits_aMergeTask_meta_prefetchSrc
+          : task_s3_bits_meta_prefetchSrc;
+  assign io_metaWReq_bits_wmeta_accessed =
+    resetFinish
+    & (_io_metaWReq_bits_wmeta_T
+         ? metaW_valid_s3_a | metaW_s3_b_accessed
+         : metaW_valid_s3_c
+             ? io_metaOnHit_s3_accessed
+             : metaW_valid_s3_mshr
+               & (task_s3_bits_mergeA
+                    ? task_s3_bits_aMergeTask_meta_accessed
+                    : task_s3_bits_meta_accessed));
+  assign io_metaWReq_bits_wmeta_tagErr =
+    resetFinish
+    & (_io_metaWReq_bits_wmeta_T
+         ? _GEN_5 & io_metaOnHit_s3_tagErr
+         : metaW_valid_s3_c
+             ? (wen_c ? task_s3_bits_denied : io_metaOnHit_s3_tagErr)
+             : metaW_valid_s3_mshr & task_s3_bits_denied);
+  assign io_metaWReq_bits_wmeta_dataErr =
+    resetFinish
+    & (_io_metaWReq_bits_wmeta_T
+         ? _GEN_5 & io_metaOnHit_s3_dataErr
+         : metaW_valid_s3_c
+             ? (wen_c ? task_s3_bits_corrupt : io_metaOnHit_s3_dataErr)
+             : metaW_valid_s3_mshr & task_s3_bits_corrupt);
+  assign io_tagWReq_valid = task_s3_valid & task_s3_bits_tagWen & mshr_refill_s3 & ~retry;
+  assign io_tagWReq_bits_set = task_s3_bits_set;
+  assign io_tagWReq_bits_wayOH =
+    _io_tagWReq_bits_wayOH_T ? io_dirReplWayOH_s3 : reqWayOH_s3;
+  assign io_tagWReq_bits_wtag = task_s3_bits_tag;
+  assign io_releaseBufWrite_valid = task_s5_valid & need_write_releaseBuf_s5;
+  assign io_releaseBufWrite_bits_id = task_s5_bits_mshrId;
+  assign io_releaseBufWrite_bits_data_data = io_toDS_rdata_s5_data;
+  assign io_nestedwb_set = task_s3_bits_set;
+  assign io_nestedwb_tag = task_s3_bits_tag;
+  assign io_nestedwb_c_set_dirty =
+    task_s3_valid & task_s3_bits_channel[2] & _perfEvents_T_7
+    & _io_nestedwb_c_set_tip_T_4;
+  assign io_nestedwb_c_set_tip =
+    task_s3_valid & task_s3_bits_channel[2] & _io_nestedwb_c_set_tip_T_2
+    & _io_nestedwb_c_set_tip_T_4;
+  assign io_nestedwb_b_inv_dirty =
+    task_s3_valid & task_s3_bits_channel[1] & task_s3_bits_snpHitReleaseToInval
+    & ~(_io_nestedwb_b_inv_dirty_T_3 | _io_nestedwb_b_inv_dirty_T_4
+        | _io_nestedwb_b_inv_dirty_T_6);
+  assign io_nestedwb_b_toB =
+    task_s3_valid & task_s3_bits_channel[1] & source_req_s3_metaWen
+    & source_req_s3_meta_state == 2'h1;
+  assign io_nestedwb_b_toN =
+    task_s3_valid & task_s3_bits_channel[1] & source_req_s3_metaWen
+    & source_req_s3_meta_state == 2'h0;
+  assign io_nestedwb_b_toClean =
+    task_s3_valid & task_s3_bits_channel[1] & source_req_s3_metaWen
+    & ~source_req_s3_meta_dirty;
+  assign io_nestedwbData_data = c_releaseData_s3;
+  assign io_prefetchTrain_valid =
+    task_s3_valid
+    & ((req_acquire_s3 | req_get_s3) & task_s3_bits_needHint
+       & (~io_dirResp_s3_hit | io_metaOnHit_s3_prefetch) | task_s3_bits_mergeA);
+  assign io_prefetchTrain_bits_tag = task_s3_bits_tag;
+  assign io_prefetchTrain_bits_set = task_s3_bits_set;
+  assign io_prefetchTrain_bits_needT =
+    task_s3_bits_mergeA
+      ? ~(task_s3_bits_aMergeTask_opcode[2]) | task_s3_bits_aMergeTask_opcode == 3'h5
+        & task_s3_bits_aMergeTask_param == 3'h1
+        | (task_s3_bits_aMergeTask_opcode == 3'h6 | (&task_s3_bits_aMergeTask_opcode))
+        & (|task_s3_bits_aMergeTask_param)
+      : req_needT_s3;
+  assign io_prefetchTrain_bits_source =
+    task_s3_bits_mergeA ? task_s3_bits_aMergeTask_sourceId : task_s3_bits_sourceId;
+  assign io_prefetchTrain_bits_vaddr =
+    task_s3_bits_mergeA ? task_s3_bits_aMergeTask_vaddr : task_s3_bits_vaddr;
+  assign io_prefetchTrain_bits_hit = task_s3_bits_mergeA | io_dirResp_s3_hit;
+  assign io_prefetchTrain_bits_prefetched =
+    task_s3_bits_mergeA | io_metaOnHit_s3_prefetch;
+  assign io_prefetchTrain_bits_pfsource =
+    task_s3_bits_mergeA ? task_s3_bits_meta_prefetchSrc : io_metaOnHit_s3_prefetchSrc;
+  assign io_prefetchTrain_bits_reqsource = task_s3_bits_reqSource;
+  assign io_error_valid = task_s5_valid;
+  assign io_error_bits_valid = l2TagError_s5 | io_toDS_error_s5;
+  assign io_error_bits_address = {task_s5_bits_tag, task_s5_bits_set, task_s5_bits_off};
+  assign io_perf_0_value = {5'h0, io_perf_0_value_REG_1};
+  assign io_perf_1_value = {5'h0, io_perf_1_value_REG_1};
+  assign io_perf_2_value = {5'h0, io_perf_2_value_REG_1};
+  assign io_perf_3_value = {5'h0, io_perf_3_value_REG_1};
+  assign io_perf_4_value = {5'h0, io_perf_4_value_REG_1};
+  assign io_perf_5_value = {5'h0, io_perf_5_value_REG_1};
+  assign io_perf_6_value = {5'h0, io_perf_6_value_REG_1};
+  assign io_perf_7_value = {5'h0, io_perf_7_value_REG_1};
+  assign io_perf_8_value = {5'h0, io_perf_8_value_REG_1};
+  assign io_perf_9_value = {5'h0, io_perf_9_value_REG_1};
+  assign io_perf_10_value = {5'h0, io_perf_10_value_REG_1};
+  assign io_perf_11_value = {5'h0, io_perf_11_value_REG_1};
+  assign io_perf_12_value = {5'h0, io_perf_12_value_REG_1};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MbistClockGateCell_186.sv b/flow/designs/src/xiangshan_coupledl2/deps/MbistClockGateCell_186.sv
new file mode 100644
index 0000000000..03fc8e2225
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MbistClockGateCell_186.sv
@@ -0,0 +1,28 @@
+// Generated by CIRCT firtool-1.135.0
+module MbistClockGateCell_186(
+  input  clock,
+  input  mbist_writeen,
+  input  mbist_readen,
+  input  mbist_req,
+  input  E,
+  input  dft_ram_mcp_hold,
+  input  dft_ram_aux_clk,
+  input  dft_ram_aux_ckbp,
+  input  dft_cgen,
+  output out_clock
+);
+
+  wire _CG_Q;
+  ClockGate CG (
+    .TE (dft_cgen),
+    .E  ((mbist_req ? mbist_readen | mbist_writeen : E) & ~dft_ram_mcp_hold),
+    .CK (clock),
+    .Q  (_CG_Q)
+  );
+  ClockMux clockMux (
+    .clk0   (_CG_Q),
+    .clk1   (dft_ram_aux_clk),
+    .sel    (dft_ram_aux_ckbp),
+    .clkout (out_clock)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MbistIntfL2.sv b/flow/designs/src/xiangshan_coupledl2/deps/MbistIntfL2.sv
new file mode 100644
index 0000000000..c5fae1145c
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MbistIntfL2.sv
@@ -0,0 +1,38 @@
+// Generated by CIRCT firtool-1.135.0
+module MbistIntfL2(
+  output [3:0]   toPipeline_0_array,
+  output         toPipeline_0_all,
+  output         toPipeline_0_req,
+  input          toPipeline_0_ack,
+  output         toPipeline_0_writeen,
+  output [7:0]   toPipeline_0_be,
+  output [11:0]  toPipeline_0_addr,
+  output [163:0] toPipeline_0_indata,
+  output         toPipeline_0_readen,
+  output [11:0]  toPipeline_0_addr_rd,
+  input  [163:0] toPipeline_0_outdata,
+  input  [3:0]   mbist_array,
+  input          mbist_all,
+  input          mbist_req,
+  output         mbist_ack,
+  input          mbist_writeen,
+  input  [7:0]   mbist_be,
+  input  [11:0]  mbist_addr,
+  input  [163:0] mbist_indata,
+  input          mbist_readen,
+  input  [11:0]  mbist_addr_rd,
+  output [163:0] mbist_outdata
+);
+
+  assign toPipeline_0_array = mbist_array;
+  assign toPipeline_0_all = mbist_all;
+  assign toPipeline_0_req = mbist_req;
+  assign toPipeline_0_writeen = mbist_writeen;
+  assign toPipeline_0_be = mbist_be;
+  assign toPipeline_0_addr = mbist_addr;
+  assign toPipeline_0_indata = mbist_indata;
+  assign toPipeline_0_readen = mbist_readen;
+  assign toPipeline_0_addr_rd = mbist_addr_rd;
+  assign mbist_ack = toPipeline_0_ack;
+  assign mbist_outdata = toPipeline_0_outdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/MbistPipeL2Prefetcher.sv b/flow/designs/src/xiangshan_coupledl2/deps/MbistPipeL2Prefetcher.sv
new file mode 100644
index 0000000000..0a00f06361
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/MbistPipeL2Prefetcher.sv
@@ -0,0 +1,185 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module MbistPipeL2Prefetcher(
+  input         clock,
+  input         reset,
+  input         mbist_array,
+  input         mbist_all,
+  input         mbist_req,
+  output        mbist_ack,
+  input         mbist_writeen,
+  input         mbist_be,
+  input  [8:0]  mbist_addr,
+  input  [12:0] mbist_indata,
+  input         mbist_readen,
+  input  [8:0]  mbist_addr_rd,
+  output [12:0] mbist_outdata,
+  output [8:0]  toSRAM_0_addr,
+  output [8:0]  toSRAM_0_addr_rd,
+  output [12:0] toSRAM_0_wdata,
+  output        toSRAM_0_wmask,
+  output        toSRAM_0_re,
+  output        toSRAM_0_we,
+  input  [12:0] toSRAM_0_rdata,
+  output        toSRAM_0_ack,
+  output        toSRAM_0_selectedOH,
+  output        toSRAM_0_array,
+  output [8:0]  toSRAM_1_addr,
+  output [8:0]  toSRAM_1_addr_rd,
+  output [12:0] toSRAM_1_wdata,
+  output        toSRAM_1_wmask,
+  output        toSRAM_1_re,
+  output        toSRAM_1_we,
+  input  [12:0] toSRAM_1_rdata,
+  output        toSRAM_1_ack,
+  output        toSRAM_1_selectedOH,
+  output        toSRAM_1_array
+);
+
+  wire [12:0] sramDataOut_1;
+  wire [12:0] sramDataOut_0;
+  reg         arrayReg;
+  reg         reqReg;
+  reg         allReg;
+  reg         wenReg;
+  reg         beReg;
+  reg  [8:0]  addrReg;
+  reg  [12:0] dataInReg;
+  reg         renReg;
+  reg  [8:0]  addrRdReg;
+  wire        doSpread = ~arrayReg | allReg;
+  assign sramDataOut_0 = arrayReg ? 13'h0 : toSRAM_0_rdata;
+  wire        doSpread_1 = arrayReg | allReg;
+  assign sramDataOut_1 = arrayReg ? toSRAM_1_rdata : 13'h0;
+  wire        activated = mbist_all | mbist_req;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      arrayReg <= 1'h0;
+      reqReg <= 1'h0;
+      allReg <= 1'h0;
+      wenReg <= 1'h0;
+      beReg <= 1'h0;
+      addrReg <= 9'h0;
+      dataInReg <= 13'h0;
+      renReg <= 1'h0;
+      addrRdReg <= 9'h0;
+    end
+    else begin
+      if (activated) begin
+        arrayReg <= mbist_array;
+        allReg <= mbist_all;
+        wenReg <= mbist_writeen;
+        renReg <= mbist_readen;
+      end
+      reqReg <= mbist_req;
+      if (activated & (mbist_readen | mbist_writeen)) begin
+        beReg <= mbist_be;
+        addrReg <= mbist_addr;
+        dataInReg <= mbist_indata;
+        addrRdReg <= mbist_addr_rd;
+      end
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:1];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
+          _RANDOM[i[0]] = `RANDOM;
+        end
+        arrayReg = _RANDOM[1'h0][0];
+        reqReg = _RANDOM[1'h0][1];
+        allReg = _RANDOM[1'h0][2];
+        wenReg = _RANDOM[1'h0][3];
+        beReg = _RANDOM[1'h0][4];
+        addrReg = _RANDOM[1'h0][13:5];
+        dataInReg = _RANDOM[1'h0][26:14];
+        renReg = _RANDOM[1'h0][27];
+        addrRdReg = {_RANDOM[1'h0][31:28], _RANDOM[1'h1][4:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        arrayReg = 1'h0;
+        reqReg = 1'h0;
+        allReg = 1'h0;
+        wenReg = 1'h0;
+        beReg = 1'h0;
+        addrReg = 9'h0;
+        dataInReg = 13'h0;
+        renReg = 1'h0;
+        addrRdReg = 9'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign mbist_ack = reqReg;
+  assign mbist_outdata = sramDataOut_0 | sramDataOut_1;
+  assign toSRAM_0_addr = doSpread ? addrReg : 9'h0;
+  assign toSRAM_0_addr_rd = doSpread ? addrRdReg : 9'h0;
+  assign toSRAM_0_wdata = dataInReg;
+  assign toSRAM_0_wmask = beReg;
+  assign toSRAM_0_re = doSpread & renReg;
+  assign toSRAM_0_we = doSpread & wenReg;
+  assign toSRAM_0_ack = reqReg;
+  assign toSRAM_0_selectedOH = allReg | ~reqReg | ~arrayReg;
+  assign toSRAM_0_array = arrayReg;
+  assign toSRAM_1_addr = doSpread_1 ? addrReg : 9'h0;
+  assign toSRAM_1_addr_rd = doSpread_1 ? addrRdReg : 9'h0;
+  assign toSRAM_1_wdata = dataInReg;
+  assign toSRAM_1_wmask = beReg;
+  assign toSRAM_1_re = doSpread_1 & renReg;
+  assign toSRAM_1_we = doSpread_1 & wenReg;
+  assign toSRAM_1_ack = reqReg;
+  assign toSRAM_1_selectedOH = allReg | ~reqReg | arrayReg;
+  assign toSRAM_1_array = arrayReg;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/OffsetScoreTable.sv b/flow/designs/src/xiangshan_coupledl2/deps/OffsetScoreTable.sv
new file mode 100644
index 0000000000..8742e502d5
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/OffsetScoreTable.sv
@@ -0,0 +1,724 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module OffsetScoreTable(
+  input         clock,
+  input         reset,
+  output        io_req_ready,
+  input         io_req_valid,
+  input  [47:0] io_req_bits,
+  output [6:0]  io_prefetchOffset,
+  output        io_prefetchDisable,
+  output        io_test_req_valid,
+  output [47:0] io_test_req_bits_addr,
+  output [6:0]  io_test_req_bits_testOffset,
+  output [5:0]  io_test_req_bits_ptr,
+  input         io_test_resp_valid,
+  input  [5:0]  io_test_resp_bits_ptr,
+  input         io_test_resp_bits_hit
+);
+
+  wire [63:0][6:0] _GEN =
+    '{7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h1E,
+      7'h1B,
+      7'h19,
+      7'h18,
+      7'h14,
+      7'h12,
+      7'h10,
+      7'hF,
+      7'hC,
+      7'hA,
+      7'h9,
+      7'h8,
+      7'h6,
+      7'h5,
+      7'h4,
+      7'h3,
+      7'h2,
+      7'h1,
+      7'h7F,
+      7'h7E,
+      7'h7D,
+      7'h7C,
+      7'h7B,
+      7'h7A,
+      7'h78,
+      7'h77,
+      7'h76,
+      7'h74,
+      7'h71,
+      7'h70,
+      7'h6E,
+      7'h6C,
+      7'h68,
+      7'h67,
+      7'h65,
+      7'h62,
+      7'h60};
+  reg  [6:0]       prefetchOffset;
+  reg              prefetchDisable;
+  reg  [4:0]       st_0_score;
+  reg  [4:0]       st_1_score;
+  reg  [4:0]       st_2_score;
+  reg  [4:0]       st_3_score;
+  reg  [4:0]       st_4_score;
+  reg  [4:0]       st_5_score;
+  reg  [4:0]       st_6_score;
+  reg  [4:0]       st_7_score;
+  reg  [4:0]       st_8_score;
+  reg  [4:0]       st_9_score;
+  reg  [4:0]       st_10_score;
+  reg  [4:0]       st_11_score;
+  reg  [4:0]       st_12_score;
+  reg  [4:0]       st_13_score;
+  reg  [4:0]       st_14_score;
+  reg  [4:0]       st_15_score;
+  reg  [4:0]       st_16_score;
+  reg  [4:0]       st_17_score;
+  reg  [4:0]       st_18_score;
+  reg  [4:0]       st_19_score;
+  reg  [4:0]       st_20_score;
+  reg  [4:0]       st_21_score;
+  reg  [4:0]       st_22_score;
+  reg  [4:0]       st_23_score;
+  reg  [4:0]       st_24_score;
+  reg  [4:0]       st_25_score;
+  reg  [4:0]       st_26_score;
+  reg  [4:0]       st_27_score;
+  reg  [4:0]       st_28_score;
+  reg  [4:0]       st_29_score;
+  reg  [4:0]       st_30_score;
+  reg  [4:0]       st_31_score;
+  reg  [4:0]       st_32_score;
+  reg  [4:0]       st_33_score;
+  reg  [4:0]       st_34_score;
+  reg  [4:0]       st_35_score;
+  reg  [4:0]       st_36_score;
+  reg  [5:0]       ptr;
+  reg  [5:0]       round;
+  reg  [6:0]       bestOffset;
+  reg  [4:0]       bestScore;
+  reg              state;
+  wire             io_test_req_valid_0 = state & io_req_valid;
+  wire             roundFinish = ptr == 6'h24;
+  wire [63:0][6:0] _GEN_0 =
+    '{7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h60,
+      7'h1E,
+      7'h1B,
+      7'h19,
+      7'h18,
+      7'h14,
+      7'h12,
+      7'h10,
+      7'hF,
+      7'hC,
+      7'hA,
+      7'h9,
+      7'h8,
+      7'h6,
+      7'h5,
+      7'h4,
+      7'h3,
+      7'h2,
+      7'h1,
+      7'h7F,
+      7'h7E,
+      7'h7D,
+      7'h7C,
+      7'h7B,
+      7'h7A,
+      7'h78,
+      7'h77,
+      7'h76,
+      7'h74,
+      7'h71,
+      7'h70,
+      7'h6E,
+      7'h6C,
+      7'h68,
+      7'h67,
+      7'h65,
+      7'h62,
+      7'h60};
+  wire             _GEN_1 = {58'h0, round} > 64'h31;
+  wire             _GEN_2 = io_test_resp_valid & io_test_resp_bits_hit;
+  wire [63:0][4:0] _GEN_3 =
+    {{st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_36_score},
+     {st_35_score},
+     {st_34_score},
+     {st_33_score},
+     {st_32_score},
+     {st_31_score},
+     {st_30_score},
+     {st_29_score},
+     {st_28_score},
+     {st_27_score},
+     {st_26_score},
+     {st_25_score},
+     {st_24_score},
+     {st_23_score},
+     {st_22_score},
+     {st_21_score},
+     {st_20_score},
+     {st_19_score},
+     {st_18_score},
+     {st_17_score},
+     {st_16_score},
+     {st_15_score},
+     {st_14_score},
+     {st_13_score},
+     {st_12_score},
+     {st_11_score},
+     {st_10_score},
+     {st_9_score},
+     {st_8_score},
+     {st_7_score},
+     {st_6_score},
+     {st_5_score},
+     {st_4_score},
+     {st_3_score},
+     {st_2_score},
+     {st_1_score},
+     {st_0_score}};
+  wire [4:0]       _newScore_T = 5'(_GEN_3[io_test_resp_bits_ptr] + 5'h1);
+  wire             renewOffset = _newScore_T > bestScore;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      prefetchOffset <= 7'h2;
+      prefetchDisable <= 1'h0;
+      st_0_score <= 5'h0;
+      st_1_score <= 5'h0;
+      st_2_score <= 5'h0;
+      st_3_score <= 5'h0;
+      st_4_score <= 5'h0;
+      st_5_score <= 5'h0;
+      st_6_score <= 5'h0;
+      st_7_score <= 5'h0;
+      st_8_score <= 5'h0;
+      st_9_score <= 5'h0;
+      st_10_score <= 5'h0;
+      st_11_score <= 5'h0;
+      st_12_score <= 5'h0;
+      st_13_score <= 5'h0;
+      st_14_score <= 5'h0;
+      st_15_score <= 5'h0;
+      st_16_score <= 5'h0;
+      st_17_score <= 5'h0;
+      st_18_score <= 5'h0;
+      st_19_score <= 5'h0;
+      st_20_score <= 5'h0;
+      st_21_score <= 5'h0;
+      st_22_score <= 5'h0;
+      st_23_score <= 5'h0;
+      st_24_score <= 5'h0;
+      st_25_score <= 5'h0;
+      st_26_score <= 5'h0;
+      st_27_score <= 5'h0;
+      st_28_score <= 5'h0;
+      st_29_score <= 5'h0;
+      st_30_score <= 5'h0;
+      st_31_score <= 5'h0;
+      st_32_score <= 5'h0;
+      st_33_score <= 5'h0;
+      st_34_score <= 5'h0;
+      st_35_score <= 5'h0;
+      st_36_score <= 5'h0;
+      ptr <= 6'h0;
+      round <= 6'h0;
+      bestOffset <= 7'h2;
+      bestScore <= 5'h0;
+      state <= 1'h0;
+    end
+    else begin
+      if (state) begin
+      end
+      else begin
+        prefetchOffset <= bestOffset;
+        prefetchDisable <= bestScore == 5'h0;
+      end
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h0)
+        st_0_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_0_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h1)
+        st_1_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_1_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h2)
+        st_2_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_2_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h3)
+        st_3_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_3_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h4)
+        st_4_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_4_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h5)
+        st_5_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_5_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h6)
+        st_6_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_6_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h7)
+        st_7_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_7_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h8)
+        st_8_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_8_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h9)
+        st_9_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_9_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'hA)
+        st_10_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_10_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'hB)
+        st_11_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_11_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'hC)
+        st_12_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_12_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'hD)
+        st_13_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_13_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'hE)
+        st_14_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_14_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'hF)
+        st_15_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_15_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h10)
+        st_16_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_16_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h11)
+        st_17_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_17_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h12)
+        st_18_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_18_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h13)
+        st_19_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_19_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h14)
+        st_20_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_20_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h15)
+        st_21_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_21_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h16)
+        st_22_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_22_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h17)
+        st_23_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_23_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h18)
+        st_24_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_24_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h19)
+        st_25_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_25_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h1A)
+        st_26_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_26_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h1B)
+        st_27_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_27_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h1C)
+        st_28_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_28_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h1D)
+        st_29_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_29_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h1E)
+        st_30_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_30_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h1F)
+        st_31_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_31_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h20)
+        st_32_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_32_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h21)
+        st_33_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_33_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h22)
+        st_34_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_34_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h23)
+        st_35_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_35_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 6'h24)
+        st_36_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_36_score <= 5'h0;
+      if (io_test_req_valid_0) begin
+        ptr <= roundFinish ? 6'h0 : 6'(ptr + 6'h1);
+        if (roundFinish)
+          round <= 6'(round + 6'h1);
+      end
+      else if (state) begin
+      end
+      else begin
+        ptr <= 6'h0;
+        round <= 6'h0;
+      end
+      if (state & _GEN_2 & renewOffset)
+        bestOffset <= _GEN_0[io_test_resp_bits_ptr];
+      if (state & _GEN_2) begin
+        if (renewOffset)
+          bestScore <= _newScore_T;
+      end
+      else if (state) begin
+      end
+      else
+        bestScore <= 5'h0;
+      state <= ~state | (_GEN_2 ? ~((&_newScore_T) | _GEN_1) : ~_GEN_1);
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:6];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h7; i += 3'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        prefetchOffset = _RANDOM[3'h0][6:0];
+        prefetchDisable = _RANDOM[3'h0][7];
+        st_0_score = _RANDOM[3'h0][12:8];
+        st_1_score = _RANDOM[3'h0][17:13];
+        st_2_score = _RANDOM[3'h0][22:18];
+        st_3_score = _RANDOM[3'h0][27:23];
+        st_4_score = {_RANDOM[3'h0][31:28], _RANDOM[3'h1][0]};
+        st_5_score = _RANDOM[3'h1][5:1];
+        st_6_score = _RANDOM[3'h1][10:6];
+        st_7_score = _RANDOM[3'h1][15:11];
+        st_8_score = _RANDOM[3'h1][20:16];
+        st_9_score = _RANDOM[3'h1][25:21];
+        st_10_score = _RANDOM[3'h1][30:26];
+        st_11_score = {_RANDOM[3'h1][31], _RANDOM[3'h2][3:0]};
+        st_12_score = _RANDOM[3'h2][8:4];
+        st_13_score = _RANDOM[3'h2][13:9];
+        st_14_score = _RANDOM[3'h2][18:14];
+        st_15_score = _RANDOM[3'h2][23:19];
+        st_16_score = _RANDOM[3'h2][28:24];
+        st_17_score = {_RANDOM[3'h2][31:29], _RANDOM[3'h3][1:0]};
+        st_18_score = _RANDOM[3'h3][6:2];
+        st_19_score = _RANDOM[3'h3][11:7];
+        st_20_score = _RANDOM[3'h3][16:12];
+        st_21_score = _RANDOM[3'h3][21:17];
+        st_22_score = _RANDOM[3'h3][26:22];
+        st_23_score = _RANDOM[3'h3][31:27];
+        st_24_score = _RANDOM[3'h4][4:0];
+        st_25_score = _RANDOM[3'h4][9:5];
+        st_26_score = _RANDOM[3'h4][14:10];
+        st_27_score = _RANDOM[3'h4][19:15];
+        st_28_score = _RANDOM[3'h4][24:20];
+        st_29_score = _RANDOM[3'h4][29:25];
+        st_30_score = {_RANDOM[3'h4][31:30], _RANDOM[3'h5][2:0]};
+        st_31_score = _RANDOM[3'h5][7:3];
+        st_32_score = _RANDOM[3'h5][12:8];
+        st_33_score = _RANDOM[3'h5][17:13];
+        st_34_score = _RANDOM[3'h5][22:18];
+        st_35_score = _RANDOM[3'h5][27:23];
+        st_36_score = {_RANDOM[3'h5][31:28], _RANDOM[3'h6][0]};
+        ptr = _RANDOM[3'h6][6:1];
+        round = _RANDOM[3'h6][12:7];
+        bestOffset = _RANDOM[3'h6][19:13];
+        bestScore = _RANDOM[3'h6][24:20];
+        state = _RANDOM[3'h6][25];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        prefetchOffset = 7'h2;
+        prefetchDisable = 1'h0;
+        st_0_score = 5'h0;
+        st_1_score = 5'h0;
+        st_2_score = 5'h0;
+        st_3_score = 5'h0;
+        st_4_score = 5'h0;
+        st_5_score = 5'h0;
+        st_6_score = 5'h0;
+        st_7_score = 5'h0;
+        st_8_score = 5'h0;
+        st_9_score = 5'h0;
+        st_10_score = 5'h0;
+        st_11_score = 5'h0;
+        st_12_score = 5'h0;
+        st_13_score = 5'h0;
+        st_14_score = 5'h0;
+        st_15_score = 5'h0;
+        st_16_score = 5'h0;
+        st_17_score = 5'h0;
+        st_18_score = 5'h0;
+        st_19_score = 5'h0;
+        st_20_score = 5'h0;
+        st_21_score = 5'h0;
+        st_22_score = 5'h0;
+        st_23_score = 5'h0;
+        st_24_score = 5'h0;
+        st_25_score = 5'h0;
+        st_26_score = 5'h0;
+        st_27_score = 5'h0;
+        st_28_score = 5'h0;
+        st_29_score = 5'h0;
+        st_30_score = 5'h0;
+        st_31_score = 5'h0;
+        st_32_score = 5'h0;
+        st_33_score = 5'h0;
+        st_34_score = 5'h0;
+        st_35_score = 5'h0;
+        st_36_score = 5'h0;
+        ptr = 6'h0;
+        round = 6'h0;
+        bestOffset = 7'h2;
+        bestScore = 5'h0;
+        state = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_req_ready = state;
+  assign io_prefetchOffset = prefetchOffset;
+  assign io_prefetchDisable = prefetchDisable;
+  assign io_test_req_valid = io_test_req_valid_0;
+  assign io_test_req_bits_addr = io_req_bits;
+  assign io_test_req_bits_testOffset = _GEN[ptr];
+  assign io_test_req_bits_ptr = ptr;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/OffsetScoreTable_1.sv b/flow/designs/src/xiangshan_coupledl2/deps/OffsetScoreTable_1.sv
new file mode 100644
index 0000000000..aeef598286
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/OffsetScoreTable_1.sv
@@ -0,0 +1,1636 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module OffsetScoreTable_1(
+  input         clock,
+  input         reset,
+  output        io_req_ready,
+  input         io_req_valid,
+  input  [49:0] io_req_bits,
+  output [9:0]  io_prefetchOffset,
+  output        io_prefetchDisable,
+  output        io_test_req_valid,
+  output [49:0] io_test_req_bits_addr,
+  output [9:0]  io_test_req_bits_testOffset,
+  output [6:0]  io_test_req_bits_ptr,
+  input         io_test_resp_valid,
+  input  [6:0]  io_test_resp_bits_ptr,
+  input         io_test_resp_bits_hit
+);
+
+  wire [127:0][9:0] _GEN =
+    '{10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'hFA,
+      10'hF3,
+      10'hF0,
+      10'hE1,
+      10'hD8,
+      10'hC8,
+      10'hC0,
+      10'hB4,
+      10'hA2,
+      10'hA0,
+      10'h96,
+      10'h90,
+      10'h87,
+      10'h80,
+      10'h7D,
+      10'h78,
+      10'h6C,
+      10'h64,
+      10'h60,
+      10'h5A,
+      10'h51,
+      10'h50,
+      10'h4B,
+      10'h48,
+      10'h40,
+      10'h3C,
+      10'h36,
+      10'h32,
+      10'h30,
+      10'h2D,
+      10'h28,
+      10'h24,
+      10'h20,
+      10'h1E,
+      10'h1B,
+      10'h19,
+      10'h18,
+      10'h14,
+      10'h12,
+      10'h10,
+      10'hF,
+      10'hC,
+      10'hA,
+      10'h9,
+      10'h8,
+      10'h6,
+      10'h5,
+      10'h4,
+      10'h3,
+      10'h2,
+      10'h1,
+      10'h3FF,
+      10'h3FE,
+      10'h3FD,
+      10'h3FC,
+      10'h3FB,
+      10'h3FA,
+      10'h3F8,
+      10'h3F7,
+      10'h3F6,
+      10'h3F4,
+      10'h3F1,
+      10'h3F0,
+      10'h3EE,
+      10'h3EC,
+      10'h3E8,
+      10'h3E7,
+      10'h3E5,
+      10'h3E2,
+      10'h3E0,
+      10'h3DC,
+      10'h3D8,
+      10'h3D3,
+      10'h3D0,
+      10'h3CE,
+      10'h3CA,
+      10'h3C4,
+      10'h3C0,
+      10'h3B8,
+      10'h3B5,
+      10'h3B0,
+      10'h3AF,
+      10'h3A6,
+      10'h3A0,
+      10'h39C,
+      10'h394,
+      10'h388,
+      10'h383,
+      10'h380,
+      10'h379,
+      10'h370,
+      10'h36A,
+      10'h360,
+      10'h35E,
+      10'h34C,
+      10'h340,
+      10'h338,
+      10'h328,
+      10'h31F,
+      10'h310,
+      10'h30D,
+      10'h306,
+      10'h300,
+      10'h5B,
+      10'h93,
+      10'h75,
+      10'h3A5,
+      10'h36D,
+      10'h38B};
+  reg  [9:0]        prefetchOffset;
+  reg               prefetchDisable;
+  reg  [4:0]        st_0_score;
+  reg  [4:0]        st_1_score;
+  reg  [4:0]        st_2_score;
+  reg  [4:0]        st_3_score;
+  reg  [4:0]        st_4_score;
+  reg  [4:0]        st_5_score;
+  reg  [4:0]        st_6_score;
+  reg  [4:0]        st_7_score;
+  reg  [4:0]        st_8_score;
+  reg  [4:0]        st_9_score;
+  reg  [4:0]        st_10_score;
+  reg  [4:0]        st_11_score;
+  reg  [4:0]        st_12_score;
+  reg  [4:0]        st_13_score;
+  reg  [4:0]        st_14_score;
+  reg  [4:0]        st_15_score;
+  reg  [4:0]        st_16_score;
+  reg  [4:0]        st_17_score;
+  reg  [4:0]        st_18_score;
+  reg  [4:0]        st_19_score;
+  reg  [4:0]        st_20_score;
+  reg  [4:0]        st_21_score;
+  reg  [4:0]        st_22_score;
+  reg  [4:0]        st_23_score;
+  reg  [4:0]        st_24_score;
+  reg  [4:0]        st_25_score;
+  reg  [4:0]        st_26_score;
+  reg  [4:0]        st_27_score;
+  reg  [4:0]        st_28_score;
+  reg  [4:0]        st_29_score;
+  reg  [4:0]        st_30_score;
+  reg  [4:0]        st_31_score;
+  reg  [4:0]        st_32_score;
+  reg  [4:0]        st_33_score;
+  reg  [4:0]        st_34_score;
+  reg  [4:0]        st_35_score;
+  reg  [4:0]        st_36_score;
+  reg  [4:0]        st_37_score;
+  reg  [4:0]        st_38_score;
+  reg  [4:0]        st_39_score;
+  reg  [4:0]        st_40_score;
+  reg  [4:0]        st_41_score;
+  reg  [4:0]        st_42_score;
+  reg  [4:0]        st_43_score;
+  reg  [4:0]        st_44_score;
+  reg  [4:0]        st_45_score;
+  reg  [4:0]        st_46_score;
+  reg  [4:0]        st_47_score;
+  reg  [4:0]        st_48_score;
+  reg  [4:0]        st_49_score;
+  reg  [4:0]        st_50_score;
+  reg  [4:0]        st_51_score;
+  reg  [4:0]        st_52_score;
+  reg  [4:0]        st_53_score;
+  reg  [4:0]        st_54_score;
+  reg  [4:0]        st_55_score;
+  reg  [4:0]        st_56_score;
+  reg  [4:0]        st_57_score;
+  reg  [4:0]        st_58_score;
+  reg  [4:0]        st_59_score;
+  reg  [4:0]        st_60_score;
+  reg  [4:0]        st_61_score;
+  reg  [4:0]        st_62_score;
+  reg  [4:0]        st_63_score;
+  reg  [4:0]        st_64_score;
+  reg  [4:0]        st_65_score;
+  reg  [4:0]        st_66_score;
+  reg  [4:0]        st_67_score;
+  reg  [4:0]        st_68_score;
+  reg  [4:0]        st_69_score;
+  reg  [4:0]        st_70_score;
+  reg  [4:0]        st_71_score;
+  reg  [4:0]        st_72_score;
+  reg  [4:0]        st_73_score;
+  reg  [4:0]        st_74_score;
+  reg  [4:0]        st_75_score;
+  reg  [4:0]        st_76_score;
+  reg  [4:0]        st_77_score;
+  reg  [4:0]        st_78_score;
+  reg  [4:0]        st_79_score;
+  reg  [4:0]        st_80_score;
+  reg  [4:0]        st_81_score;
+  reg  [4:0]        st_82_score;
+  reg  [4:0]        st_83_score;
+  reg  [4:0]        st_84_score;
+  reg  [4:0]        st_85_score;
+  reg  [4:0]        st_86_score;
+  reg  [4:0]        st_87_score;
+  reg  [4:0]        st_88_score;
+  reg  [4:0]        st_89_score;
+  reg  [4:0]        st_90_score;
+  reg  [4:0]        st_91_score;
+  reg  [4:0]        st_92_score;
+  reg  [4:0]        st_93_score;
+  reg  [4:0]        st_94_score;
+  reg  [4:0]        st_95_score;
+  reg  [4:0]        st_96_score;
+  reg  [4:0]        st_97_score;
+  reg  [4:0]        st_98_score;
+  reg  [4:0]        st_99_score;
+  reg  [4:0]        st_100_score;
+  reg  [4:0]        st_101_score;
+  reg  [4:0]        st_102_score;
+  reg  [4:0]        st_103_score;
+  reg  [4:0]        st_104_score;
+  reg  [4:0]        st_105_score;
+  reg  [4:0]        st_106_score;
+  reg  [4:0]        st_107_score;
+  reg  [4:0]        st_108_score;
+  reg  [6:0]        ptr;
+  reg  [5:0]        round;
+  reg  [9:0]        bestOffset;
+  reg  [4:0]        bestScore;
+  reg               state;
+  wire              io_test_req_valid_0 = state & io_req_valid;
+  wire              roundFinish = ptr == 7'h6C;
+  wire [127:0][9:0] _GEN_0 =
+    '{10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'h38B,
+      10'hFA,
+      10'hF3,
+      10'hF0,
+      10'hE1,
+      10'hD8,
+      10'hC8,
+      10'hC0,
+      10'hB4,
+      10'hA2,
+      10'hA0,
+      10'h96,
+      10'h90,
+      10'h87,
+      10'h80,
+      10'h7D,
+      10'h78,
+      10'h6C,
+      10'h64,
+      10'h60,
+      10'h5A,
+      10'h51,
+      10'h50,
+      10'h4B,
+      10'h48,
+      10'h40,
+      10'h3C,
+      10'h36,
+      10'h32,
+      10'h30,
+      10'h2D,
+      10'h28,
+      10'h24,
+      10'h20,
+      10'h1E,
+      10'h1B,
+      10'h19,
+      10'h18,
+      10'h14,
+      10'h12,
+      10'h10,
+      10'hF,
+      10'hC,
+      10'hA,
+      10'h9,
+      10'h8,
+      10'h6,
+      10'h5,
+      10'h4,
+      10'h3,
+      10'h2,
+      10'h1,
+      10'h3FF,
+      10'h3FE,
+      10'h3FD,
+      10'h3FC,
+      10'h3FB,
+      10'h3FA,
+      10'h3F8,
+      10'h3F7,
+      10'h3F6,
+      10'h3F4,
+      10'h3F1,
+      10'h3F0,
+      10'h3EE,
+      10'h3EC,
+      10'h3E8,
+      10'h3E7,
+      10'h3E5,
+      10'h3E2,
+      10'h3E0,
+      10'h3DC,
+      10'h3D8,
+      10'h3D3,
+      10'h3D0,
+      10'h3CE,
+      10'h3CA,
+      10'h3C4,
+      10'h3C0,
+      10'h3B8,
+      10'h3B5,
+      10'h3B0,
+      10'h3AF,
+      10'h3A6,
+      10'h3A0,
+      10'h39C,
+      10'h394,
+      10'h388,
+      10'h383,
+      10'h380,
+      10'h379,
+      10'h370,
+      10'h36A,
+      10'h360,
+      10'h35E,
+      10'h34C,
+      10'h340,
+      10'h338,
+      10'h328,
+      10'h31F,
+      10'h310,
+      10'h30D,
+      10'h306,
+      10'h300,
+      10'h5B,
+      10'h93,
+      10'h75,
+      10'h3A5,
+      10'h36D,
+      10'h38B};
+  wire              _GEN_1 = {58'h0, round} > 64'h31;
+  wire              _GEN_2 = io_test_resp_valid & io_test_resp_bits_hit;
+  wire [127:0][4:0] _GEN_3 =
+    {{st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_0_score},
+     {st_108_score},
+     {st_107_score},
+     {st_106_score},
+     {st_105_score},
+     {st_104_score},
+     {st_103_score},
+     {st_102_score},
+     {st_101_score},
+     {st_100_score},
+     {st_99_score},
+     {st_98_score},
+     {st_97_score},
+     {st_96_score},
+     {st_95_score},
+     {st_94_score},
+     {st_93_score},
+     {st_92_score},
+     {st_91_score},
+     {st_90_score},
+     {st_89_score},
+     {st_88_score},
+     {st_87_score},
+     {st_86_score},
+     {st_85_score},
+     {st_84_score},
+     {st_83_score},
+     {st_82_score},
+     {st_81_score},
+     {st_80_score},
+     {st_79_score},
+     {st_78_score},
+     {st_77_score},
+     {st_76_score},
+     {st_75_score},
+     {st_74_score},
+     {st_73_score},
+     {st_72_score},
+     {st_71_score},
+     {st_70_score},
+     {st_69_score},
+     {st_68_score},
+     {st_67_score},
+     {st_66_score},
+     {st_65_score},
+     {st_64_score},
+     {st_63_score},
+     {st_62_score},
+     {st_61_score},
+     {st_60_score},
+     {st_59_score},
+     {st_58_score},
+     {st_57_score},
+     {st_56_score},
+     {st_55_score},
+     {st_54_score},
+     {st_53_score},
+     {st_52_score},
+     {st_51_score},
+     {st_50_score},
+     {st_49_score},
+     {st_48_score},
+     {st_47_score},
+     {st_46_score},
+     {st_45_score},
+     {st_44_score},
+     {st_43_score},
+     {st_42_score},
+     {st_41_score},
+     {st_40_score},
+     {st_39_score},
+     {st_38_score},
+     {st_37_score},
+     {st_36_score},
+     {st_35_score},
+     {st_34_score},
+     {st_33_score},
+     {st_32_score},
+     {st_31_score},
+     {st_30_score},
+     {st_29_score},
+     {st_28_score},
+     {st_27_score},
+     {st_26_score},
+     {st_25_score},
+     {st_24_score},
+     {st_23_score},
+     {st_22_score},
+     {st_21_score},
+     {st_20_score},
+     {st_19_score},
+     {st_18_score},
+     {st_17_score},
+     {st_16_score},
+     {st_15_score},
+     {st_14_score},
+     {st_13_score},
+     {st_12_score},
+     {st_11_score},
+     {st_10_score},
+     {st_9_score},
+     {st_8_score},
+     {st_7_score},
+     {st_6_score},
+     {st_5_score},
+     {st_4_score},
+     {st_3_score},
+     {st_2_score},
+     {st_1_score},
+     {st_0_score}};
+  wire [4:0]        _newScore_T = 5'(_GEN_3[io_test_resp_bits_ptr] + 5'h1);
+  wire              renewOffset = _newScore_T > bestScore;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      prefetchOffset <= 10'h2;
+      prefetchDisable <= 1'h0;
+      st_0_score <= 5'h0;
+      st_1_score <= 5'h0;
+      st_2_score <= 5'h0;
+      st_3_score <= 5'h0;
+      st_4_score <= 5'h0;
+      st_5_score <= 5'h0;
+      st_6_score <= 5'h0;
+      st_7_score <= 5'h0;
+      st_8_score <= 5'h0;
+      st_9_score <= 5'h0;
+      st_10_score <= 5'h0;
+      st_11_score <= 5'h0;
+      st_12_score <= 5'h0;
+      st_13_score <= 5'h0;
+      st_14_score <= 5'h0;
+      st_15_score <= 5'h0;
+      st_16_score <= 5'h0;
+      st_17_score <= 5'h0;
+      st_18_score <= 5'h0;
+      st_19_score <= 5'h0;
+      st_20_score <= 5'h0;
+      st_21_score <= 5'h0;
+      st_22_score <= 5'h0;
+      st_23_score <= 5'h0;
+      st_24_score <= 5'h0;
+      st_25_score <= 5'h0;
+      st_26_score <= 5'h0;
+      st_27_score <= 5'h0;
+      st_28_score <= 5'h0;
+      st_29_score <= 5'h0;
+      st_30_score <= 5'h0;
+      st_31_score <= 5'h0;
+      st_32_score <= 5'h0;
+      st_33_score <= 5'h0;
+      st_34_score <= 5'h0;
+      st_35_score <= 5'h0;
+      st_36_score <= 5'h0;
+      st_37_score <= 5'h0;
+      st_38_score <= 5'h0;
+      st_39_score <= 5'h0;
+      st_40_score <= 5'h0;
+      st_41_score <= 5'h0;
+      st_42_score <= 5'h0;
+      st_43_score <= 5'h0;
+      st_44_score <= 5'h0;
+      st_45_score <= 5'h0;
+      st_46_score <= 5'h0;
+      st_47_score <= 5'h0;
+      st_48_score <= 5'h0;
+      st_49_score <= 5'h0;
+      st_50_score <= 5'h0;
+      st_51_score <= 5'h0;
+      st_52_score <= 5'h0;
+      st_53_score <= 5'h0;
+      st_54_score <= 5'h0;
+      st_55_score <= 5'h0;
+      st_56_score <= 5'h0;
+      st_57_score <= 5'h0;
+      st_58_score <= 5'h0;
+      st_59_score <= 5'h0;
+      st_60_score <= 5'h0;
+      st_61_score <= 5'h0;
+      st_62_score <= 5'h0;
+      st_63_score <= 5'h0;
+      st_64_score <= 5'h0;
+      st_65_score <= 5'h0;
+      st_66_score <= 5'h0;
+      st_67_score <= 5'h0;
+      st_68_score <= 5'h0;
+      st_69_score <= 5'h0;
+      st_70_score <= 5'h0;
+      st_71_score <= 5'h0;
+      st_72_score <= 5'h0;
+      st_73_score <= 5'h0;
+      st_74_score <= 5'h0;
+      st_75_score <= 5'h0;
+      st_76_score <= 5'h0;
+      st_77_score <= 5'h0;
+      st_78_score <= 5'h0;
+      st_79_score <= 5'h0;
+      st_80_score <= 5'h0;
+      st_81_score <= 5'h0;
+      st_82_score <= 5'h0;
+      st_83_score <= 5'h0;
+      st_84_score <= 5'h0;
+      st_85_score <= 5'h0;
+      st_86_score <= 5'h0;
+      st_87_score <= 5'h0;
+      st_88_score <= 5'h0;
+      st_89_score <= 5'h0;
+      st_90_score <= 5'h0;
+      st_91_score <= 5'h0;
+      st_92_score <= 5'h0;
+      st_93_score <= 5'h0;
+      st_94_score <= 5'h0;
+      st_95_score <= 5'h0;
+      st_96_score <= 5'h0;
+      st_97_score <= 5'h0;
+      st_98_score <= 5'h0;
+      st_99_score <= 5'h0;
+      st_100_score <= 5'h0;
+      st_101_score <= 5'h0;
+      st_102_score <= 5'h0;
+      st_103_score <= 5'h0;
+      st_104_score <= 5'h0;
+      st_105_score <= 5'h0;
+      st_106_score <= 5'h0;
+      st_107_score <= 5'h0;
+      st_108_score <= 5'h0;
+      ptr <= 7'h0;
+      round <= 6'h0;
+      bestOffset <= 10'h2;
+      bestScore <= 5'h0;
+      state <= 1'h0;
+    end
+    else begin
+      if (state) begin
+      end
+      else begin
+        prefetchOffset <= bestOffset;
+        prefetchDisable <= {59'h0, bestScore} < 64'h2;
+      end
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h0)
+        st_0_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_0_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h1)
+        st_1_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_1_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h2)
+        st_2_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_2_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h3)
+        st_3_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_3_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h4)
+        st_4_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_4_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h5)
+        st_5_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_5_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h6)
+        st_6_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_6_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h7)
+        st_7_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_7_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h8)
+        st_8_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_8_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h9)
+        st_9_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_9_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'hA)
+        st_10_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_10_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'hB)
+        st_11_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_11_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'hC)
+        st_12_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_12_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'hD)
+        st_13_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_13_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'hE)
+        st_14_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_14_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'hF)
+        st_15_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_15_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h10)
+        st_16_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_16_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h11)
+        st_17_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_17_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h12)
+        st_18_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_18_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h13)
+        st_19_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_19_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h14)
+        st_20_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_20_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h15)
+        st_21_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_21_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h16)
+        st_22_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_22_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h17)
+        st_23_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_23_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h18)
+        st_24_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_24_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h19)
+        st_25_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_25_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h1A)
+        st_26_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_26_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h1B)
+        st_27_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_27_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h1C)
+        st_28_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_28_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h1D)
+        st_29_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_29_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h1E)
+        st_30_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_30_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h1F)
+        st_31_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_31_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h20)
+        st_32_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_32_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h21)
+        st_33_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_33_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h22)
+        st_34_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_34_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h23)
+        st_35_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_35_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h24)
+        st_36_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_36_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h25)
+        st_37_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_37_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h26)
+        st_38_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_38_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h27)
+        st_39_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_39_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h28)
+        st_40_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_40_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h29)
+        st_41_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_41_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h2A)
+        st_42_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_42_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h2B)
+        st_43_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_43_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h2C)
+        st_44_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_44_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h2D)
+        st_45_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_45_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h2E)
+        st_46_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_46_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h2F)
+        st_47_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_47_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h30)
+        st_48_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_48_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h31)
+        st_49_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_49_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h32)
+        st_50_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_50_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h33)
+        st_51_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_51_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h34)
+        st_52_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_52_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h35)
+        st_53_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_53_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h36)
+        st_54_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_54_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h37)
+        st_55_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_55_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h38)
+        st_56_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_56_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h39)
+        st_57_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_57_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h3A)
+        st_58_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_58_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h3B)
+        st_59_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_59_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h3C)
+        st_60_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_60_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h3D)
+        st_61_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_61_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h3E)
+        st_62_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_62_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h3F)
+        st_63_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_63_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h40)
+        st_64_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_64_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h41)
+        st_65_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_65_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h42)
+        st_66_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_66_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h43)
+        st_67_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_67_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h44)
+        st_68_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_68_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h45)
+        st_69_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_69_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h46)
+        st_70_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_70_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h47)
+        st_71_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_71_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h48)
+        st_72_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_72_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h49)
+        st_73_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_73_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h4A)
+        st_74_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_74_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h4B)
+        st_75_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_75_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h4C)
+        st_76_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_76_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h4D)
+        st_77_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_77_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h4E)
+        st_78_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_78_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h4F)
+        st_79_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_79_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h50)
+        st_80_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_80_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h51)
+        st_81_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_81_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h52)
+        st_82_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_82_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h53)
+        st_83_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_83_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h54)
+        st_84_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_84_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h55)
+        st_85_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_85_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h56)
+        st_86_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_86_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h57)
+        st_87_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_87_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h58)
+        st_88_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_88_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h59)
+        st_89_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_89_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h5A)
+        st_90_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_90_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h5B)
+        st_91_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_91_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h5C)
+        st_92_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_92_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h5D)
+        st_93_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_93_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h5E)
+        st_94_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_94_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h5F)
+        st_95_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_95_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h60)
+        st_96_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_96_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h61)
+        st_97_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_97_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h62)
+        st_98_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_98_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h63)
+        st_99_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_99_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h64)
+        st_100_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_100_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h65)
+        st_101_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_101_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h66)
+        st_102_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_102_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h67)
+        st_103_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_103_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h68)
+        st_104_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_104_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h69)
+        st_105_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_105_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h6A)
+        st_106_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_106_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h6B)
+        st_107_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_107_score <= 5'h0;
+      if (state & _GEN_2 & io_test_resp_bits_ptr == 7'h6C)
+        st_108_score <= _newScore_T;
+      else if (state) begin
+      end
+      else
+        st_108_score <= 5'h0;
+      if (io_test_req_valid_0) begin
+        ptr <= roundFinish ? 7'h0 : 7'(ptr + 7'h1);
+        if (roundFinish)
+          round <= 6'(round + 6'h1);
+      end
+      else if (state) begin
+      end
+      else begin
+        ptr <= 7'h0;
+        round <= 6'h0;
+      end
+      if (state & _GEN_2 & renewOffset)
+        bestOffset <= _GEN_0[io_test_resp_bits_ptr];
+      if (state & _GEN_2) begin
+        if (renewOffset)
+          bestScore <= _newScore_T;
+      end
+      else if (state) begin
+      end
+      else
+        bestScore <= 5'h0;
+      state <= ~state | (_GEN_2 ? ~((&_newScore_T) | _GEN_1) : ~_GEN_1);
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:18];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h13; i += 5'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        prefetchOffset = _RANDOM[5'h0][9:0];
+        prefetchDisable = _RANDOM[5'h0][10];
+        st_0_score = _RANDOM[5'h0][15:11];
+        st_1_score = _RANDOM[5'h0][20:16];
+        st_2_score = _RANDOM[5'h0][25:21];
+        st_3_score = _RANDOM[5'h0][30:26];
+        st_4_score = {_RANDOM[5'h0][31], _RANDOM[5'h1][3:0]};
+        st_5_score = _RANDOM[5'h1][8:4];
+        st_6_score = _RANDOM[5'h1][13:9];
+        st_7_score = _RANDOM[5'h1][18:14];
+        st_8_score = _RANDOM[5'h1][23:19];
+        st_9_score = _RANDOM[5'h1][28:24];
+        st_10_score = {_RANDOM[5'h1][31:29], _RANDOM[5'h2][1:0]};
+        st_11_score = _RANDOM[5'h2][6:2];
+        st_12_score = _RANDOM[5'h2][11:7];
+        st_13_score = _RANDOM[5'h2][16:12];
+        st_14_score = _RANDOM[5'h2][21:17];
+        st_15_score = _RANDOM[5'h2][26:22];
+        st_16_score = _RANDOM[5'h2][31:27];
+        st_17_score = _RANDOM[5'h3][4:0];
+        st_18_score = _RANDOM[5'h3][9:5];
+        st_19_score = _RANDOM[5'h3][14:10];
+        st_20_score = _RANDOM[5'h3][19:15];
+        st_21_score = _RANDOM[5'h3][24:20];
+        st_22_score = _RANDOM[5'h3][29:25];
+        st_23_score = {_RANDOM[5'h3][31:30], _RANDOM[5'h4][2:0]};
+        st_24_score = _RANDOM[5'h4][7:3];
+        st_25_score = _RANDOM[5'h4][12:8];
+        st_26_score = _RANDOM[5'h4][17:13];
+        st_27_score = _RANDOM[5'h4][22:18];
+        st_28_score = _RANDOM[5'h4][27:23];
+        st_29_score = {_RANDOM[5'h4][31:28], _RANDOM[5'h5][0]};
+        st_30_score = _RANDOM[5'h5][5:1];
+        st_31_score = _RANDOM[5'h5][10:6];
+        st_32_score = _RANDOM[5'h5][15:11];
+        st_33_score = _RANDOM[5'h5][20:16];
+        st_34_score = _RANDOM[5'h5][25:21];
+        st_35_score = _RANDOM[5'h5][30:26];
+        st_36_score = {_RANDOM[5'h5][31], _RANDOM[5'h6][3:0]};
+        st_37_score = _RANDOM[5'h6][8:4];
+        st_38_score = _RANDOM[5'h6][13:9];
+        st_39_score = _RANDOM[5'h6][18:14];
+        st_40_score = _RANDOM[5'h6][23:19];
+        st_41_score = _RANDOM[5'h6][28:24];
+        st_42_score = {_RANDOM[5'h6][31:29], _RANDOM[5'h7][1:0]};
+        st_43_score = _RANDOM[5'h7][6:2];
+        st_44_score = _RANDOM[5'h7][11:7];
+        st_45_score = _RANDOM[5'h7][16:12];
+        st_46_score = _RANDOM[5'h7][21:17];
+        st_47_score = _RANDOM[5'h7][26:22];
+        st_48_score = _RANDOM[5'h7][31:27];
+        st_49_score = _RANDOM[5'h8][4:0];
+        st_50_score = _RANDOM[5'h8][9:5];
+        st_51_score = _RANDOM[5'h8][14:10];
+        st_52_score = _RANDOM[5'h8][19:15];
+        st_53_score = _RANDOM[5'h8][24:20];
+        st_54_score = _RANDOM[5'h8][29:25];
+        st_55_score = {_RANDOM[5'h8][31:30], _RANDOM[5'h9][2:0]};
+        st_56_score = _RANDOM[5'h9][7:3];
+        st_57_score = _RANDOM[5'h9][12:8];
+        st_58_score = _RANDOM[5'h9][17:13];
+        st_59_score = _RANDOM[5'h9][22:18];
+        st_60_score = _RANDOM[5'h9][27:23];
+        st_61_score = {_RANDOM[5'h9][31:28], _RANDOM[5'hA][0]};
+        st_62_score = _RANDOM[5'hA][5:1];
+        st_63_score = _RANDOM[5'hA][10:6];
+        st_64_score = _RANDOM[5'hA][15:11];
+        st_65_score = _RANDOM[5'hA][20:16];
+        st_66_score = _RANDOM[5'hA][25:21];
+        st_67_score = _RANDOM[5'hA][30:26];
+        st_68_score = {_RANDOM[5'hA][31], _RANDOM[5'hB][3:0]};
+        st_69_score = _RANDOM[5'hB][8:4];
+        st_70_score = _RANDOM[5'hB][13:9];
+        st_71_score = _RANDOM[5'hB][18:14];
+        st_72_score = _RANDOM[5'hB][23:19];
+        st_73_score = _RANDOM[5'hB][28:24];
+        st_74_score = {_RANDOM[5'hB][31:29], _RANDOM[5'hC][1:0]};
+        st_75_score = _RANDOM[5'hC][6:2];
+        st_76_score = _RANDOM[5'hC][11:7];
+        st_77_score = _RANDOM[5'hC][16:12];
+        st_78_score = _RANDOM[5'hC][21:17];
+        st_79_score = _RANDOM[5'hC][26:22];
+        st_80_score = _RANDOM[5'hC][31:27];
+        st_81_score = _RANDOM[5'hD][4:0];
+        st_82_score = _RANDOM[5'hD][9:5];
+        st_83_score = _RANDOM[5'hD][14:10];
+        st_84_score = _RANDOM[5'hD][19:15];
+        st_85_score = _RANDOM[5'hD][24:20];
+        st_86_score = _RANDOM[5'hD][29:25];
+        st_87_score = {_RANDOM[5'hD][31:30], _RANDOM[5'hE][2:0]};
+        st_88_score = _RANDOM[5'hE][7:3];
+        st_89_score = _RANDOM[5'hE][12:8];
+        st_90_score = _RANDOM[5'hE][17:13];
+        st_91_score = _RANDOM[5'hE][22:18];
+        st_92_score = _RANDOM[5'hE][27:23];
+        st_93_score = {_RANDOM[5'hE][31:28], _RANDOM[5'hF][0]};
+        st_94_score = _RANDOM[5'hF][5:1];
+        st_95_score = _RANDOM[5'hF][10:6];
+        st_96_score = _RANDOM[5'hF][15:11];
+        st_97_score = _RANDOM[5'hF][20:16];
+        st_98_score = _RANDOM[5'hF][25:21];
+        st_99_score = _RANDOM[5'hF][30:26];
+        st_100_score = {_RANDOM[5'hF][31], _RANDOM[5'h10][3:0]};
+        st_101_score = _RANDOM[5'h10][8:4];
+        st_102_score = _RANDOM[5'h10][13:9];
+        st_103_score = _RANDOM[5'h10][18:14];
+        st_104_score = _RANDOM[5'h10][23:19];
+        st_105_score = _RANDOM[5'h10][28:24];
+        st_106_score = {_RANDOM[5'h10][31:29], _RANDOM[5'h11][1:0]};
+        st_107_score = _RANDOM[5'h11][6:2];
+        st_108_score = _RANDOM[5'h11][11:7];
+        ptr = _RANDOM[5'h11][18:12];
+        round = _RANDOM[5'h11][24:19];
+        bestOffset = {_RANDOM[5'h11][31:25], _RANDOM[5'h12][2:0]};
+        bestScore = _RANDOM[5'h12][7:3];
+        state = _RANDOM[5'h12][8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        prefetchOffset = 10'h2;
+        prefetchDisable = 1'h0;
+        st_0_score = 5'h0;
+        st_1_score = 5'h0;
+        st_2_score = 5'h0;
+        st_3_score = 5'h0;
+        st_4_score = 5'h0;
+        st_5_score = 5'h0;
+        st_6_score = 5'h0;
+        st_7_score = 5'h0;
+        st_8_score = 5'h0;
+        st_9_score = 5'h0;
+        st_10_score = 5'h0;
+        st_11_score = 5'h0;
+        st_12_score = 5'h0;
+        st_13_score = 5'h0;
+        st_14_score = 5'h0;
+        st_15_score = 5'h0;
+        st_16_score = 5'h0;
+        st_17_score = 5'h0;
+        st_18_score = 5'h0;
+        st_19_score = 5'h0;
+        st_20_score = 5'h0;
+        st_21_score = 5'h0;
+        st_22_score = 5'h0;
+        st_23_score = 5'h0;
+        st_24_score = 5'h0;
+        st_25_score = 5'h0;
+        st_26_score = 5'h0;
+        st_27_score = 5'h0;
+        st_28_score = 5'h0;
+        st_29_score = 5'h0;
+        st_30_score = 5'h0;
+        st_31_score = 5'h0;
+        st_32_score = 5'h0;
+        st_33_score = 5'h0;
+        st_34_score = 5'h0;
+        st_35_score = 5'h0;
+        st_36_score = 5'h0;
+        st_37_score = 5'h0;
+        st_38_score = 5'h0;
+        st_39_score = 5'h0;
+        st_40_score = 5'h0;
+        st_41_score = 5'h0;
+        st_42_score = 5'h0;
+        st_43_score = 5'h0;
+        st_44_score = 5'h0;
+        st_45_score = 5'h0;
+        st_46_score = 5'h0;
+        st_47_score = 5'h0;
+        st_48_score = 5'h0;
+        st_49_score = 5'h0;
+        st_50_score = 5'h0;
+        st_51_score = 5'h0;
+        st_52_score = 5'h0;
+        st_53_score = 5'h0;
+        st_54_score = 5'h0;
+        st_55_score = 5'h0;
+        st_56_score = 5'h0;
+        st_57_score = 5'h0;
+        st_58_score = 5'h0;
+        st_59_score = 5'h0;
+        st_60_score = 5'h0;
+        st_61_score = 5'h0;
+        st_62_score = 5'h0;
+        st_63_score = 5'h0;
+        st_64_score = 5'h0;
+        st_65_score = 5'h0;
+        st_66_score = 5'h0;
+        st_67_score = 5'h0;
+        st_68_score = 5'h0;
+        st_69_score = 5'h0;
+        st_70_score = 5'h0;
+        st_71_score = 5'h0;
+        st_72_score = 5'h0;
+        st_73_score = 5'h0;
+        st_74_score = 5'h0;
+        st_75_score = 5'h0;
+        st_76_score = 5'h0;
+        st_77_score = 5'h0;
+        st_78_score = 5'h0;
+        st_79_score = 5'h0;
+        st_80_score = 5'h0;
+        st_81_score = 5'h0;
+        st_82_score = 5'h0;
+        st_83_score = 5'h0;
+        st_84_score = 5'h0;
+        st_85_score = 5'h0;
+        st_86_score = 5'h0;
+        st_87_score = 5'h0;
+        st_88_score = 5'h0;
+        st_89_score = 5'h0;
+        st_90_score = 5'h0;
+        st_91_score = 5'h0;
+        st_92_score = 5'h0;
+        st_93_score = 5'h0;
+        st_94_score = 5'h0;
+        st_95_score = 5'h0;
+        st_96_score = 5'h0;
+        st_97_score = 5'h0;
+        st_98_score = 5'h0;
+        st_99_score = 5'h0;
+        st_100_score = 5'h0;
+        st_101_score = 5'h0;
+        st_102_score = 5'h0;
+        st_103_score = 5'h0;
+        st_104_score = 5'h0;
+        st_105_score = 5'h0;
+        st_106_score = 5'h0;
+        st_107_score = 5'h0;
+        st_108_score = 5'h0;
+        ptr = 7'h0;
+        round = 6'h0;
+        bestOffset = 10'h2;
+        bestScore = 5'h0;
+        state = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_req_ready = state;
+  assign io_prefetchOffset = prefetchOffset;
+  assign io_prefetchDisable = prefetchDisable;
+  assign io_test_req_valid = io_test_req_valid_0;
+  assign io_test_req_bits_addr = io_req_bits;
+  assign io_test_req_bits_testOffset = _GEN[ptr];
+  assign io_test_req_bits_ptr = ptr;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/OverwriteQueue.sv b/flow/designs/src/xiangshan_coupledl2/deps/OverwriteQueue.sv
new file mode 100644
index 0000000000..ef75ec83b3
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/OverwriteQueue.sv
@@ -0,0 +1,739 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module OverwriteQueue(
+  input         clock,
+  input         reset,
+  input         io_enq_valid,
+  input  [33:0] io_enq_bits_tag,
+  input  [7:0]  io_enq_bits_set,
+  input  [43:0] io_enq_bits_vaddr,
+  input         io_enq_bits_needT,
+  input  [6:0]  io_enq_bits_source,
+  input  [4:0]  io_enq_bits_pfSource,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [33:0] io_deq_bits_tag,
+  output [7:0]  io_deq_bits_set,
+  output [43:0] io_deq_bits_vaddr,
+  output        io_deq_bits_needT,
+  output [6:0]  io_deq_bits_source,
+  output [4:0]  io_deq_bits_pfSource
+);
+
+  reg  [33:0]       queue_0_tag;
+  reg  [7:0]        queue_0_set;
+  reg  [43:0]       queue_0_vaddr;
+  reg               queue_0_needT;
+  reg  [6:0]        queue_0_source;
+  reg  [4:0]        queue_0_pfSource;
+  reg  [33:0]       queue_1_tag;
+  reg  [7:0]        queue_1_set;
+  reg  [43:0]       queue_1_vaddr;
+  reg               queue_1_needT;
+  reg  [6:0]        queue_1_source;
+  reg  [4:0]        queue_1_pfSource;
+  reg  [33:0]       queue_2_tag;
+  reg  [7:0]        queue_2_set;
+  reg  [43:0]       queue_2_vaddr;
+  reg               queue_2_needT;
+  reg  [6:0]        queue_2_source;
+  reg  [4:0]        queue_2_pfSource;
+  reg  [33:0]       queue_3_tag;
+  reg  [7:0]        queue_3_set;
+  reg  [43:0]       queue_3_vaddr;
+  reg               queue_3_needT;
+  reg  [6:0]        queue_3_source;
+  reg  [4:0]        queue_3_pfSource;
+  reg  [33:0]       queue_4_tag;
+  reg  [7:0]        queue_4_set;
+  reg  [43:0]       queue_4_vaddr;
+  reg               queue_4_needT;
+  reg  [6:0]        queue_4_source;
+  reg  [4:0]        queue_4_pfSource;
+  reg  [33:0]       queue_5_tag;
+  reg  [7:0]        queue_5_set;
+  reg  [43:0]       queue_5_vaddr;
+  reg               queue_5_needT;
+  reg  [6:0]        queue_5_source;
+  reg  [4:0]        queue_5_pfSource;
+  reg  [33:0]       queue_6_tag;
+  reg  [7:0]        queue_6_set;
+  reg  [43:0]       queue_6_vaddr;
+  reg               queue_6_needT;
+  reg  [6:0]        queue_6_source;
+  reg  [4:0]        queue_6_pfSource;
+  reg  [33:0]       queue_7_tag;
+  reg  [7:0]        queue_7_set;
+  reg  [43:0]       queue_7_vaddr;
+  reg               queue_7_needT;
+  reg  [6:0]        queue_7_source;
+  reg  [4:0]        queue_7_pfSource;
+  reg  [33:0]       queue_8_tag;
+  reg  [7:0]        queue_8_set;
+  reg  [43:0]       queue_8_vaddr;
+  reg               queue_8_needT;
+  reg  [6:0]        queue_8_source;
+  reg  [4:0]        queue_8_pfSource;
+  reg  [33:0]       queue_9_tag;
+  reg  [7:0]        queue_9_set;
+  reg  [43:0]       queue_9_vaddr;
+  reg               queue_9_needT;
+  reg  [6:0]        queue_9_source;
+  reg  [4:0]        queue_9_pfSource;
+  reg  [33:0]       queue_10_tag;
+  reg  [7:0]        queue_10_set;
+  reg  [43:0]       queue_10_vaddr;
+  reg               queue_10_needT;
+  reg  [6:0]        queue_10_source;
+  reg  [4:0]        queue_10_pfSource;
+  reg  [33:0]       queue_11_tag;
+  reg  [7:0]        queue_11_set;
+  reg  [43:0]       queue_11_vaddr;
+  reg               queue_11_needT;
+  reg  [6:0]        queue_11_source;
+  reg  [4:0]        queue_11_pfSource;
+  reg  [33:0]       queue_12_tag;
+  reg  [7:0]        queue_12_set;
+  reg  [43:0]       queue_12_vaddr;
+  reg               queue_12_needT;
+  reg  [6:0]        queue_12_source;
+  reg  [4:0]        queue_12_pfSource;
+  reg  [33:0]       queue_13_tag;
+  reg  [7:0]        queue_13_set;
+  reg  [43:0]       queue_13_vaddr;
+  reg               queue_13_needT;
+  reg  [6:0]        queue_13_source;
+  reg  [4:0]        queue_13_pfSource;
+  reg  [33:0]       queue_14_tag;
+  reg  [7:0]        queue_14_set;
+  reg  [43:0]       queue_14_vaddr;
+  reg               queue_14_needT;
+  reg  [6:0]        queue_14_source;
+  reg  [4:0]        queue_14_pfSource;
+  reg  [33:0]       queue_15_tag;
+  reg  [7:0]        queue_15_set;
+  reg  [43:0]       queue_15_vaddr;
+  reg               queue_15_needT;
+  reg  [6:0]        queue_15_source;
+  reg  [4:0]        queue_15_pfSource;
+  reg               maybe_full;
+  reg  [3:0]        headPtr;
+  reg  [3:0]        tailPtr;
+  wire              _empty_T = headPtr == tailPtr;
+  wire              empty = _empty_T & ~maybe_full;
+  wire              deq_valid = ~empty | io_enq_valid;
+  wire              flowHappens = empty & io_enq_valid & io_deq_ready;
+  wire [15:0][33:0] _GEN =
+    {{queue_15_tag},
+     {queue_14_tag},
+     {queue_13_tag},
+     {queue_12_tag},
+     {queue_11_tag},
+     {queue_10_tag},
+     {queue_9_tag},
+     {queue_8_tag},
+     {queue_7_tag},
+     {queue_6_tag},
+     {queue_5_tag},
+     {queue_4_tag},
+     {queue_3_tag},
+     {queue_2_tag},
+     {queue_1_tag},
+     {queue_0_tag}};
+  wire [15:0][7:0]  _GEN_0 =
+    {{queue_15_set},
+     {queue_14_set},
+     {queue_13_set},
+     {queue_12_set},
+     {queue_11_set},
+     {queue_10_set},
+     {queue_9_set},
+     {queue_8_set},
+     {queue_7_set},
+     {queue_6_set},
+     {queue_5_set},
+     {queue_4_set},
+     {queue_3_set},
+     {queue_2_set},
+     {queue_1_set},
+     {queue_0_set}};
+  wire [15:0][43:0] _GEN_1 =
+    {{queue_15_vaddr},
+     {queue_14_vaddr},
+     {queue_13_vaddr},
+     {queue_12_vaddr},
+     {queue_11_vaddr},
+     {queue_10_vaddr},
+     {queue_9_vaddr},
+     {queue_8_vaddr},
+     {queue_7_vaddr},
+     {queue_6_vaddr},
+     {queue_5_vaddr},
+     {queue_4_vaddr},
+     {queue_3_vaddr},
+     {queue_2_vaddr},
+     {queue_1_vaddr},
+     {queue_0_vaddr}};
+  wire [15:0]       _GEN_2 =
+    {{queue_15_needT},
+     {queue_14_needT},
+     {queue_13_needT},
+     {queue_12_needT},
+     {queue_11_needT},
+     {queue_10_needT},
+     {queue_9_needT},
+     {queue_8_needT},
+     {queue_7_needT},
+     {queue_6_needT},
+     {queue_5_needT},
+     {queue_4_needT},
+     {queue_3_needT},
+     {queue_2_needT},
+     {queue_1_needT},
+     {queue_0_needT}};
+  wire [15:0][6:0]  _GEN_3 =
+    {{queue_15_source},
+     {queue_14_source},
+     {queue_13_source},
+     {queue_12_source},
+     {queue_11_source},
+     {queue_10_source},
+     {queue_9_source},
+     {queue_8_source},
+     {queue_7_source},
+     {queue_6_source},
+     {queue_5_source},
+     {queue_4_source},
+     {queue_3_source},
+     {queue_2_source},
+     {queue_1_source},
+     {queue_0_source}};
+  wire [15:0][4:0]  _GEN_4 =
+    {{queue_15_pfSource},
+     {queue_14_pfSource},
+     {queue_13_pfSource},
+     {queue_12_pfSource},
+     {queue_11_pfSource},
+     {queue_10_pfSource},
+     {queue_9_pfSource},
+     {queue_8_pfSource},
+     {queue_7_pfSource},
+     {queue_6_pfSource},
+     {queue_5_pfSource},
+     {queue_4_pfSource},
+     {queue_3_pfSource},
+     {queue_2_pfSource},
+     {queue_1_pfSource},
+     {queue_0_pfSource}};
+  wire              do_deq = deq_valid & io_deq_ready;
+  wire              overwriteHappens = _empty_T & maybe_full & io_enq_valid & ~do_deq;
+  wire              _GEN_5 = io_enq_valid & ~flowHappens;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      queue_0_tag <= 34'h0;
+      queue_0_set <= 8'h0;
+      queue_0_vaddr <= 44'h0;
+      queue_0_needT <= 1'h0;
+      queue_0_source <= 7'h0;
+      queue_0_pfSource <= 5'h0;
+      queue_1_tag <= 34'h0;
+      queue_1_set <= 8'h0;
+      queue_1_vaddr <= 44'h0;
+      queue_1_needT <= 1'h0;
+      queue_1_source <= 7'h0;
+      queue_1_pfSource <= 5'h0;
+      queue_2_tag <= 34'h0;
+      queue_2_set <= 8'h0;
+      queue_2_vaddr <= 44'h0;
+      queue_2_needT <= 1'h0;
+      queue_2_source <= 7'h0;
+      queue_2_pfSource <= 5'h0;
+      queue_3_tag <= 34'h0;
+      queue_3_set <= 8'h0;
+      queue_3_vaddr <= 44'h0;
+      queue_3_needT <= 1'h0;
+      queue_3_source <= 7'h0;
+      queue_3_pfSource <= 5'h0;
+      queue_4_tag <= 34'h0;
+      queue_4_set <= 8'h0;
+      queue_4_vaddr <= 44'h0;
+      queue_4_needT <= 1'h0;
+      queue_4_source <= 7'h0;
+      queue_4_pfSource <= 5'h0;
+      queue_5_tag <= 34'h0;
+      queue_5_set <= 8'h0;
+      queue_5_vaddr <= 44'h0;
+      queue_5_needT <= 1'h0;
+      queue_5_source <= 7'h0;
+      queue_5_pfSource <= 5'h0;
+      queue_6_tag <= 34'h0;
+      queue_6_set <= 8'h0;
+      queue_6_vaddr <= 44'h0;
+      queue_6_needT <= 1'h0;
+      queue_6_source <= 7'h0;
+      queue_6_pfSource <= 5'h0;
+      queue_7_tag <= 34'h0;
+      queue_7_set <= 8'h0;
+      queue_7_vaddr <= 44'h0;
+      queue_7_needT <= 1'h0;
+      queue_7_source <= 7'h0;
+      queue_7_pfSource <= 5'h0;
+      queue_8_tag <= 34'h0;
+      queue_8_set <= 8'h0;
+      queue_8_vaddr <= 44'h0;
+      queue_8_needT <= 1'h0;
+      queue_8_source <= 7'h0;
+      queue_8_pfSource <= 5'h0;
+      queue_9_tag <= 34'h0;
+      queue_9_set <= 8'h0;
+      queue_9_vaddr <= 44'h0;
+      queue_9_needT <= 1'h0;
+      queue_9_source <= 7'h0;
+      queue_9_pfSource <= 5'h0;
+      queue_10_tag <= 34'h0;
+      queue_10_set <= 8'h0;
+      queue_10_vaddr <= 44'h0;
+      queue_10_needT <= 1'h0;
+      queue_10_source <= 7'h0;
+      queue_10_pfSource <= 5'h0;
+      queue_11_tag <= 34'h0;
+      queue_11_set <= 8'h0;
+      queue_11_vaddr <= 44'h0;
+      queue_11_needT <= 1'h0;
+      queue_11_source <= 7'h0;
+      queue_11_pfSource <= 5'h0;
+      queue_12_tag <= 34'h0;
+      queue_12_set <= 8'h0;
+      queue_12_vaddr <= 44'h0;
+      queue_12_needT <= 1'h0;
+      queue_12_source <= 7'h0;
+      queue_12_pfSource <= 5'h0;
+      queue_13_tag <= 34'h0;
+      queue_13_set <= 8'h0;
+      queue_13_vaddr <= 44'h0;
+      queue_13_needT <= 1'h0;
+      queue_13_source <= 7'h0;
+      queue_13_pfSource <= 5'h0;
+      queue_14_tag <= 34'h0;
+      queue_14_set <= 8'h0;
+      queue_14_vaddr <= 44'h0;
+      queue_14_needT <= 1'h0;
+      queue_14_source <= 7'h0;
+      queue_14_pfSource <= 5'h0;
+      queue_15_tag <= 34'h0;
+      queue_15_set <= 8'h0;
+      queue_15_vaddr <= 44'h0;
+      queue_15_needT <= 1'h0;
+      queue_15_source <= 7'h0;
+      queue_15_pfSource <= 5'h0;
+      maybe_full <= 1'h0;
+      headPtr <= 4'h0;
+      tailPtr <= 4'h0;
+    end
+    else begin
+      if (_GEN_5 & tailPtr == 4'h0) begin
+        queue_0_tag <= io_enq_bits_tag;
+        queue_0_set <= io_enq_bits_set;
+        queue_0_vaddr <= io_enq_bits_vaddr;
+        queue_0_needT <= io_enq_bits_needT;
+        queue_0_source <= io_enq_bits_source;
+        queue_0_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'h1) begin
+        queue_1_tag <= io_enq_bits_tag;
+        queue_1_set <= io_enq_bits_set;
+        queue_1_vaddr <= io_enq_bits_vaddr;
+        queue_1_needT <= io_enq_bits_needT;
+        queue_1_source <= io_enq_bits_source;
+        queue_1_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'h2) begin
+        queue_2_tag <= io_enq_bits_tag;
+        queue_2_set <= io_enq_bits_set;
+        queue_2_vaddr <= io_enq_bits_vaddr;
+        queue_2_needT <= io_enq_bits_needT;
+        queue_2_source <= io_enq_bits_source;
+        queue_2_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'h3) begin
+        queue_3_tag <= io_enq_bits_tag;
+        queue_3_set <= io_enq_bits_set;
+        queue_3_vaddr <= io_enq_bits_vaddr;
+        queue_3_needT <= io_enq_bits_needT;
+        queue_3_source <= io_enq_bits_source;
+        queue_3_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'h4) begin
+        queue_4_tag <= io_enq_bits_tag;
+        queue_4_set <= io_enq_bits_set;
+        queue_4_vaddr <= io_enq_bits_vaddr;
+        queue_4_needT <= io_enq_bits_needT;
+        queue_4_source <= io_enq_bits_source;
+        queue_4_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'h5) begin
+        queue_5_tag <= io_enq_bits_tag;
+        queue_5_set <= io_enq_bits_set;
+        queue_5_vaddr <= io_enq_bits_vaddr;
+        queue_5_needT <= io_enq_bits_needT;
+        queue_5_source <= io_enq_bits_source;
+        queue_5_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'h6) begin
+        queue_6_tag <= io_enq_bits_tag;
+        queue_6_set <= io_enq_bits_set;
+        queue_6_vaddr <= io_enq_bits_vaddr;
+        queue_6_needT <= io_enq_bits_needT;
+        queue_6_source <= io_enq_bits_source;
+        queue_6_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'h7) begin
+        queue_7_tag <= io_enq_bits_tag;
+        queue_7_set <= io_enq_bits_set;
+        queue_7_vaddr <= io_enq_bits_vaddr;
+        queue_7_needT <= io_enq_bits_needT;
+        queue_7_source <= io_enq_bits_source;
+        queue_7_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'h8) begin
+        queue_8_tag <= io_enq_bits_tag;
+        queue_8_set <= io_enq_bits_set;
+        queue_8_vaddr <= io_enq_bits_vaddr;
+        queue_8_needT <= io_enq_bits_needT;
+        queue_8_source <= io_enq_bits_source;
+        queue_8_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'h9) begin
+        queue_9_tag <= io_enq_bits_tag;
+        queue_9_set <= io_enq_bits_set;
+        queue_9_vaddr <= io_enq_bits_vaddr;
+        queue_9_needT <= io_enq_bits_needT;
+        queue_9_source <= io_enq_bits_source;
+        queue_9_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'hA) begin
+        queue_10_tag <= io_enq_bits_tag;
+        queue_10_set <= io_enq_bits_set;
+        queue_10_vaddr <= io_enq_bits_vaddr;
+        queue_10_needT <= io_enq_bits_needT;
+        queue_10_source <= io_enq_bits_source;
+        queue_10_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'hB) begin
+        queue_11_tag <= io_enq_bits_tag;
+        queue_11_set <= io_enq_bits_set;
+        queue_11_vaddr <= io_enq_bits_vaddr;
+        queue_11_needT <= io_enq_bits_needT;
+        queue_11_source <= io_enq_bits_source;
+        queue_11_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'hC) begin
+        queue_12_tag <= io_enq_bits_tag;
+        queue_12_set <= io_enq_bits_set;
+        queue_12_vaddr <= io_enq_bits_vaddr;
+        queue_12_needT <= io_enq_bits_needT;
+        queue_12_source <= io_enq_bits_source;
+        queue_12_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'hD) begin
+        queue_13_tag <= io_enq_bits_tag;
+        queue_13_set <= io_enq_bits_set;
+        queue_13_vaddr <= io_enq_bits_vaddr;
+        queue_13_needT <= io_enq_bits_needT;
+        queue_13_source <= io_enq_bits_source;
+        queue_13_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & tailPtr == 4'hE) begin
+        queue_14_tag <= io_enq_bits_tag;
+        queue_14_set <= io_enq_bits_set;
+        queue_14_vaddr <= io_enq_bits_vaddr;
+        queue_14_needT <= io_enq_bits_needT;
+        queue_14_source <= io_enq_bits_source;
+        queue_14_pfSource <= io_enq_bits_pfSource;
+      end
+      if (_GEN_5 & (&tailPtr)) begin
+        queue_15_tag <= io_enq_bits_tag;
+        queue_15_set <= io_enq_bits_set;
+        queue_15_vaddr <= io_enq_bits_vaddr;
+        queue_15_needT <= io_enq_bits_needT;
+        queue_15_source <= io_enq_bits_source;
+        queue_15_pfSource <= io_enq_bits_pfSource;
+      end
+      maybe_full <=
+        overwriteHappens | (io_enq_valid == do_deq ? maybe_full : io_enq_valid);
+      if (do_deq | overwriteHappens)
+        headPtr <= (&headPtr) ? 4'h0 : 4'(headPtr + 4'h1);
+      if (io_enq_valid)
+        tailPtr <= (&tailPtr) ? 4'h0 : 4'(tailPtr + 4'h1);
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:49];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [5:0] i = 6'h0; i < 6'h32; i += 6'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        queue_0_tag = {_RANDOM[6'h0], _RANDOM[6'h1][1:0]};
+        queue_0_set = _RANDOM[6'h1][9:2];
+        queue_0_vaddr = {_RANDOM[6'h1][31:10], _RANDOM[6'h2][21:0]};
+        queue_0_needT = _RANDOM[6'h2][22];
+        queue_0_source = _RANDOM[6'h2][29:23];
+        queue_0_pfSource = {_RANDOM[6'h2][31:30], _RANDOM[6'h3][2:0]};
+        queue_1_tag = {_RANDOM[6'h3][31:3], _RANDOM[6'h4][4:0]};
+        queue_1_set = _RANDOM[6'h4][12:5];
+        queue_1_vaddr = {_RANDOM[6'h4][31:13], _RANDOM[6'h5][24:0]};
+        queue_1_needT = _RANDOM[6'h5][25];
+        queue_1_source = {_RANDOM[6'h5][31:26], _RANDOM[6'h6][0]};
+        queue_1_pfSource = _RANDOM[6'h6][5:1];
+        queue_2_tag = {_RANDOM[6'h6][31:6], _RANDOM[6'h7][7:0]};
+        queue_2_set = _RANDOM[6'h7][15:8];
+        queue_2_vaddr = {_RANDOM[6'h7][31:16], _RANDOM[6'h8][27:0]};
+        queue_2_needT = _RANDOM[6'h8][28];
+        queue_2_source = {_RANDOM[6'h8][31:29], _RANDOM[6'h9][3:0]};
+        queue_2_pfSource = _RANDOM[6'h9][8:4];
+        queue_3_tag = {_RANDOM[6'h9][31:9], _RANDOM[6'hA][10:0]};
+        queue_3_set = _RANDOM[6'hA][18:11];
+        queue_3_vaddr = {_RANDOM[6'hA][31:19], _RANDOM[6'hB][30:0]};
+        queue_3_needT = _RANDOM[6'hB][31];
+        queue_3_source = _RANDOM[6'hC][6:0];
+        queue_3_pfSource = _RANDOM[6'hC][11:7];
+        queue_4_tag = {_RANDOM[6'hC][31:12], _RANDOM[6'hD][13:0]};
+        queue_4_set = _RANDOM[6'hD][21:14];
+        queue_4_vaddr = {_RANDOM[6'hD][31:22], _RANDOM[6'hE], _RANDOM[6'hF][1:0]};
+        queue_4_needT = _RANDOM[6'hF][2];
+        queue_4_source = _RANDOM[6'hF][9:3];
+        queue_4_pfSource = _RANDOM[6'hF][14:10];
+        queue_5_tag = {_RANDOM[6'hF][31:15], _RANDOM[6'h10][16:0]};
+        queue_5_set = _RANDOM[6'h10][24:17];
+        queue_5_vaddr = {_RANDOM[6'h10][31:25], _RANDOM[6'h11], _RANDOM[6'h12][4:0]};
+        queue_5_needT = _RANDOM[6'h12][5];
+        queue_5_source = _RANDOM[6'h12][12:6];
+        queue_5_pfSource = _RANDOM[6'h12][17:13];
+        queue_6_tag = {_RANDOM[6'h12][31:18], _RANDOM[6'h13][19:0]};
+        queue_6_set = _RANDOM[6'h13][27:20];
+        queue_6_vaddr = {_RANDOM[6'h13][31:28], _RANDOM[6'h14], _RANDOM[6'h15][7:0]};
+        queue_6_needT = _RANDOM[6'h15][8];
+        queue_6_source = _RANDOM[6'h15][15:9];
+        queue_6_pfSource = _RANDOM[6'h15][20:16];
+        queue_7_tag = {_RANDOM[6'h15][31:21], _RANDOM[6'h16][22:0]};
+        queue_7_set = _RANDOM[6'h16][30:23];
+        queue_7_vaddr = {_RANDOM[6'h16][31], _RANDOM[6'h17], _RANDOM[6'h18][10:0]};
+        queue_7_needT = _RANDOM[6'h18][11];
+        queue_7_source = _RANDOM[6'h18][18:12];
+        queue_7_pfSource = _RANDOM[6'h18][23:19];
+        queue_8_tag = {_RANDOM[6'h18][31:24], _RANDOM[6'h19][25:0]};
+        queue_8_set = {_RANDOM[6'h19][31:26], _RANDOM[6'h1A][1:0]};
+        queue_8_vaddr = {_RANDOM[6'h1A][31:2], _RANDOM[6'h1B][13:0]};
+        queue_8_needT = _RANDOM[6'h1B][14];
+        queue_8_source = _RANDOM[6'h1B][21:15];
+        queue_8_pfSource = _RANDOM[6'h1B][26:22];
+        queue_9_tag = {_RANDOM[6'h1B][31:27], _RANDOM[6'h1C][28:0]};
+        queue_9_set = {_RANDOM[6'h1C][31:29], _RANDOM[6'h1D][4:0]};
+        queue_9_vaddr = {_RANDOM[6'h1D][31:5], _RANDOM[6'h1E][16:0]};
+        queue_9_needT = _RANDOM[6'h1E][17];
+        queue_9_source = _RANDOM[6'h1E][24:18];
+        queue_9_pfSource = _RANDOM[6'h1E][29:25];
+        queue_10_tag = {_RANDOM[6'h1E][31:30], _RANDOM[6'h1F]};
+        queue_10_set = _RANDOM[6'h20][7:0];
+        queue_10_vaddr = {_RANDOM[6'h20][31:8], _RANDOM[6'h21][19:0]};
+        queue_10_needT = _RANDOM[6'h21][20];
+        queue_10_source = _RANDOM[6'h21][27:21];
+        queue_10_pfSource = {_RANDOM[6'h21][31:28], _RANDOM[6'h22][0]};
+        queue_11_tag = {_RANDOM[6'h22][31:1], _RANDOM[6'h23][2:0]};
+        queue_11_set = _RANDOM[6'h23][10:3];
+        queue_11_vaddr = {_RANDOM[6'h23][31:11], _RANDOM[6'h24][22:0]};
+        queue_11_needT = _RANDOM[6'h24][23];
+        queue_11_source = _RANDOM[6'h24][30:24];
+        queue_11_pfSource = {_RANDOM[6'h24][31], _RANDOM[6'h25][3:0]};
+        queue_12_tag = {_RANDOM[6'h25][31:4], _RANDOM[6'h26][5:0]};
+        queue_12_set = _RANDOM[6'h26][13:6];
+        queue_12_vaddr = {_RANDOM[6'h26][31:14], _RANDOM[6'h27][25:0]};
+        queue_12_needT = _RANDOM[6'h27][26];
+        queue_12_source = {_RANDOM[6'h27][31:27], _RANDOM[6'h28][1:0]};
+        queue_12_pfSource = _RANDOM[6'h28][6:2];
+        queue_13_tag = {_RANDOM[6'h28][31:7], _RANDOM[6'h29][8:0]};
+        queue_13_set = _RANDOM[6'h29][16:9];
+        queue_13_vaddr = {_RANDOM[6'h29][31:17], _RANDOM[6'h2A][28:0]};
+        queue_13_needT = _RANDOM[6'h2A][29];
+        queue_13_source = {_RANDOM[6'h2A][31:30], _RANDOM[6'h2B][4:0]};
+        queue_13_pfSource = _RANDOM[6'h2B][9:5];
+        queue_14_tag = {_RANDOM[6'h2B][31:10], _RANDOM[6'h2C][11:0]};
+        queue_14_set = _RANDOM[6'h2C][19:12];
+        queue_14_vaddr = {_RANDOM[6'h2C][31:20], _RANDOM[6'h2D]};
+        queue_14_needT = _RANDOM[6'h2E][0];
+        queue_14_source = _RANDOM[6'h2E][7:1];
+        queue_14_pfSource = _RANDOM[6'h2E][12:8];
+        queue_15_tag = {_RANDOM[6'h2E][31:13], _RANDOM[6'h2F][14:0]};
+        queue_15_set = _RANDOM[6'h2F][22:15];
+        queue_15_vaddr = {_RANDOM[6'h2F][31:23], _RANDOM[6'h30], _RANDOM[6'h31][2:0]};
+        queue_15_needT = _RANDOM[6'h31][3];
+        queue_15_source = _RANDOM[6'h31][10:4];
+        queue_15_pfSource = _RANDOM[6'h31][15:11];
+        maybe_full = _RANDOM[6'h31][16];
+        headPtr = _RANDOM[6'h31][20:17];
+        tailPtr = _RANDOM[6'h31][24:21];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        queue_0_tag = 34'h0;
+        queue_0_set = 8'h0;
+        queue_0_vaddr = 44'h0;
+        queue_0_needT = 1'h0;
+        queue_0_source = 7'h0;
+        queue_0_pfSource = 5'h0;
+        queue_1_tag = 34'h0;
+        queue_1_set = 8'h0;
+        queue_1_vaddr = 44'h0;
+        queue_1_needT = 1'h0;
+        queue_1_source = 7'h0;
+        queue_1_pfSource = 5'h0;
+        queue_2_tag = 34'h0;
+        queue_2_set = 8'h0;
+        queue_2_vaddr = 44'h0;
+        queue_2_needT = 1'h0;
+        queue_2_source = 7'h0;
+        queue_2_pfSource = 5'h0;
+        queue_3_tag = 34'h0;
+        queue_3_set = 8'h0;
+        queue_3_vaddr = 44'h0;
+        queue_3_needT = 1'h0;
+        queue_3_source = 7'h0;
+        queue_3_pfSource = 5'h0;
+        queue_4_tag = 34'h0;
+        queue_4_set = 8'h0;
+        queue_4_vaddr = 44'h0;
+        queue_4_needT = 1'h0;
+        queue_4_source = 7'h0;
+        queue_4_pfSource = 5'h0;
+        queue_5_tag = 34'h0;
+        queue_5_set = 8'h0;
+        queue_5_vaddr = 44'h0;
+        queue_5_needT = 1'h0;
+        queue_5_source = 7'h0;
+        queue_5_pfSource = 5'h0;
+        queue_6_tag = 34'h0;
+        queue_6_set = 8'h0;
+        queue_6_vaddr = 44'h0;
+        queue_6_needT = 1'h0;
+        queue_6_source = 7'h0;
+        queue_6_pfSource = 5'h0;
+        queue_7_tag = 34'h0;
+        queue_7_set = 8'h0;
+        queue_7_vaddr = 44'h0;
+        queue_7_needT = 1'h0;
+        queue_7_source = 7'h0;
+        queue_7_pfSource = 5'h0;
+        queue_8_tag = 34'h0;
+        queue_8_set = 8'h0;
+        queue_8_vaddr = 44'h0;
+        queue_8_needT = 1'h0;
+        queue_8_source = 7'h0;
+        queue_8_pfSource = 5'h0;
+        queue_9_tag = 34'h0;
+        queue_9_set = 8'h0;
+        queue_9_vaddr = 44'h0;
+        queue_9_needT = 1'h0;
+        queue_9_source = 7'h0;
+        queue_9_pfSource = 5'h0;
+        queue_10_tag = 34'h0;
+        queue_10_set = 8'h0;
+        queue_10_vaddr = 44'h0;
+        queue_10_needT = 1'h0;
+        queue_10_source = 7'h0;
+        queue_10_pfSource = 5'h0;
+        queue_11_tag = 34'h0;
+        queue_11_set = 8'h0;
+        queue_11_vaddr = 44'h0;
+        queue_11_needT = 1'h0;
+        queue_11_source = 7'h0;
+        queue_11_pfSource = 5'h0;
+        queue_12_tag = 34'h0;
+        queue_12_set = 8'h0;
+        queue_12_vaddr = 44'h0;
+        queue_12_needT = 1'h0;
+        queue_12_source = 7'h0;
+        queue_12_pfSource = 5'h0;
+        queue_13_tag = 34'h0;
+        queue_13_set = 8'h0;
+        queue_13_vaddr = 44'h0;
+        queue_13_needT = 1'h0;
+        queue_13_source = 7'h0;
+        queue_13_pfSource = 5'h0;
+        queue_14_tag = 34'h0;
+        queue_14_set = 8'h0;
+        queue_14_vaddr = 44'h0;
+        queue_14_needT = 1'h0;
+        queue_14_source = 7'h0;
+        queue_14_pfSource = 5'h0;
+        queue_15_tag = 34'h0;
+        queue_15_set = 8'h0;
+        queue_15_vaddr = 44'h0;
+        queue_15_needT = 1'h0;
+        queue_15_source = 7'h0;
+        queue_15_pfSource = 5'h0;
+        maybe_full = 1'h0;
+        headPtr = 4'h0;
+        tailPtr = 4'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_deq_valid = deq_valid;
+  assign io_deq_bits_tag = flowHappens ? io_enq_bits_tag : _GEN[headPtr];
+  assign io_deq_bits_set = flowHappens ? io_enq_bits_set : _GEN_0[headPtr];
+  assign io_deq_bits_vaddr = flowHappens ? io_enq_bits_vaddr : _GEN_1[headPtr];
+  assign io_deq_bits_needT = flowHappens ? io_enq_bits_needT : _GEN_2[headPtr];
+  assign io_deq_bits_source = flowHappens ? io_enq_bits_source : _GEN_3[headPtr];
+  assign io_deq_bits_pfSource = flowHappens ? io_enq_bits_pfSource : _GEN_4[headPtr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/PBestOffsetPrefetch.sv b/flow/designs/src/xiangshan_coupledl2/deps/PBestOffsetPrefetch.sv
new file mode 100644
index 0000000000..58c2603e11
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/PBestOffsetPrefetch.sv
@@ -0,0 +1,216 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module PBestOffsetPrefetch(
+  input         clock,
+  input         reset,
+  input         io_enable,
+  input  [9:0]  io_pfCtrlOfDelayLatency,
+  output        io_train_ready,
+  input         io_train_valid,
+  input  [33:0] io_train_bits_tag,
+  input  [7:0]  io_train_bits_set,
+  input         io_train_bits_needT,
+  input  [6:0]  io_train_bits_source,
+  input         io_req_ready,
+  output        io_req_valid,
+  output [33:0] io_req_bits_tag,
+  output [7:0]  io_req_bits_set,
+  output [43:0] io_req_bits_vaddr,
+  output        io_req_bits_needT,
+  output [6:0]  io_req_bits_source,
+  output        io_resp_ready,
+  input  [8:0]  boreChildrenBd_bore_addr,
+  input  [8:0]  boreChildrenBd_bore_addr_rd,
+  input  [12:0] boreChildrenBd_bore_wdata,
+  input         boreChildrenBd_bore_wmask,
+  input         boreChildrenBd_bore_re,
+  input         boreChildrenBd_bore_we,
+  output [12:0] boreChildrenBd_bore_rdata,
+  input         boreChildrenBd_bore_ack,
+  input         boreChildrenBd_bore_selectedOH,
+  input         boreChildrenBd_bore_array,
+  input         sigFromSrams_bore_ram_hold,
+  input         sigFromSrams_bore_ram_bypass,
+  input         sigFromSrams_bore_ram_bp_clken,
+  input         sigFromSrams_bore_ram_aux_clk,
+  input         sigFromSrams_bore_ram_aux_ckbp,
+  input         sigFromSrams_bore_ram_mcp_hold,
+  input         sigFromSrams_bore_cgen
+);
+
+  wire        _scoreTable_io_req_ready;
+  wire [6:0]  _scoreTable_io_prefetchOffset;
+  wire        _scoreTable_io_prefetchDisable;
+  wire        _scoreTable_io_test_req_valid;
+  wire [47:0] _scoreTable_io_test_req_bits_addr;
+  wire [6:0]  _scoreTable_io_test_req_bits_testOffset;
+  wire [5:0]  _scoreTable_io_test_req_bits_ptr;
+  wire        _rrTable_io_w_ready;
+  wire        _rrTable_io_r_resp_valid;
+  wire [5:0]  _rrTable_io_r_resp_bits_ptr;
+  wire        _rrTable_io_r_resp_bits_hit;
+  wire        _delayQueue_io_out_valid;
+  wire [47:0] _delayQueue_io_out_bits;
+  wire [47:0] _newAddr_T_5 =
+    48'({io_train_bits_tag, io_train_bits_set, 6'h0}
+        + {{35{_scoreTable_io_prefetchOffset[6]}}, _scoreTable_io_prefetchOffset, 6'h0});
+  reg  [33:0] req_tag;
+  reg  [7:0]  req_set;
+  reg         req_needT;
+  reg  [6:0]  req_source;
+  reg         req_valid;
+  wire        _GEN = _scoreTable_io_req_ready & io_train_valid;
+  wire        io_req_valid_0 = io_enable & req_valid;
+  always @(posedge clock) begin
+    if (_GEN) begin
+      req_tag <= _newAddr_T_5[47:14];
+      req_set <= _newAddr_T_5[13:6];
+      req_needT <= io_train_bits_needT;
+      req_source <= io_train_bits_source;
+    end
+  end // always @(posedge)
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      req_valid <= 1'h0;
+    else
+      req_valid <=
+        _GEN
+          ? _newAddr_T_5[47:12] == {io_train_bits_tag, io_train_bits_set[7:6]}
+            & ~_scoreTable_io_prefetchDisable
+          : ~(io_req_ready & io_req_valid_0) & req_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:3];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
+          _RANDOM[i[1:0]] = `RANDOM;
+        end
+        req_tag = {_RANDOM[2'h0], _RANDOM[2'h1][1:0]};
+        req_set = _RANDOM[2'h1][9:2];
+        req_needT = _RANDOM[2'h2][22];
+        req_source = _RANDOM[2'h2][29:23];
+        req_valid = _RANDOM[2'h3][3];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        req_valid = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  DelayQueue delayQueue (
+    .clock                   (clock),
+    .reset                   (reset),
+    .io_pfCtrlOfDelayLatency (io_pfCtrlOfDelayLatency),
+    .io_in_valid             (io_train_valid),
+    .io_in_bits              ({io_train_bits_tag, io_train_bits_set}),
+    .io_out_ready            (_rrTable_io_w_ready),
+    .io_out_valid            (_delayQueue_io_out_valid),
+    .io_out_bits             (_delayQueue_io_out_bits)
+  );
+  RecentRequestTable rrTable (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_w_ready                     (_rrTable_io_w_ready),
+    .io_w_valid                     (_delayQueue_io_out_valid),
+    .io_w_bits                      (_delayQueue_io_out_bits),
+    .io_r_req_valid                 (_scoreTable_io_test_req_valid),
+    .io_r_req_bits_addr             (_scoreTable_io_test_req_bits_addr),
+    .io_r_req_bits_testOffset       (_scoreTable_io_test_req_bits_testOffset),
+    .io_r_req_bits_ptr              (_scoreTable_io_test_req_bits_ptr),
+    .io_r_resp_valid                (_rrTable_io_r_resp_valid),
+    .io_r_resp_bits_ptr             (_rrTable_io_r_resp_bits_ptr),
+    .io_r_resp_bits_hit             (_rrTable_io_r_resp_bits_hit),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_array),
+    .sigFromSrams_bore_ram_hold     (sigFromSrams_bore_ram_hold),
+    .sigFromSrams_bore_ram_bypass   (sigFromSrams_bore_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken (sigFromSrams_bore_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk  (sigFromSrams_bore_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp (sigFromSrams_bore_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold (sigFromSrams_bore_ram_mcp_hold),
+    .sigFromSrams_bore_cgen         (sigFromSrams_bore_cgen)
+  );
+  OffsetScoreTable scoreTable (
+    .clock                       (clock),
+    .reset                       (reset),
+    .io_req_ready                (_scoreTable_io_req_ready),
+    .io_req_valid                (io_train_valid),
+    .io_req_bits                 ({io_train_bits_tag, io_train_bits_set, 6'h0}),
+    .io_prefetchOffset           (_scoreTable_io_prefetchOffset),
+    .io_prefetchDisable          (_scoreTable_io_prefetchDisable),
+    .io_test_req_valid           (_scoreTable_io_test_req_valid),
+    .io_test_req_bits_addr       (_scoreTable_io_test_req_bits_addr),
+    .io_test_req_bits_testOffset (_scoreTable_io_test_req_bits_testOffset),
+    .io_test_req_bits_ptr        (_scoreTable_io_test_req_bits_ptr),
+    .io_test_resp_valid          (_rrTable_io_r_resp_valid),
+    .io_test_resp_bits_ptr       (_rrTable_io_r_resp_bits_ptr),
+    .io_test_resp_bits_hit       (_rrTable_io_r_resp_bits_hit)
+  );
+  assign io_train_ready = _scoreTable_io_req_ready & (~req_valid | io_req_ready);
+  assign io_req_valid = io_req_valid_0;
+  assign io_req_bits_tag = req_tag;
+  assign io_req_bits_set = req_set;
+  assign io_req_bits_vaddr = 44'h0;
+  assign io_req_bits_needT = req_needT;
+  assign io_req_bits_source = req_source;
+  assign io_resp_ready = _rrTable_io_w_ready;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_10.sv b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_10.sv
new file mode 100644
index 0000000000..c492163253
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_10.sv
@@ -0,0 +1,71 @@
+// Generated by CIRCT firtool-1.135.0
+module Pipeline_10(
+  input         clock,
+  input         reset,
+  output        io_in_ready,
+  input         io_in_valid,
+  input  [3:0]  io_in_bits_qos,
+  input  [10:0] io_in_bits_tgtID,
+  input  [10:0] io_in_bits_srcID,
+  input  [11:0] io_in_bits_txnID,
+  input  [4:0]  io_in_bits_opcode,
+  input  [1:0]  io_in_bits_respErr,
+  input  [2:0]  io_in_bits_resp,
+  input  [2:0]  io_in_bits_fwdState,
+  input  [2:0]  io_in_bits_cBusy,
+  input  [11:0] io_in_bits_dbID,
+  input  [3:0]  io_in_bits_pCrdType,
+  input  [1:0]  io_in_bits_tagOp,
+  input         io_in_bits_traceTag,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_qos,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [4:0]  io_out_bits_opcode,
+  output [1:0]  io_out_bits_respErr,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output [2:0]  io_out_bits_cBusy,
+  output [11:0] io_out_bits_dbID,
+  output [3:0]  io_out_bits_pCrdType,
+  output [1:0]  io_out_bits_tagOp,
+  output        io_out_bits_traceTag
+);
+
+  Queue1_CHIRSP stages_0 (
+    .clock                (clock),
+    .reset                (reset),
+    .io_enq_ready         (io_in_ready),
+    .io_enq_valid         (io_in_valid),
+    .io_enq_bits_qos      (io_in_bits_qos),
+    .io_enq_bits_tgtID    (io_in_bits_tgtID),
+    .io_enq_bits_srcID    (io_in_bits_srcID),
+    .io_enq_bits_txnID    (io_in_bits_txnID),
+    .io_enq_bits_opcode   (io_in_bits_opcode),
+    .io_enq_bits_respErr  (io_in_bits_respErr),
+    .io_enq_bits_resp     (io_in_bits_resp),
+    .io_enq_bits_fwdState (io_in_bits_fwdState),
+    .io_enq_bits_cBusy    (io_in_bits_cBusy),
+    .io_enq_bits_dbID     (io_in_bits_dbID),
+    .io_enq_bits_pCrdType (io_in_bits_pCrdType),
+    .io_enq_bits_tagOp    (io_in_bits_tagOp),
+    .io_enq_bits_traceTag (io_in_bits_traceTag),
+    .io_deq_ready         (io_out_ready),
+    .io_deq_valid         (io_out_valid),
+    .io_deq_bits_qos      (io_out_bits_qos),
+    .io_deq_bits_tgtID    (io_out_bits_tgtID),
+    .io_deq_bits_srcID    (io_out_bits_srcID),
+    .io_deq_bits_txnID    (io_out_bits_txnID),
+    .io_deq_bits_opcode   (io_out_bits_opcode),
+    .io_deq_bits_respErr  (io_out_bits_respErr),
+    .io_deq_bits_resp     (io_out_bits_resp),
+    .io_deq_bits_fwdState (io_out_bits_fwdState),
+    .io_deq_bits_cBusy    (io_out_bits_cBusy),
+    .io_deq_bits_dbID     (io_out_bits_dbID),
+    .io_deq_bits_pCrdType (io_out_bits_pCrdType),
+    .io_deq_bits_tagOp    (io_out_bits_tagOp),
+    .io_deq_bits_traceTag (io_out_bits_traceTag)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_5.sv b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_5.sv
new file mode 100644
index 0000000000..6e5a7a85ba
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_5.sv
@@ -0,0 +1,43 @@
+// Generated by CIRCT firtool-1.135.0
+module Pipeline_5(
+  input         clock,
+  input         reset,
+  output        io_in_ready,
+  input         io_in_valid,
+  input  [33:0] io_in_bits_tag,
+  input  [7:0]  io_in_bits_set,
+  input  [43:0] io_in_bits_vaddr,
+  input         io_in_bits_needT,
+  input  [6:0]  io_in_bits_source,
+  input  [4:0]  io_in_bits_pfSource,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [33:0] io_out_bits_tag,
+  output [7:0]  io_out_bits_set,
+  output [43:0] io_out_bits_vaddr,
+  output        io_out_bits_needT,
+  output [6:0]  io_out_bits_source,
+  output [4:0]  io_out_bits_pfSource
+);
+
+  Queue1_PrefetchReq stages_0 (
+    .clock                (clock),
+    .reset                (reset),
+    .io_enq_ready         (io_in_ready),
+    .io_enq_valid         (io_in_valid),
+    .io_enq_bits_tag      (io_in_bits_tag),
+    .io_enq_bits_set      (io_in_bits_set),
+    .io_enq_bits_vaddr    (io_in_bits_vaddr),
+    .io_enq_bits_needT    (io_in_bits_needT),
+    .io_enq_bits_source   (io_in_bits_source),
+    .io_enq_bits_pfSource (io_in_bits_pfSource),
+    .io_deq_ready         (io_out_ready),
+    .io_deq_valid         (io_out_valid),
+    .io_deq_bits_tag      (io_out_bits_tag),
+    .io_deq_bits_set      (io_out_bits_set),
+    .io_deq_bits_vaddr    (io_out_bits_vaddr),
+    .io_deq_bits_needT    (io_out_bits_needT),
+    .io_deq_bits_source   (io_out_bits_source),
+    .io_deq_bits_pfSource (io_out_bits_pfSource)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_6.sv b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_6.sv
new file mode 100644
index 0000000000..50ef44cdbd
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_6.sv
@@ -0,0 +1,33 @@
+// Generated by CIRCT firtool-1.135.0
+module Pipeline_6(
+  input        clock,
+  input        reset,
+  input        io_in_valid,
+  input  [6:0] io_in_bits_source,
+  input        io_in_bits_isGrantData,
+  input        io_in_bits_isKeyword,
+  input        io_in_bits_hasData,
+  input        io_out_ready,
+  output       io_out_valid,
+  output [6:0] io_out_bits_source,
+  output       io_out_bits_isGrantData,
+  output       io_out_bits_isKeyword,
+  output       io_out_bits_hasData
+);
+
+  Queue1_HintQueueEntry stages_0 (
+    .clock                   (clock),
+    .reset                   (reset),
+    .io_enq_valid            (io_in_valid),
+    .io_enq_bits_source      (io_in_bits_source),
+    .io_enq_bits_isGrantData (io_in_bits_isGrantData),
+    .io_enq_bits_isKeyword   (io_in_bits_isKeyword),
+    .io_enq_bits_hasData     (io_in_bits_hasData),
+    .io_deq_ready            (io_out_ready),
+    .io_deq_valid            (io_out_valid),
+    .io_deq_bits_source      (io_out_bits_source),
+    .io_deq_bits_isGrantData (io_out_bits_isGrantData),
+    .io_deq_bits_isKeyword   (io_out_bits_isKeyword),
+    .io_deq_bits_hasData     (io_out_bits_hasData)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_7.sv b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_7.sv
new file mode 100644
index 0000000000..9fd654a027
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_7.sv
@@ -0,0 +1,47 @@
+// Generated by CIRCT firtool-1.135.0
+module Pipeline_7(
+  input         clock,
+  input         reset,
+  input         io_in_valid,
+  input  [33:0] io_in_bits_tag,
+  input  [7:0]  io_in_bits_set,
+  input         io_in_bits_needT,
+  input  [6:0]  io_in_bits_source,
+  input  [43:0] io_in_bits_vaddr,
+  input         io_in_bits_hit,
+  input         io_in_bits_prefetched,
+  input  [3:0]  io_in_bits_pfsource,
+  input  [4:0]  io_in_bits_reqsource,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [33:0] io_out_bits_tag,
+  output [7:0]  io_out_bits_set,
+  output        io_out_bits_needT,
+  output [6:0]  io_out_bits_source,
+  output [43:0] io_out_bits_vaddr,
+  output [4:0]  io_out_bits_reqsource
+);
+
+  Queue1_PrefetchTrain stages_0 (
+    .clock                  (clock),
+    .reset                  (reset),
+    .io_enq_valid           (io_in_valid),
+    .io_enq_bits_tag        (io_in_bits_tag),
+    .io_enq_bits_set        (io_in_bits_set),
+    .io_enq_bits_needT      (io_in_bits_needT),
+    .io_enq_bits_source     (io_in_bits_source),
+    .io_enq_bits_vaddr      (io_in_bits_vaddr),
+    .io_enq_bits_hit        (io_in_bits_hit),
+    .io_enq_bits_prefetched (io_in_bits_prefetched),
+    .io_enq_bits_pfsource   (io_in_bits_pfsource),
+    .io_enq_bits_reqsource  (io_in_bits_reqsource),
+    .io_deq_ready           (io_out_ready),
+    .io_deq_valid           (io_out_valid),
+    .io_deq_bits_tag        (io_out_bits_tag),
+    .io_deq_bits_set        (io_out_bits_set),
+    .io_deq_bits_needT      (io_out_bits_needT),
+    .io_deq_bits_source     (io_out_bits_source),
+    .io_deq_bits_vaddr      (io_out_bits_vaddr),
+    .io_deq_bits_reqsource  (io_out_bits_reqsource)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_8.sv b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_8.sv
new file mode 100644
index 0000000000..6ec480f656
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_8.sv
@@ -0,0 +1,19 @@
+// Generated by CIRCT firtool-1.135.0
+module Pipeline_8(
+  input  clock,
+  input  reset,
+  output io_in_ready,
+  input  io_in_valid,
+  input  io_out_ready,
+  output io_out_valid
+);
+
+  Queue1_PrefetchResp stages_0 (
+    .clock        (clock),
+    .reset        (reset),
+    .io_enq_ready (io_in_ready),
+    .io_enq_valid (io_in_valid),
+    .io_deq_ready (io_out_ready),
+    .io_deq_valid (io_out_valid)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_9.sv b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_9.sv
new file mode 100644
index 0000000000..5c045c736d
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Pipeline_9.sv
@@ -0,0 +1,107 @@
+// Generated by CIRCT firtool-1.135.0
+module Pipeline_9(
+  input          clock,
+  input          reset,
+  output         io_in_ready,
+  input          io_in_valid,
+  input  [3:0]   io_in_bits_qos,
+  input  [10:0]  io_in_bits_tgtID,
+  input  [10:0]  io_in_bits_srcID,
+  input  [11:0]  io_in_bits_txnID,
+  input  [10:0]  io_in_bits_homeNID,
+  input  [3:0]   io_in_bits_opcode,
+  input  [1:0]   io_in_bits_respErr,
+  input  [2:0]   io_in_bits_resp,
+  input  [3:0]   io_in_bits_dataSource,
+  input  [2:0]   io_in_bits_cBusy,
+  input  [11:0]  io_in_bits_dbID,
+  input  [1:0]   io_in_bits_ccID,
+  input  [1:0]   io_in_bits_dataID,
+  input  [1:0]   io_in_bits_tagOp,
+  input  [7:0]   io_in_bits_tag,
+  input  [1:0]   io_in_bits_tu,
+  input          io_in_bits_traceTag,
+  input  [3:0]   io_in_bits_rsvdc,
+  input  [31:0]  io_in_bits_be,
+  input  [255:0] io_in_bits_data,
+  input  [31:0]  io_in_bits_dataCheck,
+  input  [3:0]   io_in_bits_poison,
+  input          io_out_ready,
+  output         io_out_valid,
+  output [3:0]   io_out_bits_qos,
+  output [10:0]  io_out_bits_tgtID,
+  output [10:0]  io_out_bits_srcID,
+  output [11:0]  io_out_bits_txnID,
+  output [10:0]  io_out_bits_homeNID,
+  output [3:0]   io_out_bits_opcode,
+  output [1:0]   io_out_bits_respErr,
+  output [2:0]   io_out_bits_resp,
+  output [3:0]   io_out_bits_dataSource,
+  output [2:0]   io_out_bits_cBusy,
+  output [11:0]  io_out_bits_dbID,
+  output [1:0]   io_out_bits_ccID,
+  output [1:0]   io_out_bits_dataID,
+  output [1:0]   io_out_bits_tagOp,
+  output [7:0]   io_out_bits_tag,
+  output [1:0]   io_out_bits_tu,
+  output         io_out_bits_traceTag,
+  output [3:0]   io_out_bits_rsvdc,
+  output [31:0]  io_out_bits_be,
+  output [255:0] io_out_bits_data,
+  output [31:0]  io_out_bits_dataCheck,
+  output [3:0]   io_out_bits_poison
+);
+
+  Queue1_CHIDAT stages_0 (
+    .clock                  (clock),
+    .reset                  (reset),
+    .io_enq_ready           (io_in_ready),
+    .io_enq_valid           (io_in_valid),
+    .io_enq_bits_qos        (io_in_bits_qos),
+    .io_enq_bits_tgtID      (io_in_bits_tgtID),
+    .io_enq_bits_srcID      (io_in_bits_srcID),
+    .io_enq_bits_txnID      (io_in_bits_txnID),
+    .io_enq_bits_homeNID    (io_in_bits_homeNID),
+    .io_enq_bits_opcode     (io_in_bits_opcode),
+    .io_enq_bits_respErr    (io_in_bits_respErr),
+    .io_enq_bits_resp       (io_in_bits_resp),
+    .io_enq_bits_dataSource (io_in_bits_dataSource),
+    .io_enq_bits_cBusy      (io_in_bits_cBusy),
+    .io_enq_bits_dbID       (io_in_bits_dbID),
+    .io_enq_bits_ccID       (io_in_bits_ccID),
+    .io_enq_bits_dataID     (io_in_bits_dataID),
+    .io_enq_bits_tagOp      (io_in_bits_tagOp),
+    .io_enq_bits_tag        (io_in_bits_tag),
+    .io_enq_bits_tu         (io_in_bits_tu),
+    .io_enq_bits_traceTag   (io_in_bits_traceTag),
+    .io_enq_bits_rsvdc      (io_in_bits_rsvdc),
+    .io_enq_bits_be         (io_in_bits_be),
+    .io_enq_bits_data       (io_in_bits_data),
+    .io_enq_bits_dataCheck  (io_in_bits_dataCheck),
+    .io_enq_bits_poison     (io_in_bits_poison),
+    .io_deq_ready           (io_out_ready),
+    .io_deq_valid           (io_out_valid),
+    .io_deq_bits_qos        (io_out_bits_qos),
+    .io_deq_bits_tgtID      (io_out_bits_tgtID),
+    .io_deq_bits_srcID      (io_out_bits_srcID),
+    .io_deq_bits_txnID      (io_out_bits_txnID),
+    .io_deq_bits_homeNID    (io_out_bits_homeNID),
+    .io_deq_bits_opcode     (io_out_bits_opcode),
+    .io_deq_bits_respErr    (io_out_bits_respErr),
+    .io_deq_bits_resp       (io_out_bits_resp),
+    .io_deq_bits_dataSource (io_out_bits_dataSource),
+    .io_deq_bits_cBusy      (io_out_bits_cBusy),
+    .io_deq_bits_dbID       (io_out_bits_dbID),
+    .io_deq_bits_ccID       (io_out_bits_ccID),
+    .io_deq_bits_dataID     (io_out_bits_dataID),
+    .io_deq_bits_tagOp      (io_out_bits_tagOp),
+    .io_deq_bits_tag        (io_out_bits_tag),
+    .io_deq_bits_tu         (io_out_bits_tu),
+    .io_deq_bits_traceTag   (io_out_bits_traceTag),
+    .io_deq_bits_rsvdc      (io_out_bits_rsvdc),
+    .io_deq_bits_be         (io_out_bits_be),
+    .io_deq_bits_data       (io_out_bits_data),
+    .io_deq_bits_dataCheck  (io_out_bits_dataCheck),
+    .io_deq_bits_poison     (io_out_bits_poison)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/PrefetchReqBuffer.sv b/flow/designs/src/xiangshan_coupledl2/deps/PrefetchReqBuffer.sv
new file mode 100644
index 0000000000..d0cf15013d
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/PrefetchReqBuffer.sv
@@ -0,0 +1,1506 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module PrefetchReqBuffer(
+  input         clock,
+  input         reset,
+  input         io_in_req_valid,
+  input  [49:0] io_in_req_bits_full_vaddr,
+  input  [43:0] io_in_req_bits_base_vaddr,
+  input         io_in_req_bits_needT,
+  input  [6:0]  io_in_req_bits_source,
+  output        io_tlb_req_req_valid,
+  output [49:0] io_tlb_req_req_bits_vaddr,
+  input         io_tlb_req_resp_valid,
+  input  [47:0] io_tlb_req_resp_bits_paddr_0,
+  input  [1:0]  io_tlb_req_resp_bits_pbmt,
+  input         io_tlb_req_resp_bits_miss,
+  input         io_tlb_req_resp_bits_excp_0_gpf_ld,
+  input         io_tlb_req_resp_bits_excp_0_pf_ld,
+  input         io_tlb_req_resp_bits_excp_0_af_ld,
+  input         io_tlb_req_pmp_resp_ld,
+  input         io_tlb_req_pmp_resp_mmio,
+  input         io_out_req_ready,
+  output        io_out_req_valid,
+  output [33:0] io_out_req_bits_tag,
+  output [7:0]  io_out_req_bits_set,
+  output [43:0] io_out_req_bits_vaddr,
+  output        io_out_req_bits_needT,
+  output [6:0]  io_out_req_bits_source
+);
+
+  wire        alloc_15;
+  wire        alloc_14;
+  wire        alloc_13;
+  wire        alloc_12;
+  wire        alloc_11;
+  wire        alloc_10;
+  wire        alloc_9;
+  wire        alloc_8;
+  wire        alloc_7;
+  wire        alloc_6;
+  wire        alloc_5;
+  wire        alloc_4;
+  wire        alloc_3;
+  wire        alloc_2;
+  wire        alloc_1;
+  wire        alloc_0;
+  wire        _pf_req_arb_io_in_0_ready;
+  wire        _pf_req_arb_io_in_1_ready;
+  wire        _pf_req_arb_io_in_2_ready;
+  wire        _pf_req_arb_io_in_3_ready;
+  wire        _pf_req_arb_io_in_4_ready;
+  wire        _pf_req_arb_io_in_5_ready;
+  wire        _pf_req_arb_io_in_6_ready;
+  wire        _pf_req_arb_io_in_7_ready;
+  wire        _pf_req_arb_io_in_8_ready;
+  wire        _pf_req_arb_io_in_9_ready;
+  wire        _pf_req_arb_io_in_10_ready;
+  wire        _pf_req_arb_io_in_11_ready;
+  wire        _pf_req_arb_io_in_12_ready;
+  wire        _pf_req_arb_io_in_13_ready;
+  wire        _pf_req_arb_io_in_14_ready;
+  wire        _pf_req_arb_io_in_15_ready;
+  wire        _tlb_req_arb_io_in_0_ready;
+  wire        _tlb_req_arb_io_in_1_ready;
+  wire        _tlb_req_arb_io_in_2_ready;
+  wire        _tlb_req_arb_io_in_3_ready;
+  wire        _tlb_req_arb_io_in_4_ready;
+  wire        _tlb_req_arb_io_in_5_ready;
+  wire        _tlb_req_arb_io_in_6_ready;
+  wire        _tlb_req_arb_io_in_7_ready;
+  wire        _tlb_req_arb_io_in_8_ready;
+  wire        _tlb_req_arb_io_in_9_ready;
+  wire        _tlb_req_arb_io_in_10_ready;
+  wire        _tlb_req_arb_io_in_11_ready;
+  wire        _tlb_req_arb_io_in_12_ready;
+  wire        _tlb_req_arb_io_in_13_ready;
+  wire        _tlb_req_arb_io_in_14_ready;
+  wire        _tlb_req_arb_io_in_15_ready;
+  wire        _tlb_req_arb_io_out_valid;
+  wire [49:0] _tlb_req_arb_io_out_bits_vaddr;
+  reg         valids_0;
+  reg         valids_1;
+  reg         valids_2;
+  reg         valids_3;
+  reg         valids_4;
+  reg         valids_5;
+  reg         valids_6;
+  reg         valids_7;
+  reg         valids_8;
+  reg         valids_9;
+  reg         valids_10;
+  reg         valids_11;
+  reg         valids_12;
+  reg         valids_13;
+  reg         valids_14;
+  reg         valids_15;
+  reg         entries_0_paddrValid;
+  reg  [43:0] entries_0_vaddrNoOffset;
+  reg  [43:0] entries_0_baseVaddr;
+  reg  [49:0] entries_0_paddrNoOffset;
+  reg         entries_0_replayEn;
+  reg  [3:0]  entries_0_replayCnt;
+  reg         entries_0_needT;
+  reg  [6:0]  entries_0_source;
+  reg         entries_1_paddrValid;
+  reg  [43:0] entries_1_vaddrNoOffset;
+  reg  [43:0] entries_1_baseVaddr;
+  reg  [49:0] entries_1_paddrNoOffset;
+  reg         entries_1_replayEn;
+  reg  [3:0]  entries_1_replayCnt;
+  reg         entries_1_needT;
+  reg  [6:0]  entries_1_source;
+  reg         entries_2_paddrValid;
+  reg  [43:0] entries_2_vaddrNoOffset;
+  reg  [43:0] entries_2_baseVaddr;
+  reg  [49:0] entries_2_paddrNoOffset;
+  reg         entries_2_replayEn;
+  reg  [3:0]  entries_2_replayCnt;
+  reg         entries_2_needT;
+  reg  [6:0]  entries_2_source;
+  reg         entries_3_paddrValid;
+  reg  [43:0] entries_3_vaddrNoOffset;
+  reg  [43:0] entries_3_baseVaddr;
+  reg  [49:0] entries_3_paddrNoOffset;
+  reg         entries_3_replayEn;
+  reg  [3:0]  entries_3_replayCnt;
+  reg         entries_3_needT;
+  reg  [6:0]  entries_3_source;
+  reg         entries_4_paddrValid;
+  reg  [43:0] entries_4_vaddrNoOffset;
+  reg  [43:0] entries_4_baseVaddr;
+  reg  [49:0] entries_4_paddrNoOffset;
+  reg         entries_4_replayEn;
+  reg  [3:0]  entries_4_replayCnt;
+  reg         entries_4_needT;
+  reg  [6:0]  entries_4_source;
+  reg         entries_5_paddrValid;
+  reg  [43:0] entries_5_vaddrNoOffset;
+  reg  [43:0] entries_5_baseVaddr;
+  reg  [49:0] entries_5_paddrNoOffset;
+  reg         entries_5_replayEn;
+  reg  [3:0]  entries_5_replayCnt;
+  reg         entries_5_needT;
+  reg  [6:0]  entries_5_source;
+  reg         entries_6_paddrValid;
+  reg  [43:0] entries_6_vaddrNoOffset;
+  reg  [43:0] entries_6_baseVaddr;
+  reg  [49:0] entries_6_paddrNoOffset;
+  reg         entries_6_replayEn;
+  reg  [3:0]  entries_6_replayCnt;
+  reg         entries_6_needT;
+  reg  [6:0]  entries_6_source;
+  reg         entries_7_paddrValid;
+  reg  [43:0] entries_7_vaddrNoOffset;
+  reg  [43:0] entries_7_baseVaddr;
+  reg  [49:0] entries_7_paddrNoOffset;
+  reg         entries_7_replayEn;
+  reg  [3:0]  entries_7_replayCnt;
+  reg         entries_7_needT;
+  reg  [6:0]  entries_7_source;
+  reg         entries_8_paddrValid;
+  reg  [43:0] entries_8_vaddrNoOffset;
+  reg  [43:0] entries_8_baseVaddr;
+  reg  [49:0] entries_8_paddrNoOffset;
+  reg         entries_8_replayEn;
+  reg  [3:0]  entries_8_replayCnt;
+  reg         entries_8_needT;
+  reg  [6:0]  entries_8_source;
+  reg         entries_9_paddrValid;
+  reg  [43:0] entries_9_vaddrNoOffset;
+  reg  [43:0] entries_9_baseVaddr;
+  reg  [49:0] entries_9_paddrNoOffset;
+  reg         entries_9_replayEn;
+  reg  [3:0]  entries_9_replayCnt;
+  reg         entries_9_needT;
+  reg  [6:0]  entries_9_source;
+  reg         entries_10_paddrValid;
+  reg  [43:0] entries_10_vaddrNoOffset;
+  reg  [43:0] entries_10_baseVaddr;
+  reg  [49:0] entries_10_paddrNoOffset;
+  reg         entries_10_replayEn;
+  reg  [3:0]  entries_10_replayCnt;
+  reg         entries_10_needT;
+  reg  [6:0]  entries_10_source;
+  reg         entries_11_paddrValid;
+  reg  [43:0] entries_11_vaddrNoOffset;
+  reg  [43:0] entries_11_baseVaddr;
+  reg  [49:0] entries_11_paddrNoOffset;
+  reg         entries_11_replayEn;
+  reg  [3:0]  entries_11_replayCnt;
+  reg         entries_11_needT;
+  reg  [6:0]  entries_11_source;
+  reg         entries_12_paddrValid;
+  reg  [43:0] entries_12_vaddrNoOffset;
+  reg  [43:0] entries_12_baseVaddr;
+  reg  [49:0] entries_12_paddrNoOffset;
+  reg         entries_12_replayEn;
+  reg  [3:0]  entries_12_replayCnt;
+  reg         entries_12_needT;
+  reg  [6:0]  entries_12_source;
+  reg         entries_13_paddrValid;
+  reg  [43:0] entries_13_vaddrNoOffset;
+  reg  [43:0] entries_13_baseVaddr;
+  reg  [49:0] entries_13_paddrNoOffset;
+  reg         entries_13_replayEn;
+  reg  [3:0]  entries_13_replayCnt;
+  reg         entries_13_needT;
+  reg  [6:0]  entries_13_source;
+  reg         entries_14_paddrValid;
+  reg  [43:0] entries_14_vaddrNoOffset;
+  reg  [43:0] entries_14_baseVaddr;
+  reg  [49:0] entries_14_paddrNoOffset;
+  reg         entries_14_replayEn;
+  reg  [3:0]  entries_14_replayCnt;
+  reg         entries_14_needT;
+  reg  [6:0]  entries_14_source;
+  reg         entries_15_paddrValid;
+  reg  [43:0] entries_15_vaddrNoOffset;
+  reg  [43:0] entries_15_baseVaddr;
+  reg  [49:0] entries_15_paddrNoOffset;
+  reg         entries_15_replayEn;
+  reg  [3:0]  entries_15_replayCnt;
+  reg         entries_15_needT;
+  reg  [6:0]  entries_15_source;
+  reg         io_tlb_req_req_valid_REG;
+  reg  [49:0] io_tlb_req_req_bits_r_vaddr;
+  reg         prev_in_valid;
+  reg  [49:0] prev_in_req_full_vaddr;
+  wire        s0_invalid_vec_0 = ~valids_0 & ~alloc_0;
+  wire        s0_invalid_vec_1 = ~valids_1 & ~alloc_1;
+  wire        s0_invalid_vec_2 = ~valids_2 & ~alloc_2;
+  wire        s0_invalid_vec_3 = ~valids_3 & ~alloc_3;
+  wire        s0_invalid_vec_4 = ~valids_4 & ~alloc_4;
+  wire        s0_invalid_vec_5 = ~valids_5 & ~alloc_5;
+  wire        s0_invalid_vec_6 = ~valids_6 & ~alloc_6;
+  wire        s0_invalid_vec_7 = ~valids_7 & ~alloc_7;
+  wire        s0_invalid_vec_8 = ~valids_8 & ~alloc_8;
+  wire        s0_invalid_vec_9 = ~valids_9 & ~alloc_9;
+  wire        s0_invalid_vec_10 = ~valids_10 & ~alloc_10;
+  wire        s0_invalid_vec_11 = ~valids_11 & ~alloc_11;
+  wire        s0_invalid_vec_12 = ~valids_12 & ~alloc_12;
+  wire        s0_invalid_vec_13 = ~valids_13 & ~alloc_13;
+  wire        s0_invalid_vec_14 = ~valids_14 & ~alloc_14;
+  wire        s0_invalid_vec_15 = ~valids_15 & ~alloc_15;
+  reg         s1_valid;
+  reg  [49:0] s1_in_req_full_vaddr;
+  reg  [43:0] s1_in_req_base_vaddr;
+  reg         s1_in_req_needT;
+  reg  [6:0]  s1_in_req_source;
+  reg  [15:0] s1_invalid_oh;
+  reg  [15:0] s1_tlb_fire_oh;
+  reg  [15:0] s2_tlb_fire_oh;
+  reg  [15:0] s3_tlb_fire_oh;
+  reg         s3_tlb_resp_valid;
+  reg  [47:0] s3_tlb_resp_paddr_0;
+  reg  [1:0]  s3_tlb_resp_pbmt;
+  reg         s3_tlb_resp_miss;
+  reg         s3_tlb_resp_excp_0_gpf_ld;
+  reg         s3_tlb_resp_excp_0_pf_ld;
+  reg         s3_tlb_resp_excp_0_af_ld;
+  assign alloc_0 = s1_valid & s1_invalid_oh[0];
+  wire        _exp_drop_15_T_4 = s3_tlb_resp_excp_0_pf_ld | s3_tlb_resp_excp_0_gpf_ld;
+  wire        _exp_drop_15_T_8 = s3_tlb_resp_pbmt == 2'h1;
+  wire        _exp_drop_15_T_9 = s3_tlb_resp_pbmt == 2'h2;
+  wire        exp_drop_0 =
+    s3_tlb_fire_oh[0] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss = s3_tlb_fire_oh[0] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_0 =
+    s3_tlb_fire_oh[0] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_0;
+  wire        miss_drop_0 = miss & entries_0_replayEn;
+  wire        miss_first_replay_0 = miss & ~entries_0_replayEn;
+  assign alloc_1 = s1_valid & s1_invalid_oh[1];
+  wire        exp_drop_1 =
+    s3_tlb_fire_oh[1] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_1 = s3_tlb_fire_oh[1] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_1 =
+    s3_tlb_fire_oh[1] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_1;
+  wire        miss_drop_1 = miss_1 & entries_1_replayEn;
+  wire        miss_first_replay_1 = miss_1 & ~entries_1_replayEn;
+  assign alloc_2 = s1_valid & s1_invalid_oh[2];
+  wire        exp_drop_2 =
+    s3_tlb_fire_oh[2] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_2 = s3_tlb_fire_oh[2] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_2 =
+    s3_tlb_fire_oh[2] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_2;
+  wire        miss_drop_2 = miss_2 & entries_2_replayEn;
+  wire        miss_first_replay_2 = miss_2 & ~entries_2_replayEn;
+  assign alloc_3 = s1_valid & s1_invalid_oh[3];
+  wire        exp_drop_3 =
+    s3_tlb_fire_oh[3] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_3 = s3_tlb_fire_oh[3] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_3 =
+    s3_tlb_fire_oh[3] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_3;
+  wire        miss_drop_3 = miss_3 & entries_3_replayEn;
+  wire        miss_first_replay_3 = miss_3 & ~entries_3_replayEn;
+  assign alloc_4 = s1_valid & s1_invalid_oh[4];
+  wire        exp_drop_4 =
+    s3_tlb_fire_oh[4] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_4 = s3_tlb_fire_oh[4] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_4 =
+    s3_tlb_fire_oh[4] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_4;
+  wire        miss_drop_4 = miss_4 & entries_4_replayEn;
+  wire        miss_first_replay_4 = miss_4 & ~entries_4_replayEn;
+  assign alloc_5 = s1_valid & s1_invalid_oh[5];
+  wire        exp_drop_5 =
+    s3_tlb_fire_oh[5] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_5 = s3_tlb_fire_oh[5] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_5 =
+    s3_tlb_fire_oh[5] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_5;
+  wire        miss_drop_5 = miss_5 & entries_5_replayEn;
+  wire        miss_first_replay_5 = miss_5 & ~entries_5_replayEn;
+  assign alloc_6 = s1_valid & s1_invalid_oh[6];
+  wire        exp_drop_6 =
+    s3_tlb_fire_oh[6] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_6 = s3_tlb_fire_oh[6] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_6 =
+    s3_tlb_fire_oh[6] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_6;
+  wire        miss_drop_6 = miss_6 & entries_6_replayEn;
+  wire        miss_first_replay_6 = miss_6 & ~entries_6_replayEn;
+  assign alloc_7 = s1_valid & s1_invalid_oh[7];
+  wire        exp_drop_7 =
+    s3_tlb_fire_oh[7] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_7 = s3_tlb_fire_oh[7] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_7 =
+    s3_tlb_fire_oh[7] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_7;
+  wire        miss_drop_7 = miss_7 & entries_7_replayEn;
+  wire        miss_first_replay_7 = miss_7 & ~entries_7_replayEn;
+  assign alloc_8 = s1_valid & s1_invalid_oh[8];
+  wire        exp_drop_8 =
+    s3_tlb_fire_oh[8] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_8 = s3_tlb_fire_oh[8] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_8 =
+    s3_tlb_fire_oh[8] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_8;
+  wire        miss_drop_8 = miss_8 & entries_8_replayEn;
+  wire        miss_first_replay_8 = miss_8 & ~entries_8_replayEn;
+  assign alloc_9 = s1_valid & s1_invalid_oh[9];
+  wire        exp_drop_9 =
+    s3_tlb_fire_oh[9] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_9 = s3_tlb_fire_oh[9] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_9 =
+    s3_tlb_fire_oh[9] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_9;
+  wire        miss_drop_9 = miss_9 & entries_9_replayEn;
+  wire        miss_first_replay_9 = miss_9 & ~entries_9_replayEn;
+  assign alloc_10 = s1_valid & s1_invalid_oh[10];
+  wire        exp_drop_10 =
+    s3_tlb_fire_oh[10] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_10 = s3_tlb_fire_oh[10] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_10 =
+    s3_tlb_fire_oh[10] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_10;
+  wire        miss_drop_10 = miss_10 & entries_10_replayEn;
+  wire        miss_first_replay_10 = miss_10 & ~entries_10_replayEn;
+  assign alloc_11 = s1_valid & s1_invalid_oh[11];
+  wire        exp_drop_11 =
+    s3_tlb_fire_oh[11] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_11 = s3_tlb_fire_oh[11] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_11 =
+    s3_tlb_fire_oh[11] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_11;
+  wire        miss_drop_11 = miss_11 & entries_11_replayEn;
+  wire        miss_first_replay_11 = miss_11 & ~entries_11_replayEn;
+  assign alloc_12 = s1_valid & s1_invalid_oh[12];
+  wire        exp_drop_12 =
+    s3_tlb_fire_oh[12] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_12 = s3_tlb_fire_oh[12] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_12 =
+    s3_tlb_fire_oh[12] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_12;
+  wire        miss_drop_12 = miss_12 & entries_12_replayEn;
+  wire        miss_first_replay_12 = miss_12 & ~entries_12_replayEn;
+  assign alloc_13 = s1_valid & s1_invalid_oh[13];
+  wire        exp_drop_13 =
+    s3_tlb_fire_oh[13] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_13 = s3_tlb_fire_oh[13] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_13 =
+    s3_tlb_fire_oh[13] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_13;
+  wire        miss_drop_13 = miss_13 & entries_13_replayEn;
+  wire        miss_first_replay_13 = miss_13 & ~entries_13_replayEn;
+  assign alloc_14 = s1_valid & s1_invalid_oh[14];
+  wire        exp_drop_14 =
+    s3_tlb_fire_oh[14] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_14 = s3_tlb_fire_oh[14] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_14 =
+    s3_tlb_fire_oh[14] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_14;
+  wire        miss_drop_14 = miss_14 & entries_14_replayEn;
+  wire        miss_first_replay_14 = miss_14 & ~entries_14_replayEn;
+  assign alloc_15 = s1_valid & s1_invalid_oh[15];
+  wire        exp_drop_15 =
+    s3_tlb_fire_oh[15] & s3_tlb_resp_valid & ~s3_tlb_resp_miss
+    & (_exp_drop_15_T_4 | s3_tlb_resp_excp_0_af_ld | io_tlb_req_pmp_resp_ld
+       | io_tlb_req_pmp_resp_mmio | _exp_drop_15_T_8 | _exp_drop_15_T_9);
+  wire        miss_15 = s3_tlb_fire_oh[15] & s3_tlb_resp_valid & s3_tlb_resp_miss;
+  wire        tlb_fired_15 =
+    s3_tlb_fire_oh[15] & s3_tlb_resp_valid & ~s3_tlb_resp_miss & ~exp_drop_15;
+  wire        miss_drop_15 = miss_15 & entries_15_replayEn;
+  wire        miss_first_replay_15 = miss_15 & ~entries_15_replayEn;
+  wire        tlb_req_arb_io_in_0_valid =
+    valids_0 & ~entries_0_paddrValid & ~(s1_tlb_fire_oh[0]) & ~(s2_tlb_fire_oh[0])
+    & ~(s3_tlb_fire_oh[0]) & ~(|entries_0_replayCnt);
+  wire        pf_req_arb_io_in_0_valid = valids_0 & entries_0_paddrValid;
+  wire        tlb_req_arb_io_in_1_valid =
+    valids_1 & ~entries_1_paddrValid & ~(s1_tlb_fire_oh[1]) & ~(s2_tlb_fire_oh[1])
+    & ~(s3_tlb_fire_oh[1]) & ~(|entries_1_replayCnt);
+  wire        pf_req_arb_io_in_1_valid = valids_1 & entries_1_paddrValid;
+  wire        tlb_req_arb_io_in_2_valid =
+    valids_2 & ~entries_2_paddrValid & ~(s1_tlb_fire_oh[2]) & ~(s2_tlb_fire_oh[2])
+    & ~(s3_tlb_fire_oh[2]) & ~(|entries_2_replayCnt);
+  wire        pf_req_arb_io_in_2_valid = valids_2 & entries_2_paddrValid;
+  wire        tlb_req_arb_io_in_3_valid =
+    valids_3 & ~entries_3_paddrValid & ~(s1_tlb_fire_oh[3]) & ~(s2_tlb_fire_oh[3])
+    & ~(s3_tlb_fire_oh[3]) & ~(|entries_3_replayCnt);
+  wire        pf_req_arb_io_in_3_valid = valids_3 & entries_3_paddrValid;
+  wire        tlb_req_arb_io_in_4_valid =
+    valids_4 & ~entries_4_paddrValid & ~(s1_tlb_fire_oh[4]) & ~(s2_tlb_fire_oh[4])
+    & ~(s3_tlb_fire_oh[4]) & ~(|entries_4_replayCnt);
+  wire        pf_req_arb_io_in_4_valid = valids_4 & entries_4_paddrValid;
+  wire        tlb_req_arb_io_in_5_valid =
+    valids_5 & ~entries_5_paddrValid & ~(s1_tlb_fire_oh[5]) & ~(s2_tlb_fire_oh[5])
+    & ~(s3_tlb_fire_oh[5]) & ~(|entries_5_replayCnt);
+  wire        pf_req_arb_io_in_5_valid = valids_5 & entries_5_paddrValid;
+  wire        tlb_req_arb_io_in_6_valid =
+    valids_6 & ~entries_6_paddrValid & ~(s1_tlb_fire_oh[6]) & ~(s2_tlb_fire_oh[6])
+    & ~(s3_tlb_fire_oh[6]) & ~(|entries_6_replayCnt);
+  wire        pf_req_arb_io_in_6_valid = valids_6 & entries_6_paddrValid;
+  wire        tlb_req_arb_io_in_7_valid =
+    valids_7 & ~entries_7_paddrValid & ~(s1_tlb_fire_oh[7]) & ~(s2_tlb_fire_oh[7])
+    & ~(s3_tlb_fire_oh[7]) & ~(|entries_7_replayCnt);
+  wire        pf_req_arb_io_in_7_valid = valids_7 & entries_7_paddrValid;
+  wire        tlb_req_arb_io_in_8_valid =
+    valids_8 & ~entries_8_paddrValid & ~(s1_tlb_fire_oh[8]) & ~(s2_tlb_fire_oh[8])
+    & ~(s3_tlb_fire_oh[8]) & ~(|entries_8_replayCnt);
+  wire        pf_req_arb_io_in_8_valid = valids_8 & entries_8_paddrValid;
+  wire        tlb_req_arb_io_in_9_valid =
+    valids_9 & ~entries_9_paddrValid & ~(s1_tlb_fire_oh[9]) & ~(s2_tlb_fire_oh[9])
+    & ~(s3_tlb_fire_oh[9]) & ~(|entries_9_replayCnt);
+  wire        pf_req_arb_io_in_9_valid = valids_9 & entries_9_paddrValid;
+  wire        tlb_req_arb_io_in_10_valid =
+    valids_10 & ~entries_10_paddrValid & ~(s1_tlb_fire_oh[10]) & ~(s2_tlb_fire_oh[10])
+    & ~(s3_tlb_fire_oh[10]) & ~(|entries_10_replayCnt);
+  wire        pf_req_arb_io_in_10_valid = valids_10 & entries_10_paddrValid;
+  wire        tlb_req_arb_io_in_11_valid =
+    valids_11 & ~entries_11_paddrValid & ~(s1_tlb_fire_oh[11]) & ~(s2_tlb_fire_oh[11])
+    & ~(s3_tlb_fire_oh[11]) & ~(|entries_11_replayCnt);
+  wire        pf_req_arb_io_in_11_valid = valids_11 & entries_11_paddrValid;
+  wire        tlb_req_arb_io_in_12_valid =
+    valids_12 & ~entries_12_paddrValid & ~(s1_tlb_fire_oh[12]) & ~(s2_tlb_fire_oh[12])
+    & ~(s3_tlb_fire_oh[12]) & ~(|entries_12_replayCnt);
+  wire        pf_req_arb_io_in_12_valid = valids_12 & entries_12_paddrValid;
+  wire        tlb_req_arb_io_in_13_valid =
+    valids_13 & ~entries_13_paddrValid & ~(s1_tlb_fire_oh[13]) & ~(s2_tlb_fire_oh[13])
+    & ~(s3_tlb_fire_oh[13]) & ~(|entries_13_replayCnt);
+  wire        pf_req_arb_io_in_13_valid = valids_13 & entries_13_paddrValid;
+  wire        tlb_req_arb_io_in_14_valid =
+    valids_14 & ~entries_14_paddrValid & ~(s1_tlb_fire_oh[14]) & ~(s2_tlb_fire_oh[14])
+    & ~(s3_tlb_fire_oh[14]) & ~(|entries_14_replayCnt);
+  wire        pf_req_arb_io_in_14_valid = valids_14 & entries_14_paddrValid;
+  wire        tlb_req_arb_io_in_15_valid =
+    valids_15 & ~entries_15_paddrValid & ~(s1_tlb_fire_oh[15]) & ~(s2_tlb_fire_oh[15])
+    & ~(s3_tlb_fire_oh[15]) & ~(|entries_15_replayCnt);
+  wire        pf_req_arb_io_in_15_valid = valids_15 & entries_15_paddrValid;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      valids_0 <= 1'h0;
+      valids_1 <= 1'h0;
+      valids_2 <= 1'h0;
+      valids_3 <= 1'h0;
+      valids_4 <= 1'h0;
+      valids_5 <= 1'h0;
+      valids_6 <= 1'h0;
+      valids_7 <= 1'h0;
+      valids_8 <= 1'h0;
+      valids_9 <= 1'h0;
+      valids_10 <= 1'h0;
+      valids_11 <= 1'h0;
+      valids_12 <= 1'h0;
+      valids_13 <= 1'h0;
+      valids_14 <= 1'h0;
+      valids_15 <= 1'h0;
+      prev_in_valid <= 1'h0;
+      s1_valid <= 1'h0;
+      s1_tlb_fire_oh <= 16'h0;
+      s2_tlb_fire_oh <= 16'h0;
+      s3_tlb_fire_oh <= 16'h0;
+    end
+    else begin
+      valids_0 <=
+        alloc_0 | ~(_pf_req_arb_io_in_0_ready & pf_req_arb_io_in_0_valid)
+        & (tlb_fired_0 | ~miss_drop_0 & (miss_first_replay_0 | ~exp_drop_0)) & valids_0;
+      valids_1 <=
+        alloc_1 | ~(_pf_req_arb_io_in_1_ready & pf_req_arb_io_in_1_valid)
+        & (tlb_fired_1 | ~miss_drop_1 & (miss_first_replay_1 | ~exp_drop_1)) & valids_1;
+      valids_2 <=
+        alloc_2 | ~(_pf_req_arb_io_in_2_ready & pf_req_arb_io_in_2_valid)
+        & (tlb_fired_2 | ~miss_drop_2 & (miss_first_replay_2 | ~exp_drop_2)) & valids_2;
+      valids_3 <=
+        alloc_3 | ~(_pf_req_arb_io_in_3_ready & pf_req_arb_io_in_3_valid)
+        & (tlb_fired_3 | ~miss_drop_3 & (miss_first_replay_3 | ~exp_drop_3)) & valids_3;
+      valids_4 <=
+        alloc_4 | ~(_pf_req_arb_io_in_4_ready & pf_req_arb_io_in_4_valid)
+        & (tlb_fired_4 | ~miss_drop_4 & (miss_first_replay_4 | ~exp_drop_4)) & valids_4;
+      valids_5 <=
+        alloc_5 | ~(_pf_req_arb_io_in_5_ready & pf_req_arb_io_in_5_valid)
+        & (tlb_fired_5 | ~miss_drop_5 & (miss_first_replay_5 | ~exp_drop_5)) & valids_5;
+      valids_6 <=
+        alloc_6 | ~(_pf_req_arb_io_in_6_ready & pf_req_arb_io_in_6_valid)
+        & (tlb_fired_6 | ~miss_drop_6 & (miss_first_replay_6 | ~exp_drop_6)) & valids_6;
+      valids_7 <=
+        alloc_7 | ~(_pf_req_arb_io_in_7_ready & pf_req_arb_io_in_7_valid)
+        & (tlb_fired_7 | ~miss_drop_7 & (miss_first_replay_7 | ~exp_drop_7)) & valids_7;
+      valids_8 <=
+        alloc_8 | ~(_pf_req_arb_io_in_8_ready & pf_req_arb_io_in_8_valid)
+        & (tlb_fired_8 | ~miss_drop_8 & (miss_first_replay_8 | ~exp_drop_8)) & valids_8;
+      valids_9 <=
+        alloc_9 | ~(_pf_req_arb_io_in_9_ready & pf_req_arb_io_in_9_valid)
+        & (tlb_fired_9 | ~miss_drop_9 & (miss_first_replay_9 | ~exp_drop_9)) & valids_9;
+      valids_10 <=
+        alloc_10 | ~(_pf_req_arb_io_in_10_ready & pf_req_arb_io_in_10_valid)
+        & (tlb_fired_10 | ~miss_drop_10 & (miss_first_replay_10 | ~exp_drop_10))
+        & valids_10;
+      valids_11 <=
+        alloc_11 | ~(_pf_req_arb_io_in_11_ready & pf_req_arb_io_in_11_valid)
+        & (tlb_fired_11 | ~miss_drop_11 & (miss_first_replay_11 | ~exp_drop_11))
+        & valids_11;
+      valids_12 <=
+        alloc_12 | ~(_pf_req_arb_io_in_12_ready & pf_req_arb_io_in_12_valid)
+        & (tlb_fired_12 | ~miss_drop_12 & (miss_first_replay_12 | ~exp_drop_12))
+        & valids_12;
+      valids_13 <=
+        alloc_13 | ~(_pf_req_arb_io_in_13_ready & pf_req_arb_io_in_13_valid)
+        & (tlb_fired_13 | ~miss_drop_13 & (miss_first_replay_13 | ~exp_drop_13))
+        & valids_13;
+      valids_14 <=
+        alloc_14 | ~(_pf_req_arb_io_in_14_ready & pf_req_arb_io_in_14_valid)
+        & (tlb_fired_14 | ~miss_drop_14 & (miss_first_replay_14 | ~exp_drop_14))
+        & valids_14;
+      valids_15 <=
+        alloc_15 | ~(_pf_req_arb_io_in_15_ready & pf_req_arb_io_in_15_valid)
+        & (tlb_fired_15 | ~miss_drop_15 & (miss_first_replay_15 | ~exp_drop_15))
+        & valids_15;
+      prev_in_valid <= io_in_req_valid;
+      s1_valid <=
+        io_in_req_valid
+        & ~(prev_in_valid
+            & io_in_req_bits_full_vaddr[49:6] == prev_in_req_full_vaddr[49:6])
+        & {valids_15 & entries_15_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_15_needT == io_in_req_bits_needT
+             & entries_15_source == io_in_req_bits_source
+             & entries_15_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_14 & entries_14_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_14_needT == io_in_req_bits_needT
+             & entries_14_source == io_in_req_bits_source
+             & entries_14_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_13 & entries_13_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_13_needT == io_in_req_bits_needT
+             & entries_13_source == io_in_req_bits_source
+             & entries_13_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_12 & entries_12_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_12_needT == io_in_req_bits_needT
+             & entries_12_source == io_in_req_bits_source
+             & entries_12_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_11 & entries_11_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_11_needT == io_in_req_bits_needT
+             & entries_11_source == io_in_req_bits_source
+             & entries_11_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_10 & entries_10_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_10_needT == io_in_req_bits_needT
+             & entries_10_source == io_in_req_bits_source
+             & entries_10_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_9 & entries_9_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_9_needT == io_in_req_bits_needT
+             & entries_9_source == io_in_req_bits_source
+             & entries_9_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_8 & entries_8_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_8_needT == io_in_req_bits_needT
+             & entries_8_source == io_in_req_bits_source
+             & entries_8_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_7 & entries_7_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_7_needT == io_in_req_bits_needT
+             & entries_7_source == io_in_req_bits_source
+             & entries_7_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_6 & entries_6_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_6_needT == io_in_req_bits_needT
+             & entries_6_source == io_in_req_bits_source
+             & entries_6_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_5 & entries_5_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_5_needT == io_in_req_bits_needT
+             & entries_5_source == io_in_req_bits_source
+             & entries_5_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_4 & entries_4_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_4_needT == io_in_req_bits_needT
+             & entries_4_source == io_in_req_bits_source
+             & entries_4_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_3 & entries_3_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_3_needT == io_in_req_bits_needT
+             & entries_3_source == io_in_req_bits_source
+             & entries_3_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_2 & entries_2_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_2_needT == io_in_req_bits_needT
+             & entries_2_source == io_in_req_bits_source
+             & entries_2_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_1 & entries_1_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_1_needT == io_in_req_bits_needT
+             & entries_1_source == io_in_req_bits_source
+             & entries_1_baseVaddr == io_in_req_bits_base_vaddr,
+           valids_0 & entries_0_vaddrNoOffset == io_in_req_bits_full_vaddr[49:6]
+             & entries_0_needT == io_in_req_bits_needT
+             & entries_0_source == io_in_req_bits_source
+             & entries_0_baseVaddr == io_in_req_bits_base_vaddr} == 16'h0
+        & (|{s0_invalid_vec_15,
+             s0_invalid_vec_14,
+             s0_invalid_vec_13,
+             s0_invalid_vec_12,
+             s0_invalid_vec_11,
+             s0_invalid_vec_10,
+             s0_invalid_vec_9,
+             s0_invalid_vec_8,
+             s0_invalid_vec_7,
+             s0_invalid_vec_6,
+             s0_invalid_vec_5,
+             s0_invalid_vec_4,
+             s0_invalid_vec_3,
+             s0_invalid_vec_2,
+             s0_invalid_vec_1,
+             s0_invalid_vec_0});
+      s1_tlb_fire_oh <=
+        {_tlb_req_arb_io_in_15_ready & tlb_req_arb_io_in_15_valid,
+         _tlb_req_arb_io_in_14_ready & tlb_req_arb_io_in_14_valid,
+         _tlb_req_arb_io_in_13_ready & tlb_req_arb_io_in_13_valid,
+         _tlb_req_arb_io_in_12_ready & tlb_req_arb_io_in_12_valid,
+         _tlb_req_arb_io_in_11_ready & tlb_req_arb_io_in_11_valid,
+         _tlb_req_arb_io_in_10_ready & tlb_req_arb_io_in_10_valid,
+         _tlb_req_arb_io_in_9_ready & tlb_req_arb_io_in_9_valid,
+         _tlb_req_arb_io_in_8_ready & tlb_req_arb_io_in_8_valid,
+         _tlb_req_arb_io_in_7_ready & tlb_req_arb_io_in_7_valid,
+         _tlb_req_arb_io_in_6_ready & tlb_req_arb_io_in_6_valid,
+         _tlb_req_arb_io_in_5_ready & tlb_req_arb_io_in_5_valid,
+         _tlb_req_arb_io_in_4_ready & tlb_req_arb_io_in_4_valid,
+         _tlb_req_arb_io_in_3_ready & tlb_req_arb_io_in_3_valid,
+         _tlb_req_arb_io_in_2_ready & tlb_req_arb_io_in_2_valid,
+         _tlb_req_arb_io_in_1_ready & tlb_req_arb_io_in_1_valid,
+         _tlb_req_arb_io_in_0_ready & tlb_req_arb_io_in_0_valid};
+      s2_tlb_fire_oh <= s1_tlb_fire_oh;
+      s3_tlb_fire_oh <= s2_tlb_fire_oh;
+    end
+  end // always @(posedge, posedge)
+  wire        _GEN = alloc_0 | tlb_fired_0;
+  wire        _GEN_0 = alloc_1 | tlb_fired_1;
+  wire        _GEN_1 = alloc_2 | tlb_fired_2;
+  wire        _GEN_2 = alloc_3 | tlb_fired_3;
+  wire        _GEN_3 = alloc_4 | tlb_fired_4;
+  wire        _GEN_4 = alloc_5 | tlb_fired_5;
+  wire        _GEN_5 = alloc_6 | tlb_fired_6;
+  wire        _GEN_6 = alloc_7 | tlb_fired_7;
+  wire        _GEN_7 = alloc_8 | tlb_fired_8;
+  wire        _GEN_8 = alloc_9 | tlb_fired_9;
+  wire        _GEN_9 = alloc_10 | tlb_fired_10;
+  wire        _GEN_10 = alloc_11 | tlb_fired_11;
+  wire        _GEN_11 = alloc_12 | tlb_fired_12;
+  wire        _GEN_12 = alloc_13 | tlb_fired_13;
+  wire        _GEN_13 = alloc_14 | tlb_fired_14;
+  wire        _GEN_14 = alloc_15 | tlb_fired_15;
+  always @(posedge clock) begin
+    entries_0_paddrValid <= ~alloc_0 & (tlb_fired_0 | entries_0_paddrValid);
+    if (alloc_0) begin
+      entries_0_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_0_baseVaddr <= s1_in_req_base_vaddr;
+      entries_0_paddrNoOffset <= 50'h0;
+      entries_0_needT <= s1_in_req_needT;
+      entries_0_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_0)
+      entries_0_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_0_replayEn <=
+      ~_GEN & (~miss_drop_0 & miss_first_replay_0 | entries_0_replayEn);
+    if (_GEN)
+      entries_0_replayCnt <= 4'h0;
+    else if (miss_drop_0 | ~miss_first_replay_0) begin
+      if (valids_0 & (|entries_0_replayCnt))
+        entries_0_replayCnt <= 4'(entries_0_replayCnt - 4'h1);
+    end
+    else
+      entries_0_replayCnt <= 4'hA;
+    entries_1_paddrValid <= ~alloc_1 & (tlb_fired_1 | entries_1_paddrValid);
+    if (alloc_1) begin
+      entries_1_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_1_baseVaddr <= s1_in_req_base_vaddr;
+      entries_1_paddrNoOffset <= 50'h0;
+      entries_1_needT <= s1_in_req_needT;
+      entries_1_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_1)
+      entries_1_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_1_replayEn <=
+      ~_GEN_0 & (~miss_drop_1 & miss_first_replay_1 | entries_1_replayEn);
+    if (_GEN_0)
+      entries_1_replayCnt <= 4'h0;
+    else if (miss_drop_1 | ~miss_first_replay_1) begin
+      if (valids_1 & (|entries_1_replayCnt))
+        entries_1_replayCnt <= 4'(entries_1_replayCnt - 4'h1);
+    end
+    else
+      entries_1_replayCnt <= 4'hA;
+    entries_2_paddrValid <= ~alloc_2 & (tlb_fired_2 | entries_2_paddrValid);
+    if (alloc_2) begin
+      entries_2_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_2_baseVaddr <= s1_in_req_base_vaddr;
+      entries_2_paddrNoOffset <= 50'h0;
+      entries_2_needT <= s1_in_req_needT;
+      entries_2_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_2)
+      entries_2_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_2_replayEn <=
+      ~_GEN_1 & (~miss_drop_2 & miss_first_replay_2 | entries_2_replayEn);
+    if (_GEN_1)
+      entries_2_replayCnt <= 4'h0;
+    else if (miss_drop_2 | ~miss_first_replay_2) begin
+      if (valids_2 & (|entries_2_replayCnt))
+        entries_2_replayCnt <= 4'(entries_2_replayCnt - 4'h1);
+    end
+    else
+      entries_2_replayCnt <= 4'hA;
+    entries_3_paddrValid <= ~alloc_3 & (tlb_fired_3 | entries_3_paddrValid);
+    if (alloc_3) begin
+      entries_3_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_3_baseVaddr <= s1_in_req_base_vaddr;
+      entries_3_paddrNoOffset <= 50'h0;
+      entries_3_needT <= s1_in_req_needT;
+      entries_3_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_3)
+      entries_3_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_3_replayEn <=
+      ~_GEN_2 & (~miss_drop_3 & miss_first_replay_3 | entries_3_replayEn);
+    if (_GEN_2)
+      entries_3_replayCnt <= 4'h0;
+    else if (miss_drop_3 | ~miss_first_replay_3) begin
+      if (valids_3 & (|entries_3_replayCnt))
+        entries_3_replayCnt <= 4'(entries_3_replayCnt - 4'h1);
+    end
+    else
+      entries_3_replayCnt <= 4'hA;
+    entries_4_paddrValid <= ~alloc_4 & (tlb_fired_4 | entries_4_paddrValid);
+    if (alloc_4) begin
+      entries_4_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_4_baseVaddr <= s1_in_req_base_vaddr;
+      entries_4_paddrNoOffset <= 50'h0;
+      entries_4_needT <= s1_in_req_needT;
+      entries_4_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_4)
+      entries_4_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_4_replayEn <=
+      ~_GEN_3 & (~miss_drop_4 & miss_first_replay_4 | entries_4_replayEn);
+    if (_GEN_3)
+      entries_4_replayCnt <= 4'h0;
+    else if (miss_drop_4 | ~miss_first_replay_4) begin
+      if (valids_4 & (|entries_4_replayCnt))
+        entries_4_replayCnt <= 4'(entries_4_replayCnt - 4'h1);
+    end
+    else
+      entries_4_replayCnt <= 4'hA;
+    entries_5_paddrValid <= ~alloc_5 & (tlb_fired_5 | entries_5_paddrValid);
+    if (alloc_5) begin
+      entries_5_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_5_baseVaddr <= s1_in_req_base_vaddr;
+      entries_5_paddrNoOffset <= 50'h0;
+      entries_5_needT <= s1_in_req_needT;
+      entries_5_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_5)
+      entries_5_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_5_replayEn <=
+      ~_GEN_4 & (~miss_drop_5 & miss_first_replay_5 | entries_5_replayEn);
+    if (_GEN_4)
+      entries_5_replayCnt <= 4'h0;
+    else if (miss_drop_5 | ~miss_first_replay_5) begin
+      if (valids_5 & (|entries_5_replayCnt))
+        entries_5_replayCnt <= 4'(entries_5_replayCnt - 4'h1);
+    end
+    else
+      entries_5_replayCnt <= 4'hA;
+    entries_6_paddrValid <= ~alloc_6 & (tlb_fired_6 | entries_6_paddrValid);
+    if (alloc_6) begin
+      entries_6_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_6_baseVaddr <= s1_in_req_base_vaddr;
+      entries_6_paddrNoOffset <= 50'h0;
+      entries_6_needT <= s1_in_req_needT;
+      entries_6_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_6)
+      entries_6_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_6_replayEn <=
+      ~_GEN_5 & (~miss_drop_6 & miss_first_replay_6 | entries_6_replayEn);
+    if (_GEN_5)
+      entries_6_replayCnt <= 4'h0;
+    else if (miss_drop_6 | ~miss_first_replay_6) begin
+      if (valids_6 & (|entries_6_replayCnt))
+        entries_6_replayCnt <= 4'(entries_6_replayCnt - 4'h1);
+    end
+    else
+      entries_6_replayCnt <= 4'hA;
+    entries_7_paddrValid <= ~alloc_7 & (tlb_fired_7 | entries_7_paddrValid);
+    if (alloc_7) begin
+      entries_7_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_7_baseVaddr <= s1_in_req_base_vaddr;
+      entries_7_paddrNoOffset <= 50'h0;
+      entries_7_needT <= s1_in_req_needT;
+      entries_7_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_7)
+      entries_7_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_7_replayEn <=
+      ~_GEN_6 & (~miss_drop_7 & miss_first_replay_7 | entries_7_replayEn);
+    if (_GEN_6)
+      entries_7_replayCnt <= 4'h0;
+    else if (miss_drop_7 | ~miss_first_replay_7) begin
+      if (valids_7 & (|entries_7_replayCnt))
+        entries_7_replayCnt <= 4'(entries_7_replayCnt - 4'h1);
+    end
+    else
+      entries_7_replayCnt <= 4'hA;
+    entries_8_paddrValid <= ~alloc_8 & (tlb_fired_8 | entries_8_paddrValid);
+    if (alloc_8) begin
+      entries_8_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_8_baseVaddr <= s1_in_req_base_vaddr;
+      entries_8_paddrNoOffset <= 50'h0;
+      entries_8_needT <= s1_in_req_needT;
+      entries_8_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_8)
+      entries_8_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_8_replayEn <=
+      ~_GEN_7 & (~miss_drop_8 & miss_first_replay_8 | entries_8_replayEn);
+    if (_GEN_7)
+      entries_8_replayCnt <= 4'h0;
+    else if (miss_drop_8 | ~miss_first_replay_8) begin
+      if (valids_8 & (|entries_8_replayCnt))
+        entries_8_replayCnt <= 4'(entries_8_replayCnt - 4'h1);
+    end
+    else
+      entries_8_replayCnt <= 4'hA;
+    entries_9_paddrValid <= ~alloc_9 & (tlb_fired_9 | entries_9_paddrValid);
+    if (alloc_9) begin
+      entries_9_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_9_baseVaddr <= s1_in_req_base_vaddr;
+      entries_9_paddrNoOffset <= 50'h0;
+      entries_9_needT <= s1_in_req_needT;
+      entries_9_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_9)
+      entries_9_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_9_replayEn <=
+      ~_GEN_8 & (~miss_drop_9 & miss_first_replay_9 | entries_9_replayEn);
+    if (_GEN_8)
+      entries_9_replayCnt <= 4'h0;
+    else if (miss_drop_9 | ~miss_first_replay_9) begin
+      if (valids_9 & (|entries_9_replayCnt))
+        entries_9_replayCnt <= 4'(entries_9_replayCnt - 4'h1);
+    end
+    else
+      entries_9_replayCnt <= 4'hA;
+    entries_10_paddrValid <= ~alloc_10 & (tlb_fired_10 | entries_10_paddrValid);
+    if (alloc_10) begin
+      entries_10_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_10_baseVaddr <= s1_in_req_base_vaddr;
+      entries_10_paddrNoOffset <= 50'h0;
+      entries_10_needT <= s1_in_req_needT;
+      entries_10_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_10)
+      entries_10_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_10_replayEn <=
+      ~_GEN_9 & (~miss_drop_10 & miss_first_replay_10 | entries_10_replayEn);
+    if (_GEN_9)
+      entries_10_replayCnt <= 4'h0;
+    else if (miss_drop_10 | ~miss_first_replay_10) begin
+      if (valids_10 & (|entries_10_replayCnt))
+        entries_10_replayCnt <= 4'(entries_10_replayCnt - 4'h1);
+    end
+    else
+      entries_10_replayCnt <= 4'hA;
+    entries_11_paddrValid <= ~alloc_11 & (tlb_fired_11 | entries_11_paddrValid);
+    if (alloc_11) begin
+      entries_11_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_11_baseVaddr <= s1_in_req_base_vaddr;
+      entries_11_paddrNoOffset <= 50'h0;
+      entries_11_needT <= s1_in_req_needT;
+      entries_11_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_11)
+      entries_11_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_11_replayEn <=
+      ~_GEN_10 & (~miss_drop_11 & miss_first_replay_11 | entries_11_replayEn);
+    if (_GEN_10)
+      entries_11_replayCnt <= 4'h0;
+    else if (miss_drop_11 | ~miss_first_replay_11) begin
+      if (valids_11 & (|entries_11_replayCnt))
+        entries_11_replayCnt <= 4'(entries_11_replayCnt - 4'h1);
+    end
+    else
+      entries_11_replayCnt <= 4'hA;
+    entries_12_paddrValid <= ~alloc_12 & (tlb_fired_12 | entries_12_paddrValid);
+    if (alloc_12) begin
+      entries_12_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_12_baseVaddr <= s1_in_req_base_vaddr;
+      entries_12_paddrNoOffset <= 50'h0;
+      entries_12_needT <= s1_in_req_needT;
+      entries_12_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_12)
+      entries_12_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_12_replayEn <=
+      ~_GEN_11 & (~miss_drop_12 & miss_first_replay_12 | entries_12_replayEn);
+    if (_GEN_11)
+      entries_12_replayCnt <= 4'h0;
+    else if (miss_drop_12 | ~miss_first_replay_12) begin
+      if (valids_12 & (|entries_12_replayCnt))
+        entries_12_replayCnt <= 4'(entries_12_replayCnt - 4'h1);
+    end
+    else
+      entries_12_replayCnt <= 4'hA;
+    entries_13_paddrValid <= ~alloc_13 & (tlb_fired_13 | entries_13_paddrValid);
+    if (alloc_13) begin
+      entries_13_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_13_baseVaddr <= s1_in_req_base_vaddr;
+      entries_13_paddrNoOffset <= 50'h0;
+      entries_13_needT <= s1_in_req_needT;
+      entries_13_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_13)
+      entries_13_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_13_replayEn <=
+      ~_GEN_12 & (~miss_drop_13 & miss_first_replay_13 | entries_13_replayEn);
+    if (_GEN_12)
+      entries_13_replayCnt <= 4'h0;
+    else if (miss_drop_13 | ~miss_first_replay_13) begin
+      if (valids_13 & (|entries_13_replayCnt))
+        entries_13_replayCnt <= 4'(entries_13_replayCnt - 4'h1);
+    end
+    else
+      entries_13_replayCnt <= 4'hA;
+    entries_14_paddrValid <= ~alloc_14 & (tlb_fired_14 | entries_14_paddrValid);
+    if (alloc_14) begin
+      entries_14_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_14_baseVaddr <= s1_in_req_base_vaddr;
+      entries_14_paddrNoOffset <= 50'h0;
+      entries_14_needT <= s1_in_req_needT;
+      entries_14_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_14)
+      entries_14_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_14_replayEn <=
+      ~_GEN_13 & (~miss_drop_14 & miss_first_replay_14 | entries_14_replayEn);
+    if (_GEN_13)
+      entries_14_replayCnt <= 4'h0;
+    else if (miss_drop_14 | ~miss_first_replay_14) begin
+      if (valids_14 & (|entries_14_replayCnt))
+        entries_14_replayCnt <= 4'(entries_14_replayCnt - 4'h1);
+    end
+    else
+      entries_14_replayCnt <= 4'hA;
+    entries_15_paddrValid <= ~alloc_15 & (tlb_fired_15 | entries_15_paddrValid);
+    if (alloc_15) begin
+      entries_15_vaddrNoOffset <= s1_in_req_full_vaddr[49:6];
+      entries_15_baseVaddr <= s1_in_req_base_vaddr;
+      entries_15_paddrNoOffset <= 50'h0;
+      entries_15_needT <= s1_in_req_needT;
+      entries_15_source <= s1_in_req_source;
+    end
+    else if (tlb_fired_15)
+      entries_15_paddrNoOffset <= {8'h0, s3_tlb_resp_paddr_0[47:6]};
+    entries_15_replayEn <=
+      ~_GEN_14 & (~miss_drop_15 & miss_first_replay_15 | entries_15_replayEn);
+    if (_GEN_14)
+      entries_15_replayCnt <= 4'h0;
+    else if (miss_drop_15 | ~miss_first_replay_15) begin
+      if (valids_15 & (|entries_15_replayCnt))
+        entries_15_replayCnt <= 4'(entries_15_replayCnt - 4'h1);
+    end
+    else
+      entries_15_replayCnt <= 4'hA;
+    io_tlb_req_req_valid_REG <= _tlb_req_arb_io_out_valid;
+    if (_tlb_req_arb_io_out_valid)
+      io_tlb_req_req_bits_r_vaddr <= _tlb_req_arb_io_out_bits_vaddr;
+    prev_in_req_full_vaddr <= io_in_req_bits_full_vaddr;
+    s1_in_req_full_vaddr <= io_in_req_bits_full_vaddr;
+    s1_in_req_base_vaddr <= io_in_req_bits_base_vaddr;
+    s1_in_req_needT <= io_in_req_bits_needT;
+    s1_in_req_source <= io_in_req_bits_source;
+    s1_invalid_oh <=
+      s0_invalid_vec_0
+        ? 16'h1
+        : s0_invalid_vec_1
+            ? 16'h2
+            : s0_invalid_vec_2
+                ? 16'h4
+                : s0_invalid_vec_3
+                    ? 16'h8
+                    : s0_invalid_vec_4
+                        ? 16'h10
+                        : s0_invalid_vec_5
+                            ? 16'h20
+                            : s0_invalid_vec_6
+                                ? 16'h40
+                                : s0_invalid_vec_7
+                                    ? 16'h80
+                                    : s0_invalid_vec_8
+                                        ? 16'h100
+                                        : s0_invalid_vec_9
+                                            ? 16'h200
+                                            : s0_invalid_vec_10
+                                                ? 16'h400
+                                                : s0_invalid_vec_11
+                                                    ? 16'h800
+                                                    : s0_invalid_vec_12
+                                                        ? 16'h1000
+                                                        : s0_invalid_vec_13
+                                                            ? 16'h2000
+                                                            : s0_invalid_vec_14
+                                                                ? 16'h4000
+                                                                : {s0_invalid_vec_15,
+                                                                   15'h0};
+    s3_tlb_resp_valid <= io_tlb_req_resp_valid;
+    if (io_tlb_req_resp_valid) begin
+      s3_tlb_resp_paddr_0 <= io_tlb_req_resp_bits_paddr_0;
+      s3_tlb_resp_pbmt <= io_tlb_req_resp_bits_pbmt;
+      s3_tlb_resp_miss <= io_tlb_req_resp_bits_miss;
+      s3_tlb_resp_excp_0_gpf_ld <= io_tlb_req_resp_bits_excp_0_gpf_ld;
+      s3_tlb_resp_excp_0_pf_ld <= io_tlb_req_resp_bits_excp_0_pf_ld;
+      s3_tlb_resp_excp_0_af_ld <= io_tlb_req_resp_bits_excp_0_af_ld;
+    end
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:153];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [7:0] i = 8'h0; i < 8'h9A; i += 8'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        valids_0 = _RANDOM[8'h0][0];
+        valids_1 = _RANDOM[8'h0][1];
+        valids_2 = _RANDOM[8'h0][2];
+        valids_3 = _RANDOM[8'h0][3];
+        valids_4 = _RANDOM[8'h0][4];
+        valids_5 = _RANDOM[8'h0][5];
+        valids_6 = _RANDOM[8'h0][6];
+        valids_7 = _RANDOM[8'h0][7];
+        valids_8 = _RANDOM[8'h0][8];
+        valids_9 = _RANDOM[8'h0][9];
+        valids_10 = _RANDOM[8'h0][10];
+        valids_11 = _RANDOM[8'h0][11];
+        valids_12 = _RANDOM[8'h0][12];
+        valids_13 = _RANDOM[8'h0][13];
+        valids_14 = _RANDOM[8'h0][14];
+        valids_15 = _RANDOM[8'h0][15];
+        entries_0_paddrValid = _RANDOM[8'h0][16];
+        entries_0_vaddrNoOffset = {_RANDOM[8'h0][31:17], _RANDOM[8'h1][28:0]};
+        entries_0_baseVaddr = {_RANDOM[8'h1][31:29], _RANDOM[8'h2], _RANDOM[8'h3][8:0]};
+        entries_0_paddrNoOffset = {_RANDOM[8'h3][31:9], _RANDOM[8'h4][26:0]};
+        entries_0_replayEn = _RANDOM[8'h4][27];
+        entries_0_replayCnt = _RANDOM[8'h4][31:28];
+        entries_0_needT = _RANDOM[8'h5][0];
+        entries_0_source = _RANDOM[8'h5][7:1];
+        entries_1_paddrValid = _RANDOM[8'h5][8];
+        entries_1_vaddrNoOffset = {_RANDOM[8'h5][31:9], _RANDOM[8'h6][20:0]};
+        entries_1_baseVaddr = {_RANDOM[8'h6][31:21], _RANDOM[8'h7], _RANDOM[8'h8][0]};
+        entries_1_paddrNoOffset = {_RANDOM[8'h8][31:1], _RANDOM[8'h9][18:0]};
+        entries_1_replayEn = _RANDOM[8'h9][19];
+        entries_1_replayCnt = _RANDOM[8'h9][23:20];
+        entries_1_needT = _RANDOM[8'h9][24];
+        entries_1_source = _RANDOM[8'h9][31:25];
+        entries_2_paddrValid = _RANDOM[8'hA][0];
+        entries_2_vaddrNoOffset = {_RANDOM[8'hA][31:1], _RANDOM[8'hB][12:0]};
+        entries_2_baseVaddr = {_RANDOM[8'hB][31:13], _RANDOM[8'hC][24:0]};
+        entries_2_paddrNoOffset =
+          {_RANDOM[8'hC][31:25], _RANDOM[8'hD], _RANDOM[8'hE][10:0]};
+        entries_2_replayEn = _RANDOM[8'hE][11];
+        entries_2_replayCnt = _RANDOM[8'hE][15:12];
+        entries_2_needT = _RANDOM[8'hE][16];
+        entries_2_source = _RANDOM[8'hE][23:17];
+        entries_3_paddrValid = _RANDOM[8'hE][24];
+        entries_3_vaddrNoOffset =
+          {_RANDOM[8'hE][31:25], _RANDOM[8'hF], _RANDOM[8'h10][4:0]};
+        entries_3_baseVaddr = {_RANDOM[8'h10][31:5], _RANDOM[8'h11][16:0]};
+        entries_3_paddrNoOffset =
+          {_RANDOM[8'h11][31:17], _RANDOM[8'h12], _RANDOM[8'h13][2:0]};
+        entries_3_replayEn = _RANDOM[8'h13][3];
+        entries_3_replayCnt = _RANDOM[8'h13][7:4];
+        entries_3_needT = _RANDOM[8'h13][8];
+        entries_3_source = _RANDOM[8'h13][15:9];
+        entries_4_paddrValid = _RANDOM[8'h13][16];
+        entries_4_vaddrNoOffset = {_RANDOM[8'h13][31:17], _RANDOM[8'h14][28:0]};
+        entries_4_baseVaddr =
+          {_RANDOM[8'h14][31:29], _RANDOM[8'h15], _RANDOM[8'h16][8:0]};
+        entries_4_paddrNoOffset = {_RANDOM[8'h16][31:9], _RANDOM[8'h17][26:0]};
+        entries_4_replayEn = _RANDOM[8'h17][27];
+        entries_4_replayCnt = _RANDOM[8'h17][31:28];
+        entries_4_needT = _RANDOM[8'h18][0];
+        entries_4_source = _RANDOM[8'h18][7:1];
+        entries_5_paddrValid = _RANDOM[8'h18][8];
+        entries_5_vaddrNoOffset = {_RANDOM[8'h18][31:9], _RANDOM[8'h19][20:0]};
+        entries_5_baseVaddr = {_RANDOM[8'h19][31:21], _RANDOM[8'h1A], _RANDOM[8'h1B][0]};
+        entries_5_paddrNoOffset = {_RANDOM[8'h1B][31:1], _RANDOM[8'h1C][18:0]};
+        entries_5_replayEn = _RANDOM[8'h1C][19];
+        entries_5_replayCnt = _RANDOM[8'h1C][23:20];
+        entries_5_needT = _RANDOM[8'h1C][24];
+        entries_5_source = _RANDOM[8'h1C][31:25];
+        entries_6_paddrValid = _RANDOM[8'h1D][0];
+        entries_6_vaddrNoOffset = {_RANDOM[8'h1D][31:1], _RANDOM[8'h1E][12:0]};
+        entries_6_baseVaddr = {_RANDOM[8'h1E][31:13], _RANDOM[8'h1F][24:0]};
+        entries_6_paddrNoOffset =
+          {_RANDOM[8'h1F][31:25], _RANDOM[8'h20], _RANDOM[8'h21][10:0]};
+        entries_6_replayEn = _RANDOM[8'h21][11];
+        entries_6_replayCnt = _RANDOM[8'h21][15:12];
+        entries_6_needT = _RANDOM[8'h21][16];
+        entries_6_source = _RANDOM[8'h21][23:17];
+        entries_7_paddrValid = _RANDOM[8'h21][24];
+        entries_7_vaddrNoOffset =
+          {_RANDOM[8'h21][31:25], _RANDOM[8'h22], _RANDOM[8'h23][4:0]};
+        entries_7_baseVaddr = {_RANDOM[8'h23][31:5], _RANDOM[8'h24][16:0]};
+        entries_7_paddrNoOffset =
+          {_RANDOM[8'h24][31:17], _RANDOM[8'h25], _RANDOM[8'h26][2:0]};
+        entries_7_replayEn = _RANDOM[8'h26][3];
+        entries_7_replayCnt = _RANDOM[8'h26][7:4];
+        entries_7_needT = _RANDOM[8'h26][8];
+        entries_7_source = _RANDOM[8'h26][15:9];
+        entries_8_paddrValid = _RANDOM[8'h26][16];
+        entries_8_vaddrNoOffset = {_RANDOM[8'h26][31:17], _RANDOM[8'h27][28:0]};
+        entries_8_baseVaddr =
+          {_RANDOM[8'h27][31:29], _RANDOM[8'h28], _RANDOM[8'h29][8:0]};
+        entries_8_paddrNoOffset = {_RANDOM[8'h29][31:9], _RANDOM[8'h2A][26:0]};
+        entries_8_replayEn = _RANDOM[8'h2A][27];
+        entries_8_replayCnt = _RANDOM[8'h2A][31:28];
+        entries_8_needT = _RANDOM[8'h2B][0];
+        entries_8_source = _RANDOM[8'h2B][7:1];
+        entries_9_paddrValid = _RANDOM[8'h2B][8];
+        entries_9_vaddrNoOffset = {_RANDOM[8'h2B][31:9], _RANDOM[8'h2C][20:0]};
+        entries_9_baseVaddr = {_RANDOM[8'h2C][31:21], _RANDOM[8'h2D], _RANDOM[8'h2E][0]};
+        entries_9_paddrNoOffset = {_RANDOM[8'h2E][31:1], _RANDOM[8'h2F][18:0]};
+        entries_9_replayEn = _RANDOM[8'h2F][19];
+        entries_9_replayCnt = _RANDOM[8'h2F][23:20];
+        entries_9_needT = _RANDOM[8'h2F][24];
+        entries_9_source = _RANDOM[8'h2F][31:25];
+        entries_10_paddrValid = _RANDOM[8'h30][0];
+        entries_10_vaddrNoOffset = {_RANDOM[8'h30][31:1], _RANDOM[8'h31][12:0]};
+        entries_10_baseVaddr = {_RANDOM[8'h31][31:13], _RANDOM[8'h32][24:0]};
+        entries_10_paddrNoOffset =
+          {_RANDOM[8'h32][31:25], _RANDOM[8'h33], _RANDOM[8'h34][10:0]};
+        entries_10_replayEn = _RANDOM[8'h34][11];
+        entries_10_replayCnt = _RANDOM[8'h34][15:12];
+        entries_10_needT = _RANDOM[8'h34][16];
+        entries_10_source = _RANDOM[8'h34][23:17];
+        entries_11_paddrValid = _RANDOM[8'h34][24];
+        entries_11_vaddrNoOffset =
+          {_RANDOM[8'h34][31:25], _RANDOM[8'h35], _RANDOM[8'h36][4:0]};
+        entries_11_baseVaddr = {_RANDOM[8'h36][31:5], _RANDOM[8'h37][16:0]};
+        entries_11_paddrNoOffset =
+          {_RANDOM[8'h37][31:17], _RANDOM[8'h38], _RANDOM[8'h39][2:0]};
+        entries_11_replayEn = _RANDOM[8'h39][3];
+        entries_11_replayCnt = _RANDOM[8'h39][7:4];
+        entries_11_needT = _RANDOM[8'h39][8];
+        entries_11_source = _RANDOM[8'h39][15:9];
+        entries_12_paddrValid = _RANDOM[8'h39][16];
+        entries_12_vaddrNoOffset = {_RANDOM[8'h39][31:17], _RANDOM[8'h3A][28:0]};
+        entries_12_baseVaddr =
+          {_RANDOM[8'h3A][31:29], _RANDOM[8'h3B], _RANDOM[8'h3C][8:0]};
+        entries_12_paddrNoOffset = {_RANDOM[8'h3C][31:9], _RANDOM[8'h3D][26:0]};
+        entries_12_replayEn = _RANDOM[8'h3D][27];
+        entries_12_replayCnt = _RANDOM[8'h3D][31:28];
+        entries_12_needT = _RANDOM[8'h3E][0];
+        entries_12_source = _RANDOM[8'h3E][7:1];
+        entries_13_paddrValid = _RANDOM[8'h3E][8];
+        entries_13_vaddrNoOffset = {_RANDOM[8'h3E][31:9], _RANDOM[8'h3F][20:0]};
+        entries_13_baseVaddr = {_RANDOM[8'h3F][31:21], _RANDOM[8'h40], _RANDOM[8'h41][0]};
+        entries_13_paddrNoOffset = {_RANDOM[8'h41][31:1], _RANDOM[8'h42][18:0]};
+        entries_13_replayEn = _RANDOM[8'h42][19];
+        entries_13_replayCnt = _RANDOM[8'h42][23:20];
+        entries_13_needT = _RANDOM[8'h42][24];
+        entries_13_source = _RANDOM[8'h42][31:25];
+        entries_14_paddrValid = _RANDOM[8'h43][0];
+        entries_14_vaddrNoOffset = {_RANDOM[8'h43][31:1], _RANDOM[8'h44][12:0]};
+        entries_14_baseVaddr = {_RANDOM[8'h44][31:13], _RANDOM[8'h45][24:0]};
+        entries_14_paddrNoOffset =
+          {_RANDOM[8'h45][31:25], _RANDOM[8'h46], _RANDOM[8'h47][10:0]};
+        entries_14_replayEn = _RANDOM[8'h47][11];
+        entries_14_replayCnt = _RANDOM[8'h47][15:12];
+        entries_14_needT = _RANDOM[8'h47][16];
+        entries_14_source = _RANDOM[8'h47][23:17];
+        entries_15_paddrValid = _RANDOM[8'h47][24];
+        entries_15_vaddrNoOffset =
+          {_RANDOM[8'h47][31:25], _RANDOM[8'h48], _RANDOM[8'h49][4:0]};
+        entries_15_baseVaddr = {_RANDOM[8'h49][31:5], _RANDOM[8'h4A][16:0]};
+        entries_15_paddrNoOffset =
+          {_RANDOM[8'h4A][31:17], _RANDOM[8'h4B], _RANDOM[8'h4C][2:0]};
+        entries_15_replayEn = _RANDOM[8'h4C][3];
+        entries_15_replayCnt = _RANDOM[8'h4C][7:4];
+        entries_15_needT = _RANDOM[8'h4C][8];
+        entries_15_source = _RANDOM[8'h4C][15:9];
+        io_tlb_req_req_valid_REG = _RANDOM[8'h8C][16];
+        io_tlb_req_req_bits_r_vaddr =
+          {_RANDOM[8'h8C][31:17], _RANDOM[8'h8D], _RANDOM[8'h8E][2:0]};
+        prev_in_valid = _RANDOM[8'h8E][11];
+        prev_in_req_full_vaddr = {_RANDOM[8'h8E][31:12], _RANDOM[8'h8F][29:0]};
+        s1_valid = _RANDOM[8'h91][19];
+        s1_in_req_full_vaddr =
+          {_RANDOM[8'h91][31:20], _RANDOM[8'h92], _RANDOM[8'h93][5:0]};
+        s1_in_req_base_vaddr = {_RANDOM[8'h93][31:6], _RANDOM[8'h94][17:0]};
+        s1_in_req_needT = _RANDOM[8'h94][18];
+        s1_in_req_source = _RANDOM[8'h94][25:19];
+        s1_invalid_oh = {_RANDOM[8'h94][31:27], _RANDOM[8'h95][10:0]};
+        s1_tlb_fire_oh = {_RANDOM[8'h95][31:27], _RANDOM[8'h96][10:0]};
+        s2_tlb_fire_oh = _RANDOM[8'h96][26:11];
+        s3_tlb_fire_oh = {_RANDOM[8'h96][31:27], _RANDOM[8'h97][10:0]};
+        s3_tlb_resp_valid = _RANDOM[8'h97][11];
+        s3_tlb_resp_paddr_0 = {_RANDOM[8'h97][31:12], _RANDOM[8'h98][27:0]};
+        s3_tlb_resp_pbmt = _RANDOM[8'h98][29:28];
+        s3_tlb_resp_miss = _RANDOM[8'h98][30];
+        s3_tlb_resp_excp_0_gpf_ld = _RANDOM[8'h98][31];
+        s3_tlb_resp_excp_0_pf_ld = _RANDOM[8'h99][2];
+        s3_tlb_resp_excp_0_af_ld = _RANDOM[8'h99][5];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        valids_0 = 1'h0;
+        valids_1 = 1'h0;
+        valids_2 = 1'h0;
+        valids_3 = 1'h0;
+        valids_4 = 1'h0;
+        valids_5 = 1'h0;
+        valids_6 = 1'h0;
+        valids_7 = 1'h0;
+        valids_8 = 1'h0;
+        valids_9 = 1'h0;
+        valids_10 = 1'h0;
+        valids_11 = 1'h0;
+        valids_12 = 1'h0;
+        valids_13 = 1'h0;
+        valids_14 = 1'h0;
+        valids_15 = 1'h0;
+        prev_in_valid = 1'h0;
+        s1_valid = 1'h0;
+        s1_tlb_fire_oh = 16'h0;
+        s2_tlb_fire_oh = 16'h0;
+        s3_tlb_fire_oh = 16'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  TwoLevelRRArbiter_2 tlb_req_arb (
+    .clock               (clock),
+    .reset               (reset),
+    .io_in_0_ready       (_tlb_req_arb_io_in_0_ready),
+    .io_in_0_valid       (tlb_req_arb_io_in_0_valid),
+    .io_in_0_bits_vaddr  ({entries_0_vaddrNoOffset, 6'h0}),
+    .io_in_1_ready       (_tlb_req_arb_io_in_1_ready),
+    .io_in_1_valid       (tlb_req_arb_io_in_1_valid),
+    .io_in_1_bits_vaddr  ({entries_1_vaddrNoOffset, 6'h0}),
+    .io_in_2_ready       (_tlb_req_arb_io_in_2_ready),
+    .io_in_2_valid       (tlb_req_arb_io_in_2_valid),
+    .io_in_2_bits_vaddr  ({entries_2_vaddrNoOffset, 6'h0}),
+    .io_in_3_ready       (_tlb_req_arb_io_in_3_ready),
+    .io_in_3_valid       (tlb_req_arb_io_in_3_valid),
+    .io_in_3_bits_vaddr  ({entries_3_vaddrNoOffset, 6'h0}),
+    .io_in_4_ready       (_tlb_req_arb_io_in_4_ready),
+    .io_in_4_valid       (tlb_req_arb_io_in_4_valid),
+    .io_in_4_bits_vaddr  ({entries_4_vaddrNoOffset, 6'h0}),
+    .io_in_5_ready       (_tlb_req_arb_io_in_5_ready),
+    .io_in_5_valid       (tlb_req_arb_io_in_5_valid),
+    .io_in_5_bits_vaddr  ({entries_5_vaddrNoOffset, 6'h0}),
+    .io_in_6_ready       (_tlb_req_arb_io_in_6_ready),
+    .io_in_6_valid       (tlb_req_arb_io_in_6_valid),
+    .io_in_6_bits_vaddr  ({entries_6_vaddrNoOffset, 6'h0}),
+    .io_in_7_ready       (_tlb_req_arb_io_in_7_ready),
+    .io_in_7_valid       (tlb_req_arb_io_in_7_valid),
+    .io_in_7_bits_vaddr  ({entries_7_vaddrNoOffset, 6'h0}),
+    .io_in_8_ready       (_tlb_req_arb_io_in_8_ready),
+    .io_in_8_valid       (tlb_req_arb_io_in_8_valid),
+    .io_in_8_bits_vaddr  ({entries_8_vaddrNoOffset, 6'h0}),
+    .io_in_9_ready       (_tlb_req_arb_io_in_9_ready),
+    .io_in_9_valid       (tlb_req_arb_io_in_9_valid),
+    .io_in_9_bits_vaddr  ({entries_9_vaddrNoOffset, 6'h0}),
+    .io_in_10_ready      (_tlb_req_arb_io_in_10_ready),
+    .io_in_10_valid      (tlb_req_arb_io_in_10_valid),
+    .io_in_10_bits_vaddr ({entries_10_vaddrNoOffset, 6'h0}),
+    .io_in_11_ready      (_tlb_req_arb_io_in_11_ready),
+    .io_in_11_valid      (tlb_req_arb_io_in_11_valid),
+    .io_in_11_bits_vaddr ({entries_11_vaddrNoOffset, 6'h0}),
+    .io_in_12_ready      (_tlb_req_arb_io_in_12_ready),
+    .io_in_12_valid      (tlb_req_arb_io_in_12_valid),
+    .io_in_12_bits_vaddr ({entries_12_vaddrNoOffset, 6'h0}),
+    .io_in_13_ready      (_tlb_req_arb_io_in_13_ready),
+    .io_in_13_valid      (tlb_req_arb_io_in_13_valid),
+    .io_in_13_bits_vaddr ({entries_13_vaddrNoOffset, 6'h0}),
+    .io_in_14_ready      (_tlb_req_arb_io_in_14_ready),
+    .io_in_14_valid      (tlb_req_arb_io_in_14_valid),
+    .io_in_14_bits_vaddr ({entries_14_vaddrNoOffset, 6'h0}),
+    .io_in_15_ready      (_tlb_req_arb_io_in_15_ready),
+    .io_in_15_valid      (tlb_req_arb_io_in_15_valid),
+    .io_in_15_bits_vaddr ({entries_15_vaddrNoOffset, 6'h0}),
+    .io_out_valid        (_tlb_req_arb_io_out_valid),
+    .io_out_bits_vaddr   (_tlb_req_arb_io_out_bits_vaddr)
+  );
+  TwoLevelRRArbiter_3 pf_req_arb (
+    .clock                (clock),
+    .reset                (reset),
+    .io_in_0_ready        (_pf_req_arb_io_in_0_ready),
+    .io_in_0_valid        (pf_req_arb_io_in_0_valid),
+    .io_in_0_bits_tag     (entries_0_paddrNoOffset[41:8]),
+    .io_in_0_bits_set     (entries_0_paddrNoOffset[7:0]),
+    .io_in_0_bits_vaddr   (entries_0_baseVaddr),
+    .io_in_0_bits_needT   (entries_0_needT),
+    .io_in_0_bits_source  (entries_0_source),
+    .io_in_1_ready        (_pf_req_arb_io_in_1_ready),
+    .io_in_1_valid        (pf_req_arb_io_in_1_valid),
+    .io_in_1_bits_tag     (entries_1_paddrNoOffset[41:8]),
+    .io_in_1_bits_set     (entries_1_paddrNoOffset[7:0]),
+    .io_in_1_bits_vaddr   (entries_1_baseVaddr),
+    .io_in_1_bits_needT   (entries_1_needT),
+    .io_in_1_bits_source  (entries_1_source),
+    .io_in_2_ready        (_pf_req_arb_io_in_2_ready),
+    .io_in_2_valid        (pf_req_arb_io_in_2_valid),
+    .io_in_2_bits_tag     (entries_2_paddrNoOffset[41:8]),
+    .io_in_2_bits_set     (entries_2_paddrNoOffset[7:0]),
+    .io_in_2_bits_vaddr   (entries_2_baseVaddr),
+    .io_in_2_bits_needT   (entries_2_needT),
+    .io_in_2_bits_source  (entries_2_source),
+    .io_in_3_ready        (_pf_req_arb_io_in_3_ready),
+    .io_in_3_valid        (pf_req_arb_io_in_3_valid),
+    .io_in_3_bits_tag     (entries_3_paddrNoOffset[41:8]),
+    .io_in_3_bits_set     (entries_3_paddrNoOffset[7:0]),
+    .io_in_3_bits_vaddr   (entries_3_baseVaddr),
+    .io_in_3_bits_needT   (entries_3_needT),
+    .io_in_3_bits_source  (entries_3_source),
+    .io_in_4_ready        (_pf_req_arb_io_in_4_ready),
+    .io_in_4_valid        (pf_req_arb_io_in_4_valid),
+    .io_in_4_bits_tag     (entries_4_paddrNoOffset[41:8]),
+    .io_in_4_bits_set     (entries_4_paddrNoOffset[7:0]),
+    .io_in_4_bits_vaddr   (entries_4_baseVaddr),
+    .io_in_4_bits_needT   (entries_4_needT),
+    .io_in_4_bits_source  (entries_4_source),
+    .io_in_5_ready        (_pf_req_arb_io_in_5_ready),
+    .io_in_5_valid        (pf_req_arb_io_in_5_valid),
+    .io_in_5_bits_tag     (entries_5_paddrNoOffset[41:8]),
+    .io_in_5_bits_set     (entries_5_paddrNoOffset[7:0]),
+    .io_in_5_bits_vaddr   (entries_5_baseVaddr),
+    .io_in_5_bits_needT   (entries_5_needT),
+    .io_in_5_bits_source  (entries_5_source),
+    .io_in_6_ready        (_pf_req_arb_io_in_6_ready),
+    .io_in_6_valid        (pf_req_arb_io_in_6_valid),
+    .io_in_6_bits_tag     (entries_6_paddrNoOffset[41:8]),
+    .io_in_6_bits_set     (entries_6_paddrNoOffset[7:0]),
+    .io_in_6_bits_vaddr   (entries_6_baseVaddr),
+    .io_in_6_bits_needT   (entries_6_needT),
+    .io_in_6_bits_source  (entries_6_source),
+    .io_in_7_ready        (_pf_req_arb_io_in_7_ready),
+    .io_in_7_valid        (pf_req_arb_io_in_7_valid),
+    .io_in_7_bits_tag     (entries_7_paddrNoOffset[41:8]),
+    .io_in_7_bits_set     (entries_7_paddrNoOffset[7:0]),
+    .io_in_7_bits_vaddr   (entries_7_baseVaddr),
+    .io_in_7_bits_needT   (entries_7_needT),
+    .io_in_7_bits_source  (entries_7_source),
+    .io_in_8_ready        (_pf_req_arb_io_in_8_ready),
+    .io_in_8_valid        (pf_req_arb_io_in_8_valid),
+    .io_in_8_bits_tag     (entries_8_paddrNoOffset[41:8]),
+    .io_in_8_bits_set     (entries_8_paddrNoOffset[7:0]),
+    .io_in_8_bits_vaddr   (entries_8_baseVaddr),
+    .io_in_8_bits_needT   (entries_8_needT),
+    .io_in_8_bits_source  (entries_8_source),
+    .io_in_9_ready        (_pf_req_arb_io_in_9_ready),
+    .io_in_9_valid        (pf_req_arb_io_in_9_valid),
+    .io_in_9_bits_tag     (entries_9_paddrNoOffset[41:8]),
+    .io_in_9_bits_set     (entries_9_paddrNoOffset[7:0]),
+    .io_in_9_bits_vaddr   (entries_9_baseVaddr),
+    .io_in_9_bits_needT   (entries_9_needT),
+    .io_in_9_bits_source  (entries_9_source),
+    .io_in_10_ready       (_pf_req_arb_io_in_10_ready),
+    .io_in_10_valid       (pf_req_arb_io_in_10_valid),
+    .io_in_10_bits_tag    (entries_10_paddrNoOffset[41:8]),
+    .io_in_10_bits_set    (entries_10_paddrNoOffset[7:0]),
+    .io_in_10_bits_vaddr  (entries_10_baseVaddr),
+    .io_in_10_bits_needT  (entries_10_needT),
+    .io_in_10_bits_source (entries_10_source),
+    .io_in_11_ready       (_pf_req_arb_io_in_11_ready),
+    .io_in_11_valid       (pf_req_arb_io_in_11_valid),
+    .io_in_11_bits_tag    (entries_11_paddrNoOffset[41:8]),
+    .io_in_11_bits_set    (entries_11_paddrNoOffset[7:0]),
+    .io_in_11_bits_vaddr  (entries_11_baseVaddr),
+    .io_in_11_bits_needT  (entries_11_needT),
+    .io_in_11_bits_source (entries_11_source),
+    .io_in_12_ready       (_pf_req_arb_io_in_12_ready),
+    .io_in_12_valid       (pf_req_arb_io_in_12_valid),
+    .io_in_12_bits_tag    (entries_12_paddrNoOffset[41:8]),
+    .io_in_12_bits_set    (entries_12_paddrNoOffset[7:0]),
+    .io_in_12_bits_vaddr  (entries_12_baseVaddr),
+    .io_in_12_bits_needT  (entries_12_needT),
+    .io_in_12_bits_source (entries_12_source),
+    .io_in_13_ready       (_pf_req_arb_io_in_13_ready),
+    .io_in_13_valid       (pf_req_arb_io_in_13_valid),
+    .io_in_13_bits_tag    (entries_13_paddrNoOffset[41:8]),
+    .io_in_13_bits_set    (entries_13_paddrNoOffset[7:0]),
+    .io_in_13_bits_vaddr  (entries_13_baseVaddr),
+    .io_in_13_bits_needT  (entries_13_needT),
+    .io_in_13_bits_source (entries_13_source),
+    .io_in_14_ready       (_pf_req_arb_io_in_14_ready),
+    .io_in_14_valid       (pf_req_arb_io_in_14_valid),
+    .io_in_14_bits_tag    (entries_14_paddrNoOffset[41:8]),
+    .io_in_14_bits_set    (entries_14_paddrNoOffset[7:0]),
+    .io_in_14_bits_vaddr  (entries_14_baseVaddr),
+    .io_in_14_bits_needT  (entries_14_needT),
+    .io_in_14_bits_source (entries_14_source),
+    .io_in_15_ready       (_pf_req_arb_io_in_15_ready),
+    .io_in_15_valid       (pf_req_arb_io_in_15_valid),
+    .io_in_15_bits_tag    (entries_15_paddrNoOffset[41:8]),
+    .io_in_15_bits_set    (entries_15_paddrNoOffset[7:0]),
+    .io_in_15_bits_vaddr  (entries_15_baseVaddr),
+    .io_in_15_bits_needT  (entries_15_needT),
+    .io_in_15_bits_source (entries_15_source),
+    .io_out_ready         (io_out_req_ready),
+    .io_out_valid         (io_out_req_valid),
+    .io_out_bits_tag      (io_out_req_bits_tag),
+    .io_out_bits_set      (io_out_req_bits_set),
+    .io_out_bits_vaddr    (io_out_req_bits_vaddr),
+    .io_out_bits_needT    (io_out_req_bits_needT),
+    .io_out_bits_source   (io_out_req_bits_source)
+  );
+  assign io_tlb_req_req_valid = io_tlb_req_req_valid_REG;
+  assign io_tlb_req_req_bits_vaddr = io_tlb_req_req_bits_r_vaddr;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Prefetcher.sv b/flow/designs/src/xiangshan_coupledl2/deps/Prefetcher.sv
new file mode 100644
index 0000000000..488d0b2cda
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Prefetcher.sv
@@ -0,0 +1,327 @@
+// Generated by CIRCT firtool-1.135.0
+module Prefetcher(
+  input         clock,
+  input         reset,
+  output        io_train_0_ready,
+  input         io_train_0_valid,
+  input  [33:0] io_train_0_bits_tag,
+  input  [7:0]  io_train_0_bits_set,
+  input         io_train_0_bits_needT,
+  input  [6:0]  io_train_0_bits_source,
+  input  [43:0] io_train_0_bits_vaddr,
+  input  [4:0]  io_train_0_bits_reqsource,
+  output        io_tlb_req_req_valid,
+  output [49:0] io_tlb_req_req_bits_vaddr,
+  input         io_tlb_req_resp_valid,
+  input  [47:0] io_tlb_req_resp_bits_paddr_0,
+  input  [1:0]  io_tlb_req_resp_bits_pbmt,
+  input         io_tlb_req_resp_bits_miss,
+  input         io_tlb_req_resp_bits_excp_0_gpf_ld,
+  input         io_tlb_req_resp_bits_excp_0_pf_ld,
+  input         io_tlb_req_resp_bits_excp_0_af_ld,
+  input         io_tlb_req_pmp_resp_ld,
+  input         io_tlb_req_pmp_resp_mmio,
+  input         io_req_0_ready,
+  output        io_req_0_valid,
+  output [33:0] io_req_0_bits_tag,
+  output [7:0]  io_req_0_bits_set,
+  output [43:0] io_req_0_bits_vaddr,
+  output        io_req_0_bits_needT,
+  output [6:0]  io_req_0_bits_source,
+  output [4:0]  io_req_0_bits_pfSource,
+  output        io_resp_0_ready,
+  input         io_resp_0_valid,
+  input         pfCtrlFromCore_l2_pf_master_en,
+  input         pfCtrlFromCore_l2_pbop_en,
+  input         pfCtrlFromCore_l2_vbop_en,
+  input  [9:0]  pfCtrlFromCore_l2_pf_delay_latency,
+  input         sigFromSrams_bore_ram_hold,
+  input         sigFromSrams_bore_ram_bypass,
+  input         sigFromSrams_bore_ram_bp_clken,
+  input         sigFromSrams_bore_ram_aux_clk,
+  input         sigFromSrams_bore_ram_aux_ckbp,
+  input         sigFromSrams_bore_ram_mcp_hold,
+  input         sigFromSrams_bore_cgen,
+  input         sigFromSrams_bore_1_ram_hold,
+  input         sigFromSrams_bore_1_ram_bypass,
+  input         sigFromSrams_bore_1_ram_bp_clken,
+  input         sigFromSrams_bore_1_ram_aux_clk,
+  input         sigFromSrams_bore_1_ram_aux_ckbp,
+  input         sigFromSrams_bore_1_ram_mcp_hold,
+  input         sigFromSrams_bore_1_cgen,
+  input         boreChildrenBd_bore_array,
+  input         boreChildrenBd_bore_all,
+  input         boreChildrenBd_bore_req,
+  output        boreChildrenBd_bore_ack,
+  input         boreChildrenBd_bore_writeen,
+  input         boreChildrenBd_bore_be,
+  input  [8:0]  boreChildrenBd_bore_addr,
+  input  [12:0] boreChildrenBd_bore_indata,
+  input         boreChildrenBd_bore_readen,
+  input  [8:0]  boreChildrenBd_bore_addr_rd,
+  output [12:0] boreChildrenBd_bore_outdata
+);
+
+  wire [12:0] bd_outdata;
+  wire        bd_ack;
+  wire [12:0] childBd_1_rdata;
+  wire [12:0] childBd_rdata;
+  wire        _pipe_0_io_in_ready;
+  wire        _pftQueue_0_io_deq_valid;
+  wire [33:0] _pftQueue_0_io_deq_bits_tag;
+  wire [7:0]  _pftQueue_0_io_deq_bits_set;
+  wire [43:0] _pftQueue_0_io_deq_bits_vaddr;
+  wire        _pftQueue_0_io_deq_bits_needT;
+  wire [6:0]  _pftQueue_0_io_deq_bits_source;
+  wire [4:0]  _pftQueue_0_io_deq_bits_pfSource;
+  wire        _prefetch_train_arb_io_out_valid;
+  wire [33:0] _prefetch_train_arb_io_out_bits_tag;
+  wire [7:0]  _prefetch_train_arb_io_out_bits_set;
+  wire        _prefetch_train_arb_io_out_bits_needT;
+  wire [6:0]  _prefetch_train_arb_io_out_bits_source;
+  wire [43:0] _prefetch_train_arb_io_out_bits_vaddr;
+  wire [4:0]  _prefetch_train_arb_io_out_bits_reqsource;
+  wire        _vbop_io_req_valid;
+  wire [33:0] _vbop_io_req_bits_tag;
+  wire [7:0]  _vbop_io_req_bits_set;
+  wire [43:0] _vbop_io_req_bits_vaddr;
+  wire        _vbop_io_req_bits_needT;
+  wire [6:0]  _vbop_io_req_bits_source;
+  wire        _pbop_io_train_ready;
+  wire        _pbop_io_req_valid;
+  wire [33:0] _pbop_io_req_bits_tag;
+  wire [7:0]  _pbop_io_req_bits_set;
+  wire [43:0] _pbop_io_req_bits_vaddr;
+  wire        _pbop_io_req_bits_needT;
+  wire [6:0]  _pbop_io_req_bits_source;
+  wire        _pbop_io_resp_ready;
+  wire        bd_array = boreChildrenBd_bore_array;
+  wire        bd_all = boreChildrenBd_bore_all;
+  wire        bd_req = boreChildrenBd_bore_req;
+  wire        bd_writeen = boreChildrenBd_bore_writeen;
+  wire        bd_be = boreChildrenBd_bore_be;
+  wire [8:0]  bd_addr = boreChildrenBd_bore_addr;
+  wire [12:0] bd_indata = boreChildrenBd_bore_indata;
+  wire        bd_readen = boreChildrenBd_bore_readen;
+  wire [8:0]  bd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire        _pbop_io_train_valid_T = _prefetch_train_arb_io_out_bits_reqsource != 5'h6;
+  wire [1:0]  _GEN = _vbop_io_req_valid ? 2'h1 : {_pbop_io_req_valid, 1'h0};
+  wire [8:0]  childBd_addr;
+  wire [8:0]  childBd_addr_rd;
+  wire [12:0] childBd_wdata;
+  wire        childBd_wmask;
+  wire        childBd_re;
+  wire        childBd_we;
+  wire        childBd_ack;
+  wire        childBd_selectedOH;
+  wire        childBd_array;
+  PBestOffsetPrefetch pbop (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_enable
+      (pfCtrlFromCore_l2_pf_master_en & pfCtrlFromCore_l2_pbop_en),
+    .io_pfCtrlOfDelayLatency        (pfCtrlFromCore_l2_pf_delay_latency),
+    .io_train_ready                 (_pbop_io_train_ready),
+    .io_train_valid
+      (_prefetch_train_arb_io_out_valid & _pbop_io_train_valid_T),
+    .io_train_bits_tag              (_prefetch_train_arb_io_out_bits_tag),
+    .io_train_bits_set              (_prefetch_train_arb_io_out_bits_set),
+    .io_train_bits_needT            (_prefetch_train_arb_io_out_bits_needT),
+    .io_train_bits_source           (_prefetch_train_arb_io_out_bits_source),
+    .io_req_ready                   (_GEN[1]),
+    .io_req_valid                   (_pbop_io_req_valid),
+    .io_req_bits_tag                (_pbop_io_req_bits_tag),
+    .io_req_bits_set                (_pbop_io_req_bits_set),
+    .io_req_bits_vaddr              (_pbop_io_req_bits_vaddr),
+    .io_req_bits_needT              (_pbop_io_req_bits_needT),
+    .io_req_bits_source             (_pbop_io_req_bits_source),
+    .io_resp_ready                  (_pbop_io_resp_ready),
+    .boreChildrenBd_bore_addr       (childBd_addr),
+    .boreChildrenBd_bore_addr_rd    (childBd_addr_rd),
+    .boreChildrenBd_bore_wdata      (childBd_wdata),
+    .boreChildrenBd_bore_wmask      (childBd_wmask),
+    .boreChildrenBd_bore_re         (childBd_re),
+    .boreChildrenBd_bore_we         (childBd_we),
+    .boreChildrenBd_bore_rdata      (childBd_rdata),
+    .boreChildrenBd_bore_ack        (childBd_ack),
+    .boreChildrenBd_bore_selectedOH (childBd_selectedOH),
+    .boreChildrenBd_bore_array      (childBd_array),
+    .sigFromSrams_bore_ram_hold     (sigFromSrams_bore_ram_hold),
+    .sigFromSrams_bore_ram_bypass   (sigFromSrams_bore_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken (sigFromSrams_bore_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk  (sigFromSrams_bore_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp (sigFromSrams_bore_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold (sigFromSrams_bore_ram_mcp_hold),
+    .sigFromSrams_bore_cgen         (sigFromSrams_bore_cgen)
+  );
+  wire [8:0]  childBd_1_addr;
+  wire [8:0]  childBd_1_addr_rd;
+  wire [12:0] childBd_1_wdata;
+  wire        childBd_1_wmask;
+  wire        childBd_1_re;
+  wire        childBd_1_we;
+  wire        childBd_1_ack;
+  wire        childBd_1_selectedOH;
+  wire        childBd_1_array;
+  VBestOffsetPrefetch vbop (
+    .clock                              (clock),
+    .reset                              (reset),
+    .io_enable
+      (pfCtrlFromCore_l2_pf_master_en & pfCtrlFromCore_l2_vbop_en),
+    .io_pfCtrlOfDelayLatency            (pfCtrlFromCore_l2_pf_delay_latency),
+    .io_train_valid
+      (_prefetch_train_arb_io_out_valid & _pbop_io_train_valid_T),
+    .io_train_bits_needT                (_prefetch_train_arb_io_out_bits_needT),
+    .io_train_bits_source               (_prefetch_train_arb_io_out_bits_source),
+    .io_train_bits_vaddr                (_prefetch_train_arb_io_out_bits_vaddr),
+    .io_tlb_req_req_valid               (io_tlb_req_req_valid),
+    .io_tlb_req_req_bits_vaddr          (io_tlb_req_req_bits_vaddr),
+    .io_tlb_req_resp_valid              (io_tlb_req_resp_valid),
+    .io_tlb_req_resp_bits_paddr_0       (io_tlb_req_resp_bits_paddr_0),
+    .io_tlb_req_resp_bits_pbmt          (io_tlb_req_resp_bits_pbmt),
+    .io_tlb_req_resp_bits_miss          (io_tlb_req_resp_bits_miss),
+    .io_tlb_req_resp_bits_excp_0_gpf_ld (io_tlb_req_resp_bits_excp_0_gpf_ld),
+    .io_tlb_req_resp_bits_excp_0_pf_ld  (io_tlb_req_resp_bits_excp_0_pf_ld),
+    .io_tlb_req_resp_bits_excp_0_af_ld  (io_tlb_req_resp_bits_excp_0_af_ld),
+    .io_tlb_req_pmp_resp_ld             (io_tlb_req_pmp_resp_ld),
+    .io_tlb_req_pmp_resp_mmio           (io_tlb_req_pmp_resp_mmio),
+    .io_req_ready                       (_GEN[0]),
+    .io_req_valid                       (_vbop_io_req_valid),
+    .io_req_bits_tag                    (_vbop_io_req_bits_tag),
+    .io_req_bits_set                    (_vbop_io_req_bits_set),
+    .io_req_bits_vaddr                  (_vbop_io_req_bits_vaddr),
+    .io_req_bits_needT                  (_vbop_io_req_bits_needT),
+    .io_req_bits_source                 (_vbop_io_req_bits_source),
+    .boreChildrenBd_bore_addr           (childBd_1_addr),
+    .boreChildrenBd_bore_addr_rd        (childBd_1_addr_rd),
+    .boreChildrenBd_bore_wdata          (childBd_1_wdata),
+    .boreChildrenBd_bore_wmask          (childBd_1_wmask),
+    .boreChildrenBd_bore_re             (childBd_1_re),
+    .boreChildrenBd_bore_we             (childBd_1_we),
+    .boreChildrenBd_bore_rdata          (childBd_1_rdata),
+    .boreChildrenBd_bore_ack            (childBd_1_ack),
+    .boreChildrenBd_bore_selectedOH     (childBd_1_selectedOH),
+    .boreChildrenBd_bore_array          (childBd_1_array),
+    .sigFromSrams_bore_ram_hold         (sigFromSrams_bore_1_ram_hold),
+    .sigFromSrams_bore_ram_bypass       (sigFromSrams_bore_1_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken     (sigFromSrams_bore_1_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk      (sigFromSrams_bore_1_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp     (sigFromSrams_bore_1_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold     (sigFromSrams_bore_1_ram_mcp_hold),
+    .sigFromSrams_bore_cgen             (sigFromSrams_bore_1_cgen)
+  );
+  FastArbiter_8 prefetch_train_arb (
+    .io_in_0_ready          (io_train_0_ready),
+    .io_in_0_valid          (io_train_0_valid),
+    .io_in_0_bits_tag       (io_train_0_bits_tag),
+    .io_in_0_bits_set       (io_train_0_bits_set),
+    .io_in_0_bits_needT     (io_train_0_bits_needT),
+    .io_in_0_bits_source    (io_train_0_bits_source),
+    .io_in_0_bits_vaddr     (io_train_0_bits_vaddr),
+    .io_in_0_bits_reqsource (io_train_0_bits_reqsource),
+    .io_out_ready           (_pbop_io_train_ready),
+    .io_out_valid           (_prefetch_train_arb_io_out_valid),
+    .io_out_bits_tag        (_prefetch_train_arb_io_out_bits_tag),
+    .io_out_bits_set        (_prefetch_train_arb_io_out_bits_set),
+    .io_out_bits_needT      (_prefetch_train_arb_io_out_bits_needT),
+    .io_out_bits_source     (_prefetch_train_arb_io_out_bits_source),
+    .io_out_bits_vaddr      (_prefetch_train_arb_io_out_bits_vaddr),
+    .io_out_bits_reqsource  (_prefetch_train_arb_io_out_bits_reqsource)
+  );
+  FastArbiter_9 prefetch_resp_arb (
+    .io_in_0_ready (io_resp_0_ready),
+    .io_in_0_valid (io_resp_0_valid),
+    .io_out_ready  (_pbop_io_resp_ready)
+  );
+  MbistPipeL2Prefetcher mbistPl (
+    .clock               (clock),
+    .reset               (reset),
+    .mbist_array         (bd_array),
+    .mbist_all           (bd_all),
+    .mbist_req           (bd_req),
+    .mbist_ack           (bd_ack),
+    .mbist_writeen       (bd_writeen),
+    .mbist_be            (bd_be),
+    .mbist_addr          (bd_addr),
+    .mbist_indata        (bd_indata),
+    .mbist_readen        (bd_readen),
+    .mbist_addr_rd       (bd_addr_rd),
+    .mbist_outdata       (bd_outdata),
+    .toSRAM_0_addr       (childBd_addr),
+    .toSRAM_0_addr_rd    (childBd_addr_rd),
+    .toSRAM_0_wdata      (childBd_wdata),
+    .toSRAM_0_wmask      (childBd_wmask),
+    .toSRAM_0_re         (childBd_re),
+    .toSRAM_0_we         (childBd_we),
+    .toSRAM_0_rdata      (childBd_rdata),
+    .toSRAM_0_ack        (childBd_ack),
+    .toSRAM_0_selectedOH (childBd_selectedOH),
+    .toSRAM_0_array      (childBd_array),
+    .toSRAM_1_addr       (childBd_1_addr),
+    .toSRAM_1_addr_rd    (childBd_1_addr_rd),
+    .toSRAM_1_wdata      (childBd_1_wdata),
+    .toSRAM_1_wmask      (childBd_1_wmask),
+    .toSRAM_1_re         (childBd_1_re),
+    .toSRAM_1_we         (childBd_1_we),
+    .toSRAM_1_rdata      (childBd_1_rdata),
+    .toSRAM_1_ack        (childBd_1_ack),
+    .toSRAM_1_selectedOH (childBd_1_selectedOH),
+    .toSRAM_1_array      (childBd_1_array)
+  );
+  OverwriteQueue pftQueue_0 (
+    .clock                (clock),
+    .reset                (reset),
+    .io_enq_valid         (|{_pbop_io_req_valid, _vbop_io_req_valid}),
+    .io_enq_bits_tag
+      (_vbop_io_req_valid
+         ? _vbop_io_req_bits_tag
+         : _pbop_io_req_valid ? _pbop_io_req_bits_tag : 34'h0),
+    .io_enq_bits_set
+      (_vbop_io_req_valid
+         ? _vbop_io_req_bits_set
+         : _pbop_io_req_valid ? _pbop_io_req_bits_set : 8'h0),
+    .io_enq_bits_vaddr
+      (_vbop_io_req_valid
+         ? _vbop_io_req_bits_vaddr
+         : _pbop_io_req_valid ? _pbop_io_req_bits_vaddr : 44'h0),
+    .io_enq_bits_needT
+      (_vbop_io_req_valid
+         ? _vbop_io_req_bits_needT
+         : _pbop_io_req_valid & _pbop_io_req_bits_needT),
+    .io_enq_bits_source
+      (_vbop_io_req_valid
+         ? _vbop_io_req_bits_source
+         : _pbop_io_req_valid ? _pbop_io_req_bits_source : 7'h0),
+    .io_enq_bits_pfSource (_vbop_io_req_valid ? 5'h8 : _pbop_io_req_valid ? 5'h9 : 5'h0),
+    .io_deq_ready         (_pipe_0_io_in_ready),
+    .io_deq_valid         (_pftQueue_0_io_deq_valid),
+    .io_deq_bits_tag      (_pftQueue_0_io_deq_bits_tag),
+    .io_deq_bits_set      (_pftQueue_0_io_deq_bits_set),
+    .io_deq_bits_vaddr    (_pftQueue_0_io_deq_bits_vaddr),
+    .io_deq_bits_needT    (_pftQueue_0_io_deq_bits_needT),
+    .io_deq_bits_source   (_pftQueue_0_io_deq_bits_source),
+    .io_deq_bits_pfSource (_pftQueue_0_io_deq_bits_pfSource)
+  );
+  Pipeline_5 pipe_0 (
+    .clock                (clock),
+    .reset                (reset),
+    .io_in_ready          (_pipe_0_io_in_ready),
+    .io_in_valid          (_pftQueue_0_io_deq_valid),
+    .io_in_bits_tag       (_pftQueue_0_io_deq_bits_tag),
+    .io_in_bits_set       (_pftQueue_0_io_deq_bits_set),
+    .io_in_bits_vaddr     (_pftQueue_0_io_deq_bits_vaddr),
+    .io_in_bits_needT     (_pftQueue_0_io_deq_bits_needT),
+    .io_in_bits_source    (_pftQueue_0_io_deq_bits_source),
+    .io_in_bits_pfSource  (_pftQueue_0_io_deq_bits_pfSource),
+    .io_out_ready         (io_req_0_ready),
+    .io_out_valid         (io_req_0_valid),
+    .io_out_bits_tag      (io_req_0_bits_tag),
+    .io_out_bits_set      (io_req_0_bits_set),
+    .io_out_bits_vaddr    (io_req_0_bits_vaddr),
+    .io_out_bits_needT    (io_req_0_bits_needT),
+    .io_out_bits_source   (io_req_0_bits_source),
+    .io_out_bits_pfSource (io_req_0_bits_pfSource)
+  );
+  assign boreChildrenBd_bore_ack = bd_ack;
+  assign boreChildrenBd_bore_outdata = bd_outdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue10_GrantBuffer_Anon.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue10_GrantBuffer_Anon.sv
new file mode 100644
index 0000000000..1903ab2c49
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue10_GrantBuffer_Anon.sv
@@ -0,0 +1,109 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue10_GrantBuffer_Anon(
+  input        clock,
+  input        reset,
+  input        io_enq_valid,
+  input        io_deq_ready,
+  output       io_deq_valid,
+  output [3:0] io_count
+);
+
+  reg  [3:0] enq_ptr_value;
+  reg  [3:0] deq_ptr_value;
+  reg        maybe_full;
+  wire       ptr_match = enq_ptr_value == deq_ptr_value;
+  wire       empty = ptr_match & ~maybe_full;
+  wire       io_deq_valid_0 = io_enq_valid | ~empty;
+  wire [3:0] _ptr_diff_T = 4'(enq_ptr_value - deq_ptr_value);
+  wire       do_deq = ~empty & io_deq_ready & io_deq_valid_0;
+  wire       do_enq = ~(empty & io_deq_ready) & ~(ptr_match & maybe_full) & io_enq_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 4'h0;
+      deq_ptr_value <= 4'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= enq_ptr_value == 4'h9 ? 4'h0 : 4'(enq_ptr_value + 4'h1);
+      if (do_deq)
+        deq_ptr_value <= deq_ptr_value == 4'h9 ? 4'h0 : 4'(deq_ptr_value + 4'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][3:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][7:4];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 4'h0;
+        deq_ptr_value = 4'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_deq_valid = io_deq_valid_0;
+  assign io_count =
+    ptr_match
+      ? (maybe_full ? 4'hA : 4'h0)
+      : deq_ptr_value > enq_ptr_value ? 4'(_ptr_diff_T - 4'h6) : _ptr_diff_T;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue16_CHIREQ.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_CHIREQ.sv
new file mode 100644
index 0000000000..349c1bc3ca
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_CHIREQ.sv
@@ -0,0 +1,208 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue16_CHIREQ(
+  input         clock,
+  input         reset,
+  input         io_enq_valid,
+  input  [3:0]  io_enq_bits_qos,
+  input  [10:0] io_enq_bits_tgtID,
+  input  [10:0] io_enq_bits_srcID,
+  input  [11:0] io_enq_bits_txnID,
+  input  [6:0]  io_enq_bits_opcode,
+  input  [2:0]  io_enq_bits_size,
+  input  [47:0] io_enq_bits_addr,
+  input         io_enq_bits_likelyshared,
+  input         io_enq_bits_allowRetry,
+  input  [1:0]  io_enq_bits_order,
+  input  [3:0]  io_enq_bits_pCrdType,
+  input         io_enq_bits_memAttr_allocate,
+  input         io_enq_bits_memAttr_cacheable,
+  input         io_enq_bits_memAttr_device,
+  input         io_enq_bits_memAttr_ewa,
+  input         io_enq_bits_snpAttr,
+  input         io_enq_bits_expCompAck,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [3:0]  io_deq_bits_qos,
+  output [10:0] io_deq_bits_srcID,
+  output [11:0] io_deq_bits_txnID,
+  output [10:0] io_deq_bits_returnNID,
+  output        io_deq_bits_stashNIDValid,
+  output [11:0] io_deq_bits_returnTxnID,
+  output [6:0]  io_deq_bits_opcode,
+  output [47:0] io_deq_bits_addr,
+  output        io_deq_bits_ns,
+  output        io_deq_bits_likelyshared,
+  output        io_deq_bits_allowRetry,
+  output [1:0]  io_deq_bits_order,
+  output [3:0]  io_deq_bits_pCrdType,
+  output        io_deq_bits_memAttr_allocate,
+  output        io_deq_bits_memAttr_cacheable,
+  output        io_deq_bits_memAttr_device,
+  output        io_deq_bits_memAttr_ewa,
+  output        io_deq_bits_snpAttr,
+  output [7:0]  io_deq_bits_lpIDWithPadding,
+  output        io_deq_bits_snoopMe,
+  output        io_deq_bits_expCompAck,
+  output [1:0]  io_deq_bits_tagOp,
+  output        io_deq_bits_traceTag,
+  output        io_deq_bits_mpam_perfMonGroup,
+  output [8:0]  io_deq_bits_mpam_partID,
+  output        io_deq_bits_mpam_mpamNS,
+  output [3:0]  io_deq_bits_rsvdc,
+  output [4:0]  io_count
+);
+
+  wire         io_enq_ready;
+  wire [147:0] _ram_ext_R0_data;
+  reg  [3:0]   enq_ptr_value;
+  reg  [3:0]   deq_ptr_value;
+  reg          maybe_full;
+  wire         ptr_match = enq_ptr_value == deq_ptr_value;
+  wire         empty = ptr_match & ~maybe_full;
+  wire         full = ptr_match & maybe_full;
+  wire         do_enq = io_enq_ready & io_enq_valid;
+  assign io_enq_ready = ~full;
+  wire         do_deq = io_deq_ready & ~empty;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 4'h0;
+      deq_ptr_value <= 4'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 4'(enq_ptr_value + 4'h1);
+      if (do_deq)
+        deq_ptr_value <= 4'(deq_ptr_value + 4'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][3:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][7:4];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 4'h0;
+        deq_ptr_value = 4'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_16x148 ram_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data
+      ({io_enq_bits_qos,
+        io_enq_bits_srcID,
+        io_enq_bits_txnID,
+        24'h0,
+        io_enq_bits_opcode,
+        io_enq_bits_addr,
+        1'h0,
+        io_enq_bits_likelyshared,
+        io_enq_bits_allowRetry,
+        io_enq_bits_order,
+        io_enq_bits_pCrdType,
+        io_enq_bits_memAttr_allocate,
+        io_enq_bits_memAttr_cacheable,
+        io_enq_bits_memAttr_device,
+        io_enq_bits_memAttr_ewa,
+        io_enq_bits_snpAttr,
+        9'h0,
+        io_enq_bits_expCompAck,
+        18'h0})
+  );
+  assign io_deq_valid = ~empty;
+  assign io_deq_bits_qos = _ram_ext_R0_data[147:144];
+  assign io_deq_bits_srcID = _ram_ext_R0_data[143:133];
+  assign io_deq_bits_txnID = _ram_ext_R0_data[132:121];
+  assign io_deq_bits_returnNID = _ram_ext_R0_data[120:110];
+  assign io_deq_bits_stashNIDValid = _ram_ext_R0_data[109];
+  assign io_deq_bits_returnTxnID = _ram_ext_R0_data[108:97];
+  assign io_deq_bits_opcode = _ram_ext_R0_data[96:90];
+  assign io_deq_bits_addr = _ram_ext_R0_data[89:42];
+  assign io_deq_bits_ns = _ram_ext_R0_data[41];
+  assign io_deq_bits_likelyshared = _ram_ext_R0_data[40];
+  assign io_deq_bits_allowRetry = _ram_ext_R0_data[39];
+  assign io_deq_bits_order = _ram_ext_R0_data[38:37];
+  assign io_deq_bits_pCrdType = _ram_ext_R0_data[36:33];
+  assign io_deq_bits_memAttr_allocate = _ram_ext_R0_data[32];
+  assign io_deq_bits_memAttr_cacheable = _ram_ext_R0_data[31];
+  assign io_deq_bits_memAttr_device = _ram_ext_R0_data[30];
+  assign io_deq_bits_memAttr_ewa = _ram_ext_R0_data[29];
+  assign io_deq_bits_snpAttr = _ram_ext_R0_data[28];
+  assign io_deq_bits_lpIDWithPadding = _ram_ext_R0_data[27:20];
+  assign io_deq_bits_snoopMe = _ram_ext_R0_data[19];
+  assign io_deq_bits_expCompAck = _ram_ext_R0_data[18];
+  assign io_deq_bits_tagOp = _ram_ext_R0_data[17:16];
+  assign io_deq_bits_traceTag = _ram_ext_R0_data[15];
+  assign io_deq_bits_mpam_perfMonGroup = _ram_ext_R0_data[14];
+  assign io_deq_bits_mpam_partID = _ram_ext_R0_data[13:5];
+  assign io_deq_bits_mpam_mpamNS = _ram_ext_R0_data[4];
+  assign io_deq_bits_rsvdc = _ram_ext_R0_data[3:0];
+  assign io_count = {full, 4'(enq_ptr_value - deq_ptr_value)};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue16_CHIRSP.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_CHIRSP.sv
new file mode 100644
index 0000000000..977dedbdc8
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_CHIRSP.sv
@@ -0,0 +1,167 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue16_CHIRSP(
+  input         clock,
+  input         reset,
+  input         io_enq_valid,
+  input  [10:0] io_enq_bits_tgtID,
+  input  [10:0] io_enq_bits_srcID,
+  input  [11:0] io_enq_bits_txnID,
+  input  [4:0]  io_enq_bits_opcode,
+  input  [1:0]  io_enq_bits_respErr,
+  input  [2:0]  io_enq_bits_resp,
+  input  [2:0]  io_enq_bits_fwdState,
+  input  [11:0] io_enq_bits_dbID,
+  input  [3:0]  io_enq_bits_pCrdType,
+  input         io_enq_bits_traceTag,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [3:0]  io_deq_bits_qos,
+  output [10:0] io_deq_bits_tgtID,
+  output [10:0] io_deq_bits_srcID,
+  output [11:0] io_deq_bits_txnID,
+  output [4:0]  io_deq_bits_opcode,
+  output [1:0]  io_deq_bits_respErr,
+  output [2:0]  io_deq_bits_resp,
+  output [2:0]  io_deq_bits_fwdState,
+  output [2:0]  io_deq_bits_cBusy,
+  output [11:0] io_deq_bits_dbID,
+  output [3:0]  io_deq_bits_pCrdType,
+  output [1:0]  io_deq_bits_tagOp,
+  output        io_deq_bits_traceTag,
+  output [4:0]  io_count
+);
+
+  wire        io_enq_ready;
+  wire [72:0] _ram_ext_R0_data;
+  reg  [3:0]  enq_ptr_value;
+  reg  [3:0]  deq_ptr_value;
+  reg         maybe_full;
+  wire        ptr_match = enq_ptr_value == deq_ptr_value;
+  wire        empty = ptr_match & ~maybe_full;
+  wire        full = ptr_match & maybe_full;
+  wire        do_enq = io_enq_ready & io_enq_valid;
+  assign io_enq_ready = ~full;
+  wire        do_deq = io_deq_ready & ~empty;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 4'h0;
+      deq_ptr_value <= 4'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 4'(enq_ptr_value + 4'h1);
+      if (do_deq)
+        deq_ptr_value <= 4'(deq_ptr_value + 4'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][3:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][7:4];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 4'h0;
+        deq_ptr_value = 4'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_16x73 ram_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data
+      ({4'h0,
+        io_enq_bits_tgtID,
+        io_enq_bits_srcID,
+        io_enq_bits_txnID,
+        io_enq_bits_opcode,
+        io_enq_bits_respErr,
+        io_enq_bits_resp,
+        io_enq_bits_fwdState,
+        3'h0,
+        io_enq_bits_dbID,
+        io_enq_bits_pCrdType,
+        2'h0,
+        io_enq_bits_traceTag})
+  );
+  assign io_deq_valid = ~empty;
+  assign io_deq_bits_qos = _ram_ext_R0_data[72:69];
+  assign io_deq_bits_tgtID = _ram_ext_R0_data[68:58];
+  assign io_deq_bits_srcID = _ram_ext_R0_data[57:47];
+  assign io_deq_bits_txnID = _ram_ext_R0_data[46:35];
+  assign io_deq_bits_opcode = _ram_ext_R0_data[34:30];
+  assign io_deq_bits_respErr = _ram_ext_R0_data[29:28];
+  assign io_deq_bits_resp = _ram_ext_R0_data[27:25];
+  assign io_deq_bits_fwdState = _ram_ext_R0_data[24:22];
+  assign io_deq_bits_cBusy = _ram_ext_R0_data[21:19];
+  assign io_deq_bits_dbID = _ram_ext_R0_data[18:7];
+  assign io_deq_bits_pCrdType = _ram_ext_R0_data[6:3];
+  assign io_deq_bits_tagOp = _ram_ext_R0_data[2:1];
+  assign io_deq_bits_traceTag = _ram_ext_R0_data[0];
+  assign io_count = {full, 4'(enq_ptr_value - deq_ptr_value)};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue16_DSBeat.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_DSBeat.sv
new file mode 100644
index 0000000000..259b28405e
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_DSBeat.sv
@@ -0,0 +1,115 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue16_DSBeat(
+  input          clock,
+  input          reset,
+  input          io_enq_valid,
+  input  [255:0] io_enq_bits_data,
+  input          io_deq_ready,
+  output [255:0] io_deq_bits_data
+);
+
+  wire [255:0] _ram_data_ext_R0_data;
+  reg  [3:0]   enq_ptr_value;
+  reg  [3:0]   deq_ptr_value;
+  reg          maybe_full;
+  wire         ptr_match = enq_ptr_value == deq_ptr_value;
+  wire         empty = ptr_match & ~maybe_full;
+  wire         do_enq =
+    ~(empty & io_deq_ready) & ~(ptr_match & maybe_full) & io_enq_valid;
+  wire         do_deq = ~empty & io_deq_ready & (io_enq_valid | ~empty);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 4'h0;
+      deq_ptr_value <= 4'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 4'(enq_ptr_value + 4'h1);
+      if (do_deq)
+        deq_ptr_value <= 4'(deq_ptr_value + 4'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][3:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][7:4];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 4'h0;
+        deq_ptr_value = 4'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_data_16x256 ram_data_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_data_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data (io_enq_bits_data)
+  );
+  assign io_deq_bits_data = empty ? io_enq_bits_data : _ram_data_ext_R0_data;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue16_GrantQueueData.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_GrantQueueData.sv
new file mode 100644
index 0000000000..9cfea5af08
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_GrantQueueData.sv
@@ -0,0 +1,113 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue16_GrantQueueData(
+  input          clock,
+  input          reset,
+  input          io_enq_valid,
+  input  [255:0] io_enq_bits_data_data,
+  input          io_deq_ready,
+  output [255:0] io_deq_bits_data_data
+);
+
+  wire       io_enq_ready;
+  reg  [3:0] enq_ptr_value;
+  reg  [3:0] deq_ptr_value;
+  reg        maybe_full;
+  wire       ptr_match = enq_ptr_value == deq_ptr_value;
+  wire       do_enq = io_enq_ready & io_enq_valid;
+  assign io_enq_ready = ~(ptr_match & maybe_full);
+  wire       do_deq = io_deq_ready & ~(ptr_match & ~maybe_full);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 4'h0;
+      deq_ptr_value <= 4'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 4'(enq_ptr_value + 4'h1);
+      if (do_deq)
+        deq_ptr_value <= 4'(deq_ptr_value + 4'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][3:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][7:4];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 4'h0;
+        deq_ptr_value = 4'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_data_16x256 ram_data_data_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (io_deq_bits_data_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data (io_enq_bits_data_data)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue16_GrantQueueTask.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_GrantQueueTask.sv
new file mode 100644
index 0000000000..4af377c5e4
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_GrantQueueTask.sv
@@ -0,0 +1,234 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue16_GrantQueueTask(
+  input         clock,
+  input         reset,
+  input         io_enq_valid,
+  input  [2:0]  io_enq_bits_task_channel,
+  input  [2:0]  io_enq_bits_task_txChannel,
+  input  [7:0]  io_enq_bits_task_set,
+  input  [33:0] io_enq_bits_task_tag,
+  input  [5:0]  io_enq_bits_task_off,
+  input         io_enq_bits_task_alias,
+  input  [43:0] io_enq_bits_task_vaddr,
+  input         io_enq_bits_task_isKeyword,
+  input  [3:0]  io_enq_bits_task_opcode,
+  input  [2:0]  io_enq_bits_task_param,
+  input  [2:0]  io_enq_bits_task_size,
+  input  [6:0]  io_enq_bits_task_sourceId,
+  input  [1:0]  io_enq_bits_task_bufIdx,
+  input         io_enq_bits_task_needProbeAckData,
+  input         io_enq_bits_task_denied,
+  input         io_enq_bits_task_corrupt,
+  input         io_enq_bits_task_mshrTask,
+  input  [7:0]  io_enq_bits_task_mshrId,
+  input         io_enq_bits_task_aliasTask,
+  input         io_enq_bits_task_useProbeData,
+  input         io_enq_bits_task_mshrRetry,
+  input         io_enq_bits_task_readProbeDataDown,
+  input         io_enq_bits_task_fromL2pft,
+  input         io_enq_bits_task_needHint,
+  input         io_enq_bits_task_dirty,
+  input  [2:0]  io_enq_bits_task_way,
+  input         io_enq_bits_task_meta_dirty,
+  input  [1:0]  io_enq_bits_task_meta_state,
+  input         io_enq_bits_task_meta_clients,
+  input         io_enq_bits_task_meta_alias,
+  input         io_enq_bits_task_meta_prefetch,
+  input  [3:0]  io_enq_bits_task_meta_prefetchSrc,
+  input         io_enq_bits_task_meta_accessed,
+  input         io_enq_bits_task_meta_tagErr,
+  input         io_enq_bits_task_meta_dataErr,
+  input         io_enq_bits_task_metaWen,
+  input         io_enq_bits_task_tagWen,
+  input         io_enq_bits_task_dsWen,
+  input  [7:0]  io_enq_bits_task_wayMask,
+  input         io_enq_bits_task_replTask,
+  input         io_enq_bits_task_cmoTask,
+  input         io_enq_bits_task_cmoAll,
+  input  [4:0]  io_enq_bits_task_reqSource,
+  input         io_enq_bits_task_mergeA,
+  input  [5:0]  io_enq_bits_task_aMergeTask_off,
+  input         io_enq_bits_task_aMergeTask_alias,
+  input  [43:0] io_enq_bits_task_aMergeTask_vaddr,
+  input         io_enq_bits_task_aMergeTask_isKeyword,
+  input  [2:0]  io_enq_bits_task_aMergeTask_opcode,
+  input  [2:0]  io_enq_bits_task_aMergeTask_param,
+  input  [6:0]  io_enq_bits_task_aMergeTask_sourceId,
+  input         io_enq_bits_task_aMergeTask_meta_dirty,
+  input  [1:0]  io_enq_bits_task_aMergeTask_meta_state,
+  input         io_enq_bits_task_aMergeTask_meta_clients,
+  input         io_enq_bits_task_aMergeTask_meta_alias,
+  input         io_enq_bits_task_aMergeTask_meta_prefetch,
+  input  [3:0]  io_enq_bits_task_aMergeTask_meta_prefetchSrc,
+  input         io_enq_bits_task_aMergeTask_meta_accessed,
+  input         io_enq_bits_task_aMergeTask_meta_tagErr,
+  input         io_enq_bits_task_aMergeTask_meta_dataErr,
+  input         io_enq_bits_task_snpHitRelease,
+  input         io_enq_bits_task_snpHitReleaseToInval,
+  input         io_enq_bits_task_snpHitReleaseToClean,
+  input         io_enq_bits_task_snpHitReleaseWithData,
+  input  [7:0]  io_enq_bits_task_snpHitReleaseIdx,
+  input         io_enq_bits_task_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_enq_bits_task_snpHitReleaseMeta_state,
+  input         io_enq_bits_task_snpHitReleaseMeta_clients,
+  input         io_enq_bits_task_snpHitReleaseMeta_alias,
+  input         io_enq_bits_task_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_enq_bits_task_snpHitReleaseMeta_prefetchSrc,
+  input         io_enq_bits_task_snpHitReleaseMeta_accessed,
+  input         io_enq_bits_task_snpHitReleaseMeta_tagErr,
+  input         io_enq_bits_task_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_enq_bits_task_tgtID,
+  input  [10:0] io_enq_bits_task_srcID,
+  input  [11:0] io_enq_bits_task_txnID,
+  input  [10:0] io_enq_bits_task_homeNID,
+  input  [11:0] io_enq_bits_task_dbID,
+  input  [10:0] io_enq_bits_task_fwdNID,
+  input  [11:0] io_enq_bits_task_fwdTxnID,
+  input  [6:0]  io_enq_bits_task_chiOpcode,
+  input  [2:0]  io_enq_bits_task_resp,
+  input  [2:0]  io_enq_bits_task_fwdState,
+  input  [3:0]  io_enq_bits_task_pCrdType,
+  input         io_enq_bits_task_retToSrc,
+  input         io_enq_bits_task_likelyshared,
+  input         io_enq_bits_task_expCompAck,
+  input         io_enq_bits_task_allowRetry,
+  input         io_enq_bits_task_memAttr_allocate,
+  input         io_enq_bits_task_memAttr_cacheable,
+  input         io_enq_bits_task_memAttr_device,
+  input         io_enq_bits_task_memAttr_ewa,
+  input         io_enq_bits_task_traceTag,
+  input  [7:0]  io_enq_bits_grantid,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output        io_deq_bits_task_isKeyword,
+  output [3:0]  io_deq_bits_task_opcode,
+  output [2:0]  io_deq_bits_task_param,
+  output [6:0]  io_deq_bits_task_sourceId,
+  output        io_deq_bits_task_denied,
+  output        io_deq_bits_task_corrupt,
+  output [7:0]  io_deq_bits_grantid,
+  output [4:0]  io_count
+);
+
+  wire        io_enq_ready;
+  wire [24:0] _ram_ext_R0_data;
+  reg  [3:0]  enq_ptr_value;
+  reg  [3:0]  deq_ptr_value;
+  reg         maybe_full;
+  wire        ptr_match = enq_ptr_value == deq_ptr_value;
+  wire        empty = ptr_match & ~maybe_full;
+  wire        full = ptr_match & maybe_full;
+  wire        do_enq = io_enq_ready & io_enq_valid;
+  assign io_enq_ready = ~full;
+  wire        do_deq = io_deq_ready & ~empty;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 4'h0;
+      deq_ptr_value <= 4'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 4'(enq_ptr_value + 4'h1);
+      if (do_deq)
+        deq_ptr_value <= 4'(deq_ptr_value + 4'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][3:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][7:4];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 4'h0;
+        deq_ptr_value = 4'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_16x25 ram_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data
+      ({io_enq_bits_task_isKeyword,
+        io_enq_bits_task_opcode,
+        io_enq_bits_task_param,
+        io_enq_bits_task_sourceId,
+        io_enq_bits_task_denied,
+        io_enq_bits_task_corrupt,
+        io_enq_bits_grantid})
+  );
+  assign io_deq_valid = ~empty;
+  assign io_deq_bits_task_isKeyword = _ram_ext_R0_data[24];
+  assign io_deq_bits_task_opcode = _ram_ext_R0_data[23:20];
+  assign io_deq_bits_task_param = _ram_ext_R0_data[19:17];
+  assign io_deq_bits_task_sourceId = _ram_ext_R0_data[16:10];
+  assign io_deq_bits_task_denied = _ram_ext_R0_data[9];
+  assign io_deq_bits_task_corrupt = _ram_ext_R0_data[8];
+  assign io_deq_bits_grantid = _ram_ext_R0_data[7:0];
+  assign io_count = {full, 4'(enq_ptr_value - deq_ptr_value)};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue16_HintQueueEntry.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_HintQueueEntry.sv
new file mode 100644
index 0000000000..a20fe836e5
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_HintQueueEntry.sv
@@ -0,0 +1,128 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue16_HintQueueEntry(
+  input        clock,
+  input        reset,
+  output       io_enq_ready,
+  input        io_enq_valid,
+  input  [6:0] io_enq_bits_source,
+  input        io_enq_bits_isGrantData,
+  input        io_enq_bits_isKeyword,
+  input        io_enq_bits_hasData,
+  input        io_deq_ready,
+  output       io_deq_valid,
+  output [6:0] io_deq_bits_source,
+  output       io_deq_bits_isKeyword,
+  output       io_deq_bits_hasData,
+  output [4:0] io_count
+);
+
+  wire [8:0] _ram_ext_R0_data;
+  reg  [3:0] enq_ptr_value;
+  reg  [3:0] deq_ptr_value;
+  reg        maybe_full;
+  wire       ptr_match = enq_ptr_value == deq_ptr_value;
+  wire       empty = ptr_match & ~maybe_full;
+  wire       full = ptr_match & maybe_full;
+  wire       do_enq = ~full & io_enq_valid;
+  wire       do_deq = io_deq_ready & ~empty;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 4'h0;
+      deq_ptr_value <= 4'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 4'(enq_ptr_value + 4'h1);
+      if (do_deq)
+        deq_ptr_value <= 4'(deq_ptr_value + 4'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][3:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][7:4];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 4'h0;
+        deq_ptr_value = 4'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_16x9 ram_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data ({io_enq_bits_source, io_enq_bits_isKeyword, io_enq_bits_hasData})
+  );
+  assign io_enq_ready = ~full;
+  assign io_deq_valid = ~empty;
+  assign io_deq_bits_source = _ram_ext_R0_data[8:2];
+  assign io_deq_bits_isKeyword = _ram_ext_R0_data[1];
+  assign io_deq_bits_hasData = _ram_ext_R0_data[0];
+  assign io_count = {full, 4'(enq_ptr_value - deq_ptr_value)};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue16_TaskBundle.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_TaskBundle.sv
new file mode 100644
index 0000000000..669e209d5b
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue16_TaskBundle.sv
@@ -0,0 +1,246 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue16_TaskBundle(
+  input         clock,
+  input         reset,
+  output        io_enq_ready,
+  input         io_enq_valid,
+  input  [2:0]  io_enq_bits_channel,
+  input  [2:0]  io_enq_bits_txChannel,
+  input  [7:0]  io_enq_bits_set,
+  input  [33:0] io_enq_bits_tag,
+  input  [5:0]  io_enq_bits_off,
+  input         io_enq_bits_alias,
+  input  [43:0] io_enq_bits_vaddr,
+  input         io_enq_bits_isKeyword,
+  input  [3:0]  io_enq_bits_opcode,
+  input  [2:0]  io_enq_bits_param,
+  input  [2:0]  io_enq_bits_size,
+  input  [6:0]  io_enq_bits_sourceId,
+  input  [1:0]  io_enq_bits_bufIdx,
+  input         io_enq_bits_needProbeAckData,
+  input         io_enq_bits_denied,
+  input         io_enq_bits_corrupt,
+  input         io_enq_bits_mshrTask,
+  input  [7:0]  io_enq_bits_mshrId,
+  input         io_enq_bits_aliasTask,
+  input         io_enq_bits_useProbeData,
+  input         io_enq_bits_mshrRetry,
+  input         io_enq_bits_readProbeDataDown,
+  input         io_enq_bits_fromL2pft,
+  input         io_enq_bits_needHint,
+  input         io_enq_bits_dirty,
+  input  [2:0]  io_enq_bits_way,
+  input         io_enq_bits_meta_dirty,
+  input  [1:0]  io_enq_bits_meta_state,
+  input         io_enq_bits_meta_clients,
+  input         io_enq_bits_meta_alias,
+  input         io_enq_bits_meta_prefetch,
+  input  [3:0]  io_enq_bits_meta_prefetchSrc,
+  input         io_enq_bits_meta_accessed,
+  input         io_enq_bits_meta_tagErr,
+  input         io_enq_bits_meta_dataErr,
+  input         io_enq_bits_metaWen,
+  input         io_enq_bits_tagWen,
+  input         io_enq_bits_dsWen,
+  input  [7:0]  io_enq_bits_wayMask,
+  input         io_enq_bits_replTask,
+  input         io_enq_bits_cmoTask,
+  input         io_enq_bits_cmoAll,
+  input  [4:0]  io_enq_bits_reqSource,
+  input         io_enq_bits_mergeA,
+  input  [5:0]  io_enq_bits_aMergeTask_off,
+  input         io_enq_bits_aMergeTask_alias,
+  input  [43:0] io_enq_bits_aMergeTask_vaddr,
+  input         io_enq_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_enq_bits_aMergeTask_opcode,
+  input  [2:0]  io_enq_bits_aMergeTask_param,
+  input  [6:0]  io_enq_bits_aMergeTask_sourceId,
+  input         io_enq_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_enq_bits_aMergeTask_meta_state,
+  input         io_enq_bits_aMergeTask_meta_clients,
+  input         io_enq_bits_aMergeTask_meta_alias,
+  input         io_enq_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_enq_bits_aMergeTask_meta_prefetchSrc,
+  input         io_enq_bits_aMergeTask_meta_accessed,
+  input         io_enq_bits_aMergeTask_meta_tagErr,
+  input         io_enq_bits_aMergeTask_meta_dataErr,
+  input         io_enq_bits_snpHitRelease,
+  input         io_enq_bits_snpHitReleaseToInval,
+  input         io_enq_bits_snpHitReleaseToClean,
+  input         io_enq_bits_snpHitReleaseWithData,
+  input  [7:0]  io_enq_bits_snpHitReleaseIdx,
+  input         io_enq_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_enq_bits_snpHitReleaseMeta_state,
+  input         io_enq_bits_snpHitReleaseMeta_clients,
+  input         io_enq_bits_snpHitReleaseMeta_alias,
+  input         io_enq_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_enq_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_enq_bits_snpHitReleaseMeta_accessed,
+  input         io_enq_bits_snpHitReleaseMeta_tagErr,
+  input         io_enq_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_enq_bits_tgtID,
+  input  [10:0] io_enq_bits_srcID,
+  input  [11:0] io_enq_bits_txnID,
+  input  [10:0] io_enq_bits_homeNID,
+  input  [11:0] io_enq_bits_dbID,
+  input  [10:0] io_enq_bits_fwdNID,
+  input  [11:0] io_enq_bits_fwdTxnID,
+  input  [6:0]  io_enq_bits_chiOpcode,
+  input  [2:0]  io_enq_bits_resp,
+  input  [2:0]  io_enq_bits_fwdState,
+  input  [3:0]  io_enq_bits_pCrdType,
+  input         io_enq_bits_retToSrc,
+  input         io_enq_bits_likelyshared,
+  input         io_enq_bits_expCompAck,
+  input         io_enq_bits_allowRetry,
+  input         io_enq_bits_memAttr_allocate,
+  input         io_enq_bits_memAttr_cacheable,
+  input         io_enq_bits_memAttr_device,
+  input         io_enq_bits_memAttr_ewa,
+  input         io_enq_bits_traceTag,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [5:0]  io_deq_bits_off,
+  output        io_deq_bits_corrupt,
+  output [10:0] io_deq_bits_tgtID,
+  output [10:0] io_deq_bits_srcID,
+  output [11:0] io_deq_bits_txnID,
+  output [10:0] io_deq_bits_homeNID,
+  output [11:0] io_deq_bits_dbID,
+  output [6:0]  io_deq_bits_chiOpcode,
+  output [2:0]  io_deq_bits_resp,
+  output [2:0]  io_deq_bits_fwdState,
+  output        io_deq_bits_traceTag,
+  output [4:0]  io_count
+);
+
+  wire [77:0] _ram_ext_R0_data;
+  reg  [3:0]  enq_ptr_value;
+  reg  [3:0]  deq_ptr_value;
+  reg         maybe_full;
+  wire        ptr_match = enq_ptr_value == deq_ptr_value;
+  wire        empty = ptr_match & ~maybe_full;
+  wire        full = ptr_match & maybe_full;
+  wire        io_deq_valid_0 = io_enq_valid | ~empty;
+  wire        do_enq = ~(empty & io_deq_ready) & ~full & io_enq_valid;
+  wire        do_deq = ~empty & io_deq_ready & io_deq_valid_0;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 4'h0;
+      deq_ptr_value <= 4'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 4'(enq_ptr_value + 4'h1);
+      if (do_deq)
+        deq_ptr_value <= 4'(deq_ptr_value + 4'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][3:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][7:4];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][8];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 4'h0;
+        deq_ptr_value = 4'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_16x78 ram_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data
+      ({io_enq_bits_off,
+        io_enq_bits_corrupt,
+        io_enq_bits_tgtID,
+        io_enq_bits_srcID,
+        io_enq_bits_txnID,
+        io_enq_bits_homeNID,
+        io_enq_bits_dbID,
+        io_enq_bits_chiOpcode,
+        io_enq_bits_resp,
+        io_enq_bits_fwdState,
+        io_enq_bits_traceTag})
+  );
+  assign io_enq_ready = ~full;
+  assign io_deq_valid = io_deq_valid_0;
+  assign io_deq_bits_off = empty ? io_enq_bits_off : _ram_ext_R0_data[77:72];
+  assign io_deq_bits_corrupt = empty ? io_enq_bits_corrupt : _ram_ext_R0_data[71];
+  assign io_deq_bits_tgtID = empty ? io_enq_bits_tgtID : _ram_ext_R0_data[70:60];
+  assign io_deq_bits_srcID = empty ? io_enq_bits_srcID : _ram_ext_R0_data[59:49];
+  assign io_deq_bits_txnID = empty ? io_enq_bits_txnID : _ram_ext_R0_data[48:37];
+  assign io_deq_bits_homeNID = empty ? io_enq_bits_homeNID : _ram_ext_R0_data[36:26];
+  assign io_deq_bits_dbID = empty ? io_enq_bits_dbID : _ram_ext_R0_data[25:14];
+  assign io_deq_bits_chiOpcode = empty ? io_enq_bits_chiOpcode : _ram_ext_R0_data[13:7];
+  assign io_deq_bits_resp = empty ? io_enq_bits_resp : _ram_ext_R0_data[6:4];
+  assign io_deq_bits_fwdState = empty ? io_enq_bits_fwdState : _ram_ext_R0_data[3:1];
+  assign io_deq_bits_traceTag = empty ? io_enq_bits_traceTag : _ram_ext_R0_data[0];
+  assign io_count = {full, 4'(enq_ptr_value - deq_ptr_value)};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue1_CHIDAT.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_CHIDAT.sv
new file mode 100644
index 0000000000..95adfce36a
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_CHIDAT.sv
@@ -0,0 +1,197 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue1_CHIDAT(
+  input          clock,
+  input          reset,
+  output         io_enq_ready,
+  input          io_enq_valid,
+  input  [3:0]   io_enq_bits_qos,
+  input  [10:0]  io_enq_bits_tgtID,
+  input  [10:0]  io_enq_bits_srcID,
+  input  [11:0]  io_enq_bits_txnID,
+  input  [10:0]  io_enq_bits_homeNID,
+  input  [3:0]   io_enq_bits_opcode,
+  input  [1:0]   io_enq_bits_respErr,
+  input  [2:0]   io_enq_bits_resp,
+  input  [3:0]   io_enq_bits_dataSource,
+  input  [2:0]   io_enq_bits_cBusy,
+  input  [11:0]  io_enq_bits_dbID,
+  input  [1:0]   io_enq_bits_ccID,
+  input  [1:0]   io_enq_bits_dataID,
+  input  [1:0]   io_enq_bits_tagOp,
+  input  [7:0]   io_enq_bits_tag,
+  input  [1:0]   io_enq_bits_tu,
+  input          io_enq_bits_traceTag,
+  input  [3:0]   io_enq_bits_rsvdc,
+  input  [31:0]  io_enq_bits_be,
+  input  [255:0] io_enq_bits_data,
+  input  [31:0]  io_enq_bits_dataCheck,
+  input  [3:0]   io_enq_bits_poison,
+  input          io_deq_ready,
+  output         io_deq_valid,
+  output [3:0]   io_deq_bits_qos,
+  output [10:0]  io_deq_bits_tgtID,
+  output [10:0]  io_deq_bits_srcID,
+  output [11:0]  io_deq_bits_txnID,
+  output [10:0]  io_deq_bits_homeNID,
+  output [3:0]   io_deq_bits_opcode,
+  output [1:0]   io_deq_bits_respErr,
+  output [2:0]   io_deq_bits_resp,
+  output [3:0]   io_deq_bits_dataSource,
+  output [2:0]   io_deq_bits_cBusy,
+  output [11:0]  io_deq_bits_dbID,
+  output [1:0]   io_deq_bits_ccID,
+  output [1:0]   io_deq_bits_dataID,
+  output [1:0]   io_deq_bits_tagOp,
+  output [7:0]   io_deq_bits_tag,
+  output [1:0]   io_deq_bits_tu,
+  output         io_deq_bits_traceTag,
+  output [3:0]   io_deq_bits_rsvdc,
+  output [31:0]  io_deq_bits_be,
+  output [255:0] io_deq_bits_data,
+  output [31:0]  io_deq_bits_dataCheck,
+  output [3:0]   io_deq_bits_poison
+);
+
+  reg  [421:0] ram;
+  wire         io_enq_ready_0;
+  reg          maybe_full;
+  wire         do_enq = io_enq_ready_0 & io_enq_valid;
+  assign io_enq_ready_0 = io_deq_ready | ~maybe_full;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      maybe_full <= 1'h0;
+    else if (do_enq != (io_deq_ready & maybe_full))
+      maybe_full <= do_enq;
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (do_enq)
+      ram <=
+        {io_enq_bits_qos,
+         io_enq_bits_tgtID,
+         io_enq_bits_srcID,
+         io_enq_bits_txnID,
+         io_enq_bits_homeNID,
+         io_enq_bits_opcode,
+         io_enq_bits_respErr,
+         io_enq_bits_resp,
+         io_enq_bits_dataSource,
+         io_enq_bits_cBusy,
+         io_enq_bits_dbID,
+         io_enq_bits_ccID,
+         io_enq_bits_dataID,
+         io_enq_bits_tagOp,
+         io_enq_bits_tag,
+         io_enq_bits_tu,
+         io_enq_bits_traceTag,
+         io_enq_bits_rsvdc,
+         io_enq_bits_be,
+         io_enq_bits_data,
+         io_enq_bits_dataCheck,
+         io_enq_bits_poison};
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:13];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hE; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        maybe_full = _RANDOM[4'h0][0];
+        ram =
+          {_RANDOM[4'h0][31:1],
+           _RANDOM[4'h1],
+           _RANDOM[4'h2],
+           _RANDOM[4'h3],
+           _RANDOM[4'h4],
+           _RANDOM[4'h5],
+           _RANDOM[4'h6],
+           _RANDOM[4'h7],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB],
+           _RANDOM[4'hC],
+           _RANDOM[4'hD][6:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        maybe_full = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_enq_ready = io_enq_ready_0;
+  assign io_deq_valid = maybe_full;
+  assign io_deq_bits_qos = ram[421:418];
+  assign io_deq_bits_tgtID = ram[417:407];
+  assign io_deq_bits_srcID = ram[406:396];
+  assign io_deq_bits_txnID = ram[395:384];
+  assign io_deq_bits_homeNID = ram[383:373];
+  assign io_deq_bits_opcode = ram[372:369];
+  assign io_deq_bits_respErr = ram[368:367];
+  assign io_deq_bits_resp = ram[366:364];
+  assign io_deq_bits_dataSource = ram[363:360];
+  assign io_deq_bits_cBusy = ram[359:357];
+  assign io_deq_bits_dbID = ram[356:345];
+  assign io_deq_bits_ccID = ram[344:343];
+  assign io_deq_bits_dataID = ram[342:341];
+  assign io_deq_bits_tagOp = ram[340:339];
+  assign io_deq_bits_tag = ram[338:331];
+  assign io_deq_bits_tu = ram[330:329];
+  assign io_deq_bits_traceTag = ram[328];
+  assign io_deq_bits_rsvdc = ram[327:324];
+  assign io_deq_bits_be = ram[323:292];
+  assign io_deq_bits_data = ram[291:36];
+  assign io_deq_bits_dataCheck = ram[35:4];
+  assign io_deq_bits_poison = ram[3:0];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue1_CHIRSP.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_CHIRSP.sv
new file mode 100644
index 0000000000..aa346bf4d1
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_CHIRSP.sv
@@ -0,0 +1,147 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue1_CHIRSP(
+  input         clock,
+  input         reset,
+  output        io_enq_ready,
+  input         io_enq_valid,
+  input  [3:0]  io_enq_bits_qos,
+  input  [10:0] io_enq_bits_tgtID,
+  input  [10:0] io_enq_bits_srcID,
+  input  [11:0] io_enq_bits_txnID,
+  input  [4:0]  io_enq_bits_opcode,
+  input  [1:0]  io_enq_bits_respErr,
+  input  [2:0]  io_enq_bits_resp,
+  input  [2:0]  io_enq_bits_fwdState,
+  input  [2:0]  io_enq_bits_cBusy,
+  input  [11:0] io_enq_bits_dbID,
+  input  [3:0]  io_enq_bits_pCrdType,
+  input  [1:0]  io_enq_bits_tagOp,
+  input         io_enq_bits_traceTag,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [3:0]  io_deq_bits_qos,
+  output [10:0] io_deq_bits_tgtID,
+  output [10:0] io_deq_bits_srcID,
+  output [11:0] io_deq_bits_txnID,
+  output [4:0]  io_deq_bits_opcode,
+  output [1:0]  io_deq_bits_respErr,
+  output [2:0]  io_deq_bits_resp,
+  output [2:0]  io_deq_bits_fwdState,
+  output [2:0]  io_deq_bits_cBusy,
+  output [11:0] io_deq_bits_dbID,
+  output [3:0]  io_deq_bits_pCrdType,
+  output [1:0]  io_deq_bits_tagOp,
+  output        io_deq_bits_traceTag
+);
+
+  reg  [72:0] ram;
+  wire        io_enq_ready_0;
+  reg         maybe_full;
+  wire        do_enq = io_enq_ready_0 & io_enq_valid;
+  assign io_enq_ready_0 = io_deq_ready | ~maybe_full;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      maybe_full <= 1'h0;
+    else if (do_enq != (io_deq_ready & maybe_full))
+      maybe_full <= do_enq;
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (do_enq)
+      ram <=
+        {io_enq_bits_qos,
+         io_enq_bits_tgtID,
+         io_enq_bits_srcID,
+         io_enq_bits_txnID,
+         io_enq_bits_opcode,
+         io_enq_bits_respErr,
+         io_enq_bits_resp,
+         io_enq_bits_fwdState,
+         io_enq_bits_cBusy,
+         io_enq_bits_dbID,
+         io_enq_bits_pCrdType,
+         io_enq_bits_tagOp,
+         io_enq_bits_traceTag};
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:2];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        maybe_full = _RANDOM[2'h0][0];
+        ram = {_RANDOM[2'h0][31:1], _RANDOM[2'h1], _RANDOM[2'h2][9:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        maybe_full = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_enq_ready = io_enq_ready_0;
+  assign io_deq_valid = maybe_full;
+  assign io_deq_bits_qos = ram[72:69];
+  assign io_deq_bits_tgtID = ram[68:58];
+  assign io_deq_bits_srcID = ram[57:47];
+  assign io_deq_bits_txnID = ram[46:35];
+  assign io_deq_bits_opcode = ram[34:30];
+  assign io_deq_bits_respErr = ram[29:28];
+  assign io_deq_bits_resp = ram[27:25];
+  assign io_deq_bits_fwdState = ram[24:22];
+  assign io_deq_bits_cBusy = ram[21:19];
+  assign io_deq_bits_dbID = ram[18:7];
+  assign io_deq_bits_pCrdType = ram[6:3];
+  assign io_deq_bits_tagOp = ram[2:1];
+  assign io_deq_bits_traceTag = ram[0];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue1_ChosenQBundle.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_ChosenQBundle.sv
new file mode 100644
index 0000000000..34c5f79f18
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_ChosenQBundle.sv
@@ -0,0 +1,341 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue1_ChosenQBundle(
+  input         clock,
+  input         reset,
+  output        io_enq_ready,
+  input         io_enq_valid,
+  input         io_enq_bits_bits_valid,
+  input         io_enq_bits_bits_rdy,
+  input  [2:0]  io_enq_bits_bits_task_channel,
+  input  [7:0]  io_enq_bits_bits_task_set,
+  input  [33:0] io_enq_bits_bits_task_tag,
+  input  [5:0]  io_enq_bits_bits_task_off,
+  input         io_enq_bits_bits_task_alias,
+  input  [43:0] io_enq_bits_bits_task_vaddr,
+  input         io_enq_bits_bits_task_isKeyword,
+  input  [3:0]  io_enq_bits_bits_task_opcode,
+  input  [2:0]  io_enq_bits_bits_task_param,
+  input  [2:0]  io_enq_bits_bits_task_size,
+  input  [6:0]  io_enq_bits_bits_task_sourceId,
+  input         io_enq_bits_bits_task_corrupt,
+  input         io_enq_bits_bits_task_fromL2pft,
+  input         io_enq_bits_bits_task_needHint,
+  input  [4:0]  io_enq_bits_bits_task_reqSource,
+  input  [3:0]  io_enq_bits_bits_waitMP,
+  input  [15:0] io_enq_bits_bits_waitMS,
+  input  [3:0]  io_enq_bits_idOH,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [2:0]  io_deq_bits_bits_task_channel,
+  output [2:0]  io_deq_bits_bits_task_txChannel,
+  output [7:0]  io_deq_bits_bits_task_set,
+  output [33:0] io_deq_bits_bits_task_tag,
+  output [5:0]  io_deq_bits_bits_task_off,
+  output        io_deq_bits_bits_task_alias,
+  output [43:0] io_deq_bits_bits_task_vaddr,
+  output        io_deq_bits_bits_task_isKeyword,
+  output [3:0]  io_deq_bits_bits_task_opcode,
+  output [2:0]  io_deq_bits_bits_task_param,
+  output [2:0]  io_deq_bits_bits_task_size,
+  output [6:0]  io_deq_bits_bits_task_sourceId,
+  output [1:0]  io_deq_bits_bits_task_bufIdx,
+  output        io_deq_bits_bits_task_needProbeAckData,
+  output        io_deq_bits_bits_task_denied,
+  output        io_deq_bits_bits_task_corrupt,
+  output        io_deq_bits_bits_task_mshrTask,
+  output [7:0]  io_deq_bits_bits_task_mshrId,
+  output        io_deq_bits_bits_task_aliasTask,
+  output        io_deq_bits_bits_task_useProbeData,
+  output        io_deq_bits_bits_task_mshrRetry,
+  output        io_deq_bits_bits_task_readProbeDataDown,
+  output        io_deq_bits_bits_task_fromL2pft,
+  output        io_deq_bits_bits_task_needHint,
+  output        io_deq_bits_bits_task_dirty,
+  output [2:0]  io_deq_bits_bits_task_way,
+  output        io_deq_bits_bits_task_meta_dirty,
+  output [1:0]  io_deq_bits_bits_task_meta_state,
+  output        io_deq_bits_bits_task_meta_clients,
+  output        io_deq_bits_bits_task_meta_alias,
+  output        io_deq_bits_bits_task_meta_prefetch,
+  output [3:0]  io_deq_bits_bits_task_meta_prefetchSrc,
+  output        io_deq_bits_bits_task_meta_accessed,
+  output        io_deq_bits_bits_task_meta_tagErr,
+  output        io_deq_bits_bits_task_meta_dataErr,
+  output        io_deq_bits_bits_task_metaWen,
+  output        io_deq_bits_bits_task_tagWen,
+  output        io_deq_bits_bits_task_dsWen,
+  output        io_deq_bits_bits_task_replTask,
+  output        io_deq_bits_bits_task_cmoTask,
+  output        io_deq_bits_bits_task_cmoAll,
+  output [4:0]  io_deq_bits_bits_task_reqSource,
+  output        io_deq_bits_bits_task_mergeA,
+  output [5:0]  io_deq_bits_bits_task_aMergeTask_off,
+  output        io_deq_bits_bits_task_aMergeTask_alias,
+  output [43:0] io_deq_bits_bits_task_aMergeTask_vaddr,
+  output        io_deq_bits_bits_task_aMergeTask_isKeyword,
+  output [2:0]  io_deq_bits_bits_task_aMergeTask_opcode,
+  output [2:0]  io_deq_bits_bits_task_aMergeTask_param,
+  output [6:0]  io_deq_bits_bits_task_aMergeTask_sourceId,
+  output        io_deq_bits_bits_task_aMergeTask_meta_dirty,
+  output [1:0]  io_deq_bits_bits_task_aMergeTask_meta_state,
+  output        io_deq_bits_bits_task_aMergeTask_meta_clients,
+  output        io_deq_bits_bits_task_aMergeTask_meta_alias,
+  output        io_deq_bits_bits_task_aMergeTask_meta_prefetch,
+  output [3:0]  io_deq_bits_bits_task_aMergeTask_meta_prefetchSrc,
+  output        io_deq_bits_bits_task_aMergeTask_meta_accessed,
+  output        io_deq_bits_bits_task_aMergeTask_meta_tagErr,
+  output        io_deq_bits_bits_task_aMergeTask_meta_dataErr,
+  output        io_deq_bits_bits_task_snpHitRelease,
+  output        io_deq_bits_bits_task_snpHitReleaseToInval,
+  output        io_deq_bits_bits_task_snpHitReleaseToClean,
+  output        io_deq_bits_bits_task_snpHitReleaseWithData,
+  output [7:0]  io_deq_bits_bits_task_snpHitReleaseIdx,
+  output        io_deq_bits_bits_task_snpHitReleaseMeta_dirty,
+  output [1:0]  io_deq_bits_bits_task_snpHitReleaseMeta_state,
+  output        io_deq_bits_bits_task_snpHitReleaseMeta_clients,
+  output        io_deq_bits_bits_task_snpHitReleaseMeta_alias,
+  output        io_deq_bits_bits_task_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_deq_bits_bits_task_snpHitReleaseMeta_prefetchSrc,
+  output        io_deq_bits_bits_task_snpHitReleaseMeta_accessed,
+  output        io_deq_bits_bits_task_snpHitReleaseMeta_tagErr,
+  output        io_deq_bits_bits_task_snpHitReleaseMeta_dataErr,
+  output [10:0] io_deq_bits_bits_task_tgtID,
+  output [10:0] io_deq_bits_bits_task_srcID,
+  output [11:0] io_deq_bits_bits_task_txnID,
+  output [10:0] io_deq_bits_bits_task_homeNID,
+  output [11:0] io_deq_bits_bits_task_dbID,
+  output [10:0] io_deq_bits_bits_task_fwdNID,
+  output [11:0] io_deq_bits_bits_task_fwdTxnID,
+  output [6:0]  io_deq_bits_bits_task_chiOpcode,
+  output [2:0]  io_deq_bits_bits_task_resp,
+  output [2:0]  io_deq_bits_bits_task_fwdState,
+  output [3:0]  io_deq_bits_bits_task_pCrdType,
+  output        io_deq_bits_bits_task_retToSrc,
+  output        io_deq_bits_bits_task_likelyshared,
+  output        io_deq_bits_bits_task_expCompAck,
+  output        io_deq_bits_bits_task_allowRetry,
+  output        io_deq_bits_bits_task_memAttr_allocate,
+  output        io_deq_bits_bits_task_memAttr_cacheable,
+  output        io_deq_bits_bits_task_memAttr_device,
+  output        io_deq_bits_bits_task_memAttr_ewa,
+  output        io_deq_bits_bits_task_traceTag,
+  output [3:0]  io_deq_bits_idOH
+);
+
+  reg  [408:0] ram;
+  wire         io_enq_ready_0;
+  reg          maybe_full;
+  wire         do_enq = io_enq_ready_0 & io_enq_valid;
+  assign io_enq_ready_0 = io_deq_ready | ~maybe_full;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      maybe_full <= 1'h0;
+    else if (do_enq != (io_deq_ready & maybe_full))
+      maybe_full <= do_enq;
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (do_enq)
+      ram <=
+        {io_enq_bits_bits_valid,
+         io_enq_bits_bits_rdy,
+         io_enq_bits_bits_task_channel,
+         3'h0,
+         io_enq_bits_bits_task_set,
+         io_enq_bits_bits_task_tag,
+         io_enq_bits_bits_task_off,
+         io_enq_bits_bits_task_alias,
+         io_enq_bits_bits_task_vaddr,
+         io_enq_bits_bits_task_isKeyword,
+         io_enq_bits_bits_task_opcode,
+         io_enq_bits_bits_task_param,
+         io_enq_bits_bits_task_size,
+         io_enq_bits_bits_task_sourceId,
+         4'h0,
+         io_enq_bits_bits_task_corrupt,
+         13'h0,
+         io_enq_bits_bits_task_fromL2pft,
+         io_enq_bits_bits_task_needHint,
+         31'h0,
+         io_enq_bits_bits_task_reqSource,
+         210'h0,
+         io_enq_bits_bits_waitMP,
+         io_enq_bits_bits_waitMS,
+         io_enq_bits_idOH};
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:12];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hD; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        maybe_full = _RANDOM[4'h0][0];
+        ram =
+          {_RANDOM[4'h0][31:1],
+           _RANDOM[4'h1],
+           _RANDOM[4'h2],
+           _RANDOM[4'h3],
+           _RANDOM[4'h4],
+           _RANDOM[4'h5],
+           _RANDOM[4'h6],
+           _RANDOM[4'h7],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB],
+           _RANDOM[4'hC][25:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        maybe_full = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_enq_ready = io_enq_ready_0;
+  assign io_deq_valid = maybe_full;
+  assign io_deq_bits_bits_task_channel = ram[406:404];
+  assign io_deq_bits_bits_task_txChannel = ram[403:401];
+  assign io_deq_bits_bits_task_set = ram[400:393];
+  assign io_deq_bits_bits_task_tag = ram[392:359];
+  assign io_deq_bits_bits_task_off = ram[358:353];
+  assign io_deq_bits_bits_task_alias = ram[352];
+  assign io_deq_bits_bits_task_vaddr = ram[351:308];
+  assign io_deq_bits_bits_task_isKeyword = ram[307];
+  assign io_deq_bits_bits_task_opcode = ram[306:303];
+  assign io_deq_bits_bits_task_param = ram[302:300];
+  assign io_deq_bits_bits_task_size = ram[299:297];
+  assign io_deq_bits_bits_task_sourceId = ram[296:290];
+  assign io_deq_bits_bits_task_bufIdx = ram[289:288];
+  assign io_deq_bits_bits_task_needProbeAckData = ram[287];
+  assign io_deq_bits_bits_task_denied = ram[286];
+  assign io_deq_bits_bits_task_corrupt = ram[285];
+  assign io_deq_bits_bits_task_mshrTask = ram[284];
+  assign io_deq_bits_bits_task_mshrId = ram[283:276];
+  assign io_deq_bits_bits_task_aliasTask = ram[275];
+  assign io_deq_bits_bits_task_useProbeData = ram[274];
+  assign io_deq_bits_bits_task_mshrRetry = ram[273];
+  assign io_deq_bits_bits_task_readProbeDataDown = ram[272];
+  assign io_deq_bits_bits_task_fromL2pft = ram[271];
+  assign io_deq_bits_bits_task_needHint = ram[270];
+  assign io_deq_bits_bits_task_dirty = ram[269];
+  assign io_deq_bits_bits_task_way = ram[268:266];
+  assign io_deq_bits_bits_task_meta_dirty = ram[265];
+  assign io_deq_bits_bits_task_meta_state = ram[264:263];
+  assign io_deq_bits_bits_task_meta_clients = ram[262];
+  assign io_deq_bits_bits_task_meta_alias = ram[261];
+  assign io_deq_bits_bits_task_meta_prefetch = ram[260];
+  assign io_deq_bits_bits_task_meta_prefetchSrc = ram[259:256];
+  assign io_deq_bits_bits_task_meta_accessed = ram[255];
+  assign io_deq_bits_bits_task_meta_tagErr = ram[254];
+  assign io_deq_bits_bits_task_meta_dataErr = ram[253];
+  assign io_deq_bits_bits_task_metaWen = ram[252];
+  assign io_deq_bits_bits_task_tagWen = ram[251];
+  assign io_deq_bits_bits_task_dsWen = ram[250];
+  assign io_deq_bits_bits_task_replTask = ram[241];
+  assign io_deq_bits_bits_task_cmoTask = ram[240];
+  assign io_deq_bits_bits_task_cmoAll = ram[239];
+  assign io_deq_bits_bits_task_reqSource = ram[238:234];
+  assign io_deq_bits_bits_task_mergeA = ram[233];
+  assign io_deq_bits_bits_task_aMergeTask_off = ram[232:227];
+  assign io_deq_bits_bits_task_aMergeTask_alias = ram[226];
+  assign io_deq_bits_bits_task_aMergeTask_vaddr = ram[225:182];
+  assign io_deq_bits_bits_task_aMergeTask_isKeyword = ram[181];
+  assign io_deq_bits_bits_task_aMergeTask_opcode = ram[180:178];
+  assign io_deq_bits_bits_task_aMergeTask_param = ram[177:175];
+  assign io_deq_bits_bits_task_aMergeTask_sourceId = ram[174:168];
+  assign io_deq_bits_bits_task_aMergeTask_meta_dirty = ram[167];
+  assign io_deq_bits_bits_task_aMergeTask_meta_state = ram[166:165];
+  assign io_deq_bits_bits_task_aMergeTask_meta_clients = ram[164];
+  assign io_deq_bits_bits_task_aMergeTask_meta_alias = ram[163];
+  assign io_deq_bits_bits_task_aMergeTask_meta_prefetch = ram[162];
+  assign io_deq_bits_bits_task_aMergeTask_meta_prefetchSrc = ram[161:158];
+  assign io_deq_bits_bits_task_aMergeTask_meta_accessed = ram[157];
+  assign io_deq_bits_bits_task_aMergeTask_meta_tagErr = ram[156];
+  assign io_deq_bits_bits_task_aMergeTask_meta_dataErr = ram[155];
+  assign io_deq_bits_bits_task_snpHitRelease = ram[154];
+  assign io_deq_bits_bits_task_snpHitReleaseToInval = ram[153];
+  assign io_deq_bits_bits_task_snpHitReleaseToClean = ram[152];
+  assign io_deq_bits_bits_task_snpHitReleaseWithData = ram[151];
+  assign io_deq_bits_bits_task_snpHitReleaseIdx = ram[150:143];
+  assign io_deq_bits_bits_task_snpHitReleaseMeta_dirty = ram[142];
+  assign io_deq_bits_bits_task_snpHitReleaseMeta_state = ram[141:140];
+  assign io_deq_bits_bits_task_snpHitReleaseMeta_clients = ram[139];
+  assign io_deq_bits_bits_task_snpHitReleaseMeta_alias = ram[138];
+  assign io_deq_bits_bits_task_snpHitReleaseMeta_prefetch = ram[137];
+  assign io_deq_bits_bits_task_snpHitReleaseMeta_prefetchSrc = ram[136:133];
+  assign io_deq_bits_bits_task_snpHitReleaseMeta_accessed = ram[132];
+  assign io_deq_bits_bits_task_snpHitReleaseMeta_tagErr = ram[131];
+  assign io_deq_bits_bits_task_snpHitReleaseMeta_dataErr = ram[130];
+  assign io_deq_bits_bits_task_tgtID = ram[129:119];
+  assign io_deq_bits_bits_task_srcID = ram[118:108];
+  assign io_deq_bits_bits_task_txnID = ram[107:96];
+  assign io_deq_bits_bits_task_homeNID = ram[95:85];
+  assign io_deq_bits_bits_task_dbID = ram[84:73];
+  assign io_deq_bits_bits_task_fwdNID = ram[72:62];
+  assign io_deq_bits_bits_task_fwdTxnID = ram[61:50];
+  assign io_deq_bits_bits_task_chiOpcode = ram[49:43];
+  assign io_deq_bits_bits_task_resp = ram[42:40];
+  assign io_deq_bits_bits_task_fwdState = ram[39:37];
+  assign io_deq_bits_bits_task_pCrdType = ram[36:33];
+  assign io_deq_bits_bits_task_retToSrc = ram[32];
+  assign io_deq_bits_bits_task_likelyshared = ram[31];
+  assign io_deq_bits_bits_task_expCompAck = ram[30];
+  assign io_deq_bits_bits_task_allowRetry = ram[29];
+  assign io_deq_bits_bits_task_memAttr_allocate = ram[28];
+  assign io_deq_bits_bits_task_memAttr_cacheable = ram[27];
+  assign io_deq_bits_bits_task_memAttr_device = ram[26];
+  assign io_deq_bits_bits_task_memAttr_ewa = ram[25];
+  assign io_deq_bits_bits_task_traceTag = ram[24];
+  assign io_deq_bits_idOH = ram[3:0];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue1_HintQueueEntry.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_HintQueueEntry.sv
new file mode 100644
index 0000000000..55d8c40910
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_HintQueueEntry.sv
@@ -0,0 +1,107 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue1_HintQueueEntry(
+  input        clock,
+  input        reset,
+  input        io_enq_valid,
+  input  [6:0] io_enq_bits_source,
+  input        io_enq_bits_isGrantData,
+  input        io_enq_bits_isKeyword,
+  input        io_enq_bits_hasData,
+  input        io_deq_ready,
+  output       io_deq_valid,
+  output [6:0] io_deq_bits_source,
+  output       io_deq_bits_isGrantData,
+  output       io_deq_bits_isKeyword,
+  output       io_deq_bits_hasData
+);
+
+  reg  [9:0] ram;
+  wire       io_enq_ready;
+  reg        maybe_full;
+  wire       do_enq = io_enq_ready & io_enq_valid;
+  assign io_enq_ready = io_deq_ready | ~maybe_full;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      maybe_full <= 1'h0;
+    else if (do_enq != (io_deq_ready & maybe_full))
+      maybe_full <= do_enq;
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (do_enq)
+      ram <=
+        {io_enq_bits_source,
+         io_enq_bits_isGrantData,
+         io_enq_bits_isKeyword,
+         io_enq_bits_hasData};
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][0];
+        ram = _RANDOM[/*Zero width*/ 1'b0][10:1];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        maybe_full = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_deq_valid = maybe_full;
+  assign io_deq_bits_source = ram[9:3];
+  assign io_deq_bits_isGrantData = ram[2];
+  assign io_deq_bits_isKeyword = ram[1];
+  assign io_deq_bits_hasData = ram[0];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchReq.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchReq.sv
new file mode 100644
index 0000000000..f0a83e342b
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchReq.sv
@@ -0,0 +1,119 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue1_PrefetchReq(
+  input         clock,
+  input         reset,
+  output        io_enq_ready,
+  input         io_enq_valid,
+  input  [33:0] io_enq_bits_tag,
+  input  [7:0]  io_enq_bits_set,
+  input  [43:0] io_enq_bits_vaddr,
+  input         io_enq_bits_needT,
+  input  [6:0]  io_enq_bits_source,
+  input  [4:0]  io_enq_bits_pfSource,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [33:0] io_deq_bits_tag,
+  output [7:0]  io_deq_bits_set,
+  output [43:0] io_deq_bits_vaddr,
+  output        io_deq_bits_needT,
+  output [6:0]  io_deq_bits_source,
+  output [4:0]  io_deq_bits_pfSource
+);
+
+  reg  [98:0] ram;
+  wire        io_enq_ready_0;
+  reg         maybe_full;
+  wire        do_enq = io_enq_ready_0 & io_enq_valid;
+  assign io_enq_ready_0 = io_deq_ready | ~maybe_full;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      maybe_full <= 1'h0;
+    else if (do_enq != (io_deq_ready & maybe_full))
+      maybe_full <= do_enq;
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (do_enq)
+      ram <=
+        {io_enq_bits_tag,
+         io_enq_bits_set,
+         io_enq_bits_vaddr,
+         io_enq_bits_needT,
+         io_enq_bits_source,
+         io_enq_bits_pfSource};
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:3];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
+          _RANDOM[i[1:0]] = `RANDOM;
+        end
+        maybe_full = _RANDOM[2'h0][0];
+        ram = {_RANDOM[2'h0][31:1], _RANDOM[2'h1], _RANDOM[2'h2], _RANDOM[2'h3][3:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        maybe_full = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_enq_ready = io_enq_ready_0;
+  assign io_deq_valid = maybe_full;
+  assign io_deq_bits_tag = ram[98:65];
+  assign io_deq_bits_set = ram[64:57];
+  assign io_deq_bits_vaddr = ram[56:13];
+  assign io_deq_bits_needT = ram[12];
+  assign io_deq_bits_source = ram[11:5];
+  assign io_deq_bits_pfSource = ram[4:0];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchResp.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchResp.sv
new file mode 100644
index 0000000000..96b0cdff3b
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchResp.sv
@@ -0,0 +1,86 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue1_PrefetchResp(
+  input  clock,
+  input  reset,
+  output io_enq_ready,
+  input  io_enq_valid,
+  input  io_deq_ready,
+  output io_deq_valid
+);
+
+  reg  maybe_full;
+  wire io_enq_ready_0 = io_deq_ready | ~maybe_full;
+  wire do_enq = io_enq_ready_0 & io_enq_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      maybe_full <= 1'h0;
+    else if (do_enq != (io_deq_ready & maybe_full))
+      maybe_full <= do_enq;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        maybe_full = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_enq_ready = io_enq_ready_0;
+  assign io_deq_valid = maybe_full;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchTrain.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchTrain.sv
new file mode 100644
index 0000000000..536f9f5efe
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue1_PrefetchTrain.sv
@@ -0,0 +1,123 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue1_PrefetchTrain(
+  input         clock,
+  input         reset,
+  input         io_enq_valid,
+  input  [33:0] io_enq_bits_tag,
+  input  [7:0]  io_enq_bits_set,
+  input         io_enq_bits_needT,
+  input  [6:0]  io_enq_bits_source,
+  input  [43:0] io_enq_bits_vaddr,
+  input         io_enq_bits_hit,
+  input         io_enq_bits_prefetched,
+  input  [3:0]  io_enq_bits_pfsource,
+  input  [4:0]  io_enq_bits_reqsource,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [33:0] io_deq_bits_tag,
+  output [7:0]  io_deq_bits_set,
+  output        io_deq_bits_needT,
+  output [6:0]  io_deq_bits_source,
+  output [43:0] io_deq_bits_vaddr,
+  output [4:0]  io_deq_bits_reqsource
+);
+
+  reg  [104:0] ram;
+  wire         io_enq_ready;
+  reg          maybe_full;
+  wire         do_enq = io_enq_ready & io_enq_valid;
+  assign io_enq_ready = io_deq_ready | ~maybe_full;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      maybe_full <= 1'h0;
+    else if (do_enq != (io_deq_ready & maybe_full))
+      maybe_full <= do_enq;
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (do_enq)
+      ram <=
+        {io_enq_bits_tag,
+         io_enq_bits_set,
+         io_enq_bits_needT,
+         io_enq_bits_source,
+         io_enq_bits_vaddr,
+         io_enq_bits_hit,
+         io_enq_bits_prefetched,
+         io_enq_bits_pfsource,
+         io_enq_bits_reqsource};
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:3];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
+          _RANDOM[i[1:0]] = `RANDOM;
+        end
+        maybe_full = _RANDOM[2'h0][0];
+        ram = {_RANDOM[2'h0][31:1], _RANDOM[2'h1], _RANDOM[2'h2], _RANDOM[2'h3][9:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        maybe_full = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_deq_valid = maybe_full;
+  assign io_deq_bits_tag = ram[104:71];
+  assign io_deq_bits_set = ram[70:63];
+  assign io_deq_bits_needT = ram[62];
+  assign io_deq_bits_source = ram[61:55];
+  assign io_deq_bits_vaddr = ram[54:11];
+  assign io_deq_bits_reqsource = ram[4:0];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue2_CHISNP.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue2_CHISNP.sv
new file mode 100644
index 0000000000..e3050f413e
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue2_CHISNP.sv
@@ -0,0 +1,154 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue2_CHISNP(
+  input         clock,
+  input         reset,
+  output        io_enq_ready,
+  input         io_enq_valid,
+  input  [3:0]  io_enq_bits_qos,
+  input  [10:0] io_enq_bits_srcID,
+  input  [11:0] io_enq_bits_txnID,
+  input  [10:0] io_enq_bits_fwdNID,
+  input  [11:0] io_enq_bits_fwdTxnID,
+  input  [4:0]  io_enq_bits_opcode,
+  input  [44:0] io_enq_bits_addr,
+  input         io_enq_bits_ns,
+  input         io_enq_bits_doNotGoToSD,
+  input         io_enq_bits_retToSrc,
+  input         io_enq_bits_traceTag,
+  input         io_enq_bits_mpam_perfMonGroup,
+  input  [8:0]  io_enq_bits_mpam_partID,
+  input         io_enq_bits_mpam_mpamNS,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [10:0] io_deq_bits_srcID,
+  output [11:0] io_deq_bits_txnID,
+  output [10:0] io_deq_bits_fwdNID,
+  output [11:0] io_deq_bits_fwdTxnID,
+  output [4:0]  io_deq_bits_opcode,
+  output [44:0] io_deq_bits_addr,
+  output        io_deq_bits_retToSrc,
+  output        io_deq_bits_traceTag
+);
+
+  wire [97:0] _ram_ext_R0_data;
+  reg         enq_ptr_value;
+  reg         deq_ptr_value;
+  reg         maybe_full;
+  wire        ptr_match = enq_ptr_value == deq_ptr_value;
+  wire        empty = ptr_match & ~maybe_full;
+  wire        full = ptr_match & maybe_full;
+  wire        do_enq = ~full & io_enq_valid;
+  wire        do_deq = io_deq_ready & ~empty;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 1'h0;
+      deq_ptr_value <= 1'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 1'(enq_ptr_value - 1'h1);
+      if (do_deq)
+        deq_ptr_value <= 1'(deq_ptr_value - 1'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][1];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][2];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 1'h0;
+        deq_ptr_value = 1'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_2x98 ram_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data
+      ({io_enq_bits_srcID,
+        io_enq_bits_txnID,
+        io_enq_bits_fwdNID,
+        io_enq_bits_fwdTxnID,
+        io_enq_bits_opcode,
+        io_enq_bits_addr,
+        io_enq_bits_retToSrc,
+        io_enq_bits_traceTag})
+  );
+  assign io_enq_ready = ~full;
+  assign io_deq_valid = ~empty;
+  assign io_deq_bits_srcID = _ram_ext_R0_data[97:87];
+  assign io_deq_bits_txnID = _ram_ext_R0_data[86:75];
+  assign io_deq_bits_fwdNID = _ram_ext_R0_data[74:64];
+  assign io_deq_bits_fwdTxnID = _ram_ext_R0_data[63:52];
+  assign io_deq_bits_opcode = _ram_ext_R0_data[51:47];
+  assign io_deq_bits_addr = _ram_ext_R0_data[46:2];
+  assign io_deq_bits_retToSrc = _ram_ext_R0_data[1];
+  assign io_deq_bits_traceTag = _ram_ext_R0_data[0];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue2_PCrdGranted.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue2_PCrdGranted.sv
new file mode 100644
index 0000000000..3a63a3c33e
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue2_PCrdGranted.sv
@@ -0,0 +1,122 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue2_PCrdGranted(
+  input         clock,
+  input         reset,
+  output        io_enq_ready,
+  input         io_enq_valid,
+  input  [3:0]  io_enq_bits_pCrdType,
+  input  [10:0] io_enq_bits_srcID,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [3:0]  io_deq_bits_pCrdType,
+  output [10:0] io_deq_bits_srcID
+);
+
+  wire [14:0] _ram_ext_R0_data;
+  reg         enq_ptr_value;
+  reg         deq_ptr_value;
+  reg         maybe_full;
+  wire        ptr_match = enq_ptr_value == deq_ptr_value;
+  wire        empty = ptr_match & ~maybe_full;
+  wire        full = ptr_match & maybe_full;
+  wire        do_enq = ~full & io_enq_valid;
+  wire        do_deq = io_deq_ready & ~empty;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 1'h0;
+      deq_ptr_value <= 1'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 1'(enq_ptr_value - 1'h1);
+      if (do_deq)
+        deq_ptr_value <= 1'(deq_ptr_value - 1'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][1];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][2];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 1'h0;
+        deq_ptr_value = 1'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_2x15 ram_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data ({io_enq_bits_pCrdType, io_enq_bits_srcID})
+  );
+  assign io_enq_ready = ~full;
+  assign io_deq_valid = ~empty;
+  assign io_deq_bits_pCrdType = _ram_ext_R0_data[14:11];
+  assign io_deq_bits_srcID = _ram_ext_R0_data[10:0];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue30_PCrdGranted.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue30_PCrdGranted.sv
new file mode 100644
index 0000000000..6e960aad57
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue30_PCrdGranted.sv
@@ -0,0 +1,121 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue30_PCrdGranted(
+  input         clock,
+  input         reset,
+  input         io_enq_valid,
+  input  [3:0]  io_enq_bits_pCrdType,
+  input  [10:0] io_enq_bits_srcID,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [3:0]  io_deq_bits_pCrdType,
+  output [10:0] io_deq_bits_srcID
+);
+
+  wire        io_enq_ready;
+  wire [14:0] _ram_ext_R0_data;
+  reg  [4:0]  enq_ptr_value;
+  reg  [4:0]  deq_ptr_value;
+  reg         maybe_full;
+  wire        ptr_match = enq_ptr_value == deq_ptr_value;
+  wire        empty = ptr_match & ~maybe_full;
+  wire        do_enq = io_enq_ready & io_enq_valid;
+  assign io_enq_ready = ~(ptr_match & maybe_full);
+  wire        do_deq = io_deq_ready & ~empty;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 5'h0;
+      deq_ptr_value <= 5'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= enq_ptr_value == 5'h1D ? 5'h0 : 5'(enq_ptr_value + 5'h1);
+      if (do_deq)
+        deq_ptr_value <= deq_ptr_value == 5'h1D ? 5'h0 : 5'(deq_ptr_value + 5'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][4:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][9:5];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][10];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 5'h0;
+        deq_ptr_value = 5'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_30x15 ram_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data ({io_enq_bits_pCrdType, io_enq_bits_srcID})
+  );
+  assign io_deq_valid = ~empty;
+  assign io_deq_bits_pCrdType = _ram_ext_R0_data[14:11];
+  assign io_deq_bits_srcID = _ram_ext_R0_data[10:0];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Queue4_CHISNP.sv b/flow/designs/src/xiangshan_coupledl2/deps/Queue4_CHISNP.sv
new file mode 100644
index 0000000000..67bcc775fb
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Queue4_CHISNP.sv
@@ -0,0 +1,174 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Queue4_CHISNP(
+  input         clock,
+  input         reset,
+  input         io_enq_valid,
+  input  [3:0]  io_enq_bits_qos,
+  input  [10:0] io_enq_bits_srcID,
+  input  [11:0] io_enq_bits_txnID,
+  input  [10:0] io_enq_bits_fwdNID,
+  input  [11:0] io_enq_bits_fwdTxnID,
+  input  [4:0]  io_enq_bits_opcode,
+  input  [44:0] io_enq_bits_addr,
+  input         io_enq_bits_ns,
+  input         io_enq_bits_doNotGoToSD,
+  input         io_enq_bits_retToSrc,
+  input         io_enq_bits_traceTag,
+  input         io_enq_bits_mpam_perfMonGroup,
+  input  [8:0]  io_enq_bits_mpam_partID,
+  input         io_enq_bits_mpam_mpamNS,
+  input         io_deq_ready,
+  output        io_deq_valid,
+  output [3:0]  io_deq_bits_qos,
+  output [10:0] io_deq_bits_srcID,
+  output [11:0] io_deq_bits_txnID,
+  output [10:0] io_deq_bits_fwdNID,
+  output [11:0] io_deq_bits_fwdTxnID,
+  output [4:0]  io_deq_bits_opcode,
+  output [44:0] io_deq_bits_addr,
+  output        io_deq_bits_ns,
+  output        io_deq_bits_doNotGoToSD,
+  output        io_deq_bits_retToSrc,
+  output        io_deq_bits_traceTag,
+  output        io_deq_bits_mpam_perfMonGroup,
+  output [8:0]  io_deq_bits_mpam_partID,
+  output        io_deq_bits_mpam_mpamNS,
+  output [2:0]  io_count
+);
+
+  wire         io_enq_ready;
+  wire [114:0] _ram_ext_R0_data;
+  reg  [1:0]   enq_ptr_value;
+  reg  [1:0]   deq_ptr_value;
+  reg          maybe_full;
+  wire         ptr_match = enq_ptr_value == deq_ptr_value;
+  wire         empty = ptr_match & ~maybe_full;
+  wire         full = ptr_match & maybe_full;
+  wire         do_enq = io_enq_ready & io_enq_valid;
+  assign io_enq_ready = io_deq_ready | ~full;
+  wire         do_deq = io_deq_ready & ~empty;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      enq_ptr_value <= 2'h0;
+      deq_ptr_value <= 2'h0;
+      maybe_full <= 1'h0;
+    end
+    else begin
+      if (do_enq)
+        enq_ptr_value <= 2'(enq_ptr_value + 2'h1);
+      if (do_deq)
+        deq_ptr_value <= 2'(deq_ptr_value + 2'h1);
+      if (do_enq != do_deq)
+        maybe_full <= do_enq;
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        enq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][1:0];
+        deq_ptr_value = _RANDOM[/*Zero width*/ 1'b0][3:2];
+        maybe_full = _RANDOM[/*Zero width*/ 1'b0][4];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        enq_ptr_value = 2'h0;
+        deq_ptr_value = 2'h0;
+        maybe_full = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  ram_4x115 ram_ext (
+    .R0_addr (deq_ptr_value),
+    .R0_en   (1'h1),
+    .R0_clk  (clock),
+    .R0_data (_ram_ext_R0_data),
+    .W0_addr (enq_ptr_value),
+    .W0_en   (do_enq),
+    .W0_clk  (clock),
+    .W0_data
+      ({io_enq_bits_qos,
+        io_enq_bits_srcID,
+        io_enq_bits_txnID,
+        io_enq_bits_fwdNID,
+        io_enq_bits_fwdTxnID,
+        io_enq_bits_opcode,
+        io_enq_bits_addr,
+        io_enq_bits_ns,
+        io_enq_bits_doNotGoToSD,
+        io_enq_bits_retToSrc,
+        io_enq_bits_traceTag,
+        io_enq_bits_mpam_perfMonGroup,
+        io_enq_bits_mpam_partID,
+        io_enq_bits_mpam_mpamNS})
+  );
+  assign io_deq_valid = ~empty;
+  assign io_deq_bits_qos = _ram_ext_R0_data[114:111];
+  assign io_deq_bits_srcID = _ram_ext_R0_data[110:100];
+  assign io_deq_bits_txnID = _ram_ext_R0_data[99:88];
+  assign io_deq_bits_fwdNID = _ram_ext_R0_data[87:77];
+  assign io_deq_bits_fwdTxnID = _ram_ext_R0_data[76:65];
+  assign io_deq_bits_opcode = _ram_ext_R0_data[64:60];
+  assign io_deq_bits_addr = _ram_ext_R0_data[59:15];
+  assign io_deq_bits_ns = _ram_ext_R0_data[14];
+  assign io_deq_bits_doNotGoToSD = _ram_ext_R0_data[13];
+  assign io_deq_bits_retToSrc = _ram_ext_R0_data[12];
+  assign io_deq_bits_traceTag = _ram_ext_R0_data[11];
+  assign io_deq_bits_mpam_perfMonGroup = _ram_ext_R0_data[10];
+  assign io_deq_bits_mpam_partID = _ram_ext_R0_data[9:1];
+  assign io_deq_bits_mpam_mpamNS = _ram_ext_R0_data[0];
+  assign io_count = {full, 2'(enq_ptr_value - deq_ptr_value)};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/RXDAT.sv b/flow/designs/src/xiangshan_coupledl2/deps/RXDAT.sv
new file mode 100644
index 0000000000..ae97960c01
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/RXDAT.sv
@@ -0,0 +1,81 @@
+// Generated by CIRCT firtool-1.135.0
+module RXDAT(
+  input          io_out_valid,
+  input  [11:0]  io_out_bits_txnID,
+  input  [10:0]  io_out_bits_homeNID,
+  input  [3:0]   io_out_bits_opcode,
+  input  [1:0]   io_out_bits_respErr,
+  input  [2:0]   io_out_bits_resp,
+  input  [11:0]  io_out_bits_dbID,
+  input  [1:0]   io_out_bits_dataID,
+  input          io_out_bits_traceTag,
+  input  [255:0] io_out_bits_data,
+  input  [31:0]  io_out_bits_dataCheck,
+  input  [3:0]   io_out_bits_poison,
+  output         io_in_valid,
+  output [7:0]   io_in_mshrId,
+  output         io_in_respInfo_last,
+  output         io_in_respInfo_corrupt,
+  output [6:0]   io_in_respInfo_chiOpcode,
+  output [10:0]  io_in_respInfo_homeNID,
+  output [11:0]  io_in_respInfo_dbID,
+  output [2:0]   io_in_respInfo_resp,
+  output [1:0]   io_in_respInfo_respErr,
+  output         io_in_respInfo_traceTag,
+  output         io_refillBufWrite_valid,
+  output [7:0]   io_refillBufWrite_bits_id,
+  output [511:0] io_refillBufWrite_bits_data_data,
+  output [1:0]   io_refillBufWrite_bits_beatMask
+);
+
+  wire first = io_out_bits_dataID == 2'h0;
+  wire last = io_out_bits_dataID == 2'h2;
+  assign io_in_valid = (first | last) & io_out_valid;
+  assign io_in_mshrId = io_out_bits_txnID[7:0];
+  assign io_in_respInfo_last = last;
+  assign io_in_respInfo_corrupt =
+    |{io_out_bits_respErr == 2'h2 | (&io_out_bits_respErr) | io_out_bits_dataCheck[0]
+        ^ ~(^(io_out_bits_data[7:0])) | io_out_bits_dataCheck[1]
+        ^ ~(^(io_out_bits_data[15:8])) | io_out_bits_dataCheck[2]
+        ^ ~(^(io_out_bits_data[23:16])) | io_out_bits_dataCheck[3]
+        ^ ~(^(io_out_bits_data[31:24])) | io_out_bits_dataCheck[4]
+        ^ ~(^(io_out_bits_data[39:32])) | io_out_bits_dataCheck[5]
+        ^ ~(^(io_out_bits_data[47:40])) | io_out_bits_dataCheck[6]
+        ^ ~(^(io_out_bits_data[55:48])) | io_out_bits_dataCheck[7]
+        ^ ~(^(io_out_bits_data[63:56])) | io_out_bits_dataCheck[8]
+        ^ ~(^(io_out_bits_data[71:64])) | io_out_bits_dataCheck[9]
+        ^ ~(^(io_out_bits_data[79:72])) | io_out_bits_dataCheck[10]
+        ^ ~(^(io_out_bits_data[87:80])) | io_out_bits_dataCheck[11]
+        ^ ~(^(io_out_bits_data[95:88])) | io_out_bits_dataCheck[12]
+        ^ ~(^(io_out_bits_data[103:96])) | io_out_bits_dataCheck[13]
+        ^ ~(^(io_out_bits_data[111:104])) | io_out_bits_dataCheck[14]
+        ^ ~(^(io_out_bits_data[119:112])) | io_out_bits_dataCheck[15]
+        ^ ~(^(io_out_bits_data[127:120])) | io_out_bits_dataCheck[16]
+        ^ ~(^(io_out_bits_data[135:128])) | io_out_bits_dataCheck[17]
+        ^ ~(^(io_out_bits_data[143:136])) | io_out_bits_dataCheck[18]
+        ^ ~(^(io_out_bits_data[151:144])) | io_out_bits_dataCheck[19]
+        ^ ~(^(io_out_bits_data[159:152])) | io_out_bits_dataCheck[20]
+        ^ ~(^(io_out_bits_data[167:160])) | io_out_bits_dataCheck[21]
+        ^ ~(^(io_out_bits_data[175:168])) | io_out_bits_dataCheck[22]
+        ^ ~(^(io_out_bits_data[183:176])) | io_out_bits_dataCheck[23]
+        ^ ~(^(io_out_bits_data[191:184])) | io_out_bits_dataCheck[24]
+        ^ ~(^(io_out_bits_data[199:192])) | io_out_bits_dataCheck[25]
+        ^ ~(^(io_out_bits_data[207:200])) | io_out_bits_dataCheck[26]
+        ^ ~(^(io_out_bits_data[215:208])) | io_out_bits_dataCheck[27]
+        ^ ~(^(io_out_bits_data[223:216])) | io_out_bits_dataCheck[28]
+        ^ ~(^(io_out_bits_data[231:224])) | io_out_bits_dataCheck[29]
+        ^ ~(^(io_out_bits_data[239:232])) | io_out_bits_dataCheck[30]
+        ^ ~(^(io_out_bits_data[247:240])) | io_out_bits_dataCheck[31]
+        ^ ~(^(io_out_bits_data[255:248])),
+      io_out_bits_poison};
+  assign io_in_respInfo_chiOpcode = {3'h0, io_out_bits_opcode};
+  assign io_in_respInfo_homeNID = io_out_bits_homeNID;
+  assign io_in_respInfo_dbID = io_out_bits_dbID;
+  assign io_in_respInfo_resp = io_out_bits_resp;
+  assign io_in_respInfo_respErr = io_out_bits_respErr;
+  assign io_in_respInfo_traceTag = io_out_bits_traceTag;
+  assign io_refillBufWrite_valid = io_out_valid;
+  assign io_refillBufWrite_bits_id = io_out_bits_txnID[7:0];
+  assign io_refillBufWrite_bits_data_data = {2{io_out_bits_data}};
+  assign io_refillBufWrite_bits_beatMask = {last, first};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/RXRSP.sv b/flow/designs/src/xiangshan_coupledl2/deps/RXRSP.sv
new file mode 100644
index 0000000000..677f6b1c73
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/RXRSP.sv
@@ -0,0 +1,32 @@
+// Generated by CIRCT firtool-1.135.0
+module RXRSP(
+  input         io_out_valid,
+  input  [10:0] io_out_bits_srcID,
+  input  [11:0] io_out_bits_txnID,
+  input  [4:0]  io_out_bits_opcode,
+  input  [1:0]  io_out_bits_respErr,
+  input  [2:0]  io_out_bits_resp,
+  input  [11:0] io_out_bits_dbID,
+  input  [3:0]  io_out_bits_pCrdType,
+  input         io_out_bits_traceTag,
+  output        io_in_valid,
+  output [7:0]  io_in_mshrId,
+  output [6:0]  io_in_respInfo_chiOpcode,
+  output [10:0] io_in_respInfo_srcID,
+  output [11:0] io_in_respInfo_dbID,
+  output [2:0]  io_in_respInfo_resp,
+  output [3:0]  io_in_respInfo_pCrdType,
+  output [1:0]  io_in_respInfo_respErr,
+  output        io_in_respInfo_traceTag
+);
+
+  assign io_in_valid = io_out_valid;
+  assign io_in_mshrId = io_out_bits_txnID[7:0];
+  assign io_in_respInfo_chiOpcode = {2'h0, io_out_bits_opcode};
+  assign io_in_respInfo_srcID = io_out_bits_srcID;
+  assign io_in_respInfo_dbID = io_out_bits_dbID;
+  assign io_in_respInfo_resp = io_out_bits_resp;
+  assign io_in_respInfo_pCrdType = io_out_bits_pCrdType;
+  assign io_in_respInfo_respErr = io_out_bits_respErr;
+  assign io_in_respInfo_traceTag = io_out_bits_traceTag;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/RXSNP.sv b/flow/designs/src/xiangshan_coupledl2/deps/RXSNP.sv
new file mode 100644
index 0000000000..2c25de4562
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/RXSNP.sv
@@ -0,0 +1,1262 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module RXSNP(
+  input         clock,
+  input         reset,
+  output        io_rxsnp_ready,
+  input         io_rxsnp_valid,
+  input  [3:0]  io_rxsnp_bits_qos,
+  input  [10:0] io_rxsnp_bits_srcID,
+  input  [11:0] io_rxsnp_bits_txnID,
+  input  [10:0] io_rxsnp_bits_fwdNID,
+  input  [11:0] io_rxsnp_bits_fwdTxnID,
+  input  [4:0]  io_rxsnp_bits_opcode,
+  input  [44:0] io_rxsnp_bits_addr,
+  input         io_rxsnp_bits_ns,
+  input         io_rxsnp_bits_doNotGoToSD,
+  input         io_rxsnp_bits_retToSrc,
+  input         io_rxsnp_bits_traceTag,
+  input         io_rxsnp_bits_mpam_perfMonGroup,
+  input  [8:0]  io_rxsnp_bits_mpam_partID,
+  input         io_rxsnp_bits_mpam_mpamNS,
+  input         io_task_ready,
+  output        io_task_valid,
+  output [7:0]  io_task_bits_set,
+  output [33:0] io_task_bits_tag,
+  output [5:0]  io_task_bits_off,
+  output        io_task_bits_snpHitRelease,
+  output        io_task_bits_snpHitReleaseToInval,
+  output        io_task_bits_snpHitReleaseToClean,
+  output        io_task_bits_snpHitReleaseWithData,
+  output [7:0]  io_task_bits_snpHitReleaseIdx,
+  output        io_task_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_task_bits_snpHitReleaseMeta_state,
+  output        io_task_bits_snpHitReleaseMeta_clients,
+  output        io_task_bits_snpHitReleaseMeta_alias,
+  output        io_task_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_task_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_task_bits_snpHitReleaseMeta_accessed,
+  output        io_task_bits_snpHitReleaseMeta_tagErr,
+  output        io_task_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_task_bits_srcID,
+  output [11:0] io_task_bits_txnID,
+  output [10:0] io_task_bits_fwdNID,
+  output [11:0] io_task_bits_fwdTxnID,
+  output [6:0]  io_task_bits_chiOpcode,
+  output        io_task_bits_retToSrc,
+  output        io_task_bits_traceTag,
+  input         io_msInfo_0_valid,
+  input  [7:0]  io_msInfo_0_bits_set,
+  input  [33:0] io_msInfo_0_bits_reqTag,
+  input         io_msInfo_0_bits_willFree,
+  input         io_msInfo_0_bits_aliasTask,
+  input         io_msInfo_0_bits_blockRefill,
+  input         io_msInfo_0_bits_meta_dirty,
+  input  [1:0]  io_msInfo_0_bits_meta_state,
+  input         io_msInfo_0_bits_meta_clients,
+  input         io_msInfo_0_bits_meta_alias,
+  input         io_msInfo_0_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_0_bits_meta_prefetchSrc,
+  input         io_msInfo_0_bits_meta_accessed,
+  input         io_msInfo_0_bits_meta_tagErr,
+  input         io_msInfo_0_bits_meta_dataErr,
+  input  [33:0] io_msInfo_0_bits_metaTag,
+  input         io_msInfo_0_bits_dirHit,
+  input         io_msInfo_0_bits_w_grantfirst,
+  input         io_msInfo_0_bits_s_release,
+  input         io_msInfo_0_bits_s_cmoresp,
+  input         io_msInfo_0_bits_s_cmometaw,
+  input         io_msInfo_0_bits_w_releaseack,
+  input         io_msInfo_0_bits_w_replResp,
+  input         io_msInfo_0_bits_w_rprobeacklast,
+  input         io_msInfo_0_bits_replaceData,
+  input         io_msInfo_0_bits_releaseToClean,
+  input         io_msInfo_1_valid,
+  input  [7:0]  io_msInfo_1_bits_set,
+  input  [33:0] io_msInfo_1_bits_reqTag,
+  input         io_msInfo_1_bits_willFree,
+  input         io_msInfo_1_bits_aliasTask,
+  input         io_msInfo_1_bits_blockRefill,
+  input         io_msInfo_1_bits_meta_dirty,
+  input  [1:0]  io_msInfo_1_bits_meta_state,
+  input         io_msInfo_1_bits_meta_clients,
+  input         io_msInfo_1_bits_meta_alias,
+  input         io_msInfo_1_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_1_bits_meta_prefetchSrc,
+  input         io_msInfo_1_bits_meta_accessed,
+  input         io_msInfo_1_bits_meta_tagErr,
+  input         io_msInfo_1_bits_meta_dataErr,
+  input  [33:0] io_msInfo_1_bits_metaTag,
+  input         io_msInfo_1_bits_dirHit,
+  input         io_msInfo_1_bits_w_grantfirst,
+  input         io_msInfo_1_bits_s_release,
+  input         io_msInfo_1_bits_s_cmoresp,
+  input         io_msInfo_1_bits_s_cmometaw,
+  input         io_msInfo_1_bits_w_releaseack,
+  input         io_msInfo_1_bits_w_replResp,
+  input         io_msInfo_1_bits_w_rprobeacklast,
+  input         io_msInfo_1_bits_replaceData,
+  input         io_msInfo_1_bits_releaseToClean,
+  input         io_msInfo_2_valid,
+  input  [7:0]  io_msInfo_2_bits_set,
+  input  [33:0] io_msInfo_2_bits_reqTag,
+  input         io_msInfo_2_bits_willFree,
+  input         io_msInfo_2_bits_aliasTask,
+  input         io_msInfo_2_bits_blockRefill,
+  input         io_msInfo_2_bits_meta_dirty,
+  input  [1:0]  io_msInfo_2_bits_meta_state,
+  input         io_msInfo_2_bits_meta_clients,
+  input         io_msInfo_2_bits_meta_alias,
+  input         io_msInfo_2_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_2_bits_meta_prefetchSrc,
+  input         io_msInfo_2_bits_meta_accessed,
+  input         io_msInfo_2_bits_meta_tagErr,
+  input         io_msInfo_2_bits_meta_dataErr,
+  input  [33:0] io_msInfo_2_bits_metaTag,
+  input         io_msInfo_2_bits_dirHit,
+  input         io_msInfo_2_bits_w_grantfirst,
+  input         io_msInfo_2_bits_s_release,
+  input         io_msInfo_2_bits_s_cmoresp,
+  input         io_msInfo_2_bits_s_cmometaw,
+  input         io_msInfo_2_bits_w_releaseack,
+  input         io_msInfo_2_bits_w_replResp,
+  input         io_msInfo_2_bits_w_rprobeacklast,
+  input         io_msInfo_2_bits_replaceData,
+  input         io_msInfo_2_bits_releaseToClean,
+  input         io_msInfo_3_valid,
+  input  [7:0]  io_msInfo_3_bits_set,
+  input  [33:0] io_msInfo_3_bits_reqTag,
+  input         io_msInfo_3_bits_willFree,
+  input         io_msInfo_3_bits_aliasTask,
+  input         io_msInfo_3_bits_blockRefill,
+  input         io_msInfo_3_bits_meta_dirty,
+  input  [1:0]  io_msInfo_3_bits_meta_state,
+  input         io_msInfo_3_bits_meta_clients,
+  input         io_msInfo_3_bits_meta_alias,
+  input         io_msInfo_3_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_3_bits_meta_prefetchSrc,
+  input         io_msInfo_3_bits_meta_accessed,
+  input         io_msInfo_3_bits_meta_tagErr,
+  input         io_msInfo_3_bits_meta_dataErr,
+  input  [33:0] io_msInfo_3_bits_metaTag,
+  input         io_msInfo_3_bits_dirHit,
+  input         io_msInfo_3_bits_w_grantfirst,
+  input         io_msInfo_3_bits_s_release,
+  input         io_msInfo_3_bits_s_cmoresp,
+  input         io_msInfo_3_bits_s_cmometaw,
+  input         io_msInfo_3_bits_w_releaseack,
+  input         io_msInfo_3_bits_w_replResp,
+  input         io_msInfo_3_bits_w_rprobeacklast,
+  input         io_msInfo_3_bits_replaceData,
+  input         io_msInfo_3_bits_releaseToClean,
+  input         io_msInfo_4_valid,
+  input  [7:0]  io_msInfo_4_bits_set,
+  input  [33:0] io_msInfo_4_bits_reqTag,
+  input         io_msInfo_4_bits_willFree,
+  input         io_msInfo_4_bits_aliasTask,
+  input         io_msInfo_4_bits_blockRefill,
+  input         io_msInfo_4_bits_meta_dirty,
+  input  [1:0]  io_msInfo_4_bits_meta_state,
+  input         io_msInfo_4_bits_meta_clients,
+  input         io_msInfo_4_bits_meta_alias,
+  input         io_msInfo_4_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_4_bits_meta_prefetchSrc,
+  input         io_msInfo_4_bits_meta_accessed,
+  input         io_msInfo_4_bits_meta_tagErr,
+  input         io_msInfo_4_bits_meta_dataErr,
+  input  [33:0] io_msInfo_4_bits_metaTag,
+  input         io_msInfo_4_bits_dirHit,
+  input         io_msInfo_4_bits_w_grantfirst,
+  input         io_msInfo_4_bits_s_release,
+  input         io_msInfo_4_bits_s_cmoresp,
+  input         io_msInfo_4_bits_s_cmometaw,
+  input         io_msInfo_4_bits_w_releaseack,
+  input         io_msInfo_4_bits_w_replResp,
+  input         io_msInfo_4_bits_w_rprobeacklast,
+  input         io_msInfo_4_bits_replaceData,
+  input         io_msInfo_4_bits_releaseToClean,
+  input         io_msInfo_5_valid,
+  input  [7:0]  io_msInfo_5_bits_set,
+  input  [33:0] io_msInfo_5_bits_reqTag,
+  input         io_msInfo_5_bits_willFree,
+  input         io_msInfo_5_bits_aliasTask,
+  input         io_msInfo_5_bits_blockRefill,
+  input         io_msInfo_5_bits_meta_dirty,
+  input  [1:0]  io_msInfo_5_bits_meta_state,
+  input         io_msInfo_5_bits_meta_clients,
+  input         io_msInfo_5_bits_meta_alias,
+  input         io_msInfo_5_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_5_bits_meta_prefetchSrc,
+  input         io_msInfo_5_bits_meta_accessed,
+  input         io_msInfo_5_bits_meta_tagErr,
+  input         io_msInfo_5_bits_meta_dataErr,
+  input  [33:0] io_msInfo_5_bits_metaTag,
+  input         io_msInfo_5_bits_dirHit,
+  input         io_msInfo_5_bits_w_grantfirst,
+  input         io_msInfo_5_bits_s_release,
+  input         io_msInfo_5_bits_s_cmoresp,
+  input         io_msInfo_5_bits_s_cmometaw,
+  input         io_msInfo_5_bits_w_releaseack,
+  input         io_msInfo_5_bits_w_replResp,
+  input         io_msInfo_5_bits_w_rprobeacklast,
+  input         io_msInfo_5_bits_replaceData,
+  input         io_msInfo_5_bits_releaseToClean,
+  input         io_msInfo_6_valid,
+  input  [7:0]  io_msInfo_6_bits_set,
+  input  [33:0] io_msInfo_6_bits_reqTag,
+  input         io_msInfo_6_bits_willFree,
+  input         io_msInfo_6_bits_aliasTask,
+  input         io_msInfo_6_bits_blockRefill,
+  input         io_msInfo_6_bits_meta_dirty,
+  input  [1:0]  io_msInfo_6_bits_meta_state,
+  input         io_msInfo_6_bits_meta_clients,
+  input         io_msInfo_6_bits_meta_alias,
+  input         io_msInfo_6_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_6_bits_meta_prefetchSrc,
+  input         io_msInfo_6_bits_meta_accessed,
+  input         io_msInfo_6_bits_meta_tagErr,
+  input         io_msInfo_6_bits_meta_dataErr,
+  input  [33:0] io_msInfo_6_bits_metaTag,
+  input         io_msInfo_6_bits_dirHit,
+  input         io_msInfo_6_bits_w_grantfirst,
+  input         io_msInfo_6_bits_s_release,
+  input         io_msInfo_6_bits_s_cmoresp,
+  input         io_msInfo_6_bits_s_cmometaw,
+  input         io_msInfo_6_bits_w_releaseack,
+  input         io_msInfo_6_bits_w_replResp,
+  input         io_msInfo_6_bits_w_rprobeacklast,
+  input         io_msInfo_6_bits_replaceData,
+  input         io_msInfo_6_bits_releaseToClean,
+  input         io_msInfo_7_valid,
+  input  [7:0]  io_msInfo_7_bits_set,
+  input  [33:0] io_msInfo_7_bits_reqTag,
+  input         io_msInfo_7_bits_willFree,
+  input         io_msInfo_7_bits_aliasTask,
+  input         io_msInfo_7_bits_blockRefill,
+  input         io_msInfo_7_bits_meta_dirty,
+  input  [1:0]  io_msInfo_7_bits_meta_state,
+  input         io_msInfo_7_bits_meta_clients,
+  input         io_msInfo_7_bits_meta_alias,
+  input         io_msInfo_7_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_7_bits_meta_prefetchSrc,
+  input         io_msInfo_7_bits_meta_accessed,
+  input         io_msInfo_7_bits_meta_tagErr,
+  input         io_msInfo_7_bits_meta_dataErr,
+  input  [33:0] io_msInfo_7_bits_metaTag,
+  input         io_msInfo_7_bits_dirHit,
+  input         io_msInfo_7_bits_w_grantfirst,
+  input         io_msInfo_7_bits_s_release,
+  input         io_msInfo_7_bits_s_cmoresp,
+  input         io_msInfo_7_bits_s_cmometaw,
+  input         io_msInfo_7_bits_w_releaseack,
+  input         io_msInfo_7_bits_w_replResp,
+  input         io_msInfo_7_bits_w_rprobeacklast,
+  input         io_msInfo_7_bits_replaceData,
+  input         io_msInfo_7_bits_releaseToClean,
+  input         io_msInfo_8_valid,
+  input  [7:0]  io_msInfo_8_bits_set,
+  input  [33:0] io_msInfo_8_bits_reqTag,
+  input         io_msInfo_8_bits_willFree,
+  input         io_msInfo_8_bits_aliasTask,
+  input         io_msInfo_8_bits_blockRefill,
+  input         io_msInfo_8_bits_meta_dirty,
+  input  [1:0]  io_msInfo_8_bits_meta_state,
+  input         io_msInfo_8_bits_meta_clients,
+  input         io_msInfo_8_bits_meta_alias,
+  input         io_msInfo_8_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_8_bits_meta_prefetchSrc,
+  input         io_msInfo_8_bits_meta_accessed,
+  input         io_msInfo_8_bits_meta_tagErr,
+  input         io_msInfo_8_bits_meta_dataErr,
+  input  [33:0] io_msInfo_8_bits_metaTag,
+  input         io_msInfo_8_bits_dirHit,
+  input         io_msInfo_8_bits_w_grantfirst,
+  input         io_msInfo_8_bits_s_release,
+  input         io_msInfo_8_bits_s_cmoresp,
+  input         io_msInfo_8_bits_s_cmometaw,
+  input         io_msInfo_8_bits_w_releaseack,
+  input         io_msInfo_8_bits_w_replResp,
+  input         io_msInfo_8_bits_w_rprobeacklast,
+  input         io_msInfo_8_bits_replaceData,
+  input         io_msInfo_8_bits_releaseToClean,
+  input         io_msInfo_9_valid,
+  input  [7:0]  io_msInfo_9_bits_set,
+  input  [33:0] io_msInfo_9_bits_reqTag,
+  input         io_msInfo_9_bits_willFree,
+  input         io_msInfo_9_bits_aliasTask,
+  input         io_msInfo_9_bits_blockRefill,
+  input         io_msInfo_9_bits_meta_dirty,
+  input  [1:0]  io_msInfo_9_bits_meta_state,
+  input         io_msInfo_9_bits_meta_clients,
+  input         io_msInfo_9_bits_meta_alias,
+  input         io_msInfo_9_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_9_bits_meta_prefetchSrc,
+  input         io_msInfo_9_bits_meta_accessed,
+  input         io_msInfo_9_bits_meta_tagErr,
+  input         io_msInfo_9_bits_meta_dataErr,
+  input  [33:0] io_msInfo_9_bits_metaTag,
+  input         io_msInfo_9_bits_dirHit,
+  input         io_msInfo_9_bits_w_grantfirst,
+  input         io_msInfo_9_bits_s_release,
+  input         io_msInfo_9_bits_s_cmoresp,
+  input         io_msInfo_9_bits_s_cmometaw,
+  input         io_msInfo_9_bits_w_releaseack,
+  input         io_msInfo_9_bits_w_replResp,
+  input         io_msInfo_9_bits_w_rprobeacklast,
+  input         io_msInfo_9_bits_replaceData,
+  input         io_msInfo_9_bits_releaseToClean,
+  input         io_msInfo_10_valid,
+  input  [7:0]  io_msInfo_10_bits_set,
+  input  [33:0] io_msInfo_10_bits_reqTag,
+  input         io_msInfo_10_bits_willFree,
+  input         io_msInfo_10_bits_aliasTask,
+  input         io_msInfo_10_bits_blockRefill,
+  input         io_msInfo_10_bits_meta_dirty,
+  input  [1:0]  io_msInfo_10_bits_meta_state,
+  input         io_msInfo_10_bits_meta_clients,
+  input         io_msInfo_10_bits_meta_alias,
+  input         io_msInfo_10_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_10_bits_meta_prefetchSrc,
+  input         io_msInfo_10_bits_meta_accessed,
+  input         io_msInfo_10_bits_meta_tagErr,
+  input         io_msInfo_10_bits_meta_dataErr,
+  input  [33:0] io_msInfo_10_bits_metaTag,
+  input         io_msInfo_10_bits_dirHit,
+  input         io_msInfo_10_bits_w_grantfirst,
+  input         io_msInfo_10_bits_s_release,
+  input         io_msInfo_10_bits_s_cmoresp,
+  input         io_msInfo_10_bits_s_cmometaw,
+  input         io_msInfo_10_bits_w_releaseack,
+  input         io_msInfo_10_bits_w_replResp,
+  input         io_msInfo_10_bits_w_rprobeacklast,
+  input         io_msInfo_10_bits_replaceData,
+  input         io_msInfo_10_bits_releaseToClean,
+  input         io_msInfo_11_valid,
+  input  [7:0]  io_msInfo_11_bits_set,
+  input  [33:0] io_msInfo_11_bits_reqTag,
+  input         io_msInfo_11_bits_willFree,
+  input         io_msInfo_11_bits_aliasTask,
+  input         io_msInfo_11_bits_blockRefill,
+  input         io_msInfo_11_bits_meta_dirty,
+  input  [1:0]  io_msInfo_11_bits_meta_state,
+  input         io_msInfo_11_bits_meta_clients,
+  input         io_msInfo_11_bits_meta_alias,
+  input         io_msInfo_11_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_11_bits_meta_prefetchSrc,
+  input         io_msInfo_11_bits_meta_accessed,
+  input         io_msInfo_11_bits_meta_tagErr,
+  input         io_msInfo_11_bits_meta_dataErr,
+  input  [33:0] io_msInfo_11_bits_metaTag,
+  input         io_msInfo_11_bits_dirHit,
+  input         io_msInfo_11_bits_w_grantfirst,
+  input         io_msInfo_11_bits_s_release,
+  input         io_msInfo_11_bits_s_cmoresp,
+  input         io_msInfo_11_bits_s_cmometaw,
+  input         io_msInfo_11_bits_w_releaseack,
+  input         io_msInfo_11_bits_w_replResp,
+  input         io_msInfo_11_bits_w_rprobeacklast,
+  input         io_msInfo_11_bits_replaceData,
+  input         io_msInfo_11_bits_releaseToClean,
+  input         io_msInfo_12_valid,
+  input  [7:0]  io_msInfo_12_bits_set,
+  input  [33:0] io_msInfo_12_bits_reqTag,
+  input         io_msInfo_12_bits_willFree,
+  input         io_msInfo_12_bits_aliasTask,
+  input         io_msInfo_12_bits_blockRefill,
+  input         io_msInfo_12_bits_meta_dirty,
+  input  [1:0]  io_msInfo_12_bits_meta_state,
+  input         io_msInfo_12_bits_meta_clients,
+  input         io_msInfo_12_bits_meta_alias,
+  input         io_msInfo_12_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_12_bits_meta_prefetchSrc,
+  input         io_msInfo_12_bits_meta_accessed,
+  input         io_msInfo_12_bits_meta_tagErr,
+  input         io_msInfo_12_bits_meta_dataErr,
+  input  [33:0] io_msInfo_12_bits_metaTag,
+  input         io_msInfo_12_bits_dirHit,
+  input         io_msInfo_12_bits_w_grantfirst,
+  input         io_msInfo_12_bits_s_release,
+  input         io_msInfo_12_bits_s_cmoresp,
+  input         io_msInfo_12_bits_s_cmometaw,
+  input         io_msInfo_12_bits_w_releaseack,
+  input         io_msInfo_12_bits_w_replResp,
+  input         io_msInfo_12_bits_w_rprobeacklast,
+  input         io_msInfo_12_bits_replaceData,
+  input         io_msInfo_12_bits_releaseToClean,
+  input         io_msInfo_13_valid,
+  input  [7:0]  io_msInfo_13_bits_set,
+  input  [33:0] io_msInfo_13_bits_reqTag,
+  input         io_msInfo_13_bits_willFree,
+  input         io_msInfo_13_bits_aliasTask,
+  input         io_msInfo_13_bits_blockRefill,
+  input         io_msInfo_13_bits_meta_dirty,
+  input  [1:0]  io_msInfo_13_bits_meta_state,
+  input         io_msInfo_13_bits_meta_clients,
+  input         io_msInfo_13_bits_meta_alias,
+  input         io_msInfo_13_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_13_bits_meta_prefetchSrc,
+  input         io_msInfo_13_bits_meta_accessed,
+  input         io_msInfo_13_bits_meta_tagErr,
+  input         io_msInfo_13_bits_meta_dataErr,
+  input  [33:0] io_msInfo_13_bits_metaTag,
+  input         io_msInfo_13_bits_dirHit,
+  input         io_msInfo_13_bits_w_grantfirst,
+  input         io_msInfo_13_bits_s_release,
+  input         io_msInfo_13_bits_s_cmoresp,
+  input         io_msInfo_13_bits_s_cmometaw,
+  input         io_msInfo_13_bits_w_releaseack,
+  input         io_msInfo_13_bits_w_replResp,
+  input         io_msInfo_13_bits_w_rprobeacklast,
+  input         io_msInfo_13_bits_replaceData,
+  input         io_msInfo_13_bits_releaseToClean,
+  input         io_msInfo_14_valid,
+  input  [7:0]  io_msInfo_14_bits_set,
+  input  [33:0] io_msInfo_14_bits_reqTag,
+  input         io_msInfo_14_bits_willFree,
+  input         io_msInfo_14_bits_aliasTask,
+  input         io_msInfo_14_bits_blockRefill,
+  input         io_msInfo_14_bits_meta_dirty,
+  input  [1:0]  io_msInfo_14_bits_meta_state,
+  input         io_msInfo_14_bits_meta_clients,
+  input         io_msInfo_14_bits_meta_alias,
+  input         io_msInfo_14_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_14_bits_meta_prefetchSrc,
+  input         io_msInfo_14_bits_meta_accessed,
+  input         io_msInfo_14_bits_meta_tagErr,
+  input         io_msInfo_14_bits_meta_dataErr,
+  input  [33:0] io_msInfo_14_bits_metaTag,
+  input         io_msInfo_14_bits_dirHit,
+  input         io_msInfo_14_bits_w_grantfirst,
+  input         io_msInfo_14_bits_s_release,
+  input         io_msInfo_14_bits_s_cmoresp,
+  input         io_msInfo_14_bits_s_cmometaw,
+  input         io_msInfo_14_bits_w_releaseack,
+  input         io_msInfo_14_bits_w_replResp,
+  input         io_msInfo_14_bits_w_rprobeacklast,
+  input         io_msInfo_14_bits_replaceData,
+  input         io_msInfo_14_bits_releaseToClean,
+  input         io_msInfo_15_valid,
+  input  [7:0]  io_msInfo_15_bits_set,
+  input  [33:0] io_msInfo_15_bits_reqTag,
+  input         io_msInfo_15_bits_willFree,
+  input         io_msInfo_15_bits_aliasTask,
+  input         io_msInfo_15_bits_blockRefill,
+  input         io_msInfo_15_bits_meta_dirty,
+  input  [1:0]  io_msInfo_15_bits_meta_state,
+  input         io_msInfo_15_bits_meta_clients,
+  input         io_msInfo_15_bits_meta_alias,
+  input         io_msInfo_15_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_15_bits_meta_prefetchSrc,
+  input         io_msInfo_15_bits_meta_accessed,
+  input         io_msInfo_15_bits_meta_tagErr,
+  input         io_msInfo_15_bits_meta_dataErr,
+  input  [33:0] io_msInfo_15_bits_metaTag,
+  input         io_msInfo_15_bits_dirHit,
+  input         io_msInfo_15_bits_w_grantfirst,
+  input         io_msInfo_15_bits_s_release,
+  input         io_msInfo_15_bits_s_cmoresp,
+  input         io_msInfo_15_bits_s_cmometaw,
+  input         io_msInfo_15_bits_w_releaseack,
+  input         io_msInfo_15_bits_w_replResp,
+  input         io_msInfo_15_bits_w_rprobeacklast,
+  input         io_msInfo_15_bits_replaceData,
+  input         io_msInfo_15_bits_releaseToClean
+);
+
+  wire [7:0]  task_set;
+  wire [33:0] task_tag;
+  wire        _queue_io_deq_valid;
+  wire [4:0]  _queue_io_deq_bits_opcode;
+  wire [44:0] _queue_io_deq_bits_addr;
+  wire        _replaceNestSnpMask_T = io_msInfo_0_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_14 = io_msInfo_1_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_28 = io_msInfo_2_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_42 = io_msInfo_3_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_56 = io_msInfo_4_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_70 = io_msInfo_5_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_84 = io_msInfo_6_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_98 = io_msInfo_7_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_112 = io_msInfo_8_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_126 = io_msInfo_9_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_140 = io_msInfo_10_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_154 = io_msInfo_11_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_168 = io_msInfo_12_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_182 = io_msInfo_13_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_196 = io_msInfo_14_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_210 = io_msInfo_15_bits_set == task_set;
+  wire        _replaceNestSnpMask_T_2 = io_msInfo_0_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG;
+  wire        _replaceNestSnpMask_T_16 = io_msInfo_1_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_1;
+  wire        _replaceNestSnpMask_T_30 = io_msInfo_2_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_2;
+  wire        _replaceNestSnpMask_T_44 = io_msInfo_3_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_3;
+  wire        _replaceNestSnpMask_T_58 = io_msInfo_4_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_4;
+  wire        _replaceNestSnpMask_T_72 = io_msInfo_5_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_5;
+  wire        _replaceNestSnpMask_T_86 = io_msInfo_6_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_6;
+  wire        _replaceNestSnpMask_T_100 = io_msInfo_7_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_7;
+  wire        _replaceNestSnpMask_T_114 = io_msInfo_8_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_8;
+  wire        _replaceNestSnpMask_T_128 = io_msInfo_9_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_9;
+  wire        _replaceNestSnpMask_T_142 = io_msInfo_10_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_10;
+  wire        _replaceNestSnpMask_T_156 = io_msInfo_11_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_11;
+  wire        _replaceNestSnpMask_T_170 = io_msInfo_12_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_12;
+  wire        _replaceNestSnpMask_T_184 = io_msInfo_13_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_13;
+  wire        _replaceNestSnpMask_T_198 = io_msInfo_14_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_14;
+  wire        _replaceNestSnpMask_T_212 = io_msInfo_15_bits_metaTag == task_tag;
+  reg         replaceBlockSnpMask_REG_15;
+  reg         replaceNestSnpMask_REG;
+  wire        _task_task_snpHitReleaseIdx_T =
+    io_msInfo_0_valid & _replaceNestSnpMask_T & _replaceNestSnpMask_T_2
+    & (~io_msInfo_0_bits_dirHit | ~io_msInfo_0_bits_s_cmoresp)
+    & (|io_msInfo_0_bits_meta_state) & replaceNestSnpMask_REG
+    & io_msInfo_0_bits_w_rprobeacklast & ~io_msInfo_0_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_1;
+  wire        _task_task_snpHitReleaseIdx_T_1 =
+    io_msInfo_1_valid & _replaceNestSnpMask_T_14 & _replaceNestSnpMask_T_16
+    & (~io_msInfo_1_bits_dirHit | ~io_msInfo_1_bits_s_cmoresp)
+    & (|io_msInfo_1_bits_meta_state) & replaceNestSnpMask_REG_1
+    & io_msInfo_1_bits_w_rprobeacklast & ~io_msInfo_1_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_2;
+  wire        _task_task_snpHitReleaseIdx_T_2 =
+    io_msInfo_2_valid & _replaceNestSnpMask_T_28 & _replaceNestSnpMask_T_30
+    & (~io_msInfo_2_bits_dirHit | ~io_msInfo_2_bits_s_cmoresp)
+    & (|io_msInfo_2_bits_meta_state) & replaceNestSnpMask_REG_2
+    & io_msInfo_2_bits_w_rprobeacklast & ~io_msInfo_2_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_3;
+  wire        _task_task_snpHitReleaseIdx_T_3 =
+    io_msInfo_3_valid & _replaceNestSnpMask_T_42 & _replaceNestSnpMask_T_44
+    & (~io_msInfo_3_bits_dirHit | ~io_msInfo_3_bits_s_cmoresp)
+    & (|io_msInfo_3_bits_meta_state) & replaceNestSnpMask_REG_3
+    & io_msInfo_3_bits_w_rprobeacklast & ~io_msInfo_3_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_4;
+  wire        _task_task_snpHitReleaseIdx_T_4 =
+    io_msInfo_4_valid & _replaceNestSnpMask_T_56 & _replaceNestSnpMask_T_58
+    & (~io_msInfo_4_bits_dirHit | ~io_msInfo_4_bits_s_cmoresp)
+    & (|io_msInfo_4_bits_meta_state) & replaceNestSnpMask_REG_4
+    & io_msInfo_4_bits_w_rprobeacklast & ~io_msInfo_4_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_5;
+  wire        _task_task_snpHitReleaseIdx_T_5 =
+    io_msInfo_5_valid & _replaceNestSnpMask_T_70 & _replaceNestSnpMask_T_72
+    & (~io_msInfo_5_bits_dirHit | ~io_msInfo_5_bits_s_cmoresp)
+    & (|io_msInfo_5_bits_meta_state) & replaceNestSnpMask_REG_5
+    & io_msInfo_5_bits_w_rprobeacklast & ~io_msInfo_5_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_6;
+  wire        _task_task_snpHitReleaseIdx_T_6 =
+    io_msInfo_6_valid & _replaceNestSnpMask_T_84 & _replaceNestSnpMask_T_86
+    & (~io_msInfo_6_bits_dirHit | ~io_msInfo_6_bits_s_cmoresp)
+    & (|io_msInfo_6_bits_meta_state) & replaceNestSnpMask_REG_6
+    & io_msInfo_6_bits_w_rprobeacklast & ~io_msInfo_6_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_7;
+  wire        _task_task_snpHitReleaseIdx_T_7 =
+    io_msInfo_7_valid & _replaceNestSnpMask_T_98 & _replaceNestSnpMask_T_100
+    & (~io_msInfo_7_bits_dirHit | ~io_msInfo_7_bits_s_cmoresp)
+    & (|io_msInfo_7_bits_meta_state) & replaceNestSnpMask_REG_7
+    & io_msInfo_7_bits_w_rprobeacklast & ~io_msInfo_7_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_8;
+  wire        _task_task_snpHitReleaseIdx_T_8 =
+    io_msInfo_8_valid & _replaceNestSnpMask_T_112 & _replaceNestSnpMask_T_114
+    & (~io_msInfo_8_bits_dirHit | ~io_msInfo_8_bits_s_cmoresp)
+    & (|io_msInfo_8_bits_meta_state) & replaceNestSnpMask_REG_8
+    & io_msInfo_8_bits_w_rprobeacklast & ~io_msInfo_8_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_9;
+  wire        _task_task_snpHitReleaseIdx_T_9 =
+    io_msInfo_9_valid & _replaceNestSnpMask_T_126 & _replaceNestSnpMask_T_128
+    & (~io_msInfo_9_bits_dirHit | ~io_msInfo_9_bits_s_cmoresp)
+    & (|io_msInfo_9_bits_meta_state) & replaceNestSnpMask_REG_9
+    & io_msInfo_9_bits_w_rprobeacklast & ~io_msInfo_9_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_10;
+  wire        _task_task_snpHitReleaseIdx_T_10 =
+    io_msInfo_10_valid & _replaceNestSnpMask_T_140 & _replaceNestSnpMask_T_142
+    & (~io_msInfo_10_bits_dirHit | ~io_msInfo_10_bits_s_cmoresp)
+    & (|io_msInfo_10_bits_meta_state) & replaceNestSnpMask_REG_10
+    & io_msInfo_10_bits_w_rprobeacklast & ~io_msInfo_10_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_11;
+  wire        _task_task_snpHitReleaseIdx_T_11 =
+    io_msInfo_11_valid & _replaceNestSnpMask_T_154 & _replaceNestSnpMask_T_156
+    & (~io_msInfo_11_bits_dirHit | ~io_msInfo_11_bits_s_cmoresp)
+    & (|io_msInfo_11_bits_meta_state) & replaceNestSnpMask_REG_11
+    & io_msInfo_11_bits_w_rprobeacklast & ~io_msInfo_11_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_12;
+  wire        _task_task_snpHitReleaseIdx_T_12 =
+    io_msInfo_12_valid & _replaceNestSnpMask_T_168 & _replaceNestSnpMask_T_170
+    & (~io_msInfo_12_bits_dirHit | ~io_msInfo_12_bits_s_cmoresp)
+    & (|io_msInfo_12_bits_meta_state) & replaceNestSnpMask_REG_12
+    & io_msInfo_12_bits_w_rprobeacklast & ~io_msInfo_12_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_13;
+  wire        _task_task_snpHitReleaseIdx_T_13 =
+    io_msInfo_13_valid & _replaceNestSnpMask_T_182 & _replaceNestSnpMask_T_184
+    & (~io_msInfo_13_bits_dirHit | ~io_msInfo_13_bits_s_cmoresp)
+    & (|io_msInfo_13_bits_meta_state) & replaceNestSnpMask_REG_13
+    & io_msInfo_13_bits_w_rprobeacklast & ~io_msInfo_13_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_14;
+  wire        _task_task_snpHitReleaseIdx_T_14 =
+    io_msInfo_14_valid & _replaceNestSnpMask_T_196 & _replaceNestSnpMask_T_198
+    & (~io_msInfo_14_bits_dirHit | ~io_msInfo_14_bits_s_cmoresp)
+    & (|io_msInfo_14_bits_meta_state) & replaceNestSnpMask_REG_14
+    & io_msInfo_14_bits_w_rprobeacklast & ~io_msInfo_14_bits_w_releaseack;
+  reg         replaceNestSnpMask_REG_15;
+  wire        _task_task_snpHitReleaseIdx_T_15 =
+    io_msInfo_15_valid & _replaceNestSnpMask_T_210 & _replaceNestSnpMask_T_212
+    & (~io_msInfo_15_bits_dirHit | ~io_msInfo_15_bits_s_cmoresp)
+    & (|io_msInfo_15_bits_meta_state) & replaceNestSnpMask_REG_15
+    & io_msInfo_15_bits_w_rprobeacklast & ~io_msInfo_15_bits_w_releaseack;
+  wire [15:0] replaceNestSnpMask =
+    {_task_task_snpHitReleaseIdx_T_15,
+     _task_task_snpHitReleaseIdx_T_14,
+     _task_task_snpHitReleaseIdx_T_13,
+     _task_task_snpHitReleaseIdx_T_12,
+     _task_task_snpHitReleaseIdx_T_11,
+     _task_task_snpHitReleaseIdx_T_10,
+     _task_task_snpHitReleaseIdx_T_9,
+     _task_task_snpHitReleaseIdx_T_8,
+     _task_task_snpHitReleaseIdx_T_7,
+     _task_task_snpHitReleaseIdx_T_6,
+     _task_task_snpHitReleaseIdx_T_5,
+     _task_task_snpHitReleaseIdx_T_4,
+     _task_task_snpHitReleaseIdx_T_3,
+     _task_task_snpHitReleaseIdx_T_2,
+     _task_task_snpHitReleaseIdx_T_1,
+     _task_task_snpHitReleaseIdx_T};
+  wire [12:0] _replaceNestSnpMeta_T_272 =
+    {_task_task_snpHitReleaseIdx_T & io_msInfo_0_bits_meta_dirty,
+     _task_task_snpHitReleaseIdx_T ? io_msInfo_0_bits_meta_state : 2'h0,
+     _task_task_snpHitReleaseIdx_T & io_msInfo_0_bits_meta_clients,
+     _task_task_snpHitReleaseIdx_T & io_msInfo_0_bits_meta_alias,
+     _task_task_snpHitReleaseIdx_T & io_msInfo_0_bits_meta_prefetch,
+     _task_task_snpHitReleaseIdx_T ? io_msInfo_0_bits_meta_prefetchSrc : 4'h0,
+     _task_task_snpHitReleaseIdx_T & io_msInfo_0_bits_meta_accessed,
+     _task_task_snpHitReleaseIdx_T & io_msInfo_0_bits_meta_tagErr,
+     _task_task_snpHitReleaseIdx_T & io_msInfo_0_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_1 & io_msInfo_1_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_1 ? io_msInfo_1_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_1 & io_msInfo_1_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_1 & io_msInfo_1_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_1 & io_msInfo_1_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_1 ? io_msInfo_1_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_1 & io_msInfo_1_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_1 & io_msInfo_1_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_1 & io_msInfo_1_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_2 & io_msInfo_2_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_2 ? io_msInfo_2_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_2 & io_msInfo_2_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_2 & io_msInfo_2_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_2 & io_msInfo_2_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_2 ? io_msInfo_2_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_2 & io_msInfo_2_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_2 & io_msInfo_2_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_2 & io_msInfo_2_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_3 & io_msInfo_3_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_3 ? io_msInfo_3_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_3 & io_msInfo_3_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_3 & io_msInfo_3_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_3 & io_msInfo_3_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_3 ? io_msInfo_3_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_3 & io_msInfo_3_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_3 & io_msInfo_3_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_3 & io_msInfo_3_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_4 & io_msInfo_4_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_4 ? io_msInfo_4_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_4 & io_msInfo_4_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_4 & io_msInfo_4_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_4 & io_msInfo_4_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_4 ? io_msInfo_4_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_4 & io_msInfo_4_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_4 & io_msInfo_4_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_4 & io_msInfo_4_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_5 & io_msInfo_5_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_5 ? io_msInfo_5_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_5 & io_msInfo_5_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_5 & io_msInfo_5_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_5 & io_msInfo_5_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_5 ? io_msInfo_5_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_5 & io_msInfo_5_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_5 & io_msInfo_5_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_5 & io_msInfo_5_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_6 & io_msInfo_6_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_6 ? io_msInfo_6_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_6 & io_msInfo_6_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_6 & io_msInfo_6_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_6 & io_msInfo_6_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_6 ? io_msInfo_6_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_6 & io_msInfo_6_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_6 & io_msInfo_6_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_6 & io_msInfo_6_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_7 & io_msInfo_7_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_7 ? io_msInfo_7_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_7 & io_msInfo_7_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_7 & io_msInfo_7_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_7 & io_msInfo_7_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_7 ? io_msInfo_7_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_7 & io_msInfo_7_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_7 & io_msInfo_7_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_7 & io_msInfo_7_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_8 & io_msInfo_8_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_8 ? io_msInfo_8_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_8 & io_msInfo_8_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_8 & io_msInfo_8_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_8 & io_msInfo_8_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_8 ? io_msInfo_8_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_8 & io_msInfo_8_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_8 & io_msInfo_8_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_8 & io_msInfo_8_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_9 & io_msInfo_9_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_9 ? io_msInfo_9_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_9 & io_msInfo_9_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_9 & io_msInfo_9_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_9 & io_msInfo_9_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_9 ? io_msInfo_9_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_9 & io_msInfo_9_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_9 & io_msInfo_9_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_9 & io_msInfo_9_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_10 & io_msInfo_10_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_10 ? io_msInfo_10_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_10 & io_msInfo_10_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_10 & io_msInfo_10_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_10 & io_msInfo_10_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_10 ? io_msInfo_10_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_10 & io_msInfo_10_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_10 & io_msInfo_10_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_10 & io_msInfo_10_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_11 & io_msInfo_11_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_11 ? io_msInfo_11_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_11 & io_msInfo_11_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_11 & io_msInfo_11_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_11 & io_msInfo_11_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_11 ? io_msInfo_11_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_11 & io_msInfo_11_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_11 & io_msInfo_11_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_11 & io_msInfo_11_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_12 & io_msInfo_12_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_12 ? io_msInfo_12_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_12 & io_msInfo_12_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_12 & io_msInfo_12_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_12 & io_msInfo_12_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_12 ? io_msInfo_12_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_12 & io_msInfo_12_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_12 & io_msInfo_12_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_12 & io_msInfo_12_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_13 & io_msInfo_13_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_13 ? io_msInfo_13_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_13 & io_msInfo_13_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_13 & io_msInfo_13_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_13 & io_msInfo_13_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_13 ? io_msInfo_13_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_13 & io_msInfo_13_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_13 & io_msInfo_13_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_13 & io_msInfo_13_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_14 & io_msInfo_14_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_14 ? io_msInfo_14_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_14 & io_msInfo_14_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_14 & io_msInfo_14_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_14 & io_msInfo_14_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_14 ? io_msInfo_14_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_14 & io_msInfo_14_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_14 & io_msInfo_14_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_14 & io_msInfo_14_bits_meta_dataErr}
+    | {_task_task_snpHitReleaseIdx_T_15 & io_msInfo_15_bits_meta_dirty,
+       _task_task_snpHitReleaseIdx_T_15 ? io_msInfo_15_bits_meta_state : 2'h0,
+       _task_task_snpHitReleaseIdx_T_15 & io_msInfo_15_bits_meta_clients,
+       _task_task_snpHitReleaseIdx_T_15 & io_msInfo_15_bits_meta_alias,
+       _task_task_snpHitReleaseIdx_T_15 & io_msInfo_15_bits_meta_prefetch,
+       _task_task_snpHitReleaseIdx_T_15 ? io_msInfo_15_bits_meta_prefetchSrc : 4'h0,
+       _task_task_snpHitReleaseIdx_T_15 & io_msInfo_15_bits_meta_accessed,
+       _task_task_snpHitReleaseIdx_T_15 & io_msInfo_15_bits_meta_tagErr,
+       _task_task_snpHitReleaseIdx_T_15 & io_msInfo_15_bits_meta_dataErr};
+  assign task_tag = _queue_io_deq_bits_addr[44:11];
+  assign task_set = _queue_io_deq_bits_addr[10:3];
+  wire [47:0] _GEN =
+    {io_msInfo_15_valid & _replaceNestSnpMask_T_210 & io_msInfo_15_bits_reqTag == task_tag
+       & (io_msInfo_15_bits_w_grantfirst | io_msInfo_15_bits_aliasTask
+          & ~io_msInfo_15_bits_w_rprobeacklast)
+       & (io_msInfo_15_bits_blockRefill | io_msInfo_15_bits_w_releaseack)
+       & ~io_msInfo_15_bits_willFree,
+     io_msInfo_14_valid & _replaceNestSnpMask_T_196 & io_msInfo_14_bits_reqTag == task_tag
+       & (io_msInfo_14_bits_w_grantfirst | io_msInfo_14_bits_aliasTask
+          & ~io_msInfo_14_bits_w_rprobeacklast)
+       & (io_msInfo_14_bits_blockRefill | io_msInfo_14_bits_w_releaseack)
+       & ~io_msInfo_14_bits_willFree,
+     io_msInfo_13_valid & _replaceNestSnpMask_T_182 & io_msInfo_13_bits_reqTag == task_tag
+       & (io_msInfo_13_bits_w_grantfirst | io_msInfo_13_bits_aliasTask
+          & ~io_msInfo_13_bits_w_rprobeacklast)
+       & (io_msInfo_13_bits_blockRefill | io_msInfo_13_bits_w_releaseack)
+       & ~io_msInfo_13_bits_willFree,
+     io_msInfo_12_valid & _replaceNestSnpMask_T_168 & io_msInfo_12_bits_reqTag == task_tag
+       & (io_msInfo_12_bits_w_grantfirst | io_msInfo_12_bits_aliasTask
+          & ~io_msInfo_12_bits_w_rprobeacklast)
+       & (io_msInfo_12_bits_blockRefill | io_msInfo_12_bits_w_releaseack)
+       & ~io_msInfo_12_bits_willFree,
+     io_msInfo_11_valid & _replaceNestSnpMask_T_154 & io_msInfo_11_bits_reqTag == task_tag
+       & (io_msInfo_11_bits_w_grantfirst | io_msInfo_11_bits_aliasTask
+          & ~io_msInfo_11_bits_w_rprobeacklast)
+       & (io_msInfo_11_bits_blockRefill | io_msInfo_11_bits_w_releaseack)
+       & ~io_msInfo_11_bits_willFree,
+     io_msInfo_10_valid & _replaceNestSnpMask_T_140 & io_msInfo_10_bits_reqTag == task_tag
+       & (io_msInfo_10_bits_w_grantfirst | io_msInfo_10_bits_aliasTask
+          & ~io_msInfo_10_bits_w_rprobeacklast)
+       & (io_msInfo_10_bits_blockRefill | io_msInfo_10_bits_w_releaseack)
+       & ~io_msInfo_10_bits_willFree,
+     io_msInfo_9_valid & _replaceNestSnpMask_T_126 & io_msInfo_9_bits_reqTag == task_tag
+       & (io_msInfo_9_bits_w_grantfirst | io_msInfo_9_bits_aliasTask
+          & ~io_msInfo_9_bits_w_rprobeacklast)
+       & (io_msInfo_9_bits_blockRefill | io_msInfo_9_bits_w_releaseack)
+       & ~io_msInfo_9_bits_willFree,
+     io_msInfo_8_valid & _replaceNestSnpMask_T_112 & io_msInfo_8_bits_reqTag == task_tag
+       & (io_msInfo_8_bits_w_grantfirst | io_msInfo_8_bits_aliasTask
+          & ~io_msInfo_8_bits_w_rprobeacklast)
+       & (io_msInfo_8_bits_blockRefill | io_msInfo_8_bits_w_releaseack)
+       & ~io_msInfo_8_bits_willFree,
+     io_msInfo_7_valid & _replaceNestSnpMask_T_98 & io_msInfo_7_bits_reqTag == task_tag
+       & (io_msInfo_7_bits_w_grantfirst | io_msInfo_7_bits_aliasTask
+          & ~io_msInfo_7_bits_w_rprobeacklast)
+       & (io_msInfo_7_bits_blockRefill | io_msInfo_7_bits_w_releaseack)
+       & ~io_msInfo_7_bits_willFree,
+     io_msInfo_6_valid & _replaceNestSnpMask_T_84 & io_msInfo_6_bits_reqTag == task_tag
+       & (io_msInfo_6_bits_w_grantfirst | io_msInfo_6_bits_aliasTask
+          & ~io_msInfo_6_bits_w_rprobeacklast)
+       & (io_msInfo_6_bits_blockRefill | io_msInfo_6_bits_w_releaseack)
+       & ~io_msInfo_6_bits_willFree,
+     io_msInfo_5_valid & _replaceNestSnpMask_T_70 & io_msInfo_5_bits_reqTag == task_tag
+       & (io_msInfo_5_bits_w_grantfirst | io_msInfo_5_bits_aliasTask
+          & ~io_msInfo_5_bits_w_rprobeacklast)
+       & (io_msInfo_5_bits_blockRefill | io_msInfo_5_bits_w_releaseack)
+       & ~io_msInfo_5_bits_willFree,
+     io_msInfo_4_valid & _replaceNestSnpMask_T_56 & io_msInfo_4_bits_reqTag == task_tag
+       & (io_msInfo_4_bits_w_grantfirst | io_msInfo_4_bits_aliasTask
+          & ~io_msInfo_4_bits_w_rprobeacklast)
+       & (io_msInfo_4_bits_blockRefill | io_msInfo_4_bits_w_releaseack)
+       & ~io_msInfo_4_bits_willFree,
+     io_msInfo_3_valid & _replaceNestSnpMask_T_42 & io_msInfo_3_bits_reqTag == task_tag
+       & (io_msInfo_3_bits_w_grantfirst | io_msInfo_3_bits_aliasTask
+          & ~io_msInfo_3_bits_w_rprobeacklast)
+       & (io_msInfo_3_bits_blockRefill | io_msInfo_3_bits_w_releaseack)
+       & ~io_msInfo_3_bits_willFree,
+     io_msInfo_2_valid & _replaceNestSnpMask_T_28 & io_msInfo_2_bits_reqTag == task_tag
+       & (io_msInfo_2_bits_w_grantfirst | io_msInfo_2_bits_aliasTask
+          & ~io_msInfo_2_bits_w_rprobeacklast)
+       & (io_msInfo_2_bits_blockRefill | io_msInfo_2_bits_w_releaseack)
+       & ~io_msInfo_2_bits_willFree,
+     io_msInfo_1_valid & _replaceNestSnpMask_T_14 & io_msInfo_1_bits_reqTag == task_tag
+       & (io_msInfo_1_bits_w_grantfirst | io_msInfo_1_bits_aliasTask
+          & ~io_msInfo_1_bits_w_rprobeacklast)
+       & (io_msInfo_1_bits_blockRefill | io_msInfo_1_bits_w_releaseack)
+       & ~io_msInfo_1_bits_willFree,
+     io_msInfo_0_valid & _replaceNestSnpMask_T & io_msInfo_0_bits_reqTag == task_tag
+       & (io_msInfo_0_bits_w_grantfirst | io_msInfo_0_bits_aliasTask
+          & ~io_msInfo_0_bits_w_rprobeacklast)
+       & (io_msInfo_0_bits_blockRefill | io_msInfo_0_bits_w_releaseack)
+       & ~io_msInfo_0_bits_willFree,
+     io_msInfo_15_valid & _replaceNestSnpMask_T_210 & _replaceNestSnpMask_T_212
+       & ~io_msInfo_15_bits_dirHit & (|io_msInfo_15_bits_meta_state)
+       & io_msInfo_15_bits_s_cmoresp & io_msInfo_15_bits_w_replResp
+       & (~io_msInfo_15_bits_w_rprobeacklast | io_msInfo_15_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_15) & ~io_msInfo_15_bits_willFree,
+     io_msInfo_14_valid & _replaceNestSnpMask_T_196 & _replaceNestSnpMask_T_198
+       & ~io_msInfo_14_bits_dirHit & (|io_msInfo_14_bits_meta_state)
+       & io_msInfo_14_bits_s_cmoresp & io_msInfo_14_bits_w_replResp
+       & (~io_msInfo_14_bits_w_rprobeacklast | io_msInfo_14_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_14) & ~io_msInfo_14_bits_willFree,
+     io_msInfo_13_valid & _replaceNestSnpMask_T_182 & _replaceNestSnpMask_T_184
+       & ~io_msInfo_13_bits_dirHit & (|io_msInfo_13_bits_meta_state)
+       & io_msInfo_13_bits_s_cmoresp & io_msInfo_13_bits_w_replResp
+       & (~io_msInfo_13_bits_w_rprobeacklast | io_msInfo_13_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_13) & ~io_msInfo_13_bits_willFree,
+     io_msInfo_12_valid & _replaceNestSnpMask_T_168 & _replaceNestSnpMask_T_170
+       & ~io_msInfo_12_bits_dirHit & (|io_msInfo_12_bits_meta_state)
+       & io_msInfo_12_bits_s_cmoresp & io_msInfo_12_bits_w_replResp
+       & (~io_msInfo_12_bits_w_rprobeacklast | io_msInfo_12_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_12) & ~io_msInfo_12_bits_willFree,
+     io_msInfo_11_valid & _replaceNestSnpMask_T_154 & _replaceNestSnpMask_T_156
+       & ~io_msInfo_11_bits_dirHit & (|io_msInfo_11_bits_meta_state)
+       & io_msInfo_11_bits_s_cmoresp & io_msInfo_11_bits_w_replResp
+       & (~io_msInfo_11_bits_w_rprobeacklast | io_msInfo_11_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_11) & ~io_msInfo_11_bits_willFree,
+     io_msInfo_10_valid & _replaceNestSnpMask_T_140 & _replaceNestSnpMask_T_142
+       & ~io_msInfo_10_bits_dirHit & (|io_msInfo_10_bits_meta_state)
+       & io_msInfo_10_bits_s_cmoresp & io_msInfo_10_bits_w_replResp
+       & (~io_msInfo_10_bits_w_rprobeacklast | io_msInfo_10_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_10) & ~io_msInfo_10_bits_willFree,
+     io_msInfo_9_valid & _replaceNestSnpMask_T_126 & _replaceNestSnpMask_T_128
+       & ~io_msInfo_9_bits_dirHit & (|io_msInfo_9_bits_meta_state)
+       & io_msInfo_9_bits_s_cmoresp & io_msInfo_9_bits_w_replResp
+       & (~io_msInfo_9_bits_w_rprobeacklast | io_msInfo_9_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_9) & ~io_msInfo_9_bits_willFree,
+     io_msInfo_8_valid & _replaceNestSnpMask_T_112 & _replaceNestSnpMask_T_114
+       & ~io_msInfo_8_bits_dirHit & (|io_msInfo_8_bits_meta_state)
+       & io_msInfo_8_bits_s_cmoresp & io_msInfo_8_bits_w_replResp
+       & (~io_msInfo_8_bits_w_rprobeacklast | io_msInfo_8_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_8) & ~io_msInfo_8_bits_willFree,
+     io_msInfo_7_valid & _replaceNestSnpMask_T_98 & _replaceNestSnpMask_T_100
+       & ~io_msInfo_7_bits_dirHit & (|io_msInfo_7_bits_meta_state)
+       & io_msInfo_7_bits_s_cmoresp & io_msInfo_7_bits_w_replResp
+       & (~io_msInfo_7_bits_w_rprobeacklast | io_msInfo_7_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_7) & ~io_msInfo_7_bits_willFree,
+     io_msInfo_6_valid & _replaceNestSnpMask_T_84 & _replaceNestSnpMask_T_86
+       & ~io_msInfo_6_bits_dirHit & (|io_msInfo_6_bits_meta_state)
+       & io_msInfo_6_bits_s_cmoresp & io_msInfo_6_bits_w_replResp
+       & (~io_msInfo_6_bits_w_rprobeacklast | io_msInfo_6_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_6) & ~io_msInfo_6_bits_willFree,
+     io_msInfo_5_valid & _replaceNestSnpMask_T_70 & _replaceNestSnpMask_T_72
+       & ~io_msInfo_5_bits_dirHit & (|io_msInfo_5_bits_meta_state)
+       & io_msInfo_5_bits_s_cmoresp & io_msInfo_5_bits_w_replResp
+       & (~io_msInfo_5_bits_w_rprobeacklast | io_msInfo_5_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_5) & ~io_msInfo_5_bits_willFree,
+     io_msInfo_4_valid & _replaceNestSnpMask_T_56 & _replaceNestSnpMask_T_58
+       & ~io_msInfo_4_bits_dirHit & (|io_msInfo_4_bits_meta_state)
+       & io_msInfo_4_bits_s_cmoresp & io_msInfo_4_bits_w_replResp
+       & (~io_msInfo_4_bits_w_rprobeacklast | io_msInfo_4_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_4) & ~io_msInfo_4_bits_willFree,
+     io_msInfo_3_valid & _replaceNestSnpMask_T_42 & _replaceNestSnpMask_T_44
+       & ~io_msInfo_3_bits_dirHit & (|io_msInfo_3_bits_meta_state)
+       & io_msInfo_3_bits_s_cmoresp & io_msInfo_3_bits_w_replResp
+       & (~io_msInfo_3_bits_w_rprobeacklast | io_msInfo_3_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_3) & ~io_msInfo_3_bits_willFree,
+     io_msInfo_2_valid & _replaceNestSnpMask_T_28 & _replaceNestSnpMask_T_30
+       & ~io_msInfo_2_bits_dirHit & (|io_msInfo_2_bits_meta_state)
+       & io_msInfo_2_bits_s_cmoresp & io_msInfo_2_bits_w_replResp
+       & (~io_msInfo_2_bits_w_rprobeacklast | io_msInfo_2_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_2) & ~io_msInfo_2_bits_willFree,
+     io_msInfo_1_valid & _replaceNestSnpMask_T_14 & _replaceNestSnpMask_T_16
+       & ~io_msInfo_1_bits_dirHit & (|io_msInfo_1_bits_meta_state)
+       & io_msInfo_1_bits_s_cmoresp & io_msInfo_1_bits_w_replResp
+       & (~io_msInfo_1_bits_w_rprobeacklast | io_msInfo_1_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG_1) & ~io_msInfo_1_bits_willFree,
+     io_msInfo_0_valid & _replaceNestSnpMask_T & _replaceNestSnpMask_T_2
+       & ~io_msInfo_0_bits_dirHit & (|io_msInfo_0_bits_meta_state)
+       & io_msInfo_0_bits_s_cmoresp & io_msInfo_0_bits_w_replResp
+       & (~io_msInfo_0_bits_w_rprobeacklast | io_msInfo_0_bits_w_releaseack
+          | ~replaceBlockSnpMask_REG) & ~io_msInfo_0_bits_willFree,
+     io_msInfo_15_valid & io_msInfo_15_bits_dirHit & (|io_msInfo_15_bits_meta_state)
+       & ~io_msInfo_15_bits_s_cmoresp
+       & (~io_msInfo_15_bits_s_release | ~io_msInfo_15_bits_w_rprobeacklast
+          | ~io_msInfo_15_bits_s_cmometaw) & ~io_msInfo_15_bits_willFree,
+     io_msInfo_14_valid & io_msInfo_14_bits_dirHit & (|io_msInfo_14_bits_meta_state)
+       & ~io_msInfo_14_bits_s_cmoresp
+       & (~io_msInfo_14_bits_s_release | ~io_msInfo_14_bits_w_rprobeacklast
+          | ~io_msInfo_14_bits_s_cmometaw) & ~io_msInfo_14_bits_willFree,
+     io_msInfo_13_valid & io_msInfo_13_bits_dirHit & (|io_msInfo_13_bits_meta_state)
+       & ~io_msInfo_13_bits_s_cmoresp
+       & (~io_msInfo_13_bits_s_release | ~io_msInfo_13_bits_w_rprobeacklast
+          | ~io_msInfo_13_bits_s_cmometaw) & ~io_msInfo_13_bits_willFree,
+     io_msInfo_12_valid & io_msInfo_12_bits_dirHit & (|io_msInfo_12_bits_meta_state)
+       & ~io_msInfo_12_bits_s_cmoresp
+       & (~io_msInfo_12_bits_s_release | ~io_msInfo_12_bits_w_rprobeacklast
+          | ~io_msInfo_12_bits_s_cmometaw) & ~io_msInfo_12_bits_willFree,
+     io_msInfo_11_valid & io_msInfo_11_bits_dirHit & (|io_msInfo_11_bits_meta_state)
+       & ~io_msInfo_11_bits_s_cmoresp
+       & (~io_msInfo_11_bits_s_release | ~io_msInfo_11_bits_w_rprobeacklast
+          | ~io_msInfo_11_bits_s_cmometaw) & ~io_msInfo_11_bits_willFree,
+     io_msInfo_10_valid & io_msInfo_10_bits_dirHit & (|io_msInfo_10_bits_meta_state)
+       & ~io_msInfo_10_bits_s_cmoresp
+       & (~io_msInfo_10_bits_s_release | ~io_msInfo_10_bits_w_rprobeacklast
+          | ~io_msInfo_10_bits_s_cmometaw) & ~io_msInfo_10_bits_willFree,
+     io_msInfo_9_valid & io_msInfo_9_bits_dirHit & (|io_msInfo_9_bits_meta_state)
+       & ~io_msInfo_9_bits_s_cmoresp
+       & (~io_msInfo_9_bits_s_release | ~io_msInfo_9_bits_w_rprobeacklast
+          | ~io_msInfo_9_bits_s_cmometaw) & ~io_msInfo_9_bits_willFree,
+     io_msInfo_8_valid & io_msInfo_8_bits_dirHit & (|io_msInfo_8_bits_meta_state)
+       & ~io_msInfo_8_bits_s_cmoresp
+       & (~io_msInfo_8_bits_s_release | ~io_msInfo_8_bits_w_rprobeacklast
+          | ~io_msInfo_8_bits_s_cmometaw) & ~io_msInfo_8_bits_willFree,
+     io_msInfo_7_valid & io_msInfo_7_bits_dirHit & (|io_msInfo_7_bits_meta_state)
+       & ~io_msInfo_7_bits_s_cmoresp
+       & (~io_msInfo_7_bits_s_release | ~io_msInfo_7_bits_w_rprobeacklast
+          | ~io_msInfo_7_bits_s_cmometaw) & ~io_msInfo_7_bits_willFree,
+     io_msInfo_6_valid & io_msInfo_6_bits_dirHit & (|io_msInfo_6_bits_meta_state)
+       & ~io_msInfo_6_bits_s_cmoresp
+       & (~io_msInfo_6_bits_s_release | ~io_msInfo_6_bits_w_rprobeacklast
+          | ~io_msInfo_6_bits_s_cmometaw) & ~io_msInfo_6_bits_willFree,
+     io_msInfo_5_valid & io_msInfo_5_bits_dirHit & (|io_msInfo_5_bits_meta_state)
+       & ~io_msInfo_5_bits_s_cmoresp
+       & (~io_msInfo_5_bits_s_release | ~io_msInfo_5_bits_w_rprobeacklast
+          | ~io_msInfo_5_bits_s_cmometaw) & ~io_msInfo_5_bits_willFree,
+     io_msInfo_4_valid & io_msInfo_4_bits_dirHit & (|io_msInfo_4_bits_meta_state)
+       & ~io_msInfo_4_bits_s_cmoresp
+       & (~io_msInfo_4_bits_s_release | ~io_msInfo_4_bits_w_rprobeacklast
+          | ~io_msInfo_4_bits_s_cmometaw) & ~io_msInfo_4_bits_willFree,
+     io_msInfo_3_valid & io_msInfo_3_bits_dirHit & (|io_msInfo_3_bits_meta_state)
+       & ~io_msInfo_3_bits_s_cmoresp
+       & (~io_msInfo_3_bits_s_release | ~io_msInfo_3_bits_w_rprobeacklast
+          | ~io_msInfo_3_bits_s_cmometaw) & ~io_msInfo_3_bits_willFree,
+     io_msInfo_2_valid & io_msInfo_2_bits_dirHit & (|io_msInfo_2_bits_meta_state)
+       & ~io_msInfo_2_bits_s_cmoresp
+       & (~io_msInfo_2_bits_s_release | ~io_msInfo_2_bits_w_rprobeacklast
+          | ~io_msInfo_2_bits_s_cmometaw) & ~io_msInfo_2_bits_willFree,
+     io_msInfo_1_valid & io_msInfo_1_bits_dirHit & (|io_msInfo_1_bits_meta_state)
+       & ~io_msInfo_1_bits_s_cmoresp
+       & (~io_msInfo_1_bits_s_release | ~io_msInfo_1_bits_w_rprobeacklast
+          | ~io_msInfo_1_bits_s_cmometaw) & ~io_msInfo_1_bits_willFree,
+     io_msInfo_0_valid & io_msInfo_0_bits_dirHit & (|io_msInfo_0_bits_meta_state)
+       & ~io_msInfo_0_bits_s_cmoresp
+       & (~io_msInfo_0_bits_s_release | ~io_msInfo_0_bits_w_rprobeacklast
+          | ~io_msInfo_0_bits_s_cmometaw) & ~io_msInfo_0_bits_willFree};
+  wire        _rxsnp_ready_T = _GEN == 48'h0;
+  always @(posedge clock) begin
+    replaceBlockSnpMask_REG <= io_msInfo_0_bits_w_replResp;
+    replaceBlockSnpMask_REG_1 <= io_msInfo_1_bits_w_replResp;
+    replaceBlockSnpMask_REG_2 <= io_msInfo_2_bits_w_replResp;
+    replaceBlockSnpMask_REG_3 <= io_msInfo_3_bits_w_replResp;
+    replaceBlockSnpMask_REG_4 <= io_msInfo_4_bits_w_replResp;
+    replaceBlockSnpMask_REG_5 <= io_msInfo_5_bits_w_replResp;
+    replaceBlockSnpMask_REG_6 <= io_msInfo_6_bits_w_replResp;
+    replaceBlockSnpMask_REG_7 <= io_msInfo_7_bits_w_replResp;
+    replaceBlockSnpMask_REG_8 <= io_msInfo_8_bits_w_replResp;
+    replaceBlockSnpMask_REG_9 <= io_msInfo_9_bits_w_replResp;
+    replaceBlockSnpMask_REG_10 <= io_msInfo_10_bits_w_replResp;
+    replaceBlockSnpMask_REG_11 <= io_msInfo_11_bits_w_replResp;
+    replaceBlockSnpMask_REG_12 <= io_msInfo_12_bits_w_replResp;
+    replaceBlockSnpMask_REG_13 <= io_msInfo_13_bits_w_replResp;
+    replaceBlockSnpMask_REG_14 <= io_msInfo_14_bits_w_replResp;
+    replaceBlockSnpMask_REG_15 <= io_msInfo_15_bits_w_replResp;
+    replaceNestSnpMask_REG <= io_msInfo_0_bits_w_replResp;
+    replaceNestSnpMask_REG_1 <= io_msInfo_1_bits_w_replResp;
+    replaceNestSnpMask_REG_2 <= io_msInfo_2_bits_w_replResp;
+    replaceNestSnpMask_REG_3 <= io_msInfo_3_bits_w_replResp;
+    replaceNestSnpMask_REG_4 <= io_msInfo_4_bits_w_replResp;
+    replaceNestSnpMask_REG_5 <= io_msInfo_5_bits_w_replResp;
+    replaceNestSnpMask_REG_6 <= io_msInfo_6_bits_w_replResp;
+    replaceNestSnpMask_REG_7 <= io_msInfo_7_bits_w_replResp;
+    replaceNestSnpMask_REG_8 <= io_msInfo_8_bits_w_replResp;
+    replaceNestSnpMask_REG_9 <= io_msInfo_9_bits_w_replResp;
+    replaceNestSnpMask_REG_10 <= io_msInfo_10_bits_w_replResp;
+    replaceNestSnpMask_REG_11 <= io_msInfo_11_bits_w_replResp;
+    replaceNestSnpMask_REG_12 <= io_msInfo_12_bits_w_replResp;
+    replaceNestSnpMask_REG_13 <= io_msInfo_13_bits_w_replResp;
+    replaceNestSnpMask_REG_14 <= io_msInfo_14_bits_w_replResp;
+    replaceNestSnpMask_REG_15 <= io_msInfo_15_bits_w_replResp;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        replaceBlockSnpMask_REG = _RANDOM[/*Zero width*/ 1'b0][0];
+        replaceBlockSnpMask_REG_1 = _RANDOM[/*Zero width*/ 1'b0][1];
+        replaceBlockSnpMask_REG_2 = _RANDOM[/*Zero width*/ 1'b0][2];
+        replaceBlockSnpMask_REG_3 = _RANDOM[/*Zero width*/ 1'b0][3];
+        replaceBlockSnpMask_REG_4 = _RANDOM[/*Zero width*/ 1'b0][4];
+        replaceBlockSnpMask_REG_5 = _RANDOM[/*Zero width*/ 1'b0][5];
+        replaceBlockSnpMask_REG_6 = _RANDOM[/*Zero width*/ 1'b0][6];
+        replaceBlockSnpMask_REG_7 = _RANDOM[/*Zero width*/ 1'b0][7];
+        replaceBlockSnpMask_REG_8 = _RANDOM[/*Zero width*/ 1'b0][8];
+        replaceBlockSnpMask_REG_9 = _RANDOM[/*Zero width*/ 1'b0][9];
+        replaceBlockSnpMask_REG_10 = _RANDOM[/*Zero width*/ 1'b0][10];
+        replaceBlockSnpMask_REG_11 = _RANDOM[/*Zero width*/ 1'b0][11];
+        replaceBlockSnpMask_REG_12 = _RANDOM[/*Zero width*/ 1'b0][12];
+        replaceBlockSnpMask_REG_13 = _RANDOM[/*Zero width*/ 1'b0][13];
+        replaceBlockSnpMask_REG_14 = _RANDOM[/*Zero width*/ 1'b0][14];
+        replaceBlockSnpMask_REG_15 = _RANDOM[/*Zero width*/ 1'b0][15];
+        replaceNestSnpMask_REG = _RANDOM[/*Zero width*/ 1'b0][16];
+        replaceNestSnpMask_REG_1 = _RANDOM[/*Zero width*/ 1'b0][17];
+        replaceNestSnpMask_REG_2 = _RANDOM[/*Zero width*/ 1'b0][18];
+        replaceNestSnpMask_REG_3 = _RANDOM[/*Zero width*/ 1'b0][19];
+        replaceNestSnpMask_REG_4 = _RANDOM[/*Zero width*/ 1'b0][20];
+        replaceNestSnpMask_REG_5 = _RANDOM[/*Zero width*/ 1'b0][21];
+        replaceNestSnpMask_REG_6 = _RANDOM[/*Zero width*/ 1'b0][22];
+        replaceNestSnpMask_REG_7 = _RANDOM[/*Zero width*/ 1'b0][23];
+        replaceNestSnpMask_REG_8 = _RANDOM[/*Zero width*/ 1'b0][24];
+        replaceNestSnpMask_REG_9 = _RANDOM[/*Zero width*/ 1'b0][25];
+        replaceNestSnpMask_REG_10 = _RANDOM[/*Zero width*/ 1'b0][26];
+        replaceNestSnpMask_REG_11 = _RANDOM[/*Zero width*/ 1'b0][27];
+        replaceNestSnpMask_REG_12 = _RANDOM[/*Zero width*/ 1'b0][28];
+        replaceNestSnpMask_REG_13 = _RANDOM[/*Zero width*/ 1'b0][29];
+        replaceNestSnpMask_REG_14 = _RANDOM[/*Zero width*/ 1'b0][30];
+        replaceNestSnpMask_REG_15 = _RANDOM[/*Zero width*/ 1'b0][31];
+      `endif // RANDOMIZE_REG_INIT
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  Queue2_CHISNP queue (
+    .clock                         (clock),
+    .reset                         (reset),
+    .io_enq_ready                  (io_rxsnp_ready),
+    .io_enq_valid                  (io_rxsnp_valid),
+    .io_enq_bits_qos               (io_rxsnp_bits_qos),
+    .io_enq_bits_srcID             (io_rxsnp_bits_srcID),
+    .io_enq_bits_txnID             (io_rxsnp_bits_txnID),
+    .io_enq_bits_fwdNID            (io_rxsnp_bits_fwdNID),
+    .io_enq_bits_fwdTxnID          (io_rxsnp_bits_fwdTxnID),
+    .io_enq_bits_opcode            (io_rxsnp_bits_opcode),
+    .io_enq_bits_addr              (io_rxsnp_bits_addr),
+    .io_enq_bits_ns                (io_rxsnp_bits_ns),
+    .io_enq_bits_doNotGoToSD       (io_rxsnp_bits_doNotGoToSD),
+    .io_enq_bits_retToSrc          (io_rxsnp_bits_retToSrc),
+    .io_enq_bits_traceTag          (io_rxsnp_bits_traceTag),
+    .io_enq_bits_mpam_perfMonGroup (io_rxsnp_bits_mpam_perfMonGroup),
+    .io_enq_bits_mpam_partID       (io_rxsnp_bits_mpam_partID),
+    .io_enq_bits_mpam_mpamNS       (io_rxsnp_bits_mpam_mpamNS),
+    .io_deq_ready                  (io_task_ready & _rxsnp_ready_T),
+    .io_deq_valid                  (_queue_io_deq_valid),
+    .io_deq_bits_srcID             (io_task_bits_srcID),
+    .io_deq_bits_txnID             (io_task_bits_txnID),
+    .io_deq_bits_fwdNID            (io_task_bits_fwdNID),
+    .io_deq_bits_fwdTxnID          (io_task_bits_fwdTxnID),
+    .io_deq_bits_opcode            (_queue_io_deq_bits_opcode),
+    .io_deq_bits_addr              (_queue_io_deq_bits_addr),
+    .io_deq_bits_retToSrc          (io_task_bits_retToSrc),
+    .io_deq_bits_traceTag          (io_task_bits_traceTag)
+  );
+  assign io_task_valid = _queue_io_deq_valid & _rxsnp_ready_T;
+  assign io_task_bits_set = task_set;
+  assign io_task_bits_tag = task_tag;
+  assign io_task_bits_off = {_queue_io_deq_bits_addr[2:0], 3'h0};
+  assign io_task_bits_snpHitRelease = |replaceNestSnpMask;
+  assign io_task_bits_snpHitReleaseToInval =
+    |(replaceNestSnpMask
+      & {~io_msInfo_15_bits_releaseToClean,
+         ~io_msInfo_14_bits_releaseToClean,
+         ~io_msInfo_13_bits_releaseToClean,
+         ~io_msInfo_12_bits_releaseToClean,
+         ~io_msInfo_11_bits_releaseToClean,
+         ~io_msInfo_10_bits_releaseToClean,
+         ~io_msInfo_9_bits_releaseToClean,
+         ~io_msInfo_8_bits_releaseToClean,
+         ~io_msInfo_7_bits_releaseToClean,
+         ~io_msInfo_6_bits_releaseToClean,
+         ~io_msInfo_5_bits_releaseToClean,
+         ~io_msInfo_4_bits_releaseToClean,
+         ~io_msInfo_3_bits_releaseToClean,
+         ~io_msInfo_2_bits_releaseToClean,
+         ~io_msInfo_1_bits_releaseToClean,
+         ~io_msInfo_0_bits_releaseToClean});
+  assign io_task_bits_snpHitReleaseToClean =
+    |(replaceNestSnpMask
+      & {io_msInfo_15_bits_releaseToClean,
+         io_msInfo_14_bits_releaseToClean,
+         io_msInfo_13_bits_releaseToClean,
+         io_msInfo_12_bits_releaseToClean,
+         io_msInfo_11_bits_releaseToClean,
+         io_msInfo_10_bits_releaseToClean,
+         io_msInfo_9_bits_releaseToClean,
+         io_msInfo_8_bits_releaseToClean,
+         io_msInfo_7_bits_releaseToClean,
+         io_msInfo_6_bits_releaseToClean,
+         io_msInfo_5_bits_releaseToClean,
+         io_msInfo_4_bits_releaseToClean,
+         io_msInfo_3_bits_releaseToClean,
+         io_msInfo_2_bits_releaseToClean,
+         io_msInfo_1_bits_releaseToClean,
+         io_msInfo_0_bits_releaseToClean});
+  assign io_task_bits_snpHitReleaseWithData =
+    |(replaceNestSnpMask
+      & {io_msInfo_15_bits_replaceData,
+         io_msInfo_14_bits_replaceData,
+         io_msInfo_13_bits_replaceData,
+         io_msInfo_12_bits_replaceData,
+         io_msInfo_11_bits_replaceData,
+         io_msInfo_10_bits_replaceData,
+         io_msInfo_9_bits_replaceData,
+         io_msInfo_8_bits_replaceData,
+         io_msInfo_7_bits_replaceData,
+         io_msInfo_6_bits_replaceData,
+         io_msInfo_5_bits_replaceData,
+         io_msInfo_4_bits_replaceData,
+         io_msInfo_3_bits_replaceData,
+         io_msInfo_2_bits_replaceData,
+         io_msInfo_1_bits_replaceData,
+         io_msInfo_0_bits_replaceData});
+  assign io_task_bits_snpHitReleaseIdx =
+    {4'h0,
+     _task_task_snpHitReleaseIdx_T
+       ? 4'h0
+       : _task_task_snpHitReleaseIdx_T_1
+           ? 4'h1
+           : _task_task_snpHitReleaseIdx_T_2
+               ? 4'h2
+               : _task_task_snpHitReleaseIdx_T_3
+                   ? 4'h3
+                   : _task_task_snpHitReleaseIdx_T_4
+                       ? 4'h4
+                       : _task_task_snpHitReleaseIdx_T_5
+                           ? 4'h5
+                           : _task_task_snpHitReleaseIdx_T_6
+                               ? 4'h6
+                               : _task_task_snpHitReleaseIdx_T_7
+                                   ? 4'h7
+                                   : _task_task_snpHitReleaseIdx_T_8
+                                       ? 4'h8
+                                       : _task_task_snpHitReleaseIdx_T_9
+                                           ? 4'h9
+                                           : _task_task_snpHitReleaseIdx_T_10
+                                               ? 4'hA
+                                               : _task_task_snpHitReleaseIdx_T_11
+                                                   ? 4'hB
+                                                   : _task_task_snpHitReleaseIdx_T_12
+                                                       ? 4'hC
+                                                       : _task_task_snpHitReleaseIdx_T_13
+                                                           ? 4'hD
+                                                           : {3'h7,
+                                                              ~_task_task_snpHitReleaseIdx_T_14}};
+  assign io_task_bits_snpHitReleaseMeta_dirty = _replaceNestSnpMeta_T_272[12];
+  assign io_task_bits_snpHitReleaseMeta_state = _replaceNestSnpMeta_T_272[11:10];
+  assign io_task_bits_snpHitReleaseMeta_clients = _replaceNestSnpMeta_T_272[9];
+  assign io_task_bits_snpHitReleaseMeta_alias = _replaceNestSnpMeta_T_272[8];
+  assign io_task_bits_snpHitReleaseMeta_prefetch = _replaceNestSnpMeta_T_272[7];
+  assign io_task_bits_snpHitReleaseMeta_prefetchSrc = _replaceNestSnpMeta_T_272[6:3];
+  assign io_task_bits_snpHitReleaseMeta_accessed = _replaceNestSnpMeta_T_272[2];
+  assign io_task_bits_snpHitReleaseMeta_tagErr = _replaceNestSnpMeta_T_272[1];
+  assign io_task_bits_snpHitReleaseMeta_dataErr = _replaceNestSnpMeta_T_272[0];
+  assign io_task_bits_chiOpcode = {2'h0, _queue_io_deq_bits_opcode};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/RecentRequestTable.sv b/flow/designs/src/xiangshan_coupledl2/deps/RecentRequestTable.sv
new file mode 100644
index 0000000000..7650877326
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/RecentRequestTable.sv
@@ -0,0 +1,172 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module RecentRequestTable(
+  input         clock,
+  input         reset,
+  output        io_w_ready,
+  input         io_w_valid,
+  input  [47:0] io_w_bits,
+  input         io_r_req_valid,
+  input  [47:0] io_r_req_bits_addr,
+  input  [6:0]  io_r_req_bits_testOffset,
+  input  [5:0]  io_r_req_bits_ptr,
+  output        io_r_resp_valid,
+  output [5:0]  io_r_resp_bits_ptr,
+  output        io_r_resp_bits_hit,
+  input  [8:0]  boreChildrenBd_bore_addr,
+  input  [8:0]  boreChildrenBd_bore_addr_rd,
+  input  [12:0] boreChildrenBd_bore_wdata,
+  input         boreChildrenBd_bore_wmask,
+  input         boreChildrenBd_bore_re,
+  input         boreChildrenBd_bore_we,
+  output [12:0] boreChildrenBd_bore_rdata,
+  input         boreChildrenBd_bore_ack,
+  input         boreChildrenBd_bore_selectedOH,
+  input         boreChildrenBd_bore_array,
+  input         sigFromSrams_bore_ram_hold,
+  input         sigFromSrams_bore_ram_bypass,
+  input         sigFromSrams_bore_ram_bp_clken,
+  input         sigFromSrams_bore_ram_aux_clk,
+  input         sigFromSrams_bore_ram_aux_ckbp,
+  input         sigFromSrams_bore_ram_mcp_hold,
+  input         sigFromSrams_bore_cgen
+);
+
+  wire        _rrTable_io_r_req_ready;
+  wire        _rrTable_io_r_resp_data_0_valid;
+  wire [11:0] _rrTable_io_r_resp_data_0_tag;
+  wire        _rrTable_io_w_req_ready;
+  wire [25:0] _rAddr_T_5 =
+    26'(io_r_req_bits_addr[25:0]
+        - {{13{io_r_req_bits_testOffset[6]}}, io_r_req_bits_testOffset, 6'h0});
+  reg         s1_valid;
+  reg  [5:0]  s1_ptr;
+  reg  [11:0] s1_hit_REG;
+  reg         s2_valid;
+  reg  [5:0]  io_r_resp_bits_ptr_r;
+  reg         io_r_resp_bits_hit_r;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      s1_valid <= 1'h0;
+      s2_valid <= 1'h0;
+    end
+    else begin
+      s1_valid <= _rrTable_io_r_req_ready & io_r_req_valid;
+      s2_valid <= s1_valid;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    s1_ptr <= io_r_req_bits_ptr;
+    s1_hit_REG <= _rAddr_T_5[25:14];
+    if (s1_valid) begin
+      io_r_resp_bits_ptr_r <= s1_ptr;
+      io_r_resp_bits_hit_r <=
+        _rrTable_io_r_resp_data_0_valid & _rrTable_io_r_resp_data_0_tag == s1_hit_REG;
+    end
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        s1_valid = _RANDOM[/*Zero width*/ 1'b0][1];
+        s1_ptr = _RANDOM[/*Zero width*/ 1'b0][7:2];
+        s1_hit_REG = _RANDOM[/*Zero width*/ 1'b0][19:8];
+        s2_valid = _RANDOM[/*Zero width*/ 1'b0][20];
+        io_r_resp_bits_ptr_r = _RANDOM[/*Zero width*/ 1'b0][26:21];
+        io_r_resp_bits_hit_r = _RANDOM[/*Zero width*/ 1'b0][27];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        s1_valid = 1'h0;
+        s2_valid = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  SRAMTemplate_239 rrTable (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_ready                 (_rrTable_io_r_req_ready),
+    .io_r_req_valid                 (io_r_req_valid),
+    .io_r_req_bits_setIdx           (_rAddr_T_5[13:6] ^ _rAddr_T_5[21:14]),
+    .io_r_resp_data_0_valid         (_rrTable_io_r_resp_data_0_valid),
+    .io_r_resp_data_0_tag           (_rrTable_io_r_resp_data_0_tag),
+    .io_w_req_ready                 (_rrTable_io_w_req_ready),
+    .io_w_req_valid                 (io_w_valid & ~io_r_req_valid),
+    .io_w_req_bits_setIdx           (io_w_bits[13:6] ^ io_w_bits[21:14]),
+    .io_w_req_bits_data_0_tag       (io_w_bits[25:14]),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_cgen),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_array)
+  );
+  assign io_w_ready = _rrTable_io_w_req_ready & ~io_r_req_valid;
+  assign io_r_resp_valid = s2_valid;
+  assign io_r_resp_bits_ptr = io_r_resp_bits_ptr_r;
+  assign io_r_resp_bits_hit = io_r_resp_bits_hit_r;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/RecentRequestTable_1.sv b/flow/designs/src/xiangshan_coupledl2/deps/RecentRequestTable_1.sv
new file mode 100644
index 0000000000..3334648a33
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/RecentRequestTable_1.sv
@@ -0,0 +1,172 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module RecentRequestTable_1(
+  input         clock,
+  input         reset,
+  output        io_w_ready,
+  input         io_w_valid,
+  input  [49:0] io_w_bits,
+  input         io_r_req_valid,
+  input  [49:0] io_r_req_bits_addr,
+  input  [9:0]  io_r_req_bits_testOffset,
+  input  [6:0]  io_r_req_bits_ptr,
+  output        io_r_resp_valid,
+  output [6:0]  io_r_resp_bits_ptr,
+  output        io_r_resp_bits_hit,
+  input  [8:0]  boreChildrenBd_bore_addr,
+  input  [8:0]  boreChildrenBd_bore_addr_rd,
+  input  [12:0] boreChildrenBd_bore_wdata,
+  input         boreChildrenBd_bore_wmask,
+  input         boreChildrenBd_bore_re,
+  input         boreChildrenBd_bore_we,
+  output [12:0] boreChildrenBd_bore_rdata,
+  input         boreChildrenBd_bore_ack,
+  input         boreChildrenBd_bore_selectedOH,
+  input         boreChildrenBd_bore_array,
+  input         sigFromSrams_bore_ram_hold,
+  input         sigFromSrams_bore_ram_bypass,
+  input         sigFromSrams_bore_ram_bp_clken,
+  input         sigFromSrams_bore_ram_aux_clk,
+  input         sigFromSrams_bore_ram_aux_ckbp,
+  input         sigFromSrams_bore_ram_mcp_hold,
+  input         sigFromSrams_bore_cgen
+);
+
+  wire        _rrTable_io_r_req_ready;
+  wire        _rrTable_io_r_resp_data_0_valid;
+  wire [11:0] _rrTable_io_r_resp_data_0_tag;
+  wire        _rrTable_io_w_req_ready;
+  wire [25:0] _rAddr_T_5 =
+    26'(io_r_req_bits_addr[25:0]
+        - {{10{io_r_req_bits_testOffset[9]}}, io_r_req_bits_testOffset, 6'h0});
+  reg         s1_valid;
+  reg  [6:0]  s1_ptr;
+  reg  [11:0] s1_hit_REG;
+  reg         s2_valid;
+  reg  [6:0]  io_r_resp_bits_ptr_r;
+  reg         io_r_resp_bits_hit_r;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      s1_valid <= 1'h0;
+      s2_valid <= 1'h0;
+    end
+    else begin
+      s1_valid <= _rrTable_io_r_req_ready & io_r_req_valid;
+      s2_valid <= s1_valid;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    s1_ptr <= io_r_req_bits_ptr;
+    s1_hit_REG <= _rAddr_T_5[25:14];
+    if (s1_valid) begin
+      io_r_resp_bits_ptr_r <= s1_ptr;
+      io_r_resp_bits_hit_r <=
+        _rrTable_io_r_resp_data_0_valid & _rrTable_io_r_resp_data_0_tag == s1_hit_REG;
+    end
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        s1_valid = _RANDOM[/*Zero width*/ 1'b0][1];
+        s1_ptr = _RANDOM[/*Zero width*/ 1'b0][8:2];
+        s1_hit_REG = _RANDOM[/*Zero width*/ 1'b0][20:9];
+        s2_valid = _RANDOM[/*Zero width*/ 1'b0][21];
+        io_r_resp_bits_ptr_r = _RANDOM[/*Zero width*/ 1'b0][28:22];
+        io_r_resp_bits_hit_r = _RANDOM[/*Zero width*/ 1'b0][29];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        s1_valid = 1'h0;
+        s2_valid = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  SRAMTemplate_239 rrTable (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_ready                 (_rrTable_io_r_req_ready),
+    .io_r_req_valid                 (io_r_req_valid),
+    .io_r_req_bits_setIdx           (_rAddr_T_5[13:6] ^ _rAddr_T_5[21:14]),
+    .io_r_resp_data_0_valid         (_rrTable_io_r_resp_data_0_valid),
+    .io_r_resp_data_0_tag           (_rrTable_io_r_resp_data_0_tag),
+    .io_w_req_ready                 (_rrTable_io_w_req_ready),
+    .io_w_req_valid                 (io_w_valid & ~io_r_req_valid),
+    .io_w_req_bits_setIdx           (io_w_bits[13:6] ^ io_w_bits[21:14]),
+    .io_w_req_bits_data_0_tag       (io_w_bits[25:14]),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_cgen),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_array)
+  );
+  assign io_w_ready = _rrTable_io_w_req_ready & ~io_r_req_valid;
+  assign io_r_resp_valid = s2_valid;
+  assign io_r_resp_bits_ptr = io_r_resp_bits_ptr_r;
+  assign io_r_resp_bits_hit = io_r_resp_bits_hit_r;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/RequestArb.sv b/flow/designs/src/xiangshan_coupledl2/deps/RequestArb.sv
new file mode 100644
index 0000000000..db9b7397d1
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/RequestArb.sv
@@ -0,0 +1,3443 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module RequestArb(
+  input         clock,
+  input         reset,
+  output        io_sinkA_ready,
+  input         io_sinkA_valid,
+  input  [2:0]  io_sinkA_bits_channel,
+  input  [2:0]  io_sinkA_bits_txChannel,
+  input  [7:0]  io_sinkA_bits_set,
+  input  [33:0] io_sinkA_bits_tag,
+  input  [5:0]  io_sinkA_bits_off,
+  input         io_sinkA_bits_alias,
+  input  [43:0] io_sinkA_bits_vaddr,
+  input         io_sinkA_bits_isKeyword,
+  input  [3:0]  io_sinkA_bits_opcode,
+  input  [2:0]  io_sinkA_bits_param,
+  input  [2:0]  io_sinkA_bits_size,
+  input  [6:0]  io_sinkA_bits_sourceId,
+  input  [1:0]  io_sinkA_bits_bufIdx,
+  input         io_sinkA_bits_needProbeAckData,
+  input         io_sinkA_bits_denied,
+  input         io_sinkA_bits_corrupt,
+  input         io_sinkA_bits_mshrTask,
+  input  [7:0]  io_sinkA_bits_mshrId,
+  input         io_sinkA_bits_aliasTask,
+  input         io_sinkA_bits_useProbeData,
+  input         io_sinkA_bits_mshrRetry,
+  input         io_sinkA_bits_readProbeDataDown,
+  input         io_sinkA_bits_fromL2pft,
+  input         io_sinkA_bits_needHint,
+  input         io_sinkA_bits_dirty,
+  input  [2:0]  io_sinkA_bits_way,
+  input         io_sinkA_bits_meta_dirty,
+  input  [1:0]  io_sinkA_bits_meta_state,
+  input         io_sinkA_bits_meta_clients,
+  input         io_sinkA_bits_meta_alias,
+  input         io_sinkA_bits_meta_prefetch,
+  input  [3:0]  io_sinkA_bits_meta_prefetchSrc,
+  input         io_sinkA_bits_meta_accessed,
+  input         io_sinkA_bits_meta_tagErr,
+  input         io_sinkA_bits_meta_dataErr,
+  input         io_sinkA_bits_metaWen,
+  input         io_sinkA_bits_tagWen,
+  input         io_sinkA_bits_dsWen,
+  input  [7:0]  io_sinkA_bits_wayMask,
+  input         io_sinkA_bits_replTask,
+  input         io_sinkA_bits_cmoTask,
+  input         io_sinkA_bits_cmoAll,
+  input  [4:0]  io_sinkA_bits_reqSource,
+  input         io_sinkA_bits_mergeA,
+  input  [5:0]  io_sinkA_bits_aMergeTask_off,
+  input         io_sinkA_bits_aMergeTask_alias,
+  input  [43:0] io_sinkA_bits_aMergeTask_vaddr,
+  input         io_sinkA_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_sinkA_bits_aMergeTask_opcode,
+  input  [2:0]  io_sinkA_bits_aMergeTask_param,
+  input  [6:0]  io_sinkA_bits_aMergeTask_sourceId,
+  input         io_sinkA_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_sinkA_bits_aMergeTask_meta_state,
+  input         io_sinkA_bits_aMergeTask_meta_clients,
+  input         io_sinkA_bits_aMergeTask_meta_alias,
+  input         io_sinkA_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_sinkA_bits_aMergeTask_meta_prefetchSrc,
+  input         io_sinkA_bits_aMergeTask_meta_accessed,
+  input         io_sinkA_bits_aMergeTask_meta_tagErr,
+  input         io_sinkA_bits_aMergeTask_meta_dataErr,
+  input         io_sinkA_bits_snpHitRelease,
+  input         io_sinkA_bits_snpHitReleaseToInval,
+  input         io_sinkA_bits_snpHitReleaseToClean,
+  input         io_sinkA_bits_snpHitReleaseWithData,
+  input  [7:0]  io_sinkA_bits_snpHitReleaseIdx,
+  input         io_sinkA_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_sinkA_bits_snpHitReleaseMeta_state,
+  input         io_sinkA_bits_snpHitReleaseMeta_clients,
+  input         io_sinkA_bits_snpHitReleaseMeta_alias,
+  input         io_sinkA_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_sinkA_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_sinkA_bits_snpHitReleaseMeta_accessed,
+  input         io_sinkA_bits_snpHitReleaseMeta_tagErr,
+  input         io_sinkA_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_sinkA_bits_tgtID,
+  input  [10:0] io_sinkA_bits_srcID,
+  input  [11:0] io_sinkA_bits_txnID,
+  input  [10:0] io_sinkA_bits_homeNID,
+  input  [11:0] io_sinkA_bits_dbID,
+  input  [10:0] io_sinkA_bits_fwdNID,
+  input  [11:0] io_sinkA_bits_fwdTxnID,
+  input  [6:0]  io_sinkA_bits_chiOpcode,
+  input  [2:0]  io_sinkA_bits_resp,
+  input  [2:0]  io_sinkA_bits_fwdState,
+  input  [3:0]  io_sinkA_bits_pCrdType,
+  input         io_sinkA_bits_retToSrc,
+  input         io_sinkA_bits_likelyshared,
+  input         io_sinkA_bits_expCompAck,
+  input         io_sinkA_bits_allowRetry,
+  input         io_sinkA_bits_memAttr_allocate,
+  input         io_sinkA_bits_memAttr_cacheable,
+  input         io_sinkA_bits_memAttr_device,
+  input         io_sinkA_bits_memAttr_ewa,
+  input         io_sinkA_bits_traceTag,
+  input  [33:0] io_ATag,
+  input  [7:0]  io_ASet,
+  output        io_s1Entrance_valid,
+  output [7:0]  io_s1Entrance_bits_set,
+  output        io_sinkB_ready,
+  input         io_sinkB_valid,
+  input  [2:0]  io_sinkB_bits_channel,
+  input  [2:0]  io_sinkB_bits_txChannel,
+  input  [7:0]  io_sinkB_bits_set,
+  input  [33:0] io_sinkB_bits_tag,
+  input  [5:0]  io_sinkB_bits_off,
+  input         io_sinkB_bits_alias,
+  input  [43:0] io_sinkB_bits_vaddr,
+  input         io_sinkB_bits_isKeyword,
+  input  [3:0]  io_sinkB_bits_opcode,
+  input  [2:0]  io_sinkB_bits_param,
+  input  [2:0]  io_sinkB_bits_size,
+  input  [6:0]  io_sinkB_bits_sourceId,
+  input  [1:0]  io_sinkB_bits_bufIdx,
+  input         io_sinkB_bits_needProbeAckData,
+  input         io_sinkB_bits_denied,
+  input         io_sinkB_bits_corrupt,
+  input         io_sinkB_bits_mshrTask,
+  input  [7:0]  io_sinkB_bits_mshrId,
+  input         io_sinkB_bits_aliasTask,
+  input         io_sinkB_bits_useProbeData,
+  input         io_sinkB_bits_mshrRetry,
+  input         io_sinkB_bits_readProbeDataDown,
+  input         io_sinkB_bits_fromL2pft,
+  input         io_sinkB_bits_needHint,
+  input         io_sinkB_bits_dirty,
+  input  [2:0]  io_sinkB_bits_way,
+  input         io_sinkB_bits_meta_dirty,
+  input  [1:0]  io_sinkB_bits_meta_state,
+  input         io_sinkB_bits_meta_clients,
+  input         io_sinkB_bits_meta_alias,
+  input         io_sinkB_bits_meta_prefetch,
+  input  [3:0]  io_sinkB_bits_meta_prefetchSrc,
+  input         io_sinkB_bits_meta_accessed,
+  input         io_sinkB_bits_meta_tagErr,
+  input         io_sinkB_bits_meta_dataErr,
+  input         io_sinkB_bits_metaWen,
+  input         io_sinkB_bits_tagWen,
+  input         io_sinkB_bits_dsWen,
+  input  [7:0]  io_sinkB_bits_wayMask,
+  input         io_sinkB_bits_replTask,
+  input         io_sinkB_bits_cmoTask,
+  input         io_sinkB_bits_cmoAll,
+  input  [4:0]  io_sinkB_bits_reqSource,
+  input         io_sinkB_bits_mergeA,
+  input  [5:0]  io_sinkB_bits_aMergeTask_off,
+  input         io_sinkB_bits_aMergeTask_alias,
+  input  [43:0] io_sinkB_bits_aMergeTask_vaddr,
+  input         io_sinkB_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_sinkB_bits_aMergeTask_opcode,
+  input  [2:0]  io_sinkB_bits_aMergeTask_param,
+  input  [6:0]  io_sinkB_bits_aMergeTask_sourceId,
+  input         io_sinkB_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_sinkB_bits_aMergeTask_meta_state,
+  input         io_sinkB_bits_aMergeTask_meta_clients,
+  input         io_sinkB_bits_aMergeTask_meta_alias,
+  input         io_sinkB_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_sinkB_bits_aMergeTask_meta_prefetchSrc,
+  input         io_sinkB_bits_aMergeTask_meta_accessed,
+  input         io_sinkB_bits_aMergeTask_meta_tagErr,
+  input         io_sinkB_bits_aMergeTask_meta_dataErr,
+  input         io_sinkB_bits_snpHitRelease,
+  input         io_sinkB_bits_snpHitReleaseToInval,
+  input         io_sinkB_bits_snpHitReleaseToClean,
+  input         io_sinkB_bits_snpHitReleaseWithData,
+  input  [7:0]  io_sinkB_bits_snpHitReleaseIdx,
+  input         io_sinkB_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_sinkB_bits_snpHitReleaseMeta_state,
+  input         io_sinkB_bits_snpHitReleaseMeta_clients,
+  input         io_sinkB_bits_snpHitReleaseMeta_alias,
+  input         io_sinkB_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_sinkB_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_sinkB_bits_snpHitReleaseMeta_accessed,
+  input         io_sinkB_bits_snpHitReleaseMeta_tagErr,
+  input         io_sinkB_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_sinkB_bits_tgtID,
+  input  [10:0] io_sinkB_bits_srcID,
+  input  [11:0] io_sinkB_bits_txnID,
+  input  [10:0] io_sinkB_bits_homeNID,
+  input  [11:0] io_sinkB_bits_dbID,
+  input  [10:0] io_sinkB_bits_fwdNID,
+  input  [11:0] io_sinkB_bits_fwdTxnID,
+  input  [6:0]  io_sinkB_bits_chiOpcode,
+  input  [2:0]  io_sinkB_bits_resp,
+  input  [2:0]  io_sinkB_bits_fwdState,
+  input  [3:0]  io_sinkB_bits_pCrdType,
+  input         io_sinkB_bits_retToSrc,
+  input         io_sinkB_bits_likelyshared,
+  input         io_sinkB_bits_expCompAck,
+  input         io_sinkB_bits_allowRetry,
+  input         io_sinkB_bits_memAttr_allocate,
+  input         io_sinkB_bits_memAttr_cacheable,
+  input         io_sinkB_bits_memAttr_device,
+  input         io_sinkB_bits_memAttr_ewa,
+  input         io_sinkB_bits_traceTag,
+  output        io_sinkC_ready,
+  input         io_sinkC_valid,
+  input  [2:0]  io_sinkC_bits_channel,
+  input  [2:0]  io_sinkC_bits_txChannel,
+  input  [7:0]  io_sinkC_bits_set,
+  input  [33:0] io_sinkC_bits_tag,
+  input  [5:0]  io_sinkC_bits_off,
+  input         io_sinkC_bits_alias,
+  input  [43:0] io_sinkC_bits_vaddr,
+  input         io_sinkC_bits_isKeyword,
+  input  [3:0]  io_sinkC_bits_opcode,
+  input  [2:0]  io_sinkC_bits_param,
+  input  [2:0]  io_sinkC_bits_size,
+  input  [6:0]  io_sinkC_bits_sourceId,
+  input  [1:0]  io_sinkC_bits_bufIdx,
+  input         io_sinkC_bits_needProbeAckData,
+  input         io_sinkC_bits_denied,
+  input         io_sinkC_bits_corrupt,
+  input         io_sinkC_bits_mshrTask,
+  input  [7:0]  io_sinkC_bits_mshrId,
+  input         io_sinkC_bits_aliasTask,
+  input         io_sinkC_bits_useProbeData,
+  input         io_sinkC_bits_mshrRetry,
+  input         io_sinkC_bits_readProbeDataDown,
+  input         io_sinkC_bits_fromL2pft,
+  input         io_sinkC_bits_needHint,
+  input         io_sinkC_bits_dirty,
+  input  [2:0]  io_sinkC_bits_way,
+  input         io_sinkC_bits_meta_dirty,
+  input  [1:0]  io_sinkC_bits_meta_state,
+  input         io_sinkC_bits_meta_clients,
+  input         io_sinkC_bits_meta_alias,
+  input         io_sinkC_bits_meta_prefetch,
+  input  [3:0]  io_sinkC_bits_meta_prefetchSrc,
+  input         io_sinkC_bits_meta_accessed,
+  input         io_sinkC_bits_meta_tagErr,
+  input         io_sinkC_bits_meta_dataErr,
+  input         io_sinkC_bits_metaWen,
+  input         io_sinkC_bits_tagWen,
+  input         io_sinkC_bits_dsWen,
+  input  [7:0]  io_sinkC_bits_wayMask,
+  input         io_sinkC_bits_replTask,
+  input         io_sinkC_bits_cmoTask,
+  input         io_sinkC_bits_cmoAll,
+  input  [4:0]  io_sinkC_bits_reqSource,
+  input         io_sinkC_bits_mergeA,
+  input  [5:0]  io_sinkC_bits_aMergeTask_off,
+  input         io_sinkC_bits_aMergeTask_alias,
+  input  [43:0] io_sinkC_bits_aMergeTask_vaddr,
+  input         io_sinkC_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_sinkC_bits_aMergeTask_opcode,
+  input  [2:0]  io_sinkC_bits_aMergeTask_param,
+  input  [6:0]  io_sinkC_bits_aMergeTask_sourceId,
+  input         io_sinkC_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_sinkC_bits_aMergeTask_meta_state,
+  input         io_sinkC_bits_aMergeTask_meta_clients,
+  input         io_sinkC_bits_aMergeTask_meta_alias,
+  input         io_sinkC_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_sinkC_bits_aMergeTask_meta_prefetchSrc,
+  input         io_sinkC_bits_aMergeTask_meta_accessed,
+  input         io_sinkC_bits_aMergeTask_meta_tagErr,
+  input         io_sinkC_bits_aMergeTask_meta_dataErr,
+  input         io_sinkC_bits_snpHitRelease,
+  input         io_sinkC_bits_snpHitReleaseToInval,
+  input         io_sinkC_bits_snpHitReleaseToClean,
+  input         io_sinkC_bits_snpHitReleaseWithData,
+  input  [7:0]  io_sinkC_bits_snpHitReleaseIdx,
+  input         io_sinkC_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_sinkC_bits_snpHitReleaseMeta_state,
+  input         io_sinkC_bits_snpHitReleaseMeta_clients,
+  input         io_sinkC_bits_snpHitReleaseMeta_alias,
+  input         io_sinkC_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_sinkC_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_sinkC_bits_snpHitReleaseMeta_accessed,
+  input         io_sinkC_bits_snpHitReleaseMeta_tagErr,
+  input         io_sinkC_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_sinkC_bits_tgtID,
+  input  [10:0] io_sinkC_bits_srcID,
+  input  [11:0] io_sinkC_bits_txnID,
+  input  [10:0] io_sinkC_bits_homeNID,
+  input  [11:0] io_sinkC_bits_dbID,
+  input  [10:0] io_sinkC_bits_fwdNID,
+  input  [11:0] io_sinkC_bits_fwdTxnID,
+  input  [6:0]  io_sinkC_bits_chiOpcode,
+  input  [2:0]  io_sinkC_bits_resp,
+  input  [2:0]  io_sinkC_bits_fwdState,
+  input  [3:0]  io_sinkC_bits_pCrdType,
+  input         io_sinkC_bits_retToSrc,
+  input         io_sinkC_bits_likelyshared,
+  input         io_sinkC_bits_expCompAck,
+  input         io_sinkC_bits_allowRetry,
+  input         io_sinkC_bits_memAttr_allocate,
+  input         io_sinkC_bits_memAttr_cacheable,
+  input         io_sinkC_bits_memAttr_device,
+  input         io_sinkC_bits_memAttr_ewa,
+  input         io_sinkC_bits_traceTag,
+  output        io_mshrTask_ready,
+  input         io_mshrTask_valid,
+  input  [2:0]  io_mshrTask_bits_channel,
+  input  [2:0]  io_mshrTask_bits_txChannel,
+  input  [7:0]  io_mshrTask_bits_set,
+  input  [33:0] io_mshrTask_bits_tag,
+  input  [5:0]  io_mshrTask_bits_off,
+  input         io_mshrTask_bits_alias,
+  input  [43:0] io_mshrTask_bits_vaddr,
+  input         io_mshrTask_bits_isKeyword,
+  input  [3:0]  io_mshrTask_bits_opcode,
+  input  [2:0]  io_mshrTask_bits_param,
+  input  [2:0]  io_mshrTask_bits_size,
+  input  [6:0]  io_mshrTask_bits_sourceId,
+  input  [1:0]  io_mshrTask_bits_bufIdx,
+  input         io_mshrTask_bits_needProbeAckData,
+  input         io_mshrTask_bits_denied,
+  input         io_mshrTask_bits_corrupt,
+  input         io_mshrTask_bits_mshrTask,
+  input  [7:0]  io_mshrTask_bits_mshrId,
+  input         io_mshrTask_bits_aliasTask,
+  input         io_mshrTask_bits_useProbeData,
+  input         io_mshrTask_bits_mshrRetry,
+  input         io_mshrTask_bits_readProbeDataDown,
+  input         io_mshrTask_bits_fromL2pft,
+  input         io_mshrTask_bits_needHint,
+  input         io_mshrTask_bits_dirty,
+  input  [2:0]  io_mshrTask_bits_way,
+  input         io_mshrTask_bits_meta_dirty,
+  input  [1:0]  io_mshrTask_bits_meta_state,
+  input         io_mshrTask_bits_meta_clients,
+  input         io_mshrTask_bits_meta_alias,
+  input         io_mshrTask_bits_meta_prefetch,
+  input  [3:0]  io_mshrTask_bits_meta_prefetchSrc,
+  input         io_mshrTask_bits_meta_accessed,
+  input         io_mshrTask_bits_meta_tagErr,
+  input         io_mshrTask_bits_meta_dataErr,
+  input         io_mshrTask_bits_metaWen,
+  input         io_mshrTask_bits_tagWen,
+  input         io_mshrTask_bits_dsWen,
+  input  [7:0]  io_mshrTask_bits_wayMask,
+  input         io_mshrTask_bits_replTask,
+  input         io_mshrTask_bits_cmoTask,
+  input         io_mshrTask_bits_cmoAll,
+  input  [4:0]  io_mshrTask_bits_reqSource,
+  input         io_mshrTask_bits_mergeA,
+  input  [5:0]  io_mshrTask_bits_aMergeTask_off,
+  input         io_mshrTask_bits_aMergeTask_alias,
+  input  [43:0] io_mshrTask_bits_aMergeTask_vaddr,
+  input         io_mshrTask_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_mshrTask_bits_aMergeTask_opcode,
+  input  [2:0]  io_mshrTask_bits_aMergeTask_param,
+  input  [6:0]  io_mshrTask_bits_aMergeTask_sourceId,
+  input         io_mshrTask_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_mshrTask_bits_aMergeTask_meta_state,
+  input         io_mshrTask_bits_aMergeTask_meta_clients,
+  input         io_mshrTask_bits_aMergeTask_meta_alias,
+  input         io_mshrTask_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_mshrTask_bits_aMergeTask_meta_prefetchSrc,
+  input         io_mshrTask_bits_aMergeTask_meta_accessed,
+  input         io_mshrTask_bits_aMergeTask_meta_tagErr,
+  input         io_mshrTask_bits_aMergeTask_meta_dataErr,
+  input         io_mshrTask_bits_snpHitRelease,
+  input         io_mshrTask_bits_snpHitReleaseToInval,
+  input         io_mshrTask_bits_snpHitReleaseToClean,
+  input         io_mshrTask_bits_snpHitReleaseWithData,
+  input  [7:0]  io_mshrTask_bits_snpHitReleaseIdx,
+  input         io_mshrTask_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_mshrTask_bits_snpHitReleaseMeta_state,
+  input         io_mshrTask_bits_snpHitReleaseMeta_clients,
+  input         io_mshrTask_bits_snpHitReleaseMeta_alias,
+  input         io_mshrTask_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_mshrTask_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_mshrTask_bits_snpHitReleaseMeta_accessed,
+  input         io_mshrTask_bits_snpHitReleaseMeta_tagErr,
+  input         io_mshrTask_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_mshrTask_bits_tgtID,
+  input  [10:0] io_mshrTask_bits_srcID,
+  input  [11:0] io_mshrTask_bits_txnID,
+  input  [10:0] io_mshrTask_bits_homeNID,
+  input  [11:0] io_mshrTask_bits_dbID,
+  input  [10:0] io_mshrTask_bits_fwdNID,
+  input  [11:0] io_mshrTask_bits_fwdTxnID,
+  input  [6:0]  io_mshrTask_bits_chiOpcode,
+  input  [2:0]  io_mshrTask_bits_resp,
+  input  [2:0]  io_mshrTask_bits_fwdState,
+  input  [3:0]  io_mshrTask_bits_pCrdType,
+  input         io_mshrTask_bits_retToSrc,
+  input         io_mshrTask_bits_likelyshared,
+  input         io_mshrTask_bits_expCompAck,
+  input         io_mshrTask_bits_allowRetry,
+  input         io_mshrTask_bits_memAttr_allocate,
+  input         io_mshrTask_bits_memAttr_cacheable,
+  input         io_mshrTask_bits_memAttr_device,
+  input         io_mshrTask_bits_memAttr_ewa,
+  input         io_mshrTask_bits_traceTag,
+  input         io_dirRead_s1_ready,
+  output        io_dirRead_s1_valid,
+  output [33:0] io_dirRead_s1_bits_tag,
+  output [7:0]  io_dirRead_s1_bits_set,
+  output [7:0]  io_dirRead_s1_bits_wayMask,
+  output [2:0]  io_dirRead_s1_bits_replacerInfo_channel,
+  output [2:0]  io_dirRead_s1_bits_replacerInfo_opcode,
+  output [4:0]  io_dirRead_s1_bits_replacerInfo_reqSource,
+  output        io_dirRead_s1_bits_replacerInfo_refill_prefetch,
+  output        io_dirRead_s1_bits_refill,
+  output [7:0]  io_dirRead_s1_bits_mshrId,
+  output        io_dirRead_s1_bits_cmoAll,
+  output [2:0]  io_dirRead_s1_bits_cmoWay,
+  output        io_taskToPipe_s2_valid,
+  output [2:0]  io_taskToPipe_s2_bits_channel,
+  output [2:0]  io_taskToPipe_s2_bits_txChannel,
+  output [7:0]  io_taskToPipe_s2_bits_set,
+  output [33:0] io_taskToPipe_s2_bits_tag,
+  output [5:0]  io_taskToPipe_s2_bits_off,
+  output        io_taskToPipe_s2_bits_alias,
+  output [43:0] io_taskToPipe_s2_bits_vaddr,
+  output        io_taskToPipe_s2_bits_isKeyword,
+  output [3:0]  io_taskToPipe_s2_bits_opcode,
+  output [2:0]  io_taskToPipe_s2_bits_param,
+  output [2:0]  io_taskToPipe_s2_bits_size,
+  output [6:0]  io_taskToPipe_s2_bits_sourceId,
+  output [1:0]  io_taskToPipe_s2_bits_bufIdx,
+  output        io_taskToPipe_s2_bits_needProbeAckData,
+  output        io_taskToPipe_s2_bits_denied,
+  output        io_taskToPipe_s2_bits_corrupt,
+  output        io_taskToPipe_s2_bits_mshrTask,
+  output [7:0]  io_taskToPipe_s2_bits_mshrId,
+  output        io_taskToPipe_s2_bits_aliasTask,
+  output        io_taskToPipe_s2_bits_useProbeData,
+  output        io_taskToPipe_s2_bits_mshrRetry,
+  output        io_taskToPipe_s2_bits_readProbeDataDown,
+  output        io_taskToPipe_s2_bits_fromL2pft,
+  output        io_taskToPipe_s2_bits_needHint,
+  output        io_taskToPipe_s2_bits_dirty,
+  output [2:0]  io_taskToPipe_s2_bits_way,
+  output        io_taskToPipe_s2_bits_meta_dirty,
+  output [1:0]  io_taskToPipe_s2_bits_meta_state,
+  output        io_taskToPipe_s2_bits_meta_clients,
+  output        io_taskToPipe_s2_bits_meta_alias,
+  output        io_taskToPipe_s2_bits_meta_prefetch,
+  output [3:0]  io_taskToPipe_s2_bits_meta_prefetchSrc,
+  output        io_taskToPipe_s2_bits_meta_accessed,
+  output        io_taskToPipe_s2_bits_meta_tagErr,
+  output        io_taskToPipe_s2_bits_meta_dataErr,
+  output        io_taskToPipe_s2_bits_metaWen,
+  output        io_taskToPipe_s2_bits_tagWen,
+  output        io_taskToPipe_s2_bits_dsWen,
+  output [7:0]  io_taskToPipe_s2_bits_wayMask,
+  output        io_taskToPipe_s2_bits_replTask,
+  output        io_taskToPipe_s2_bits_cmoTask,
+  output        io_taskToPipe_s2_bits_cmoAll,
+  output [4:0]  io_taskToPipe_s2_bits_reqSource,
+  output        io_taskToPipe_s2_bits_mergeA,
+  output [5:0]  io_taskToPipe_s2_bits_aMergeTask_off,
+  output        io_taskToPipe_s2_bits_aMergeTask_alias,
+  output [43:0] io_taskToPipe_s2_bits_aMergeTask_vaddr,
+  output        io_taskToPipe_s2_bits_aMergeTask_isKeyword,
+  output [2:0]  io_taskToPipe_s2_bits_aMergeTask_opcode,
+  output [2:0]  io_taskToPipe_s2_bits_aMergeTask_param,
+  output [6:0]  io_taskToPipe_s2_bits_aMergeTask_sourceId,
+  output        io_taskToPipe_s2_bits_aMergeTask_meta_dirty,
+  output [1:0]  io_taskToPipe_s2_bits_aMergeTask_meta_state,
+  output        io_taskToPipe_s2_bits_aMergeTask_meta_clients,
+  output        io_taskToPipe_s2_bits_aMergeTask_meta_alias,
+  output        io_taskToPipe_s2_bits_aMergeTask_meta_prefetch,
+  output [3:0]  io_taskToPipe_s2_bits_aMergeTask_meta_prefetchSrc,
+  output        io_taskToPipe_s2_bits_aMergeTask_meta_accessed,
+  output        io_taskToPipe_s2_bits_aMergeTask_meta_tagErr,
+  output        io_taskToPipe_s2_bits_aMergeTask_meta_dataErr,
+  output        io_taskToPipe_s2_bits_snpHitRelease,
+  output        io_taskToPipe_s2_bits_snpHitReleaseToInval,
+  output        io_taskToPipe_s2_bits_snpHitReleaseToClean,
+  output        io_taskToPipe_s2_bits_snpHitReleaseWithData,
+  output [7:0]  io_taskToPipe_s2_bits_snpHitReleaseIdx,
+  output        io_taskToPipe_s2_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_taskToPipe_s2_bits_snpHitReleaseMeta_state,
+  output        io_taskToPipe_s2_bits_snpHitReleaseMeta_clients,
+  output        io_taskToPipe_s2_bits_snpHitReleaseMeta_alias,
+  output        io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_taskToPipe_s2_bits_snpHitReleaseMeta_accessed,
+  output        io_taskToPipe_s2_bits_snpHitReleaseMeta_tagErr,
+  output        io_taskToPipe_s2_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_taskToPipe_s2_bits_tgtID,
+  output [10:0] io_taskToPipe_s2_bits_srcID,
+  output [11:0] io_taskToPipe_s2_bits_txnID,
+  output [10:0] io_taskToPipe_s2_bits_homeNID,
+  output [11:0] io_taskToPipe_s2_bits_dbID,
+  output [10:0] io_taskToPipe_s2_bits_fwdNID,
+  output [11:0] io_taskToPipe_s2_bits_fwdTxnID,
+  output [6:0]  io_taskToPipe_s2_bits_chiOpcode,
+  output [2:0]  io_taskToPipe_s2_bits_resp,
+  output [2:0]  io_taskToPipe_s2_bits_fwdState,
+  output [3:0]  io_taskToPipe_s2_bits_pCrdType,
+  output        io_taskToPipe_s2_bits_retToSrc,
+  output        io_taskToPipe_s2_bits_likelyshared,
+  output        io_taskToPipe_s2_bits_expCompAck,
+  output        io_taskToPipe_s2_bits_allowRetry,
+  output        io_taskToPipe_s2_bits_memAttr_allocate,
+  output        io_taskToPipe_s2_bits_memAttr_cacheable,
+  output        io_taskToPipe_s2_bits_memAttr_device,
+  output        io_taskToPipe_s2_bits_memAttr_ewa,
+  output        io_taskToPipe_s2_bits_traceTag,
+  output        io_mshrHintQInfo_valid,
+  output [2:0]  io_mshrHintQInfo_bits_channel,
+  output [2:0]  io_mshrHintQInfo_bits_txChannel,
+  output [7:0]  io_mshrHintQInfo_bits_set,
+  output [33:0] io_mshrHintQInfo_bits_tag,
+  output [5:0]  io_mshrHintQInfo_bits_off,
+  output        io_mshrHintQInfo_bits_alias,
+  output [43:0] io_mshrHintQInfo_bits_vaddr,
+  output        io_mshrHintQInfo_bits_isKeyword,
+  output [3:0]  io_mshrHintQInfo_bits_opcode,
+  output [2:0]  io_mshrHintQInfo_bits_param,
+  output [2:0]  io_mshrHintQInfo_bits_size,
+  output [6:0]  io_mshrHintQInfo_bits_sourceId,
+  output [1:0]  io_mshrHintQInfo_bits_bufIdx,
+  output        io_mshrHintQInfo_bits_needProbeAckData,
+  output        io_mshrHintQInfo_bits_denied,
+  output        io_mshrHintQInfo_bits_corrupt,
+  output        io_mshrHintQInfo_bits_mshrTask,
+  output [7:0]  io_mshrHintQInfo_bits_mshrId,
+  output        io_mshrHintQInfo_bits_aliasTask,
+  output        io_mshrHintQInfo_bits_useProbeData,
+  output        io_mshrHintQInfo_bits_mshrRetry,
+  output        io_mshrHintQInfo_bits_readProbeDataDown,
+  output        io_mshrHintQInfo_bits_fromL2pft,
+  output        io_mshrHintQInfo_bits_needHint,
+  output        io_mshrHintQInfo_bits_dirty,
+  output [2:0]  io_mshrHintQInfo_bits_way,
+  output        io_mshrHintQInfo_bits_meta_dirty,
+  output [1:0]  io_mshrHintQInfo_bits_meta_state,
+  output        io_mshrHintQInfo_bits_meta_clients,
+  output        io_mshrHintQInfo_bits_meta_alias,
+  output        io_mshrHintQInfo_bits_meta_prefetch,
+  output [3:0]  io_mshrHintQInfo_bits_meta_prefetchSrc,
+  output        io_mshrHintQInfo_bits_meta_accessed,
+  output        io_mshrHintQInfo_bits_meta_tagErr,
+  output        io_mshrHintQInfo_bits_meta_dataErr,
+  output        io_mshrHintQInfo_bits_metaWen,
+  output        io_mshrHintQInfo_bits_tagWen,
+  output        io_mshrHintQInfo_bits_dsWen,
+  output [7:0]  io_mshrHintQInfo_bits_wayMask,
+  output        io_mshrHintQInfo_bits_replTask,
+  output        io_mshrHintQInfo_bits_cmoTask,
+  output        io_mshrHintQInfo_bits_cmoAll,
+  output [4:0]  io_mshrHintQInfo_bits_reqSource,
+  output        io_mshrHintQInfo_bits_mergeA,
+  output [5:0]  io_mshrHintQInfo_bits_aMergeTask_off,
+  output        io_mshrHintQInfo_bits_aMergeTask_alias,
+  output [43:0] io_mshrHintQInfo_bits_aMergeTask_vaddr,
+  output        io_mshrHintQInfo_bits_aMergeTask_isKeyword,
+  output [2:0]  io_mshrHintQInfo_bits_aMergeTask_opcode,
+  output [2:0]  io_mshrHintQInfo_bits_aMergeTask_param,
+  output [6:0]  io_mshrHintQInfo_bits_aMergeTask_sourceId,
+  output        io_mshrHintQInfo_bits_aMergeTask_meta_dirty,
+  output [1:0]  io_mshrHintQInfo_bits_aMergeTask_meta_state,
+  output        io_mshrHintQInfo_bits_aMergeTask_meta_clients,
+  output        io_mshrHintQInfo_bits_aMergeTask_meta_alias,
+  output        io_mshrHintQInfo_bits_aMergeTask_meta_prefetch,
+  output [3:0]  io_mshrHintQInfo_bits_aMergeTask_meta_prefetchSrc,
+  output        io_mshrHintQInfo_bits_aMergeTask_meta_accessed,
+  output        io_mshrHintQInfo_bits_aMergeTask_meta_tagErr,
+  output        io_mshrHintQInfo_bits_aMergeTask_meta_dataErr,
+  output        io_mshrHintQInfo_bits_snpHitRelease,
+  output        io_mshrHintQInfo_bits_snpHitReleaseToInval,
+  output        io_mshrHintQInfo_bits_snpHitReleaseToClean,
+  output        io_mshrHintQInfo_bits_snpHitReleaseWithData,
+  output [7:0]  io_mshrHintQInfo_bits_snpHitReleaseIdx,
+  output        io_mshrHintQInfo_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_mshrHintQInfo_bits_snpHitReleaseMeta_state,
+  output        io_mshrHintQInfo_bits_snpHitReleaseMeta_clients,
+  output        io_mshrHintQInfo_bits_snpHitReleaseMeta_alias,
+  output        io_mshrHintQInfo_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_mshrHintQInfo_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_mshrHintQInfo_bits_snpHitReleaseMeta_accessed,
+  output        io_mshrHintQInfo_bits_snpHitReleaseMeta_tagErr,
+  output        io_mshrHintQInfo_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_mshrHintQInfo_bits_tgtID,
+  output [10:0] io_mshrHintQInfo_bits_srcID,
+  output [11:0] io_mshrHintQInfo_bits_txnID,
+  output [10:0] io_mshrHintQInfo_bits_homeNID,
+  output [11:0] io_mshrHintQInfo_bits_dbID,
+  output [10:0] io_mshrHintQInfo_bits_fwdNID,
+  output [11:0] io_mshrHintQInfo_bits_fwdTxnID,
+  output [6:0]  io_mshrHintQInfo_bits_chiOpcode,
+  output [2:0]  io_mshrHintQInfo_bits_resp,
+  output [2:0]  io_mshrHintQInfo_bits_fwdState,
+  output [3:0]  io_mshrHintQInfo_bits_pCrdType,
+  output        io_mshrHintQInfo_bits_retToSrc,
+  output        io_mshrHintQInfo_bits_likelyshared,
+  output        io_mshrHintQInfo_bits_expCompAck,
+  output        io_mshrHintQInfo_bits_allowRetry,
+  output        io_mshrHintQInfo_bits_memAttr_allocate,
+  output        io_mshrHintQInfo_bits_memAttr_cacheable,
+  output        io_mshrHintQInfo_bits_memAttr_device,
+  output        io_mshrHintQInfo_bits_memAttr_ewa,
+  output        io_mshrHintQInfo_bits_traceTag,
+  output        io_sinkCHintQInfo_valid,
+  output [2:0]  io_sinkCHintQInfo_bits_channel,
+  output [2:0]  io_sinkCHintQInfo_bits_txChannel,
+  output [7:0]  io_sinkCHintQInfo_bits_set,
+  output [33:0] io_sinkCHintQInfo_bits_tag,
+  output [5:0]  io_sinkCHintQInfo_bits_off,
+  output        io_sinkCHintQInfo_bits_alias,
+  output [43:0] io_sinkCHintQInfo_bits_vaddr,
+  output        io_sinkCHintQInfo_bits_isKeyword,
+  output [3:0]  io_sinkCHintQInfo_bits_opcode,
+  output [2:0]  io_sinkCHintQInfo_bits_param,
+  output [2:0]  io_sinkCHintQInfo_bits_size,
+  output [6:0]  io_sinkCHintQInfo_bits_sourceId,
+  output [1:0]  io_sinkCHintQInfo_bits_bufIdx,
+  output        io_sinkCHintQInfo_bits_needProbeAckData,
+  output        io_sinkCHintQInfo_bits_denied,
+  output        io_sinkCHintQInfo_bits_corrupt,
+  output        io_sinkCHintQInfo_bits_mshrTask,
+  output [7:0]  io_sinkCHintQInfo_bits_mshrId,
+  output        io_sinkCHintQInfo_bits_aliasTask,
+  output        io_sinkCHintQInfo_bits_useProbeData,
+  output        io_sinkCHintQInfo_bits_mshrRetry,
+  output        io_sinkCHintQInfo_bits_readProbeDataDown,
+  output        io_sinkCHintQInfo_bits_fromL2pft,
+  output        io_sinkCHintQInfo_bits_needHint,
+  output        io_sinkCHintQInfo_bits_dirty,
+  output [2:0]  io_sinkCHintQInfo_bits_way,
+  output        io_sinkCHintQInfo_bits_meta_dirty,
+  output [1:0]  io_sinkCHintQInfo_bits_meta_state,
+  output        io_sinkCHintQInfo_bits_meta_clients,
+  output        io_sinkCHintQInfo_bits_meta_alias,
+  output        io_sinkCHintQInfo_bits_meta_prefetch,
+  output [3:0]  io_sinkCHintQInfo_bits_meta_prefetchSrc,
+  output        io_sinkCHintQInfo_bits_meta_accessed,
+  output        io_sinkCHintQInfo_bits_meta_tagErr,
+  output        io_sinkCHintQInfo_bits_meta_dataErr,
+  output        io_sinkCHintQInfo_bits_metaWen,
+  output        io_sinkCHintQInfo_bits_tagWen,
+  output        io_sinkCHintQInfo_bits_dsWen,
+  output [7:0]  io_sinkCHintQInfo_bits_wayMask,
+  output        io_sinkCHintQInfo_bits_replTask,
+  output        io_sinkCHintQInfo_bits_cmoTask,
+  output        io_sinkCHintQInfo_bits_cmoAll,
+  output [4:0]  io_sinkCHintQInfo_bits_reqSource,
+  output        io_sinkCHintQInfo_bits_mergeA,
+  output [5:0]  io_sinkCHintQInfo_bits_aMergeTask_off,
+  output        io_sinkCHintQInfo_bits_aMergeTask_alias,
+  output [43:0] io_sinkCHintQInfo_bits_aMergeTask_vaddr,
+  output        io_sinkCHintQInfo_bits_aMergeTask_isKeyword,
+  output [2:0]  io_sinkCHintQInfo_bits_aMergeTask_opcode,
+  output [2:0]  io_sinkCHintQInfo_bits_aMergeTask_param,
+  output [6:0]  io_sinkCHintQInfo_bits_aMergeTask_sourceId,
+  output        io_sinkCHintQInfo_bits_aMergeTask_meta_dirty,
+  output [1:0]  io_sinkCHintQInfo_bits_aMergeTask_meta_state,
+  output        io_sinkCHintQInfo_bits_aMergeTask_meta_clients,
+  output        io_sinkCHintQInfo_bits_aMergeTask_meta_alias,
+  output        io_sinkCHintQInfo_bits_aMergeTask_meta_prefetch,
+  output [3:0]  io_sinkCHintQInfo_bits_aMergeTask_meta_prefetchSrc,
+  output        io_sinkCHintQInfo_bits_aMergeTask_meta_accessed,
+  output        io_sinkCHintQInfo_bits_aMergeTask_meta_tagErr,
+  output        io_sinkCHintQInfo_bits_aMergeTask_meta_dataErr,
+  output        io_sinkCHintQInfo_bits_snpHitRelease,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseToInval,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseToClean,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseWithData,
+  output [7:0]  io_sinkCHintQInfo_bits_snpHitReleaseIdx,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_sinkCHintQInfo_bits_snpHitReleaseMeta_state,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseMeta_clients,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseMeta_alias,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_sinkCHintQInfo_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseMeta_accessed,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseMeta_tagErr,
+  output        io_sinkCHintQInfo_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_sinkCHintQInfo_bits_tgtID,
+  output [10:0] io_sinkCHintQInfo_bits_srcID,
+  output [11:0] io_sinkCHintQInfo_bits_txnID,
+  output [10:0] io_sinkCHintQInfo_bits_homeNID,
+  output [11:0] io_sinkCHintQInfo_bits_dbID,
+  output [10:0] io_sinkCHintQInfo_bits_fwdNID,
+  output [11:0] io_sinkCHintQInfo_bits_fwdTxnID,
+  output [6:0]  io_sinkCHintQInfo_bits_chiOpcode,
+  output [2:0]  io_sinkCHintQInfo_bits_resp,
+  output [2:0]  io_sinkCHintQInfo_bits_fwdState,
+  output [3:0]  io_sinkCHintQInfo_bits_pCrdType,
+  output        io_sinkCHintQInfo_bits_retToSrc,
+  output        io_sinkCHintQInfo_bits_likelyshared,
+  output        io_sinkCHintQInfo_bits_expCompAck,
+  output        io_sinkCHintQInfo_bits_allowRetry,
+  output        io_sinkCHintQInfo_bits_memAttr_allocate,
+  output        io_sinkCHintQInfo_bits_memAttr_cacheable,
+  output        io_sinkCHintQInfo_bits_memAttr_device,
+  output        io_sinkCHintQInfo_bits_memAttr_ewa,
+  output        io_sinkCHintQInfo_bits_traceTag,
+  output        io_refillBufRead_s2_valid,
+  output [7:0]  io_refillBufRead_s2_bits_id,
+  output        io_releaseBufRead_s2_valid,
+  output [7:0]  io_releaseBufRead_s2_bits_id,
+  output [33:0] io_status_s1_tags_0,
+  output [33:0] io_status_s1_tags_1,
+  output [33:0] io_status_s1_tags_2,
+  output [33:0] io_status_s1_tags_3,
+  output [7:0]  io_status_s1_sets_0,
+  output [7:0]  io_status_s1_sets_1,
+  output [7:0]  io_status_s1_sets_2,
+  output [7:0]  io_status_s1_sets_3,
+  output        io_status_vec_0_valid,
+  output [2:0]  io_status_vec_0_bits_channel,
+  output        io_status_vec_1_valid,
+  output [2:0]  io_status_vec_1_bits_channel,
+  output        io_status_vec_toTX_0_valid,
+  output [2:0]  io_status_vec_toTX_0_bits_channel,
+  output [2:0]  io_status_vec_toTX_0_bits_txChannel,
+  output        io_status_vec_toTX_0_bits_mshrTask,
+  output        io_status_vec_toTX_1_valid,
+  output [2:0]  io_status_vec_toTX_1_bits_channel,
+  output [2:0]  io_status_vec_toTX_1_bits_txChannel,
+  output        io_status_vec_toTX_1_bits_mshrTask,
+  input         io_fromMSHRCtl_blockG_s1,
+  input         io_fromMSHRCtl_blockA_s1,
+  input         io_fromMSHRCtl_blockB_s1,
+  input         io_fromMSHRCtl_blockC_s1,
+  input         io_fromMainPipe_blockG_s1,
+  input         io_fromMainPipe_blockA_s1,
+  input         io_fromMainPipe_blockB_s1,
+  input         io_fromMainPipe_blockC_s1,
+  input         io_fromGrantBuffer_blockSinkReqEntrance_blockG_s1,
+  input         io_fromGrantBuffer_blockSinkReqEntrance_blockA_s1,
+  input         io_fromGrantBuffer_blockSinkReqEntrance_blockB_s1,
+  input         io_fromGrantBuffer_blockSinkReqEntrance_blockC_s1,
+  input         io_fromGrantBuffer_blockMSHRReqEntrance,
+  input         io_fromTXDAT_blockMSHRReqEntrance,
+  input         io_fromTXDAT_blockSinkBReqEntrance,
+  input         io_fromTXRSP_blockMSHRReqEntrance,
+  input         io_fromTXRSP_blockSinkBReqEntrance,
+  input         io_fromTXREQ_blockMSHRReqEntrance,
+  input         io_msInfo_0_valid,
+  input  [2:0]  io_msInfo_0_bits_channel,
+  input  [7:0]  io_msInfo_0_bits_set,
+  input  [2:0]  io_msInfo_0_bits_way,
+  input  [33:0] io_msInfo_0_bits_reqTag,
+  input  [4:0]  io_msInfo_0_bits_reqSource,
+  input         io_msInfo_0_bits_willFree,
+  input         io_msInfo_0_bits_aliasTask,
+  input         io_msInfo_0_bits_needRelease,
+  input         io_msInfo_0_bits_blockRefill,
+  input         io_msInfo_0_bits_meta_dirty,
+  input  [1:0]  io_msInfo_0_bits_meta_state,
+  input         io_msInfo_0_bits_meta_clients,
+  input         io_msInfo_0_bits_meta_alias,
+  input         io_msInfo_0_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_0_bits_meta_prefetchSrc,
+  input         io_msInfo_0_bits_meta_accessed,
+  input         io_msInfo_0_bits_meta_tagErr,
+  input         io_msInfo_0_bits_meta_dataErr,
+  input  [33:0] io_msInfo_0_bits_metaTag,
+  input         io_msInfo_0_bits_dirHit,
+  input         io_msInfo_0_bits_isAcqOrPrefetch,
+  input         io_msInfo_0_bits_isPrefetch,
+  input  [2:0]  io_msInfo_0_bits_param,
+  input         io_msInfo_0_bits_mergeA,
+  input         io_msInfo_0_bits_w_grantfirst,
+  input         io_msInfo_0_bits_w_grantlast,
+  input         io_msInfo_0_bits_w_grant,
+  input         io_msInfo_0_bits_s_release,
+  input         io_msInfo_0_bits_s_refill,
+  input         io_msInfo_0_bits_s_cmoresp,
+  input         io_msInfo_0_bits_s_cmometaw,
+  input         io_msInfo_0_bits_w_releaseack,
+  input         io_msInfo_0_bits_w_replResp,
+  input         io_msInfo_0_bits_w_rprobeacklast,
+  input         io_msInfo_0_bits_replaceData,
+  input         io_msInfo_0_bits_releaseToClean,
+  input         io_msInfo_1_valid,
+  input  [2:0]  io_msInfo_1_bits_channel,
+  input  [7:0]  io_msInfo_1_bits_set,
+  input  [2:0]  io_msInfo_1_bits_way,
+  input  [33:0] io_msInfo_1_bits_reqTag,
+  input  [4:0]  io_msInfo_1_bits_reqSource,
+  input         io_msInfo_1_bits_willFree,
+  input         io_msInfo_1_bits_aliasTask,
+  input         io_msInfo_1_bits_needRelease,
+  input         io_msInfo_1_bits_blockRefill,
+  input         io_msInfo_1_bits_meta_dirty,
+  input  [1:0]  io_msInfo_1_bits_meta_state,
+  input         io_msInfo_1_bits_meta_clients,
+  input         io_msInfo_1_bits_meta_alias,
+  input         io_msInfo_1_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_1_bits_meta_prefetchSrc,
+  input         io_msInfo_1_bits_meta_accessed,
+  input         io_msInfo_1_bits_meta_tagErr,
+  input         io_msInfo_1_bits_meta_dataErr,
+  input  [33:0] io_msInfo_1_bits_metaTag,
+  input         io_msInfo_1_bits_dirHit,
+  input         io_msInfo_1_bits_isAcqOrPrefetch,
+  input         io_msInfo_1_bits_isPrefetch,
+  input  [2:0]  io_msInfo_1_bits_param,
+  input         io_msInfo_1_bits_mergeA,
+  input         io_msInfo_1_bits_w_grantfirst,
+  input         io_msInfo_1_bits_w_grantlast,
+  input         io_msInfo_1_bits_w_grant,
+  input         io_msInfo_1_bits_s_release,
+  input         io_msInfo_1_bits_s_refill,
+  input         io_msInfo_1_bits_s_cmoresp,
+  input         io_msInfo_1_bits_s_cmometaw,
+  input         io_msInfo_1_bits_w_releaseack,
+  input         io_msInfo_1_bits_w_replResp,
+  input         io_msInfo_1_bits_w_rprobeacklast,
+  input         io_msInfo_1_bits_replaceData,
+  input         io_msInfo_1_bits_releaseToClean,
+  input         io_msInfo_2_valid,
+  input  [2:0]  io_msInfo_2_bits_channel,
+  input  [7:0]  io_msInfo_2_bits_set,
+  input  [2:0]  io_msInfo_2_bits_way,
+  input  [33:0] io_msInfo_2_bits_reqTag,
+  input  [4:0]  io_msInfo_2_bits_reqSource,
+  input         io_msInfo_2_bits_willFree,
+  input         io_msInfo_2_bits_aliasTask,
+  input         io_msInfo_2_bits_needRelease,
+  input         io_msInfo_2_bits_blockRefill,
+  input         io_msInfo_2_bits_meta_dirty,
+  input  [1:0]  io_msInfo_2_bits_meta_state,
+  input         io_msInfo_2_bits_meta_clients,
+  input         io_msInfo_2_bits_meta_alias,
+  input         io_msInfo_2_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_2_bits_meta_prefetchSrc,
+  input         io_msInfo_2_bits_meta_accessed,
+  input         io_msInfo_2_bits_meta_tagErr,
+  input         io_msInfo_2_bits_meta_dataErr,
+  input  [33:0] io_msInfo_2_bits_metaTag,
+  input         io_msInfo_2_bits_dirHit,
+  input         io_msInfo_2_bits_isAcqOrPrefetch,
+  input         io_msInfo_2_bits_isPrefetch,
+  input  [2:0]  io_msInfo_2_bits_param,
+  input         io_msInfo_2_bits_mergeA,
+  input         io_msInfo_2_bits_w_grantfirst,
+  input         io_msInfo_2_bits_w_grantlast,
+  input         io_msInfo_2_bits_w_grant,
+  input         io_msInfo_2_bits_s_release,
+  input         io_msInfo_2_bits_s_refill,
+  input         io_msInfo_2_bits_s_cmoresp,
+  input         io_msInfo_2_bits_s_cmometaw,
+  input         io_msInfo_2_bits_w_releaseack,
+  input         io_msInfo_2_bits_w_replResp,
+  input         io_msInfo_2_bits_w_rprobeacklast,
+  input         io_msInfo_2_bits_replaceData,
+  input         io_msInfo_2_bits_releaseToClean,
+  input         io_msInfo_3_valid,
+  input  [2:0]  io_msInfo_3_bits_channel,
+  input  [7:0]  io_msInfo_3_bits_set,
+  input  [2:0]  io_msInfo_3_bits_way,
+  input  [33:0] io_msInfo_3_bits_reqTag,
+  input  [4:0]  io_msInfo_3_bits_reqSource,
+  input         io_msInfo_3_bits_willFree,
+  input         io_msInfo_3_bits_aliasTask,
+  input         io_msInfo_3_bits_needRelease,
+  input         io_msInfo_3_bits_blockRefill,
+  input         io_msInfo_3_bits_meta_dirty,
+  input  [1:0]  io_msInfo_3_bits_meta_state,
+  input         io_msInfo_3_bits_meta_clients,
+  input         io_msInfo_3_bits_meta_alias,
+  input         io_msInfo_3_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_3_bits_meta_prefetchSrc,
+  input         io_msInfo_3_bits_meta_accessed,
+  input         io_msInfo_3_bits_meta_tagErr,
+  input         io_msInfo_3_bits_meta_dataErr,
+  input  [33:0] io_msInfo_3_bits_metaTag,
+  input         io_msInfo_3_bits_dirHit,
+  input         io_msInfo_3_bits_isAcqOrPrefetch,
+  input         io_msInfo_3_bits_isPrefetch,
+  input  [2:0]  io_msInfo_3_bits_param,
+  input         io_msInfo_3_bits_mergeA,
+  input         io_msInfo_3_bits_w_grantfirst,
+  input         io_msInfo_3_bits_w_grantlast,
+  input         io_msInfo_3_bits_w_grant,
+  input         io_msInfo_3_bits_s_release,
+  input         io_msInfo_3_bits_s_refill,
+  input         io_msInfo_3_bits_s_cmoresp,
+  input         io_msInfo_3_bits_s_cmometaw,
+  input         io_msInfo_3_bits_w_releaseack,
+  input         io_msInfo_3_bits_w_replResp,
+  input         io_msInfo_3_bits_w_rprobeacklast,
+  input         io_msInfo_3_bits_replaceData,
+  input         io_msInfo_3_bits_releaseToClean,
+  input         io_msInfo_4_valid,
+  input  [2:0]  io_msInfo_4_bits_channel,
+  input  [7:0]  io_msInfo_4_bits_set,
+  input  [2:0]  io_msInfo_4_bits_way,
+  input  [33:0] io_msInfo_4_bits_reqTag,
+  input  [4:0]  io_msInfo_4_bits_reqSource,
+  input         io_msInfo_4_bits_willFree,
+  input         io_msInfo_4_bits_aliasTask,
+  input         io_msInfo_4_bits_needRelease,
+  input         io_msInfo_4_bits_blockRefill,
+  input         io_msInfo_4_bits_meta_dirty,
+  input  [1:0]  io_msInfo_4_bits_meta_state,
+  input         io_msInfo_4_bits_meta_clients,
+  input         io_msInfo_4_bits_meta_alias,
+  input         io_msInfo_4_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_4_bits_meta_prefetchSrc,
+  input         io_msInfo_4_bits_meta_accessed,
+  input         io_msInfo_4_bits_meta_tagErr,
+  input         io_msInfo_4_bits_meta_dataErr,
+  input  [33:0] io_msInfo_4_bits_metaTag,
+  input         io_msInfo_4_bits_dirHit,
+  input         io_msInfo_4_bits_isAcqOrPrefetch,
+  input         io_msInfo_4_bits_isPrefetch,
+  input  [2:0]  io_msInfo_4_bits_param,
+  input         io_msInfo_4_bits_mergeA,
+  input         io_msInfo_4_bits_w_grantfirst,
+  input         io_msInfo_4_bits_w_grantlast,
+  input         io_msInfo_4_bits_w_grant,
+  input         io_msInfo_4_bits_s_release,
+  input         io_msInfo_4_bits_s_refill,
+  input         io_msInfo_4_bits_s_cmoresp,
+  input         io_msInfo_4_bits_s_cmometaw,
+  input         io_msInfo_4_bits_w_releaseack,
+  input         io_msInfo_4_bits_w_replResp,
+  input         io_msInfo_4_bits_w_rprobeacklast,
+  input         io_msInfo_4_bits_replaceData,
+  input         io_msInfo_4_bits_releaseToClean,
+  input         io_msInfo_5_valid,
+  input  [2:0]  io_msInfo_5_bits_channel,
+  input  [7:0]  io_msInfo_5_bits_set,
+  input  [2:0]  io_msInfo_5_bits_way,
+  input  [33:0] io_msInfo_5_bits_reqTag,
+  input  [4:0]  io_msInfo_5_bits_reqSource,
+  input         io_msInfo_5_bits_willFree,
+  input         io_msInfo_5_bits_aliasTask,
+  input         io_msInfo_5_bits_needRelease,
+  input         io_msInfo_5_bits_blockRefill,
+  input         io_msInfo_5_bits_meta_dirty,
+  input  [1:0]  io_msInfo_5_bits_meta_state,
+  input         io_msInfo_5_bits_meta_clients,
+  input         io_msInfo_5_bits_meta_alias,
+  input         io_msInfo_5_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_5_bits_meta_prefetchSrc,
+  input         io_msInfo_5_bits_meta_accessed,
+  input         io_msInfo_5_bits_meta_tagErr,
+  input         io_msInfo_5_bits_meta_dataErr,
+  input  [33:0] io_msInfo_5_bits_metaTag,
+  input         io_msInfo_5_bits_dirHit,
+  input         io_msInfo_5_bits_isAcqOrPrefetch,
+  input         io_msInfo_5_bits_isPrefetch,
+  input  [2:0]  io_msInfo_5_bits_param,
+  input         io_msInfo_5_bits_mergeA,
+  input         io_msInfo_5_bits_w_grantfirst,
+  input         io_msInfo_5_bits_w_grantlast,
+  input         io_msInfo_5_bits_w_grant,
+  input         io_msInfo_5_bits_s_release,
+  input         io_msInfo_5_bits_s_refill,
+  input         io_msInfo_5_bits_s_cmoresp,
+  input         io_msInfo_5_bits_s_cmometaw,
+  input         io_msInfo_5_bits_w_releaseack,
+  input         io_msInfo_5_bits_w_replResp,
+  input         io_msInfo_5_bits_w_rprobeacklast,
+  input         io_msInfo_5_bits_replaceData,
+  input         io_msInfo_5_bits_releaseToClean,
+  input         io_msInfo_6_valid,
+  input  [2:0]  io_msInfo_6_bits_channel,
+  input  [7:0]  io_msInfo_6_bits_set,
+  input  [2:0]  io_msInfo_6_bits_way,
+  input  [33:0] io_msInfo_6_bits_reqTag,
+  input  [4:0]  io_msInfo_6_bits_reqSource,
+  input         io_msInfo_6_bits_willFree,
+  input         io_msInfo_6_bits_aliasTask,
+  input         io_msInfo_6_bits_needRelease,
+  input         io_msInfo_6_bits_blockRefill,
+  input         io_msInfo_6_bits_meta_dirty,
+  input  [1:0]  io_msInfo_6_bits_meta_state,
+  input         io_msInfo_6_bits_meta_clients,
+  input         io_msInfo_6_bits_meta_alias,
+  input         io_msInfo_6_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_6_bits_meta_prefetchSrc,
+  input         io_msInfo_6_bits_meta_accessed,
+  input         io_msInfo_6_bits_meta_tagErr,
+  input         io_msInfo_6_bits_meta_dataErr,
+  input  [33:0] io_msInfo_6_bits_metaTag,
+  input         io_msInfo_6_bits_dirHit,
+  input         io_msInfo_6_bits_isAcqOrPrefetch,
+  input         io_msInfo_6_bits_isPrefetch,
+  input  [2:0]  io_msInfo_6_bits_param,
+  input         io_msInfo_6_bits_mergeA,
+  input         io_msInfo_6_bits_w_grantfirst,
+  input         io_msInfo_6_bits_w_grantlast,
+  input         io_msInfo_6_bits_w_grant,
+  input         io_msInfo_6_bits_s_release,
+  input         io_msInfo_6_bits_s_refill,
+  input         io_msInfo_6_bits_s_cmoresp,
+  input         io_msInfo_6_bits_s_cmometaw,
+  input         io_msInfo_6_bits_w_releaseack,
+  input         io_msInfo_6_bits_w_replResp,
+  input         io_msInfo_6_bits_w_rprobeacklast,
+  input         io_msInfo_6_bits_replaceData,
+  input         io_msInfo_6_bits_releaseToClean,
+  input         io_msInfo_7_valid,
+  input  [2:0]  io_msInfo_7_bits_channel,
+  input  [7:0]  io_msInfo_7_bits_set,
+  input  [2:0]  io_msInfo_7_bits_way,
+  input  [33:0] io_msInfo_7_bits_reqTag,
+  input  [4:0]  io_msInfo_7_bits_reqSource,
+  input         io_msInfo_7_bits_willFree,
+  input         io_msInfo_7_bits_aliasTask,
+  input         io_msInfo_7_bits_needRelease,
+  input         io_msInfo_7_bits_blockRefill,
+  input         io_msInfo_7_bits_meta_dirty,
+  input  [1:0]  io_msInfo_7_bits_meta_state,
+  input         io_msInfo_7_bits_meta_clients,
+  input         io_msInfo_7_bits_meta_alias,
+  input         io_msInfo_7_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_7_bits_meta_prefetchSrc,
+  input         io_msInfo_7_bits_meta_accessed,
+  input         io_msInfo_7_bits_meta_tagErr,
+  input         io_msInfo_7_bits_meta_dataErr,
+  input  [33:0] io_msInfo_7_bits_metaTag,
+  input         io_msInfo_7_bits_dirHit,
+  input         io_msInfo_7_bits_isAcqOrPrefetch,
+  input         io_msInfo_7_bits_isPrefetch,
+  input  [2:0]  io_msInfo_7_bits_param,
+  input         io_msInfo_7_bits_mergeA,
+  input         io_msInfo_7_bits_w_grantfirst,
+  input         io_msInfo_7_bits_w_grantlast,
+  input         io_msInfo_7_bits_w_grant,
+  input         io_msInfo_7_bits_s_release,
+  input         io_msInfo_7_bits_s_refill,
+  input         io_msInfo_7_bits_s_cmoresp,
+  input         io_msInfo_7_bits_s_cmometaw,
+  input         io_msInfo_7_bits_w_releaseack,
+  input         io_msInfo_7_bits_w_replResp,
+  input         io_msInfo_7_bits_w_rprobeacklast,
+  input         io_msInfo_7_bits_replaceData,
+  input         io_msInfo_7_bits_releaseToClean,
+  input         io_msInfo_8_valid,
+  input  [2:0]  io_msInfo_8_bits_channel,
+  input  [7:0]  io_msInfo_8_bits_set,
+  input  [2:0]  io_msInfo_8_bits_way,
+  input  [33:0] io_msInfo_8_bits_reqTag,
+  input  [4:0]  io_msInfo_8_bits_reqSource,
+  input         io_msInfo_8_bits_willFree,
+  input         io_msInfo_8_bits_aliasTask,
+  input         io_msInfo_8_bits_needRelease,
+  input         io_msInfo_8_bits_blockRefill,
+  input         io_msInfo_8_bits_meta_dirty,
+  input  [1:0]  io_msInfo_8_bits_meta_state,
+  input         io_msInfo_8_bits_meta_clients,
+  input         io_msInfo_8_bits_meta_alias,
+  input         io_msInfo_8_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_8_bits_meta_prefetchSrc,
+  input         io_msInfo_8_bits_meta_accessed,
+  input         io_msInfo_8_bits_meta_tagErr,
+  input         io_msInfo_8_bits_meta_dataErr,
+  input  [33:0] io_msInfo_8_bits_metaTag,
+  input         io_msInfo_8_bits_dirHit,
+  input         io_msInfo_8_bits_isAcqOrPrefetch,
+  input         io_msInfo_8_bits_isPrefetch,
+  input  [2:0]  io_msInfo_8_bits_param,
+  input         io_msInfo_8_bits_mergeA,
+  input         io_msInfo_8_bits_w_grantfirst,
+  input         io_msInfo_8_bits_w_grantlast,
+  input         io_msInfo_8_bits_w_grant,
+  input         io_msInfo_8_bits_s_release,
+  input         io_msInfo_8_bits_s_refill,
+  input         io_msInfo_8_bits_s_cmoresp,
+  input         io_msInfo_8_bits_s_cmometaw,
+  input         io_msInfo_8_bits_w_releaseack,
+  input         io_msInfo_8_bits_w_replResp,
+  input         io_msInfo_8_bits_w_rprobeacklast,
+  input         io_msInfo_8_bits_replaceData,
+  input         io_msInfo_8_bits_releaseToClean,
+  input         io_msInfo_9_valid,
+  input  [2:0]  io_msInfo_9_bits_channel,
+  input  [7:0]  io_msInfo_9_bits_set,
+  input  [2:0]  io_msInfo_9_bits_way,
+  input  [33:0] io_msInfo_9_bits_reqTag,
+  input  [4:0]  io_msInfo_9_bits_reqSource,
+  input         io_msInfo_9_bits_willFree,
+  input         io_msInfo_9_bits_aliasTask,
+  input         io_msInfo_9_bits_needRelease,
+  input         io_msInfo_9_bits_blockRefill,
+  input         io_msInfo_9_bits_meta_dirty,
+  input  [1:0]  io_msInfo_9_bits_meta_state,
+  input         io_msInfo_9_bits_meta_clients,
+  input         io_msInfo_9_bits_meta_alias,
+  input         io_msInfo_9_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_9_bits_meta_prefetchSrc,
+  input         io_msInfo_9_bits_meta_accessed,
+  input         io_msInfo_9_bits_meta_tagErr,
+  input         io_msInfo_9_bits_meta_dataErr,
+  input  [33:0] io_msInfo_9_bits_metaTag,
+  input         io_msInfo_9_bits_dirHit,
+  input         io_msInfo_9_bits_isAcqOrPrefetch,
+  input         io_msInfo_9_bits_isPrefetch,
+  input  [2:0]  io_msInfo_9_bits_param,
+  input         io_msInfo_9_bits_mergeA,
+  input         io_msInfo_9_bits_w_grantfirst,
+  input         io_msInfo_9_bits_w_grantlast,
+  input         io_msInfo_9_bits_w_grant,
+  input         io_msInfo_9_bits_s_release,
+  input         io_msInfo_9_bits_s_refill,
+  input         io_msInfo_9_bits_s_cmoresp,
+  input         io_msInfo_9_bits_s_cmometaw,
+  input         io_msInfo_9_bits_w_releaseack,
+  input         io_msInfo_9_bits_w_replResp,
+  input         io_msInfo_9_bits_w_rprobeacklast,
+  input         io_msInfo_9_bits_replaceData,
+  input         io_msInfo_9_bits_releaseToClean,
+  input         io_msInfo_10_valid,
+  input  [2:0]  io_msInfo_10_bits_channel,
+  input  [7:0]  io_msInfo_10_bits_set,
+  input  [2:0]  io_msInfo_10_bits_way,
+  input  [33:0] io_msInfo_10_bits_reqTag,
+  input  [4:0]  io_msInfo_10_bits_reqSource,
+  input         io_msInfo_10_bits_willFree,
+  input         io_msInfo_10_bits_aliasTask,
+  input         io_msInfo_10_bits_needRelease,
+  input         io_msInfo_10_bits_blockRefill,
+  input         io_msInfo_10_bits_meta_dirty,
+  input  [1:0]  io_msInfo_10_bits_meta_state,
+  input         io_msInfo_10_bits_meta_clients,
+  input         io_msInfo_10_bits_meta_alias,
+  input         io_msInfo_10_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_10_bits_meta_prefetchSrc,
+  input         io_msInfo_10_bits_meta_accessed,
+  input         io_msInfo_10_bits_meta_tagErr,
+  input         io_msInfo_10_bits_meta_dataErr,
+  input  [33:0] io_msInfo_10_bits_metaTag,
+  input         io_msInfo_10_bits_dirHit,
+  input         io_msInfo_10_bits_isAcqOrPrefetch,
+  input         io_msInfo_10_bits_isPrefetch,
+  input  [2:0]  io_msInfo_10_bits_param,
+  input         io_msInfo_10_bits_mergeA,
+  input         io_msInfo_10_bits_w_grantfirst,
+  input         io_msInfo_10_bits_w_grantlast,
+  input         io_msInfo_10_bits_w_grant,
+  input         io_msInfo_10_bits_s_release,
+  input         io_msInfo_10_bits_s_refill,
+  input         io_msInfo_10_bits_s_cmoresp,
+  input         io_msInfo_10_bits_s_cmometaw,
+  input         io_msInfo_10_bits_w_releaseack,
+  input         io_msInfo_10_bits_w_replResp,
+  input         io_msInfo_10_bits_w_rprobeacklast,
+  input         io_msInfo_10_bits_replaceData,
+  input         io_msInfo_10_bits_releaseToClean,
+  input         io_msInfo_11_valid,
+  input  [2:0]  io_msInfo_11_bits_channel,
+  input  [7:0]  io_msInfo_11_bits_set,
+  input  [2:0]  io_msInfo_11_bits_way,
+  input  [33:0] io_msInfo_11_bits_reqTag,
+  input  [4:0]  io_msInfo_11_bits_reqSource,
+  input         io_msInfo_11_bits_willFree,
+  input         io_msInfo_11_bits_aliasTask,
+  input         io_msInfo_11_bits_needRelease,
+  input         io_msInfo_11_bits_blockRefill,
+  input         io_msInfo_11_bits_meta_dirty,
+  input  [1:0]  io_msInfo_11_bits_meta_state,
+  input         io_msInfo_11_bits_meta_clients,
+  input         io_msInfo_11_bits_meta_alias,
+  input         io_msInfo_11_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_11_bits_meta_prefetchSrc,
+  input         io_msInfo_11_bits_meta_accessed,
+  input         io_msInfo_11_bits_meta_tagErr,
+  input         io_msInfo_11_bits_meta_dataErr,
+  input  [33:0] io_msInfo_11_bits_metaTag,
+  input         io_msInfo_11_bits_dirHit,
+  input         io_msInfo_11_bits_isAcqOrPrefetch,
+  input         io_msInfo_11_bits_isPrefetch,
+  input  [2:0]  io_msInfo_11_bits_param,
+  input         io_msInfo_11_bits_mergeA,
+  input         io_msInfo_11_bits_w_grantfirst,
+  input         io_msInfo_11_bits_w_grantlast,
+  input         io_msInfo_11_bits_w_grant,
+  input         io_msInfo_11_bits_s_release,
+  input         io_msInfo_11_bits_s_refill,
+  input         io_msInfo_11_bits_s_cmoresp,
+  input         io_msInfo_11_bits_s_cmometaw,
+  input         io_msInfo_11_bits_w_releaseack,
+  input         io_msInfo_11_bits_w_replResp,
+  input         io_msInfo_11_bits_w_rprobeacklast,
+  input         io_msInfo_11_bits_replaceData,
+  input         io_msInfo_11_bits_releaseToClean,
+  input         io_msInfo_12_valid,
+  input  [2:0]  io_msInfo_12_bits_channel,
+  input  [7:0]  io_msInfo_12_bits_set,
+  input  [2:0]  io_msInfo_12_bits_way,
+  input  [33:0] io_msInfo_12_bits_reqTag,
+  input  [4:0]  io_msInfo_12_bits_reqSource,
+  input         io_msInfo_12_bits_willFree,
+  input         io_msInfo_12_bits_aliasTask,
+  input         io_msInfo_12_bits_needRelease,
+  input         io_msInfo_12_bits_blockRefill,
+  input         io_msInfo_12_bits_meta_dirty,
+  input  [1:0]  io_msInfo_12_bits_meta_state,
+  input         io_msInfo_12_bits_meta_clients,
+  input         io_msInfo_12_bits_meta_alias,
+  input         io_msInfo_12_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_12_bits_meta_prefetchSrc,
+  input         io_msInfo_12_bits_meta_accessed,
+  input         io_msInfo_12_bits_meta_tagErr,
+  input         io_msInfo_12_bits_meta_dataErr,
+  input  [33:0] io_msInfo_12_bits_metaTag,
+  input         io_msInfo_12_bits_dirHit,
+  input         io_msInfo_12_bits_isAcqOrPrefetch,
+  input         io_msInfo_12_bits_isPrefetch,
+  input  [2:0]  io_msInfo_12_bits_param,
+  input         io_msInfo_12_bits_mergeA,
+  input         io_msInfo_12_bits_w_grantfirst,
+  input         io_msInfo_12_bits_w_grantlast,
+  input         io_msInfo_12_bits_w_grant,
+  input         io_msInfo_12_bits_s_release,
+  input         io_msInfo_12_bits_s_refill,
+  input         io_msInfo_12_bits_s_cmoresp,
+  input         io_msInfo_12_bits_s_cmometaw,
+  input         io_msInfo_12_bits_w_releaseack,
+  input         io_msInfo_12_bits_w_replResp,
+  input         io_msInfo_12_bits_w_rprobeacklast,
+  input         io_msInfo_12_bits_replaceData,
+  input         io_msInfo_12_bits_releaseToClean,
+  input         io_msInfo_13_valid,
+  input  [2:0]  io_msInfo_13_bits_channel,
+  input  [7:0]  io_msInfo_13_bits_set,
+  input  [2:0]  io_msInfo_13_bits_way,
+  input  [33:0] io_msInfo_13_bits_reqTag,
+  input  [4:0]  io_msInfo_13_bits_reqSource,
+  input         io_msInfo_13_bits_willFree,
+  input         io_msInfo_13_bits_aliasTask,
+  input         io_msInfo_13_bits_needRelease,
+  input         io_msInfo_13_bits_blockRefill,
+  input         io_msInfo_13_bits_meta_dirty,
+  input  [1:0]  io_msInfo_13_bits_meta_state,
+  input         io_msInfo_13_bits_meta_clients,
+  input         io_msInfo_13_bits_meta_alias,
+  input         io_msInfo_13_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_13_bits_meta_prefetchSrc,
+  input         io_msInfo_13_bits_meta_accessed,
+  input         io_msInfo_13_bits_meta_tagErr,
+  input         io_msInfo_13_bits_meta_dataErr,
+  input  [33:0] io_msInfo_13_bits_metaTag,
+  input         io_msInfo_13_bits_dirHit,
+  input         io_msInfo_13_bits_isAcqOrPrefetch,
+  input         io_msInfo_13_bits_isPrefetch,
+  input  [2:0]  io_msInfo_13_bits_param,
+  input         io_msInfo_13_bits_mergeA,
+  input         io_msInfo_13_bits_w_grantfirst,
+  input         io_msInfo_13_bits_w_grantlast,
+  input         io_msInfo_13_bits_w_grant,
+  input         io_msInfo_13_bits_s_release,
+  input         io_msInfo_13_bits_s_refill,
+  input         io_msInfo_13_bits_s_cmoresp,
+  input         io_msInfo_13_bits_s_cmometaw,
+  input         io_msInfo_13_bits_w_releaseack,
+  input         io_msInfo_13_bits_w_replResp,
+  input         io_msInfo_13_bits_w_rprobeacklast,
+  input         io_msInfo_13_bits_replaceData,
+  input         io_msInfo_13_bits_releaseToClean,
+  input         io_msInfo_14_valid,
+  input  [2:0]  io_msInfo_14_bits_channel,
+  input  [7:0]  io_msInfo_14_bits_set,
+  input  [2:0]  io_msInfo_14_bits_way,
+  input  [33:0] io_msInfo_14_bits_reqTag,
+  input  [4:0]  io_msInfo_14_bits_reqSource,
+  input         io_msInfo_14_bits_willFree,
+  input         io_msInfo_14_bits_aliasTask,
+  input         io_msInfo_14_bits_needRelease,
+  input         io_msInfo_14_bits_blockRefill,
+  input         io_msInfo_14_bits_meta_dirty,
+  input  [1:0]  io_msInfo_14_bits_meta_state,
+  input         io_msInfo_14_bits_meta_clients,
+  input         io_msInfo_14_bits_meta_alias,
+  input         io_msInfo_14_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_14_bits_meta_prefetchSrc,
+  input         io_msInfo_14_bits_meta_accessed,
+  input         io_msInfo_14_bits_meta_tagErr,
+  input         io_msInfo_14_bits_meta_dataErr,
+  input  [33:0] io_msInfo_14_bits_metaTag,
+  input         io_msInfo_14_bits_dirHit,
+  input         io_msInfo_14_bits_isAcqOrPrefetch,
+  input         io_msInfo_14_bits_isPrefetch,
+  input  [2:0]  io_msInfo_14_bits_param,
+  input         io_msInfo_14_bits_mergeA,
+  input         io_msInfo_14_bits_w_grantfirst,
+  input         io_msInfo_14_bits_w_grantlast,
+  input         io_msInfo_14_bits_w_grant,
+  input         io_msInfo_14_bits_s_release,
+  input         io_msInfo_14_bits_s_refill,
+  input         io_msInfo_14_bits_s_cmoresp,
+  input         io_msInfo_14_bits_s_cmometaw,
+  input         io_msInfo_14_bits_w_releaseack,
+  input         io_msInfo_14_bits_w_replResp,
+  input         io_msInfo_14_bits_w_rprobeacklast,
+  input         io_msInfo_14_bits_replaceData,
+  input         io_msInfo_14_bits_releaseToClean,
+  input         io_msInfo_15_valid,
+  input  [2:0]  io_msInfo_15_bits_channel,
+  input  [7:0]  io_msInfo_15_bits_set,
+  input  [2:0]  io_msInfo_15_bits_way,
+  input  [33:0] io_msInfo_15_bits_reqTag,
+  input  [4:0]  io_msInfo_15_bits_reqSource,
+  input         io_msInfo_15_bits_willFree,
+  input         io_msInfo_15_bits_aliasTask,
+  input         io_msInfo_15_bits_needRelease,
+  input         io_msInfo_15_bits_blockRefill,
+  input         io_msInfo_15_bits_meta_dirty,
+  input  [1:0]  io_msInfo_15_bits_meta_state,
+  input         io_msInfo_15_bits_meta_clients,
+  input         io_msInfo_15_bits_meta_alias,
+  input         io_msInfo_15_bits_meta_prefetch,
+  input  [3:0]  io_msInfo_15_bits_meta_prefetchSrc,
+  input         io_msInfo_15_bits_meta_accessed,
+  input         io_msInfo_15_bits_meta_tagErr,
+  input         io_msInfo_15_bits_meta_dataErr,
+  input  [33:0] io_msInfo_15_bits_metaTag,
+  input         io_msInfo_15_bits_dirHit,
+  input         io_msInfo_15_bits_isAcqOrPrefetch,
+  input         io_msInfo_15_bits_isPrefetch,
+  input  [2:0]  io_msInfo_15_bits_param,
+  input         io_msInfo_15_bits_mergeA,
+  input         io_msInfo_15_bits_w_grantfirst,
+  input         io_msInfo_15_bits_w_grantlast,
+  input         io_msInfo_15_bits_w_grant,
+  input         io_msInfo_15_bits_s_release,
+  input         io_msInfo_15_bits_s_refill,
+  input         io_msInfo_15_bits_s_cmoresp,
+  input         io_msInfo_15_bits_s_cmometaw,
+  input         io_msInfo_15_bits_w_releaseack,
+  input         io_msInfo_15_bits_w_replResp,
+  input         io_msInfo_15_bits_w_rprobeacklast,
+  input         io_msInfo_15_bits_replaceData,
+  input         io_msInfo_15_bits_releaseToClean
+);
+
+  reg         ds_mcp2_stall;
+  reg         resetFinish;
+  reg  [7:0]  resetIdx;
+  reg         mshr_task_s1_valid;
+  reg  [2:0]  mshr_task_s1_bits_channel;
+  reg  [2:0]  mshr_task_s1_bits_txChannel;
+  reg  [7:0]  mshr_task_s1_bits_set;
+  reg  [33:0] mshr_task_s1_bits_tag;
+  reg  [5:0]  mshr_task_s1_bits_off;
+  reg         mshr_task_s1_bits_alias;
+  reg  [43:0] mshr_task_s1_bits_vaddr;
+  reg         mshr_task_s1_bits_isKeyword;
+  reg  [3:0]  mshr_task_s1_bits_opcode;
+  reg  [2:0]  mshr_task_s1_bits_param;
+  reg  [2:0]  mshr_task_s1_bits_size;
+  reg  [6:0]  mshr_task_s1_bits_sourceId;
+  reg  [1:0]  mshr_task_s1_bits_bufIdx;
+  reg         mshr_task_s1_bits_needProbeAckData;
+  reg         mshr_task_s1_bits_denied;
+  reg         mshr_task_s1_bits_corrupt;
+  reg         mshr_task_s1_bits_mshrTask;
+  reg  [7:0]  mshr_task_s1_bits_mshrId;
+  reg         mshr_task_s1_bits_aliasTask;
+  reg         mshr_task_s1_bits_useProbeData;
+  reg         mshr_task_s1_bits_mshrRetry;
+  reg         mshr_task_s1_bits_readProbeDataDown;
+  reg         mshr_task_s1_bits_fromL2pft;
+  reg         mshr_task_s1_bits_needHint;
+  reg         mshr_task_s1_bits_dirty;
+  reg  [2:0]  mshr_task_s1_bits_way;
+  reg         mshr_task_s1_bits_meta_dirty;
+  reg  [1:0]  mshr_task_s1_bits_meta_state;
+  reg         mshr_task_s1_bits_meta_clients;
+  reg         mshr_task_s1_bits_meta_alias;
+  reg         mshr_task_s1_bits_meta_prefetch;
+  reg  [3:0]  mshr_task_s1_bits_meta_prefetchSrc;
+  reg         mshr_task_s1_bits_meta_accessed;
+  reg         mshr_task_s1_bits_meta_tagErr;
+  reg         mshr_task_s1_bits_meta_dataErr;
+  reg         mshr_task_s1_bits_metaWen;
+  reg         mshr_task_s1_bits_tagWen;
+  reg         mshr_task_s1_bits_dsWen;
+  reg  [7:0]  mshr_task_s1_bits_wayMask;
+  reg         mshr_task_s1_bits_replTask;
+  reg         mshr_task_s1_bits_cmoTask;
+  reg         mshr_task_s1_bits_cmoAll;
+  reg  [4:0]  mshr_task_s1_bits_reqSource;
+  reg         mshr_task_s1_bits_mergeA;
+  reg  [5:0]  mshr_task_s1_bits_aMergeTask_off;
+  reg         mshr_task_s1_bits_aMergeTask_alias;
+  reg  [43:0] mshr_task_s1_bits_aMergeTask_vaddr;
+  reg         mshr_task_s1_bits_aMergeTask_isKeyword;
+  reg  [2:0]  mshr_task_s1_bits_aMergeTask_opcode;
+  reg  [2:0]  mshr_task_s1_bits_aMergeTask_param;
+  reg  [6:0]  mshr_task_s1_bits_aMergeTask_sourceId;
+  reg         mshr_task_s1_bits_aMergeTask_meta_dirty;
+  reg  [1:0]  mshr_task_s1_bits_aMergeTask_meta_state;
+  reg         mshr_task_s1_bits_aMergeTask_meta_clients;
+  reg         mshr_task_s1_bits_aMergeTask_meta_alias;
+  reg         mshr_task_s1_bits_aMergeTask_meta_prefetch;
+  reg  [3:0]  mshr_task_s1_bits_aMergeTask_meta_prefetchSrc;
+  reg         mshr_task_s1_bits_aMergeTask_meta_accessed;
+  reg         mshr_task_s1_bits_aMergeTask_meta_tagErr;
+  reg         mshr_task_s1_bits_aMergeTask_meta_dataErr;
+  reg         mshr_task_s1_bits_snpHitRelease;
+  reg         mshr_task_s1_bits_snpHitReleaseToInval;
+  reg         mshr_task_s1_bits_snpHitReleaseToClean;
+  reg         mshr_task_s1_bits_snpHitReleaseWithData;
+  reg  [7:0]  mshr_task_s1_bits_snpHitReleaseIdx;
+  reg         mshr_task_s1_bits_snpHitReleaseMeta_dirty;
+  reg  [1:0]  mshr_task_s1_bits_snpHitReleaseMeta_state;
+  reg         mshr_task_s1_bits_snpHitReleaseMeta_clients;
+  reg         mshr_task_s1_bits_snpHitReleaseMeta_alias;
+  reg         mshr_task_s1_bits_snpHitReleaseMeta_prefetch;
+  reg  [3:0]  mshr_task_s1_bits_snpHitReleaseMeta_prefetchSrc;
+  reg         mshr_task_s1_bits_snpHitReleaseMeta_accessed;
+  reg         mshr_task_s1_bits_snpHitReleaseMeta_tagErr;
+  reg         mshr_task_s1_bits_snpHitReleaseMeta_dataErr;
+  reg  [10:0] mshr_task_s1_bits_tgtID;
+  reg  [10:0] mshr_task_s1_bits_srcID;
+  reg  [11:0] mshr_task_s1_bits_txnID;
+  reg  [10:0] mshr_task_s1_bits_homeNID;
+  reg  [11:0] mshr_task_s1_bits_dbID;
+  reg  [10:0] mshr_task_s1_bits_fwdNID;
+  reg  [11:0] mshr_task_s1_bits_fwdTxnID;
+  reg  [6:0]  mshr_task_s1_bits_chiOpcode;
+  reg  [2:0]  mshr_task_s1_bits_resp;
+  reg  [2:0]  mshr_task_s1_bits_fwdState;
+  reg  [3:0]  mshr_task_s1_bits_pCrdType;
+  reg         mshr_task_s1_bits_retToSrc;
+  reg         mshr_task_s1_bits_likelyshared;
+  reg         mshr_task_s1_bits_expCompAck;
+  reg         mshr_task_s1_bits_allowRetry;
+  reg         mshr_task_s1_bits_memAttr_allocate;
+  reg         mshr_task_s1_bits_memAttr_cacheable;
+  reg         mshr_task_s1_bits_memAttr_device;
+  reg         mshr_task_s1_bits_memAttr_ewa;
+  reg         mshr_task_s1_bits_traceTag;
+  wire        _io_dirRead_s1_bits_replacerInfo_refill_prefetch_T =
+    mshr_task_s1_bits_opcode == 4'h2;
+  wire        s1_needs_replRead =
+    mshr_task_s1_valid & mshr_task_s1_bits_channel[0] & mshr_task_s1_bits_replTask
+    & (mshr_task_s1_bits_opcode == 4'h4 | mshr_task_s1_bits_opcode == 4'h5
+       | mshr_task_s1_bits_opcode == 4'h1
+       | _io_dirRead_s1_bits_replacerInfo_refill_prefetch_T);
+  wire        io_mshrTask_ready_0 =
+    ~io_fromGrantBuffer_blockMSHRReqEntrance & ~s1_needs_replRead
+    & ~(mshr_task_s1_valid & ds_mcp2_stall) & ~io_fromTXDAT_blockMSHRReqEntrance
+    & ~io_fromTXRSP_blockMSHRReqEntrance & ~io_fromTXREQ_blockMSHRReqEntrance;
+  wire        mshr_replRead_stall =
+    s1_needs_replRead & (~io_dirRead_s1_ready | io_fromMainPipe_blockG_s1);
+  wire        block_A =
+    io_fromMSHRCtl_blockA_s1 | io_fromMainPipe_blockA_s1
+    | io_fromGrantBuffer_blockSinkReqEntrance_blockA_s1;
+  wire        block_B =
+    io_fromMSHRCtl_blockB_s1 | io_fromMainPipe_blockB_s1
+    | io_fromGrantBuffer_blockSinkReqEntrance_blockB_s1
+    | io_fromTXDAT_blockSinkBReqEntrance | io_fromTXRSP_blockSinkBReqEntrance;
+  wire        block_C =
+    io_fromMSHRCtl_blockC_s1 | io_fromMainPipe_blockC_s1
+    | io_fromGrantBuffer_blockSinkReqEntrance_blockC_s1;
+  wire        _chnl_task_s1_bits_T = io_sinkC_valid & ~block_C;
+  wire        _chnl_task_s1_bits_T_1 = io_sinkB_valid & ~block_B;
+  wire        sink_ready_basic =
+    io_dirRead_s1_ready & resetFinish & ~mshr_task_s1_valid & ~ds_mcp2_stall;
+  wire        io_sinkA_ready_0 =
+    sink_ready_basic & ~block_A & ~_chnl_task_s1_bits_T_1 & ~_chnl_task_s1_bits_T;
+  wire        io_sinkB_ready_0 = sink_ready_basic & ~block_B & ~_chnl_task_s1_bits_T;
+  wire        io_sinkC_ready_0 = sink_ready_basic & ~block_C;
+  wire        chnl_task_s1_valid =
+    io_dirRead_s1_ready
+    & (|{io_sinkA_valid & ~block_A, _chnl_task_s1_bits_T_1, _chnl_task_s1_bits_T})
+    & resetFinish;
+  wire        task_s1_valid =
+    mshr_task_s1_valid ? mshr_task_s1_valid : chnl_task_s1_valid;
+  wire [2:0]  task_s1_bits_channel =
+    mshr_task_s1_valid
+      ? mshr_task_s1_bits_channel
+      : _chnl_task_s1_bits_T
+          ? io_sinkC_bits_channel
+          : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_channel : io_sinkA_bits_channel;
+  wire [2:0]  task_s1_bits_txChannel =
+    mshr_task_s1_valid
+      ? mshr_task_s1_bits_txChannel
+      : _chnl_task_s1_bits_T
+          ? io_sinkC_bits_txChannel
+          : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_txChannel : io_sinkA_bits_txChannel;
+  wire [7:0]  task_s1_bits_set =
+    mshr_task_s1_valid
+      ? mshr_task_s1_bits_set
+      : _chnl_task_s1_bits_T
+          ? io_sinkC_bits_set
+          : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_set : io_sinkA_bits_set;
+  wire [33:0] task_s1_bits_tag =
+    mshr_task_s1_valid
+      ? mshr_task_s1_bits_tag
+      : _chnl_task_s1_bits_T
+          ? io_sinkC_bits_tag
+          : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_tag : io_sinkA_bits_tag;
+  wire [3:0]  task_s1_bits_opcode =
+    mshr_task_s1_valid
+      ? mshr_task_s1_bits_opcode
+      : _chnl_task_s1_bits_T
+          ? io_sinkC_bits_opcode
+          : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_opcode : io_sinkA_bits_opcode;
+  wire        task_s1_bits_mshrTask =
+    mshr_task_s1_valid
+      ? mshr_task_s1_bits_mshrTask
+      : _chnl_task_s1_bits_T
+          ? io_sinkC_bits_mshrTask
+          : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_mshrTask : io_sinkA_bits_mshrTask;
+  wire [7:0]  task_s1_bits_mshrId =
+    mshr_task_s1_valid
+      ? mshr_task_s1_bits_mshrId
+      : _chnl_task_s1_bits_T
+          ? io_sinkC_bits_mshrId
+          : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_mshrId : io_sinkA_bits_mshrId;
+  wire [4:0]  task_s1_bits_reqSource =
+    mshr_task_s1_valid
+      ? mshr_task_s1_bits_reqSource
+      : _chnl_task_s1_bits_T
+          ? io_sinkC_bits_reqSource
+          : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_reqSource : io_sinkA_bits_reqSource;
+  wire        s1_fire = task_s1_valid & ~mshr_replRead_stall & ~ds_mcp2_stall;
+  wire        io_sinkCHintQInfo_valid_0 = io_sinkC_ready_0 & io_sinkC_valid;
+  wire [14:0] _io_dirRead_s1_bits_wayMask_T_1 = 15'h1 << mshr_task_s1_bits_way;
+  reg         task_s2_valid;
+  reg  [2:0]  task_s2_bits_channel;
+  reg  [2:0]  task_s2_bits_txChannel;
+  reg  [7:0]  task_s2_bits_set;
+  reg  [33:0] task_s2_bits_tag;
+  reg  [5:0]  task_s2_bits_off;
+  reg         task_s2_bits_alias;
+  reg  [43:0] task_s2_bits_vaddr;
+  reg         task_s2_bits_isKeyword;
+  reg  [3:0]  task_s2_bits_opcode;
+  reg  [2:0]  task_s2_bits_param;
+  reg  [2:0]  task_s2_bits_size;
+  reg  [6:0]  task_s2_bits_sourceId;
+  reg  [1:0]  task_s2_bits_bufIdx;
+  reg         task_s2_bits_needProbeAckData;
+  reg         task_s2_bits_denied;
+  reg         task_s2_bits_corrupt;
+  reg         task_s2_bits_mshrTask;
+  reg  [7:0]  task_s2_bits_mshrId;
+  reg         task_s2_bits_aliasTask;
+  reg         task_s2_bits_useProbeData;
+  reg         task_s2_bits_mshrRetry;
+  reg         task_s2_bits_readProbeDataDown;
+  reg         task_s2_bits_fromL2pft;
+  reg         task_s2_bits_needHint;
+  reg         task_s2_bits_dirty;
+  reg  [2:0]  task_s2_bits_way;
+  reg         task_s2_bits_meta_dirty;
+  reg  [1:0]  task_s2_bits_meta_state;
+  reg         task_s2_bits_meta_clients;
+  reg         task_s2_bits_meta_alias;
+  reg         task_s2_bits_meta_prefetch;
+  reg  [3:0]  task_s2_bits_meta_prefetchSrc;
+  reg         task_s2_bits_meta_accessed;
+  reg         task_s2_bits_meta_tagErr;
+  reg         task_s2_bits_meta_dataErr;
+  reg         task_s2_bits_metaWen;
+  reg         task_s2_bits_tagWen;
+  reg         task_s2_bits_dsWen;
+  reg  [7:0]  task_s2_bits_wayMask;
+  reg         task_s2_bits_replTask;
+  reg         task_s2_bits_cmoTask;
+  reg         task_s2_bits_cmoAll;
+  reg  [4:0]  task_s2_bits_reqSource;
+  reg         task_s2_bits_mergeA;
+  reg  [5:0]  task_s2_bits_aMergeTask_off;
+  reg         task_s2_bits_aMergeTask_alias;
+  reg  [43:0] task_s2_bits_aMergeTask_vaddr;
+  reg         task_s2_bits_aMergeTask_isKeyword;
+  reg  [2:0]  task_s2_bits_aMergeTask_opcode;
+  reg  [2:0]  task_s2_bits_aMergeTask_param;
+  reg  [6:0]  task_s2_bits_aMergeTask_sourceId;
+  reg         task_s2_bits_aMergeTask_meta_dirty;
+  reg  [1:0]  task_s2_bits_aMergeTask_meta_state;
+  reg         task_s2_bits_aMergeTask_meta_clients;
+  reg         task_s2_bits_aMergeTask_meta_alias;
+  reg         task_s2_bits_aMergeTask_meta_prefetch;
+  reg  [3:0]  task_s2_bits_aMergeTask_meta_prefetchSrc;
+  reg         task_s2_bits_aMergeTask_meta_accessed;
+  reg         task_s2_bits_aMergeTask_meta_tagErr;
+  reg         task_s2_bits_aMergeTask_meta_dataErr;
+  reg         task_s2_bits_snpHitRelease;
+  reg         task_s2_bits_snpHitReleaseToInval;
+  reg         task_s2_bits_snpHitReleaseToClean;
+  reg         task_s2_bits_snpHitReleaseWithData;
+  reg  [7:0]  task_s2_bits_snpHitReleaseIdx;
+  reg         task_s2_bits_snpHitReleaseMeta_dirty;
+  reg  [1:0]  task_s2_bits_snpHitReleaseMeta_state;
+  reg         task_s2_bits_snpHitReleaseMeta_clients;
+  reg         task_s2_bits_snpHitReleaseMeta_alias;
+  reg         task_s2_bits_snpHitReleaseMeta_prefetch;
+  reg  [3:0]  task_s2_bits_snpHitReleaseMeta_prefetchSrc;
+  reg         task_s2_bits_snpHitReleaseMeta_accessed;
+  reg         task_s2_bits_snpHitReleaseMeta_tagErr;
+  reg         task_s2_bits_snpHitReleaseMeta_dataErr;
+  reg  [10:0] task_s2_bits_tgtID;
+  reg  [10:0] task_s2_bits_srcID;
+  reg  [11:0] task_s2_bits_txnID;
+  reg  [10:0] task_s2_bits_homeNID;
+  reg  [11:0] task_s2_bits_dbID;
+  reg  [10:0] task_s2_bits_fwdNID;
+  reg  [11:0] task_s2_bits_fwdTxnID;
+  reg  [6:0]  task_s2_bits_chiOpcode;
+  reg  [2:0]  task_s2_bits_resp;
+  reg  [2:0]  task_s2_bits_fwdState;
+  reg  [3:0]  task_s2_bits_pCrdType;
+  reg         task_s2_bits_retToSrc;
+  reg         task_s2_bits_likelyshared;
+  reg         task_s2_bits_expCompAck;
+  reg         task_s2_bits_allowRetry;
+  reg         task_s2_bits_memAttr_allocate;
+  reg         task_s2_bits_memAttr_cacheable;
+  reg         task_s2_bits_memAttr_device;
+  reg         task_s2_bits_memAttr_ewa;
+  reg         task_s2_bits_traceTag;
+  wire        mshrTask_s2 = task_s2_valid & task_s2_bits_mshrTask;
+  wire        mshrTask_s2_a_upwards =
+    task_s2_bits_channel[0]
+    & (task_s2_bits_opcode == 4'h5 | task_s2_bits_opcode == 4'h4 & task_s2_bits_dsWen
+       | task_s2_bits_opcode == 4'h1 | task_s2_bits_opcode == 4'h2 & task_s2_bits_dsWen);
+  wire        s0_fire = io_mshrTask_valid & io_mshrTask_ready_0;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      resetFinish <= 1'h0;
+      resetIdx <= 8'hFF;
+      mshr_task_s1_valid <= 1'h0;
+      mshr_task_s1_bits_channel <= 3'h0;
+      mshr_task_s1_bits_txChannel <= 3'h0;
+      mshr_task_s1_bits_set <= 8'h0;
+      mshr_task_s1_bits_tag <= 34'h0;
+      mshr_task_s1_bits_off <= 6'h0;
+      mshr_task_s1_bits_alias <= 1'h0;
+      mshr_task_s1_bits_vaddr <= 44'h0;
+      mshr_task_s1_bits_isKeyword <= 1'h0;
+      mshr_task_s1_bits_opcode <= 4'h0;
+      mshr_task_s1_bits_param <= 3'h0;
+      mshr_task_s1_bits_size <= 3'h0;
+      mshr_task_s1_bits_sourceId <= 7'h0;
+      mshr_task_s1_bits_bufIdx <= 2'h0;
+      mshr_task_s1_bits_needProbeAckData <= 1'h0;
+      mshr_task_s1_bits_denied <= 1'h0;
+      mshr_task_s1_bits_corrupt <= 1'h0;
+      mshr_task_s1_bits_mshrTask <= 1'h0;
+      mshr_task_s1_bits_mshrId <= 8'h0;
+      mshr_task_s1_bits_aliasTask <= 1'h0;
+      mshr_task_s1_bits_useProbeData <= 1'h0;
+      mshr_task_s1_bits_mshrRetry <= 1'h0;
+      mshr_task_s1_bits_readProbeDataDown <= 1'h0;
+      mshr_task_s1_bits_fromL2pft <= 1'h0;
+      mshr_task_s1_bits_needHint <= 1'h0;
+      mshr_task_s1_bits_dirty <= 1'h0;
+      mshr_task_s1_bits_way <= 3'h0;
+      mshr_task_s1_bits_meta_dirty <= 1'h0;
+      mshr_task_s1_bits_meta_state <= 2'h0;
+      mshr_task_s1_bits_meta_clients <= 1'h0;
+      mshr_task_s1_bits_meta_alias <= 1'h0;
+      mshr_task_s1_bits_meta_prefetch <= 1'h0;
+      mshr_task_s1_bits_meta_prefetchSrc <= 4'h0;
+      mshr_task_s1_bits_meta_accessed <= 1'h0;
+      mshr_task_s1_bits_meta_tagErr <= 1'h0;
+      mshr_task_s1_bits_meta_dataErr <= 1'h0;
+      mshr_task_s1_bits_metaWen <= 1'h0;
+      mshr_task_s1_bits_tagWen <= 1'h0;
+      mshr_task_s1_bits_dsWen <= 1'h0;
+      mshr_task_s1_bits_wayMask <= 8'h0;
+      mshr_task_s1_bits_replTask <= 1'h0;
+      mshr_task_s1_bits_cmoTask <= 1'h0;
+      mshr_task_s1_bits_cmoAll <= 1'h0;
+      mshr_task_s1_bits_reqSource <= 5'h0;
+      mshr_task_s1_bits_mergeA <= 1'h0;
+      mshr_task_s1_bits_aMergeTask_off <= 6'h0;
+      mshr_task_s1_bits_aMergeTask_alias <= 1'h0;
+      mshr_task_s1_bits_aMergeTask_vaddr <= 44'h0;
+      mshr_task_s1_bits_aMergeTask_isKeyword <= 1'h0;
+      mshr_task_s1_bits_aMergeTask_opcode <= 3'h0;
+      mshr_task_s1_bits_aMergeTask_param <= 3'h0;
+      mshr_task_s1_bits_aMergeTask_sourceId <= 7'h0;
+      mshr_task_s1_bits_aMergeTask_meta_dirty <= 1'h0;
+      mshr_task_s1_bits_aMergeTask_meta_state <= 2'h0;
+      mshr_task_s1_bits_aMergeTask_meta_clients <= 1'h0;
+      mshr_task_s1_bits_aMergeTask_meta_alias <= 1'h0;
+      mshr_task_s1_bits_aMergeTask_meta_prefetch <= 1'h0;
+      mshr_task_s1_bits_aMergeTask_meta_prefetchSrc <= 4'h0;
+      mshr_task_s1_bits_aMergeTask_meta_accessed <= 1'h0;
+      mshr_task_s1_bits_aMergeTask_meta_tagErr <= 1'h0;
+      mshr_task_s1_bits_aMergeTask_meta_dataErr <= 1'h0;
+      mshr_task_s1_bits_snpHitRelease <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseToInval <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseToClean <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseWithData <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseIdx <= 8'h0;
+      mshr_task_s1_bits_snpHitReleaseMeta_dirty <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseMeta_state <= 2'h0;
+      mshr_task_s1_bits_snpHitReleaseMeta_clients <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseMeta_alias <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseMeta_prefetch <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseMeta_prefetchSrc <= 4'h0;
+      mshr_task_s1_bits_snpHitReleaseMeta_accessed <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseMeta_tagErr <= 1'h0;
+      mshr_task_s1_bits_snpHitReleaseMeta_dataErr <= 1'h0;
+      mshr_task_s1_bits_tgtID <= 11'h0;
+      mshr_task_s1_bits_srcID <= 11'h0;
+      mshr_task_s1_bits_txnID <= 12'h0;
+      mshr_task_s1_bits_homeNID <= 11'h0;
+      mshr_task_s1_bits_dbID <= 12'h0;
+      mshr_task_s1_bits_fwdNID <= 11'h0;
+      mshr_task_s1_bits_fwdTxnID <= 12'h0;
+      mshr_task_s1_bits_chiOpcode <= 7'h0;
+      mshr_task_s1_bits_resp <= 3'h0;
+      mshr_task_s1_bits_fwdState <= 3'h0;
+      mshr_task_s1_bits_pCrdType <= 4'h0;
+      mshr_task_s1_bits_retToSrc <= 1'h0;
+      mshr_task_s1_bits_likelyshared <= 1'h0;
+      mshr_task_s1_bits_expCompAck <= 1'h0;
+      mshr_task_s1_bits_allowRetry <= 1'h0;
+      mshr_task_s1_bits_memAttr_allocate <= 1'h0;
+      mshr_task_s1_bits_memAttr_cacheable <= 1'h0;
+      mshr_task_s1_bits_memAttr_device <= 1'h0;
+      mshr_task_s1_bits_memAttr_ewa <= 1'h0;
+      mshr_task_s1_bits_traceTag <= 1'h0;
+      task_s2_valid <= 1'h0;
+      task_s2_bits_channel <= 3'h0;
+      task_s2_bits_txChannel <= 3'h0;
+      task_s2_bits_set <= 8'h0;
+      task_s2_bits_tag <= 34'h0;
+      task_s2_bits_off <= 6'h0;
+      task_s2_bits_alias <= 1'h0;
+      task_s2_bits_vaddr <= 44'h0;
+      task_s2_bits_isKeyword <= 1'h0;
+      task_s2_bits_opcode <= 4'h0;
+      task_s2_bits_param <= 3'h0;
+      task_s2_bits_size <= 3'h0;
+      task_s2_bits_sourceId <= 7'h0;
+      task_s2_bits_bufIdx <= 2'h0;
+      task_s2_bits_needProbeAckData <= 1'h0;
+      task_s2_bits_denied <= 1'h0;
+      task_s2_bits_corrupt <= 1'h0;
+      task_s2_bits_mshrTask <= 1'h0;
+      task_s2_bits_mshrId <= 8'h0;
+      task_s2_bits_aliasTask <= 1'h0;
+      task_s2_bits_useProbeData <= 1'h0;
+      task_s2_bits_mshrRetry <= 1'h0;
+      task_s2_bits_readProbeDataDown <= 1'h0;
+      task_s2_bits_fromL2pft <= 1'h0;
+      task_s2_bits_needHint <= 1'h0;
+      task_s2_bits_dirty <= 1'h0;
+      task_s2_bits_way <= 3'h0;
+      task_s2_bits_meta_dirty <= 1'h0;
+      task_s2_bits_meta_state <= 2'h0;
+      task_s2_bits_meta_clients <= 1'h0;
+      task_s2_bits_meta_alias <= 1'h0;
+      task_s2_bits_meta_prefetch <= 1'h0;
+      task_s2_bits_meta_prefetchSrc <= 4'h0;
+      task_s2_bits_meta_accessed <= 1'h0;
+      task_s2_bits_meta_tagErr <= 1'h0;
+      task_s2_bits_meta_dataErr <= 1'h0;
+      task_s2_bits_metaWen <= 1'h0;
+      task_s2_bits_tagWen <= 1'h0;
+      task_s2_bits_dsWen <= 1'h0;
+      task_s2_bits_wayMask <= 8'h0;
+      task_s2_bits_replTask <= 1'h0;
+      task_s2_bits_cmoTask <= 1'h0;
+      task_s2_bits_cmoAll <= 1'h0;
+      task_s2_bits_reqSource <= 5'h0;
+      task_s2_bits_mergeA <= 1'h0;
+      task_s2_bits_aMergeTask_off <= 6'h0;
+      task_s2_bits_aMergeTask_alias <= 1'h0;
+      task_s2_bits_aMergeTask_vaddr <= 44'h0;
+      task_s2_bits_aMergeTask_isKeyword <= 1'h0;
+      task_s2_bits_aMergeTask_opcode <= 3'h0;
+      task_s2_bits_aMergeTask_param <= 3'h0;
+      task_s2_bits_aMergeTask_sourceId <= 7'h0;
+      task_s2_bits_aMergeTask_meta_dirty <= 1'h0;
+      task_s2_bits_aMergeTask_meta_state <= 2'h0;
+      task_s2_bits_aMergeTask_meta_clients <= 1'h0;
+      task_s2_bits_aMergeTask_meta_alias <= 1'h0;
+      task_s2_bits_aMergeTask_meta_prefetch <= 1'h0;
+      task_s2_bits_aMergeTask_meta_prefetchSrc <= 4'h0;
+      task_s2_bits_aMergeTask_meta_accessed <= 1'h0;
+      task_s2_bits_aMergeTask_meta_tagErr <= 1'h0;
+      task_s2_bits_aMergeTask_meta_dataErr <= 1'h0;
+      task_s2_bits_snpHitRelease <= 1'h0;
+      task_s2_bits_snpHitReleaseToInval <= 1'h0;
+      task_s2_bits_snpHitReleaseToClean <= 1'h0;
+      task_s2_bits_snpHitReleaseWithData <= 1'h0;
+      task_s2_bits_snpHitReleaseIdx <= 8'h0;
+      task_s2_bits_snpHitReleaseMeta_dirty <= 1'h0;
+      task_s2_bits_snpHitReleaseMeta_state <= 2'h0;
+      task_s2_bits_snpHitReleaseMeta_clients <= 1'h0;
+      task_s2_bits_snpHitReleaseMeta_alias <= 1'h0;
+      task_s2_bits_snpHitReleaseMeta_prefetch <= 1'h0;
+      task_s2_bits_snpHitReleaseMeta_prefetchSrc <= 4'h0;
+      task_s2_bits_snpHitReleaseMeta_accessed <= 1'h0;
+      task_s2_bits_snpHitReleaseMeta_tagErr <= 1'h0;
+      task_s2_bits_snpHitReleaseMeta_dataErr <= 1'h0;
+      task_s2_bits_tgtID <= 11'h0;
+      task_s2_bits_srcID <= 11'h0;
+      task_s2_bits_txnID <= 12'h0;
+      task_s2_bits_homeNID <= 11'h0;
+      task_s2_bits_dbID <= 12'h0;
+      task_s2_bits_fwdNID <= 11'h0;
+      task_s2_bits_fwdTxnID <= 12'h0;
+      task_s2_bits_chiOpcode <= 7'h0;
+      task_s2_bits_resp <= 3'h0;
+      task_s2_bits_fwdState <= 3'h0;
+      task_s2_bits_pCrdType <= 4'h0;
+      task_s2_bits_retToSrc <= 1'h0;
+      task_s2_bits_likelyshared <= 1'h0;
+      task_s2_bits_expCompAck <= 1'h0;
+      task_s2_bits_allowRetry <= 1'h0;
+      task_s2_bits_memAttr_allocate <= 1'h0;
+      task_s2_bits_memAttr_cacheable <= 1'h0;
+      task_s2_bits_memAttr_device <= 1'h0;
+      task_s2_bits_memAttr_ewa <= 1'h0;
+      task_s2_bits_traceTag <= 1'h0;
+    end
+    else begin
+      resetFinish <= resetIdx == 8'h0 | resetFinish;
+      if (resetFinish) begin
+      end
+      else
+        resetIdx <= 8'(resetIdx - 8'h1);
+      mshr_task_s1_valid <= mshr_task_s1_valid & ~s1_fire | s0_fire;
+      if (s0_fire) begin
+        mshr_task_s1_bits_channel <= io_mshrTask_bits_channel;
+        mshr_task_s1_bits_txChannel <= io_mshrTask_bits_txChannel;
+        mshr_task_s1_bits_set <= io_mshrTask_bits_set;
+        mshr_task_s1_bits_tag <= io_mshrTask_bits_tag;
+        mshr_task_s1_bits_off <= io_mshrTask_bits_off;
+        mshr_task_s1_bits_alias <= io_mshrTask_bits_alias;
+        mshr_task_s1_bits_vaddr <= io_mshrTask_bits_vaddr;
+        mshr_task_s1_bits_isKeyword <= io_mshrTask_bits_isKeyword;
+        mshr_task_s1_bits_opcode <= io_mshrTask_bits_opcode;
+        mshr_task_s1_bits_param <= io_mshrTask_bits_param;
+        mshr_task_s1_bits_size <= io_mshrTask_bits_size;
+        mshr_task_s1_bits_sourceId <= io_mshrTask_bits_sourceId;
+        mshr_task_s1_bits_bufIdx <= io_mshrTask_bits_bufIdx;
+        mshr_task_s1_bits_needProbeAckData <= io_mshrTask_bits_needProbeAckData;
+        mshr_task_s1_bits_denied <= io_mshrTask_bits_denied;
+        mshr_task_s1_bits_corrupt <= io_mshrTask_bits_corrupt;
+        mshr_task_s1_bits_mshrTask <= io_mshrTask_bits_mshrTask;
+        mshr_task_s1_bits_mshrId <= io_mshrTask_bits_mshrId;
+        mshr_task_s1_bits_aliasTask <= io_mshrTask_bits_aliasTask;
+        mshr_task_s1_bits_useProbeData <= io_mshrTask_bits_useProbeData;
+        mshr_task_s1_bits_mshrRetry <= io_mshrTask_bits_mshrRetry;
+        mshr_task_s1_bits_readProbeDataDown <= io_mshrTask_bits_readProbeDataDown;
+        mshr_task_s1_bits_fromL2pft <= io_mshrTask_bits_fromL2pft;
+        mshr_task_s1_bits_needHint <= io_mshrTask_bits_needHint;
+        mshr_task_s1_bits_dirty <= io_mshrTask_bits_dirty;
+        mshr_task_s1_bits_way <= io_mshrTask_bits_way;
+        mshr_task_s1_bits_meta_dirty <= io_mshrTask_bits_meta_dirty;
+        mshr_task_s1_bits_meta_state <= io_mshrTask_bits_meta_state;
+        mshr_task_s1_bits_meta_clients <= io_mshrTask_bits_meta_clients;
+        mshr_task_s1_bits_meta_alias <= io_mshrTask_bits_meta_alias;
+        mshr_task_s1_bits_meta_prefetch <= io_mshrTask_bits_meta_prefetch;
+        mshr_task_s1_bits_meta_prefetchSrc <= io_mshrTask_bits_meta_prefetchSrc;
+        mshr_task_s1_bits_meta_accessed <= io_mshrTask_bits_meta_accessed;
+        mshr_task_s1_bits_meta_tagErr <= io_mshrTask_bits_meta_tagErr;
+        mshr_task_s1_bits_meta_dataErr <= io_mshrTask_bits_meta_dataErr;
+        mshr_task_s1_bits_metaWen <= io_mshrTask_bits_metaWen;
+        mshr_task_s1_bits_tagWen <= io_mshrTask_bits_tagWen;
+        mshr_task_s1_bits_dsWen <= io_mshrTask_bits_dsWen;
+        mshr_task_s1_bits_wayMask <= io_mshrTask_bits_wayMask;
+        mshr_task_s1_bits_replTask <= io_mshrTask_bits_replTask;
+        mshr_task_s1_bits_cmoTask <= io_mshrTask_bits_cmoTask;
+        mshr_task_s1_bits_cmoAll <= io_mshrTask_bits_cmoAll;
+        mshr_task_s1_bits_reqSource <= io_mshrTask_bits_reqSource;
+        mshr_task_s1_bits_mergeA <= io_mshrTask_bits_mergeA;
+        mshr_task_s1_bits_aMergeTask_off <= io_mshrTask_bits_aMergeTask_off;
+        mshr_task_s1_bits_aMergeTask_alias <= io_mshrTask_bits_aMergeTask_alias;
+        mshr_task_s1_bits_aMergeTask_vaddr <= io_mshrTask_bits_aMergeTask_vaddr;
+        mshr_task_s1_bits_aMergeTask_isKeyword <= io_mshrTask_bits_aMergeTask_isKeyword;
+        mshr_task_s1_bits_aMergeTask_opcode <= io_mshrTask_bits_aMergeTask_opcode;
+        mshr_task_s1_bits_aMergeTask_param <= io_mshrTask_bits_aMergeTask_param;
+        mshr_task_s1_bits_aMergeTask_sourceId <= io_mshrTask_bits_aMergeTask_sourceId;
+        mshr_task_s1_bits_aMergeTask_meta_dirty <= io_mshrTask_bits_aMergeTask_meta_dirty;
+        mshr_task_s1_bits_aMergeTask_meta_state <= io_mshrTask_bits_aMergeTask_meta_state;
+        mshr_task_s1_bits_aMergeTask_meta_clients <=
+          io_mshrTask_bits_aMergeTask_meta_clients;
+        mshr_task_s1_bits_aMergeTask_meta_alias <= io_mshrTask_bits_aMergeTask_meta_alias;
+        mshr_task_s1_bits_aMergeTask_meta_prefetch <=
+          io_mshrTask_bits_aMergeTask_meta_prefetch;
+        mshr_task_s1_bits_aMergeTask_meta_prefetchSrc <=
+          io_mshrTask_bits_aMergeTask_meta_prefetchSrc;
+        mshr_task_s1_bits_aMergeTask_meta_accessed <=
+          io_mshrTask_bits_aMergeTask_meta_accessed;
+        mshr_task_s1_bits_aMergeTask_meta_tagErr <=
+          io_mshrTask_bits_aMergeTask_meta_tagErr;
+        mshr_task_s1_bits_aMergeTask_meta_dataErr <=
+          io_mshrTask_bits_aMergeTask_meta_dataErr;
+        mshr_task_s1_bits_snpHitRelease <= io_mshrTask_bits_snpHitRelease;
+        mshr_task_s1_bits_snpHitReleaseToInval <= io_mshrTask_bits_snpHitReleaseToInval;
+        mshr_task_s1_bits_snpHitReleaseToClean <= io_mshrTask_bits_snpHitReleaseToClean;
+        mshr_task_s1_bits_snpHitReleaseWithData <= io_mshrTask_bits_snpHitReleaseWithData;
+        mshr_task_s1_bits_snpHitReleaseIdx <= io_mshrTask_bits_snpHitReleaseIdx;
+        mshr_task_s1_bits_snpHitReleaseMeta_dirty <=
+          io_mshrTask_bits_snpHitReleaseMeta_dirty;
+        mshr_task_s1_bits_snpHitReleaseMeta_state <=
+          io_mshrTask_bits_snpHitReleaseMeta_state;
+        mshr_task_s1_bits_snpHitReleaseMeta_clients <=
+          io_mshrTask_bits_snpHitReleaseMeta_clients;
+        mshr_task_s1_bits_snpHitReleaseMeta_alias <=
+          io_mshrTask_bits_snpHitReleaseMeta_alias;
+        mshr_task_s1_bits_snpHitReleaseMeta_prefetch <=
+          io_mshrTask_bits_snpHitReleaseMeta_prefetch;
+        mshr_task_s1_bits_snpHitReleaseMeta_prefetchSrc <=
+          io_mshrTask_bits_snpHitReleaseMeta_prefetchSrc;
+        mshr_task_s1_bits_snpHitReleaseMeta_accessed <=
+          io_mshrTask_bits_snpHitReleaseMeta_accessed;
+        mshr_task_s1_bits_snpHitReleaseMeta_tagErr <=
+          io_mshrTask_bits_snpHitReleaseMeta_tagErr;
+        mshr_task_s1_bits_snpHitReleaseMeta_dataErr <=
+          io_mshrTask_bits_snpHitReleaseMeta_dataErr;
+        mshr_task_s1_bits_tgtID <= io_mshrTask_bits_tgtID;
+        mshr_task_s1_bits_srcID <= io_mshrTask_bits_srcID;
+        mshr_task_s1_bits_txnID <= io_mshrTask_bits_txnID;
+        mshr_task_s1_bits_homeNID <= io_mshrTask_bits_homeNID;
+        mshr_task_s1_bits_dbID <= io_mshrTask_bits_dbID;
+        mshr_task_s1_bits_fwdNID <= io_mshrTask_bits_fwdNID;
+        mshr_task_s1_bits_fwdTxnID <= io_mshrTask_bits_fwdTxnID;
+        mshr_task_s1_bits_chiOpcode <= io_mshrTask_bits_chiOpcode;
+        mshr_task_s1_bits_resp <= io_mshrTask_bits_resp;
+        mshr_task_s1_bits_fwdState <= io_mshrTask_bits_fwdState;
+        mshr_task_s1_bits_pCrdType <= io_mshrTask_bits_pCrdType;
+        mshr_task_s1_bits_retToSrc <= io_mshrTask_bits_retToSrc;
+        mshr_task_s1_bits_likelyshared <= io_mshrTask_bits_likelyshared;
+        mshr_task_s1_bits_expCompAck <= io_mshrTask_bits_expCompAck;
+        mshr_task_s1_bits_allowRetry <= io_mshrTask_bits_allowRetry;
+        mshr_task_s1_bits_memAttr_allocate <= io_mshrTask_bits_memAttr_allocate;
+        mshr_task_s1_bits_memAttr_cacheable <= io_mshrTask_bits_memAttr_cacheable;
+        mshr_task_s1_bits_memAttr_device <= io_mshrTask_bits_memAttr_device;
+        mshr_task_s1_bits_memAttr_ewa <= io_mshrTask_bits_memAttr_ewa;
+        mshr_task_s1_bits_traceTag <= io_mshrTask_bits_traceTag;
+      end
+      task_s2_valid <= s1_fire;
+      if (s1_fire) begin
+        task_s2_bits_channel <= task_s1_bits_channel;
+        task_s2_bits_txChannel <= task_s1_bits_txChannel;
+        task_s2_bits_set <= task_s1_bits_set;
+        task_s2_bits_tag <= task_s1_bits_tag;
+        task_s2_bits_off <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_off
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_off
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_off : io_sinkA_bits_off;
+        task_s2_bits_alias <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_alias
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_alias
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_alias : io_sinkA_bits_alias;
+        task_s2_bits_vaddr <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_vaddr
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_vaddr
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_vaddr : io_sinkA_bits_vaddr;
+        task_s2_bits_isKeyword <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_isKeyword
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_isKeyword
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_isKeyword
+                    : io_sinkA_bits_isKeyword;
+        task_s2_bits_opcode <= task_s1_bits_opcode;
+        task_s2_bits_param <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_param
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_param
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_param : io_sinkA_bits_param;
+        task_s2_bits_size <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_size
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_size
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_size : io_sinkA_bits_size;
+        task_s2_bits_sourceId <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_sourceId
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_sourceId
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_sourceId
+                    : io_sinkA_bits_sourceId;
+        task_s2_bits_bufIdx <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_bufIdx
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_bufIdx
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_bufIdx : io_sinkA_bits_bufIdx;
+        task_s2_bits_needProbeAckData <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_needProbeAckData
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_needProbeAckData
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_needProbeAckData
+                    : io_sinkA_bits_needProbeAckData;
+        task_s2_bits_denied <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_denied
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_denied
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_denied : io_sinkA_bits_denied;
+        task_s2_bits_corrupt <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_corrupt
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_corrupt
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_corrupt : io_sinkA_bits_corrupt;
+        task_s2_bits_mshrTask <= task_s1_bits_mshrTask;
+        task_s2_bits_mshrId <= task_s1_bits_mshrId;
+        task_s2_bits_aliasTask <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aliasTask
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aliasTask
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aliasTask
+                    : io_sinkA_bits_aliasTask;
+        task_s2_bits_useProbeData <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_useProbeData
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_useProbeData
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_useProbeData
+                    : io_sinkA_bits_useProbeData;
+        task_s2_bits_mshrRetry <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_mshrRetry
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_mshrRetry
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_mshrRetry
+                    : io_sinkA_bits_mshrRetry;
+        task_s2_bits_readProbeDataDown <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_readProbeDataDown
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_readProbeDataDown
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_readProbeDataDown
+                    : io_sinkA_bits_readProbeDataDown;
+        task_s2_bits_fromL2pft <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_fromL2pft
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_fromL2pft
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_fromL2pft
+                    : io_sinkA_bits_fromL2pft;
+        task_s2_bits_needHint <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_needHint
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_needHint
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_needHint
+                    : io_sinkA_bits_needHint;
+        task_s2_bits_dirty <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_dirty
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_dirty
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_dirty : io_sinkA_bits_dirty;
+        task_s2_bits_way <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_way
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_way
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_way : io_sinkA_bits_way;
+        task_s2_bits_meta_dirty <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_meta_dirty
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_meta_dirty
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_meta_dirty
+                    : io_sinkA_bits_meta_dirty;
+        task_s2_bits_meta_state <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_meta_state
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_meta_state
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_meta_state
+                    : io_sinkA_bits_meta_state;
+        task_s2_bits_meta_clients <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_meta_clients
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_meta_clients
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_meta_clients
+                    : io_sinkA_bits_meta_clients;
+        task_s2_bits_meta_alias <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_meta_alias
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_meta_alias
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_meta_alias
+                    : io_sinkA_bits_meta_alias;
+        task_s2_bits_meta_prefetch <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_meta_prefetch
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_meta_prefetch
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_meta_prefetch
+                    : io_sinkA_bits_meta_prefetch;
+        task_s2_bits_meta_prefetchSrc <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_meta_prefetchSrc
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_meta_prefetchSrc
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_meta_prefetchSrc
+                    : io_sinkA_bits_meta_prefetchSrc;
+        task_s2_bits_meta_accessed <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_meta_accessed
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_meta_accessed
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_meta_accessed
+                    : io_sinkA_bits_meta_accessed;
+        task_s2_bits_meta_tagErr <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_meta_tagErr
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_meta_tagErr
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_meta_tagErr
+                    : io_sinkA_bits_meta_tagErr;
+        task_s2_bits_meta_dataErr <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_meta_dataErr
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_meta_dataErr
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_meta_dataErr
+                    : io_sinkA_bits_meta_dataErr;
+        task_s2_bits_metaWen <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_metaWen
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_metaWen
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_metaWen : io_sinkA_bits_metaWen;
+        task_s2_bits_tagWen <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_tagWen
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_tagWen
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_tagWen : io_sinkA_bits_tagWen;
+        task_s2_bits_dsWen <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_dsWen
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_dsWen
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_dsWen : io_sinkA_bits_dsWen;
+        task_s2_bits_wayMask <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_wayMask
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_wayMask
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_wayMask : io_sinkA_bits_wayMask;
+        task_s2_bits_replTask <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_replTask
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_replTask
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_replTask
+                    : io_sinkA_bits_replTask;
+        task_s2_bits_cmoTask <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_cmoTask
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_cmoTask
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_cmoTask : io_sinkA_bits_cmoTask;
+        task_s2_bits_cmoAll <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_cmoAll
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_cmoAll
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_cmoAll : io_sinkA_bits_cmoAll;
+        task_s2_bits_reqSource <= task_s1_bits_reqSource;
+        task_s2_bits_mergeA <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_mergeA
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_mergeA
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_mergeA : io_sinkA_bits_mergeA;
+        task_s2_bits_aMergeTask_off <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_off
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_off
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_off
+                    : io_sinkA_bits_aMergeTask_off;
+        task_s2_bits_aMergeTask_alias <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_alias
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_alias
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_alias
+                    : io_sinkA_bits_aMergeTask_alias;
+        task_s2_bits_aMergeTask_vaddr <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_vaddr
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_vaddr
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_vaddr
+                    : io_sinkA_bits_aMergeTask_vaddr;
+        task_s2_bits_aMergeTask_isKeyword <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_isKeyword
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_isKeyword
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_isKeyword
+                    : io_sinkA_bits_aMergeTask_isKeyword;
+        task_s2_bits_aMergeTask_opcode <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_opcode
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_opcode
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_opcode
+                    : io_sinkA_bits_aMergeTask_opcode;
+        task_s2_bits_aMergeTask_param <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_param
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_param
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_param
+                    : io_sinkA_bits_aMergeTask_param;
+        task_s2_bits_aMergeTask_sourceId <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_sourceId
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_sourceId
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_sourceId
+                    : io_sinkA_bits_aMergeTask_sourceId;
+        task_s2_bits_aMergeTask_meta_dirty <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_meta_dirty
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_meta_dirty
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_meta_dirty
+                    : io_sinkA_bits_aMergeTask_meta_dirty;
+        task_s2_bits_aMergeTask_meta_state <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_meta_state
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_meta_state
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_meta_state
+                    : io_sinkA_bits_aMergeTask_meta_state;
+        task_s2_bits_aMergeTask_meta_clients <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_meta_clients
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_meta_clients
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_meta_clients
+                    : io_sinkA_bits_aMergeTask_meta_clients;
+        task_s2_bits_aMergeTask_meta_alias <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_meta_alias
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_meta_alias
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_meta_alias
+                    : io_sinkA_bits_aMergeTask_meta_alias;
+        task_s2_bits_aMergeTask_meta_prefetch <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_meta_prefetch
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_meta_prefetch
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_meta_prefetch
+                    : io_sinkA_bits_aMergeTask_meta_prefetch;
+        task_s2_bits_aMergeTask_meta_prefetchSrc <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_meta_prefetchSrc
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_meta_prefetchSrc
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_meta_prefetchSrc
+                    : io_sinkA_bits_aMergeTask_meta_prefetchSrc;
+        task_s2_bits_aMergeTask_meta_accessed <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_meta_accessed
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_meta_accessed
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_meta_accessed
+                    : io_sinkA_bits_aMergeTask_meta_accessed;
+        task_s2_bits_aMergeTask_meta_tagErr <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_meta_tagErr
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_meta_tagErr
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_meta_tagErr
+                    : io_sinkA_bits_aMergeTask_meta_tagErr;
+        task_s2_bits_aMergeTask_meta_dataErr <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_aMergeTask_meta_dataErr
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_aMergeTask_meta_dataErr
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_aMergeTask_meta_dataErr
+                    : io_sinkA_bits_aMergeTask_meta_dataErr;
+        task_s2_bits_snpHitRelease <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitRelease
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitRelease
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitRelease
+                    : io_sinkA_bits_snpHitRelease;
+        task_s2_bits_snpHitReleaseToInval <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseToInval
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseToInval
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseToInval
+                    : io_sinkA_bits_snpHitReleaseToInval;
+        task_s2_bits_snpHitReleaseToClean <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseToClean
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseToClean
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseToClean
+                    : io_sinkA_bits_snpHitReleaseToClean;
+        task_s2_bits_snpHitReleaseWithData <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseWithData
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseWithData
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseWithData
+                    : io_sinkA_bits_snpHitReleaseWithData;
+        task_s2_bits_snpHitReleaseIdx <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseIdx
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseIdx
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseIdx
+                    : io_sinkA_bits_snpHitReleaseIdx;
+        task_s2_bits_snpHitReleaseMeta_dirty <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseMeta_dirty
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseMeta_dirty
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseMeta_dirty
+                    : io_sinkA_bits_snpHitReleaseMeta_dirty;
+        task_s2_bits_snpHitReleaseMeta_state <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseMeta_state
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseMeta_state
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseMeta_state
+                    : io_sinkA_bits_snpHitReleaseMeta_state;
+        task_s2_bits_snpHitReleaseMeta_clients <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseMeta_clients
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseMeta_clients
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseMeta_clients
+                    : io_sinkA_bits_snpHitReleaseMeta_clients;
+        task_s2_bits_snpHitReleaseMeta_alias <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseMeta_alias
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseMeta_alias
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseMeta_alias
+                    : io_sinkA_bits_snpHitReleaseMeta_alias;
+        task_s2_bits_snpHitReleaseMeta_prefetch <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseMeta_prefetch
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseMeta_prefetch
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseMeta_prefetch
+                    : io_sinkA_bits_snpHitReleaseMeta_prefetch;
+        task_s2_bits_snpHitReleaseMeta_prefetchSrc <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseMeta_prefetchSrc
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseMeta_prefetchSrc
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseMeta_prefetchSrc
+                    : io_sinkA_bits_snpHitReleaseMeta_prefetchSrc;
+        task_s2_bits_snpHitReleaseMeta_accessed <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseMeta_accessed
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseMeta_accessed
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseMeta_accessed
+                    : io_sinkA_bits_snpHitReleaseMeta_accessed;
+        task_s2_bits_snpHitReleaseMeta_tagErr <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseMeta_tagErr
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseMeta_tagErr
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseMeta_tagErr
+                    : io_sinkA_bits_snpHitReleaseMeta_tagErr;
+        task_s2_bits_snpHitReleaseMeta_dataErr <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_snpHitReleaseMeta_dataErr
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_snpHitReleaseMeta_dataErr
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_snpHitReleaseMeta_dataErr
+                    : io_sinkA_bits_snpHitReleaseMeta_dataErr;
+        task_s2_bits_tgtID <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_tgtID
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_tgtID
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_tgtID : io_sinkA_bits_tgtID;
+        task_s2_bits_srcID <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_srcID
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_srcID
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_srcID : io_sinkA_bits_srcID;
+        task_s2_bits_txnID <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_txnID
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_txnID
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_txnID : io_sinkA_bits_txnID;
+        task_s2_bits_homeNID <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_homeNID
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_homeNID
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_homeNID : io_sinkA_bits_homeNID;
+        task_s2_bits_dbID <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_dbID
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_dbID
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_dbID : io_sinkA_bits_dbID;
+        task_s2_bits_fwdNID <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_fwdNID
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_fwdNID
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_fwdNID : io_sinkA_bits_fwdNID;
+        task_s2_bits_fwdTxnID <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_fwdTxnID
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_fwdTxnID
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_fwdTxnID
+                    : io_sinkA_bits_fwdTxnID;
+        task_s2_bits_chiOpcode <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_chiOpcode
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_chiOpcode
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_chiOpcode
+                    : io_sinkA_bits_chiOpcode;
+        task_s2_bits_resp <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_resp
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_resp
+                : _chnl_task_s1_bits_T_1 ? io_sinkB_bits_resp : io_sinkA_bits_resp;
+        task_s2_bits_fwdState <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_fwdState
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_fwdState
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_fwdState
+                    : io_sinkA_bits_fwdState;
+        task_s2_bits_pCrdType <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_pCrdType
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_pCrdType
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_pCrdType
+                    : io_sinkA_bits_pCrdType;
+        task_s2_bits_retToSrc <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_retToSrc
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_retToSrc
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_retToSrc
+                    : io_sinkA_bits_retToSrc;
+        task_s2_bits_likelyshared <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_likelyshared
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_likelyshared
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_likelyshared
+                    : io_sinkA_bits_likelyshared;
+        task_s2_bits_expCompAck <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_expCompAck
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_expCompAck
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_expCompAck
+                    : io_sinkA_bits_expCompAck;
+        task_s2_bits_allowRetry <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_allowRetry
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_allowRetry
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_allowRetry
+                    : io_sinkA_bits_allowRetry;
+        task_s2_bits_memAttr_allocate <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_memAttr_allocate
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_memAttr_allocate
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_memAttr_allocate
+                    : io_sinkA_bits_memAttr_allocate;
+        task_s2_bits_memAttr_cacheable <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_memAttr_cacheable
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_memAttr_cacheable
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_memAttr_cacheable
+                    : io_sinkA_bits_memAttr_cacheable;
+        task_s2_bits_memAttr_device <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_memAttr_device
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_memAttr_device
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_memAttr_device
+                    : io_sinkA_bits_memAttr_device;
+        task_s2_bits_memAttr_ewa <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_memAttr_ewa
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_memAttr_ewa
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_memAttr_ewa
+                    : io_sinkA_bits_memAttr_ewa;
+        task_s2_bits_traceTag <=
+          mshr_task_s1_valid
+            ? mshr_task_s1_bits_traceTag
+            : _chnl_task_s1_bits_T
+                ? io_sinkC_bits_traceTag
+                : _chnl_task_s1_bits_T_1
+                    ? io_sinkB_bits_traceTag
+                    : io_sinkA_bits_traceTag;
+      end
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock)
+    ds_mcp2_stall <=
+      s1_fire & ~(io_sinkA_ready_0 & io_sinkA_valid & io_sinkA_bits_opcode == 4'h5);
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:24];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h19; i += 5'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        resetFinish = _RANDOM[5'h0][0];
+        resetIdx = _RANDOM[5'h0][8:1];
+        mshr_task_s1_valid = _RANDOM[5'h0][9];
+        mshr_task_s1_bits_channel = _RANDOM[5'h0][12:10];
+        mshr_task_s1_bits_txChannel = _RANDOM[5'h0][15:13];
+        mshr_task_s1_bits_set = _RANDOM[5'h0][23:16];
+        mshr_task_s1_bits_tag = {_RANDOM[5'h0][31:24], _RANDOM[5'h1][25:0]};
+        mshr_task_s1_bits_off = _RANDOM[5'h1][31:26];
+        mshr_task_s1_bits_alias = _RANDOM[5'h2][0];
+        mshr_task_s1_bits_vaddr = {_RANDOM[5'h2][31:1], _RANDOM[5'h3][12:0]};
+        mshr_task_s1_bits_isKeyword = _RANDOM[5'h3][13];
+        mshr_task_s1_bits_opcode = _RANDOM[5'h3][17:14];
+        mshr_task_s1_bits_param = _RANDOM[5'h3][20:18];
+        mshr_task_s1_bits_size = _RANDOM[5'h3][23:21];
+        mshr_task_s1_bits_sourceId = _RANDOM[5'h3][30:24];
+        mshr_task_s1_bits_bufIdx = {_RANDOM[5'h3][31], _RANDOM[5'h4][0]};
+        mshr_task_s1_bits_needProbeAckData = _RANDOM[5'h4][1];
+        mshr_task_s1_bits_denied = _RANDOM[5'h4][2];
+        mshr_task_s1_bits_corrupt = _RANDOM[5'h4][3];
+        mshr_task_s1_bits_mshrTask = _RANDOM[5'h4][4];
+        mshr_task_s1_bits_mshrId = _RANDOM[5'h4][12:5];
+        mshr_task_s1_bits_aliasTask = _RANDOM[5'h4][13];
+        mshr_task_s1_bits_useProbeData = _RANDOM[5'h4][14];
+        mshr_task_s1_bits_mshrRetry = _RANDOM[5'h4][15];
+        mshr_task_s1_bits_readProbeDataDown = _RANDOM[5'h4][16];
+        mshr_task_s1_bits_fromL2pft = _RANDOM[5'h4][17];
+        mshr_task_s1_bits_needHint = _RANDOM[5'h4][18];
+        mshr_task_s1_bits_dirty = _RANDOM[5'h4][19];
+        mshr_task_s1_bits_way = _RANDOM[5'h4][22:20];
+        mshr_task_s1_bits_meta_dirty = _RANDOM[5'h4][23];
+        mshr_task_s1_bits_meta_state = _RANDOM[5'h4][25:24];
+        mshr_task_s1_bits_meta_clients = _RANDOM[5'h4][26];
+        mshr_task_s1_bits_meta_alias = _RANDOM[5'h4][27];
+        mshr_task_s1_bits_meta_prefetch = _RANDOM[5'h4][28];
+        mshr_task_s1_bits_meta_prefetchSrc = {_RANDOM[5'h4][31:29], _RANDOM[5'h5][0]};
+        mshr_task_s1_bits_meta_accessed = _RANDOM[5'h5][1];
+        mshr_task_s1_bits_meta_tagErr = _RANDOM[5'h5][2];
+        mshr_task_s1_bits_meta_dataErr = _RANDOM[5'h5][3];
+        mshr_task_s1_bits_metaWen = _RANDOM[5'h5][4];
+        mshr_task_s1_bits_tagWen = _RANDOM[5'h5][5];
+        mshr_task_s1_bits_dsWen = _RANDOM[5'h5][6];
+        mshr_task_s1_bits_wayMask = _RANDOM[5'h5][14:7];
+        mshr_task_s1_bits_replTask = _RANDOM[5'h5][15];
+        mshr_task_s1_bits_cmoTask = _RANDOM[5'h5][16];
+        mshr_task_s1_bits_cmoAll = _RANDOM[5'h5][17];
+        mshr_task_s1_bits_reqSource = _RANDOM[5'h5][22:18];
+        mshr_task_s1_bits_mergeA = _RANDOM[5'h5][23];
+        mshr_task_s1_bits_aMergeTask_off = _RANDOM[5'h5][29:24];
+        mshr_task_s1_bits_aMergeTask_alias = _RANDOM[5'h5][30];
+        mshr_task_s1_bits_aMergeTask_vaddr =
+          {_RANDOM[5'h5][31], _RANDOM[5'h6], _RANDOM[5'h7][10:0]};
+        mshr_task_s1_bits_aMergeTask_isKeyword = _RANDOM[5'h7][11];
+        mshr_task_s1_bits_aMergeTask_opcode = _RANDOM[5'h7][14:12];
+        mshr_task_s1_bits_aMergeTask_param = _RANDOM[5'h7][17:15];
+        mshr_task_s1_bits_aMergeTask_sourceId = _RANDOM[5'h7][24:18];
+        mshr_task_s1_bits_aMergeTask_meta_dirty = _RANDOM[5'h7][25];
+        mshr_task_s1_bits_aMergeTask_meta_state = _RANDOM[5'h7][27:26];
+        mshr_task_s1_bits_aMergeTask_meta_clients = _RANDOM[5'h7][28];
+        mshr_task_s1_bits_aMergeTask_meta_alias = _RANDOM[5'h7][29];
+        mshr_task_s1_bits_aMergeTask_meta_prefetch = _RANDOM[5'h7][30];
+        mshr_task_s1_bits_aMergeTask_meta_prefetchSrc =
+          {_RANDOM[5'h7][31], _RANDOM[5'h8][2:0]};
+        mshr_task_s1_bits_aMergeTask_meta_accessed = _RANDOM[5'h8][3];
+        mshr_task_s1_bits_aMergeTask_meta_tagErr = _RANDOM[5'h8][4];
+        mshr_task_s1_bits_aMergeTask_meta_dataErr = _RANDOM[5'h8][5];
+        mshr_task_s1_bits_snpHitRelease = _RANDOM[5'h8][6];
+        mshr_task_s1_bits_snpHitReleaseToInval = _RANDOM[5'h8][7];
+        mshr_task_s1_bits_snpHitReleaseToClean = _RANDOM[5'h8][8];
+        mshr_task_s1_bits_snpHitReleaseWithData = _RANDOM[5'h8][9];
+        mshr_task_s1_bits_snpHitReleaseIdx = _RANDOM[5'h8][17:10];
+        mshr_task_s1_bits_snpHitReleaseMeta_dirty = _RANDOM[5'h8][18];
+        mshr_task_s1_bits_snpHitReleaseMeta_state = _RANDOM[5'h8][20:19];
+        mshr_task_s1_bits_snpHitReleaseMeta_clients = _RANDOM[5'h8][21];
+        mshr_task_s1_bits_snpHitReleaseMeta_alias = _RANDOM[5'h8][22];
+        mshr_task_s1_bits_snpHitReleaseMeta_prefetch = _RANDOM[5'h8][23];
+        mshr_task_s1_bits_snpHitReleaseMeta_prefetchSrc = _RANDOM[5'h8][27:24];
+        mshr_task_s1_bits_snpHitReleaseMeta_accessed = _RANDOM[5'h8][28];
+        mshr_task_s1_bits_snpHitReleaseMeta_tagErr = _RANDOM[5'h8][29];
+        mshr_task_s1_bits_snpHitReleaseMeta_dataErr = _RANDOM[5'h8][30];
+        mshr_task_s1_bits_tgtID = {_RANDOM[5'h8][31], _RANDOM[5'h9][9:0]};
+        mshr_task_s1_bits_srcID = _RANDOM[5'h9][20:10];
+        mshr_task_s1_bits_txnID = {_RANDOM[5'h9][31:21], _RANDOM[5'hA][0]};
+        mshr_task_s1_bits_homeNID = _RANDOM[5'hA][11:1];
+        mshr_task_s1_bits_dbID = _RANDOM[5'hA][23:12];
+        mshr_task_s1_bits_fwdNID = {_RANDOM[5'hA][31:24], _RANDOM[5'hB][2:0]};
+        mshr_task_s1_bits_fwdTxnID = _RANDOM[5'hB][14:3];
+        mshr_task_s1_bits_chiOpcode = _RANDOM[5'hB][21:15];
+        mshr_task_s1_bits_resp = _RANDOM[5'hB][24:22];
+        mshr_task_s1_bits_fwdState = _RANDOM[5'hB][27:25];
+        mshr_task_s1_bits_pCrdType = _RANDOM[5'hB][31:28];
+        mshr_task_s1_bits_retToSrc = _RANDOM[5'hC][0];
+        mshr_task_s1_bits_likelyshared = _RANDOM[5'hC][1];
+        mshr_task_s1_bits_expCompAck = _RANDOM[5'hC][2];
+        mshr_task_s1_bits_allowRetry = _RANDOM[5'hC][3];
+        mshr_task_s1_bits_memAttr_allocate = _RANDOM[5'hC][4];
+        mshr_task_s1_bits_memAttr_cacheable = _RANDOM[5'hC][5];
+        mshr_task_s1_bits_memAttr_device = _RANDOM[5'hC][6];
+        mshr_task_s1_bits_memAttr_ewa = _RANDOM[5'hC][7];
+        mshr_task_s1_bits_traceTag = _RANDOM[5'hC][8];
+        ds_mcp2_stall = _RANDOM[5'hC][9];
+        task_s2_valid = _RANDOM[5'hC][10];
+        task_s2_bits_channel = _RANDOM[5'hC][13:11];
+        task_s2_bits_txChannel = _RANDOM[5'hC][16:14];
+        task_s2_bits_set = _RANDOM[5'hC][24:17];
+        task_s2_bits_tag = {_RANDOM[5'hC][31:25], _RANDOM[5'hD][26:0]};
+        task_s2_bits_off = {_RANDOM[5'hD][31:27], _RANDOM[5'hE][0]};
+        task_s2_bits_alias = _RANDOM[5'hE][1];
+        task_s2_bits_vaddr = {_RANDOM[5'hE][31:2], _RANDOM[5'hF][13:0]};
+        task_s2_bits_isKeyword = _RANDOM[5'hF][14];
+        task_s2_bits_opcode = _RANDOM[5'hF][18:15];
+        task_s2_bits_param = _RANDOM[5'hF][21:19];
+        task_s2_bits_size = _RANDOM[5'hF][24:22];
+        task_s2_bits_sourceId = _RANDOM[5'hF][31:25];
+        task_s2_bits_bufIdx = _RANDOM[5'h10][1:0];
+        task_s2_bits_needProbeAckData = _RANDOM[5'h10][2];
+        task_s2_bits_denied = _RANDOM[5'h10][3];
+        task_s2_bits_corrupt = _RANDOM[5'h10][4];
+        task_s2_bits_mshrTask = _RANDOM[5'h10][5];
+        task_s2_bits_mshrId = _RANDOM[5'h10][13:6];
+        task_s2_bits_aliasTask = _RANDOM[5'h10][14];
+        task_s2_bits_useProbeData = _RANDOM[5'h10][15];
+        task_s2_bits_mshrRetry = _RANDOM[5'h10][16];
+        task_s2_bits_readProbeDataDown = _RANDOM[5'h10][17];
+        task_s2_bits_fromL2pft = _RANDOM[5'h10][18];
+        task_s2_bits_needHint = _RANDOM[5'h10][19];
+        task_s2_bits_dirty = _RANDOM[5'h10][20];
+        task_s2_bits_way = _RANDOM[5'h10][23:21];
+        task_s2_bits_meta_dirty = _RANDOM[5'h10][24];
+        task_s2_bits_meta_state = _RANDOM[5'h10][26:25];
+        task_s2_bits_meta_clients = _RANDOM[5'h10][27];
+        task_s2_bits_meta_alias = _RANDOM[5'h10][28];
+        task_s2_bits_meta_prefetch = _RANDOM[5'h10][29];
+        task_s2_bits_meta_prefetchSrc = {_RANDOM[5'h10][31:30], _RANDOM[5'h11][1:0]};
+        task_s2_bits_meta_accessed = _RANDOM[5'h11][2];
+        task_s2_bits_meta_tagErr = _RANDOM[5'h11][3];
+        task_s2_bits_meta_dataErr = _RANDOM[5'h11][4];
+        task_s2_bits_metaWen = _RANDOM[5'h11][5];
+        task_s2_bits_tagWen = _RANDOM[5'h11][6];
+        task_s2_bits_dsWen = _RANDOM[5'h11][7];
+        task_s2_bits_wayMask = _RANDOM[5'h11][15:8];
+        task_s2_bits_replTask = _RANDOM[5'h11][16];
+        task_s2_bits_cmoTask = _RANDOM[5'h11][17];
+        task_s2_bits_cmoAll = _RANDOM[5'h11][18];
+        task_s2_bits_reqSource = _RANDOM[5'h11][23:19];
+        task_s2_bits_mergeA = _RANDOM[5'h11][24];
+        task_s2_bits_aMergeTask_off = _RANDOM[5'h11][30:25];
+        task_s2_bits_aMergeTask_alias = _RANDOM[5'h11][31];
+        task_s2_bits_aMergeTask_vaddr = {_RANDOM[5'h12], _RANDOM[5'h13][11:0]};
+        task_s2_bits_aMergeTask_isKeyword = _RANDOM[5'h13][12];
+        task_s2_bits_aMergeTask_opcode = _RANDOM[5'h13][15:13];
+        task_s2_bits_aMergeTask_param = _RANDOM[5'h13][18:16];
+        task_s2_bits_aMergeTask_sourceId = _RANDOM[5'h13][25:19];
+        task_s2_bits_aMergeTask_meta_dirty = _RANDOM[5'h13][26];
+        task_s2_bits_aMergeTask_meta_state = _RANDOM[5'h13][28:27];
+        task_s2_bits_aMergeTask_meta_clients = _RANDOM[5'h13][29];
+        task_s2_bits_aMergeTask_meta_alias = _RANDOM[5'h13][30];
+        task_s2_bits_aMergeTask_meta_prefetch = _RANDOM[5'h13][31];
+        task_s2_bits_aMergeTask_meta_prefetchSrc = _RANDOM[5'h14][3:0];
+        task_s2_bits_aMergeTask_meta_accessed = _RANDOM[5'h14][4];
+        task_s2_bits_aMergeTask_meta_tagErr = _RANDOM[5'h14][5];
+        task_s2_bits_aMergeTask_meta_dataErr = _RANDOM[5'h14][6];
+        task_s2_bits_snpHitRelease = _RANDOM[5'h14][7];
+        task_s2_bits_snpHitReleaseToInval = _RANDOM[5'h14][8];
+        task_s2_bits_snpHitReleaseToClean = _RANDOM[5'h14][9];
+        task_s2_bits_snpHitReleaseWithData = _RANDOM[5'h14][10];
+        task_s2_bits_snpHitReleaseIdx = _RANDOM[5'h14][18:11];
+        task_s2_bits_snpHitReleaseMeta_dirty = _RANDOM[5'h14][19];
+        task_s2_bits_snpHitReleaseMeta_state = _RANDOM[5'h14][21:20];
+        task_s2_bits_snpHitReleaseMeta_clients = _RANDOM[5'h14][22];
+        task_s2_bits_snpHitReleaseMeta_alias = _RANDOM[5'h14][23];
+        task_s2_bits_snpHitReleaseMeta_prefetch = _RANDOM[5'h14][24];
+        task_s2_bits_snpHitReleaseMeta_prefetchSrc = _RANDOM[5'h14][28:25];
+        task_s2_bits_snpHitReleaseMeta_accessed = _RANDOM[5'h14][29];
+        task_s2_bits_snpHitReleaseMeta_tagErr = _RANDOM[5'h14][30];
+        task_s2_bits_snpHitReleaseMeta_dataErr = _RANDOM[5'h14][31];
+        task_s2_bits_tgtID = _RANDOM[5'h15][10:0];
+        task_s2_bits_srcID = _RANDOM[5'h15][21:11];
+        task_s2_bits_txnID = {_RANDOM[5'h15][31:22], _RANDOM[5'h16][1:0]};
+        task_s2_bits_homeNID = _RANDOM[5'h16][12:2];
+        task_s2_bits_dbID = _RANDOM[5'h16][24:13];
+        task_s2_bits_fwdNID = {_RANDOM[5'h16][31:25], _RANDOM[5'h17][3:0]};
+        task_s2_bits_fwdTxnID = _RANDOM[5'h17][15:4];
+        task_s2_bits_chiOpcode = _RANDOM[5'h17][22:16];
+        task_s2_bits_resp = _RANDOM[5'h17][25:23];
+        task_s2_bits_fwdState = _RANDOM[5'h17][28:26];
+        task_s2_bits_pCrdType = {_RANDOM[5'h17][31:29], _RANDOM[5'h18][0]};
+        task_s2_bits_retToSrc = _RANDOM[5'h18][1];
+        task_s2_bits_likelyshared = _RANDOM[5'h18][2];
+        task_s2_bits_expCompAck = _RANDOM[5'h18][3];
+        task_s2_bits_allowRetry = _RANDOM[5'h18][4];
+        task_s2_bits_memAttr_allocate = _RANDOM[5'h18][5];
+        task_s2_bits_memAttr_cacheable = _RANDOM[5'h18][6];
+        task_s2_bits_memAttr_device = _RANDOM[5'h18][7];
+        task_s2_bits_memAttr_ewa = _RANDOM[5'h18][8];
+        task_s2_bits_traceTag = _RANDOM[5'h18][9];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        resetFinish = 1'h0;
+        resetIdx = 8'hFF;
+        mshr_task_s1_valid = 1'h0;
+        mshr_task_s1_bits_channel = 3'h0;
+        mshr_task_s1_bits_txChannel = 3'h0;
+        mshr_task_s1_bits_set = 8'h0;
+        mshr_task_s1_bits_tag = 34'h0;
+        mshr_task_s1_bits_off = 6'h0;
+        mshr_task_s1_bits_alias = 1'h0;
+        mshr_task_s1_bits_vaddr = 44'h0;
+        mshr_task_s1_bits_isKeyword = 1'h0;
+        mshr_task_s1_bits_opcode = 4'h0;
+        mshr_task_s1_bits_param = 3'h0;
+        mshr_task_s1_bits_size = 3'h0;
+        mshr_task_s1_bits_sourceId = 7'h0;
+        mshr_task_s1_bits_bufIdx = 2'h0;
+        mshr_task_s1_bits_needProbeAckData = 1'h0;
+        mshr_task_s1_bits_denied = 1'h0;
+        mshr_task_s1_bits_corrupt = 1'h0;
+        mshr_task_s1_bits_mshrTask = 1'h0;
+        mshr_task_s1_bits_mshrId = 8'h0;
+        mshr_task_s1_bits_aliasTask = 1'h0;
+        mshr_task_s1_bits_useProbeData = 1'h0;
+        mshr_task_s1_bits_mshrRetry = 1'h0;
+        mshr_task_s1_bits_readProbeDataDown = 1'h0;
+        mshr_task_s1_bits_fromL2pft = 1'h0;
+        mshr_task_s1_bits_needHint = 1'h0;
+        mshr_task_s1_bits_dirty = 1'h0;
+        mshr_task_s1_bits_way = 3'h0;
+        mshr_task_s1_bits_meta_dirty = 1'h0;
+        mshr_task_s1_bits_meta_state = 2'h0;
+        mshr_task_s1_bits_meta_clients = 1'h0;
+        mshr_task_s1_bits_meta_alias = 1'h0;
+        mshr_task_s1_bits_meta_prefetch = 1'h0;
+        mshr_task_s1_bits_meta_prefetchSrc = 4'h0;
+        mshr_task_s1_bits_meta_accessed = 1'h0;
+        mshr_task_s1_bits_meta_tagErr = 1'h0;
+        mshr_task_s1_bits_meta_dataErr = 1'h0;
+        mshr_task_s1_bits_metaWen = 1'h0;
+        mshr_task_s1_bits_tagWen = 1'h0;
+        mshr_task_s1_bits_dsWen = 1'h0;
+        mshr_task_s1_bits_wayMask = 8'h0;
+        mshr_task_s1_bits_replTask = 1'h0;
+        mshr_task_s1_bits_cmoTask = 1'h0;
+        mshr_task_s1_bits_cmoAll = 1'h0;
+        mshr_task_s1_bits_reqSource = 5'h0;
+        mshr_task_s1_bits_mergeA = 1'h0;
+        mshr_task_s1_bits_aMergeTask_off = 6'h0;
+        mshr_task_s1_bits_aMergeTask_alias = 1'h0;
+        mshr_task_s1_bits_aMergeTask_vaddr = 44'h0;
+        mshr_task_s1_bits_aMergeTask_isKeyword = 1'h0;
+        mshr_task_s1_bits_aMergeTask_opcode = 3'h0;
+        mshr_task_s1_bits_aMergeTask_param = 3'h0;
+        mshr_task_s1_bits_aMergeTask_sourceId = 7'h0;
+        mshr_task_s1_bits_aMergeTask_meta_dirty = 1'h0;
+        mshr_task_s1_bits_aMergeTask_meta_state = 2'h0;
+        mshr_task_s1_bits_aMergeTask_meta_clients = 1'h0;
+        mshr_task_s1_bits_aMergeTask_meta_alias = 1'h0;
+        mshr_task_s1_bits_aMergeTask_meta_prefetch = 1'h0;
+        mshr_task_s1_bits_aMergeTask_meta_prefetchSrc = 4'h0;
+        mshr_task_s1_bits_aMergeTask_meta_accessed = 1'h0;
+        mshr_task_s1_bits_aMergeTask_meta_tagErr = 1'h0;
+        mshr_task_s1_bits_aMergeTask_meta_dataErr = 1'h0;
+        mshr_task_s1_bits_snpHitRelease = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseToInval = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseToClean = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseWithData = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseIdx = 8'h0;
+        mshr_task_s1_bits_snpHitReleaseMeta_dirty = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseMeta_state = 2'h0;
+        mshr_task_s1_bits_snpHitReleaseMeta_clients = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseMeta_alias = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseMeta_prefetch = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseMeta_prefetchSrc = 4'h0;
+        mshr_task_s1_bits_snpHitReleaseMeta_accessed = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseMeta_tagErr = 1'h0;
+        mshr_task_s1_bits_snpHitReleaseMeta_dataErr = 1'h0;
+        mshr_task_s1_bits_tgtID = 11'h0;
+        mshr_task_s1_bits_srcID = 11'h0;
+        mshr_task_s1_bits_txnID = 12'h0;
+        mshr_task_s1_bits_homeNID = 11'h0;
+        mshr_task_s1_bits_dbID = 12'h0;
+        mshr_task_s1_bits_fwdNID = 11'h0;
+        mshr_task_s1_bits_fwdTxnID = 12'h0;
+        mshr_task_s1_bits_chiOpcode = 7'h0;
+        mshr_task_s1_bits_resp = 3'h0;
+        mshr_task_s1_bits_fwdState = 3'h0;
+        mshr_task_s1_bits_pCrdType = 4'h0;
+        mshr_task_s1_bits_retToSrc = 1'h0;
+        mshr_task_s1_bits_likelyshared = 1'h0;
+        mshr_task_s1_bits_expCompAck = 1'h0;
+        mshr_task_s1_bits_allowRetry = 1'h0;
+        mshr_task_s1_bits_memAttr_allocate = 1'h0;
+        mshr_task_s1_bits_memAttr_cacheable = 1'h0;
+        mshr_task_s1_bits_memAttr_device = 1'h0;
+        mshr_task_s1_bits_memAttr_ewa = 1'h0;
+        mshr_task_s1_bits_traceTag = 1'h0;
+        task_s2_valid = 1'h0;
+        task_s2_bits_channel = 3'h0;
+        task_s2_bits_txChannel = 3'h0;
+        task_s2_bits_set = 8'h0;
+        task_s2_bits_tag = 34'h0;
+        task_s2_bits_off = 6'h0;
+        task_s2_bits_alias = 1'h0;
+        task_s2_bits_vaddr = 44'h0;
+        task_s2_bits_isKeyword = 1'h0;
+        task_s2_bits_opcode = 4'h0;
+        task_s2_bits_param = 3'h0;
+        task_s2_bits_size = 3'h0;
+        task_s2_bits_sourceId = 7'h0;
+        task_s2_bits_bufIdx = 2'h0;
+        task_s2_bits_needProbeAckData = 1'h0;
+        task_s2_bits_denied = 1'h0;
+        task_s2_bits_corrupt = 1'h0;
+        task_s2_bits_mshrTask = 1'h0;
+        task_s2_bits_mshrId = 8'h0;
+        task_s2_bits_aliasTask = 1'h0;
+        task_s2_bits_useProbeData = 1'h0;
+        task_s2_bits_mshrRetry = 1'h0;
+        task_s2_bits_readProbeDataDown = 1'h0;
+        task_s2_bits_fromL2pft = 1'h0;
+        task_s2_bits_needHint = 1'h0;
+        task_s2_bits_dirty = 1'h0;
+        task_s2_bits_way = 3'h0;
+        task_s2_bits_meta_dirty = 1'h0;
+        task_s2_bits_meta_state = 2'h0;
+        task_s2_bits_meta_clients = 1'h0;
+        task_s2_bits_meta_alias = 1'h0;
+        task_s2_bits_meta_prefetch = 1'h0;
+        task_s2_bits_meta_prefetchSrc = 4'h0;
+        task_s2_bits_meta_accessed = 1'h0;
+        task_s2_bits_meta_tagErr = 1'h0;
+        task_s2_bits_meta_dataErr = 1'h0;
+        task_s2_bits_metaWen = 1'h0;
+        task_s2_bits_tagWen = 1'h0;
+        task_s2_bits_dsWen = 1'h0;
+        task_s2_bits_wayMask = 8'h0;
+        task_s2_bits_replTask = 1'h0;
+        task_s2_bits_cmoTask = 1'h0;
+        task_s2_bits_cmoAll = 1'h0;
+        task_s2_bits_reqSource = 5'h0;
+        task_s2_bits_mergeA = 1'h0;
+        task_s2_bits_aMergeTask_off = 6'h0;
+        task_s2_bits_aMergeTask_alias = 1'h0;
+        task_s2_bits_aMergeTask_vaddr = 44'h0;
+        task_s2_bits_aMergeTask_isKeyword = 1'h0;
+        task_s2_bits_aMergeTask_opcode = 3'h0;
+        task_s2_bits_aMergeTask_param = 3'h0;
+        task_s2_bits_aMergeTask_sourceId = 7'h0;
+        task_s2_bits_aMergeTask_meta_dirty = 1'h0;
+        task_s2_bits_aMergeTask_meta_state = 2'h0;
+        task_s2_bits_aMergeTask_meta_clients = 1'h0;
+        task_s2_bits_aMergeTask_meta_alias = 1'h0;
+        task_s2_bits_aMergeTask_meta_prefetch = 1'h0;
+        task_s2_bits_aMergeTask_meta_prefetchSrc = 4'h0;
+        task_s2_bits_aMergeTask_meta_accessed = 1'h0;
+        task_s2_bits_aMergeTask_meta_tagErr = 1'h0;
+        task_s2_bits_aMergeTask_meta_dataErr = 1'h0;
+        task_s2_bits_snpHitRelease = 1'h0;
+        task_s2_bits_snpHitReleaseToInval = 1'h0;
+        task_s2_bits_snpHitReleaseToClean = 1'h0;
+        task_s2_bits_snpHitReleaseWithData = 1'h0;
+        task_s2_bits_snpHitReleaseIdx = 8'h0;
+        task_s2_bits_snpHitReleaseMeta_dirty = 1'h0;
+        task_s2_bits_snpHitReleaseMeta_state = 2'h0;
+        task_s2_bits_snpHitReleaseMeta_clients = 1'h0;
+        task_s2_bits_snpHitReleaseMeta_alias = 1'h0;
+        task_s2_bits_snpHitReleaseMeta_prefetch = 1'h0;
+        task_s2_bits_snpHitReleaseMeta_prefetchSrc = 4'h0;
+        task_s2_bits_snpHitReleaseMeta_accessed = 1'h0;
+        task_s2_bits_snpHitReleaseMeta_tagErr = 1'h0;
+        task_s2_bits_snpHitReleaseMeta_dataErr = 1'h0;
+        task_s2_bits_tgtID = 11'h0;
+        task_s2_bits_srcID = 11'h0;
+        task_s2_bits_txnID = 12'h0;
+        task_s2_bits_homeNID = 11'h0;
+        task_s2_bits_dbID = 12'h0;
+        task_s2_bits_fwdNID = 11'h0;
+        task_s2_bits_fwdTxnID = 12'h0;
+        task_s2_bits_chiOpcode = 7'h0;
+        task_s2_bits_resp = 3'h0;
+        task_s2_bits_fwdState = 3'h0;
+        task_s2_bits_pCrdType = 4'h0;
+        task_s2_bits_retToSrc = 1'h0;
+        task_s2_bits_likelyshared = 1'h0;
+        task_s2_bits_expCompAck = 1'h0;
+        task_s2_bits_allowRetry = 1'h0;
+        task_s2_bits_memAttr_allocate = 1'h0;
+        task_s2_bits_memAttr_cacheable = 1'h0;
+        task_s2_bits_memAttr_device = 1'h0;
+        task_s2_bits_memAttr_ewa = 1'h0;
+        task_s2_bits_traceTag = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  assign io_sinkA_ready = io_sinkA_ready_0;
+  assign io_s1Entrance_valid =
+    mshr_task_s1_valid & ~ds_mcp2_stall & mshr_task_s1_bits_metaWen
+    | io_sinkCHintQInfo_valid_0 | io_sinkB_ready_0 & io_sinkB_valid;
+  assign io_s1Entrance_bits_set =
+    mshr_task_s1_valid & mshr_task_s1_bits_metaWen
+      ? mshr_task_s1_bits_set
+      : io_sinkCHintQInfo_valid_0 ? io_sinkC_bits_set : io_sinkB_bits_set;
+  assign io_sinkB_ready = io_sinkB_ready_0;
+  assign io_sinkC_ready = io_sinkC_ready_0;
+  assign io_mshrTask_ready = io_mshrTask_ready_0;
+  assign io_dirRead_s1_valid =
+    ~ds_mcp2_stall
+    & (chnl_task_s1_valid & ~mshr_task_s1_valid | s1_needs_replRead
+       & ~io_fromMainPipe_blockG_s1);
+  assign io_dirRead_s1_bits_tag = task_s1_bits_tag;
+  assign io_dirRead_s1_bits_set = task_s1_bits_set;
+  assign io_dirRead_s1_bits_wayMask =
+    ~({8{mshr_task_s1_valid & mshr_task_s1_bits_mshrRetry}}
+      & _io_dirRead_s1_bits_wayMask_T_1[7:0]);
+  assign io_dirRead_s1_bits_replacerInfo_channel = task_s1_bits_channel;
+  assign io_dirRead_s1_bits_replacerInfo_opcode = task_s1_bits_opcode[2:0];
+  assign io_dirRead_s1_bits_replacerInfo_reqSource = task_s1_bits_reqSource;
+  assign io_dirRead_s1_bits_replacerInfo_refill_prefetch =
+    s1_needs_replRead & _io_dirRead_s1_bits_replacerInfo_refill_prefetch_T
+    & mshr_task_s1_bits_dsWen;
+  assign io_dirRead_s1_bits_refill = s1_needs_replRead;
+  assign io_dirRead_s1_bits_mshrId = task_s1_bits_mshrId;
+  assign io_dirRead_s1_bits_cmoAll = io_sinkA_bits_cmoAll;
+  assign io_dirRead_s1_bits_cmoWay = io_sinkA_bits_way;
+  assign io_taskToPipe_s2_valid = task_s2_valid;
+  assign io_taskToPipe_s2_bits_channel = task_s2_bits_channel;
+  assign io_taskToPipe_s2_bits_txChannel = task_s2_bits_txChannel;
+  assign io_taskToPipe_s2_bits_set = task_s2_bits_set;
+  assign io_taskToPipe_s2_bits_tag = task_s2_bits_tag;
+  assign io_taskToPipe_s2_bits_off = task_s2_bits_off;
+  assign io_taskToPipe_s2_bits_alias = task_s2_bits_alias;
+  assign io_taskToPipe_s2_bits_vaddr = task_s2_bits_vaddr;
+  assign io_taskToPipe_s2_bits_isKeyword = task_s2_bits_isKeyword;
+  assign io_taskToPipe_s2_bits_opcode = task_s2_bits_opcode;
+  assign io_taskToPipe_s2_bits_param = task_s2_bits_param;
+  assign io_taskToPipe_s2_bits_size = task_s2_bits_size;
+  assign io_taskToPipe_s2_bits_sourceId = task_s2_bits_sourceId;
+  assign io_taskToPipe_s2_bits_bufIdx = task_s2_bits_bufIdx;
+  assign io_taskToPipe_s2_bits_needProbeAckData = task_s2_bits_needProbeAckData;
+  assign io_taskToPipe_s2_bits_denied = task_s2_bits_denied;
+  assign io_taskToPipe_s2_bits_corrupt = task_s2_bits_corrupt;
+  assign io_taskToPipe_s2_bits_mshrTask = task_s2_bits_mshrTask;
+  assign io_taskToPipe_s2_bits_mshrId = task_s2_bits_mshrId;
+  assign io_taskToPipe_s2_bits_aliasTask = task_s2_bits_aliasTask;
+  assign io_taskToPipe_s2_bits_useProbeData = task_s2_bits_useProbeData;
+  assign io_taskToPipe_s2_bits_mshrRetry = task_s2_bits_mshrRetry;
+  assign io_taskToPipe_s2_bits_readProbeDataDown = task_s2_bits_readProbeDataDown;
+  assign io_taskToPipe_s2_bits_fromL2pft = task_s2_bits_fromL2pft;
+  assign io_taskToPipe_s2_bits_needHint = task_s2_bits_needHint;
+  assign io_taskToPipe_s2_bits_dirty = task_s2_bits_dirty;
+  assign io_taskToPipe_s2_bits_way = task_s2_bits_way;
+  assign io_taskToPipe_s2_bits_meta_dirty = task_s2_bits_meta_dirty;
+  assign io_taskToPipe_s2_bits_meta_state = task_s2_bits_meta_state;
+  assign io_taskToPipe_s2_bits_meta_clients = task_s2_bits_meta_clients;
+  assign io_taskToPipe_s2_bits_meta_alias = task_s2_bits_meta_alias;
+  assign io_taskToPipe_s2_bits_meta_prefetch = task_s2_bits_meta_prefetch;
+  assign io_taskToPipe_s2_bits_meta_prefetchSrc = task_s2_bits_meta_prefetchSrc;
+  assign io_taskToPipe_s2_bits_meta_accessed = task_s2_bits_meta_accessed;
+  assign io_taskToPipe_s2_bits_meta_tagErr = task_s2_bits_meta_tagErr;
+  assign io_taskToPipe_s2_bits_meta_dataErr = task_s2_bits_meta_dataErr;
+  assign io_taskToPipe_s2_bits_metaWen = task_s2_bits_metaWen;
+  assign io_taskToPipe_s2_bits_tagWen = task_s2_bits_tagWen;
+  assign io_taskToPipe_s2_bits_dsWen = task_s2_bits_dsWen;
+  assign io_taskToPipe_s2_bits_wayMask = task_s2_bits_wayMask;
+  assign io_taskToPipe_s2_bits_replTask = task_s2_bits_replTask;
+  assign io_taskToPipe_s2_bits_cmoTask = task_s2_bits_cmoTask;
+  assign io_taskToPipe_s2_bits_cmoAll = task_s2_bits_cmoAll;
+  assign io_taskToPipe_s2_bits_reqSource = task_s2_bits_reqSource;
+  assign io_taskToPipe_s2_bits_mergeA = task_s2_bits_mergeA;
+  assign io_taskToPipe_s2_bits_aMergeTask_off = task_s2_bits_aMergeTask_off;
+  assign io_taskToPipe_s2_bits_aMergeTask_alias = task_s2_bits_aMergeTask_alias;
+  assign io_taskToPipe_s2_bits_aMergeTask_vaddr = task_s2_bits_aMergeTask_vaddr;
+  assign io_taskToPipe_s2_bits_aMergeTask_isKeyword = task_s2_bits_aMergeTask_isKeyword;
+  assign io_taskToPipe_s2_bits_aMergeTask_opcode = task_s2_bits_aMergeTask_opcode;
+  assign io_taskToPipe_s2_bits_aMergeTask_param = task_s2_bits_aMergeTask_param;
+  assign io_taskToPipe_s2_bits_aMergeTask_sourceId = task_s2_bits_aMergeTask_sourceId;
+  assign io_taskToPipe_s2_bits_aMergeTask_meta_dirty = task_s2_bits_aMergeTask_meta_dirty;
+  assign io_taskToPipe_s2_bits_aMergeTask_meta_state = task_s2_bits_aMergeTask_meta_state;
+  assign io_taskToPipe_s2_bits_aMergeTask_meta_clients =
+    task_s2_bits_aMergeTask_meta_clients;
+  assign io_taskToPipe_s2_bits_aMergeTask_meta_alias = task_s2_bits_aMergeTask_meta_alias;
+  assign io_taskToPipe_s2_bits_aMergeTask_meta_prefetch =
+    task_s2_bits_aMergeTask_meta_prefetch;
+  assign io_taskToPipe_s2_bits_aMergeTask_meta_prefetchSrc =
+    task_s2_bits_aMergeTask_meta_prefetchSrc;
+  assign io_taskToPipe_s2_bits_aMergeTask_meta_accessed =
+    task_s2_bits_aMergeTask_meta_accessed;
+  assign io_taskToPipe_s2_bits_aMergeTask_meta_tagErr =
+    task_s2_bits_aMergeTask_meta_tagErr;
+  assign io_taskToPipe_s2_bits_aMergeTask_meta_dataErr =
+    task_s2_bits_aMergeTask_meta_dataErr;
+  assign io_taskToPipe_s2_bits_snpHitRelease = task_s2_bits_snpHitRelease;
+  assign io_taskToPipe_s2_bits_snpHitReleaseToInval = task_s2_bits_snpHitReleaseToInval;
+  assign io_taskToPipe_s2_bits_snpHitReleaseToClean = task_s2_bits_snpHitReleaseToClean;
+  assign io_taskToPipe_s2_bits_snpHitReleaseWithData = task_s2_bits_snpHitReleaseWithData;
+  assign io_taskToPipe_s2_bits_snpHitReleaseIdx = task_s2_bits_snpHitReleaseIdx;
+  assign io_taskToPipe_s2_bits_snpHitReleaseMeta_dirty =
+    task_s2_bits_snpHitReleaseMeta_dirty;
+  assign io_taskToPipe_s2_bits_snpHitReleaseMeta_state =
+    task_s2_bits_snpHitReleaseMeta_state;
+  assign io_taskToPipe_s2_bits_snpHitReleaseMeta_clients =
+    task_s2_bits_snpHitReleaseMeta_clients;
+  assign io_taskToPipe_s2_bits_snpHitReleaseMeta_alias =
+    task_s2_bits_snpHitReleaseMeta_alias;
+  assign io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetch =
+    task_s2_bits_snpHitReleaseMeta_prefetch;
+  assign io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetchSrc =
+    task_s2_bits_snpHitReleaseMeta_prefetchSrc;
+  assign io_taskToPipe_s2_bits_snpHitReleaseMeta_accessed =
+    task_s2_bits_snpHitReleaseMeta_accessed;
+  assign io_taskToPipe_s2_bits_snpHitReleaseMeta_tagErr =
+    task_s2_bits_snpHitReleaseMeta_tagErr;
+  assign io_taskToPipe_s2_bits_snpHitReleaseMeta_dataErr =
+    task_s2_bits_snpHitReleaseMeta_dataErr;
+  assign io_taskToPipe_s2_bits_tgtID = task_s2_bits_tgtID;
+  assign io_taskToPipe_s2_bits_srcID = task_s2_bits_srcID;
+  assign io_taskToPipe_s2_bits_txnID = task_s2_bits_txnID;
+  assign io_taskToPipe_s2_bits_homeNID = task_s2_bits_homeNID;
+  assign io_taskToPipe_s2_bits_dbID = task_s2_bits_dbID;
+  assign io_taskToPipe_s2_bits_fwdNID = task_s2_bits_fwdNID;
+  assign io_taskToPipe_s2_bits_fwdTxnID = task_s2_bits_fwdTxnID;
+  assign io_taskToPipe_s2_bits_chiOpcode = task_s2_bits_chiOpcode;
+  assign io_taskToPipe_s2_bits_resp = task_s2_bits_resp;
+  assign io_taskToPipe_s2_bits_fwdState = task_s2_bits_fwdState;
+  assign io_taskToPipe_s2_bits_pCrdType = task_s2_bits_pCrdType;
+  assign io_taskToPipe_s2_bits_retToSrc = task_s2_bits_retToSrc;
+  assign io_taskToPipe_s2_bits_likelyshared = task_s2_bits_likelyshared;
+  assign io_taskToPipe_s2_bits_expCompAck = task_s2_bits_expCompAck;
+  assign io_taskToPipe_s2_bits_allowRetry = task_s2_bits_allowRetry;
+  assign io_taskToPipe_s2_bits_memAttr_allocate = task_s2_bits_memAttr_allocate;
+  assign io_taskToPipe_s2_bits_memAttr_cacheable = task_s2_bits_memAttr_cacheable;
+  assign io_taskToPipe_s2_bits_memAttr_device = task_s2_bits_memAttr_device;
+  assign io_taskToPipe_s2_bits_memAttr_ewa = task_s2_bits_memAttr_ewa;
+  assign io_taskToPipe_s2_bits_traceTag = task_s2_bits_traceTag;
+  assign io_mshrHintQInfo_valid =
+    mshr_task_s1_valid & ~mshr_replRead_stall & ~ds_mcp2_stall;
+  assign io_mshrHintQInfo_bits_channel = mshr_task_s1_bits_channel;
+  assign io_mshrHintQInfo_bits_txChannel = mshr_task_s1_bits_txChannel;
+  assign io_mshrHintQInfo_bits_set = mshr_task_s1_bits_set;
+  assign io_mshrHintQInfo_bits_tag = mshr_task_s1_bits_tag;
+  assign io_mshrHintQInfo_bits_off = mshr_task_s1_bits_off;
+  assign io_mshrHintQInfo_bits_alias = mshr_task_s1_bits_alias;
+  assign io_mshrHintQInfo_bits_vaddr = mshr_task_s1_bits_vaddr;
+  assign io_mshrHintQInfo_bits_isKeyword = mshr_task_s1_bits_isKeyword;
+  assign io_mshrHintQInfo_bits_opcode = mshr_task_s1_bits_opcode;
+  assign io_mshrHintQInfo_bits_param = mshr_task_s1_bits_param;
+  assign io_mshrHintQInfo_bits_size = mshr_task_s1_bits_size;
+  assign io_mshrHintQInfo_bits_sourceId = mshr_task_s1_bits_sourceId;
+  assign io_mshrHintQInfo_bits_bufIdx = mshr_task_s1_bits_bufIdx;
+  assign io_mshrHintQInfo_bits_needProbeAckData = mshr_task_s1_bits_needProbeAckData;
+  assign io_mshrHintQInfo_bits_denied = mshr_task_s1_bits_denied;
+  assign io_mshrHintQInfo_bits_corrupt = mshr_task_s1_bits_corrupt;
+  assign io_mshrHintQInfo_bits_mshrTask = mshr_task_s1_bits_mshrTask;
+  assign io_mshrHintQInfo_bits_mshrId = mshr_task_s1_bits_mshrId;
+  assign io_mshrHintQInfo_bits_aliasTask = mshr_task_s1_bits_aliasTask;
+  assign io_mshrHintQInfo_bits_useProbeData = mshr_task_s1_bits_useProbeData;
+  assign io_mshrHintQInfo_bits_mshrRetry = mshr_task_s1_bits_mshrRetry;
+  assign io_mshrHintQInfo_bits_readProbeDataDown = mshr_task_s1_bits_readProbeDataDown;
+  assign io_mshrHintQInfo_bits_fromL2pft = mshr_task_s1_bits_fromL2pft;
+  assign io_mshrHintQInfo_bits_needHint = mshr_task_s1_bits_needHint;
+  assign io_mshrHintQInfo_bits_dirty = mshr_task_s1_bits_dirty;
+  assign io_mshrHintQInfo_bits_way = mshr_task_s1_bits_way;
+  assign io_mshrHintQInfo_bits_meta_dirty = mshr_task_s1_bits_meta_dirty;
+  assign io_mshrHintQInfo_bits_meta_state = mshr_task_s1_bits_meta_state;
+  assign io_mshrHintQInfo_bits_meta_clients = mshr_task_s1_bits_meta_clients;
+  assign io_mshrHintQInfo_bits_meta_alias = mshr_task_s1_bits_meta_alias;
+  assign io_mshrHintQInfo_bits_meta_prefetch = mshr_task_s1_bits_meta_prefetch;
+  assign io_mshrHintQInfo_bits_meta_prefetchSrc = mshr_task_s1_bits_meta_prefetchSrc;
+  assign io_mshrHintQInfo_bits_meta_accessed = mshr_task_s1_bits_meta_accessed;
+  assign io_mshrHintQInfo_bits_meta_tagErr = mshr_task_s1_bits_meta_tagErr;
+  assign io_mshrHintQInfo_bits_meta_dataErr = mshr_task_s1_bits_meta_dataErr;
+  assign io_mshrHintQInfo_bits_metaWen = mshr_task_s1_bits_metaWen;
+  assign io_mshrHintQInfo_bits_tagWen = mshr_task_s1_bits_tagWen;
+  assign io_mshrHintQInfo_bits_dsWen = mshr_task_s1_bits_dsWen;
+  assign io_mshrHintQInfo_bits_wayMask = mshr_task_s1_bits_wayMask;
+  assign io_mshrHintQInfo_bits_replTask = mshr_task_s1_bits_replTask;
+  assign io_mshrHintQInfo_bits_cmoTask = mshr_task_s1_bits_cmoTask;
+  assign io_mshrHintQInfo_bits_cmoAll = mshr_task_s1_bits_cmoAll;
+  assign io_mshrHintQInfo_bits_reqSource = mshr_task_s1_bits_reqSource;
+  assign io_mshrHintQInfo_bits_mergeA = mshr_task_s1_bits_mergeA;
+  assign io_mshrHintQInfo_bits_aMergeTask_off = mshr_task_s1_bits_aMergeTask_off;
+  assign io_mshrHintQInfo_bits_aMergeTask_alias = mshr_task_s1_bits_aMergeTask_alias;
+  assign io_mshrHintQInfo_bits_aMergeTask_vaddr = mshr_task_s1_bits_aMergeTask_vaddr;
+  assign io_mshrHintQInfo_bits_aMergeTask_isKeyword =
+    mshr_task_s1_bits_aMergeTask_isKeyword;
+  assign io_mshrHintQInfo_bits_aMergeTask_opcode = mshr_task_s1_bits_aMergeTask_opcode;
+  assign io_mshrHintQInfo_bits_aMergeTask_param = mshr_task_s1_bits_aMergeTask_param;
+  assign io_mshrHintQInfo_bits_aMergeTask_sourceId =
+    mshr_task_s1_bits_aMergeTask_sourceId;
+  assign io_mshrHintQInfo_bits_aMergeTask_meta_dirty =
+    mshr_task_s1_bits_aMergeTask_meta_dirty;
+  assign io_mshrHintQInfo_bits_aMergeTask_meta_state =
+    mshr_task_s1_bits_aMergeTask_meta_state;
+  assign io_mshrHintQInfo_bits_aMergeTask_meta_clients =
+    mshr_task_s1_bits_aMergeTask_meta_clients;
+  assign io_mshrHintQInfo_bits_aMergeTask_meta_alias =
+    mshr_task_s1_bits_aMergeTask_meta_alias;
+  assign io_mshrHintQInfo_bits_aMergeTask_meta_prefetch =
+    mshr_task_s1_bits_aMergeTask_meta_prefetch;
+  assign io_mshrHintQInfo_bits_aMergeTask_meta_prefetchSrc =
+    mshr_task_s1_bits_aMergeTask_meta_prefetchSrc;
+  assign io_mshrHintQInfo_bits_aMergeTask_meta_accessed =
+    mshr_task_s1_bits_aMergeTask_meta_accessed;
+  assign io_mshrHintQInfo_bits_aMergeTask_meta_tagErr =
+    mshr_task_s1_bits_aMergeTask_meta_tagErr;
+  assign io_mshrHintQInfo_bits_aMergeTask_meta_dataErr =
+    mshr_task_s1_bits_aMergeTask_meta_dataErr;
+  assign io_mshrHintQInfo_bits_snpHitRelease = mshr_task_s1_bits_snpHitRelease;
+  assign io_mshrHintQInfo_bits_snpHitReleaseToInval =
+    mshr_task_s1_bits_snpHitReleaseToInval;
+  assign io_mshrHintQInfo_bits_snpHitReleaseToClean =
+    mshr_task_s1_bits_snpHitReleaseToClean;
+  assign io_mshrHintQInfo_bits_snpHitReleaseWithData =
+    mshr_task_s1_bits_snpHitReleaseWithData;
+  assign io_mshrHintQInfo_bits_snpHitReleaseIdx = mshr_task_s1_bits_snpHitReleaseIdx;
+  assign io_mshrHintQInfo_bits_snpHitReleaseMeta_dirty =
+    mshr_task_s1_bits_snpHitReleaseMeta_dirty;
+  assign io_mshrHintQInfo_bits_snpHitReleaseMeta_state =
+    mshr_task_s1_bits_snpHitReleaseMeta_state;
+  assign io_mshrHintQInfo_bits_snpHitReleaseMeta_clients =
+    mshr_task_s1_bits_snpHitReleaseMeta_clients;
+  assign io_mshrHintQInfo_bits_snpHitReleaseMeta_alias =
+    mshr_task_s1_bits_snpHitReleaseMeta_alias;
+  assign io_mshrHintQInfo_bits_snpHitReleaseMeta_prefetch =
+    mshr_task_s1_bits_snpHitReleaseMeta_prefetch;
+  assign io_mshrHintQInfo_bits_snpHitReleaseMeta_prefetchSrc =
+    mshr_task_s1_bits_snpHitReleaseMeta_prefetchSrc;
+  assign io_mshrHintQInfo_bits_snpHitReleaseMeta_accessed =
+    mshr_task_s1_bits_snpHitReleaseMeta_accessed;
+  assign io_mshrHintQInfo_bits_snpHitReleaseMeta_tagErr =
+    mshr_task_s1_bits_snpHitReleaseMeta_tagErr;
+  assign io_mshrHintQInfo_bits_snpHitReleaseMeta_dataErr =
+    mshr_task_s1_bits_snpHitReleaseMeta_dataErr;
+  assign io_mshrHintQInfo_bits_tgtID = mshr_task_s1_bits_tgtID;
+  assign io_mshrHintQInfo_bits_srcID = mshr_task_s1_bits_srcID;
+  assign io_mshrHintQInfo_bits_txnID = mshr_task_s1_bits_txnID;
+  assign io_mshrHintQInfo_bits_homeNID = mshr_task_s1_bits_homeNID;
+  assign io_mshrHintQInfo_bits_dbID = mshr_task_s1_bits_dbID;
+  assign io_mshrHintQInfo_bits_fwdNID = mshr_task_s1_bits_fwdNID;
+  assign io_mshrHintQInfo_bits_fwdTxnID = mshr_task_s1_bits_fwdTxnID;
+  assign io_mshrHintQInfo_bits_chiOpcode = mshr_task_s1_bits_chiOpcode;
+  assign io_mshrHintQInfo_bits_resp = mshr_task_s1_bits_resp;
+  assign io_mshrHintQInfo_bits_fwdState = mshr_task_s1_bits_fwdState;
+  assign io_mshrHintQInfo_bits_pCrdType = mshr_task_s1_bits_pCrdType;
+  assign io_mshrHintQInfo_bits_retToSrc = mshr_task_s1_bits_retToSrc;
+  assign io_mshrHintQInfo_bits_likelyshared = mshr_task_s1_bits_likelyshared;
+  assign io_mshrHintQInfo_bits_expCompAck = mshr_task_s1_bits_expCompAck;
+  assign io_mshrHintQInfo_bits_allowRetry = mshr_task_s1_bits_allowRetry;
+  assign io_mshrHintQInfo_bits_memAttr_allocate = mshr_task_s1_bits_memAttr_allocate;
+  assign io_mshrHintQInfo_bits_memAttr_cacheable = mshr_task_s1_bits_memAttr_cacheable;
+  assign io_mshrHintQInfo_bits_memAttr_device = mshr_task_s1_bits_memAttr_device;
+  assign io_mshrHintQInfo_bits_memAttr_ewa = mshr_task_s1_bits_memAttr_ewa;
+  assign io_mshrHintQInfo_bits_traceTag = mshr_task_s1_bits_traceTag;
+  assign io_sinkCHintQInfo_valid = io_sinkCHintQInfo_valid_0;
+  assign io_sinkCHintQInfo_bits_channel = io_sinkC_bits_channel;
+  assign io_sinkCHintQInfo_bits_txChannel = io_sinkC_bits_txChannel;
+  assign io_sinkCHintQInfo_bits_set = io_sinkC_bits_set;
+  assign io_sinkCHintQInfo_bits_tag = io_sinkC_bits_tag;
+  assign io_sinkCHintQInfo_bits_off = io_sinkC_bits_off;
+  assign io_sinkCHintQInfo_bits_alias = io_sinkC_bits_alias;
+  assign io_sinkCHintQInfo_bits_vaddr = io_sinkC_bits_vaddr;
+  assign io_sinkCHintQInfo_bits_isKeyword = io_sinkC_bits_isKeyword;
+  assign io_sinkCHintQInfo_bits_opcode = io_sinkC_bits_opcode;
+  assign io_sinkCHintQInfo_bits_param = io_sinkC_bits_param;
+  assign io_sinkCHintQInfo_bits_size = io_sinkC_bits_size;
+  assign io_sinkCHintQInfo_bits_sourceId = io_sinkC_bits_sourceId;
+  assign io_sinkCHintQInfo_bits_bufIdx = io_sinkC_bits_bufIdx;
+  assign io_sinkCHintQInfo_bits_needProbeAckData = io_sinkC_bits_needProbeAckData;
+  assign io_sinkCHintQInfo_bits_denied = io_sinkC_bits_denied;
+  assign io_sinkCHintQInfo_bits_corrupt = io_sinkC_bits_corrupt;
+  assign io_sinkCHintQInfo_bits_mshrTask = io_sinkC_bits_mshrTask;
+  assign io_sinkCHintQInfo_bits_mshrId = io_sinkC_bits_mshrId;
+  assign io_sinkCHintQInfo_bits_aliasTask = io_sinkC_bits_aliasTask;
+  assign io_sinkCHintQInfo_bits_useProbeData = io_sinkC_bits_useProbeData;
+  assign io_sinkCHintQInfo_bits_mshrRetry = io_sinkC_bits_mshrRetry;
+  assign io_sinkCHintQInfo_bits_readProbeDataDown = io_sinkC_bits_readProbeDataDown;
+  assign io_sinkCHintQInfo_bits_fromL2pft = io_sinkC_bits_fromL2pft;
+  assign io_sinkCHintQInfo_bits_needHint = io_sinkC_bits_needHint;
+  assign io_sinkCHintQInfo_bits_dirty = io_sinkC_bits_dirty;
+  assign io_sinkCHintQInfo_bits_way = io_sinkC_bits_way;
+  assign io_sinkCHintQInfo_bits_meta_dirty = io_sinkC_bits_meta_dirty;
+  assign io_sinkCHintQInfo_bits_meta_state = io_sinkC_bits_meta_state;
+  assign io_sinkCHintQInfo_bits_meta_clients = io_sinkC_bits_meta_clients;
+  assign io_sinkCHintQInfo_bits_meta_alias = io_sinkC_bits_meta_alias;
+  assign io_sinkCHintQInfo_bits_meta_prefetch = io_sinkC_bits_meta_prefetch;
+  assign io_sinkCHintQInfo_bits_meta_prefetchSrc = io_sinkC_bits_meta_prefetchSrc;
+  assign io_sinkCHintQInfo_bits_meta_accessed = io_sinkC_bits_meta_accessed;
+  assign io_sinkCHintQInfo_bits_meta_tagErr = io_sinkC_bits_meta_tagErr;
+  assign io_sinkCHintQInfo_bits_meta_dataErr = io_sinkC_bits_meta_dataErr;
+  assign io_sinkCHintQInfo_bits_metaWen = io_sinkC_bits_metaWen;
+  assign io_sinkCHintQInfo_bits_tagWen = io_sinkC_bits_tagWen;
+  assign io_sinkCHintQInfo_bits_dsWen = io_sinkC_bits_dsWen;
+  assign io_sinkCHintQInfo_bits_wayMask = io_sinkC_bits_wayMask;
+  assign io_sinkCHintQInfo_bits_replTask = io_sinkC_bits_replTask;
+  assign io_sinkCHintQInfo_bits_cmoTask = io_sinkC_bits_cmoTask;
+  assign io_sinkCHintQInfo_bits_cmoAll = io_sinkC_bits_cmoAll;
+  assign io_sinkCHintQInfo_bits_reqSource = io_sinkC_bits_reqSource;
+  assign io_sinkCHintQInfo_bits_mergeA = io_sinkC_bits_mergeA;
+  assign io_sinkCHintQInfo_bits_aMergeTask_off = io_sinkC_bits_aMergeTask_off;
+  assign io_sinkCHintQInfo_bits_aMergeTask_alias = io_sinkC_bits_aMergeTask_alias;
+  assign io_sinkCHintQInfo_bits_aMergeTask_vaddr = io_sinkC_bits_aMergeTask_vaddr;
+  assign io_sinkCHintQInfo_bits_aMergeTask_isKeyword = io_sinkC_bits_aMergeTask_isKeyword;
+  assign io_sinkCHintQInfo_bits_aMergeTask_opcode = io_sinkC_bits_aMergeTask_opcode;
+  assign io_sinkCHintQInfo_bits_aMergeTask_param = io_sinkC_bits_aMergeTask_param;
+  assign io_sinkCHintQInfo_bits_aMergeTask_sourceId = io_sinkC_bits_aMergeTask_sourceId;
+  assign io_sinkCHintQInfo_bits_aMergeTask_meta_dirty =
+    io_sinkC_bits_aMergeTask_meta_dirty;
+  assign io_sinkCHintQInfo_bits_aMergeTask_meta_state =
+    io_sinkC_bits_aMergeTask_meta_state;
+  assign io_sinkCHintQInfo_bits_aMergeTask_meta_clients =
+    io_sinkC_bits_aMergeTask_meta_clients;
+  assign io_sinkCHintQInfo_bits_aMergeTask_meta_alias =
+    io_sinkC_bits_aMergeTask_meta_alias;
+  assign io_sinkCHintQInfo_bits_aMergeTask_meta_prefetch =
+    io_sinkC_bits_aMergeTask_meta_prefetch;
+  assign io_sinkCHintQInfo_bits_aMergeTask_meta_prefetchSrc =
+    io_sinkC_bits_aMergeTask_meta_prefetchSrc;
+  assign io_sinkCHintQInfo_bits_aMergeTask_meta_accessed =
+    io_sinkC_bits_aMergeTask_meta_accessed;
+  assign io_sinkCHintQInfo_bits_aMergeTask_meta_tagErr =
+    io_sinkC_bits_aMergeTask_meta_tagErr;
+  assign io_sinkCHintQInfo_bits_aMergeTask_meta_dataErr =
+    io_sinkC_bits_aMergeTask_meta_dataErr;
+  assign io_sinkCHintQInfo_bits_snpHitRelease = io_sinkC_bits_snpHitRelease;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseToInval = io_sinkC_bits_snpHitReleaseToInval;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseToClean = io_sinkC_bits_snpHitReleaseToClean;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseWithData =
+    io_sinkC_bits_snpHitReleaseWithData;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseIdx = io_sinkC_bits_snpHitReleaseIdx;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseMeta_dirty =
+    io_sinkC_bits_snpHitReleaseMeta_dirty;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseMeta_state =
+    io_sinkC_bits_snpHitReleaseMeta_state;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseMeta_clients =
+    io_sinkC_bits_snpHitReleaseMeta_clients;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseMeta_alias =
+    io_sinkC_bits_snpHitReleaseMeta_alias;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseMeta_prefetch =
+    io_sinkC_bits_snpHitReleaseMeta_prefetch;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseMeta_prefetchSrc =
+    io_sinkC_bits_snpHitReleaseMeta_prefetchSrc;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseMeta_accessed =
+    io_sinkC_bits_snpHitReleaseMeta_accessed;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseMeta_tagErr =
+    io_sinkC_bits_snpHitReleaseMeta_tagErr;
+  assign io_sinkCHintQInfo_bits_snpHitReleaseMeta_dataErr =
+    io_sinkC_bits_snpHitReleaseMeta_dataErr;
+  assign io_sinkCHintQInfo_bits_tgtID = io_sinkC_bits_tgtID;
+  assign io_sinkCHintQInfo_bits_srcID = io_sinkC_bits_srcID;
+  assign io_sinkCHintQInfo_bits_txnID = io_sinkC_bits_txnID;
+  assign io_sinkCHintQInfo_bits_homeNID = io_sinkC_bits_homeNID;
+  assign io_sinkCHintQInfo_bits_dbID = io_sinkC_bits_dbID;
+  assign io_sinkCHintQInfo_bits_fwdNID = io_sinkC_bits_fwdNID;
+  assign io_sinkCHintQInfo_bits_fwdTxnID = io_sinkC_bits_fwdTxnID;
+  assign io_sinkCHintQInfo_bits_chiOpcode = io_sinkC_bits_chiOpcode;
+  assign io_sinkCHintQInfo_bits_resp = io_sinkC_bits_resp;
+  assign io_sinkCHintQInfo_bits_fwdState = io_sinkC_bits_fwdState;
+  assign io_sinkCHintQInfo_bits_pCrdType = io_sinkC_bits_pCrdType;
+  assign io_sinkCHintQInfo_bits_retToSrc = io_sinkC_bits_retToSrc;
+  assign io_sinkCHintQInfo_bits_likelyshared = io_sinkC_bits_likelyshared;
+  assign io_sinkCHintQInfo_bits_expCompAck = io_sinkC_bits_expCompAck;
+  assign io_sinkCHintQInfo_bits_allowRetry = io_sinkC_bits_allowRetry;
+  assign io_sinkCHintQInfo_bits_memAttr_allocate = io_sinkC_bits_memAttr_allocate;
+  assign io_sinkCHintQInfo_bits_memAttr_cacheable = io_sinkC_bits_memAttr_cacheable;
+  assign io_sinkCHintQInfo_bits_memAttr_device = io_sinkC_bits_memAttr_device;
+  assign io_sinkCHintQInfo_bits_memAttr_ewa = io_sinkC_bits_memAttr_ewa;
+  assign io_sinkCHintQInfo_bits_traceTag = io_sinkC_bits_traceTag;
+  assign io_refillBufRead_s2_valid =
+    mshrTask_s2
+    & (task_s2_bits_replTask & task_s2_bits_txChannel[0]
+       & (task_s2_bits_chiOpcode == 7'h1B | task_s2_bits_chiOpcode == 7'h15
+          | task_s2_bits_chiOpcode == 7'h42 | task_s2_bits_chiOpcode == 7'hD)
+       | mshrTask_s2_a_upwards & ~task_s2_bits_useProbeData);
+  assign io_refillBufRead_s2_bits_id = task_s2_bits_mshrId;
+  assign io_releaseBufRead_s2_valid =
+    task_s2_valid
+    & (mshrTask_s2
+         ? task_s2_bits_readProbeDataDown | mshrTask_s2_a_upwards
+           & task_s2_bits_useProbeData
+         : ~mshrTask_s2 & task_s2_bits_channel[1] & task_s2_bits_snpHitReleaseWithData);
+  assign io_releaseBufRead_s2_bits_id =
+    task_s2_bits_snpHitRelease ? task_s2_bits_snpHitReleaseIdx : task_s2_bits_mshrId;
+  assign io_status_s1_tags_0 = io_sinkC_bits_tag;
+  assign io_status_s1_tags_1 = io_sinkB_bits_tag;
+  assign io_status_s1_tags_2 = io_ATag;
+  assign io_status_s1_tags_3 = mshr_task_s1_bits_tag;
+  assign io_status_s1_sets_0 = io_sinkC_bits_set;
+  assign io_status_s1_sets_1 = io_sinkB_bits_set;
+  assign io_status_s1_sets_2 = io_ASet;
+  assign io_status_s1_sets_3 = mshr_task_s1_bits_set;
+  assign io_status_vec_0_valid = task_s1_valid;
+  assign io_status_vec_0_bits_channel = task_s1_bits_channel;
+  assign io_status_vec_1_valid = task_s2_valid;
+  assign io_status_vec_1_bits_channel = task_s2_bits_channel;
+  assign io_status_vec_toTX_0_valid = task_s1_valid;
+  assign io_status_vec_toTX_0_bits_channel = task_s1_bits_channel;
+  assign io_status_vec_toTX_0_bits_txChannel = task_s1_bits_txChannel;
+  assign io_status_vec_toTX_0_bits_mshrTask = task_s1_bits_mshrTask;
+  assign io_status_vec_toTX_1_valid = task_s2_valid;
+  assign io_status_vec_toTX_1_bits_channel = task_s2_bits_channel;
+  assign io_status_vec_toTX_1_bits_txChannel = task_s2_bits_txChannel;
+  assign io_status_vec_toTX_1_bits_mshrTask = task_s2_bits_mshrTask;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/RequestBuffer.sv b/flow/designs/src/xiangshan_coupledl2/deps/RequestBuffer.sv
new file mode 100644
index 0000000000..df60ce115f
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/RequestBuffer.sv
@@ -0,0 +1,3372 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module RequestBuffer(
+  input         clock,
+  input         reset,
+  output        io_in_ready,
+  input         io_in_valid,
+  input  [7:0]  io_in_bits_set,
+  input  [33:0] io_in_bits_tag,
+  input  [5:0]  io_in_bits_off,
+  input         io_in_bits_alias,
+  input  [43:0] io_in_bits_vaddr,
+  input         io_in_bits_isKeyword,
+  input  [3:0]  io_in_bits_opcode,
+  input  [2:0]  io_in_bits_param,
+  input  [2:0]  io_in_bits_size,
+  input  [6:0]  io_in_bits_sourceId,
+  input         io_in_bits_corrupt,
+  input         io_in_bits_fromL2pft,
+  input         io_in_bits_needHint,
+  input  [4:0]  io_in_bits_reqSource,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [2:0]  io_out_bits_channel,
+  output [2:0]  io_out_bits_txChannel,
+  output [7:0]  io_out_bits_set,
+  output [33:0] io_out_bits_tag,
+  output [5:0]  io_out_bits_off,
+  output        io_out_bits_alias,
+  output [43:0] io_out_bits_vaddr,
+  output        io_out_bits_isKeyword,
+  output [3:0]  io_out_bits_opcode,
+  output [2:0]  io_out_bits_param,
+  output [2:0]  io_out_bits_size,
+  output [6:0]  io_out_bits_sourceId,
+  output [1:0]  io_out_bits_bufIdx,
+  output        io_out_bits_needProbeAckData,
+  output        io_out_bits_denied,
+  output        io_out_bits_corrupt,
+  output        io_out_bits_mshrTask,
+  output [7:0]  io_out_bits_mshrId,
+  output        io_out_bits_aliasTask,
+  output        io_out_bits_useProbeData,
+  output        io_out_bits_mshrRetry,
+  output        io_out_bits_readProbeDataDown,
+  output        io_out_bits_fromL2pft,
+  output        io_out_bits_needHint,
+  output        io_out_bits_dirty,
+  output [2:0]  io_out_bits_way,
+  output        io_out_bits_meta_dirty,
+  output [1:0]  io_out_bits_meta_state,
+  output        io_out_bits_meta_clients,
+  output        io_out_bits_meta_alias,
+  output        io_out_bits_meta_prefetch,
+  output [3:0]  io_out_bits_meta_prefetchSrc,
+  output        io_out_bits_meta_accessed,
+  output        io_out_bits_meta_tagErr,
+  output        io_out_bits_meta_dataErr,
+  output        io_out_bits_metaWen,
+  output        io_out_bits_tagWen,
+  output        io_out_bits_dsWen,
+  output        io_out_bits_replTask,
+  output        io_out_bits_cmoTask,
+  output        io_out_bits_cmoAll,
+  output [4:0]  io_out_bits_reqSource,
+  output        io_out_bits_mergeA,
+  output [5:0]  io_out_bits_aMergeTask_off,
+  output        io_out_bits_aMergeTask_alias,
+  output [43:0] io_out_bits_aMergeTask_vaddr,
+  output        io_out_bits_aMergeTask_isKeyword,
+  output [2:0]  io_out_bits_aMergeTask_opcode,
+  output [2:0]  io_out_bits_aMergeTask_param,
+  output [6:0]  io_out_bits_aMergeTask_sourceId,
+  output        io_out_bits_aMergeTask_meta_dirty,
+  output [1:0]  io_out_bits_aMergeTask_meta_state,
+  output        io_out_bits_aMergeTask_meta_clients,
+  output        io_out_bits_aMergeTask_meta_alias,
+  output        io_out_bits_aMergeTask_meta_prefetch,
+  output [3:0]  io_out_bits_aMergeTask_meta_prefetchSrc,
+  output        io_out_bits_aMergeTask_meta_accessed,
+  output        io_out_bits_aMergeTask_meta_tagErr,
+  output        io_out_bits_aMergeTask_meta_dataErr,
+  output        io_out_bits_snpHitRelease,
+  output        io_out_bits_snpHitReleaseToInval,
+  output        io_out_bits_snpHitReleaseToClean,
+  output        io_out_bits_snpHitReleaseWithData,
+  output [7:0]  io_out_bits_snpHitReleaseIdx,
+  output        io_out_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_out_bits_snpHitReleaseMeta_state,
+  output        io_out_bits_snpHitReleaseMeta_clients,
+  output        io_out_bits_snpHitReleaseMeta_alias,
+  output        io_out_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_out_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_out_bits_snpHitReleaseMeta_accessed,
+  output        io_out_bits_snpHitReleaseMeta_tagErr,
+  output        io_out_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [10:0] io_out_bits_homeNID,
+  output [11:0] io_out_bits_dbID,
+  output [10:0] io_out_bits_fwdNID,
+  output [11:0] io_out_bits_fwdTxnID,
+  output [6:0]  io_out_bits_chiOpcode,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_retToSrc,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_expCompAck,
+  output        io_out_bits_allowRetry,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_device,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_traceTag,
+  input         io_mshrInfo_0_valid,
+  input  [2:0]  io_mshrInfo_0_bits_channel,
+  input  [7:0]  io_mshrInfo_0_bits_set,
+  input  [33:0] io_mshrInfo_0_bits_reqTag,
+  input         io_mshrInfo_0_bits_willFree,
+  input         io_mshrInfo_0_bits_needRelease,
+  input  [33:0] io_mshrInfo_0_bits_metaTag,
+  input         io_mshrInfo_0_bits_dirHit,
+  input         io_mshrInfo_0_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_0_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_0_bits_param,
+  input         io_mshrInfo_0_bits_mergeA,
+  input         io_mshrInfo_0_bits_w_grantlast,
+  input         io_mshrInfo_0_bits_w_grant,
+  input         io_mshrInfo_1_valid,
+  input  [2:0]  io_mshrInfo_1_bits_channel,
+  input  [7:0]  io_mshrInfo_1_bits_set,
+  input  [33:0] io_mshrInfo_1_bits_reqTag,
+  input         io_mshrInfo_1_bits_willFree,
+  input         io_mshrInfo_1_bits_needRelease,
+  input  [33:0] io_mshrInfo_1_bits_metaTag,
+  input         io_mshrInfo_1_bits_dirHit,
+  input         io_mshrInfo_1_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_1_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_1_bits_param,
+  input         io_mshrInfo_1_bits_mergeA,
+  input         io_mshrInfo_1_bits_w_grantlast,
+  input         io_mshrInfo_1_bits_w_grant,
+  input         io_mshrInfo_2_valid,
+  input  [2:0]  io_mshrInfo_2_bits_channel,
+  input  [7:0]  io_mshrInfo_2_bits_set,
+  input  [33:0] io_mshrInfo_2_bits_reqTag,
+  input         io_mshrInfo_2_bits_willFree,
+  input         io_mshrInfo_2_bits_needRelease,
+  input  [33:0] io_mshrInfo_2_bits_metaTag,
+  input         io_mshrInfo_2_bits_dirHit,
+  input         io_mshrInfo_2_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_2_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_2_bits_param,
+  input         io_mshrInfo_2_bits_mergeA,
+  input         io_mshrInfo_2_bits_w_grantlast,
+  input         io_mshrInfo_2_bits_w_grant,
+  input         io_mshrInfo_3_valid,
+  input  [2:0]  io_mshrInfo_3_bits_channel,
+  input  [7:0]  io_mshrInfo_3_bits_set,
+  input  [33:0] io_mshrInfo_3_bits_reqTag,
+  input         io_mshrInfo_3_bits_willFree,
+  input         io_mshrInfo_3_bits_needRelease,
+  input  [33:0] io_mshrInfo_3_bits_metaTag,
+  input         io_mshrInfo_3_bits_dirHit,
+  input         io_mshrInfo_3_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_3_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_3_bits_param,
+  input         io_mshrInfo_3_bits_mergeA,
+  input         io_mshrInfo_3_bits_w_grantlast,
+  input         io_mshrInfo_3_bits_w_grant,
+  input         io_mshrInfo_4_valid,
+  input  [2:0]  io_mshrInfo_4_bits_channel,
+  input  [7:0]  io_mshrInfo_4_bits_set,
+  input  [33:0] io_mshrInfo_4_bits_reqTag,
+  input         io_mshrInfo_4_bits_willFree,
+  input         io_mshrInfo_4_bits_needRelease,
+  input  [33:0] io_mshrInfo_4_bits_metaTag,
+  input         io_mshrInfo_4_bits_dirHit,
+  input         io_mshrInfo_4_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_4_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_4_bits_param,
+  input         io_mshrInfo_4_bits_mergeA,
+  input         io_mshrInfo_4_bits_w_grantlast,
+  input         io_mshrInfo_4_bits_w_grant,
+  input         io_mshrInfo_5_valid,
+  input  [2:0]  io_mshrInfo_5_bits_channel,
+  input  [7:0]  io_mshrInfo_5_bits_set,
+  input  [33:0] io_mshrInfo_5_bits_reqTag,
+  input         io_mshrInfo_5_bits_willFree,
+  input         io_mshrInfo_5_bits_needRelease,
+  input  [33:0] io_mshrInfo_5_bits_metaTag,
+  input         io_mshrInfo_5_bits_dirHit,
+  input         io_mshrInfo_5_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_5_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_5_bits_param,
+  input         io_mshrInfo_5_bits_mergeA,
+  input         io_mshrInfo_5_bits_w_grantlast,
+  input         io_mshrInfo_5_bits_w_grant,
+  input         io_mshrInfo_6_valid,
+  input  [2:0]  io_mshrInfo_6_bits_channel,
+  input  [7:0]  io_mshrInfo_6_bits_set,
+  input  [33:0] io_mshrInfo_6_bits_reqTag,
+  input         io_mshrInfo_6_bits_willFree,
+  input         io_mshrInfo_6_bits_needRelease,
+  input  [33:0] io_mshrInfo_6_bits_metaTag,
+  input         io_mshrInfo_6_bits_dirHit,
+  input         io_mshrInfo_6_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_6_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_6_bits_param,
+  input         io_mshrInfo_6_bits_mergeA,
+  input         io_mshrInfo_6_bits_w_grantlast,
+  input         io_mshrInfo_6_bits_w_grant,
+  input         io_mshrInfo_7_valid,
+  input  [2:0]  io_mshrInfo_7_bits_channel,
+  input  [7:0]  io_mshrInfo_7_bits_set,
+  input  [33:0] io_mshrInfo_7_bits_reqTag,
+  input         io_mshrInfo_7_bits_willFree,
+  input         io_mshrInfo_7_bits_needRelease,
+  input  [33:0] io_mshrInfo_7_bits_metaTag,
+  input         io_mshrInfo_7_bits_dirHit,
+  input         io_mshrInfo_7_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_7_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_7_bits_param,
+  input         io_mshrInfo_7_bits_mergeA,
+  input         io_mshrInfo_7_bits_w_grantlast,
+  input         io_mshrInfo_7_bits_w_grant,
+  input         io_mshrInfo_8_valid,
+  input  [2:0]  io_mshrInfo_8_bits_channel,
+  input  [7:0]  io_mshrInfo_8_bits_set,
+  input  [33:0] io_mshrInfo_8_bits_reqTag,
+  input         io_mshrInfo_8_bits_willFree,
+  input         io_mshrInfo_8_bits_needRelease,
+  input  [33:0] io_mshrInfo_8_bits_metaTag,
+  input         io_mshrInfo_8_bits_dirHit,
+  input         io_mshrInfo_8_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_8_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_8_bits_param,
+  input         io_mshrInfo_8_bits_mergeA,
+  input         io_mshrInfo_8_bits_w_grantlast,
+  input         io_mshrInfo_8_bits_w_grant,
+  input         io_mshrInfo_9_valid,
+  input  [2:0]  io_mshrInfo_9_bits_channel,
+  input  [7:0]  io_mshrInfo_9_bits_set,
+  input  [33:0] io_mshrInfo_9_bits_reqTag,
+  input         io_mshrInfo_9_bits_willFree,
+  input         io_mshrInfo_9_bits_needRelease,
+  input  [33:0] io_mshrInfo_9_bits_metaTag,
+  input         io_mshrInfo_9_bits_dirHit,
+  input         io_mshrInfo_9_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_9_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_9_bits_param,
+  input         io_mshrInfo_9_bits_mergeA,
+  input         io_mshrInfo_9_bits_w_grantlast,
+  input         io_mshrInfo_9_bits_w_grant,
+  input         io_mshrInfo_10_valid,
+  input  [2:0]  io_mshrInfo_10_bits_channel,
+  input  [7:0]  io_mshrInfo_10_bits_set,
+  input  [33:0] io_mshrInfo_10_bits_reqTag,
+  input         io_mshrInfo_10_bits_willFree,
+  input         io_mshrInfo_10_bits_needRelease,
+  input  [33:0] io_mshrInfo_10_bits_metaTag,
+  input         io_mshrInfo_10_bits_dirHit,
+  input         io_mshrInfo_10_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_10_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_10_bits_param,
+  input         io_mshrInfo_10_bits_mergeA,
+  input         io_mshrInfo_10_bits_w_grantlast,
+  input         io_mshrInfo_10_bits_w_grant,
+  input         io_mshrInfo_11_valid,
+  input  [2:0]  io_mshrInfo_11_bits_channel,
+  input  [7:0]  io_mshrInfo_11_bits_set,
+  input  [33:0] io_mshrInfo_11_bits_reqTag,
+  input         io_mshrInfo_11_bits_willFree,
+  input         io_mshrInfo_11_bits_needRelease,
+  input  [33:0] io_mshrInfo_11_bits_metaTag,
+  input         io_mshrInfo_11_bits_dirHit,
+  input         io_mshrInfo_11_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_11_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_11_bits_param,
+  input         io_mshrInfo_11_bits_mergeA,
+  input         io_mshrInfo_11_bits_w_grantlast,
+  input         io_mshrInfo_11_bits_w_grant,
+  input         io_mshrInfo_12_valid,
+  input  [2:0]  io_mshrInfo_12_bits_channel,
+  input  [7:0]  io_mshrInfo_12_bits_set,
+  input  [33:0] io_mshrInfo_12_bits_reqTag,
+  input         io_mshrInfo_12_bits_willFree,
+  input         io_mshrInfo_12_bits_needRelease,
+  input  [33:0] io_mshrInfo_12_bits_metaTag,
+  input         io_mshrInfo_12_bits_dirHit,
+  input         io_mshrInfo_12_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_12_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_12_bits_param,
+  input         io_mshrInfo_12_bits_mergeA,
+  input         io_mshrInfo_12_bits_w_grantlast,
+  input         io_mshrInfo_12_bits_w_grant,
+  input         io_mshrInfo_13_valid,
+  input  [2:0]  io_mshrInfo_13_bits_channel,
+  input  [7:0]  io_mshrInfo_13_bits_set,
+  input  [33:0] io_mshrInfo_13_bits_reqTag,
+  input         io_mshrInfo_13_bits_willFree,
+  input         io_mshrInfo_13_bits_needRelease,
+  input  [33:0] io_mshrInfo_13_bits_metaTag,
+  input         io_mshrInfo_13_bits_dirHit,
+  input         io_mshrInfo_13_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_13_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_13_bits_param,
+  input         io_mshrInfo_13_bits_mergeA,
+  input         io_mshrInfo_13_bits_w_grantlast,
+  input         io_mshrInfo_13_bits_w_grant,
+  input         io_mshrInfo_14_valid,
+  input  [2:0]  io_mshrInfo_14_bits_channel,
+  input  [7:0]  io_mshrInfo_14_bits_set,
+  input  [33:0] io_mshrInfo_14_bits_reqTag,
+  input         io_mshrInfo_14_bits_willFree,
+  input         io_mshrInfo_14_bits_needRelease,
+  input  [33:0] io_mshrInfo_14_bits_metaTag,
+  input         io_mshrInfo_14_bits_dirHit,
+  input         io_mshrInfo_14_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_14_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_14_bits_param,
+  input         io_mshrInfo_14_bits_mergeA,
+  input         io_mshrInfo_14_bits_w_grantlast,
+  input         io_mshrInfo_14_bits_w_grant,
+  input         io_mshrInfo_15_valid,
+  input  [2:0]  io_mshrInfo_15_bits_channel,
+  input  [7:0]  io_mshrInfo_15_bits_set,
+  input  [33:0] io_mshrInfo_15_bits_reqTag,
+  input         io_mshrInfo_15_bits_willFree,
+  input         io_mshrInfo_15_bits_needRelease,
+  input  [33:0] io_mshrInfo_15_bits_metaTag,
+  input         io_mshrInfo_15_bits_dirHit,
+  input         io_mshrInfo_15_bits_isAcqOrPrefetch,
+  input         io_mshrInfo_15_bits_isPrefetch,
+  input  [2:0]  io_mshrInfo_15_bits_param,
+  input         io_mshrInfo_15_bits_mergeA,
+  input         io_mshrInfo_15_bits_w_grantlast,
+  input         io_mshrInfo_15_bits_w_grant,
+  output        io_aMergeTask_valid,
+  output [15:0] io_aMergeTask_bits_idOH,
+  output [5:0]  io_aMergeTask_bits_task_off,
+  output        io_aMergeTask_bits_task_alias,
+  output [43:0] io_aMergeTask_bits_task_vaddr,
+  output        io_aMergeTask_bits_task_isKeyword,
+  output [3:0]  io_aMergeTask_bits_task_opcode,
+  output [2:0]  io_aMergeTask_bits_task_param,
+  output [6:0]  io_aMergeTask_bits_task_sourceId,
+  input         io_mainPipeBlock_0,
+  input         io_mainPipeBlock_1,
+  input         io_taskFromArb_s2_valid,
+  input  [2:0]  io_taskFromArb_s2_bits_channel,
+  input  [7:0]  io_taskFromArb_s2_bits_set,
+  input         io_taskFromArb_s2_bits_mshrTask,
+  output [33:0] io_ATag,
+  output [7:0]  io_ASet,
+  input         io_s1Entrance_valid,
+  input  [7:0]  io_s1Entrance_bits_set
+);
+
+  wire        _chosenQ_io_enq_ready;
+  wire        _chosenQ_io_deq_valid;
+  wire [2:0]  _chosenQ_io_deq_bits_bits_task_channel;
+  wire [2:0]  _chosenQ_io_deq_bits_bits_task_txChannel;
+  wire [7:0]  _chosenQ_io_deq_bits_bits_task_set;
+  wire [33:0] _chosenQ_io_deq_bits_bits_task_tag;
+  wire [5:0]  _chosenQ_io_deq_bits_bits_task_off;
+  wire        _chosenQ_io_deq_bits_bits_task_alias;
+  wire [43:0] _chosenQ_io_deq_bits_bits_task_vaddr;
+  wire        _chosenQ_io_deq_bits_bits_task_isKeyword;
+  wire [3:0]  _chosenQ_io_deq_bits_bits_task_opcode;
+  wire [2:0]  _chosenQ_io_deq_bits_bits_task_param;
+  wire [2:0]  _chosenQ_io_deq_bits_bits_task_size;
+  wire [6:0]  _chosenQ_io_deq_bits_bits_task_sourceId;
+  wire [1:0]  _chosenQ_io_deq_bits_bits_task_bufIdx;
+  wire        _chosenQ_io_deq_bits_bits_task_needProbeAckData;
+  wire        _chosenQ_io_deq_bits_bits_task_denied;
+  wire        _chosenQ_io_deq_bits_bits_task_corrupt;
+  wire        _chosenQ_io_deq_bits_bits_task_mshrTask;
+  wire [7:0]  _chosenQ_io_deq_bits_bits_task_mshrId;
+  wire        _chosenQ_io_deq_bits_bits_task_aliasTask;
+  wire        _chosenQ_io_deq_bits_bits_task_useProbeData;
+  wire        _chosenQ_io_deq_bits_bits_task_mshrRetry;
+  wire        _chosenQ_io_deq_bits_bits_task_readProbeDataDown;
+  wire        _chosenQ_io_deq_bits_bits_task_fromL2pft;
+  wire        _chosenQ_io_deq_bits_bits_task_needHint;
+  wire        _chosenQ_io_deq_bits_bits_task_dirty;
+  wire [2:0]  _chosenQ_io_deq_bits_bits_task_way;
+  wire        _chosenQ_io_deq_bits_bits_task_meta_dirty;
+  wire [1:0]  _chosenQ_io_deq_bits_bits_task_meta_state;
+  wire        _chosenQ_io_deq_bits_bits_task_meta_clients;
+  wire        _chosenQ_io_deq_bits_bits_task_meta_alias;
+  wire        _chosenQ_io_deq_bits_bits_task_meta_prefetch;
+  wire [3:0]  _chosenQ_io_deq_bits_bits_task_meta_prefetchSrc;
+  wire        _chosenQ_io_deq_bits_bits_task_meta_accessed;
+  wire        _chosenQ_io_deq_bits_bits_task_meta_tagErr;
+  wire        _chosenQ_io_deq_bits_bits_task_meta_dataErr;
+  wire        _chosenQ_io_deq_bits_bits_task_metaWen;
+  wire        _chosenQ_io_deq_bits_bits_task_tagWen;
+  wire        _chosenQ_io_deq_bits_bits_task_dsWen;
+  wire        _chosenQ_io_deq_bits_bits_task_replTask;
+  wire        _chosenQ_io_deq_bits_bits_task_cmoTask;
+  wire        _chosenQ_io_deq_bits_bits_task_cmoAll;
+  wire [4:0]  _chosenQ_io_deq_bits_bits_task_reqSource;
+  wire        _chosenQ_io_deq_bits_bits_task_mergeA;
+  wire [5:0]  _chosenQ_io_deq_bits_bits_task_aMergeTask_off;
+  wire        _chosenQ_io_deq_bits_bits_task_aMergeTask_alias;
+  wire [43:0] _chosenQ_io_deq_bits_bits_task_aMergeTask_vaddr;
+  wire        _chosenQ_io_deq_bits_bits_task_aMergeTask_isKeyword;
+  wire [2:0]  _chosenQ_io_deq_bits_bits_task_aMergeTask_opcode;
+  wire [2:0]  _chosenQ_io_deq_bits_bits_task_aMergeTask_param;
+  wire [6:0]  _chosenQ_io_deq_bits_bits_task_aMergeTask_sourceId;
+  wire        _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_dirty;
+  wire [1:0]  _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_state;
+  wire        _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_clients;
+  wire        _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_alias;
+  wire        _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_prefetch;
+  wire [3:0]  _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_prefetchSrc;
+  wire        _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_accessed;
+  wire        _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_tagErr;
+  wire        _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_dataErr;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitRelease;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseToInval;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseToClean;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseWithData;
+  wire [7:0]  _chosenQ_io_deq_bits_bits_task_snpHitReleaseIdx;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_dirty;
+  wire [1:0]  _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_state;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_clients;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_alias;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_prefetchSrc;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_accessed;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_tagErr;
+  wire        _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_dataErr;
+  wire [10:0] _chosenQ_io_deq_bits_bits_task_tgtID;
+  wire [10:0] _chosenQ_io_deq_bits_bits_task_srcID;
+  wire [11:0] _chosenQ_io_deq_bits_bits_task_txnID;
+  wire [10:0] _chosenQ_io_deq_bits_bits_task_homeNID;
+  wire [11:0] _chosenQ_io_deq_bits_bits_task_dbID;
+  wire [10:0] _chosenQ_io_deq_bits_bits_task_fwdNID;
+  wire [11:0] _chosenQ_io_deq_bits_bits_task_fwdTxnID;
+  wire [6:0]  _chosenQ_io_deq_bits_bits_task_chiOpcode;
+  wire [2:0]  _chosenQ_io_deq_bits_bits_task_resp;
+  wire [2:0]  _chosenQ_io_deq_bits_bits_task_fwdState;
+  wire [3:0]  _chosenQ_io_deq_bits_bits_task_pCrdType;
+  wire        _chosenQ_io_deq_bits_bits_task_retToSrc;
+  wire        _chosenQ_io_deq_bits_bits_task_likelyshared;
+  wire        _chosenQ_io_deq_bits_bits_task_expCompAck;
+  wire        _chosenQ_io_deq_bits_bits_task_allowRetry;
+  wire        _chosenQ_io_deq_bits_bits_task_memAttr_allocate;
+  wire        _chosenQ_io_deq_bits_bits_task_memAttr_cacheable;
+  wire        _chosenQ_io_deq_bits_bits_task_memAttr_device;
+  wire        _chosenQ_io_deq_bits_bits_task_memAttr_ewa;
+  wire        _chosenQ_io_deq_bits_bits_task_traceTag;
+  wire [3:0]  _chosenQ_io_deq_bits_idOH;
+  wire        _issueArb_io_out_valid;
+  wire        _issueArb_io_out_bits_valid;
+  wire        _issueArb_io_out_bits_rdy;
+  wire [2:0]  _issueArb_io_out_bits_task_channel;
+  wire [7:0]  _issueArb_io_out_bits_task_set;
+  wire [33:0] _issueArb_io_out_bits_task_tag;
+  wire [5:0]  _issueArb_io_out_bits_task_off;
+  wire        _issueArb_io_out_bits_task_alias;
+  wire [43:0] _issueArb_io_out_bits_task_vaddr;
+  wire        _issueArb_io_out_bits_task_isKeyword;
+  wire [3:0]  _issueArb_io_out_bits_task_opcode;
+  wire [2:0]  _issueArb_io_out_bits_task_param;
+  wire [2:0]  _issueArb_io_out_bits_task_size;
+  wire [6:0]  _issueArb_io_out_bits_task_sourceId;
+  wire        _issueArb_io_out_bits_task_corrupt;
+  wire        _issueArb_io_out_bits_task_fromL2pft;
+  wire        _issueArb_io_out_bits_task_needHint;
+  wire [4:0]  _issueArb_io_out_bits_task_reqSource;
+  wire [3:0]  _issueArb_io_out_bits_waitMP;
+  wire [15:0] _issueArb_io_out_bits_waitMS;
+  wire [3:0]  _issueArb_io_chosenOH;
+  reg         buffer_0_valid;
+  reg         buffer_0_rdy;
+  reg  [2:0]  buffer_0_task_channel;
+  reg  [7:0]  buffer_0_task_set;
+  reg  [33:0] buffer_0_task_tag;
+  reg  [5:0]  buffer_0_task_off;
+  reg         buffer_0_task_alias;
+  reg  [43:0] buffer_0_task_vaddr;
+  reg         buffer_0_task_isKeyword;
+  reg  [3:0]  buffer_0_task_opcode;
+  reg  [2:0]  buffer_0_task_param;
+  reg  [2:0]  buffer_0_task_size;
+  reg  [6:0]  buffer_0_task_sourceId;
+  reg         buffer_0_task_corrupt;
+  reg         buffer_0_task_fromL2pft;
+  reg         buffer_0_task_needHint;
+  reg  [4:0]  buffer_0_task_reqSource;
+  reg  [3:0]  buffer_0_waitMP;
+  reg  [15:0] buffer_0_waitMS;
+  reg         buffer_1_valid;
+  reg         buffer_1_rdy;
+  reg  [2:0]  buffer_1_task_channel;
+  reg  [7:0]  buffer_1_task_set;
+  reg  [33:0] buffer_1_task_tag;
+  reg  [5:0]  buffer_1_task_off;
+  reg         buffer_1_task_alias;
+  reg  [43:0] buffer_1_task_vaddr;
+  reg         buffer_1_task_isKeyword;
+  reg  [3:0]  buffer_1_task_opcode;
+  reg  [2:0]  buffer_1_task_param;
+  reg  [2:0]  buffer_1_task_size;
+  reg  [6:0]  buffer_1_task_sourceId;
+  reg         buffer_1_task_corrupt;
+  reg         buffer_1_task_fromL2pft;
+  reg         buffer_1_task_needHint;
+  reg  [4:0]  buffer_1_task_reqSource;
+  reg  [3:0]  buffer_1_waitMP;
+  reg  [15:0] buffer_1_waitMS;
+  reg         buffer_2_valid;
+  reg         buffer_2_rdy;
+  reg  [2:0]  buffer_2_task_channel;
+  reg  [7:0]  buffer_2_task_set;
+  reg  [33:0] buffer_2_task_tag;
+  reg  [5:0]  buffer_2_task_off;
+  reg         buffer_2_task_alias;
+  reg  [43:0] buffer_2_task_vaddr;
+  reg         buffer_2_task_isKeyword;
+  reg  [3:0]  buffer_2_task_opcode;
+  reg  [2:0]  buffer_2_task_param;
+  reg  [2:0]  buffer_2_task_size;
+  reg  [6:0]  buffer_2_task_sourceId;
+  reg         buffer_2_task_corrupt;
+  reg         buffer_2_task_fromL2pft;
+  reg         buffer_2_task_needHint;
+  reg  [4:0]  buffer_2_task_reqSource;
+  reg  [3:0]  buffer_2_waitMP;
+  reg  [15:0] buffer_2_waitMS;
+  reg         buffer_3_valid;
+  reg         buffer_3_rdy;
+  reg  [2:0]  buffer_3_task_channel;
+  reg  [7:0]  buffer_3_task_set;
+  reg  [33:0] buffer_3_task_tag;
+  reg  [5:0]  buffer_3_task_off;
+  reg         buffer_3_task_alias;
+  reg  [43:0] buffer_3_task_vaddr;
+  reg         buffer_3_task_isKeyword;
+  reg  [3:0]  buffer_3_task_opcode;
+  reg  [2:0]  buffer_3_task_param;
+  reg  [2:0]  buffer_3_task_size;
+  reg  [6:0]  buffer_3_task_sourceId;
+  reg         buffer_3_task_corrupt;
+  reg         buffer_3_task_fromL2pft;
+  reg         buffer_3_task_needHint;
+  reg  [4:0]  buffer_3_task_reqSource;
+  reg  [3:0]  buffer_3_waitMP;
+  reg  [15:0] buffer_3_waitMS;
+  wire [41:0] _io_hasMergeA_T_1 = {io_in_bits_tag, io_in_bits_set};
+  wire [41:0] _latePrefetchRes_matchVec_T_2 =
+    {io_mshrInfo_0_bits_reqTag, io_mshrInfo_0_bits_set};
+  wire        _latePrefetchRes_matchVec_T_204 = io_in_bits_opcode == 4'h6;
+  wire        _latePrefetchRes_matchVec_T_205 = io_in_bits_opcode == 4'h7;
+  wire        _mergeAMask_T_331 = io_in_bits_param == 3'h1;
+  wire        _mergeAMask_WIRE_0 =
+    io_mshrInfo_0_valid & io_mshrInfo_0_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_2 & ~io_mshrInfo_0_bits_dirHit
+    & ~(io_mshrInfo_0_bits_w_grantlast & io_mshrInfo_0_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_0_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_0_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_15 =
+    {io_mshrInfo_1_bits_reqTag, io_mshrInfo_1_bits_set};
+  wire        _mergeAMask_WIRE_1 =
+    io_mshrInfo_1_valid & io_mshrInfo_1_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_15 & ~io_mshrInfo_1_bits_dirHit
+    & ~(io_mshrInfo_1_bits_w_grantlast & io_mshrInfo_1_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_1_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_1_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_28 =
+    {io_mshrInfo_2_bits_reqTag, io_mshrInfo_2_bits_set};
+  wire        _mergeAMask_WIRE_2 =
+    io_mshrInfo_2_valid & io_mshrInfo_2_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_28 & ~io_mshrInfo_2_bits_dirHit
+    & ~(io_mshrInfo_2_bits_w_grantlast & io_mshrInfo_2_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_2_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_2_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_41 =
+    {io_mshrInfo_3_bits_reqTag, io_mshrInfo_3_bits_set};
+  wire        _mergeAMask_WIRE_3 =
+    io_mshrInfo_3_valid & io_mshrInfo_3_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_41 & ~io_mshrInfo_3_bits_dirHit
+    & ~(io_mshrInfo_3_bits_w_grantlast & io_mshrInfo_3_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_3_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_3_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_54 =
+    {io_mshrInfo_4_bits_reqTag, io_mshrInfo_4_bits_set};
+  wire        _mergeAMask_WIRE_4 =
+    io_mshrInfo_4_valid & io_mshrInfo_4_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_54 & ~io_mshrInfo_4_bits_dirHit
+    & ~(io_mshrInfo_4_bits_w_grantlast & io_mshrInfo_4_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_4_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_4_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_67 =
+    {io_mshrInfo_5_bits_reqTag, io_mshrInfo_5_bits_set};
+  wire        _mergeAMask_WIRE_5 =
+    io_mshrInfo_5_valid & io_mshrInfo_5_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_67 & ~io_mshrInfo_5_bits_dirHit
+    & ~(io_mshrInfo_5_bits_w_grantlast & io_mshrInfo_5_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_5_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_5_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_80 =
+    {io_mshrInfo_6_bits_reqTag, io_mshrInfo_6_bits_set};
+  wire        _mergeAMask_WIRE_6 =
+    io_mshrInfo_6_valid & io_mshrInfo_6_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_80 & ~io_mshrInfo_6_bits_dirHit
+    & ~(io_mshrInfo_6_bits_w_grantlast & io_mshrInfo_6_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_6_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_6_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_93 =
+    {io_mshrInfo_7_bits_reqTag, io_mshrInfo_7_bits_set};
+  wire        _mergeAMask_WIRE_7 =
+    io_mshrInfo_7_valid & io_mshrInfo_7_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_93 & ~io_mshrInfo_7_bits_dirHit
+    & ~(io_mshrInfo_7_bits_w_grantlast & io_mshrInfo_7_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_7_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_7_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_106 =
+    {io_mshrInfo_8_bits_reqTag, io_mshrInfo_8_bits_set};
+  wire        _mergeAMask_WIRE_8 =
+    io_mshrInfo_8_valid & io_mshrInfo_8_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_106 & ~io_mshrInfo_8_bits_dirHit
+    & ~(io_mshrInfo_8_bits_w_grantlast & io_mshrInfo_8_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_8_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_8_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_119 =
+    {io_mshrInfo_9_bits_reqTag, io_mshrInfo_9_bits_set};
+  wire        _mergeAMask_WIRE_9 =
+    io_mshrInfo_9_valid & io_mshrInfo_9_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_119 & ~io_mshrInfo_9_bits_dirHit
+    & ~(io_mshrInfo_9_bits_w_grantlast & io_mshrInfo_9_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_9_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_9_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_132 =
+    {io_mshrInfo_10_bits_reqTag, io_mshrInfo_10_bits_set};
+  wire        _mergeAMask_WIRE_10 =
+    io_mshrInfo_10_valid & io_mshrInfo_10_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_132 & ~io_mshrInfo_10_bits_dirHit
+    & ~(io_mshrInfo_10_bits_w_grantlast & io_mshrInfo_10_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_10_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_10_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_145 =
+    {io_mshrInfo_11_bits_reqTag, io_mshrInfo_11_bits_set};
+  wire        _mergeAMask_WIRE_11 =
+    io_mshrInfo_11_valid & io_mshrInfo_11_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_145 & ~io_mshrInfo_11_bits_dirHit
+    & ~(io_mshrInfo_11_bits_w_grantlast & io_mshrInfo_11_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_11_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_11_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_158 =
+    {io_mshrInfo_12_bits_reqTag, io_mshrInfo_12_bits_set};
+  wire        _mergeAMask_WIRE_12 =
+    io_mshrInfo_12_valid & io_mshrInfo_12_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_158 & ~io_mshrInfo_12_bits_dirHit
+    & ~(io_mshrInfo_12_bits_w_grantlast & io_mshrInfo_12_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_12_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_12_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_171 =
+    {io_mshrInfo_13_bits_reqTag, io_mshrInfo_13_bits_set};
+  wire        _mergeAMask_WIRE_13 =
+    io_mshrInfo_13_valid & io_mshrInfo_13_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_171 & ~io_mshrInfo_13_bits_dirHit
+    & ~(io_mshrInfo_13_bits_w_grantlast & io_mshrInfo_13_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_13_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_13_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_184 =
+    {io_mshrInfo_14_bits_reqTag, io_mshrInfo_14_bits_set};
+  wire        _mergeAMask_WIRE_14 =
+    io_mshrInfo_14_valid & io_mshrInfo_14_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_184 & ~io_mshrInfo_14_bits_dirHit
+    & ~(io_mshrInfo_14_bits_w_grantlast & io_mshrInfo_14_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_14_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_14_bits_param == 3'h0);
+  wire [41:0] _latePrefetchRes_matchVec_T_197 =
+    {io_mshrInfo_15_bits_reqTag, io_mshrInfo_15_bits_set};
+  wire        _mergeAMask_WIRE_15 =
+    io_mshrInfo_15_valid & io_mshrInfo_15_bits_isPrefetch
+    & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_197 & ~io_mshrInfo_15_bits_dirHit
+    & ~(io_mshrInfo_15_bits_w_grantlast & io_mshrInfo_15_bits_w_grant)
+    & (_latePrefetchRes_matchVec_T_204 | _latePrefetchRes_matchVec_T_205)
+    & ~io_mshrInfo_15_bits_mergeA
+    & ~(_mergeAMask_T_331 & io_mshrInfo_15_bits_param == 3'h0);
+  wire [15:0] mergeAMask =
+    {_mergeAMask_WIRE_15,
+     _mergeAMask_WIRE_14,
+     _mergeAMask_WIRE_13,
+     _mergeAMask_WIRE_12,
+     _mergeAMask_WIRE_11,
+     _mergeAMask_WIRE_10,
+     _mergeAMask_WIRE_9,
+     _mergeAMask_WIRE_8,
+     _mergeAMask_WIRE_7,
+     _mergeAMask_WIRE_6,
+     _mergeAMask_WIRE_5,
+     _mergeAMask_WIRE_4,
+     _mergeAMask_WIRE_3,
+     _mergeAMask_WIRE_2,
+     _mergeAMask_WIRE_1,
+     _mergeAMask_WIRE_0};
+  wire        _alloc_T =
+    {buffer_0_valid, buffer_1_valid, buffer_2_valid, buffer_3_valid} != 4'hF;
+  wire        _buffer_3_waitMS_T = io_in_bits_set == io_mshrInfo_0_bits_set;
+  wire        _buffer_3_waitMS_T_1 = io_in_bits_tag == io_mshrInfo_0_bits_reqTag;
+  wire        _buffer_3_waitMS_T_2 = io_in_bits_tag == io_mshrInfo_0_bits_metaTag;
+  wire        _buffer_3_waitMS_T_9 = io_in_bits_set == io_mshrInfo_1_bits_set;
+  wire        _buffer_3_waitMS_T_10 = io_in_bits_tag == io_mshrInfo_1_bits_reqTag;
+  wire        _buffer_3_waitMS_T_11 = io_in_bits_tag == io_mshrInfo_1_bits_metaTag;
+  wire        _buffer_3_waitMS_T_18 = io_in_bits_set == io_mshrInfo_2_bits_set;
+  wire        _buffer_3_waitMS_T_19 = io_in_bits_tag == io_mshrInfo_2_bits_reqTag;
+  wire        _buffer_3_waitMS_T_20 = io_in_bits_tag == io_mshrInfo_2_bits_metaTag;
+  wire        _buffer_3_waitMS_T_27 = io_in_bits_set == io_mshrInfo_3_bits_set;
+  wire        _buffer_3_waitMS_T_28 = io_in_bits_tag == io_mshrInfo_3_bits_reqTag;
+  wire        _buffer_3_waitMS_T_29 = io_in_bits_tag == io_mshrInfo_3_bits_metaTag;
+  wire        _buffer_3_waitMS_T_36 = io_in_bits_set == io_mshrInfo_4_bits_set;
+  wire        _buffer_3_waitMS_T_37 = io_in_bits_tag == io_mshrInfo_4_bits_reqTag;
+  wire        _buffer_3_waitMS_T_38 = io_in_bits_tag == io_mshrInfo_4_bits_metaTag;
+  wire        _buffer_3_waitMS_T_45 = io_in_bits_set == io_mshrInfo_5_bits_set;
+  wire        _buffer_3_waitMS_T_46 = io_in_bits_tag == io_mshrInfo_5_bits_reqTag;
+  wire        _buffer_3_waitMS_T_47 = io_in_bits_tag == io_mshrInfo_5_bits_metaTag;
+  wire        _buffer_3_waitMS_T_54 = io_in_bits_set == io_mshrInfo_6_bits_set;
+  wire        _buffer_3_waitMS_T_55 = io_in_bits_tag == io_mshrInfo_6_bits_reqTag;
+  wire        _buffer_3_waitMS_T_56 = io_in_bits_tag == io_mshrInfo_6_bits_metaTag;
+  wire        _buffer_3_waitMS_T_63 = io_in_bits_set == io_mshrInfo_7_bits_set;
+  wire        _buffer_3_waitMS_T_64 = io_in_bits_tag == io_mshrInfo_7_bits_reqTag;
+  wire        _buffer_3_waitMS_T_65 = io_in_bits_tag == io_mshrInfo_7_bits_metaTag;
+  wire        _buffer_3_waitMS_T_72 = io_in_bits_set == io_mshrInfo_8_bits_set;
+  wire        _buffer_3_waitMS_T_73 = io_in_bits_tag == io_mshrInfo_8_bits_reqTag;
+  wire        _buffer_3_waitMS_T_74 = io_in_bits_tag == io_mshrInfo_8_bits_metaTag;
+  wire        _buffer_3_waitMS_T_81 = io_in_bits_set == io_mshrInfo_9_bits_set;
+  wire        _buffer_3_waitMS_T_82 = io_in_bits_tag == io_mshrInfo_9_bits_reqTag;
+  wire        _buffer_3_waitMS_T_83 = io_in_bits_tag == io_mshrInfo_9_bits_metaTag;
+  wire        _buffer_3_waitMS_T_90 = io_in_bits_set == io_mshrInfo_10_bits_set;
+  wire        _buffer_3_waitMS_T_91 = io_in_bits_tag == io_mshrInfo_10_bits_reqTag;
+  wire        _buffer_3_waitMS_T_92 = io_in_bits_tag == io_mshrInfo_10_bits_metaTag;
+  wire        _buffer_3_waitMS_T_99 = io_in_bits_set == io_mshrInfo_11_bits_set;
+  wire        _buffer_3_waitMS_T_100 = io_in_bits_tag == io_mshrInfo_11_bits_reqTag;
+  wire        _buffer_3_waitMS_T_101 = io_in_bits_tag == io_mshrInfo_11_bits_metaTag;
+  wire        _buffer_3_waitMS_T_108 = io_in_bits_set == io_mshrInfo_12_bits_set;
+  wire        _buffer_3_waitMS_T_109 = io_in_bits_tag == io_mshrInfo_12_bits_reqTag;
+  wire        _buffer_3_waitMS_T_110 = io_in_bits_tag == io_mshrInfo_12_bits_metaTag;
+  wire        _buffer_3_waitMS_T_117 = io_in_bits_set == io_mshrInfo_13_bits_set;
+  wire        _buffer_3_waitMS_T_118 = io_in_bits_tag == io_mshrInfo_13_bits_reqTag;
+  wire        _buffer_3_waitMS_T_119 = io_in_bits_tag == io_mshrInfo_13_bits_metaTag;
+  wire        _buffer_3_waitMS_T_126 = io_in_bits_set == io_mshrInfo_14_bits_set;
+  wire        _buffer_3_waitMS_T_127 = io_in_bits_tag == io_mshrInfo_14_bits_reqTag;
+  wire        _buffer_3_waitMS_T_128 = io_in_bits_tag == io_mshrInfo_14_bits_metaTag;
+  wire        _buffer_3_waitMS_T_135 = io_in_bits_set == io_mshrInfo_15_bits_set;
+  wire        _buffer_3_waitMS_T_136 = io_in_bits_tag == io_mshrInfo_15_bits_reqTag;
+  wire        _buffer_3_waitMS_T_137 = io_in_bits_tag == io_mshrInfo_15_bits_metaTag;
+  wire [1:0]  _mpBlock_T_3 = {io_mainPipeBlock_0, io_mainPipeBlock_1};
+  wire        _buffer_3_rdy_sameSet_s2_T_4 = io_taskFromArb_s2_bits_set == io_in_bits_set;
+  reg         canFlow_sameSet_s3_REG;
+  reg  [7:0]  canFlow_sameSet_s3_r;
+  wire        canFlow =
+    _alloc_T
+    & {io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+         & (_buffer_3_waitMS_T_136 | _buffer_3_waitMS_T_137
+            & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+       io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+         & (_buffer_3_waitMS_T_127 | _buffer_3_waitMS_T_128
+            & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+       io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+         & (_buffer_3_waitMS_T_118 | _buffer_3_waitMS_T_119
+            & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+       io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+         & (_buffer_3_waitMS_T_109 | _buffer_3_waitMS_T_110
+            & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+       io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+         & (_buffer_3_waitMS_T_100 | _buffer_3_waitMS_T_101
+            & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+       io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+         & (_buffer_3_waitMS_T_91 | _buffer_3_waitMS_T_92
+            & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+       io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+         & (_buffer_3_waitMS_T_82 | _buffer_3_waitMS_T_83
+            & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+       io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+         & (_buffer_3_waitMS_T_73 | _buffer_3_waitMS_T_74
+            & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+       io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+         & (_buffer_3_waitMS_T_64 | _buffer_3_waitMS_T_65
+            & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+       io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+         & (_buffer_3_waitMS_T_55 | _buffer_3_waitMS_T_56
+            & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+       io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+         & (_buffer_3_waitMS_T_46 | _buffer_3_waitMS_T_47
+            & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+       io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+         & (_buffer_3_waitMS_T_37 | _buffer_3_waitMS_T_38
+            & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+       io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+         & (_buffer_3_waitMS_T_28 | _buffer_3_waitMS_T_29
+            & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+       io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+         & (_buffer_3_waitMS_T_19 | _buffer_3_waitMS_T_20
+            & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+       io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+         & (_buffer_3_waitMS_T_10 | _buffer_3_waitMS_T_11
+            & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+       io_mshrInfo_0_valid & _buffer_3_waitMS_T
+         & (_buffer_3_waitMS_T_1 | _buffer_3_waitMS_T_2 & io_mshrInfo_0_bits_needRelease)
+         & ~io_mshrInfo_0_bits_willFree} == 16'h0 & ~_chosenQ_io_deq_valid
+    & _mpBlock_T_3 == 2'h0
+    & 5'({1'h0,
+          4'({1'h0,
+              3'({1'h0,
+                  2'({1'h0,
+                      io_mshrInfo_0_valid & _buffer_3_waitMS_T
+                        & io_mshrInfo_0_bits_channel[0]}
+                     + {1'h0,
+                        io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+                          & io_mshrInfo_1_bits_channel[0]})}
+                 + {1'h0,
+                    2'({1'h0,
+                        io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+                          & io_mshrInfo_2_bits_channel[0]}
+                       + {1'h0,
+                          io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+                            & io_mshrInfo_3_bits_channel[0]})})}
+             + {1'h0,
+                3'({1'h0,
+                    2'({1'h0,
+                        io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+                          & io_mshrInfo_4_bits_channel[0]}
+                       + {1'h0,
+                          io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+                            & io_mshrInfo_5_bits_channel[0]})}
+                   + {1'h0,
+                      2'({1'h0,
+                          io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+                            & io_mshrInfo_6_bits_channel[0]}
+                         + 2'({1'h0,
+                               io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+                                 & io_mshrInfo_7_bits_channel[0]}
+                              + {1'h0,
+                                 io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+                                   & io_mshrInfo_8_bits_channel[0]}))})})}
+         + {1'h0,
+            4'({1'h0,
+                3'({1'h0,
+                    2'({1'h0,
+                        io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+                          & io_mshrInfo_9_bits_channel[0]}
+                       + {1'h0,
+                          io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+                            & io_mshrInfo_10_bits_channel[0]})}
+                   + {1'h0,
+                      2'({1'h0,
+                          io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+                            & io_mshrInfo_11_bits_channel[0]}
+                         + {1'h0,
+                            io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+                              & io_mshrInfo_12_bits_channel[0]})})}
+               + {1'h0,
+                  3'({1'h0,
+                      2'({1'h0,
+                          io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+                            & io_mshrInfo_13_bits_channel[0]}
+                         + {1'h0,
+                            io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+                              & io_mshrInfo_14_bits_channel[0]})}
+                     + {1'h0,
+                        2'({1'h0,
+                            io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+                              & io_mshrInfo_15_bits_channel[0]}
+                           + 2'({1'h0,
+                                 io_taskFromArb_s2_valid
+                                   & io_taskFromArb_s2_bits_channel[0]
+                                   & ~io_taskFromArb_s2_bits_mshrTask
+                                   & _buffer_3_rdy_sameSet_s2_T_4}
+                                + {1'h0,
+                                   canFlow_sameSet_s3_REG
+                                     & canFlow_sameSet_s3_r == io_in_bits_set}))})})}) < 5'h8;
+  wire        doFlow = canFlow & io_out_ready;
+  wire        dup =
+    io_in_bits_opcode == 4'h5
+    & (|{buffer_3_valid & _io_hasMergeA_T_1 == {buffer_3_task_tag, buffer_3_task_set},
+         buffer_2_valid & _io_hasMergeA_T_1 == {buffer_2_task_tag, buffer_2_task_set},
+         buffer_1_valid & _io_hasMergeA_T_1 == {buffer_1_task_tag, buffer_1_task_set},
+         buffer_0_valid & _io_hasMergeA_T_1 == {buffer_0_task_tag, buffer_0_task_set},
+         io_mshrInfo_15_valid & io_mshrInfo_15_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_197,
+         io_mshrInfo_14_valid & io_mshrInfo_14_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_184,
+         io_mshrInfo_13_valid & io_mshrInfo_13_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_171,
+         io_mshrInfo_12_valid & io_mshrInfo_12_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_158,
+         io_mshrInfo_11_valid & io_mshrInfo_11_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_145,
+         io_mshrInfo_10_valid & io_mshrInfo_10_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_132,
+         io_mshrInfo_9_valid & io_mshrInfo_9_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_119,
+         io_mshrInfo_8_valid & io_mshrInfo_8_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_106,
+         io_mshrInfo_7_valid & io_mshrInfo_7_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_93,
+         io_mshrInfo_6_valid & io_mshrInfo_6_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_80,
+         io_mshrInfo_5_valid & io_mshrInfo_5_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_67,
+         io_mshrInfo_4_valid & io_mshrInfo_4_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_54,
+         io_mshrInfo_3_valid & io_mshrInfo_3_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_41,
+         io_mshrInfo_2_valid & io_mshrInfo_2_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_28,
+         io_mshrInfo_1_valid & io_mshrInfo_1_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_15,
+         io_mshrInfo_0_valid & io_mshrInfo_0_bits_isAcqOrPrefetch
+           & _io_hasMergeA_T_1 == _latePrefetchRes_matchVec_T_2});
+  reg         buffer_0_rdy_sameSet_s3_REG;
+  reg  [7:0]  buffer_0_rdy_sameSet_s3_r;
+  reg         buffer_1_rdy_sameSet_s3_REG;
+  reg  [7:0]  buffer_1_rdy_sameSet_s3_r;
+  reg         buffer_2_rdy_sameSet_s3_REG;
+  reg  [7:0]  buffer_2_rdy_sameSet_s3_r;
+  reg         buffer_3_rdy_sameSet_s3_REG;
+  reg  [7:0]  buffer_3_rdy_sameSet_s3_r;
+  reg         buffer_0_rdy_sameSet_s3_REG_1;
+  reg  [7:0]  buffer_0_rdy_sameSet_s3_r_1;
+  reg         buffer_1_rdy_sameSet_s3_REG_1;
+  reg  [7:0]  buffer_1_rdy_sameSet_s3_r_1;
+  reg         buffer_2_rdy_sameSet_s3_REG_1;
+  reg  [7:0]  buffer_2_rdy_sameSet_s3_r_1;
+  reg         buffer_3_rdy_sameSet_s3_REG_1;
+  reg  [7:0]  buffer_3_rdy_sameSet_s3_r_1;
+  wire        _io_out_valid_T =
+    _chosenQ_io_deq_bits_idOH[0] & buffer_0_rdy | _chosenQ_io_deq_bits_idOH[1]
+    & buffer_1_rdy | _chosenQ_io_deq_bits_idOH[2] & buffer_2_rdy
+    | _chosenQ_io_deq_bits_idOH[3] & buffer_3_rdy;
+  wire        chosenQ_io_deq_ready = io_out_ready | ~_io_out_valid_T;
+  wire        io_out_valid_0 =
+    _chosenQ_io_deq_valid & _io_out_valid_T | io_in_valid & canFlow;
+  wire [7:0]  io_out_bits_set_0 =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_set : io_in_bits_set;
+  wire [15:0] waitMSUpdate =
+    ~(buffer_0_waitMP[1]) & buffer_0_waitMP[0]
+      ? {io_mshrInfo_15_valid & buffer_0_task_set == io_mshrInfo_15_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_15_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_15_bits_metaTag
+              & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+         io_mshrInfo_14_valid & buffer_0_task_set == io_mshrInfo_14_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_14_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_14_bits_metaTag
+              & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+         io_mshrInfo_13_valid & buffer_0_task_set == io_mshrInfo_13_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_13_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_13_bits_metaTag
+              & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+         io_mshrInfo_12_valid & buffer_0_task_set == io_mshrInfo_12_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_12_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_12_bits_metaTag
+              & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+         io_mshrInfo_11_valid & buffer_0_task_set == io_mshrInfo_11_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_11_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_11_bits_metaTag
+              & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+         io_mshrInfo_10_valid & buffer_0_task_set == io_mshrInfo_10_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_10_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_10_bits_metaTag
+              & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+         io_mshrInfo_9_valid & buffer_0_task_set == io_mshrInfo_9_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_9_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_9_bits_metaTag
+              & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+         io_mshrInfo_8_valid & buffer_0_task_set == io_mshrInfo_8_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_8_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_8_bits_metaTag
+              & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+         io_mshrInfo_7_valid & buffer_0_task_set == io_mshrInfo_7_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_7_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_7_bits_metaTag
+              & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+         io_mshrInfo_6_valid & buffer_0_task_set == io_mshrInfo_6_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_6_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_6_bits_metaTag
+              & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+         io_mshrInfo_5_valid & buffer_0_task_set == io_mshrInfo_5_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_5_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_5_bits_metaTag
+              & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+         io_mshrInfo_4_valid & buffer_0_task_set == io_mshrInfo_4_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_4_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_4_bits_metaTag
+              & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+         io_mshrInfo_3_valid & buffer_0_task_set == io_mshrInfo_3_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_3_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_3_bits_metaTag
+              & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+         io_mshrInfo_2_valid & buffer_0_task_set == io_mshrInfo_2_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_2_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_2_bits_metaTag
+              & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+         io_mshrInfo_1_valid & buffer_0_task_set == io_mshrInfo_1_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_1_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_1_bits_metaTag
+              & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+         io_mshrInfo_0_valid & buffer_0_task_set == io_mshrInfo_0_bits_set
+           & (buffer_0_task_tag == io_mshrInfo_0_bits_reqTag
+              | buffer_0_task_tag == io_mshrInfo_0_bits_metaTag
+              & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree}
+      : buffer_0_waitMS
+        & ~{io_mshrInfo_15_valid & io_mshrInfo_15_bits_willFree,
+            io_mshrInfo_14_valid & io_mshrInfo_14_bits_willFree,
+            io_mshrInfo_13_valid & io_mshrInfo_13_bits_willFree,
+            io_mshrInfo_12_valid & io_mshrInfo_12_bits_willFree,
+            io_mshrInfo_11_valid & io_mshrInfo_11_bits_willFree,
+            io_mshrInfo_10_valid & io_mshrInfo_10_bits_willFree,
+            io_mshrInfo_9_valid & io_mshrInfo_9_bits_willFree,
+            io_mshrInfo_8_valid & io_mshrInfo_8_bits_willFree,
+            io_mshrInfo_7_valid & io_mshrInfo_7_bits_willFree,
+            io_mshrInfo_6_valid & io_mshrInfo_6_bits_willFree,
+            io_mshrInfo_5_valid & io_mshrInfo_5_bits_willFree,
+            io_mshrInfo_4_valid & io_mshrInfo_4_bits_willFree,
+            io_mshrInfo_3_valid & io_mshrInfo_3_bits_willFree,
+            io_mshrInfo_2_valid & io_mshrInfo_2_bits_willFree,
+            io_mshrInfo_1_valid & io_mshrInfo_1_bits_willFree,
+            io_mshrInfo_0_valid & io_mshrInfo_0_bits_willFree};
+  wire        s1_Block =
+    io_out_ready & io_out_valid_0 & buffer_0_task_set == io_out_bits_set_0
+    | io_s1Entrance_valid & io_s1Entrance_bits_set == buffer_0_task_set;
+  wire        s1Block =
+    io_out_ready & io_out_valid_0 & io_in_bits_set == io_out_bits_set_0
+    | io_s1Entrance_valid & io_s1Entrance_bits_set == io_in_bits_set;
+  wire [15:0] waitMSUpdate_1 =
+    ~(buffer_1_waitMP[1]) & buffer_1_waitMP[0]
+      ? {io_mshrInfo_15_valid & buffer_1_task_set == io_mshrInfo_15_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_15_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_15_bits_metaTag
+              & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+         io_mshrInfo_14_valid & buffer_1_task_set == io_mshrInfo_14_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_14_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_14_bits_metaTag
+              & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+         io_mshrInfo_13_valid & buffer_1_task_set == io_mshrInfo_13_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_13_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_13_bits_metaTag
+              & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+         io_mshrInfo_12_valid & buffer_1_task_set == io_mshrInfo_12_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_12_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_12_bits_metaTag
+              & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+         io_mshrInfo_11_valid & buffer_1_task_set == io_mshrInfo_11_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_11_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_11_bits_metaTag
+              & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+         io_mshrInfo_10_valid & buffer_1_task_set == io_mshrInfo_10_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_10_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_10_bits_metaTag
+              & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+         io_mshrInfo_9_valid & buffer_1_task_set == io_mshrInfo_9_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_9_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_9_bits_metaTag
+              & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+         io_mshrInfo_8_valid & buffer_1_task_set == io_mshrInfo_8_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_8_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_8_bits_metaTag
+              & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+         io_mshrInfo_7_valid & buffer_1_task_set == io_mshrInfo_7_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_7_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_7_bits_metaTag
+              & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+         io_mshrInfo_6_valid & buffer_1_task_set == io_mshrInfo_6_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_6_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_6_bits_metaTag
+              & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+         io_mshrInfo_5_valid & buffer_1_task_set == io_mshrInfo_5_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_5_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_5_bits_metaTag
+              & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+         io_mshrInfo_4_valid & buffer_1_task_set == io_mshrInfo_4_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_4_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_4_bits_metaTag
+              & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+         io_mshrInfo_3_valid & buffer_1_task_set == io_mshrInfo_3_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_3_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_3_bits_metaTag
+              & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+         io_mshrInfo_2_valid & buffer_1_task_set == io_mshrInfo_2_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_2_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_2_bits_metaTag
+              & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+         io_mshrInfo_1_valid & buffer_1_task_set == io_mshrInfo_1_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_1_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_1_bits_metaTag
+              & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+         io_mshrInfo_0_valid & buffer_1_task_set == io_mshrInfo_0_bits_set
+           & (buffer_1_task_tag == io_mshrInfo_0_bits_reqTag
+              | buffer_1_task_tag == io_mshrInfo_0_bits_metaTag
+              & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree}
+      : buffer_1_waitMS
+        & ~{io_mshrInfo_15_valid & io_mshrInfo_15_bits_willFree,
+            io_mshrInfo_14_valid & io_mshrInfo_14_bits_willFree,
+            io_mshrInfo_13_valid & io_mshrInfo_13_bits_willFree,
+            io_mshrInfo_12_valid & io_mshrInfo_12_bits_willFree,
+            io_mshrInfo_11_valid & io_mshrInfo_11_bits_willFree,
+            io_mshrInfo_10_valid & io_mshrInfo_10_bits_willFree,
+            io_mshrInfo_9_valid & io_mshrInfo_9_bits_willFree,
+            io_mshrInfo_8_valid & io_mshrInfo_8_bits_willFree,
+            io_mshrInfo_7_valid & io_mshrInfo_7_bits_willFree,
+            io_mshrInfo_6_valid & io_mshrInfo_6_bits_willFree,
+            io_mshrInfo_5_valid & io_mshrInfo_5_bits_willFree,
+            io_mshrInfo_4_valid & io_mshrInfo_4_bits_willFree,
+            io_mshrInfo_3_valid & io_mshrInfo_3_bits_willFree,
+            io_mshrInfo_2_valid & io_mshrInfo_2_bits_willFree,
+            io_mshrInfo_1_valid & io_mshrInfo_1_bits_willFree,
+            io_mshrInfo_0_valid & io_mshrInfo_0_bits_willFree};
+  wire        s1_Block_1 =
+    io_out_ready & io_out_valid_0 & buffer_1_task_set == io_out_bits_set_0
+    | io_s1Entrance_valid & io_s1Entrance_bits_set == buffer_1_task_set;
+  wire        s1Block_1 =
+    io_out_ready & io_out_valid_0 & io_in_bits_set == io_out_bits_set_0
+    | io_s1Entrance_valid & io_s1Entrance_bits_set == io_in_bits_set;
+  wire [15:0] waitMSUpdate_2 =
+    ~(buffer_2_waitMP[1]) & buffer_2_waitMP[0]
+      ? {io_mshrInfo_15_valid & buffer_2_task_set == io_mshrInfo_15_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_15_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_15_bits_metaTag
+              & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+         io_mshrInfo_14_valid & buffer_2_task_set == io_mshrInfo_14_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_14_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_14_bits_metaTag
+              & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+         io_mshrInfo_13_valid & buffer_2_task_set == io_mshrInfo_13_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_13_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_13_bits_metaTag
+              & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+         io_mshrInfo_12_valid & buffer_2_task_set == io_mshrInfo_12_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_12_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_12_bits_metaTag
+              & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+         io_mshrInfo_11_valid & buffer_2_task_set == io_mshrInfo_11_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_11_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_11_bits_metaTag
+              & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+         io_mshrInfo_10_valid & buffer_2_task_set == io_mshrInfo_10_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_10_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_10_bits_metaTag
+              & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+         io_mshrInfo_9_valid & buffer_2_task_set == io_mshrInfo_9_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_9_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_9_bits_metaTag
+              & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+         io_mshrInfo_8_valid & buffer_2_task_set == io_mshrInfo_8_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_8_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_8_bits_metaTag
+              & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+         io_mshrInfo_7_valid & buffer_2_task_set == io_mshrInfo_7_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_7_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_7_bits_metaTag
+              & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+         io_mshrInfo_6_valid & buffer_2_task_set == io_mshrInfo_6_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_6_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_6_bits_metaTag
+              & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+         io_mshrInfo_5_valid & buffer_2_task_set == io_mshrInfo_5_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_5_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_5_bits_metaTag
+              & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+         io_mshrInfo_4_valid & buffer_2_task_set == io_mshrInfo_4_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_4_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_4_bits_metaTag
+              & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+         io_mshrInfo_3_valid & buffer_2_task_set == io_mshrInfo_3_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_3_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_3_bits_metaTag
+              & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+         io_mshrInfo_2_valid & buffer_2_task_set == io_mshrInfo_2_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_2_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_2_bits_metaTag
+              & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+         io_mshrInfo_1_valid & buffer_2_task_set == io_mshrInfo_1_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_1_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_1_bits_metaTag
+              & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+         io_mshrInfo_0_valid & buffer_2_task_set == io_mshrInfo_0_bits_set
+           & (buffer_2_task_tag == io_mshrInfo_0_bits_reqTag
+              | buffer_2_task_tag == io_mshrInfo_0_bits_metaTag
+              & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree}
+      : buffer_2_waitMS
+        & ~{io_mshrInfo_15_valid & io_mshrInfo_15_bits_willFree,
+            io_mshrInfo_14_valid & io_mshrInfo_14_bits_willFree,
+            io_mshrInfo_13_valid & io_mshrInfo_13_bits_willFree,
+            io_mshrInfo_12_valid & io_mshrInfo_12_bits_willFree,
+            io_mshrInfo_11_valid & io_mshrInfo_11_bits_willFree,
+            io_mshrInfo_10_valid & io_mshrInfo_10_bits_willFree,
+            io_mshrInfo_9_valid & io_mshrInfo_9_bits_willFree,
+            io_mshrInfo_8_valid & io_mshrInfo_8_bits_willFree,
+            io_mshrInfo_7_valid & io_mshrInfo_7_bits_willFree,
+            io_mshrInfo_6_valid & io_mshrInfo_6_bits_willFree,
+            io_mshrInfo_5_valid & io_mshrInfo_5_bits_willFree,
+            io_mshrInfo_4_valid & io_mshrInfo_4_bits_willFree,
+            io_mshrInfo_3_valid & io_mshrInfo_3_bits_willFree,
+            io_mshrInfo_2_valid & io_mshrInfo_2_bits_willFree,
+            io_mshrInfo_1_valid & io_mshrInfo_1_bits_willFree,
+            io_mshrInfo_0_valid & io_mshrInfo_0_bits_willFree};
+  wire        s1_Block_2 =
+    io_out_ready & io_out_valid_0 & buffer_2_task_set == io_out_bits_set_0
+    | io_s1Entrance_valid & io_s1Entrance_bits_set == buffer_2_task_set;
+  wire        s1Block_2 =
+    io_out_ready & io_out_valid_0 & io_in_bits_set == io_out_bits_set_0
+    | io_s1Entrance_valid & io_s1Entrance_bits_set == io_in_bits_set;
+  wire [15:0] waitMSUpdate_3 =
+    ~(buffer_3_waitMP[1]) & buffer_3_waitMP[0]
+      ? {io_mshrInfo_15_valid & buffer_3_task_set == io_mshrInfo_15_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_15_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_15_bits_metaTag
+              & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+         io_mshrInfo_14_valid & buffer_3_task_set == io_mshrInfo_14_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_14_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_14_bits_metaTag
+              & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+         io_mshrInfo_13_valid & buffer_3_task_set == io_mshrInfo_13_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_13_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_13_bits_metaTag
+              & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+         io_mshrInfo_12_valid & buffer_3_task_set == io_mshrInfo_12_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_12_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_12_bits_metaTag
+              & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+         io_mshrInfo_11_valid & buffer_3_task_set == io_mshrInfo_11_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_11_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_11_bits_metaTag
+              & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+         io_mshrInfo_10_valid & buffer_3_task_set == io_mshrInfo_10_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_10_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_10_bits_metaTag
+              & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+         io_mshrInfo_9_valid & buffer_3_task_set == io_mshrInfo_9_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_9_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_9_bits_metaTag
+              & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+         io_mshrInfo_8_valid & buffer_3_task_set == io_mshrInfo_8_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_8_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_8_bits_metaTag
+              & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+         io_mshrInfo_7_valid & buffer_3_task_set == io_mshrInfo_7_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_7_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_7_bits_metaTag
+              & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+         io_mshrInfo_6_valid & buffer_3_task_set == io_mshrInfo_6_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_6_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_6_bits_metaTag
+              & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+         io_mshrInfo_5_valid & buffer_3_task_set == io_mshrInfo_5_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_5_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_5_bits_metaTag
+              & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+         io_mshrInfo_4_valid & buffer_3_task_set == io_mshrInfo_4_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_4_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_4_bits_metaTag
+              & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+         io_mshrInfo_3_valid & buffer_3_task_set == io_mshrInfo_3_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_3_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_3_bits_metaTag
+              & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+         io_mshrInfo_2_valid & buffer_3_task_set == io_mshrInfo_2_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_2_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_2_bits_metaTag
+              & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+         io_mshrInfo_1_valid & buffer_3_task_set == io_mshrInfo_1_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_1_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_1_bits_metaTag
+              & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+         io_mshrInfo_0_valid & buffer_3_task_set == io_mshrInfo_0_bits_set
+           & (buffer_3_task_tag == io_mshrInfo_0_bits_reqTag
+              | buffer_3_task_tag == io_mshrInfo_0_bits_metaTag
+              & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree}
+      : buffer_3_waitMS
+        & ~{io_mshrInfo_15_valid & io_mshrInfo_15_bits_willFree,
+            io_mshrInfo_14_valid & io_mshrInfo_14_bits_willFree,
+            io_mshrInfo_13_valid & io_mshrInfo_13_bits_willFree,
+            io_mshrInfo_12_valid & io_mshrInfo_12_bits_willFree,
+            io_mshrInfo_11_valid & io_mshrInfo_11_bits_willFree,
+            io_mshrInfo_10_valid & io_mshrInfo_10_bits_willFree,
+            io_mshrInfo_9_valid & io_mshrInfo_9_bits_willFree,
+            io_mshrInfo_8_valid & io_mshrInfo_8_bits_willFree,
+            io_mshrInfo_7_valid & io_mshrInfo_7_bits_willFree,
+            io_mshrInfo_6_valid & io_mshrInfo_6_bits_willFree,
+            io_mshrInfo_5_valid & io_mshrInfo_5_bits_willFree,
+            io_mshrInfo_4_valid & io_mshrInfo_4_bits_willFree,
+            io_mshrInfo_3_valid & io_mshrInfo_3_bits_willFree,
+            io_mshrInfo_2_valid & io_mshrInfo_2_bits_willFree,
+            io_mshrInfo_1_valid & io_mshrInfo_1_bits_willFree,
+            io_mshrInfo_0_valid & io_mshrInfo_0_bits_willFree};
+  wire        s1_Block_3 =
+    io_out_ready & io_out_valid_0 & buffer_3_task_set == io_out_bits_set_0
+    | io_s1Entrance_valid & io_s1Entrance_bits_set == buffer_3_task_set;
+  wire        s1Block_3 =
+    io_out_ready & io_out_valid_0 & io_in_bits_set == io_out_bits_set_0
+    | io_s1Entrance_valid & io_s1Entrance_bits_set == io_in_bits_set;
+  wire        alloc = _alloc_T & io_in_valid & ~doFlow & ~dup & ~(|mergeAMask);
+  wire        _GEN = alloc & ~buffer_0_valid;
+  wire        _GEN_0 = alloc & ~buffer_1_valid & buffer_0_valid;
+  wire        _GEN_1 =
+    alloc & ~buffer_2_valid & {~buffer_0_valid, ~buffer_1_valid} == 2'h0;
+  wire        _GEN_2 =
+    alloc & ~buffer_3_valid & {~buffer_0_valid, ~buffer_1_valid, ~buffer_2_valid} == 3'h0;
+  wire        _GEN_3 = chosenQ_io_deq_ready & _chosenQ_io_deq_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      buffer_0_valid <= 1'h0;
+      buffer_0_rdy <= 1'h0;
+      buffer_0_task_channel <= 3'h0;
+      buffer_0_task_set <= 8'h0;
+      buffer_0_task_tag <= 34'h0;
+      buffer_0_task_off <= 6'h0;
+      buffer_0_task_alias <= 1'h0;
+      buffer_0_task_vaddr <= 44'h0;
+      buffer_0_task_isKeyword <= 1'h0;
+      buffer_0_task_opcode <= 4'h0;
+      buffer_0_task_param <= 3'h0;
+      buffer_0_task_size <= 3'h0;
+      buffer_0_task_sourceId <= 7'h0;
+      buffer_0_task_corrupt <= 1'h0;
+      buffer_0_task_fromL2pft <= 1'h0;
+      buffer_0_task_needHint <= 1'h0;
+      buffer_0_task_reqSource <= 5'h0;
+      buffer_0_waitMP <= 4'h0;
+      buffer_0_waitMS <= 16'h0;
+      buffer_1_valid <= 1'h0;
+      buffer_1_rdy <= 1'h0;
+      buffer_1_task_channel <= 3'h0;
+      buffer_1_task_set <= 8'h0;
+      buffer_1_task_tag <= 34'h0;
+      buffer_1_task_off <= 6'h0;
+      buffer_1_task_alias <= 1'h0;
+      buffer_1_task_vaddr <= 44'h0;
+      buffer_1_task_isKeyword <= 1'h0;
+      buffer_1_task_opcode <= 4'h0;
+      buffer_1_task_param <= 3'h0;
+      buffer_1_task_size <= 3'h0;
+      buffer_1_task_sourceId <= 7'h0;
+      buffer_1_task_corrupt <= 1'h0;
+      buffer_1_task_fromL2pft <= 1'h0;
+      buffer_1_task_needHint <= 1'h0;
+      buffer_1_task_reqSource <= 5'h0;
+      buffer_1_waitMP <= 4'h0;
+      buffer_1_waitMS <= 16'h0;
+      buffer_2_valid <= 1'h0;
+      buffer_2_rdy <= 1'h0;
+      buffer_2_task_channel <= 3'h0;
+      buffer_2_task_set <= 8'h0;
+      buffer_2_task_tag <= 34'h0;
+      buffer_2_task_off <= 6'h0;
+      buffer_2_task_alias <= 1'h0;
+      buffer_2_task_vaddr <= 44'h0;
+      buffer_2_task_isKeyword <= 1'h0;
+      buffer_2_task_opcode <= 4'h0;
+      buffer_2_task_param <= 3'h0;
+      buffer_2_task_size <= 3'h0;
+      buffer_2_task_sourceId <= 7'h0;
+      buffer_2_task_corrupt <= 1'h0;
+      buffer_2_task_fromL2pft <= 1'h0;
+      buffer_2_task_needHint <= 1'h0;
+      buffer_2_task_reqSource <= 5'h0;
+      buffer_2_waitMP <= 4'h0;
+      buffer_2_waitMS <= 16'h0;
+      buffer_3_valid <= 1'h0;
+      buffer_3_rdy <= 1'h0;
+      buffer_3_task_channel <= 3'h0;
+      buffer_3_task_set <= 8'h0;
+      buffer_3_task_tag <= 34'h0;
+      buffer_3_task_off <= 6'h0;
+      buffer_3_task_alias <= 1'h0;
+      buffer_3_task_vaddr <= 44'h0;
+      buffer_3_task_isKeyword <= 1'h0;
+      buffer_3_task_opcode <= 4'h0;
+      buffer_3_task_param <= 3'h0;
+      buffer_3_task_size <= 3'h0;
+      buffer_3_task_sourceId <= 7'h0;
+      buffer_3_task_corrupt <= 1'h0;
+      buffer_3_task_fromL2pft <= 1'h0;
+      buffer_3_task_needHint <= 1'h0;
+      buffer_3_task_reqSource <= 5'h0;
+      buffer_3_waitMP <= 4'h0;
+      buffer_3_waitMS <= 16'h0;
+    end
+    else begin
+      buffer_0_valid <=
+        ~(_GEN_3 & _chosenQ_io_deq_bits_idOH[0] & _io_out_valid_T)
+        & (_GEN | buffer_0_valid);
+      if (buffer_0_valid) begin
+        buffer_0_rdy <=
+          waitMSUpdate == 16'h0 & buffer_0_waitMP == 4'h0 & ~s1_Block
+          & 5'({1'h0,
+                4'({1'h0,
+                    3'({1'h0,
+                        2'({1'h0,
+                            io_mshrInfo_0_valid
+                              & io_mshrInfo_0_bits_set == buffer_0_task_set
+                              & io_mshrInfo_0_bits_channel[0]}
+                           + {1'h0,
+                              io_mshrInfo_1_valid
+                                & io_mshrInfo_1_bits_set == buffer_0_task_set
+                                & io_mshrInfo_1_bits_channel[0]})}
+                       + {1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_2_valid
+                                & io_mshrInfo_2_bits_set == buffer_0_task_set
+                                & io_mshrInfo_2_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_3_valid
+                                  & io_mshrInfo_3_bits_set == buffer_0_task_set
+                                  & io_mshrInfo_3_bits_channel[0]})})}
+                   + {1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_4_valid
+                                & io_mshrInfo_4_bits_set == buffer_0_task_set
+                                & io_mshrInfo_4_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_5_valid
+                                  & io_mshrInfo_5_bits_set == buffer_0_task_set
+                                  & io_mshrInfo_5_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_6_valid
+                                  & io_mshrInfo_6_bits_set == buffer_0_task_set
+                                  & io_mshrInfo_6_bits_channel[0]}
+                               + 2'({1'h0,
+                                     io_mshrInfo_7_valid
+                                       & io_mshrInfo_7_bits_set == buffer_0_task_set
+                                       & io_mshrInfo_7_bits_channel[0]}
+                                    + {1'h0,
+                                       io_mshrInfo_8_valid
+                                         & io_mshrInfo_8_bits_set == buffer_0_task_set
+                                         & io_mshrInfo_8_bits_channel[0]}))})})}
+               + {1'h0,
+                  4'({1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_9_valid
+                                & io_mshrInfo_9_bits_set == buffer_0_task_set
+                                & io_mshrInfo_9_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_10_valid
+                                  & io_mshrInfo_10_bits_set == buffer_0_task_set
+                                  & io_mshrInfo_10_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_11_valid
+                                  & io_mshrInfo_11_bits_set == buffer_0_task_set
+                                  & io_mshrInfo_11_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_12_valid
+                                    & io_mshrInfo_12_bits_set == buffer_0_task_set
+                                    & io_mshrInfo_12_bits_channel[0]})})}
+                     + {1'h0,
+                        3'({1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_13_valid
+                                  & io_mshrInfo_13_bits_set == buffer_0_task_set
+                                  & io_mshrInfo_13_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_14_valid
+                                    & io_mshrInfo_14_bits_set == buffer_0_task_set
+                                    & io_mshrInfo_14_bits_channel[0]})}
+                           + {1'h0,
+                              2'({1'h0,
+                                  io_mshrInfo_15_valid
+                                    & io_mshrInfo_15_bits_set == buffer_0_task_set
+                                    & io_mshrInfo_15_bits_channel[0]}
+                                 + 2'({1'h0,
+                                       io_taskFromArb_s2_valid
+                                         & io_taskFromArb_s2_bits_channel[0]
+                                         & ~io_taskFromArb_s2_bits_mshrTask
+                                         & io_taskFromArb_s2_bits_set == buffer_0_task_set}
+                                      + {1'h0,
+                                         buffer_0_rdy_sameSet_s3_REG_1
+                                           & buffer_0_rdy_sameSet_s3_r_1 == buffer_0_task_set}))})})}) < 5'h8;
+        buffer_0_waitMP <= {1'h0, {s1_Block, 2'h0} | buffer_0_waitMP[3:1]};
+        buffer_0_waitMS <= waitMSUpdate;
+      end
+      else if (_GEN) begin
+        buffer_0_rdy <=
+          {io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+             & (_buffer_3_waitMS_T_136 | _buffer_3_waitMS_T_137
+                & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+           io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+             & (_buffer_3_waitMS_T_127 | _buffer_3_waitMS_T_128
+                & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+           io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+             & (_buffer_3_waitMS_T_118 | _buffer_3_waitMS_T_119
+                & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+           io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+             & (_buffer_3_waitMS_T_109 | _buffer_3_waitMS_T_110
+                & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+           io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+             & (_buffer_3_waitMS_T_100 | _buffer_3_waitMS_T_101
+                & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+           io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+             & (_buffer_3_waitMS_T_91 | _buffer_3_waitMS_T_92
+                & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+           io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+             & (_buffer_3_waitMS_T_82 | _buffer_3_waitMS_T_83
+                & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+           io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+             & (_buffer_3_waitMS_T_73 | _buffer_3_waitMS_T_74
+                & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+           io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+             & (_buffer_3_waitMS_T_64 | _buffer_3_waitMS_T_65
+                & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+           io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+             & (_buffer_3_waitMS_T_55 | _buffer_3_waitMS_T_56
+                & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+           io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+             & (_buffer_3_waitMS_T_46 | _buffer_3_waitMS_T_47
+                & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+           io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+             & (_buffer_3_waitMS_T_37 | _buffer_3_waitMS_T_38
+                & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+           io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+             & (_buffer_3_waitMS_T_28 | _buffer_3_waitMS_T_29
+                & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+           io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+             & (_buffer_3_waitMS_T_19 | _buffer_3_waitMS_T_20
+                & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+           io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+             & (_buffer_3_waitMS_T_10 | _buffer_3_waitMS_T_11
+                & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+           io_mshrInfo_0_valid & _buffer_3_waitMS_T
+             & (_buffer_3_waitMS_T_1 | _buffer_3_waitMS_T_2
+                & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree} == 16'h0
+          & _mpBlock_T_3 == 2'h0 & ~s1Block
+          & 5'({1'h0,
+                4'({1'h0,
+                    3'({1'h0,
+                        2'({1'h0,
+                            io_mshrInfo_0_valid & _buffer_3_waitMS_T
+                              & io_mshrInfo_0_bits_channel[0]}
+                           + {1'h0,
+                              io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+                                & io_mshrInfo_1_bits_channel[0]})}
+                       + {1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+                                & io_mshrInfo_2_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+                                  & io_mshrInfo_3_bits_channel[0]})})}
+                   + {1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+                                & io_mshrInfo_4_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+                                  & io_mshrInfo_5_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+                                  & io_mshrInfo_6_bits_channel[0]}
+                               + 2'({1'h0,
+                                     io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+                                       & io_mshrInfo_7_bits_channel[0]}
+                                    + {1'h0,
+                                       io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+                                         & io_mshrInfo_8_bits_channel[0]}))})})}
+               + {1'h0,
+                  4'({1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+                                & io_mshrInfo_9_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+                                  & io_mshrInfo_10_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+                                  & io_mshrInfo_11_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+                                    & io_mshrInfo_12_bits_channel[0]})})}
+                     + {1'h0,
+                        3'({1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+                                  & io_mshrInfo_13_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+                                    & io_mshrInfo_14_bits_channel[0]})}
+                           + {1'h0,
+                              2'({1'h0,
+                                  io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+                                    & io_mshrInfo_15_bits_channel[0]}
+                                 + 2'({1'h0,
+                                       io_taskFromArb_s2_valid
+                                         & io_taskFromArb_s2_bits_channel[0]
+                                         & ~io_taskFromArb_s2_bits_mshrTask
+                                         & _buffer_3_rdy_sameSet_s2_T_4}
+                                      + {1'h0,
+                                         buffer_0_rdy_sameSet_s3_REG
+                                           & buffer_0_rdy_sameSet_s3_r == io_in_bits_set}))})})}) < 5'h8;
+        buffer_0_waitMP <= {s1Block, io_mainPipeBlock_0, io_mainPipeBlock_1, 1'h0};
+        buffer_0_waitMS <=
+          {io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+             & (_buffer_3_waitMS_T_136 | _buffer_3_waitMS_T_137
+                & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+           io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+             & (_buffer_3_waitMS_T_127 | _buffer_3_waitMS_T_128
+                & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+           io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+             & (_buffer_3_waitMS_T_118 | _buffer_3_waitMS_T_119
+                & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+           io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+             & (_buffer_3_waitMS_T_109 | _buffer_3_waitMS_T_110
+                & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+           io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+             & (_buffer_3_waitMS_T_100 | _buffer_3_waitMS_T_101
+                & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+           io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+             & (_buffer_3_waitMS_T_91 | _buffer_3_waitMS_T_92
+                & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+           io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+             & (_buffer_3_waitMS_T_82 | _buffer_3_waitMS_T_83
+                & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+           io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+             & (_buffer_3_waitMS_T_73 | _buffer_3_waitMS_T_74
+                & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+           io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+             & (_buffer_3_waitMS_T_64 | _buffer_3_waitMS_T_65
+                & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+           io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+             & (_buffer_3_waitMS_T_55 | _buffer_3_waitMS_T_56
+                & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+           io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+             & (_buffer_3_waitMS_T_46 | _buffer_3_waitMS_T_47
+                & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+           io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+             & (_buffer_3_waitMS_T_37 | _buffer_3_waitMS_T_38
+                & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+           io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+             & (_buffer_3_waitMS_T_28 | _buffer_3_waitMS_T_29
+                & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+           io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+             & (_buffer_3_waitMS_T_19 | _buffer_3_waitMS_T_20
+                & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+           io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+             & (_buffer_3_waitMS_T_10 | _buffer_3_waitMS_T_11
+                & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+           io_mshrInfo_0_valid & _buffer_3_waitMS_T
+             & (_buffer_3_waitMS_T_1 | _buffer_3_waitMS_T_2
+                & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree};
+      end
+      if (_GEN) begin
+        buffer_0_task_channel <= 3'h1;
+        buffer_0_task_set <= io_in_bits_set;
+        buffer_0_task_tag <= io_in_bits_tag;
+        buffer_0_task_off <= io_in_bits_off;
+        buffer_0_task_alias <= io_in_bits_alias;
+        buffer_0_task_vaddr <= io_in_bits_vaddr;
+        buffer_0_task_isKeyword <= io_in_bits_isKeyword;
+        buffer_0_task_opcode <= io_in_bits_opcode;
+        buffer_0_task_param <= io_in_bits_param;
+        buffer_0_task_size <= io_in_bits_size;
+        buffer_0_task_sourceId <= io_in_bits_sourceId;
+        buffer_0_task_corrupt <= io_in_bits_corrupt;
+        buffer_0_task_fromL2pft <= io_in_bits_fromL2pft;
+        buffer_0_task_needHint <= io_in_bits_needHint;
+        buffer_0_task_reqSource <= io_in_bits_reqSource;
+      end
+      buffer_1_valid <=
+        ~(_GEN_3 & _chosenQ_io_deq_bits_idOH[1] & _io_out_valid_T)
+        & (_GEN_0 | buffer_1_valid);
+      if (buffer_1_valid) begin
+        buffer_1_rdy <=
+          waitMSUpdate_1 == 16'h0 & buffer_1_waitMP == 4'h0 & ~s1_Block_1
+          & 5'({1'h0,
+                4'({1'h0,
+                    3'({1'h0,
+                        2'({1'h0,
+                            io_mshrInfo_0_valid
+                              & io_mshrInfo_0_bits_set == buffer_1_task_set
+                              & io_mshrInfo_0_bits_channel[0]}
+                           + {1'h0,
+                              io_mshrInfo_1_valid
+                                & io_mshrInfo_1_bits_set == buffer_1_task_set
+                                & io_mshrInfo_1_bits_channel[0]})}
+                       + {1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_2_valid
+                                & io_mshrInfo_2_bits_set == buffer_1_task_set
+                                & io_mshrInfo_2_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_3_valid
+                                  & io_mshrInfo_3_bits_set == buffer_1_task_set
+                                  & io_mshrInfo_3_bits_channel[0]})})}
+                   + {1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_4_valid
+                                & io_mshrInfo_4_bits_set == buffer_1_task_set
+                                & io_mshrInfo_4_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_5_valid
+                                  & io_mshrInfo_5_bits_set == buffer_1_task_set
+                                  & io_mshrInfo_5_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_6_valid
+                                  & io_mshrInfo_6_bits_set == buffer_1_task_set
+                                  & io_mshrInfo_6_bits_channel[0]}
+                               + 2'({1'h0,
+                                     io_mshrInfo_7_valid
+                                       & io_mshrInfo_7_bits_set == buffer_1_task_set
+                                       & io_mshrInfo_7_bits_channel[0]}
+                                    + {1'h0,
+                                       io_mshrInfo_8_valid
+                                         & io_mshrInfo_8_bits_set == buffer_1_task_set
+                                         & io_mshrInfo_8_bits_channel[0]}))})})}
+               + {1'h0,
+                  4'({1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_9_valid
+                                & io_mshrInfo_9_bits_set == buffer_1_task_set
+                                & io_mshrInfo_9_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_10_valid
+                                  & io_mshrInfo_10_bits_set == buffer_1_task_set
+                                  & io_mshrInfo_10_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_11_valid
+                                  & io_mshrInfo_11_bits_set == buffer_1_task_set
+                                  & io_mshrInfo_11_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_12_valid
+                                    & io_mshrInfo_12_bits_set == buffer_1_task_set
+                                    & io_mshrInfo_12_bits_channel[0]})})}
+                     + {1'h0,
+                        3'({1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_13_valid
+                                  & io_mshrInfo_13_bits_set == buffer_1_task_set
+                                  & io_mshrInfo_13_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_14_valid
+                                    & io_mshrInfo_14_bits_set == buffer_1_task_set
+                                    & io_mshrInfo_14_bits_channel[0]})}
+                           + {1'h0,
+                              2'({1'h0,
+                                  io_mshrInfo_15_valid
+                                    & io_mshrInfo_15_bits_set == buffer_1_task_set
+                                    & io_mshrInfo_15_bits_channel[0]}
+                                 + 2'({1'h0,
+                                       io_taskFromArb_s2_valid
+                                         & io_taskFromArb_s2_bits_channel[0]
+                                         & ~io_taskFromArb_s2_bits_mshrTask
+                                         & io_taskFromArb_s2_bits_set == buffer_1_task_set}
+                                      + {1'h0,
+                                         buffer_1_rdy_sameSet_s3_REG_1
+                                           & buffer_1_rdy_sameSet_s3_r_1 == buffer_1_task_set}))})})}) < 5'h8;
+        buffer_1_waitMP <= {1'h0, {s1_Block_1, 2'h0} | buffer_1_waitMP[3:1]};
+        buffer_1_waitMS <= waitMSUpdate_1;
+      end
+      else if (_GEN_0) begin
+        buffer_1_rdy <=
+          {io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+             & (_buffer_3_waitMS_T_136 | _buffer_3_waitMS_T_137
+                & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+           io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+             & (_buffer_3_waitMS_T_127 | _buffer_3_waitMS_T_128
+                & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+           io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+             & (_buffer_3_waitMS_T_118 | _buffer_3_waitMS_T_119
+                & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+           io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+             & (_buffer_3_waitMS_T_109 | _buffer_3_waitMS_T_110
+                & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+           io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+             & (_buffer_3_waitMS_T_100 | _buffer_3_waitMS_T_101
+                & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+           io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+             & (_buffer_3_waitMS_T_91 | _buffer_3_waitMS_T_92
+                & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+           io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+             & (_buffer_3_waitMS_T_82 | _buffer_3_waitMS_T_83
+                & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+           io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+             & (_buffer_3_waitMS_T_73 | _buffer_3_waitMS_T_74
+                & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+           io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+             & (_buffer_3_waitMS_T_64 | _buffer_3_waitMS_T_65
+                & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+           io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+             & (_buffer_3_waitMS_T_55 | _buffer_3_waitMS_T_56
+                & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+           io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+             & (_buffer_3_waitMS_T_46 | _buffer_3_waitMS_T_47
+                & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+           io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+             & (_buffer_3_waitMS_T_37 | _buffer_3_waitMS_T_38
+                & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+           io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+             & (_buffer_3_waitMS_T_28 | _buffer_3_waitMS_T_29
+                & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+           io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+             & (_buffer_3_waitMS_T_19 | _buffer_3_waitMS_T_20
+                & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+           io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+             & (_buffer_3_waitMS_T_10 | _buffer_3_waitMS_T_11
+                & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+           io_mshrInfo_0_valid & _buffer_3_waitMS_T
+             & (_buffer_3_waitMS_T_1 | _buffer_3_waitMS_T_2
+                & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree} == 16'h0
+          & _mpBlock_T_3 == 2'h0 & ~s1Block_1
+          & 5'({1'h0,
+                4'({1'h0,
+                    3'({1'h0,
+                        2'({1'h0,
+                            io_mshrInfo_0_valid & _buffer_3_waitMS_T
+                              & io_mshrInfo_0_bits_channel[0]}
+                           + {1'h0,
+                              io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+                                & io_mshrInfo_1_bits_channel[0]})}
+                       + {1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+                                & io_mshrInfo_2_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+                                  & io_mshrInfo_3_bits_channel[0]})})}
+                   + {1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+                                & io_mshrInfo_4_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+                                  & io_mshrInfo_5_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+                                  & io_mshrInfo_6_bits_channel[0]}
+                               + 2'({1'h0,
+                                     io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+                                       & io_mshrInfo_7_bits_channel[0]}
+                                    + {1'h0,
+                                       io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+                                         & io_mshrInfo_8_bits_channel[0]}))})})}
+               + {1'h0,
+                  4'({1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+                                & io_mshrInfo_9_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+                                  & io_mshrInfo_10_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+                                  & io_mshrInfo_11_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+                                    & io_mshrInfo_12_bits_channel[0]})})}
+                     + {1'h0,
+                        3'({1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+                                  & io_mshrInfo_13_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+                                    & io_mshrInfo_14_bits_channel[0]})}
+                           + {1'h0,
+                              2'({1'h0,
+                                  io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+                                    & io_mshrInfo_15_bits_channel[0]}
+                                 + 2'({1'h0,
+                                       io_taskFromArb_s2_valid
+                                         & io_taskFromArb_s2_bits_channel[0]
+                                         & ~io_taskFromArb_s2_bits_mshrTask
+                                         & _buffer_3_rdy_sameSet_s2_T_4}
+                                      + {1'h0,
+                                         buffer_1_rdy_sameSet_s3_REG
+                                           & buffer_1_rdy_sameSet_s3_r == io_in_bits_set}))})})}) < 5'h8;
+        buffer_1_waitMP <= {s1Block_1, io_mainPipeBlock_0, io_mainPipeBlock_1, 1'h0};
+        buffer_1_waitMS <=
+          {io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+             & (_buffer_3_waitMS_T_136 | _buffer_3_waitMS_T_137
+                & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+           io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+             & (_buffer_3_waitMS_T_127 | _buffer_3_waitMS_T_128
+                & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+           io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+             & (_buffer_3_waitMS_T_118 | _buffer_3_waitMS_T_119
+                & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+           io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+             & (_buffer_3_waitMS_T_109 | _buffer_3_waitMS_T_110
+                & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+           io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+             & (_buffer_3_waitMS_T_100 | _buffer_3_waitMS_T_101
+                & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+           io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+             & (_buffer_3_waitMS_T_91 | _buffer_3_waitMS_T_92
+                & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+           io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+             & (_buffer_3_waitMS_T_82 | _buffer_3_waitMS_T_83
+                & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+           io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+             & (_buffer_3_waitMS_T_73 | _buffer_3_waitMS_T_74
+                & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+           io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+             & (_buffer_3_waitMS_T_64 | _buffer_3_waitMS_T_65
+                & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+           io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+             & (_buffer_3_waitMS_T_55 | _buffer_3_waitMS_T_56
+                & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+           io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+             & (_buffer_3_waitMS_T_46 | _buffer_3_waitMS_T_47
+                & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+           io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+             & (_buffer_3_waitMS_T_37 | _buffer_3_waitMS_T_38
+                & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+           io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+             & (_buffer_3_waitMS_T_28 | _buffer_3_waitMS_T_29
+                & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+           io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+             & (_buffer_3_waitMS_T_19 | _buffer_3_waitMS_T_20
+                & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+           io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+             & (_buffer_3_waitMS_T_10 | _buffer_3_waitMS_T_11
+                & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+           io_mshrInfo_0_valid & _buffer_3_waitMS_T
+             & (_buffer_3_waitMS_T_1 | _buffer_3_waitMS_T_2
+                & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree};
+      end
+      if (_GEN_0) begin
+        buffer_1_task_channel <= 3'h1;
+        buffer_1_task_set <= io_in_bits_set;
+        buffer_1_task_tag <= io_in_bits_tag;
+        buffer_1_task_off <= io_in_bits_off;
+        buffer_1_task_alias <= io_in_bits_alias;
+        buffer_1_task_vaddr <= io_in_bits_vaddr;
+        buffer_1_task_isKeyword <= io_in_bits_isKeyword;
+        buffer_1_task_opcode <= io_in_bits_opcode;
+        buffer_1_task_param <= io_in_bits_param;
+        buffer_1_task_size <= io_in_bits_size;
+        buffer_1_task_sourceId <= io_in_bits_sourceId;
+        buffer_1_task_corrupt <= io_in_bits_corrupt;
+        buffer_1_task_fromL2pft <= io_in_bits_fromL2pft;
+        buffer_1_task_needHint <= io_in_bits_needHint;
+        buffer_1_task_reqSource <= io_in_bits_reqSource;
+      end
+      buffer_2_valid <=
+        ~(_GEN_3 & _chosenQ_io_deq_bits_idOH[2] & _io_out_valid_T)
+        & (_GEN_1 | buffer_2_valid);
+      if (buffer_2_valid) begin
+        buffer_2_rdy <=
+          waitMSUpdate_2 == 16'h0 & buffer_2_waitMP == 4'h0 & ~s1_Block_2
+          & 5'({1'h0,
+                4'({1'h0,
+                    3'({1'h0,
+                        2'({1'h0,
+                            io_mshrInfo_0_valid
+                              & io_mshrInfo_0_bits_set == buffer_2_task_set
+                              & io_mshrInfo_0_bits_channel[0]}
+                           + {1'h0,
+                              io_mshrInfo_1_valid
+                                & io_mshrInfo_1_bits_set == buffer_2_task_set
+                                & io_mshrInfo_1_bits_channel[0]})}
+                       + {1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_2_valid
+                                & io_mshrInfo_2_bits_set == buffer_2_task_set
+                                & io_mshrInfo_2_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_3_valid
+                                  & io_mshrInfo_3_bits_set == buffer_2_task_set
+                                  & io_mshrInfo_3_bits_channel[0]})})}
+                   + {1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_4_valid
+                                & io_mshrInfo_4_bits_set == buffer_2_task_set
+                                & io_mshrInfo_4_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_5_valid
+                                  & io_mshrInfo_5_bits_set == buffer_2_task_set
+                                  & io_mshrInfo_5_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_6_valid
+                                  & io_mshrInfo_6_bits_set == buffer_2_task_set
+                                  & io_mshrInfo_6_bits_channel[0]}
+                               + 2'({1'h0,
+                                     io_mshrInfo_7_valid
+                                       & io_mshrInfo_7_bits_set == buffer_2_task_set
+                                       & io_mshrInfo_7_bits_channel[0]}
+                                    + {1'h0,
+                                       io_mshrInfo_8_valid
+                                         & io_mshrInfo_8_bits_set == buffer_2_task_set
+                                         & io_mshrInfo_8_bits_channel[0]}))})})}
+               + {1'h0,
+                  4'({1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_9_valid
+                                & io_mshrInfo_9_bits_set == buffer_2_task_set
+                                & io_mshrInfo_9_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_10_valid
+                                  & io_mshrInfo_10_bits_set == buffer_2_task_set
+                                  & io_mshrInfo_10_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_11_valid
+                                  & io_mshrInfo_11_bits_set == buffer_2_task_set
+                                  & io_mshrInfo_11_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_12_valid
+                                    & io_mshrInfo_12_bits_set == buffer_2_task_set
+                                    & io_mshrInfo_12_bits_channel[0]})})}
+                     + {1'h0,
+                        3'({1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_13_valid
+                                  & io_mshrInfo_13_bits_set == buffer_2_task_set
+                                  & io_mshrInfo_13_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_14_valid
+                                    & io_mshrInfo_14_bits_set == buffer_2_task_set
+                                    & io_mshrInfo_14_bits_channel[0]})}
+                           + {1'h0,
+                              2'({1'h0,
+                                  io_mshrInfo_15_valid
+                                    & io_mshrInfo_15_bits_set == buffer_2_task_set
+                                    & io_mshrInfo_15_bits_channel[0]}
+                                 + 2'({1'h0,
+                                       io_taskFromArb_s2_valid
+                                         & io_taskFromArb_s2_bits_channel[0]
+                                         & ~io_taskFromArb_s2_bits_mshrTask
+                                         & io_taskFromArb_s2_bits_set == buffer_2_task_set}
+                                      + {1'h0,
+                                         buffer_2_rdy_sameSet_s3_REG_1
+                                           & buffer_2_rdy_sameSet_s3_r_1 == buffer_2_task_set}))})})}) < 5'h8;
+        buffer_2_waitMP <= {1'h0, {s1_Block_2, 2'h0} | buffer_2_waitMP[3:1]};
+        buffer_2_waitMS <= waitMSUpdate_2;
+      end
+      else if (_GEN_1) begin
+        buffer_2_rdy <=
+          {io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+             & (_buffer_3_waitMS_T_136 | _buffer_3_waitMS_T_137
+                & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+           io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+             & (_buffer_3_waitMS_T_127 | _buffer_3_waitMS_T_128
+                & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+           io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+             & (_buffer_3_waitMS_T_118 | _buffer_3_waitMS_T_119
+                & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+           io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+             & (_buffer_3_waitMS_T_109 | _buffer_3_waitMS_T_110
+                & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+           io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+             & (_buffer_3_waitMS_T_100 | _buffer_3_waitMS_T_101
+                & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+           io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+             & (_buffer_3_waitMS_T_91 | _buffer_3_waitMS_T_92
+                & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+           io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+             & (_buffer_3_waitMS_T_82 | _buffer_3_waitMS_T_83
+                & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+           io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+             & (_buffer_3_waitMS_T_73 | _buffer_3_waitMS_T_74
+                & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+           io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+             & (_buffer_3_waitMS_T_64 | _buffer_3_waitMS_T_65
+                & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+           io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+             & (_buffer_3_waitMS_T_55 | _buffer_3_waitMS_T_56
+                & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+           io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+             & (_buffer_3_waitMS_T_46 | _buffer_3_waitMS_T_47
+                & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+           io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+             & (_buffer_3_waitMS_T_37 | _buffer_3_waitMS_T_38
+                & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+           io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+             & (_buffer_3_waitMS_T_28 | _buffer_3_waitMS_T_29
+                & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+           io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+             & (_buffer_3_waitMS_T_19 | _buffer_3_waitMS_T_20
+                & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+           io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+             & (_buffer_3_waitMS_T_10 | _buffer_3_waitMS_T_11
+                & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+           io_mshrInfo_0_valid & _buffer_3_waitMS_T
+             & (_buffer_3_waitMS_T_1 | _buffer_3_waitMS_T_2
+                & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree} == 16'h0
+          & _mpBlock_T_3 == 2'h0 & ~s1Block_2
+          & 5'({1'h0,
+                4'({1'h0,
+                    3'({1'h0,
+                        2'({1'h0,
+                            io_mshrInfo_0_valid & _buffer_3_waitMS_T
+                              & io_mshrInfo_0_bits_channel[0]}
+                           + {1'h0,
+                              io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+                                & io_mshrInfo_1_bits_channel[0]})}
+                       + {1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+                                & io_mshrInfo_2_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+                                  & io_mshrInfo_3_bits_channel[0]})})}
+                   + {1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+                                & io_mshrInfo_4_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+                                  & io_mshrInfo_5_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+                                  & io_mshrInfo_6_bits_channel[0]}
+                               + 2'({1'h0,
+                                     io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+                                       & io_mshrInfo_7_bits_channel[0]}
+                                    + {1'h0,
+                                       io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+                                         & io_mshrInfo_8_bits_channel[0]}))})})}
+               + {1'h0,
+                  4'({1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+                                & io_mshrInfo_9_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+                                  & io_mshrInfo_10_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+                                  & io_mshrInfo_11_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+                                    & io_mshrInfo_12_bits_channel[0]})})}
+                     + {1'h0,
+                        3'({1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+                                  & io_mshrInfo_13_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+                                    & io_mshrInfo_14_bits_channel[0]})}
+                           + {1'h0,
+                              2'({1'h0,
+                                  io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+                                    & io_mshrInfo_15_bits_channel[0]}
+                                 + 2'({1'h0,
+                                       io_taskFromArb_s2_valid
+                                         & io_taskFromArb_s2_bits_channel[0]
+                                         & ~io_taskFromArb_s2_bits_mshrTask
+                                         & _buffer_3_rdy_sameSet_s2_T_4}
+                                      + {1'h0,
+                                         buffer_2_rdy_sameSet_s3_REG
+                                           & buffer_2_rdy_sameSet_s3_r == io_in_bits_set}))})})}) < 5'h8;
+        buffer_2_waitMP <= {s1Block_2, io_mainPipeBlock_0, io_mainPipeBlock_1, 1'h0};
+        buffer_2_waitMS <=
+          {io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+             & (_buffer_3_waitMS_T_136 | _buffer_3_waitMS_T_137
+                & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+           io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+             & (_buffer_3_waitMS_T_127 | _buffer_3_waitMS_T_128
+                & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+           io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+             & (_buffer_3_waitMS_T_118 | _buffer_3_waitMS_T_119
+                & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+           io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+             & (_buffer_3_waitMS_T_109 | _buffer_3_waitMS_T_110
+                & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+           io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+             & (_buffer_3_waitMS_T_100 | _buffer_3_waitMS_T_101
+                & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+           io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+             & (_buffer_3_waitMS_T_91 | _buffer_3_waitMS_T_92
+                & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+           io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+             & (_buffer_3_waitMS_T_82 | _buffer_3_waitMS_T_83
+                & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+           io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+             & (_buffer_3_waitMS_T_73 | _buffer_3_waitMS_T_74
+                & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+           io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+             & (_buffer_3_waitMS_T_64 | _buffer_3_waitMS_T_65
+                & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+           io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+             & (_buffer_3_waitMS_T_55 | _buffer_3_waitMS_T_56
+                & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+           io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+             & (_buffer_3_waitMS_T_46 | _buffer_3_waitMS_T_47
+                & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+           io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+             & (_buffer_3_waitMS_T_37 | _buffer_3_waitMS_T_38
+                & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+           io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+             & (_buffer_3_waitMS_T_28 | _buffer_3_waitMS_T_29
+                & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+           io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+             & (_buffer_3_waitMS_T_19 | _buffer_3_waitMS_T_20
+                & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+           io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+             & (_buffer_3_waitMS_T_10 | _buffer_3_waitMS_T_11
+                & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+           io_mshrInfo_0_valid & _buffer_3_waitMS_T
+             & (_buffer_3_waitMS_T_1 | _buffer_3_waitMS_T_2
+                & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree};
+      end
+      if (_GEN_1) begin
+        buffer_2_task_channel <= 3'h1;
+        buffer_2_task_set <= io_in_bits_set;
+        buffer_2_task_tag <= io_in_bits_tag;
+        buffer_2_task_off <= io_in_bits_off;
+        buffer_2_task_alias <= io_in_bits_alias;
+        buffer_2_task_vaddr <= io_in_bits_vaddr;
+        buffer_2_task_isKeyword <= io_in_bits_isKeyword;
+        buffer_2_task_opcode <= io_in_bits_opcode;
+        buffer_2_task_param <= io_in_bits_param;
+        buffer_2_task_size <= io_in_bits_size;
+        buffer_2_task_sourceId <= io_in_bits_sourceId;
+        buffer_2_task_corrupt <= io_in_bits_corrupt;
+        buffer_2_task_fromL2pft <= io_in_bits_fromL2pft;
+        buffer_2_task_needHint <= io_in_bits_needHint;
+        buffer_2_task_reqSource <= io_in_bits_reqSource;
+      end
+      buffer_3_valid <=
+        ~(_GEN_3 & _chosenQ_io_deq_bits_idOH[3] & _io_out_valid_T)
+        & (_GEN_2 | buffer_3_valid);
+      if (buffer_3_valid) begin
+        buffer_3_rdy <=
+          waitMSUpdate_3 == 16'h0 & buffer_3_waitMP == 4'h0 & ~s1_Block_3
+          & 5'({1'h0,
+                4'({1'h0,
+                    3'({1'h0,
+                        2'({1'h0,
+                            io_mshrInfo_0_valid
+                              & io_mshrInfo_0_bits_set == buffer_3_task_set
+                              & io_mshrInfo_0_bits_channel[0]}
+                           + {1'h0,
+                              io_mshrInfo_1_valid
+                                & io_mshrInfo_1_bits_set == buffer_3_task_set
+                                & io_mshrInfo_1_bits_channel[0]})}
+                       + {1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_2_valid
+                                & io_mshrInfo_2_bits_set == buffer_3_task_set
+                                & io_mshrInfo_2_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_3_valid
+                                  & io_mshrInfo_3_bits_set == buffer_3_task_set
+                                  & io_mshrInfo_3_bits_channel[0]})})}
+                   + {1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_4_valid
+                                & io_mshrInfo_4_bits_set == buffer_3_task_set
+                                & io_mshrInfo_4_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_5_valid
+                                  & io_mshrInfo_5_bits_set == buffer_3_task_set
+                                  & io_mshrInfo_5_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_6_valid
+                                  & io_mshrInfo_6_bits_set == buffer_3_task_set
+                                  & io_mshrInfo_6_bits_channel[0]}
+                               + 2'({1'h0,
+                                     io_mshrInfo_7_valid
+                                       & io_mshrInfo_7_bits_set == buffer_3_task_set
+                                       & io_mshrInfo_7_bits_channel[0]}
+                                    + {1'h0,
+                                       io_mshrInfo_8_valid
+                                         & io_mshrInfo_8_bits_set == buffer_3_task_set
+                                         & io_mshrInfo_8_bits_channel[0]}))})})}
+               + {1'h0,
+                  4'({1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_9_valid
+                                & io_mshrInfo_9_bits_set == buffer_3_task_set
+                                & io_mshrInfo_9_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_10_valid
+                                  & io_mshrInfo_10_bits_set == buffer_3_task_set
+                                  & io_mshrInfo_10_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_11_valid
+                                  & io_mshrInfo_11_bits_set == buffer_3_task_set
+                                  & io_mshrInfo_11_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_12_valid
+                                    & io_mshrInfo_12_bits_set == buffer_3_task_set
+                                    & io_mshrInfo_12_bits_channel[0]})})}
+                     + {1'h0,
+                        3'({1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_13_valid
+                                  & io_mshrInfo_13_bits_set == buffer_3_task_set
+                                  & io_mshrInfo_13_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_14_valid
+                                    & io_mshrInfo_14_bits_set == buffer_3_task_set
+                                    & io_mshrInfo_14_bits_channel[0]})}
+                           + {1'h0,
+                              2'({1'h0,
+                                  io_mshrInfo_15_valid
+                                    & io_mshrInfo_15_bits_set == buffer_3_task_set
+                                    & io_mshrInfo_15_bits_channel[0]}
+                                 + 2'({1'h0,
+                                       io_taskFromArb_s2_valid
+                                         & io_taskFromArb_s2_bits_channel[0]
+                                         & ~io_taskFromArb_s2_bits_mshrTask
+                                         & io_taskFromArb_s2_bits_set == buffer_3_task_set}
+                                      + {1'h0,
+                                         buffer_3_rdy_sameSet_s3_REG_1
+                                           & buffer_3_rdy_sameSet_s3_r_1 == buffer_3_task_set}))})})}) < 5'h8;
+        buffer_3_waitMP <= {1'h0, {s1_Block_3, 2'h0} | buffer_3_waitMP[3:1]};
+        buffer_3_waitMS <= waitMSUpdate_3;
+      end
+      else if (_GEN_2) begin
+        buffer_3_rdy <=
+          {io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+             & (_buffer_3_waitMS_T_136 | _buffer_3_waitMS_T_137
+                & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+           io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+             & (_buffer_3_waitMS_T_127 | _buffer_3_waitMS_T_128
+                & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+           io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+             & (_buffer_3_waitMS_T_118 | _buffer_3_waitMS_T_119
+                & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+           io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+             & (_buffer_3_waitMS_T_109 | _buffer_3_waitMS_T_110
+                & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+           io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+             & (_buffer_3_waitMS_T_100 | _buffer_3_waitMS_T_101
+                & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+           io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+             & (_buffer_3_waitMS_T_91 | _buffer_3_waitMS_T_92
+                & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+           io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+             & (_buffer_3_waitMS_T_82 | _buffer_3_waitMS_T_83
+                & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+           io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+             & (_buffer_3_waitMS_T_73 | _buffer_3_waitMS_T_74
+                & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+           io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+             & (_buffer_3_waitMS_T_64 | _buffer_3_waitMS_T_65
+                & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+           io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+             & (_buffer_3_waitMS_T_55 | _buffer_3_waitMS_T_56
+                & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+           io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+             & (_buffer_3_waitMS_T_46 | _buffer_3_waitMS_T_47
+                & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+           io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+             & (_buffer_3_waitMS_T_37 | _buffer_3_waitMS_T_38
+                & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+           io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+             & (_buffer_3_waitMS_T_28 | _buffer_3_waitMS_T_29
+                & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+           io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+             & (_buffer_3_waitMS_T_19 | _buffer_3_waitMS_T_20
+                & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+           io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+             & (_buffer_3_waitMS_T_10 | _buffer_3_waitMS_T_11
+                & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+           io_mshrInfo_0_valid & _buffer_3_waitMS_T
+             & (_buffer_3_waitMS_T_1 | _buffer_3_waitMS_T_2
+                & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree} == 16'h0
+          & _mpBlock_T_3 == 2'h0 & ~s1Block_3
+          & 5'({1'h0,
+                4'({1'h0,
+                    3'({1'h0,
+                        2'({1'h0,
+                            io_mshrInfo_0_valid & _buffer_3_waitMS_T
+                              & io_mshrInfo_0_bits_channel[0]}
+                           + {1'h0,
+                              io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+                                & io_mshrInfo_1_bits_channel[0]})}
+                       + {1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+                                & io_mshrInfo_2_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+                                  & io_mshrInfo_3_bits_channel[0]})})}
+                   + {1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+                                & io_mshrInfo_4_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+                                  & io_mshrInfo_5_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+                                  & io_mshrInfo_6_bits_channel[0]}
+                               + 2'({1'h0,
+                                     io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+                                       & io_mshrInfo_7_bits_channel[0]}
+                                    + {1'h0,
+                                       io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+                                         & io_mshrInfo_8_bits_channel[0]}))})})}
+               + {1'h0,
+                  4'({1'h0,
+                      3'({1'h0,
+                          2'({1'h0,
+                              io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+                                & io_mshrInfo_9_bits_channel[0]}
+                             + {1'h0,
+                                io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+                                  & io_mshrInfo_10_bits_channel[0]})}
+                         + {1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+                                  & io_mshrInfo_11_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+                                    & io_mshrInfo_12_bits_channel[0]})})}
+                     + {1'h0,
+                        3'({1'h0,
+                            2'({1'h0,
+                                io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+                                  & io_mshrInfo_13_bits_channel[0]}
+                               + {1'h0,
+                                  io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+                                    & io_mshrInfo_14_bits_channel[0]})}
+                           + {1'h0,
+                              2'({1'h0,
+                                  io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+                                    & io_mshrInfo_15_bits_channel[0]}
+                                 + 2'({1'h0,
+                                       io_taskFromArb_s2_valid
+                                         & io_taskFromArb_s2_bits_channel[0]
+                                         & ~io_taskFromArb_s2_bits_mshrTask
+                                         & _buffer_3_rdy_sameSet_s2_T_4}
+                                      + {1'h0,
+                                         buffer_3_rdy_sameSet_s3_REG
+                                           & buffer_3_rdy_sameSet_s3_r == io_in_bits_set}))})})}) < 5'h8;
+        buffer_3_waitMP <= {s1Block_3, io_mainPipeBlock_0, io_mainPipeBlock_1, 1'h0};
+        buffer_3_waitMS <=
+          {io_mshrInfo_15_valid & _buffer_3_waitMS_T_135
+             & (_buffer_3_waitMS_T_136 | _buffer_3_waitMS_T_137
+                & io_mshrInfo_15_bits_needRelease) & ~io_mshrInfo_15_bits_willFree,
+           io_mshrInfo_14_valid & _buffer_3_waitMS_T_126
+             & (_buffer_3_waitMS_T_127 | _buffer_3_waitMS_T_128
+                & io_mshrInfo_14_bits_needRelease) & ~io_mshrInfo_14_bits_willFree,
+           io_mshrInfo_13_valid & _buffer_3_waitMS_T_117
+             & (_buffer_3_waitMS_T_118 | _buffer_3_waitMS_T_119
+                & io_mshrInfo_13_bits_needRelease) & ~io_mshrInfo_13_bits_willFree,
+           io_mshrInfo_12_valid & _buffer_3_waitMS_T_108
+             & (_buffer_3_waitMS_T_109 | _buffer_3_waitMS_T_110
+                & io_mshrInfo_12_bits_needRelease) & ~io_mshrInfo_12_bits_willFree,
+           io_mshrInfo_11_valid & _buffer_3_waitMS_T_99
+             & (_buffer_3_waitMS_T_100 | _buffer_3_waitMS_T_101
+                & io_mshrInfo_11_bits_needRelease) & ~io_mshrInfo_11_bits_willFree,
+           io_mshrInfo_10_valid & _buffer_3_waitMS_T_90
+             & (_buffer_3_waitMS_T_91 | _buffer_3_waitMS_T_92
+                & io_mshrInfo_10_bits_needRelease) & ~io_mshrInfo_10_bits_willFree,
+           io_mshrInfo_9_valid & _buffer_3_waitMS_T_81
+             & (_buffer_3_waitMS_T_82 | _buffer_3_waitMS_T_83
+                & io_mshrInfo_9_bits_needRelease) & ~io_mshrInfo_9_bits_willFree,
+           io_mshrInfo_8_valid & _buffer_3_waitMS_T_72
+             & (_buffer_3_waitMS_T_73 | _buffer_3_waitMS_T_74
+                & io_mshrInfo_8_bits_needRelease) & ~io_mshrInfo_8_bits_willFree,
+           io_mshrInfo_7_valid & _buffer_3_waitMS_T_63
+             & (_buffer_3_waitMS_T_64 | _buffer_3_waitMS_T_65
+                & io_mshrInfo_7_bits_needRelease) & ~io_mshrInfo_7_bits_willFree,
+           io_mshrInfo_6_valid & _buffer_3_waitMS_T_54
+             & (_buffer_3_waitMS_T_55 | _buffer_3_waitMS_T_56
+                & io_mshrInfo_6_bits_needRelease) & ~io_mshrInfo_6_bits_willFree,
+           io_mshrInfo_5_valid & _buffer_3_waitMS_T_45
+             & (_buffer_3_waitMS_T_46 | _buffer_3_waitMS_T_47
+                & io_mshrInfo_5_bits_needRelease) & ~io_mshrInfo_5_bits_willFree,
+           io_mshrInfo_4_valid & _buffer_3_waitMS_T_36
+             & (_buffer_3_waitMS_T_37 | _buffer_3_waitMS_T_38
+                & io_mshrInfo_4_bits_needRelease) & ~io_mshrInfo_4_bits_willFree,
+           io_mshrInfo_3_valid & _buffer_3_waitMS_T_27
+             & (_buffer_3_waitMS_T_28 | _buffer_3_waitMS_T_29
+                & io_mshrInfo_3_bits_needRelease) & ~io_mshrInfo_3_bits_willFree,
+           io_mshrInfo_2_valid & _buffer_3_waitMS_T_18
+             & (_buffer_3_waitMS_T_19 | _buffer_3_waitMS_T_20
+                & io_mshrInfo_2_bits_needRelease) & ~io_mshrInfo_2_bits_willFree,
+           io_mshrInfo_1_valid & _buffer_3_waitMS_T_9
+             & (_buffer_3_waitMS_T_10 | _buffer_3_waitMS_T_11
+                & io_mshrInfo_1_bits_needRelease) & ~io_mshrInfo_1_bits_willFree,
+           io_mshrInfo_0_valid & _buffer_3_waitMS_T
+             & (_buffer_3_waitMS_T_1 | _buffer_3_waitMS_T_2
+                & io_mshrInfo_0_bits_needRelease) & ~io_mshrInfo_0_bits_willFree};
+      end
+      if (_GEN_2) begin
+        buffer_3_task_channel <= 3'h1;
+        buffer_3_task_set <= io_in_bits_set;
+        buffer_3_task_tag <= io_in_bits_tag;
+        buffer_3_task_off <= io_in_bits_off;
+        buffer_3_task_alias <= io_in_bits_alias;
+        buffer_3_task_vaddr <= io_in_bits_vaddr;
+        buffer_3_task_isKeyword <= io_in_bits_isKeyword;
+        buffer_3_task_opcode <= io_in_bits_opcode;
+        buffer_3_task_param <= io_in_bits_param;
+        buffer_3_task_size <= io_in_bits_size;
+        buffer_3_task_sourceId <= io_in_bits_sourceId;
+        buffer_3_task_corrupt <= io_in_bits_corrupt;
+        buffer_3_task_fromL2pft <= io_in_bits_fromL2pft;
+        buffer_3_task_needHint <= io_in_bits_needHint;
+        buffer_3_task_reqSource <= io_in_bits_reqSource;
+      end
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    canFlow_sameSet_s3_REG <=
+      io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_channel[0]
+      & ~io_taskFromArb_s2_bits_mshrTask;
+    if (io_taskFromArb_s2_valid) begin
+      canFlow_sameSet_s3_r <= io_taskFromArb_s2_bits_set;
+      buffer_0_rdy_sameSet_s3_r <= io_taskFromArb_s2_bits_set;
+      buffer_1_rdy_sameSet_s3_r <= io_taskFromArb_s2_bits_set;
+      buffer_2_rdy_sameSet_s3_r <= io_taskFromArb_s2_bits_set;
+      buffer_3_rdy_sameSet_s3_r <= io_taskFromArb_s2_bits_set;
+      buffer_0_rdy_sameSet_s3_r_1 <= io_taskFromArb_s2_bits_set;
+      buffer_1_rdy_sameSet_s3_r_1 <= io_taskFromArb_s2_bits_set;
+      buffer_2_rdy_sameSet_s3_r_1 <= io_taskFromArb_s2_bits_set;
+      buffer_3_rdy_sameSet_s3_r_1 <= io_taskFromArb_s2_bits_set;
+    end
+    buffer_0_rdy_sameSet_s3_REG <=
+      io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_channel[0]
+      & ~io_taskFromArb_s2_bits_mshrTask;
+    buffer_1_rdy_sameSet_s3_REG <=
+      io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_channel[0]
+      & ~io_taskFromArb_s2_bits_mshrTask;
+    buffer_2_rdy_sameSet_s3_REG <=
+      io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_channel[0]
+      & ~io_taskFromArb_s2_bits_mshrTask;
+    buffer_3_rdy_sameSet_s3_REG <=
+      io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_channel[0]
+      & ~io_taskFromArb_s2_bits_mshrTask;
+    buffer_0_rdy_sameSet_s3_REG_1 <=
+      io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_channel[0]
+      & ~io_taskFromArb_s2_bits_mshrTask;
+    buffer_1_rdy_sameSet_s3_REG_1 <=
+      io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_channel[0]
+      & ~io_taskFromArb_s2_bits_mshrTask;
+    buffer_2_rdy_sameSet_s3_REG_1 <=
+      io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_channel[0]
+      & ~io_taskFromArb_s2_bits_mshrTask;
+    buffer_3_rdy_sameSet_s3_REG_1 <=
+      io_taskFromArb_s2_valid & io_taskFromArb_s2_bits_channel[0]
+      & ~io_taskFromArb_s2_bits_mshrTask;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:85];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [6:0] i = 7'h0; i < 7'h56; i += 7'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        buffer_0_valid = _RANDOM[7'h0][0];
+        buffer_0_rdy = _RANDOM[7'h0][1];
+        buffer_0_task_channel = _RANDOM[7'h0][4:2];
+        buffer_0_task_set = _RANDOM[7'h0][15:8];
+        buffer_0_task_tag = {_RANDOM[7'h0][31:16], _RANDOM[7'h1][17:0]};
+        buffer_0_task_off = _RANDOM[7'h1][23:18];
+        buffer_0_task_alias = _RANDOM[7'h1][24];
+        buffer_0_task_vaddr = {_RANDOM[7'h1][31:25], _RANDOM[7'h2], _RANDOM[7'h3][4:0]};
+        buffer_0_task_isKeyword = _RANDOM[7'h3][5];
+        buffer_0_task_opcode = _RANDOM[7'h3][9:6];
+        buffer_0_task_param = _RANDOM[7'h3][12:10];
+        buffer_0_task_size = _RANDOM[7'h3][15:13];
+        buffer_0_task_sourceId = _RANDOM[7'h3][22:16];
+        buffer_0_task_corrupt = _RANDOM[7'h3][27];
+        buffer_0_task_fromL2pft = _RANDOM[7'h4][9];
+        buffer_0_task_needHint = _RANDOM[7'h4][10];
+        buffer_0_task_reqSource = _RANDOM[7'h5][14:10];
+        buffer_0_waitMP = _RANDOM[7'hC][4:1];
+        buffer_0_waitMS = _RANDOM[7'hC][20:5];
+        buffer_1_valid = _RANDOM[7'hC][21];
+        buffer_1_rdy = _RANDOM[7'hC][22];
+        buffer_1_task_channel = _RANDOM[7'hC][25:23];
+        buffer_1_task_set = {_RANDOM[7'hC][31:29], _RANDOM[7'hD][4:0]};
+        buffer_1_task_tag = {_RANDOM[7'hD][31:5], _RANDOM[7'hE][6:0]};
+        buffer_1_task_off = _RANDOM[7'hE][12:7];
+        buffer_1_task_alias = _RANDOM[7'hE][13];
+        buffer_1_task_vaddr = {_RANDOM[7'hE][31:14], _RANDOM[7'hF][25:0]};
+        buffer_1_task_isKeyword = _RANDOM[7'hF][26];
+        buffer_1_task_opcode = _RANDOM[7'hF][30:27];
+        buffer_1_task_param = {_RANDOM[7'hF][31], _RANDOM[7'h10][1:0]};
+        buffer_1_task_size = _RANDOM[7'h10][4:2];
+        buffer_1_task_sourceId = _RANDOM[7'h10][11:5];
+        buffer_1_task_corrupt = _RANDOM[7'h10][16];
+        buffer_1_task_fromL2pft = _RANDOM[7'h10][30];
+        buffer_1_task_needHint = _RANDOM[7'h10][31];
+        buffer_1_task_reqSource = {_RANDOM[7'h11][31], _RANDOM[7'h12][3:0]};
+        buffer_1_waitMP = _RANDOM[7'h18][25:22];
+        buffer_1_waitMS = {_RANDOM[7'h18][31:26], _RANDOM[7'h19][9:0]};
+        buffer_2_valid = _RANDOM[7'h19][10];
+        buffer_2_rdy = _RANDOM[7'h19][11];
+        buffer_2_task_channel = _RANDOM[7'h19][14:12];
+        buffer_2_task_set = _RANDOM[7'h19][25:18];
+        buffer_2_task_tag = {_RANDOM[7'h19][31:26], _RANDOM[7'h1A][27:0]};
+        buffer_2_task_off = {_RANDOM[7'h1A][31:28], _RANDOM[7'h1B][1:0]};
+        buffer_2_task_alias = _RANDOM[7'h1B][2];
+        buffer_2_task_vaddr = {_RANDOM[7'h1B][31:3], _RANDOM[7'h1C][14:0]};
+        buffer_2_task_isKeyword = _RANDOM[7'h1C][15];
+        buffer_2_task_opcode = _RANDOM[7'h1C][19:16];
+        buffer_2_task_param = _RANDOM[7'h1C][22:20];
+        buffer_2_task_size = _RANDOM[7'h1C][25:23];
+        buffer_2_task_sourceId = {_RANDOM[7'h1C][31:26], _RANDOM[7'h1D][0]};
+        buffer_2_task_corrupt = _RANDOM[7'h1D][5];
+        buffer_2_task_fromL2pft = _RANDOM[7'h1D][19];
+        buffer_2_task_needHint = _RANDOM[7'h1D][20];
+        buffer_2_task_reqSource = _RANDOM[7'h1E][24:20];
+        buffer_2_waitMP = _RANDOM[7'h25][14:11];
+        buffer_2_waitMS = _RANDOM[7'h25][30:15];
+        buffer_3_valid = _RANDOM[7'h25][31];
+        buffer_3_rdy = _RANDOM[7'h26][0];
+        buffer_3_task_channel = _RANDOM[7'h26][3:1];
+        buffer_3_task_set = _RANDOM[7'h26][14:7];
+        buffer_3_task_tag = {_RANDOM[7'h26][31:15], _RANDOM[7'h27][16:0]};
+        buffer_3_task_off = _RANDOM[7'h27][22:17];
+        buffer_3_task_alias = _RANDOM[7'h27][23];
+        buffer_3_task_vaddr =
+          {_RANDOM[7'h27][31:24], _RANDOM[7'h28], _RANDOM[7'h29][3:0]};
+        buffer_3_task_isKeyword = _RANDOM[7'h29][4];
+        buffer_3_task_opcode = _RANDOM[7'h29][8:5];
+        buffer_3_task_param = _RANDOM[7'h29][11:9];
+        buffer_3_task_size = _RANDOM[7'h29][14:12];
+        buffer_3_task_sourceId = _RANDOM[7'h29][21:15];
+        buffer_3_task_corrupt = _RANDOM[7'h29][26];
+        buffer_3_task_fromL2pft = _RANDOM[7'h2A][8];
+        buffer_3_task_needHint = _RANDOM[7'h2A][9];
+        buffer_3_task_reqSource = _RANDOM[7'h2B][13:9];
+        buffer_3_waitMP = _RANDOM[7'h32][3:0];
+        buffer_3_waitMS = _RANDOM[7'h32][19:4];
+        canFlow_sameSet_s3_REG = _RANDOM[7'h3A][20];
+        canFlow_sameSet_s3_r = _RANDOM[7'h3A][28:21];
+        buffer_0_rdy_sameSet_s3_REG = _RANDOM[7'h52][27];
+        buffer_0_rdy_sameSet_s3_r = {_RANDOM[7'h52][31:28], _RANDOM[7'h53][3:0]};
+        buffer_1_rdy_sameSet_s3_REG = _RANDOM[7'h53][4];
+        buffer_1_rdy_sameSet_s3_r = _RANDOM[7'h53][12:5];
+        buffer_2_rdy_sameSet_s3_REG = _RANDOM[7'h53][13];
+        buffer_2_rdy_sameSet_s3_r = _RANDOM[7'h53][21:14];
+        buffer_3_rdy_sameSet_s3_REG = _RANDOM[7'h53][22];
+        buffer_3_rdy_sameSet_s3_r = _RANDOM[7'h53][30:23];
+        buffer_0_rdy_sameSet_s3_REG_1 = _RANDOM[7'h53][31];
+        buffer_0_rdy_sameSet_s3_r_1 = _RANDOM[7'h54][7:0];
+        buffer_1_rdy_sameSet_s3_REG_1 = _RANDOM[7'h54][8];
+        buffer_1_rdy_sameSet_s3_r_1 = _RANDOM[7'h54][16:9];
+        buffer_2_rdy_sameSet_s3_REG_1 = _RANDOM[7'h54][17];
+        buffer_2_rdy_sameSet_s3_r_1 = _RANDOM[7'h54][25:18];
+        buffer_3_rdy_sameSet_s3_REG_1 = _RANDOM[7'h54][26];
+        buffer_3_rdy_sameSet_s3_r_1 = {_RANDOM[7'h54][31:27], _RANDOM[7'h55][2:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        buffer_0_valid = 1'h0;
+        buffer_0_rdy = 1'h0;
+        buffer_0_task_channel = 3'h0;
+        buffer_0_task_set = 8'h0;
+        buffer_0_task_tag = 34'h0;
+        buffer_0_task_off = 6'h0;
+        buffer_0_task_alias = 1'h0;
+        buffer_0_task_vaddr = 44'h0;
+        buffer_0_task_isKeyword = 1'h0;
+        buffer_0_task_opcode = 4'h0;
+        buffer_0_task_param = 3'h0;
+        buffer_0_task_size = 3'h0;
+        buffer_0_task_sourceId = 7'h0;
+        buffer_0_task_corrupt = 1'h0;
+        buffer_0_task_fromL2pft = 1'h0;
+        buffer_0_task_needHint = 1'h0;
+        buffer_0_task_reqSource = 5'h0;
+        buffer_0_waitMP = 4'h0;
+        buffer_0_waitMS = 16'h0;
+        buffer_1_valid = 1'h0;
+        buffer_1_rdy = 1'h0;
+        buffer_1_task_channel = 3'h0;
+        buffer_1_task_set = 8'h0;
+        buffer_1_task_tag = 34'h0;
+        buffer_1_task_off = 6'h0;
+        buffer_1_task_alias = 1'h0;
+        buffer_1_task_vaddr = 44'h0;
+        buffer_1_task_isKeyword = 1'h0;
+        buffer_1_task_opcode = 4'h0;
+        buffer_1_task_param = 3'h0;
+        buffer_1_task_size = 3'h0;
+        buffer_1_task_sourceId = 7'h0;
+        buffer_1_task_corrupt = 1'h0;
+        buffer_1_task_fromL2pft = 1'h0;
+        buffer_1_task_needHint = 1'h0;
+        buffer_1_task_reqSource = 5'h0;
+        buffer_1_waitMP = 4'h0;
+        buffer_1_waitMS = 16'h0;
+        buffer_2_valid = 1'h0;
+        buffer_2_rdy = 1'h0;
+        buffer_2_task_channel = 3'h0;
+        buffer_2_task_set = 8'h0;
+        buffer_2_task_tag = 34'h0;
+        buffer_2_task_off = 6'h0;
+        buffer_2_task_alias = 1'h0;
+        buffer_2_task_vaddr = 44'h0;
+        buffer_2_task_isKeyword = 1'h0;
+        buffer_2_task_opcode = 4'h0;
+        buffer_2_task_param = 3'h0;
+        buffer_2_task_size = 3'h0;
+        buffer_2_task_sourceId = 7'h0;
+        buffer_2_task_corrupt = 1'h0;
+        buffer_2_task_fromL2pft = 1'h0;
+        buffer_2_task_needHint = 1'h0;
+        buffer_2_task_reqSource = 5'h0;
+        buffer_2_waitMP = 4'h0;
+        buffer_2_waitMS = 16'h0;
+        buffer_3_valid = 1'h0;
+        buffer_3_rdy = 1'h0;
+        buffer_3_task_channel = 3'h0;
+        buffer_3_task_set = 8'h0;
+        buffer_3_task_tag = 34'h0;
+        buffer_3_task_off = 6'h0;
+        buffer_3_task_alias = 1'h0;
+        buffer_3_task_vaddr = 44'h0;
+        buffer_3_task_isKeyword = 1'h0;
+        buffer_3_task_opcode = 4'h0;
+        buffer_3_task_param = 3'h0;
+        buffer_3_task_size = 3'h0;
+        buffer_3_task_sourceId = 7'h0;
+        buffer_3_task_corrupt = 1'h0;
+        buffer_3_task_fromL2pft = 1'h0;
+        buffer_3_task_needHint = 1'h0;
+        buffer_3_task_reqSource = 5'h0;
+        buffer_3_waitMP = 4'h0;
+        buffer_3_waitMS = 16'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  TwoLevelRRArbiter_5 issueArb (
+    .clock                       (clock),
+    .reset                       (reset),
+    .io_in_0_valid               (buffer_0_valid & buffer_0_rdy),
+    .io_in_0_bits_valid          (buffer_0_valid),
+    .io_in_0_bits_rdy            (buffer_0_rdy),
+    .io_in_0_bits_task_channel   (buffer_0_task_channel),
+    .io_in_0_bits_task_set       (buffer_0_task_set),
+    .io_in_0_bits_task_tag       (buffer_0_task_tag),
+    .io_in_0_bits_task_off       (buffer_0_task_off),
+    .io_in_0_bits_task_alias     (buffer_0_task_alias),
+    .io_in_0_bits_task_vaddr     (buffer_0_task_vaddr),
+    .io_in_0_bits_task_isKeyword (buffer_0_task_isKeyword),
+    .io_in_0_bits_task_opcode    (buffer_0_task_opcode),
+    .io_in_0_bits_task_param     (buffer_0_task_param),
+    .io_in_0_bits_task_size      (buffer_0_task_size),
+    .io_in_0_bits_task_sourceId  (buffer_0_task_sourceId),
+    .io_in_0_bits_task_corrupt   (buffer_0_task_corrupt),
+    .io_in_0_bits_task_fromL2pft (buffer_0_task_fromL2pft),
+    .io_in_0_bits_task_needHint  (buffer_0_task_needHint),
+    .io_in_0_bits_task_reqSource (buffer_0_task_reqSource),
+    .io_in_0_bits_waitMP         (buffer_0_waitMP),
+    .io_in_0_bits_waitMS         (buffer_0_waitMS),
+    .io_in_1_valid               (buffer_1_valid & buffer_1_rdy),
+    .io_in_1_bits_valid          (buffer_1_valid),
+    .io_in_1_bits_rdy            (buffer_1_rdy),
+    .io_in_1_bits_task_channel   (buffer_1_task_channel),
+    .io_in_1_bits_task_set       (buffer_1_task_set),
+    .io_in_1_bits_task_tag       (buffer_1_task_tag),
+    .io_in_1_bits_task_off       (buffer_1_task_off),
+    .io_in_1_bits_task_alias     (buffer_1_task_alias),
+    .io_in_1_bits_task_vaddr     (buffer_1_task_vaddr),
+    .io_in_1_bits_task_isKeyword (buffer_1_task_isKeyword),
+    .io_in_1_bits_task_opcode    (buffer_1_task_opcode),
+    .io_in_1_bits_task_param     (buffer_1_task_param),
+    .io_in_1_bits_task_size      (buffer_1_task_size),
+    .io_in_1_bits_task_sourceId  (buffer_1_task_sourceId),
+    .io_in_1_bits_task_corrupt   (buffer_1_task_corrupt),
+    .io_in_1_bits_task_fromL2pft (buffer_1_task_fromL2pft),
+    .io_in_1_bits_task_needHint  (buffer_1_task_needHint),
+    .io_in_1_bits_task_reqSource (buffer_1_task_reqSource),
+    .io_in_1_bits_waitMP         (buffer_1_waitMP),
+    .io_in_1_bits_waitMS         (buffer_1_waitMS),
+    .io_in_2_valid               (buffer_2_valid & buffer_2_rdy),
+    .io_in_2_bits_valid          (buffer_2_valid),
+    .io_in_2_bits_rdy            (buffer_2_rdy),
+    .io_in_2_bits_task_channel   (buffer_2_task_channel),
+    .io_in_2_bits_task_set       (buffer_2_task_set),
+    .io_in_2_bits_task_tag       (buffer_2_task_tag),
+    .io_in_2_bits_task_off       (buffer_2_task_off),
+    .io_in_2_bits_task_alias     (buffer_2_task_alias),
+    .io_in_2_bits_task_vaddr     (buffer_2_task_vaddr),
+    .io_in_2_bits_task_isKeyword (buffer_2_task_isKeyword),
+    .io_in_2_bits_task_opcode    (buffer_2_task_opcode),
+    .io_in_2_bits_task_param     (buffer_2_task_param),
+    .io_in_2_bits_task_size      (buffer_2_task_size),
+    .io_in_2_bits_task_sourceId  (buffer_2_task_sourceId),
+    .io_in_2_bits_task_corrupt   (buffer_2_task_corrupt),
+    .io_in_2_bits_task_fromL2pft (buffer_2_task_fromL2pft),
+    .io_in_2_bits_task_needHint  (buffer_2_task_needHint),
+    .io_in_2_bits_task_reqSource (buffer_2_task_reqSource),
+    .io_in_2_bits_waitMP         (buffer_2_waitMP),
+    .io_in_2_bits_waitMS         (buffer_2_waitMS),
+    .io_in_3_valid               (buffer_3_valid & buffer_3_rdy),
+    .io_in_3_bits_valid          (buffer_3_valid),
+    .io_in_3_bits_rdy            (buffer_3_rdy),
+    .io_in_3_bits_task_channel   (buffer_3_task_channel),
+    .io_in_3_bits_task_set       (buffer_3_task_set),
+    .io_in_3_bits_task_tag       (buffer_3_task_tag),
+    .io_in_3_bits_task_off       (buffer_3_task_off),
+    .io_in_3_bits_task_alias     (buffer_3_task_alias),
+    .io_in_3_bits_task_vaddr     (buffer_3_task_vaddr),
+    .io_in_3_bits_task_isKeyword (buffer_3_task_isKeyword),
+    .io_in_3_bits_task_opcode    (buffer_3_task_opcode),
+    .io_in_3_bits_task_param     (buffer_3_task_param),
+    .io_in_3_bits_task_size      (buffer_3_task_size),
+    .io_in_3_bits_task_sourceId  (buffer_3_task_sourceId),
+    .io_in_3_bits_task_corrupt   (buffer_3_task_corrupt),
+    .io_in_3_bits_task_fromL2pft (buffer_3_task_fromL2pft),
+    .io_in_3_bits_task_needHint  (buffer_3_task_needHint),
+    .io_in_3_bits_task_reqSource (buffer_3_task_reqSource),
+    .io_in_3_bits_waitMP         (buffer_3_waitMP),
+    .io_in_3_bits_waitMS         (buffer_3_waitMS),
+    .io_out_ready                (_chosenQ_io_enq_ready),
+    .io_out_valid                (_issueArb_io_out_valid),
+    .io_out_bits_valid           (_issueArb_io_out_bits_valid),
+    .io_out_bits_rdy             (_issueArb_io_out_bits_rdy),
+    .io_out_bits_task_channel    (_issueArb_io_out_bits_task_channel),
+    .io_out_bits_task_set        (_issueArb_io_out_bits_task_set),
+    .io_out_bits_task_tag        (_issueArb_io_out_bits_task_tag),
+    .io_out_bits_task_off        (_issueArb_io_out_bits_task_off),
+    .io_out_bits_task_alias      (_issueArb_io_out_bits_task_alias),
+    .io_out_bits_task_vaddr      (_issueArb_io_out_bits_task_vaddr),
+    .io_out_bits_task_isKeyword  (_issueArb_io_out_bits_task_isKeyword),
+    .io_out_bits_task_opcode     (_issueArb_io_out_bits_task_opcode),
+    .io_out_bits_task_param      (_issueArb_io_out_bits_task_param),
+    .io_out_bits_task_size       (_issueArb_io_out_bits_task_size),
+    .io_out_bits_task_sourceId   (_issueArb_io_out_bits_task_sourceId),
+    .io_out_bits_task_corrupt    (_issueArb_io_out_bits_task_corrupt),
+    .io_out_bits_task_fromL2pft  (_issueArb_io_out_bits_task_fromL2pft),
+    .io_out_bits_task_needHint   (_issueArb_io_out_bits_task_needHint),
+    .io_out_bits_task_reqSource  (_issueArb_io_out_bits_task_reqSource),
+    .io_out_bits_waitMP          (_issueArb_io_out_bits_waitMP),
+    .io_out_bits_waitMS          (_issueArb_io_out_bits_waitMS),
+    .io_chosenOH                 (_issueArb_io_chosenOH)
+  );
+  Queue1_ChosenQBundle chosenQ (
+    .clock                                               (clock),
+    .reset                                               (reset),
+    .io_enq_ready                                        (_chosenQ_io_enq_ready),
+    .io_enq_valid                                        (_issueArb_io_out_valid),
+    .io_enq_bits_bits_valid                              (_issueArb_io_out_bits_valid),
+    .io_enq_bits_bits_rdy                                (_issueArb_io_out_bits_rdy),
+    .io_enq_bits_bits_task_channel
+      (_issueArb_io_out_bits_task_channel),
+    .io_enq_bits_bits_task_set                           (_issueArb_io_out_bits_task_set),
+    .io_enq_bits_bits_task_tag                           (_issueArb_io_out_bits_task_tag),
+    .io_enq_bits_bits_task_off                           (_issueArb_io_out_bits_task_off),
+    .io_enq_bits_bits_task_alias
+      (_issueArb_io_out_bits_task_alias),
+    .io_enq_bits_bits_task_vaddr
+      (_issueArb_io_out_bits_task_vaddr),
+    .io_enq_bits_bits_task_isKeyword
+      (_issueArb_io_out_bits_task_isKeyword),
+    .io_enq_bits_bits_task_opcode
+      (_issueArb_io_out_bits_task_opcode),
+    .io_enq_bits_bits_task_param
+      (_issueArb_io_out_bits_task_param),
+    .io_enq_bits_bits_task_size
+      (_issueArb_io_out_bits_task_size),
+    .io_enq_bits_bits_task_sourceId
+      (_issueArb_io_out_bits_task_sourceId),
+    .io_enq_bits_bits_task_corrupt
+      (_issueArb_io_out_bits_task_corrupt),
+    .io_enq_bits_bits_task_fromL2pft
+      (_issueArb_io_out_bits_task_fromL2pft),
+    .io_enq_bits_bits_task_needHint
+      (_issueArb_io_out_bits_task_needHint),
+    .io_enq_bits_bits_task_reqSource
+      (_issueArb_io_out_bits_task_reqSource),
+    .io_enq_bits_bits_waitMP                             (_issueArb_io_out_bits_waitMP),
+    .io_enq_bits_bits_waitMS                             (_issueArb_io_out_bits_waitMS),
+    .io_enq_bits_idOH                                    (_issueArb_io_chosenOH),
+    .io_deq_ready                                        (chosenQ_io_deq_ready),
+    .io_deq_valid                                        (_chosenQ_io_deq_valid),
+    .io_deq_bits_bits_task_channel
+      (_chosenQ_io_deq_bits_bits_task_channel),
+    .io_deq_bits_bits_task_txChannel
+      (_chosenQ_io_deq_bits_bits_task_txChannel),
+    .io_deq_bits_bits_task_set
+      (_chosenQ_io_deq_bits_bits_task_set),
+    .io_deq_bits_bits_task_tag
+      (_chosenQ_io_deq_bits_bits_task_tag),
+    .io_deq_bits_bits_task_off
+      (_chosenQ_io_deq_bits_bits_task_off),
+    .io_deq_bits_bits_task_alias
+      (_chosenQ_io_deq_bits_bits_task_alias),
+    .io_deq_bits_bits_task_vaddr
+      (_chosenQ_io_deq_bits_bits_task_vaddr),
+    .io_deq_bits_bits_task_isKeyword
+      (_chosenQ_io_deq_bits_bits_task_isKeyword),
+    .io_deq_bits_bits_task_opcode
+      (_chosenQ_io_deq_bits_bits_task_opcode),
+    .io_deq_bits_bits_task_param
+      (_chosenQ_io_deq_bits_bits_task_param),
+    .io_deq_bits_bits_task_size
+      (_chosenQ_io_deq_bits_bits_task_size),
+    .io_deq_bits_bits_task_sourceId
+      (_chosenQ_io_deq_bits_bits_task_sourceId),
+    .io_deq_bits_bits_task_bufIdx
+      (_chosenQ_io_deq_bits_bits_task_bufIdx),
+    .io_deq_bits_bits_task_needProbeAckData
+      (_chosenQ_io_deq_bits_bits_task_needProbeAckData),
+    .io_deq_bits_bits_task_denied
+      (_chosenQ_io_deq_bits_bits_task_denied),
+    .io_deq_bits_bits_task_corrupt
+      (_chosenQ_io_deq_bits_bits_task_corrupt),
+    .io_deq_bits_bits_task_mshrTask
+      (_chosenQ_io_deq_bits_bits_task_mshrTask),
+    .io_deq_bits_bits_task_mshrId
+      (_chosenQ_io_deq_bits_bits_task_mshrId),
+    .io_deq_bits_bits_task_aliasTask
+      (_chosenQ_io_deq_bits_bits_task_aliasTask),
+    .io_deq_bits_bits_task_useProbeData
+      (_chosenQ_io_deq_bits_bits_task_useProbeData),
+    .io_deq_bits_bits_task_mshrRetry
+      (_chosenQ_io_deq_bits_bits_task_mshrRetry),
+    .io_deq_bits_bits_task_readProbeDataDown
+      (_chosenQ_io_deq_bits_bits_task_readProbeDataDown),
+    .io_deq_bits_bits_task_fromL2pft
+      (_chosenQ_io_deq_bits_bits_task_fromL2pft),
+    .io_deq_bits_bits_task_needHint
+      (_chosenQ_io_deq_bits_bits_task_needHint),
+    .io_deq_bits_bits_task_dirty
+      (_chosenQ_io_deq_bits_bits_task_dirty),
+    .io_deq_bits_bits_task_way
+      (_chosenQ_io_deq_bits_bits_task_way),
+    .io_deq_bits_bits_task_meta_dirty
+      (_chosenQ_io_deq_bits_bits_task_meta_dirty),
+    .io_deq_bits_bits_task_meta_state
+      (_chosenQ_io_deq_bits_bits_task_meta_state),
+    .io_deq_bits_bits_task_meta_clients
+      (_chosenQ_io_deq_bits_bits_task_meta_clients),
+    .io_deq_bits_bits_task_meta_alias
+      (_chosenQ_io_deq_bits_bits_task_meta_alias),
+    .io_deq_bits_bits_task_meta_prefetch
+      (_chosenQ_io_deq_bits_bits_task_meta_prefetch),
+    .io_deq_bits_bits_task_meta_prefetchSrc
+      (_chosenQ_io_deq_bits_bits_task_meta_prefetchSrc),
+    .io_deq_bits_bits_task_meta_accessed
+      (_chosenQ_io_deq_bits_bits_task_meta_accessed),
+    .io_deq_bits_bits_task_meta_tagErr
+      (_chosenQ_io_deq_bits_bits_task_meta_tagErr),
+    .io_deq_bits_bits_task_meta_dataErr
+      (_chosenQ_io_deq_bits_bits_task_meta_dataErr),
+    .io_deq_bits_bits_task_metaWen
+      (_chosenQ_io_deq_bits_bits_task_metaWen),
+    .io_deq_bits_bits_task_tagWen
+      (_chosenQ_io_deq_bits_bits_task_tagWen),
+    .io_deq_bits_bits_task_dsWen
+      (_chosenQ_io_deq_bits_bits_task_dsWen),
+    .io_deq_bits_bits_task_replTask
+      (_chosenQ_io_deq_bits_bits_task_replTask),
+    .io_deq_bits_bits_task_cmoTask
+      (_chosenQ_io_deq_bits_bits_task_cmoTask),
+    .io_deq_bits_bits_task_cmoAll
+      (_chosenQ_io_deq_bits_bits_task_cmoAll),
+    .io_deq_bits_bits_task_reqSource
+      (_chosenQ_io_deq_bits_bits_task_reqSource),
+    .io_deq_bits_bits_task_mergeA
+      (_chosenQ_io_deq_bits_bits_task_mergeA),
+    .io_deq_bits_bits_task_aMergeTask_off
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_off),
+    .io_deq_bits_bits_task_aMergeTask_alias
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_alias),
+    .io_deq_bits_bits_task_aMergeTask_vaddr
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_vaddr),
+    .io_deq_bits_bits_task_aMergeTask_isKeyword
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_isKeyword),
+    .io_deq_bits_bits_task_aMergeTask_opcode
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_opcode),
+    .io_deq_bits_bits_task_aMergeTask_param
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_param),
+    .io_deq_bits_bits_task_aMergeTask_sourceId
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_sourceId),
+    .io_deq_bits_bits_task_aMergeTask_meta_dirty
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_meta_dirty),
+    .io_deq_bits_bits_task_aMergeTask_meta_state
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_meta_state),
+    .io_deq_bits_bits_task_aMergeTask_meta_clients
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_meta_clients),
+    .io_deq_bits_bits_task_aMergeTask_meta_alias
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_meta_alias),
+    .io_deq_bits_bits_task_aMergeTask_meta_prefetch
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_meta_prefetch),
+    .io_deq_bits_bits_task_aMergeTask_meta_prefetchSrc
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_meta_prefetchSrc),
+    .io_deq_bits_bits_task_aMergeTask_meta_accessed
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_meta_accessed),
+    .io_deq_bits_bits_task_aMergeTask_meta_tagErr
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_meta_tagErr),
+    .io_deq_bits_bits_task_aMergeTask_meta_dataErr
+      (_chosenQ_io_deq_bits_bits_task_aMergeTask_meta_dataErr),
+    .io_deq_bits_bits_task_snpHitRelease
+      (_chosenQ_io_deq_bits_bits_task_snpHitRelease),
+    .io_deq_bits_bits_task_snpHitReleaseToInval
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseToInval),
+    .io_deq_bits_bits_task_snpHitReleaseToClean
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseToClean),
+    .io_deq_bits_bits_task_snpHitReleaseWithData
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseWithData),
+    .io_deq_bits_bits_task_snpHitReleaseIdx
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseIdx),
+    .io_deq_bits_bits_task_snpHitReleaseMeta_dirty
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_dirty),
+    .io_deq_bits_bits_task_snpHitReleaseMeta_state
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_state),
+    .io_deq_bits_bits_task_snpHitReleaseMeta_clients
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_clients),
+    .io_deq_bits_bits_task_snpHitReleaseMeta_alias
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_alias),
+    .io_deq_bits_bits_task_snpHitReleaseMeta_prefetch
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_prefetch),
+    .io_deq_bits_bits_task_snpHitReleaseMeta_prefetchSrc
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_deq_bits_bits_task_snpHitReleaseMeta_accessed
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_accessed),
+    .io_deq_bits_bits_task_snpHitReleaseMeta_tagErr
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_tagErr),
+    .io_deq_bits_bits_task_snpHitReleaseMeta_dataErr
+      (_chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_dataErr),
+    .io_deq_bits_bits_task_tgtID
+      (_chosenQ_io_deq_bits_bits_task_tgtID),
+    .io_deq_bits_bits_task_srcID
+      (_chosenQ_io_deq_bits_bits_task_srcID),
+    .io_deq_bits_bits_task_txnID
+      (_chosenQ_io_deq_bits_bits_task_txnID),
+    .io_deq_bits_bits_task_homeNID
+      (_chosenQ_io_deq_bits_bits_task_homeNID),
+    .io_deq_bits_bits_task_dbID
+      (_chosenQ_io_deq_bits_bits_task_dbID),
+    .io_deq_bits_bits_task_fwdNID
+      (_chosenQ_io_deq_bits_bits_task_fwdNID),
+    .io_deq_bits_bits_task_fwdTxnID
+      (_chosenQ_io_deq_bits_bits_task_fwdTxnID),
+    .io_deq_bits_bits_task_chiOpcode
+      (_chosenQ_io_deq_bits_bits_task_chiOpcode),
+    .io_deq_bits_bits_task_resp
+      (_chosenQ_io_deq_bits_bits_task_resp),
+    .io_deq_bits_bits_task_fwdState
+      (_chosenQ_io_deq_bits_bits_task_fwdState),
+    .io_deq_bits_bits_task_pCrdType
+      (_chosenQ_io_deq_bits_bits_task_pCrdType),
+    .io_deq_bits_bits_task_retToSrc
+      (_chosenQ_io_deq_bits_bits_task_retToSrc),
+    .io_deq_bits_bits_task_likelyshared
+      (_chosenQ_io_deq_bits_bits_task_likelyshared),
+    .io_deq_bits_bits_task_expCompAck
+      (_chosenQ_io_deq_bits_bits_task_expCompAck),
+    .io_deq_bits_bits_task_allowRetry
+      (_chosenQ_io_deq_bits_bits_task_allowRetry),
+    .io_deq_bits_bits_task_memAttr_allocate
+      (_chosenQ_io_deq_bits_bits_task_memAttr_allocate),
+    .io_deq_bits_bits_task_memAttr_cacheable
+      (_chosenQ_io_deq_bits_bits_task_memAttr_cacheable),
+    .io_deq_bits_bits_task_memAttr_device
+      (_chosenQ_io_deq_bits_bits_task_memAttr_device),
+    .io_deq_bits_bits_task_memAttr_ewa
+      (_chosenQ_io_deq_bits_bits_task_memAttr_ewa),
+    .io_deq_bits_bits_task_traceTag
+      (_chosenQ_io_deq_bits_bits_task_traceTag),
+    .io_deq_bits_idOH                                    (_chosenQ_io_deq_bits_idOH)
+  );
+  assign io_in_ready =
+    (|{_alloc_T | doFlow,
+       _mergeAMask_WIRE_15,
+       _mergeAMask_WIRE_14,
+       _mergeAMask_WIRE_13,
+       _mergeAMask_WIRE_12,
+       _mergeAMask_WIRE_11,
+       _mergeAMask_WIRE_10,
+       _mergeAMask_WIRE_9,
+       _mergeAMask_WIRE_8,
+       _mergeAMask_WIRE_7,
+       _mergeAMask_WIRE_6,
+       _mergeAMask_WIRE_5,
+       _mergeAMask_WIRE_4,
+       _mergeAMask_WIRE_3,
+       _mergeAMask_WIRE_2,
+       _mergeAMask_WIRE_1,
+       _mergeAMask_WIRE_0}) | dup;
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_channel =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_channel : 3'h1;
+  assign io_out_bits_txChannel =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_txChannel : 3'h0;
+  assign io_out_bits_set = io_out_bits_set_0;
+  assign io_out_bits_tag =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_tag : io_in_bits_tag;
+  assign io_out_bits_off =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_off : io_in_bits_off;
+  assign io_out_bits_alias =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_alias : io_in_bits_alias;
+  assign io_out_bits_vaddr =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_vaddr : io_in_bits_vaddr;
+  assign io_out_bits_isKeyword =
+    _chosenQ_io_deq_valid
+      ? _chosenQ_io_deq_bits_bits_task_isKeyword
+      : io_in_bits_isKeyword;
+  assign io_out_bits_opcode =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_opcode : io_in_bits_opcode;
+  assign io_out_bits_param =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_param : io_in_bits_param;
+  assign io_out_bits_size =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_size : io_in_bits_size;
+  assign io_out_bits_sourceId =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_sourceId : io_in_bits_sourceId;
+  assign io_out_bits_bufIdx =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_bufIdx : 2'h0;
+  assign io_out_bits_needProbeAckData =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_needProbeAckData;
+  assign io_out_bits_denied =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_denied;
+  assign io_out_bits_corrupt =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_corrupt : io_in_bits_corrupt;
+  assign io_out_bits_mshrTask =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_mshrTask;
+  assign io_out_bits_mshrId =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_mshrId : 8'h0;
+  assign io_out_bits_aliasTask =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aliasTask;
+  assign io_out_bits_useProbeData =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_useProbeData;
+  assign io_out_bits_mshrRetry =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_mshrRetry;
+  assign io_out_bits_readProbeDataDown =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_readProbeDataDown;
+  assign io_out_bits_fromL2pft =
+    _chosenQ_io_deq_valid
+      ? _chosenQ_io_deq_bits_bits_task_fromL2pft
+      : io_in_bits_fromL2pft;
+  assign io_out_bits_needHint =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_needHint : io_in_bits_needHint;
+  assign io_out_bits_dirty = _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_dirty;
+  assign io_out_bits_way =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_way : 3'h0;
+  assign io_out_bits_meta_dirty =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_meta_dirty;
+  assign io_out_bits_meta_state =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_meta_state : 2'h0;
+  assign io_out_bits_meta_clients =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_meta_clients;
+  assign io_out_bits_meta_alias =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_meta_alias;
+  assign io_out_bits_meta_prefetch =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_meta_prefetch;
+  assign io_out_bits_meta_prefetchSrc =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_meta_prefetchSrc : 4'h0;
+  assign io_out_bits_meta_accessed =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_meta_accessed;
+  assign io_out_bits_meta_tagErr =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_meta_tagErr;
+  assign io_out_bits_meta_dataErr =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_meta_dataErr;
+  assign io_out_bits_metaWen =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_metaWen;
+  assign io_out_bits_tagWen =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_tagWen;
+  assign io_out_bits_dsWen = _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_dsWen;
+  assign io_out_bits_replTask =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_replTask;
+  assign io_out_bits_cmoTask =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_cmoTask;
+  assign io_out_bits_cmoAll =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_cmoAll;
+  assign io_out_bits_reqSource =
+    _chosenQ_io_deq_valid
+      ? _chosenQ_io_deq_bits_bits_task_reqSource
+      : io_in_bits_reqSource;
+  assign io_out_bits_mergeA =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_mergeA;
+  assign io_out_bits_aMergeTask_off =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_aMergeTask_off : 6'h0;
+  assign io_out_bits_aMergeTask_alias =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aMergeTask_alias;
+  assign io_out_bits_aMergeTask_vaddr =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_aMergeTask_vaddr : 44'h0;
+  assign io_out_bits_aMergeTask_isKeyword =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aMergeTask_isKeyword;
+  assign io_out_bits_aMergeTask_opcode =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_aMergeTask_opcode : 3'h0;
+  assign io_out_bits_aMergeTask_param =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_aMergeTask_param : 3'h0;
+  assign io_out_bits_aMergeTask_sourceId =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_aMergeTask_sourceId : 7'h0;
+  assign io_out_bits_aMergeTask_meta_dirty =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_dirty;
+  assign io_out_bits_aMergeTask_meta_state =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_state : 2'h0;
+  assign io_out_bits_aMergeTask_meta_clients =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_clients;
+  assign io_out_bits_aMergeTask_meta_alias =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_alias;
+  assign io_out_bits_aMergeTask_meta_prefetch =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_prefetch;
+  assign io_out_bits_aMergeTask_meta_prefetchSrc =
+    _chosenQ_io_deq_valid
+      ? _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_prefetchSrc
+      : 4'h0;
+  assign io_out_bits_aMergeTask_meta_accessed =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_accessed;
+  assign io_out_bits_aMergeTask_meta_tagErr =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_tagErr;
+  assign io_out_bits_aMergeTask_meta_dataErr =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_aMergeTask_meta_dataErr;
+  assign io_out_bits_snpHitRelease =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitRelease;
+  assign io_out_bits_snpHitReleaseToInval =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseToInval;
+  assign io_out_bits_snpHitReleaseToClean =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseToClean;
+  assign io_out_bits_snpHitReleaseWithData =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseWithData;
+  assign io_out_bits_snpHitReleaseIdx =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_snpHitReleaseIdx : 8'h0;
+  assign io_out_bits_snpHitReleaseMeta_dirty =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_dirty;
+  assign io_out_bits_snpHitReleaseMeta_state =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_state : 2'h0;
+  assign io_out_bits_snpHitReleaseMeta_clients =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_clients;
+  assign io_out_bits_snpHitReleaseMeta_alias =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_alias;
+  assign io_out_bits_snpHitReleaseMeta_prefetch =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_prefetch;
+  assign io_out_bits_snpHitReleaseMeta_prefetchSrc =
+    _chosenQ_io_deq_valid
+      ? _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_prefetchSrc
+      : 4'h0;
+  assign io_out_bits_snpHitReleaseMeta_accessed =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_accessed;
+  assign io_out_bits_snpHitReleaseMeta_tagErr =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_tagErr;
+  assign io_out_bits_snpHitReleaseMeta_dataErr =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_snpHitReleaseMeta_dataErr;
+  assign io_out_bits_tgtID =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_tgtID : 11'h0;
+  assign io_out_bits_srcID =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_srcID : 11'h0;
+  assign io_out_bits_txnID =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_txnID : 12'h0;
+  assign io_out_bits_homeNID =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_homeNID : 11'h0;
+  assign io_out_bits_dbID =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_dbID : 12'h0;
+  assign io_out_bits_fwdNID =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_fwdNID : 11'h0;
+  assign io_out_bits_fwdTxnID =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_fwdTxnID : 12'h0;
+  assign io_out_bits_chiOpcode =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_chiOpcode : 7'h0;
+  assign io_out_bits_resp =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_resp : 3'h0;
+  assign io_out_bits_fwdState =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_fwdState : 3'h0;
+  assign io_out_bits_pCrdType =
+    _chosenQ_io_deq_valid ? _chosenQ_io_deq_bits_bits_task_pCrdType : 4'h0;
+  assign io_out_bits_retToSrc =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_retToSrc;
+  assign io_out_bits_likelyshared =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_likelyshared;
+  assign io_out_bits_expCompAck =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_expCompAck;
+  assign io_out_bits_allowRetry =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_allowRetry;
+  assign io_out_bits_memAttr_allocate =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_memAttr_cacheable;
+  assign io_out_bits_memAttr_device =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_memAttr_device;
+  assign io_out_bits_memAttr_ewa =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_memAttr_ewa;
+  assign io_out_bits_traceTag =
+    _chosenQ_io_deq_valid & _chosenQ_io_deq_bits_bits_task_traceTag;
+  assign io_aMergeTask_valid = io_in_valid & (|mergeAMask);
+  assign io_aMergeTask_bits_idOH = mergeAMask;
+  assign io_aMergeTask_bits_task_off = io_in_bits_off;
+  assign io_aMergeTask_bits_task_alias = io_in_bits_alias;
+  assign io_aMergeTask_bits_task_vaddr = io_in_bits_vaddr;
+  assign io_aMergeTask_bits_task_isKeyword = io_in_bits_isKeyword;
+  assign io_aMergeTask_bits_task_opcode = io_in_bits_opcode;
+  assign io_aMergeTask_bits_task_param = io_in_bits_param;
+  assign io_aMergeTask_bits_task_sourceId = io_in_bits_sourceId;
+  assign io_ATag = io_in_bits_tag;
+  assign io_ASet = io_in_bits_set;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_239.sv b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_239.sv
new file mode 100644
index 0000000000..69c6cab22d
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_239.sv
@@ -0,0 +1,166 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module SRAMTemplate_239(
+  input         clock,
+  input         reset,
+  output        io_r_req_ready,
+  input         io_r_req_valid,
+  input  [7:0]  io_r_req_bits_setIdx,
+  output        io_r_resp_data_0_valid,
+  output [11:0] io_r_resp_data_0_tag,
+  output        io_w_req_ready,
+  input         io_w_req_valid,
+  input  [7:0]  io_w_req_bits_setIdx,
+  input  [11:0] io_w_req_bits_data_0_tag,
+  input         io_broadcast_ram_hold,
+  input         io_broadcast_ram_bypass,
+  input         io_broadcast_ram_bp_clken,
+  input         io_broadcast_ram_aux_clk,
+  input         io_broadcast_ram_aux_ckbp,
+  input         io_broadcast_ram_mcp_hold,
+  input  [63:0] io_broadcast_ram_ctl,
+  input         io_broadcast_cgen,
+  input  [8:0]  boreChildrenBd_bore_addr,
+  input  [8:0]  boreChildrenBd_bore_addr_rd,
+  input  [12:0] boreChildrenBd_bore_wdata,
+  input         boreChildrenBd_bore_wmask,
+  input         boreChildrenBd_bore_re,
+  input         boreChildrenBd_bore_we,
+  output [12:0] boreChildrenBd_bore_rdata,
+  input         boreChildrenBd_bore_ack,
+  input         boreChildrenBd_bore_selectedOH,
+  input         boreChildrenBd_bore_array
+);
+
+  wire        io_r_req_ready_0;
+  wire [12:0] _array_RW0_rdata;
+  wire [8:0]  mbistBd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire [12:0] mbistBd_wdata = boreChildrenBd_bore_wdata;
+  wire        mbistBd_re = boreChildrenBd_bore_re;
+  wire        mbistBd_we = boreChildrenBd_bore_we;
+  wire        mbistBd_ack = boreChildrenBd_bore_ack;
+  wire        mbistWmask = boreChildrenBd_bore_selectedOH;
+  wire [8:0]  mbistBd_addr = boreChildrenBd_bore_addr;
+  wire        mbistBd_wmask = boreChildrenBd_bore_wmask;
+  wire        mbistBd_array = boreChildrenBd_bore_array;
+  reg         _resetState;
+  reg  [7:0]  _resetSet;
+  wire        rckEn = mbistBd_ack ? mbistBd_re : io_r_req_ready_0 & io_r_req_valid;
+  wire        finalRamWen =
+    (mbistBd_ack ? mbistBd_we : io_w_req_valid | _resetState) & ~io_broadcast_ram_hold;
+  reg         respReg;
+  reg  [12:0] rdataReg;
+  wire [12:0] mbistBd_rdata = rdataReg;
+  assign io_r_req_ready_0 = ~_resetState & ~io_w_req_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _resetState <= 1'h1;
+      _resetSet <= 8'h0;
+      respReg <= 1'h0;
+    end
+    else begin
+      _resetState <= ~(_resetState & (&_resetSet)) & _resetState;
+      if (_resetState)
+        _resetSet <= 8'(_resetSet + 8'h1);
+      respReg <= rckEn;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (respReg)
+      rdataReg <= _array_RW0_rdata;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:3];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
+          _RANDOM[i[1:0]] = `RANDOM;
+        end
+        _resetState = _RANDOM[2'h0][0];
+        _resetSet = _RANDOM[2'h0][8:1];
+        respReg = _RANDOM[2'h1][8];
+        rdataReg = _RANDOM[2'h3][21:9];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        _resetState = 1'h1;
+        _resetSet = 8'h0;
+        respReg = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  sram_array_1p256x13m13s1h0l1b_l2_pftch_rrt array (
+    .mbist_dft_ram_bypass   (io_broadcast_ram_bypass),
+    .mbist_dft_ram_bp_clken (io_broadcast_ram_bp_clken),
+    .RW0_clk                (clock),
+    .RW0_addr
+      (mbistBd_ack
+         ? mbistBd_addr_rd[7:0]
+         : finalRamWen
+             ? (_resetState ? _resetSet : io_w_req_bits_setIdx)
+             : io_r_req_bits_setIdx),
+    .RW0_en                 (finalRamWen | rckEn),
+    .RW0_wmode              (finalRamWen),
+    .RW0_wdata
+      (mbistBd_ack
+         ? mbistBd_wdata
+         : _resetState ? 13'h0 : {1'h1, io_w_req_bits_data_0_tag}),
+    .RW0_rdata              (_array_RW0_rdata)
+  );
+  assign io_r_req_ready = io_r_req_ready_0;
+  assign io_r_resp_data_0_valid = _array_RW0_rdata[12];
+  assign io_r_resp_data_0_tag = _array_RW0_rdata[11:0];
+  assign io_w_req_ready = ~_resetState;
+  assign boreChildrenBd_bore_rdata = mbistBd_rdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_241.sv b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_241.sv
new file mode 100644
index 0000000000..25b1b953d6
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_241.sv
@@ -0,0 +1,165 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module SRAMTemplate_241(
+  input          clock,
+  input          reset,
+  output         io_r_req_ready,
+  input          io_r_req_valid,
+  input  [7:0]   io_r_req_bits_setIdx,
+  output [40:0]  io_r_resp_data_0,
+  output [40:0]  io_r_resp_data_1,
+  output [40:0]  io_r_resp_data_2,
+  output [40:0]  io_r_resp_data_3,
+  input          io_w_req_valid,
+  input  [7:0]   io_w_req_bits_setIdx,
+  input  [40:0]  io_w_req_bits_data_0,
+  input  [40:0]  io_w_req_bits_data_1,
+  input  [40:0]  io_w_req_bits_data_2,
+  input  [40:0]  io_w_req_bits_data_3,
+  input  [3:0]   io_w_req_bits_waymask,
+  input          io_broadcast_ram_hold,
+  input          io_broadcast_ram_bypass,
+  input          io_broadcast_ram_bp_clken,
+  input          io_broadcast_ram_aux_clk,
+  input          io_broadcast_ram_aux_ckbp,
+  input          io_broadcast_ram_mcp_hold,
+  input  [63:0]  io_broadcast_ram_ctl,
+  input          io_broadcast_cgen,
+  input  [8:0]   boreChildrenBd_bore_addr,
+  input  [8:0]   boreChildrenBd_bore_addr_rd,
+  input  [163:0] boreChildrenBd_bore_wdata,
+  input  [3:0]   boreChildrenBd_bore_wmask,
+  input          boreChildrenBd_bore_re,
+  input          boreChildrenBd_bore_we,
+  output [163:0] boreChildrenBd_bore_rdata,
+  input          boreChildrenBd_bore_ack,
+  input          boreChildrenBd_bore_selectedOH,
+  input  [1:0]   boreChildrenBd_bore_array
+);
+
+  wire [163:0] _array_RW0_rdata;
+  wire [8:0]   mbistBd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire [163:0] mbistBd_wdata = boreChildrenBd_bore_wdata;
+  wire [3:0]   mbistBd_wmask = boreChildrenBd_bore_wmask;
+  wire         mbistBd_re = boreChildrenBd_bore_re;
+  wire         mbistBd_we = boreChildrenBd_bore_we;
+  wire         mbistBd_ack = boreChildrenBd_bore_ack;
+  wire         mbistBd_selectedOH = boreChildrenBd_bore_selectedOH;
+  wire [8:0]   mbistBd_addr = boreChildrenBd_bore_addr;
+  wire [1:0]   mbistBd_array = boreChildrenBd_bore_array;
+  wire         rckEn = mbistBd_ack ? mbistBd_re : ~io_w_req_valid & io_r_req_valid;
+  wire         finalRamWen =
+    (mbistBd_ack ? mbistBd_we : io_w_req_valid) & ~io_broadcast_ram_hold;
+  reg          respReg;
+  reg  [163:0] rdataReg;
+  wire [163:0] mbistBd_rdata = rdataReg;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      respReg <= 1'h0;
+    else
+      respReg <= rckEn;
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (respReg)
+      rdataReg <= _array_RW0_rdata;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:18];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h13; i += 5'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        respReg = _RANDOM[5'h5][25];
+        rdataReg =
+          {_RANDOM[5'hD][31:26],
+           _RANDOM[5'hE],
+           _RANDOM[5'hF],
+           _RANDOM[5'h10],
+           _RANDOM[5'h11],
+           _RANDOM[5'h12][29:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        respReg = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  sram_array_1p256x164m41s1h0l1b_l2_tag array (
+    .mbist_dft_ram_bypass   (io_broadcast_ram_bypass),
+    .mbist_dft_ram_bp_clken (io_broadcast_ram_bp_clken),
+    .RW0_clk                (clock),
+    .RW0_addr
+      (mbistBd_ack
+         ? mbistBd_addr_rd[7:0]
+         : finalRamWen ? io_w_req_bits_setIdx : io_r_req_bits_setIdx),
+    .RW0_en                 (finalRamWen | rckEn),
+    .RW0_wmode              (finalRamWen),
+    .RW0_wmask
+      (mbistBd_ack ? {4{mbistBd_selectedOH}} & mbistBd_wmask : io_w_req_bits_waymask),
+    .RW0_wdata
+      (mbistBd_ack
+         ? mbistBd_wdata
+         : {io_w_req_bits_data_3,
+            io_w_req_bits_data_2,
+            io_w_req_bits_data_1,
+            io_w_req_bits_data_0}),
+    .RW0_rdata              (_array_RW0_rdata)
+  );
+  assign io_r_req_ready = ~io_w_req_valid;
+  assign io_r_resp_data_0 = _array_RW0_rdata[40:0];
+  assign io_r_resp_data_1 = _array_RW0_rdata[81:41];
+  assign io_r_resp_data_2 = _array_RW0_rdata[122:82];
+  assign io_r_resp_data_3 = _array_RW0_rdata[163:123];
+  assign boreChildrenBd_bore_rdata = mbistBd_rdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_243.sv b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_243.sv
new file mode 100644
index 0000000000..8264524a5b
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_243.sv
@@ -0,0 +1,436 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module SRAMTemplate_243(
+  input          clock,
+  input          reset,
+  output         io_r_req_ready,
+  input          io_r_req_valid,
+  input  [7:0]   io_r_req_bits_setIdx,
+  output         io_r_resp_data_0_dirty,
+  output [1:0]   io_r_resp_data_0_state,
+  output         io_r_resp_data_0_clients,
+  output         io_r_resp_data_0_alias,
+  output         io_r_resp_data_0_prefetch,
+  output [3:0]   io_r_resp_data_0_prefetchSrc,
+  output         io_r_resp_data_0_accessed,
+  output         io_r_resp_data_0_tagErr,
+  output         io_r_resp_data_0_dataErr,
+  output         io_r_resp_data_1_dirty,
+  output [1:0]   io_r_resp_data_1_state,
+  output         io_r_resp_data_1_clients,
+  output         io_r_resp_data_1_alias,
+  output         io_r_resp_data_1_prefetch,
+  output [3:0]   io_r_resp_data_1_prefetchSrc,
+  output         io_r_resp_data_1_accessed,
+  output         io_r_resp_data_1_tagErr,
+  output         io_r_resp_data_1_dataErr,
+  output         io_r_resp_data_2_dirty,
+  output [1:0]   io_r_resp_data_2_state,
+  output         io_r_resp_data_2_clients,
+  output         io_r_resp_data_2_alias,
+  output         io_r_resp_data_2_prefetch,
+  output [3:0]   io_r_resp_data_2_prefetchSrc,
+  output         io_r_resp_data_2_accessed,
+  output         io_r_resp_data_2_tagErr,
+  output         io_r_resp_data_2_dataErr,
+  output         io_r_resp_data_3_dirty,
+  output [1:0]   io_r_resp_data_3_state,
+  output         io_r_resp_data_3_clients,
+  output         io_r_resp_data_3_alias,
+  output         io_r_resp_data_3_prefetch,
+  output [3:0]   io_r_resp_data_3_prefetchSrc,
+  output         io_r_resp_data_3_accessed,
+  output         io_r_resp_data_3_tagErr,
+  output         io_r_resp_data_3_dataErr,
+  output         io_r_resp_data_4_dirty,
+  output [1:0]   io_r_resp_data_4_state,
+  output         io_r_resp_data_4_clients,
+  output         io_r_resp_data_4_alias,
+  output         io_r_resp_data_4_prefetch,
+  output [3:0]   io_r_resp_data_4_prefetchSrc,
+  output         io_r_resp_data_4_accessed,
+  output         io_r_resp_data_4_tagErr,
+  output         io_r_resp_data_4_dataErr,
+  output         io_r_resp_data_5_dirty,
+  output [1:0]   io_r_resp_data_5_state,
+  output         io_r_resp_data_5_clients,
+  output         io_r_resp_data_5_alias,
+  output         io_r_resp_data_5_prefetch,
+  output [3:0]   io_r_resp_data_5_prefetchSrc,
+  output         io_r_resp_data_5_accessed,
+  output         io_r_resp_data_5_tagErr,
+  output         io_r_resp_data_5_dataErr,
+  output         io_r_resp_data_6_dirty,
+  output [1:0]   io_r_resp_data_6_state,
+  output         io_r_resp_data_6_clients,
+  output         io_r_resp_data_6_alias,
+  output         io_r_resp_data_6_prefetch,
+  output [3:0]   io_r_resp_data_6_prefetchSrc,
+  output         io_r_resp_data_6_accessed,
+  output         io_r_resp_data_6_tagErr,
+  output         io_r_resp_data_6_dataErr,
+  output         io_r_resp_data_7_dirty,
+  output [1:0]   io_r_resp_data_7_state,
+  output         io_r_resp_data_7_clients,
+  output         io_r_resp_data_7_alias,
+  output         io_r_resp_data_7_prefetch,
+  output [3:0]   io_r_resp_data_7_prefetchSrc,
+  output         io_r_resp_data_7_accessed,
+  output         io_r_resp_data_7_tagErr,
+  output         io_r_resp_data_7_dataErr,
+  output         io_w_req_ready,
+  input          io_w_req_valid,
+  input  [7:0]   io_w_req_bits_setIdx,
+  input          io_w_req_bits_data_0_dirty,
+  input  [1:0]   io_w_req_bits_data_0_state,
+  input          io_w_req_bits_data_0_clients,
+  input          io_w_req_bits_data_0_alias,
+  input          io_w_req_bits_data_0_prefetch,
+  input  [3:0]   io_w_req_bits_data_0_prefetchSrc,
+  input          io_w_req_bits_data_0_accessed,
+  input          io_w_req_bits_data_0_tagErr,
+  input          io_w_req_bits_data_0_dataErr,
+  input          io_w_req_bits_data_1_dirty,
+  input  [1:0]   io_w_req_bits_data_1_state,
+  input          io_w_req_bits_data_1_clients,
+  input          io_w_req_bits_data_1_alias,
+  input          io_w_req_bits_data_1_prefetch,
+  input  [3:0]   io_w_req_bits_data_1_prefetchSrc,
+  input          io_w_req_bits_data_1_accessed,
+  input          io_w_req_bits_data_1_tagErr,
+  input          io_w_req_bits_data_1_dataErr,
+  input          io_w_req_bits_data_2_dirty,
+  input  [1:0]   io_w_req_bits_data_2_state,
+  input          io_w_req_bits_data_2_clients,
+  input          io_w_req_bits_data_2_alias,
+  input          io_w_req_bits_data_2_prefetch,
+  input  [3:0]   io_w_req_bits_data_2_prefetchSrc,
+  input          io_w_req_bits_data_2_accessed,
+  input          io_w_req_bits_data_2_tagErr,
+  input          io_w_req_bits_data_2_dataErr,
+  input          io_w_req_bits_data_3_dirty,
+  input  [1:0]   io_w_req_bits_data_3_state,
+  input          io_w_req_bits_data_3_clients,
+  input          io_w_req_bits_data_3_alias,
+  input          io_w_req_bits_data_3_prefetch,
+  input  [3:0]   io_w_req_bits_data_3_prefetchSrc,
+  input          io_w_req_bits_data_3_accessed,
+  input          io_w_req_bits_data_3_tagErr,
+  input          io_w_req_bits_data_3_dataErr,
+  input          io_w_req_bits_data_4_dirty,
+  input  [1:0]   io_w_req_bits_data_4_state,
+  input          io_w_req_bits_data_4_clients,
+  input          io_w_req_bits_data_4_alias,
+  input          io_w_req_bits_data_4_prefetch,
+  input  [3:0]   io_w_req_bits_data_4_prefetchSrc,
+  input          io_w_req_bits_data_4_accessed,
+  input          io_w_req_bits_data_4_tagErr,
+  input          io_w_req_bits_data_4_dataErr,
+  input          io_w_req_bits_data_5_dirty,
+  input  [1:0]   io_w_req_bits_data_5_state,
+  input          io_w_req_bits_data_5_clients,
+  input          io_w_req_bits_data_5_alias,
+  input          io_w_req_bits_data_5_prefetch,
+  input  [3:0]   io_w_req_bits_data_5_prefetchSrc,
+  input          io_w_req_bits_data_5_accessed,
+  input          io_w_req_bits_data_5_tagErr,
+  input          io_w_req_bits_data_5_dataErr,
+  input          io_w_req_bits_data_6_dirty,
+  input  [1:0]   io_w_req_bits_data_6_state,
+  input          io_w_req_bits_data_6_clients,
+  input          io_w_req_bits_data_6_alias,
+  input          io_w_req_bits_data_6_prefetch,
+  input  [3:0]   io_w_req_bits_data_6_prefetchSrc,
+  input          io_w_req_bits_data_6_accessed,
+  input          io_w_req_bits_data_6_tagErr,
+  input          io_w_req_bits_data_6_dataErr,
+  input          io_w_req_bits_data_7_dirty,
+  input  [1:0]   io_w_req_bits_data_7_state,
+  input          io_w_req_bits_data_7_clients,
+  input          io_w_req_bits_data_7_alias,
+  input          io_w_req_bits_data_7_prefetch,
+  input  [3:0]   io_w_req_bits_data_7_prefetchSrc,
+  input          io_w_req_bits_data_7_accessed,
+  input          io_w_req_bits_data_7_tagErr,
+  input          io_w_req_bits_data_7_dataErr,
+  input  [7:0]   io_w_req_bits_waymask,
+  input          io_broadcast_ram_hold,
+  input          io_broadcast_ram_bypass,
+  input          io_broadcast_ram_bp_clken,
+  input          io_broadcast_ram_aux_clk,
+  input          io_broadcast_ram_aux_ckbp,
+  input          io_broadcast_ram_mcp_hold,
+  input  [63:0]  io_broadcast_ram_ctl,
+  input          io_broadcast_cgen,
+  output         io_resetDone,
+  input  [8:0]   boreChildrenBd_bore_addr,
+  input  [8:0]   boreChildrenBd_bore_addr_rd,
+  input  [103:0] boreChildrenBd_bore_wdata,
+  input  [7:0]   boreChildrenBd_bore_wmask,
+  input          boreChildrenBd_bore_re,
+  input          boreChildrenBd_bore_we,
+  output [103:0] boreChildrenBd_bore_rdata,
+  input          boreChildrenBd_bore_ack,
+  input          boreChildrenBd_bore_selectedOH,
+  input  [2:0]   boreChildrenBd_bore_array
+);
+
+  wire [103:0] _array_RW0_rdata;
+  wire [8:0]   mbistBd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire [103:0] mbistBd_wdata = boreChildrenBd_bore_wdata;
+  wire [7:0]   mbistBd_wmask = boreChildrenBd_bore_wmask;
+  wire         mbistBd_re = boreChildrenBd_bore_re;
+  wire         mbistBd_we = boreChildrenBd_bore_we;
+  wire         mbistBd_ack = boreChildrenBd_bore_ack;
+  wire         mbistBd_selectedOH = boreChildrenBd_bore_selectedOH;
+  wire [8:0]   mbistBd_addr = boreChildrenBd_bore_addr;
+  wire [2:0]   mbistBd_array = boreChildrenBd_bore_array;
+  wire         rckEn = mbistBd_ack ? mbistBd_re : ~io_w_req_valid & io_r_req_valid;
+  wire         finalRamWen =
+    (mbistBd_ack ? mbistBd_we : io_w_req_valid) & ~io_broadcast_ram_hold;
+  reg          respReg;
+  reg  [103:0] rdataReg;
+  wire [103:0] mbistBd_rdata = rdataReg;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      respReg <= 1'h0;
+    else
+      respReg <= rckEn;
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (respReg)
+      rdataReg <= _array_RW0_rdata;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:23];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h18; i += 5'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        respReg = _RANDOM[5'h4][1];
+        rdataReg =
+          {_RANDOM[5'h14][31:2], _RANDOM[5'h15], _RANDOM[5'h16], _RANDOM[5'h17][9:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        respReg = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  sram_array_1p256x104m13s1h0l1b_l2_meta array (
+    .mbist_dft_ram_bypass   (io_broadcast_ram_bypass),
+    .mbist_dft_ram_bp_clken (io_broadcast_ram_bp_clken),
+    .RW0_clk                (clock),
+    .RW0_addr
+      (mbistBd_ack
+         ? mbistBd_addr_rd[7:0]
+         : finalRamWen ? io_w_req_bits_setIdx : io_r_req_bits_setIdx),
+    .RW0_en                 (finalRamWen | rckEn),
+    .RW0_wmode              (finalRamWen),
+    .RW0_wmask
+      (mbistBd_ack ? {8{mbistBd_selectedOH}} & mbistBd_wmask : io_w_req_bits_waymask),
+    .RW0_wdata
+      (mbistBd_ack
+         ? mbistBd_wdata
+         : {io_w_req_bits_data_7_dirty,
+            io_w_req_bits_data_7_state,
+            io_w_req_bits_data_7_clients,
+            io_w_req_bits_data_7_alias,
+            io_w_req_bits_data_7_prefetch,
+            io_w_req_bits_data_7_prefetchSrc,
+            io_w_req_bits_data_7_accessed,
+            io_w_req_bits_data_7_tagErr,
+            io_w_req_bits_data_7_dataErr,
+            io_w_req_bits_data_6_dirty,
+            io_w_req_bits_data_6_state,
+            io_w_req_bits_data_6_clients,
+            io_w_req_bits_data_6_alias,
+            io_w_req_bits_data_6_prefetch,
+            io_w_req_bits_data_6_prefetchSrc,
+            io_w_req_bits_data_6_accessed,
+            io_w_req_bits_data_6_tagErr,
+            io_w_req_bits_data_6_dataErr,
+            io_w_req_bits_data_5_dirty,
+            io_w_req_bits_data_5_state,
+            io_w_req_bits_data_5_clients,
+            io_w_req_bits_data_5_alias,
+            io_w_req_bits_data_5_prefetch,
+            io_w_req_bits_data_5_prefetchSrc,
+            io_w_req_bits_data_5_accessed,
+            io_w_req_bits_data_5_tagErr,
+            io_w_req_bits_data_5_dataErr,
+            io_w_req_bits_data_4_dirty,
+            io_w_req_bits_data_4_state,
+            io_w_req_bits_data_4_clients,
+            io_w_req_bits_data_4_alias,
+            io_w_req_bits_data_4_prefetch,
+            io_w_req_bits_data_4_prefetchSrc,
+            io_w_req_bits_data_4_accessed,
+            io_w_req_bits_data_4_tagErr,
+            io_w_req_bits_data_4_dataErr,
+            io_w_req_bits_data_3_dirty,
+            io_w_req_bits_data_3_state,
+            io_w_req_bits_data_3_clients,
+            io_w_req_bits_data_3_alias,
+            io_w_req_bits_data_3_prefetch,
+            io_w_req_bits_data_3_prefetchSrc,
+            io_w_req_bits_data_3_accessed,
+            io_w_req_bits_data_3_tagErr,
+            io_w_req_bits_data_3_dataErr,
+            io_w_req_bits_data_2_dirty,
+            io_w_req_bits_data_2_state,
+            io_w_req_bits_data_2_clients,
+            io_w_req_bits_data_2_alias,
+            io_w_req_bits_data_2_prefetch,
+            io_w_req_bits_data_2_prefetchSrc,
+            io_w_req_bits_data_2_accessed,
+            io_w_req_bits_data_2_tagErr,
+            io_w_req_bits_data_2_dataErr,
+            io_w_req_bits_data_1_dirty,
+            io_w_req_bits_data_1_state,
+            io_w_req_bits_data_1_clients,
+            io_w_req_bits_data_1_alias,
+            io_w_req_bits_data_1_prefetch,
+            io_w_req_bits_data_1_prefetchSrc,
+            io_w_req_bits_data_1_accessed,
+            io_w_req_bits_data_1_tagErr,
+            io_w_req_bits_data_1_dataErr,
+            io_w_req_bits_data_0_dirty,
+            io_w_req_bits_data_0_state,
+            io_w_req_bits_data_0_clients,
+            io_w_req_bits_data_0_alias,
+            io_w_req_bits_data_0_prefetch,
+            io_w_req_bits_data_0_prefetchSrc,
+            io_w_req_bits_data_0_accessed,
+            io_w_req_bits_data_0_tagErr,
+            io_w_req_bits_data_0_dataErr}),
+    .RW0_rdata              (_array_RW0_rdata)
+  );
+  assign io_r_req_ready = ~io_w_req_valid;
+  assign io_r_resp_data_0_dirty = _array_RW0_rdata[12];
+  assign io_r_resp_data_0_state = _array_RW0_rdata[11:10];
+  assign io_r_resp_data_0_clients = _array_RW0_rdata[9];
+  assign io_r_resp_data_0_alias = _array_RW0_rdata[8];
+  assign io_r_resp_data_0_prefetch = _array_RW0_rdata[7];
+  assign io_r_resp_data_0_prefetchSrc = _array_RW0_rdata[6:3];
+  assign io_r_resp_data_0_accessed = _array_RW0_rdata[2];
+  assign io_r_resp_data_0_tagErr = _array_RW0_rdata[1];
+  assign io_r_resp_data_0_dataErr = _array_RW0_rdata[0];
+  assign io_r_resp_data_1_dirty = _array_RW0_rdata[25];
+  assign io_r_resp_data_1_state = _array_RW0_rdata[24:23];
+  assign io_r_resp_data_1_clients = _array_RW0_rdata[22];
+  assign io_r_resp_data_1_alias = _array_RW0_rdata[21];
+  assign io_r_resp_data_1_prefetch = _array_RW0_rdata[20];
+  assign io_r_resp_data_1_prefetchSrc = _array_RW0_rdata[19:16];
+  assign io_r_resp_data_1_accessed = _array_RW0_rdata[15];
+  assign io_r_resp_data_1_tagErr = _array_RW0_rdata[14];
+  assign io_r_resp_data_1_dataErr = _array_RW0_rdata[13];
+  assign io_r_resp_data_2_dirty = _array_RW0_rdata[38];
+  assign io_r_resp_data_2_state = _array_RW0_rdata[37:36];
+  assign io_r_resp_data_2_clients = _array_RW0_rdata[35];
+  assign io_r_resp_data_2_alias = _array_RW0_rdata[34];
+  assign io_r_resp_data_2_prefetch = _array_RW0_rdata[33];
+  assign io_r_resp_data_2_prefetchSrc = _array_RW0_rdata[32:29];
+  assign io_r_resp_data_2_accessed = _array_RW0_rdata[28];
+  assign io_r_resp_data_2_tagErr = _array_RW0_rdata[27];
+  assign io_r_resp_data_2_dataErr = _array_RW0_rdata[26];
+  assign io_r_resp_data_3_dirty = _array_RW0_rdata[51];
+  assign io_r_resp_data_3_state = _array_RW0_rdata[50:49];
+  assign io_r_resp_data_3_clients = _array_RW0_rdata[48];
+  assign io_r_resp_data_3_alias = _array_RW0_rdata[47];
+  assign io_r_resp_data_3_prefetch = _array_RW0_rdata[46];
+  assign io_r_resp_data_3_prefetchSrc = _array_RW0_rdata[45:42];
+  assign io_r_resp_data_3_accessed = _array_RW0_rdata[41];
+  assign io_r_resp_data_3_tagErr = _array_RW0_rdata[40];
+  assign io_r_resp_data_3_dataErr = _array_RW0_rdata[39];
+  assign io_r_resp_data_4_dirty = _array_RW0_rdata[64];
+  assign io_r_resp_data_4_state = _array_RW0_rdata[63:62];
+  assign io_r_resp_data_4_clients = _array_RW0_rdata[61];
+  assign io_r_resp_data_4_alias = _array_RW0_rdata[60];
+  assign io_r_resp_data_4_prefetch = _array_RW0_rdata[59];
+  assign io_r_resp_data_4_prefetchSrc = _array_RW0_rdata[58:55];
+  assign io_r_resp_data_4_accessed = _array_RW0_rdata[54];
+  assign io_r_resp_data_4_tagErr = _array_RW0_rdata[53];
+  assign io_r_resp_data_4_dataErr = _array_RW0_rdata[52];
+  assign io_r_resp_data_5_dirty = _array_RW0_rdata[77];
+  assign io_r_resp_data_5_state = _array_RW0_rdata[76:75];
+  assign io_r_resp_data_5_clients = _array_RW0_rdata[74];
+  assign io_r_resp_data_5_alias = _array_RW0_rdata[73];
+  assign io_r_resp_data_5_prefetch = _array_RW0_rdata[72];
+  assign io_r_resp_data_5_prefetchSrc = _array_RW0_rdata[71:68];
+  assign io_r_resp_data_5_accessed = _array_RW0_rdata[67];
+  assign io_r_resp_data_5_tagErr = _array_RW0_rdata[66];
+  assign io_r_resp_data_5_dataErr = _array_RW0_rdata[65];
+  assign io_r_resp_data_6_dirty = _array_RW0_rdata[90];
+  assign io_r_resp_data_6_state = _array_RW0_rdata[89:88];
+  assign io_r_resp_data_6_clients = _array_RW0_rdata[87];
+  assign io_r_resp_data_6_alias = _array_RW0_rdata[86];
+  assign io_r_resp_data_6_prefetch = _array_RW0_rdata[85];
+  assign io_r_resp_data_6_prefetchSrc = _array_RW0_rdata[84:81];
+  assign io_r_resp_data_6_accessed = _array_RW0_rdata[80];
+  assign io_r_resp_data_6_tagErr = _array_RW0_rdata[79];
+  assign io_r_resp_data_6_dataErr = _array_RW0_rdata[78];
+  assign io_r_resp_data_7_dirty = _array_RW0_rdata[103];
+  assign io_r_resp_data_7_state = _array_RW0_rdata[102:101];
+  assign io_r_resp_data_7_clients = _array_RW0_rdata[100];
+  assign io_r_resp_data_7_alias = _array_RW0_rdata[99];
+  assign io_r_resp_data_7_prefetch = _array_RW0_rdata[98];
+  assign io_r_resp_data_7_prefetchSrc = _array_RW0_rdata[97:94];
+  assign io_r_resp_data_7_accessed = _array_RW0_rdata[93];
+  assign io_r_resp_data_7_tagErr = _array_RW0_rdata[92];
+  assign io_r_resp_data_7_dataErr = _array_RW0_rdata[91];
+  assign io_w_req_ready = 1'h1;
+  assign io_resetDone = 1'h1;
+  assign boreChildrenBd_bore_rdata = mbistBd_rdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_244.sv b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_244.sv
new file mode 100644
index 0000000000..9617a84b48
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_244.sv
@@ -0,0 +1,161 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module SRAMTemplate_244(
+  input         clock,
+  input         reset,
+  input         io_r_req_valid,
+  input  [7:0]  io_r_req_bits_setIdx,
+  output [15:0] io_r_resp_data_0,
+  input         io_w_req_valid,
+  input  [7:0]  io_w_req_bits_setIdx,
+  input  [15:0] io_w_req_bits_data_0,
+  input         io_broadcast_ram_hold,
+  input         io_broadcast_ram_bypass,
+  input         io_broadcast_ram_bp_clken,
+  input         io_broadcast_ram_aux_clk,
+  input         io_broadcast_ram_aux_ckbp,
+  input         io_broadcast_ram_mcp_hold,
+  input  [63:0] io_broadcast_ram_ctl,
+  input         io_broadcast_cgen,
+  input  [8:0]  boreChildrenBd_bore_addr,
+  input  [8:0]  boreChildrenBd_bore_addr_rd,
+  input  [15:0] boreChildrenBd_bore_wdata,
+  input         boreChildrenBd_bore_wmask,
+  input         boreChildrenBd_bore_re,
+  input         boreChildrenBd_bore_we,
+  output [15:0] boreChildrenBd_bore_rdata,
+  input         boreChildrenBd_bore_ack,
+  input         boreChildrenBd_bore_selectedOH,
+  input  [2:0]  boreChildrenBd_bore_array
+);
+
+  wire        _io_r_req_ready_T_1;
+  wire        _io_resetDone_T;
+  wire [15:0] _array_RW0_rdata;
+  wire [8:0]  mbistBd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire [15:0] mbistBd_wdata = boreChildrenBd_bore_wdata;
+  wire        mbistBd_re = boreChildrenBd_bore_re;
+  wire        mbistBd_we = boreChildrenBd_bore_we;
+  wire        mbistBd_ack = boreChildrenBd_bore_ack;
+  wire        mbistWmask = boreChildrenBd_bore_selectedOH;
+  wire [8:0]  mbistBd_addr = boreChildrenBd_bore_addr;
+  wire        mbistBd_wmask = boreChildrenBd_bore_wmask;
+  wire [2:0]  mbistBd_array = boreChildrenBd_bore_array;
+  reg         _resetState;
+  reg  [7:0]  _resetSet;
+  wire        rckEn =
+    mbistBd_ack ? mbistBd_re : _io_resetDone_T & _io_r_req_ready_T_1 & io_r_req_valid;
+  wire        finalRamWen =
+    (mbistBd_ack ? mbistBd_we : io_w_req_valid | _resetState) & ~io_broadcast_ram_hold;
+  reg         respReg;
+  reg  [15:0] rdataReg;
+  wire [15:0] mbistBd_rdata = rdataReg;
+  assign _io_resetDone_T = ~_resetState;
+  assign _io_r_req_ready_T_1 = ~io_w_req_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _resetState <= 1'h1;
+      _resetSet <= 8'h0;
+      respReg <= 1'h0;
+    end
+    else begin
+      _resetState <= ~(_resetState & (&_resetSet)) & _resetState;
+      if (_resetState)
+        _resetSet <= 8'(_resetSet + 8'h1);
+      respReg <= rckEn;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (respReg)
+      rdataReg <= _array_RW0_rdata;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:3];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
+          _RANDOM[i[1:0]] = `RANDOM;
+        end
+        _resetState = _RANDOM[2'h0][0];
+        _resetSet = _RANDOM[2'h0][8:1];
+        respReg = _RANDOM[2'h1][11];
+        rdataReg = _RANDOM[2'h3][27:12];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        _resetState = 1'h1;
+        _resetSet = 8'h0;
+        respReg = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  sram_array_1p256x16m16s1h0l1b_l2_repl array (
+    .mbist_dft_ram_bypass   (io_broadcast_ram_bypass),
+    .mbist_dft_ram_bp_clken (io_broadcast_ram_bp_clken),
+    .RW0_clk                (clock),
+    .RW0_addr
+      (mbistBd_ack
+         ? mbistBd_addr_rd[7:0]
+         : finalRamWen
+             ? (_resetState ? _resetSet : io_w_req_bits_setIdx)
+             : io_r_req_bits_setIdx),
+    .RW0_en                 (finalRamWen | rckEn),
+    .RW0_wmode              (finalRamWen),
+    .RW0_wdata
+      (mbistBd_ack ? mbistBd_wdata : _resetState ? 16'h0 : io_w_req_bits_data_0),
+    .RW0_rdata              (_array_RW0_rdata)
+  );
+  assign io_r_resp_data_0 = _array_RW0_rdata;
+  assign boreChildrenBd_bore_rdata = mbistBd_rdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_245.sv b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_245.sv
new file mode 100644
index 0000000000..af8430e589
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_245.sv
@@ -0,0 +1,198 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module SRAMTemplate_245(
+  input         clock,
+  input         reset,
+  input         io_r_req_valid,
+  input  [7:0]  io_r_req_bits_setIdx,
+  output        io_r_resp_data_0,
+  output        io_r_resp_data_1,
+  output        io_r_resp_data_2,
+  output        io_r_resp_data_3,
+  output        io_r_resp_data_4,
+  output        io_r_resp_data_5,
+  output        io_r_resp_data_6,
+  output        io_r_resp_data_7,
+  input         io_w_req_valid,
+  input  [7:0]  io_w_req_bits_setIdx,
+  input         io_w_req_bits_data_0,
+  input         io_w_req_bits_data_1,
+  input         io_w_req_bits_data_2,
+  input         io_w_req_bits_data_3,
+  input         io_w_req_bits_data_4,
+  input         io_w_req_bits_data_5,
+  input         io_w_req_bits_data_6,
+  input         io_w_req_bits_data_7,
+  input  [7:0]  io_w_req_bits_waymask,
+  input         io_broadcast_ram_hold,
+  input         io_broadcast_ram_bypass,
+  input         io_broadcast_ram_bp_clken,
+  input         io_broadcast_ram_aux_clk,
+  input         io_broadcast_ram_aux_ckbp,
+  input         io_broadcast_ram_mcp_hold,
+  input  [63:0] io_broadcast_ram_ctl,
+  input         io_broadcast_cgen,
+  input  [8:0]  boreChildrenBd_bore_addr,
+  input  [8:0]  boreChildrenBd_bore_addr_rd,
+  input  [7:0]  boreChildrenBd_bore_wdata,
+  input  [7:0]  boreChildrenBd_bore_wmask,
+  input         boreChildrenBd_bore_re,
+  input         boreChildrenBd_bore_we,
+  output [7:0]  boreChildrenBd_bore_rdata,
+  input         boreChildrenBd_bore_ack,
+  input         boreChildrenBd_bore_selectedOH,
+  input  [2:0]  boreChildrenBd_bore_array
+);
+
+  wire       _io_r_req_ready_T_1;
+  wire       _io_resetDone_T;
+  wire [7:0] _array_RW0_rdata;
+  wire [8:0] mbistBd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire [7:0] mbistBd_wdata = boreChildrenBd_bore_wdata;
+  wire [7:0] mbistBd_wmask = boreChildrenBd_bore_wmask;
+  wire       mbistBd_re = boreChildrenBd_bore_re;
+  wire       mbistBd_we = boreChildrenBd_bore_we;
+  wire       mbistBd_ack = boreChildrenBd_bore_ack;
+  wire       mbistBd_selectedOH = boreChildrenBd_bore_selectedOH;
+  wire [8:0] mbistBd_addr = boreChildrenBd_bore_addr;
+  wire [2:0] mbistBd_array = boreChildrenBd_bore_array;
+  reg        _resetState;
+  reg  [7:0] _resetSet;
+  wire       rckEn =
+    mbistBd_ack ? mbistBd_re : _io_resetDone_T & _io_r_req_ready_T_1 & io_r_req_valid;
+  wire       finalRamWen =
+    (mbistBd_ack ? mbistBd_we : io_w_req_valid | _resetState) & ~io_broadcast_ram_hold;
+  reg        respReg;
+  reg  [7:0] rdataReg;
+  wire [7:0] mbistBd_rdata = rdataReg;
+  assign _io_resetDone_T = ~_resetState;
+  assign _io_r_req_ready_T_1 = ~io_w_req_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      _resetState <= 1'h1;
+      _resetSet <= 8'h0;
+      respReg <= 1'h0;
+    end
+    else begin
+      _resetState <= ~(_resetState & (&_resetSet)) & _resetState;
+      if (_resetState)
+        _resetSet <= 8'(_resetSet + 8'h1);
+      respReg <= rckEn;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (respReg)
+      rdataReg <= _array_RW0_rdata;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:17];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h12; i += 5'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        _resetState = _RANDOM[5'h0][0];
+        _resetSet = _RANDOM[5'h0][8:1];
+        respReg = _RANDOM[5'h1][10];
+        rdataReg = _RANDOM[5'h11][18:11];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        _resetState = 1'h1;
+        _resetSet = 8'h0;
+        respReg = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  sram_array_1p256x8m1s1h0l1b_l2_orgb array (
+    .mbist_dft_ram_bypass   (io_broadcast_ram_bypass),
+    .mbist_dft_ram_bp_clken (io_broadcast_ram_bp_clken),
+    .RW0_clk                (clock),
+    .RW0_addr
+      (mbistBd_ack
+         ? mbistBd_addr_rd[7:0]
+         : finalRamWen
+             ? (_resetState ? _resetSet : io_w_req_bits_setIdx)
+             : io_r_req_bits_setIdx),
+    .RW0_en                 (finalRamWen | rckEn),
+    .RW0_wmode              (finalRamWen),
+    .RW0_wmask
+      (mbistBd_ack
+         ? {8{mbistBd_selectedOH}} & mbistBd_wmask
+         : _resetState ? 8'hFF : io_w_req_bits_waymask),
+    .RW0_wdata
+      (mbistBd_ack
+         ? mbistBd_wdata
+         : _resetState
+             ? 8'h0
+             : {io_w_req_bits_data_7,
+                io_w_req_bits_data_6,
+                io_w_req_bits_data_5,
+                io_w_req_bits_data_4,
+                io_w_req_bits_data_3,
+                io_w_req_bits_data_2,
+                io_w_req_bits_data_1,
+                io_w_req_bits_data_0}),
+    .RW0_rdata              (_array_RW0_rdata)
+  );
+  assign io_r_resp_data_0 = _array_RW0_rdata[0];
+  assign io_r_resp_data_1 = _array_RW0_rdata[1];
+  assign io_r_resp_data_2 = _array_RW0_rdata[2];
+  assign io_r_resp_data_3 = _array_RW0_rdata[3];
+  assign io_r_resp_data_4 = _array_RW0_rdata[4];
+  assign io_r_resp_data_5 = _array_RW0_rdata[5];
+  assign io_r_resp_data_6 = _array_RW0_rdata[6];
+  assign io_r_resp_data_7 = _array_RW0_rdata[7];
+  assign boreChildrenBd_bore_rdata = mbistBd_rdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_246.sv b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_246.sv
new file mode 100644
index 0000000000..c44f6b4743
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_246.sv
@@ -0,0 +1,168 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module SRAMTemplate_246(
+  input          clock,
+  input          reset,
+  input          io_r_req_valid,
+  input  [10:0]  io_r_req_bits_setIdx,
+  output [136:0] io_r_resp_data_0,
+  input          io_w_req_valid,
+  input  [10:0]  io_w_req_bits_setIdx,
+  input  [136:0] io_w_req_bits_data_0,
+  input          io_broadcast_ram_hold,
+  input          io_broadcast_ram_bypass,
+  input          io_broadcast_ram_bp_clken,
+  input          io_broadcast_ram_aux_clk,
+  input          io_broadcast_ram_aux_ckbp,
+  input          io_broadcast_ram_mcp_hold,
+  input  [63:0]  io_broadcast_ram_ctl,
+  input          io_broadcast_cgen,
+  output         io_mbistCgCtl_en,
+  output         io_mbistCgCtl_rckEn,
+  output         io_mbistCgCtl_wckEn,
+  input          io_mbistCgCtl_rclk,
+  input  [11:0]  boreChildrenBd_bore_addr,
+  input  [11:0]  boreChildrenBd_bore_addr_rd,
+  input  [136:0] boreChildrenBd_bore_wdata,
+  input          boreChildrenBd_bore_wmask,
+  input          boreChildrenBd_bore_re,
+  input          boreChildrenBd_bore_we,
+  output [136:0] boreChildrenBd_bore_rdata,
+  input          boreChildrenBd_bore_ack,
+  input          boreChildrenBd_bore_selectedOH,
+  input  [2:0]   boreChildrenBd_bore_array
+);
+
+  wire         io_r_req_ready;
+  wire [136:0] _array_RW0_rdata;
+  wire [11:0]  mbistBd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire [136:0] mbistBd_wdata = boreChildrenBd_bore_wdata;
+  wire         mbistBd_re = boreChildrenBd_bore_re;
+  wire         mbistBd_we = boreChildrenBd_bore_we;
+  wire         mbistBd_ack = boreChildrenBd_bore_ack;
+  wire         mbistWmask = boreChildrenBd_bore_selectedOH;
+  wire [11:0]  mbistBd_addr = boreChildrenBd_bore_addr;
+  wire         mbistBd_wmask = boreChildrenBd_bore_wmask;
+  wire [2:0]   mbistBd_array = boreChildrenBd_bore_array;
+  wire         ramWen = mbistBd_ack ? mbistBd_we : io_w_req_valid;
+  wire         ramRen = mbistBd_ack ? mbistBd_re : io_r_req_ready & io_r_req_valid;
+  reg          rckEnReg;
+  reg          wckEnReg;
+  wire         rckEn = {ramRen, rckEnReg} == 2'h2;
+  wire         wckEn = {ramWen, wckEnReg} == 2'h2;
+  wire         finalRamWen = ramWen & ~io_broadcast_ram_hold;
+  reg  [1:0]   respReg;
+  reg  [136:0] rdataReg;
+  wire [136:0] mbistBd_rdata = rdataReg;
+  assign io_r_req_ready = ~io_w_req_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      rckEnReg <= 1'h0;
+      wckEnReg <= 1'h0;
+      respReg <= 2'h0;
+    end
+    else begin
+      rckEnReg <= rckEn;
+      wckEnReg <= wckEn;
+      respReg <= rckEn ? 2'h2 : {1'h0, respReg[1]};
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (respReg[0])
+      rdataReg <= _array_RW0_rdata;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:11];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hC; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        rckEnReg = _RANDOM[4'h5][1];
+        wckEnReg = _RANDOM[4'h5][2];
+        respReg = _RANDOM[4'h5][4:3];
+        rdataReg =
+          {_RANDOM[4'h7][31:5],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB][13:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        rckEnReg = 1'h0;
+        wckEnReg = 1'h0;
+        respReg = 2'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  sram_array_1p2048x137m137s1h1l2b_l2_dat array (
+    .mbist_dft_ram_bypass   (io_broadcast_ram_bypass),
+    .mbist_dft_ram_bp_clken (io_broadcast_ram_bp_clken),
+    .RW0_clk                (io_mbistCgCtl_rclk),
+    .RW0_addr
+      (mbistBd_ack
+         ? mbistBd_addr_rd[10:0]
+         : finalRamWen ? io_w_req_bits_setIdx : io_r_req_bits_setIdx),
+    .RW0_en                 (finalRamWen | ramRen),
+    .RW0_wmode              (finalRamWen),
+    .RW0_wdata              (mbistBd_ack ? mbistBd_wdata : io_w_req_bits_data_0),
+    .RW0_rdata              (_array_RW0_rdata)
+  );
+  assign io_r_resp_data_0 = _array_RW0_rdata;
+  assign io_mbistCgCtl_en = mbistBd_ack;
+  assign io_mbistCgCtl_rckEn = rckEn;
+  assign io_mbistCgCtl_wckEn = wckEn;
+  assign boreChildrenBd_bore_rdata = mbistBd_rdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_247.sv b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_247.sv
new file mode 100644
index 0000000000..f6251f21db
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SRAMTemplate_247.sv
@@ -0,0 +1,168 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module SRAMTemplate_247(
+  input          clock,
+  input          reset,
+  input          io_r_req_valid,
+  input  [10:0]  io_r_req_bits_setIdx,
+  output [136:0] io_r_resp_data_0,
+  input          io_w_req_valid,
+  input  [10:0]  io_w_req_bits_setIdx,
+  input  [136:0] io_w_req_bits_data_0,
+  input          io_broadcast_ram_hold,
+  input          io_broadcast_ram_bypass,
+  input          io_broadcast_ram_bp_clken,
+  input          io_broadcast_ram_aux_clk,
+  input          io_broadcast_ram_aux_ckbp,
+  input          io_broadcast_ram_mcp_hold,
+  input  [63:0]  io_broadcast_ram_ctl,
+  input          io_broadcast_cgen,
+  output         io_mbistCgCtl_en,
+  output         io_mbistCgCtl_rckEn,
+  output         io_mbistCgCtl_wckEn,
+  input          io_mbistCgCtl_rclk,
+  input  [11:0]  boreChildrenBd_bore_addr,
+  input  [11:0]  boreChildrenBd_bore_addr_rd,
+  input  [136:0] boreChildrenBd_bore_wdata,
+  input          boreChildrenBd_bore_wmask,
+  input          boreChildrenBd_bore_re,
+  input          boreChildrenBd_bore_we,
+  output [136:0] boreChildrenBd_bore_rdata,
+  input          boreChildrenBd_bore_ack,
+  input          boreChildrenBd_bore_selectedOH,
+  input  [3:0]   boreChildrenBd_bore_array
+);
+
+  wire         io_r_req_ready;
+  wire [136:0] _array_RW0_rdata;
+  wire [11:0]  mbistBd_addr_rd = boreChildrenBd_bore_addr_rd;
+  wire [136:0] mbistBd_wdata = boreChildrenBd_bore_wdata;
+  wire         mbistBd_re = boreChildrenBd_bore_re;
+  wire         mbistBd_we = boreChildrenBd_bore_we;
+  wire         mbistBd_ack = boreChildrenBd_bore_ack;
+  wire         mbistWmask = boreChildrenBd_bore_selectedOH;
+  wire [11:0]  mbistBd_addr = boreChildrenBd_bore_addr;
+  wire         mbistBd_wmask = boreChildrenBd_bore_wmask;
+  wire [3:0]   mbistBd_array = boreChildrenBd_bore_array;
+  wire         ramWen = mbistBd_ack ? mbistBd_we : io_w_req_valid;
+  wire         ramRen = mbistBd_ack ? mbistBd_re : io_r_req_ready & io_r_req_valid;
+  reg          rckEnReg;
+  reg          wckEnReg;
+  wire         rckEn = {ramRen, rckEnReg} == 2'h2;
+  wire         wckEn = {ramWen, wckEnReg} == 2'h2;
+  wire         finalRamWen = ramWen & ~io_broadcast_ram_hold;
+  reg  [1:0]   respReg;
+  reg  [136:0] rdataReg;
+  wire [136:0] mbistBd_rdata = rdataReg;
+  assign io_r_req_ready = ~io_w_req_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      rckEnReg <= 1'h0;
+      wckEnReg <= 1'h0;
+      respReg <= 2'h0;
+    end
+    else begin
+      rckEnReg <= rckEn;
+      wckEnReg <= wckEn;
+      respReg <= rckEn ? 2'h2 : {1'h0, respReg[1]};
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (respReg[0])
+      rdataReg <= _array_RW0_rdata;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:11];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'hC; i += 4'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        rckEnReg = _RANDOM[4'h5][1];
+        wckEnReg = _RANDOM[4'h5][2];
+        respReg = _RANDOM[4'h5][4:3];
+        rdataReg =
+          {_RANDOM[4'h7][31:5],
+           _RANDOM[4'h8],
+           _RANDOM[4'h9],
+           _RANDOM[4'hA],
+           _RANDOM[4'hB][13:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        rckEnReg = 1'h0;
+        wckEnReg = 1'h0;
+        respReg = 2'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  sram_array_1p2048x137m137s1h1l2b_l2_dat array (
+    .mbist_dft_ram_bypass   (io_broadcast_ram_bypass),
+    .mbist_dft_ram_bp_clken (io_broadcast_ram_bp_clken),
+    .RW0_clk                (io_mbistCgCtl_rclk),
+    .RW0_addr
+      (mbistBd_ack
+         ? mbistBd_addr_rd[10:0]
+         : finalRamWen ? io_w_req_bits_setIdx : io_r_req_bits_setIdx),
+    .RW0_en                 (finalRamWen | ramRen),
+    .RW0_wmode              (finalRamWen),
+    .RW0_wdata              (mbistBd_ack ? mbistBd_wdata : io_w_req_bits_data_0),
+    .RW0_rdata              (_array_RW0_rdata)
+  );
+  assign io_r_resp_data_0 = _array_RW0_rdata;
+  assign io_mbistCgCtl_en = mbistBd_ack;
+  assign io_mbistCgCtl_rckEn = rckEn;
+  assign io_mbistCgCtl_wckEn = wckEn;
+  assign boreChildrenBd_bore_rdata = mbistBd_rdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SinkA.sv b/flow/designs/src/xiangshan_coupledl2/deps/SinkA.sv
new file mode 100644
index 0000000000..2334a2af6d
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SinkA.sv
@@ -0,0 +1,67 @@
+// Generated by CIRCT firtool-1.135.0
+module SinkA(
+  output        io_a_ready,
+  input         io_a_valid,
+  input  [3:0]  io_a_bits_opcode,
+  input  [2:0]  io_a_bits_param,
+  input  [2:0]  io_a_bits_size,
+  input  [6:0]  io_a_bits_source,
+  input  [47:0] io_a_bits_address,
+  input  [4:0]  io_a_bits_user_reqSource,
+  input         io_a_bits_user_alias,
+  input  [43:0] io_a_bits_user_vaddr,
+  input         io_a_bits_user_needHint,
+  input         io_a_bits_echo_isKeyword,
+  input         io_a_bits_corrupt,
+  output        io_prefetchReq_ready,
+  input         io_prefetchReq_valid,
+  input  [33:0] io_prefetchReq_bits_tag,
+  input  [7:0]  io_prefetchReq_bits_set,
+  input  [43:0] io_prefetchReq_bits_vaddr,
+  input         io_prefetchReq_bits_needT,
+  input  [6:0]  io_prefetchReq_bits_source,
+  input  [4:0]  io_prefetchReq_bits_pfSource,
+  input         io_task_ready,
+  output        io_task_valid,
+  output [7:0]  io_task_bits_set,
+  output [33:0] io_task_bits_tag,
+  output [5:0]  io_task_bits_off,
+  output        io_task_bits_alias,
+  output [43:0] io_task_bits_vaddr,
+  output        io_task_bits_isKeyword,
+  output [3:0]  io_task_bits_opcode,
+  output [2:0]  io_task_bits_param,
+  output [2:0]  io_task_bits_size,
+  output [6:0]  io_task_bits_sourceId,
+  output        io_task_bits_corrupt,
+  output        io_task_bits_fromL2pft,
+  output        io_task_bits_needHint,
+  output [4:0]  io_task_bits_reqSource
+);
+
+  assign io_a_ready = io_task_ready;
+  assign io_prefetchReq_ready = io_task_ready & ~io_a_valid;
+  assign io_task_valid = io_a_valid | io_prefetchReq_valid;
+  assign io_task_bits_set =
+    io_a_valid ? io_a_bits_address[13:6] : io_prefetchReq_bits_set;
+  assign io_task_bits_tag =
+    io_a_valid ? io_a_bits_address[47:14] : io_prefetchReq_bits_tag;
+  assign io_task_bits_off = io_a_valid ? io_a_bits_address[5:0] : 6'h0;
+  assign io_task_bits_alias = io_a_valid & io_a_bits_user_alias;
+  assign io_task_bits_vaddr =
+    io_a_valid ? io_a_bits_user_vaddr : io_prefetchReq_bits_vaddr;
+  assign io_task_bits_isKeyword = io_a_valid & io_a_bits_echo_isKeyword;
+  assign io_task_bits_opcode = io_a_valid ? io_a_bits_opcode : 4'h5;
+  assign io_task_bits_param =
+    io_a_valid ? io_a_bits_param : {2'h0, io_prefetchReq_bits_needT};
+  assign io_task_bits_size = io_a_valid ? io_a_bits_size : 3'h6;
+  assign io_task_bits_sourceId =
+    io_a_valid ? io_a_bits_source : io_prefetchReq_bits_source;
+  assign io_task_bits_corrupt = io_a_valid & io_a_bits_corrupt;
+  assign io_task_bits_fromL2pft =
+    ~io_a_valid
+    & (io_prefetchReq_bits_pfSource == 5'h8 | io_prefetchReq_bits_pfSource == 5'h9);
+  assign io_task_bits_needHint = io_a_valid & io_a_bits_user_needHint;
+  assign io_task_bits_reqSource =
+    io_a_valid ? io_a_bits_user_reqSource : io_prefetchReq_bits_pfSource;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SinkC.sv b/flow/designs/src/xiangshan_coupledl2/deps/SinkC.sv
new file mode 100644
index 0000000000..bffc225d1b
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SinkC.sv
@@ -0,0 +1,3256 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module SinkC(
+  input          clock,
+  input          reset,
+  output         io_c_ready,
+  input          io_c_valid,
+  input  [2:0]   io_c_bits_opcode,
+  input  [2:0]   io_c_bits_param,
+  input  [2:0]   io_c_bits_size,
+  input  [6:0]   io_c_bits_source,
+  input  [47:0]  io_c_bits_address,
+  input  [255:0] io_c_bits_data,
+  input          io_c_bits_corrupt,
+  input          io_task_ready,
+  output         io_task_valid,
+  output [2:0]   io_task_bits_channel,
+  output [2:0]   io_task_bits_txChannel,
+  output [7:0]   io_task_bits_set,
+  output [33:0]  io_task_bits_tag,
+  output [5:0]   io_task_bits_off,
+  output         io_task_bits_alias,
+  output [43:0]  io_task_bits_vaddr,
+  output         io_task_bits_isKeyword,
+  output [3:0]   io_task_bits_opcode,
+  output [2:0]   io_task_bits_param,
+  output [2:0]   io_task_bits_size,
+  output [6:0]   io_task_bits_sourceId,
+  output [1:0]   io_task_bits_bufIdx,
+  output         io_task_bits_needProbeAckData,
+  output         io_task_bits_denied,
+  output         io_task_bits_corrupt,
+  output         io_task_bits_mshrTask,
+  output [7:0]   io_task_bits_mshrId,
+  output         io_task_bits_aliasTask,
+  output         io_task_bits_useProbeData,
+  output         io_task_bits_mshrRetry,
+  output         io_task_bits_readProbeDataDown,
+  output         io_task_bits_fromL2pft,
+  output         io_task_bits_needHint,
+  output         io_task_bits_dirty,
+  output [2:0]   io_task_bits_way,
+  output         io_task_bits_meta_dirty,
+  output [1:0]   io_task_bits_meta_state,
+  output         io_task_bits_meta_clients,
+  output         io_task_bits_meta_alias,
+  output         io_task_bits_meta_prefetch,
+  output [3:0]   io_task_bits_meta_prefetchSrc,
+  output         io_task_bits_meta_accessed,
+  output         io_task_bits_meta_tagErr,
+  output         io_task_bits_meta_dataErr,
+  output         io_task_bits_metaWen,
+  output         io_task_bits_tagWen,
+  output         io_task_bits_dsWen,
+  output [7:0]   io_task_bits_wayMask,
+  output         io_task_bits_replTask,
+  output         io_task_bits_cmoTask,
+  output         io_task_bits_cmoAll,
+  output [4:0]   io_task_bits_reqSource,
+  output         io_task_bits_mergeA,
+  output [5:0]   io_task_bits_aMergeTask_off,
+  output         io_task_bits_aMergeTask_alias,
+  output [43:0]  io_task_bits_aMergeTask_vaddr,
+  output         io_task_bits_aMergeTask_isKeyword,
+  output [2:0]   io_task_bits_aMergeTask_opcode,
+  output [2:0]   io_task_bits_aMergeTask_param,
+  output [6:0]   io_task_bits_aMergeTask_sourceId,
+  output         io_task_bits_aMergeTask_meta_dirty,
+  output [1:0]   io_task_bits_aMergeTask_meta_state,
+  output         io_task_bits_aMergeTask_meta_clients,
+  output         io_task_bits_aMergeTask_meta_alias,
+  output         io_task_bits_aMergeTask_meta_prefetch,
+  output [3:0]   io_task_bits_aMergeTask_meta_prefetchSrc,
+  output         io_task_bits_aMergeTask_meta_accessed,
+  output         io_task_bits_aMergeTask_meta_tagErr,
+  output         io_task_bits_aMergeTask_meta_dataErr,
+  output         io_task_bits_snpHitRelease,
+  output         io_task_bits_snpHitReleaseToInval,
+  output         io_task_bits_snpHitReleaseToClean,
+  output         io_task_bits_snpHitReleaseWithData,
+  output [7:0]   io_task_bits_snpHitReleaseIdx,
+  output         io_task_bits_snpHitReleaseMeta_dirty,
+  output [1:0]   io_task_bits_snpHitReleaseMeta_state,
+  output         io_task_bits_snpHitReleaseMeta_clients,
+  output         io_task_bits_snpHitReleaseMeta_alias,
+  output         io_task_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]   io_task_bits_snpHitReleaseMeta_prefetchSrc,
+  output         io_task_bits_snpHitReleaseMeta_accessed,
+  output         io_task_bits_snpHitReleaseMeta_tagErr,
+  output         io_task_bits_snpHitReleaseMeta_dataErr,
+  output [10:0]  io_task_bits_tgtID,
+  output [10:0]  io_task_bits_srcID,
+  output [11:0]  io_task_bits_txnID,
+  output [10:0]  io_task_bits_homeNID,
+  output [11:0]  io_task_bits_dbID,
+  output [10:0]  io_task_bits_fwdNID,
+  output [11:0]  io_task_bits_fwdTxnID,
+  output [6:0]   io_task_bits_chiOpcode,
+  output [2:0]   io_task_bits_resp,
+  output [2:0]   io_task_bits_fwdState,
+  output [3:0]   io_task_bits_pCrdType,
+  output         io_task_bits_retToSrc,
+  output         io_task_bits_likelyshared,
+  output         io_task_bits_expCompAck,
+  output         io_task_bits_allowRetry,
+  output         io_task_bits_memAttr_allocate,
+  output         io_task_bits_memAttr_cacheable,
+  output         io_task_bits_memAttr_device,
+  output         io_task_bits_memAttr_ewa,
+  output         io_task_bits_traceTag,
+  output         io_resp_valid,
+  output [7:0]   io_resp_set,
+  output [33:0]  io_resp_tag,
+  output [2:0]   io_resp_respInfo_opcode,
+  output [2:0]   io_resp_respInfo_param,
+  output         io_resp_respInfo_last,
+  output         io_resp_respInfo_denied,
+  output         io_resp_respInfo_corrupt,
+  output         io_releaseBufWrite_valid,
+  output [511:0] io_releaseBufWrite_bits_data_data,
+  output [255:0] io_bufResp_data_0,
+  output [255:0] io_bufResp_data_1,
+  output         io_refillBufWrite_valid,
+  output [7:0]   io_refillBufWrite_bits_id,
+  output [511:0] io_refillBufWrite_bits_data_data,
+  input          io_msInfo_0_valid,
+  input  [7:0]   io_msInfo_0_bits_set,
+  input  [33:0]  io_msInfo_0_bits_reqTag,
+  input          io_msInfo_0_bits_blockRefill,
+  input          io_msInfo_1_valid,
+  input  [7:0]   io_msInfo_1_bits_set,
+  input  [33:0]  io_msInfo_1_bits_reqTag,
+  input          io_msInfo_1_bits_blockRefill,
+  input          io_msInfo_2_valid,
+  input  [7:0]   io_msInfo_2_bits_set,
+  input  [33:0]  io_msInfo_2_bits_reqTag,
+  input          io_msInfo_2_bits_blockRefill,
+  input          io_msInfo_3_valid,
+  input  [7:0]   io_msInfo_3_bits_set,
+  input  [33:0]  io_msInfo_3_bits_reqTag,
+  input          io_msInfo_3_bits_blockRefill,
+  input          io_msInfo_4_valid,
+  input  [7:0]   io_msInfo_4_bits_set,
+  input  [33:0]  io_msInfo_4_bits_reqTag,
+  input          io_msInfo_4_bits_blockRefill,
+  input          io_msInfo_5_valid,
+  input  [7:0]   io_msInfo_5_bits_set,
+  input  [33:0]  io_msInfo_5_bits_reqTag,
+  input          io_msInfo_5_bits_blockRefill,
+  input          io_msInfo_6_valid,
+  input  [7:0]   io_msInfo_6_bits_set,
+  input  [33:0]  io_msInfo_6_bits_reqTag,
+  input          io_msInfo_6_bits_blockRefill,
+  input          io_msInfo_7_valid,
+  input  [7:0]   io_msInfo_7_bits_set,
+  input  [33:0]  io_msInfo_7_bits_reqTag,
+  input          io_msInfo_7_bits_blockRefill,
+  input          io_msInfo_8_valid,
+  input  [7:0]   io_msInfo_8_bits_set,
+  input  [33:0]  io_msInfo_8_bits_reqTag,
+  input          io_msInfo_8_bits_blockRefill,
+  input          io_msInfo_9_valid,
+  input  [7:0]   io_msInfo_9_bits_set,
+  input  [33:0]  io_msInfo_9_bits_reqTag,
+  input          io_msInfo_9_bits_blockRefill,
+  input          io_msInfo_10_valid,
+  input  [7:0]   io_msInfo_10_bits_set,
+  input  [33:0]  io_msInfo_10_bits_reqTag,
+  input          io_msInfo_10_bits_blockRefill,
+  input          io_msInfo_11_valid,
+  input  [7:0]   io_msInfo_11_bits_set,
+  input  [33:0]  io_msInfo_11_bits_reqTag,
+  input          io_msInfo_11_bits_blockRefill,
+  input          io_msInfo_12_valid,
+  input  [7:0]   io_msInfo_12_bits_set,
+  input  [33:0]  io_msInfo_12_bits_reqTag,
+  input          io_msInfo_12_bits_blockRefill,
+  input          io_msInfo_13_valid,
+  input  [7:0]   io_msInfo_13_bits_set,
+  input  [33:0]  io_msInfo_13_bits_reqTag,
+  input          io_msInfo_13_bits_blockRefill,
+  input          io_msInfo_14_valid,
+  input  [7:0]   io_msInfo_14_bits_set,
+  input  [33:0]  io_msInfo_14_bits_reqTag,
+  input          io_msInfo_14_bits_blockRefill,
+  input          io_msInfo_15_valid,
+  input  [7:0]   io_msInfo_15_bits_set,
+  input  [33:0]  io_msInfo_15_bits_reqTag,
+  input          io_msInfo_15_bits_blockRefill
+);
+
+  wire              _taskArb_io_in_0_ready;
+  wire              _taskArb_io_in_1_ready;
+  wire              _taskArb_io_in_2_ready;
+  wire              _taskArb_io_in_3_ready;
+  wire              _taskArb_io_out_valid;
+  wire [7:0]        _taskArb_io_out_bits_set;
+  wire [33:0]       _taskArb_io_out_bits_tag;
+  wire [3:0]        _taskArb_io_out_bits_opcode;
+  wire [1:0]        _taskArb_io_out_bits_bufIdx;
+  wire [12:0]       _r_beats1_decode_T = 13'h3F << io_c_bits_size;
+  wire              r_beats1 = io_c_bits_opcode[0] & ~(_r_beats1_decode_T[5]);
+  reg               r_counter;
+  wire              last = r_counter | ~r_beats1;
+  reg  [255:0]      dataBuf_0_0;
+  reg  [255:0]      dataBuf_0_1;
+  reg  [255:0]      dataBuf_1_0;
+  reg  [255:0]      dataBuf_1_1;
+  reg  [255:0]      dataBuf_2_0;
+  reg  [255:0]      dataBuf_2_1;
+  reg  [255:0]      dataBuf_3_0;
+  reg  [255:0]      dataBuf_3_1;
+  reg               beatValids_0_0;
+  reg               beatValids_0_1;
+  reg               beatValids_1_0;
+  reg               beatValids_1_1;
+  reg               beatValids_2_0;
+  reg               beatValids_2_1;
+  reg               beatValids_3_0;
+  reg               beatValids_3_1;
+  reg  [2:0]        taskBuf_0_channel;
+  reg  [7:0]        taskBuf_0_set;
+  reg  [33:0]       taskBuf_0_tag;
+  reg  [5:0]        taskBuf_0_off;
+  reg               taskBuf_0_alias;
+  reg               taskBuf_0_isKeyword;
+  reg  [3:0]        taskBuf_0_opcode;
+  reg  [2:0]        taskBuf_0_param;
+  reg  [2:0]        taskBuf_0_size;
+  reg  [6:0]        taskBuf_0_sourceId;
+  reg  [1:0]        taskBuf_0_bufIdx;
+  reg               taskBuf_0_needProbeAckData;
+  reg               taskBuf_0_denied;
+  reg               taskBuf_0_corrupt;
+  reg               taskBuf_0_mshrTask;
+  reg               taskBuf_0_aliasTask;
+  reg               taskBuf_0_useProbeData;
+  reg               taskBuf_0_mshrRetry;
+  reg               taskBuf_0_readProbeDataDown;
+  reg               taskBuf_0_fromL2pft;
+  reg               taskBuf_0_needHint;
+  reg               taskBuf_0_dirty;
+  reg               taskBuf_0_meta_dirty;
+  reg               taskBuf_0_meta_clients;
+  reg               taskBuf_0_meta_alias;
+  reg               taskBuf_0_meta_prefetch;
+  reg               taskBuf_0_meta_accessed;
+  reg               taskBuf_0_meta_tagErr;
+  reg               taskBuf_0_meta_dataErr;
+  reg               taskBuf_0_metaWen;
+  reg               taskBuf_0_tagWen;
+  reg               taskBuf_0_dsWen;
+  reg  [7:0]        taskBuf_0_wayMask;
+  reg               taskBuf_0_replTask;
+  reg               taskBuf_0_cmoTask;
+  reg               taskBuf_0_cmoAll;
+  reg               taskBuf_0_mergeA;
+  reg               taskBuf_0_aMergeTask_alias;
+  reg               taskBuf_0_aMergeTask_isKeyword;
+  reg               taskBuf_0_aMergeTask_meta_dirty;
+  reg               taskBuf_0_aMergeTask_meta_clients;
+  reg               taskBuf_0_aMergeTask_meta_alias;
+  reg               taskBuf_0_aMergeTask_meta_prefetch;
+  reg               taskBuf_0_aMergeTask_meta_accessed;
+  reg               taskBuf_0_aMergeTask_meta_tagErr;
+  reg               taskBuf_0_aMergeTask_meta_dataErr;
+  reg               taskBuf_0_snpHitRelease;
+  reg               taskBuf_0_snpHitReleaseToInval;
+  reg               taskBuf_0_snpHitReleaseToClean;
+  reg               taskBuf_0_snpHitReleaseWithData;
+  reg               taskBuf_0_snpHitReleaseMeta_dirty;
+  reg               taskBuf_0_snpHitReleaseMeta_clients;
+  reg               taskBuf_0_snpHitReleaseMeta_alias;
+  reg               taskBuf_0_snpHitReleaseMeta_prefetch;
+  reg               taskBuf_0_snpHitReleaseMeta_accessed;
+  reg               taskBuf_0_snpHitReleaseMeta_tagErr;
+  reg               taskBuf_0_snpHitReleaseMeta_dataErr;
+  reg               taskBuf_0_retToSrc;
+  reg               taskBuf_0_likelyshared;
+  reg               taskBuf_0_expCompAck;
+  reg               taskBuf_0_allowRetry;
+  reg               taskBuf_0_memAttr_allocate;
+  reg               taskBuf_0_memAttr_cacheable;
+  reg               taskBuf_0_memAttr_device;
+  reg               taskBuf_0_memAttr_ewa;
+  reg               taskBuf_0_traceTag;
+  reg  [2:0]        taskBuf_1_channel;
+  reg  [7:0]        taskBuf_1_set;
+  reg  [33:0]       taskBuf_1_tag;
+  reg  [5:0]        taskBuf_1_off;
+  reg               taskBuf_1_alias;
+  reg               taskBuf_1_isKeyword;
+  reg  [3:0]        taskBuf_1_opcode;
+  reg  [2:0]        taskBuf_1_param;
+  reg  [2:0]        taskBuf_1_size;
+  reg  [6:0]        taskBuf_1_sourceId;
+  reg  [1:0]        taskBuf_1_bufIdx;
+  reg               taskBuf_1_needProbeAckData;
+  reg               taskBuf_1_denied;
+  reg               taskBuf_1_corrupt;
+  reg               taskBuf_1_mshrTask;
+  reg               taskBuf_1_aliasTask;
+  reg               taskBuf_1_useProbeData;
+  reg               taskBuf_1_mshrRetry;
+  reg               taskBuf_1_readProbeDataDown;
+  reg               taskBuf_1_fromL2pft;
+  reg               taskBuf_1_needHint;
+  reg               taskBuf_1_dirty;
+  reg               taskBuf_1_meta_dirty;
+  reg               taskBuf_1_meta_clients;
+  reg               taskBuf_1_meta_alias;
+  reg               taskBuf_1_meta_prefetch;
+  reg               taskBuf_1_meta_accessed;
+  reg               taskBuf_1_meta_tagErr;
+  reg               taskBuf_1_meta_dataErr;
+  reg               taskBuf_1_metaWen;
+  reg               taskBuf_1_tagWen;
+  reg               taskBuf_1_dsWen;
+  reg  [7:0]        taskBuf_1_wayMask;
+  reg               taskBuf_1_replTask;
+  reg               taskBuf_1_cmoTask;
+  reg               taskBuf_1_cmoAll;
+  reg               taskBuf_1_mergeA;
+  reg               taskBuf_1_aMergeTask_alias;
+  reg               taskBuf_1_aMergeTask_isKeyword;
+  reg               taskBuf_1_aMergeTask_meta_dirty;
+  reg               taskBuf_1_aMergeTask_meta_clients;
+  reg               taskBuf_1_aMergeTask_meta_alias;
+  reg               taskBuf_1_aMergeTask_meta_prefetch;
+  reg               taskBuf_1_aMergeTask_meta_accessed;
+  reg               taskBuf_1_aMergeTask_meta_tagErr;
+  reg               taskBuf_1_aMergeTask_meta_dataErr;
+  reg               taskBuf_1_snpHitRelease;
+  reg               taskBuf_1_snpHitReleaseToInval;
+  reg               taskBuf_1_snpHitReleaseToClean;
+  reg               taskBuf_1_snpHitReleaseWithData;
+  reg               taskBuf_1_snpHitReleaseMeta_dirty;
+  reg               taskBuf_1_snpHitReleaseMeta_clients;
+  reg               taskBuf_1_snpHitReleaseMeta_alias;
+  reg               taskBuf_1_snpHitReleaseMeta_prefetch;
+  reg               taskBuf_1_snpHitReleaseMeta_accessed;
+  reg               taskBuf_1_snpHitReleaseMeta_tagErr;
+  reg               taskBuf_1_snpHitReleaseMeta_dataErr;
+  reg               taskBuf_1_retToSrc;
+  reg               taskBuf_1_likelyshared;
+  reg               taskBuf_1_expCompAck;
+  reg               taskBuf_1_allowRetry;
+  reg               taskBuf_1_memAttr_allocate;
+  reg               taskBuf_1_memAttr_cacheable;
+  reg               taskBuf_1_memAttr_device;
+  reg               taskBuf_1_memAttr_ewa;
+  reg               taskBuf_1_traceTag;
+  reg  [2:0]        taskBuf_2_channel;
+  reg  [7:0]        taskBuf_2_set;
+  reg  [33:0]       taskBuf_2_tag;
+  reg  [5:0]        taskBuf_2_off;
+  reg               taskBuf_2_alias;
+  reg               taskBuf_2_isKeyword;
+  reg  [3:0]        taskBuf_2_opcode;
+  reg  [2:0]        taskBuf_2_param;
+  reg  [2:0]        taskBuf_2_size;
+  reg  [6:0]        taskBuf_2_sourceId;
+  reg  [1:0]        taskBuf_2_bufIdx;
+  reg               taskBuf_2_needProbeAckData;
+  reg               taskBuf_2_denied;
+  reg               taskBuf_2_corrupt;
+  reg               taskBuf_2_mshrTask;
+  reg               taskBuf_2_aliasTask;
+  reg               taskBuf_2_useProbeData;
+  reg               taskBuf_2_mshrRetry;
+  reg               taskBuf_2_readProbeDataDown;
+  reg               taskBuf_2_fromL2pft;
+  reg               taskBuf_2_needHint;
+  reg               taskBuf_2_dirty;
+  reg               taskBuf_2_meta_dirty;
+  reg               taskBuf_2_meta_clients;
+  reg               taskBuf_2_meta_alias;
+  reg               taskBuf_2_meta_prefetch;
+  reg               taskBuf_2_meta_accessed;
+  reg               taskBuf_2_meta_tagErr;
+  reg               taskBuf_2_meta_dataErr;
+  reg               taskBuf_2_metaWen;
+  reg               taskBuf_2_tagWen;
+  reg               taskBuf_2_dsWen;
+  reg  [7:0]        taskBuf_2_wayMask;
+  reg               taskBuf_2_replTask;
+  reg               taskBuf_2_cmoTask;
+  reg               taskBuf_2_cmoAll;
+  reg               taskBuf_2_mergeA;
+  reg               taskBuf_2_aMergeTask_alias;
+  reg               taskBuf_2_aMergeTask_isKeyword;
+  reg               taskBuf_2_aMergeTask_meta_dirty;
+  reg               taskBuf_2_aMergeTask_meta_clients;
+  reg               taskBuf_2_aMergeTask_meta_alias;
+  reg               taskBuf_2_aMergeTask_meta_prefetch;
+  reg               taskBuf_2_aMergeTask_meta_accessed;
+  reg               taskBuf_2_aMergeTask_meta_tagErr;
+  reg               taskBuf_2_aMergeTask_meta_dataErr;
+  reg               taskBuf_2_snpHitRelease;
+  reg               taskBuf_2_snpHitReleaseToInval;
+  reg               taskBuf_2_snpHitReleaseToClean;
+  reg               taskBuf_2_snpHitReleaseWithData;
+  reg               taskBuf_2_snpHitReleaseMeta_dirty;
+  reg               taskBuf_2_snpHitReleaseMeta_clients;
+  reg               taskBuf_2_snpHitReleaseMeta_alias;
+  reg               taskBuf_2_snpHitReleaseMeta_prefetch;
+  reg               taskBuf_2_snpHitReleaseMeta_accessed;
+  reg               taskBuf_2_snpHitReleaseMeta_tagErr;
+  reg               taskBuf_2_snpHitReleaseMeta_dataErr;
+  reg               taskBuf_2_retToSrc;
+  reg               taskBuf_2_likelyshared;
+  reg               taskBuf_2_expCompAck;
+  reg               taskBuf_2_allowRetry;
+  reg               taskBuf_2_memAttr_allocate;
+  reg               taskBuf_2_memAttr_cacheable;
+  reg               taskBuf_2_memAttr_device;
+  reg               taskBuf_2_memAttr_ewa;
+  reg               taskBuf_2_traceTag;
+  reg  [2:0]        taskBuf_3_channel;
+  reg  [7:0]        taskBuf_3_set;
+  reg  [33:0]       taskBuf_3_tag;
+  reg  [5:0]        taskBuf_3_off;
+  reg               taskBuf_3_alias;
+  reg               taskBuf_3_isKeyword;
+  reg  [3:0]        taskBuf_3_opcode;
+  reg  [2:0]        taskBuf_3_param;
+  reg  [2:0]        taskBuf_3_size;
+  reg  [6:0]        taskBuf_3_sourceId;
+  reg  [1:0]        taskBuf_3_bufIdx;
+  reg               taskBuf_3_needProbeAckData;
+  reg               taskBuf_3_denied;
+  reg               taskBuf_3_corrupt;
+  reg               taskBuf_3_mshrTask;
+  reg               taskBuf_3_aliasTask;
+  reg               taskBuf_3_useProbeData;
+  reg               taskBuf_3_mshrRetry;
+  reg               taskBuf_3_readProbeDataDown;
+  reg               taskBuf_3_fromL2pft;
+  reg               taskBuf_3_needHint;
+  reg               taskBuf_3_dirty;
+  reg               taskBuf_3_meta_dirty;
+  reg               taskBuf_3_meta_clients;
+  reg               taskBuf_3_meta_alias;
+  reg               taskBuf_3_meta_prefetch;
+  reg               taskBuf_3_meta_accessed;
+  reg               taskBuf_3_meta_tagErr;
+  reg               taskBuf_3_meta_dataErr;
+  reg               taskBuf_3_metaWen;
+  reg               taskBuf_3_tagWen;
+  reg               taskBuf_3_dsWen;
+  reg  [7:0]        taskBuf_3_wayMask;
+  reg               taskBuf_3_replTask;
+  reg               taskBuf_3_cmoTask;
+  reg               taskBuf_3_cmoAll;
+  reg               taskBuf_3_mergeA;
+  reg               taskBuf_3_aMergeTask_alias;
+  reg               taskBuf_3_aMergeTask_isKeyword;
+  reg               taskBuf_3_aMergeTask_meta_dirty;
+  reg               taskBuf_3_aMergeTask_meta_clients;
+  reg               taskBuf_3_aMergeTask_meta_alias;
+  reg               taskBuf_3_aMergeTask_meta_prefetch;
+  reg               taskBuf_3_aMergeTask_meta_accessed;
+  reg               taskBuf_3_aMergeTask_meta_tagErr;
+  reg               taskBuf_3_aMergeTask_meta_dataErr;
+  reg               taskBuf_3_snpHitRelease;
+  reg               taskBuf_3_snpHitReleaseToInval;
+  reg               taskBuf_3_snpHitReleaseToClean;
+  reg               taskBuf_3_snpHitReleaseWithData;
+  reg               taskBuf_3_snpHitReleaseMeta_dirty;
+  reg               taskBuf_3_snpHitReleaseMeta_clients;
+  reg               taskBuf_3_snpHitReleaseMeta_alias;
+  reg               taskBuf_3_snpHitReleaseMeta_prefetch;
+  reg               taskBuf_3_snpHitReleaseMeta_accessed;
+  reg               taskBuf_3_snpHitReleaseMeta_tagErr;
+  reg               taskBuf_3_snpHitReleaseMeta_dataErr;
+  reg               taskBuf_3_retToSrc;
+  reg               taskBuf_3_likelyshared;
+  reg               taskBuf_3_expCompAck;
+  reg               taskBuf_3_allowRetry;
+  reg               taskBuf_3_memAttr_allocate;
+  reg               taskBuf_3_memAttr_cacheable;
+  reg               taskBuf_3_memAttr_device;
+  reg               taskBuf_3_memAttr_ewa;
+  reg               taskBuf_3_traceTag;
+  reg               taskValids_0;
+  reg               taskValids_1;
+  reg               taskValids_2;
+  reg               taskValids_3;
+  wire [3:0]        bufValids =
+    {taskValids_3, taskValids_2, taskValids_1, taskValids_0}
+    | {|{beatValids_3_1, beatValids_3_0},
+       |{beatValids_2_1, beatValids_2_0},
+       |{beatValids_1_1, beatValids_1_0},
+       |{beatValids_0_1, beatValids_0_0}};
+  reg  [1:0]        nextPtrReg;
+  wire              _io_releaseBufWrite_valid_T = io_c_bits_opcode == 3'h5;
+  reg  [255:0]      probeAckDataBuf;
+  wire              _newdataMask_WIRE_1 =
+    io_msInfo_1_valid & io_msInfo_1_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_1_bits_reqTag == _taskArb_io_out_bits_tag & io_msInfo_1_bits_blockRefill;
+  wire              _newdataMask_WIRE_2 =
+    io_msInfo_2_valid & io_msInfo_2_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_2_bits_reqTag == _taskArb_io_out_bits_tag & io_msInfo_2_bits_blockRefill;
+  wire              _newdataMask_WIRE_3 =
+    io_msInfo_3_valid & io_msInfo_3_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_3_bits_reqTag == _taskArb_io_out_bits_tag & io_msInfo_3_bits_blockRefill;
+  wire              _newdataMask_WIRE_4 =
+    io_msInfo_4_valid & io_msInfo_4_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_4_bits_reqTag == _taskArb_io_out_bits_tag & io_msInfo_4_bits_blockRefill;
+  wire              _newdataMask_WIRE_5 =
+    io_msInfo_5_valid & io_msInfo_5_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_5_bits_reqTag == _taskArb_io_out_bits_tag & io_msInfo_5_bits_blockRefill;
+  wire              _newdataMask_WIRE_6 =
+    io_msInfo_6_valid & io_msInfo_6_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_6_bits_reqTag == _taskArb_io_out_bits_tag & io_msInfo_6_bits_blockRefill;
+  wire              _newdataMask_WIRE_7 =
+    io_msInfo_7_valid & io_msInfo_7_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_7_bits_reqTag == _taskArb_io_out_bits_tag & io_msInfo_7_bits_blockRefill;
+  wire              _newdataMask_WIRE_8 =
+    io_msInfo_8_valid & io_msInfo_8_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_8_bits_reqTag == _taskArb_io_out_bits_tag & io_msInfo_8_bits_blockRefill;
+  wire              _newdataMask_WIRE_9 =
+    io_msInfo_9_valid & io_msInfo_9_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_9_bits_reqTag == _taskArb_io_out_bits_tag & io_msInfo_9_bits_blockRefill;
+  wire              _newdataMask_WIRE_10 =
+    io_msInfo_10_valid & io_msInfo_10_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_10_bits_reqTag == _taskArb_io_out_bits_tag
+    & io_msInfo_10_bits_blockRefill;
+  wire              _newdataMask_WIRE_11 =
+    io_msInfo_11_valid & io_msInfo_11_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_11_bits_reqTag == _taskArb_io_out_bits_tag
+    & io_msInfo_11_bits_blockRefill;
+  wire              _newdataMask_WIRE_12 =
+    io_msInfo_12_valid & io_msInfo_12_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_12_bits_reqTag == _taskArb_io_out_bits_tag
+    & io_msInfo_12_bits_blockRefill;
+  wire              _newdataMask_WIRE_13 =
+    io_msInfo_13_valid & io_msInfo_13_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_13_bits_reqTag == _taskArb_io_out_bits_tag
+    & io_msInfo_13_bits_blockRefill;
+  wire              _newdataMask_WIRE_14 =
+    io_msInfo_14_valid & io_msInfo_14_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_14_bits_reqTag == _taskArb_io_out_bits_tag
+    & io_msInfo_14_bits_blockRefill;
+  wire              _newdataMask_WIRE_15 =
+    io_msInfo_15_valid & io_msInfo_15_bits_set == _taskArb_io_out_bits_set
+    & io_msInfo_15_bits_reqTag == _taskArb_io_out_bits_tag
+    & io_msInfo_15_bits_blockRefill;
+  wire              _io_refillBufWrite_valid_T = io_task_ready & _taskArb_io_out_valid;
+  reg               io_refillBufWrite_valid_REG;
+  reg  [3:0]        io_refillBufWrite_bits_id_REG;
+  reg  [1:0]        io_refillBufWrite_bits_data_data_REG;
+  wire [3:0][255:0] _GEN = {{dataBuf_3_0}, {dataBuf_2_0}, {dataBuf_1_0}, {dataBuf_0_0}};
+  wire [3:0][255:0] _GEN_0 = {{dataBuf_3_1}, {dataBuf_2_1}, {dataBuf_1_1}, {dataBuf_0_1}};
+  wire              io_c_ready_0 = ~(io_c_bits_opcode[1]) | r_counter | bufValids != 4'hF;
+  reg  [255:0]      r_0;
+  reg  [255:0]      r_1;
+  reg  [255:0]      REG_0;
+  reg  [255:0]      REG_1;
+  reg               REG_1_0;
+  reg  [1:0]        REG_2;
+  wire              taskBuf_task_corrupt =
+    io_c_bits_corrupt & (io_c_bits_opcode == 3'h5 | (&io_c_bits_opcode));
+  wire              taskBuf_task_denied =
+    io_c_bits_corrupt & (io_c_bits_opcode == 3'h4 | io_c_bits_opcode == 3'h6);
+  wire              taskBuf_task_1_corrupt =
+    io_c_bits_corrupt & (io_c_bits_opcode == 3'h5 | (&io_c_bits_opcode));
+  wire              taskBuf_task_1_denied =
+    io_c_bits_corrupt & (io_c_bits_opcode == 3'h4 | io_c_bits_opcode == 3'h6);
+  wire              _nextPtrReg_T = io_c_ready_0 & io_c_valid;
+  wire              _r_counter1_T = 1'(r_counter - 1'h1);
+  wire              beat = r_beats1 & ~_r_counter1_T;
+  wire [2:0]        _nextPtr_T = ~(bufValids[2:0]);
+  wire [1:0]        nextPtr =
+    _nextPtr_T[0] ? 2'h0 : _nextPtr_T[1] ? 2'h1 : {1'h1, ~(_nextPtr_T[2])};
+  wire              _GEN_1 = _nextPtrReg_T & io_c_bits_opcode[1];
+  wire              _GEN_2 = nextPtr == 2'h0;
+  wire              _GEN_3 = _GEN_2 & ~beat;
+  wire              _GEN_4 = _GEN_2 & beat;
+  wire              _GEN_5 = nextPtr == 2'h1;
+  wire              _GEN_6 = _GEN_5 & ~beat;
+  wire              _GEN_7 = _GEN_5 & beat;
+  wire              _GEN_8 = nextPtr == 2'h2;
+  wire              _GEN_9 = _GEN_8 & ~beat;
+  wire              _GEN_10 = _GEN_8 & beat;
+  wire              _GEN_11 = (&nextPtr) & ~beat;
+  wire              _GEN_12 = (&nextPtr) & beat;
+  wire              _GEN_13 = nextPtrReg == 2'h0;
+  wire              _GEN_14 = _GEN_13 & ~beat;
+  wire              _GEN_15 = _GEN_1 & io_c_bits_opcode[0];
+  wire              _GEN_16 = _GEN_13 & beat;
+  wire              _GEN_17 = nextPtrReg == 2'h1;
+  wire              _GEN_18 = _GEN_17 & ~beat;
+  wire              _GEN_19 = _GEN_17 & beat;
+  wire              _GEN_20 = nextPtrReg == 2'h2;
+  wire              _GEN_21 = _GEN_20 & ~beat;
+  wire              _GEN_22 = _GEN_20 & beat;
+  wire              _GEN_23 = (&nextPtrReg) & ~beat;
+  wire              _GEN_24 = (&nextPtrReg) & beat;
+  wire              _GEN_25 = _GEN_1 & last;
+  wire [3:0]        _GEN_26 = {1'h0, io_c_bits_opcode};
+  wire              _GEN_27 = _GEN_25 & (io_c_bits_opcode[0] ? _GEN_13 : _GEN_2);
+  wire              _GEN_28 = REG_1_0 & REG_2 == 2'h0;
+  wire              _GEN_29 = REG_1_0 & REG_2 == 2'h1;
+  wire              _GEN_30 = REG_1_0 & REG_2 == 2'h2;
+  wire              _GEN_31 = REG_1_0 & (&REG_2);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      r_counter <= 1'h0;
+      dataBuf_0_0 <= 256'h0;
+      dataBuf_0_1 <= 256'h0;
+      dataBuf_1_0 <= 256'h0;
+      dataBuf_1_1 <= 256'h0;
+      dataBuf_2_0 <= 256'h0;
+      dataBuf_2_1 <= 256'h0;
+      dataBuf_3_0 <= 256'h0;
+      dataBuf_3_1 <= 256'h0;
+      beatValids_0_0 <= 1'h0;
+      beatValids_0_1 <= 1'h0;
+      beatValids_1_0 <= 1'h0;
+      beatValids_1_1 <= 1'h0;
+      beatValids_2_0 <= 1'h0;
+      beatValids_2_1 <= 1'h0;
+      beatValids_3_0 <= 1'h0;
+      beatValids_3_1 <= 1'h0;
+      taskBuf_0_channel <= 3'h0;
+      taskBuf_0_set <= 8'h0;
+      taskBuf_0_tag <= 34'h0;
+      taskBuf_0_off <= 6'h0;
+      taskBuf_0_alias <= 1'h0;
+      taskBuf_0_isKeyword <= 1'h0;
+      taskBuf_0_opcode <= 4'h0;
+      taskBuf_0_param <= 3'h0;
+      taskBuf_0_size <= 3'h0;
+      taskBuf_0_sourceId <= 7'h0;
+      taskBuf_0_bufIdx <= 2'h0;
+      taskBuf_0_needProbeAckData <= 1'h0;
+      taskBuf_0_denied <= 1'h0;
+      taskBuf_0_corrupt <= 1'h0;
+      taskBuf_0_mshrTask <= 1'h0;
+      taskBuf_0_aliasTask <= 1'h0;
+      taskBuf_0_useProbeData <= 1'h0;
+      taskBuf_0_mshrRetry <= 1'h0;
+      taskBuf_0_readProbeDataDown <= 1'h0;
+      taskBuf_0_fromL2pft <= 1'h0;
+      taskBuf_0_needHint <= 1'h0;
+      taskBuf_0_dirty <= 1'h0;
+      taskBuf_0_meta_dirty <= 1'h0;
+      taskBuf_0_meta_clients <= 1'h0;
+      taskBuf_0_meta_alias <= 1'h0;
+      taskBuf_0_meta_prefetch <= 1'h0;
+      taskBuf_0_meta_accessed <= 1'h0;
+      taskBuf_0_meta_tagErr <= 1'h0;
+      taskBuf_0_meta_dataErr <= 1'h0;
+      taskBuf_0_metaWen <= 1'h0;
+      taskBuf_0_tagWen <= 1'h0;
+      taskBuf_0_dsWen <= 1'h0;
+      taskBuf_0_wayMask <= 8'h0;
+      taskBuf_0_replTask <= 1'h0;
+      taskBuf_0_cmoTask <= 1'h0;
+      taskBuf_0_cmoAll <= 1'h0;
+      taskBuf_0_mergeA <= 1'h0;
+      taskBuf_0_aMergeTask_alias <= 1'h0;
+      taskBuf_0_aMergeTask_isKeyword <= 1'h0;
+      taskBuf_0_aMergeTask_meta_dirty <= 1'h0;
+      taskBuf_0_aMergeTask_meta_clients <= 1'h0;
+      taskBuf_0_aMergeTask_meta_alias <= 1'h0;
+      taskBuf_0_aMergeTask_meta_prefetch <= 1'h0;
+      taskBuf_0_aMergeTask_meta_accessed <= 1'h0;
+      taskBuf_0_aMergeTask_meta_tagErr <= 1'h0;
+      taskBuf_0_aMergeTask_meta_dataErr <= 1'h0;
+      taskBuf_0_snpHitRelease <= 1'h0;
+      taskBuf_0_snpHitReleaseToInval <= 1'h0;
+      taskBuf_0_snpHitReleaseToClean <= 1'h0;
+      taskBuf_0_snpHitReleaseWithData <= 1'h0;
+      taskBuf_0_snpHitReleaseMeta_dirty <= 1'h0;
+      taskBuf_0_snpHitReleaseMeta_clients <= 1'h0;
+      taskBuf_0_snpHitReleaseMeta_alias <= 1'h0;
+      taskBuf_0_snpHitReleaseMeta_prefetch <= 1'h0;
+      taskBuf_0_snpHitReleaseMeta_accessed <= 1'h0;
+      taskBuf_0_snpHitReleaseMeta_tagErr <= 1'h0;
+      taskBuf_0_snpHitReleaseMeta_dataErr <= 1'h0;
+      taskBuf_0_retToSrc <= 1'h0;
+      taskBuf_0_likelyshared <= 1'h0;
+      taskBuf_0_expCompAck <= 1'h0;
+      taskBuf_0_allowRetry <= 1'h0;
+      taskBuf_0_memAttr_allocate <= 1'h0;
+      taskBuf_0_memAttr_cacheable <= 1'h0;
+      taskBuf_0_memAttr_device <= 1'h0;
+      taskBuf_0_memAttr_ewa <= 1'h0;
+      taskBuf_0_traceTag <= 1'h0;
+      taskBuf_1_channel <= 3'h0;
+      taskBuf_1_set <= 8'h0;
+      taskBuf_1_tag <= 34'h0;
+      taskBuf_1_off <= 6'h0;
+      taskBuf_1_alias <= 1'h0;
+      taskBuf_1_isKeyword <= 1'h0;
+      taskBuf_1_opcode <= 4'h0;
+      taskBuf_1_param <= 3'h0;
+      taskBuf_1_size <= 3'h0;
+      taskBuf_1_sourceId <= 7'h0;
+      taskBuf_1_bufIdx <= 2'h0;
+      taskBuf_1_needProbeAckData <= 1'h0;
+      taskBuf_1_denied <= 1'h0;
+      taskBuf_1_corrupt <= 1'h0;
+      taskBuf_1_mshrTask <= 1'h0;
+      taskBuf_1_aliasTask <= 1'h0;
+      taskBuf_1_useProbeData <= 1'h0;
+      taskBuf_1_mshrRetry <= 1'h0;
+      taskBuf_1_readProbeDataDown <= 1'h0;
+      taskBuf_1_fromL2pft <= 1'h0;
+      taskBuf_1_needHint <= 1'h0;
+      taskBuf_1_dirty <= 1'h0;
+      taskBuf_1_meta_dirty <= 1'h0;
+      taskBuf_1_meta_clients <= 1'h0;
+      taskBuf_1_meta_alias <= 1'h0;
+      taskBuf_1_meta_prefetch <= 1'h0;
+      taskBuf_1_meta_accessed <= 1'h0;
+      taskBuf_1_meta_tagErr <= 1'h0;
+      taskBuf_1_meta_dataErr <= 1'h0;
+      taskBuf_1_metaWen <= 1'h0;
+      taskBuf_1_tagWen <= 1'h0;
+      taskBuf_1_dsWen <= 1'h0;
+      taskBuf_1_wayMask <= 8'h0;
+      taskBuf_1_replTask <= 1'h0;
+      taskBuf_1_cmoTask <= 1'h0;
+      taskBuf_1_cmoAll <= 1'h0;
+      taskBuf_1_mergeA <= 1'h0;
+      taskBuf_1_aMergeTask_alias <= 1'h0;
+      taskBuf_1_aMergeTask_isKeyword <= 1'h0;
+      taskBuf_1_aMergeTask_meta_dirty <= 1'h0;
+      taskBuf_1_aMergeTask_meta_clients <= 1'h0;
+      taskBuf_1_aMergeTask_meta_alias <= 1'h0;
+      taskBuf_1_aMergeTask_meta_prefetch <= 1'h0;
+      taskBuf_1_aMergeTask_meta_accessed <= 1'h0;
+      taskBuf_1_aMergeTask_meta_tagErr <= 1'h0;
+      taskBuf_1_aMergeTask_meta_dataErr <= 1'h0;
+      taskBuf_1_snpHitRelease <= 1'h0;
+      taskBuf_1_snpHitReleaseToInval <= 1'h0;
+      taskBuf_1_snpHitReleaseToClean <= 1'h0;
+      taskBuf_1_snpHitReleaseWithData <= 1'h0;
+      taskBuf_1_snpHitReleaseMeta_dirty <= 1'h0;
+      taskBuf_1_snpHitReleaseMeta_clients <= 1'h0;
+      taskBuf_1_snpHitReleaseMeta_alias <= 1'h0;
+      taskBuf_1_snpHitReleaseMeta_prefetch <= 1'h0;
+      taskBuf_1_snpHitReleaseMeta_accessed <= 1'h0;
+      taskBuf_1_snpHitReleaseMeta_tagErr <= 1'h0;
+      taskBuf_1_snpHitReleaseMeta_dataErr <= 1'h0;
+      taskBuf_1_retToSrc <= 1'h0;
+      taskBuf_1_likelyshared <= 1'h0;
+      taskBuf_1_expCompAck <= 1'h0;
+      taskBuf_1_allowRetry <= 1'h0;
+      taskBuf_1_memAttr_allocate <= 1'h0;
+      taskBuf_1_memAttr_cacheable <= 1'h0;
+      taskBuf_1_memAttr_device <= 1'h0;
+      taskBuf_1_memAttr_ewa <= 1'h0;
+      taskBuf_1_traceTag <= 1'h0;
+      taskBuf_2_channel <= 3'h0;
+      taskBuf_2_set <= 8'h0;
+      taskBuf_2_tag <= 34'h0;
+      taskBuf_2_off <= 6'h0;
+      taskBuf_2_alias <= 1'h0;
+      taskBuf_2_isKeyword <= 1'h0;
+      taskBuf_2_opcode <= 4'h0;
+      taskBuf_2_param <= 3'h0;
+      taskBuf_2_size <= 3'h0;
+      taskBuf_2_sourceId <= 7'h0;
+      taskBuf_2_bufIdx <= 2'h0;
+      taskBuf_2_needProbeAckData <= 1'h0;
+      taskBuf_2_denied <= 1'h0;
+      taskBuf_2_corrupt <= 1'h0;
+      taskBuf_2_mshrTask <= 1'h0;
+      taskBuf_2_aliasTask <= 1'h0;
+      taskBuf_2_useProbeData <= 1'h0;
+      taskBuf_2_mshrRetry <= 1'h0;
+      taskBuf_2_readProbeDataDown <= 1'h0;
+      taskBuf_2_fromL2pft <= 1'h0;
+      taskBuf_2_needHint <= 1'h0;
+      taskBuf_2_dirty <= 1'h0;
+      taskBuf_2_meta_dirty <= 1'h0;
+      taskBuf_2_meta_clients <= 1'h0;
+      taskBuf_2_meta_alias <= 1'h0;
+      taskBuf_2_meta_prefetch <= 1'h0;
+      taskBuf_2_meta_accessed <= 1'h0;
+      taskBuf_2_meta_tagErr <= 1'h0;
+      taskBuf_2_meta_dataErr <= 1'h0;
+      taskBuf_2_metaWen <= 1'h0;
+      taskBuf_2_tagWen <= 1'h0;
+      taskBuf_2_dsWen <= 1'h0;
+      taskBuf_2_wayMask <= 8'h0;
+      taskBuf_2_replTask <= 1'h0;
+      taskBuf_2_cmoTask <= 1'h0;
+      taskBuf_2_cmoAll <= 1'h0;
+      taskBuf_2_mergeA <= 1'h0;
+      taskBuf_2_aMergeTask_alias <= 1'h0;
+      taskBuf_2_aMergeTask_isKeyword <= 1'h0;
+      taskBuf_2_aMergeTask_meta_dirty <= 1'h0;
+      taskBuf_2_aMergeTask_meta_clients <= 1'h0;
+      taskBuf_2_aMergeTask_meta_alias <= 1'h0;
+      taskBuf_2_aMergeTask_meta_prefetch <= 1'h0;
+      taskBuf_2_aMergeTask_meta_accessed <= 1'h0;
+      taskBuf_2_aMergeTask_meta_tagErr <= 1'h0;
+      taskBuf_2_aMergeTask_meta_dataErr <= 1'h0;
+      taskBuf_2_snpHitRelease <= 1'h0;
+      taskBuf_2_snpHitReleaseToInval <= 1'h0;
+      taskBuf_2_snpHitReleaseToClean <= 1'h0;
+      taskBuf_2_snpHitReleaseWithData <= 1'h0;
+      taskBuf_2_snpHitReleaseMeta_dirty <= 1'h0;
+      taskBuf_2_snpHitReleaseMeta_clients <= 1'h0;
+      taskBuf_2_snpHitReleaseMeta_alias <= 1'h0;
+      taskBuf_2_snpHitReleaseMeta_prefetch <= 1'h0;
+      taskBuf_2_snpHitReleaseMeta_accessed <= 1'h0;
+      taskBuf_2_snpHitReleaseMeta_tagErr <= 1'h0;
+      taskBuf_2_snpHitReleaseMeta_dataErr <= 1'h0;
+      taskBuf_2_retToSrc <= 1'h0;
+      taskBuf_2_likelyshared <= 1'h0;
+      taskBuf_2_expCompAck <= 1'h0;
+      taskBuf_2_allowRetry <= 1'h0;
+      taskBuf_2_memAttr_allocate <= 1'h0;
+      taskBuf_2_memAttr_cacheable <= 1'h0;
+      taskBuf_2_memAttr_device <= 1'h0;
+      taskBuf_2_memAttr_ewa <= 1'h0;
+      taskBuf_2_traceTag <= 1'h0;
+      taskBuf_3_channel <= 3'h0;
+      taskBuf_3_set <= 8'h0;
+      taskBuf_3_tag <= 34'h0;
+      taskBuf_3_off <= 6'h0;
+      taskBuf_3_alias <= 1'h0;
+      taskBuf_3_isKeyword <= 1'h0;
+      taskBuf_3_opcode <= 4'h0;
+      taskBuf_3_param <= 3'h0;
+      taskBuf_3_size <= 3'h0;
+      taskBuf_3_sourceId <= 7'h0;
+      taskBuf_3_bufIdx <= 2'h0;
+      taskBuf_3_needProbeAckData <= 1'h0;
+      taskBuf_3_denied <= 1'h0;
+      taskBuf_3_corrupt <= 1'h0;
+      taskBuf_3_mshrTask <= 1'h0;
+      taskBuf_3_aliasTask <= 1'h0;
+      taskBuf_3_useProbeData <= 1'h0;
+      taskBuf_3_mshrRetry <= 1'h0;
+      taskBuf_3_readProbeDataDown <= 1'h0;
+      taskBuf_3_fromL2pft <= 1'h0;
+      taskBuf_3_needHint <= 1'h0;
+      taskBuf_3_dirty <= 1'h0;
+      taskBuf_3_meta_dirty <= 1'h0;
+      taskBuf_3_meta_clients <= 1'h0;
+      taskBuf_3_meta_alias <= 1'h0;
+      taskBuf_3_meta_prefetch <= 1'h0;
+      taskBuf_3_meta_accessed <= 1'h0;
+      taskBuf_3_meta_tagErr <= 1'h0;
+      taskBuf_3_meta_dataErr <= 1'h0;
+      taskBuf_3_metaWen <= 1'h0;
+      taskBuf_3_tagWen <= 1'h0;
+      taskBuf_3_dsWen <= 1'h0;
+      taskBuf_3_wayMask <= 8'h0;
+      taskBuf_3_replTask <= 1'h0;
+      taskBuf_3_cmoTask <= 1'h0;
+      taskBuf_3_cmoAll <= 1'h0;
+      taskBuf_3_mergeA <= 1'h0;
+      taskBuf_3_aMergeTask_alias <= 1'h0;
+      taskBuf_3_aMergeTask_isKeyword <= 1'h0;
+      taskBuf_3_aMergeTask_meta_dirty <= 1'h0;
+      taskBuf_3_aMergeTask_meta_clients <= 1'h0;
+      taskBuf_3_aMergeTask_meta_alias <= 1'h0;
+      taskBuf_3_aMergeTask_meta_prefetch <= 1'h0;
+      taskBuf_3_aMergeTask_meta_accessed <= 1'h0;
+      taskBuf_3_aMergeTask_meta_tagErr <= 1'h0;
+      taskBuf_3_aMergeTask_meta_dataErr <= 1'h0;
+      taskBuf_3_snpHitRelease <= 1'h0;
+      taskBuf_3_snpHitReleaseToInval <= 1'h0;
+      taskBuf_3_snpHitReleaseToClean <= 1'h0;
+      taskBuf_3_snpHitReleaseWithData <= 1'h0;
+      taskBuf_3_snpHitReleaseMeta_dirty <= 1'h0;
+      taskBuf_3_snpHitReleaseMeta_clients <= 1'h0;
+      taskBuf_3_snpHitReleaseMeta_alias <= 1'h0;
+      taskBuf_3_snpHitReleaseMeta_prefetch <= 1'h0;
+      taskBuf_3_snpHitReleaseMeta_accessed <= 1'h0;
+      taskBuf_3_snpHitReleaseMeta_tagErr <= 1'h0;
+      taskBuf_3_snpHitReleaseMeta_dataErr <= 1'h0;
+      taskBuf_3_retToSrc <= 1'h0;
+      taskBuf_3_likelyshared <= 1'h0;
+      taskBuf_3_expCompAck <= 1'h0;
+      taskBuf_3_allowRetry <= 1'h0;
+      taskBuf_3_memAttr_allocate <= 1'h0;
+      taskBuf_3_memAttr_cacheable <= 1'h0;
+      taskBuf_3_memAttr_device <= 1'h0;
+      taskBuf_3_memAttr_ewa <= 1'h0;
+      taskBuf_3_traceTag <= 1'h0;
+      taskValids_0 <= 1'h0;
+      taskValids_1 <= 1'h0;
+      taskValids_2 <= 1'h0;
+      taskValids_3 <= 1'h0;
+      nextPtrReg <= 2'h0;
+      probeAckDataBuf <= 256'h0;
+      io_refillBufWrite_valid_REG <= 1'h0;
+    end
+    else begin
+      if (_nextPtrReg_T) begin
+        if (r_counter)
+          r_counter <= _r_counter1_T;
+        else
+          r_counter <= r_beats1;
+      end
+      if (_GEN_15 & (r_counter ? _GEN_14 : _GEN_3))
+        dataBuf_0_0 <= io_c_bits_data;
+      if (_GEN_15 & (r_counter ? _GEN_16 : _GEN_4))
+        dataBuf_0_1 <= io_c_bits_data;
+      if (_GEN_15 & (r_counter ? _GEN_18 : _GEN_6))
+        dataBuf_1_0 <= io_c_bits_data;
+      if (_GEN_15 & (r_counter ? _GEN_19 : _GEN_7))
+        dataBuf_1_1 <= io_c_bits_data;
+      if (_GEN_15 & (r_counter ? _GEN_21 : _GEN_9))
+        dataBuf_2_0 <= io_c_bits_data;
+      if (_GEN_15 & (r_counter ? _GEN_22 : _GEN_10))
+        dataBuf_2_1 <= io_c_bits_data;
+      if (_GEN_15 & (r_counter ? _GEN_23 : _GEN_11))
+        dataBuf_3_0 <= io_c_bits_data;
+      if (_GEN_15 & (r_counter ? _GEN_24 : _GEN_12))
+        dataBuf_3_1 <= io_c_bits_data;
+      beatValids_0_0 <=
+        ~_GEN_28
+        & (_GEN_15
+             ? (r_counter ? _GEN_14 | beatValids_0_0 : _GEN_3 | beatValids_0_0)
+             : beatValids_0_0);
+      beatValids_0_1 <=
+        ~_GEN_28
+        & (_GEN_15
+             ? (r_counter ? _GEN_16 | beatValids_0_1 : _GEN_4 | beatValids_0_1)
+             : beatValids_0_1);
+      beatValids_1_0 <=
+        ~_GEN_29
+        & (_GEN_15
+             ? (r_counter ? _GEN_18 | beatValids_1_0 : _GEN_6 | beatValids_1_0)
+             : beatValids_1_0);
+      beatValids_1_1 <=
+        ~_GEN_29
+        & (_GEN_15
+             ? (r_counter ? _GEN_19 | beatValids_1_1 : _GEN_7 | beatValids_1_1)
+             : beatValids_1_1);
+      beatValids_2_0 <=
+        ~_GEN_30
+        & (_GEN_15
+             ? (r_counter ? _GEN_21 | beatValids_2_0 : _GEN_9 | beatValids_2_0)
+             : beatValids_2_0);
+      beatValids_2_1 <=
+        ~_GEN_30
+        & (_GEN_15
+             ? (r_counter ? _GEN_22 | beatValids_2_1 : _GEN_10 | beatValids_2_1)
+             : beatValids_2_1);
+      beatValids_3_0 <=
+        ~_GEN_31
+        & (_GEN_15
+             ? (r_counter ? _GEN_23 | beatValids_3_0 : _GEN_11 | beatValids_3_0)
+             : beatValids_3_0);
+      beatValids_3_1 <=
+        ~_GEN_31
+        & (_GEN_15
+             ? (r_counter ? _GEN_24 | beatValids_3_1 : _GEN_12 | beatValids_3_1)
+             : beatValids_3_1);
+      if (_GEN_27)
+        taskBuf_0_channel <= 3'h4;
+      if (_GEN_25) begin
+        if (io_c_bits_opcode[0]) begin
+          if (_GEN_13) begin
+            taskBuf_0_set <= io_c_bits_address[13:6];
+            taskBuf_0_tag <= io_c_bits_address[47:14];
+            taskBuf_0_off <= io_c_bits_address[5:0];
+            taskBuf_0_bufIdx <= nextPtrReg;
+            taskBuf_0_denied <= taskBuf_task_denied;
+            taskBuf_0_corrupt <= taskBuf_task_corrupt;
+          end
+          if (_GEN_17) begin
+            taskBuf_1_set <= io_c_bits_address[13:6];
+            taskBuf_1_tag <= io_c_bits_address[47:14];
+            taskBuf_1_off <= io_c_bits_address[5:0];
+            taskBuf_1_bufIdx <= nextPtrReg;
+            taskBuf_1_denied <= taskBuf_task_denied;
+            taskBuf_1_corrupt <= taskBuf_task_corrupt;
+          end
+          if (_GEN_20) begin
+            taskBuf_2_set <= io_c_bits_address[13:6];
+            taskBuf_2_tag <= io_c_bits_address[47:14];
+            taskBuf_2_off <= io_c_bits_address[5:0];
+            taskBuf_2_bufIdx <= nextPtrReg;
+            taskBuf_2_denied <= taskBuf_task_denied;
+            taskBuf_2_corrupt <= taskBuf_task_corrupt;
+          end
+          if (&nextPtrReg) begin
+            taskBuf_3_set <= io_c_bits_address[13:6];
+            taskBuf_3_tag <= io_c_bits_address[47:14];
+            taskBuf_3_off <= io_c_bits_address[5:0];
+            taskBuf_3_bufIdx <= nextPtrReg;
+            taskBuf_3_denied <= taskBuf_task_denied;
+            taskBuf_3_corrupt <= taskBuf_task_corrupt;
+          end
+        end
+        else begin
+          if (_GEN_2) begin
+            taskBuf_0_set <= io_c_bits_address[13:6];
+            taskBuf_0_tag <= io_c_bits_address[47:14];
+            taskBuf_0_off <= io_c_bits_address[5:0];
+            taskBuf_0_bufIdx <= nextPtr;
+            taskBuf_0_denied <= taskBuf_task_1_denied;
+            taskBuf_0_corrupt <= taskBuf_task_1_corrupt;
+          end
+          if (_GEN_5) begin
+            taskBuf_1_set <= io_c_bits_address[13:6];
+            taskBuf_1_tag <= io_c_bits_address[47:14];
+            taskBuf_1_off <= io_c_bits_address[5:0];
+            taskBuf_1_bufIdx <= nextPtr;
+            taskBuf_1_denied <= taskBuf_task_1_denied;
+            taskBuf_1_corrupt <= taskBuf_task_1_corrupt;
+          end
+          if (_GEN_8) begin
+            taskBuf_2_set <= io_c_bits_address[13:6];
+            taskBuf_2_tag <= io_c_bits_address[47:14];
+            taskBuf_2_off <= io_c_bits_address[5:0];
+            taskBuf_2_bufIdx <= nextPtr;
+            taskBuf_2_denied <= taskBuf_task_1_denied;
+            taskBuf_2_corrupt <= taskBuf_task_1_corrupt;
+          end
+          if (&nextPtr) begin
+            taskBuf_3_set <= io_c_bits_address[13:6];
+            taskBuf_3_tag <= io_c_bits_address[47:14];
+            taskBuf_3_off <= io_c_bits_address[5:0];
+            taskBuf_3_bufIdx <= nextPtr;
+            taskBuf_3_denied <= taskBuf_task_1_denied;
+            taskBuf_3_corrupt <= taskBuf_task_1_corrupt;
+          end
+        end
+        taskBuf_0_alias <=
+          io_c_bits_opcode[0] ? ~_GEN_13 & taskBuf_0_alias : ~_GEN_2 & taskBuf_0_alias;
+        taskBuf_0_isKeyword <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_isKeyword
+            : ~_GEN_2 & taskBuf_0_isKeyword;
+        taskBuf_0_needProbeAckData <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_needProbeAckData
+            : ~_GEN_2 & taskBuf_0_needProbeAckData;
+        taskBuf_0_mshrTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_mshrTask
+            : ~_GEN_2 & taskBuf_0_mshrTask;
+        taskBuf_0_aliasTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aliasTask
+            : ~_GEN_2 & taskBuf_0_aliasTask;
+        taskBuf_0_useProbeData <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_useProbeData
+            : ~_GEN_2 & taskBuf_0_useProbeData;
+        taskBuf_0_mshrRetry <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_mshrRetry
+            : ~_GEN_2 & taskBuf_0_mshrRetry;
+        taskBuf_0_readProbeDataDown <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_readProbeDataDown
+            : ~_GEN_2 & taskBuf_0_readProbeDataDown;
+        taskBuf_0_fromL2pft <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_fromL2pft
+            : ~_GEN_2 & taskBuf_0_fromL2pft;
+        taskBuf_0_needHint <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_needHint
+            : ~_GEN_2 & taskBuf_0_needHint;
+        taskBuf_0_dirty <=
+          io_c_bits_opcode[0] ? ~_GEN_13 & taskBuf_0_dirty : ~_GEN_2 & taskBuf_0_dirty;
+        taskBuf_0_meta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_meta_dirty
+            : ~_GEN_2 & taskBuf_0_meta_dirty;
+        taskBuf_0_meta_clients <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_meta_clients
+            : ~_GEN_2 & taskBuf_0_meta_clients;
+        taskBuf_0_meta_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_meta_alias
+            : ~_GEN_2 & taskBuf_0_meta_alias;
+        taskBuf_0_meta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_meta_prefetch
+            : ~_GEN_2 & taskBuf_0_meta_prefetch;
+        taskBuf_0_meta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_meta_accessed
+            : ~_GEN_2 & taskBuf_0_meta_accessed;
+        taskBuf_0_meta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_meta_tagErr
+            : ~_GEN_2 & taskBuf_0_meta_tagErr;
+        taskBuf_0_meta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_meta_dataErr
+            : ~_GEN_2 & taskBuf_0_meta_dataErr;
+        taskBuf_0_metaWen <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_metaWen
+            : ~_GEN_2 & taskBuf_0_metaWen;
+        taskBuf_0_tagWen <=
+          io_c_bits_opcode[0] ? ~_GEN_13 & taskBuf_0_tagWen : ~_GEN_2 & taskBuf_0_tagWen;
+        taskBuf_0_dsWen <=
+          io_c_bits_opcode[0] ? ~_GEN_13 & taskBuf_0_dsWen : ~_GEN_2 & taskBuf_0_dsWen;
+        taskBuf_0_replTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_replTask
+            : ~_GEN_2 & taskBuf_0_replTask;
+        taskBuf_0_cmoTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_cmoTask
+            : ~_GEN_2 & taskBuf_0_cmoTask;
+        taskBuf_0_cmoAll <=
+          io_c_bits_opcode[0] ? ~_GEN_13 & taskBuf_0_cmoAll : ~_GEN_2 & taskBuf_0_cmoAll;
+        taskBuf_0_mergeA <=
+          io_c_bits_opcode[0] ? ~_GEN_13 & taskBuf_0_mergeA : ~_GEN_2 & taskBuf_0_mergeA;
+        taskBuf_0_aMergeTask_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aMergeTask_alias
+            : ~_GEN_2 & taskBuf_0_aMergeTask_alias;
+        taskBuf_0_aMergeTask_isKeyword <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aMergeTask_isKeyword
+            : ~_GEN_2 & taskBuf_0_aMergeTask_isKeyword;
+        taskBuf_0_aMergeTask_meta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aMergeTask_meta_dirty
+            : ~_GEN_2 & taskBuf_0_aMergeTask_meta_dirty;
+        taskBuf_0_aMergeTask_meta_clients <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aMergeTask_meta_clients
+            : ~_GEN_2 & taskBuf_0_aMergeTask_meta_clients;
+        taskBuf_0_aMergeTask_meta_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aMergeTask_meta_alias
+            : ~_GEN_2 & taskBuf_0_aMergeTask_meta_alias;
+        taskBuf_0_aMergeTask_meta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aMergeTask_meta_prefetch
+            : ~_GEN_2 & taskBuf_0_aMergeTask_meta_prefetch;
+        taskBuf_0_aMergeTask_meta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aMergeTask_meta_accessed
+            : ~_GEN_2 & taskBuf_0_aMergeTask_meta_accessed;
+        taskBuf_0_aMergeTask_meta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aMergeTask_meta_tagErr
+            : ~_GEN_2 & taskBuf_0_aMergeTask_meta_tagErr;
+        taskBuf_0_aMergeTask_meta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_aMergeTask_meta_dataErr
+            : ~_GEN_2 & taskBuf_0_aMergeTask_meta_dataErr;
+        taskBuf_0_snpHitRelease <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitRelease
+            : ~_GEN_2 & taskBuf_0_snpHitRelease;
+        taskBuf_0_snpHitReleaseToInval <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseToInval
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseToInval;
+        taskBuf_0_snpHitReleaseToClean <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseToClean
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseToClean;
+        taskBuf_0_snpHitReleaseWithData <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseWithData
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseWithData;
+        taskBuf_0_snpHitReleaseMeta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseMeta_dirty
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseMeta_dirty;
+        taskBuf_0_snpHitReleaseMeta_clients <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseMeta_clients
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseMeta_clients;
+        taskBuf_0_snpHitReleaseMeta_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseMeta_alias
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseMeta_alias;
+        taskBuf_0_snpHitReleaseMeta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseMeta_prefetch
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseMeta_prefetch;
+        taskBuf_0_snpHitReleaseMeta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseMeta_accessed
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseMeta_accessed;
+        taskBuf_0_snpHitReleaseMeta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseMeta_tagErr
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseMeta_tagErr;
+        taskBuf_0_snpHitReleaseMeta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_snpHitReleaseMeta_dataErr
+            : ~_GEN_2 & taskBuf_0_snpHitReleaseMeta_dataErr;
+        taskBuf_0_retToSrc <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_retToSrc
+            : ~_GEN_2 & taskBuf_0_retToSrc;
+        taskBuf_0_likelyshared <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_likelyshared
+            : ~_GEN_2 & taskBuf_0_likelyshared;
+        taskBuf_0_expCompAck <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_expCompAck
+            : ~_GEN_2 & taskBuf_0_expCompAck;
+        taskBuf_0_allowRetry <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_allowRetry
+            : ~_GEN_2 & taskBuf_0_allowRetry;
+        taskBuf_0_memAttr_allocate <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_memAttr_allocate
+            : ~_GEN_2 & taskBuf_0_memAttr_allocate;
+        taskBuf_0_memAttr_cacheable <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_memAttr_cacheable
+            : ~_GEN_2 & taskBuf_0_memAttr_cacheable;
+        taskBuf_0_memAttr_device <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_memAttr_device
+            : ~_GEN_2 & taskBuf_0_memAttr_device;
+        taskBuf_0_memAttr_ewa <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_memAttr_ewa
+            : ~_GEN_2 & taskBuf_0_memAttr_ewa;
+        taskBuf_0_traceTag <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_13 & taskBuf_0_traceTag
+            : ~_GEN_2 & taskBuf_0_traceTag;
+        taskBuf_1_alias <=
+          io_c_bits_opcode[0] ? ~_GEN_17 & taskBuf_1_alias : ~_GEN_5 & taskBuf_1_alias;
+        taskBuf_1_isKeyword <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_isKeyword
+            : ~_GEN_5 & taskBuf_1_isKeyword;
+        taskBuf_1_needProbeAckData <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_needProbeAckData
+            : ~_GEN_5 & taskBuf_1_needProbeAckData;
+        taskBuf_1_mshrTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_mshrTask
+            : ~_GEN_5 & taskBuf_1_mshrTask;
+        taskBuf_1_aliasTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aliasTask
+            : ~_GEN_5 & taskBuf_1_aliasTask;
+        taskBuf_1_useProbeData <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_useProbeData
+            : ~_GEN_5 & taskBuf_1_useProbeData;
+        taskBuf_1_mshrRetry <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_mshrRetry
+            : ~_GEN_5 & taskBuf_1_mshrRetry;
+        taskBuf_1_readProbeDataDown <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_readProbeDataDown
+            : ~_GEN_5 & taskBuf_1_readProbeDataDown;
+        taskBuf_1_fromL2pft <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_fromL2pft
+            : ~_GEN_5 & taskBuf_1_fromL2pft;
+        taskBuf_1_needHint <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_needHint
+            : ~_GEN_5 & taskBuf_1_needHint;
+        taskBuf_1_dirty <=
+          io_c_bits_opcode[0] ? ~_GEN_17 & taskBuf_1_dirty : ~_GEN_5 & taskBuf_1_dirty;
+        taskBuf_1_meta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_meta_dirty
+            : ~_GEN_5 & taskBuf_1_meta_dirty;
+        taskBuf_1_meta_clients <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_meta_clients
+            : ~_GEN_5 & taskBuf_1_meta_clients;
+        taskBuf_1_meta_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_meta_alias
+            : ~_GEN_5 & taskBuf_1_meta_alias;
+        taskBuf_1_meta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_meta_prefetch
+            : ~_GEN_5 & taskBuf_1_meta_prefetch;
+        taskBuf_1_meta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_meta_accessed
+            : ~_GEN_5 & taskBuf_1_meta_accessed;
+        taskBuf_1_meta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_meta_tagErr
+            : ~_GEN_5 & taskBuf_1_meta_tagErr;
+        taskBuf_1_meta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_meta_dataErr
+            : ~_GEN_5 & taskBuf_1_meta_dataErr;
+        taskBuf_1_metaWen <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_metaWen
+            : ~_GEN_5 & taskBuf_1_metaWen;
+        taskBuf_1_tagWen <=
+          io_c_bits_opcode[0] ? ~_GEN_17 & taskBuf_1_tagWen : ~_GEN_5 & taskBuf_1_tagWen;
+        taskBuf_1_dsWen <=
+          io_c_bits_opcode[0] ? ~_GEN_17 & taskBuf_1_dsWen : ~_GEN_5 & taskBuf_1_dsWen;
+        taskBuf_1_replTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_replTask
+            : ~_GEN_5 & taskBuf_1_replTask;
+        taskBuf_1_cmoTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_cmoTask
+            : ~_GEN_5 & taskBuf_1_cmoTask;
+        taskBuf_1_cmoAll <=
+          io_c_bits_opcode[0] ? ~_GEN_17 & taskBuf_1_cmoAll : ~_GEN_5 & taskBuf_1_cmoAll;
+        taskBuf_1_mergeA <=
+          io_c_bits_opcode[0] ? ~_GEN_17 & taskBuf_1_mergeA : ~_GEN_5 & taskBuf_1_mergeA;
+        taskBuf_1_aMergeTask_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aMergeTask_alias
+            : ~_GEN_5 & taskBuf_1_aMergeTask_alias;
+        taskBuf_1_aMergeTask_isKeyword <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aMergeTask_isKeyword
+            : ~_GEN_5 & taskBuf_1_aMergeTask_isKeyword;
+        taskBuf_1_aMergeTask_meta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aMergeTask_meta_dirty
+            : ~_GEN_5 & taskBuf_1_aMergeTask_meta_dirty;
+        taskBuf_1_aMergeTask_meta_clients <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aMergeTask_meta_clients
+            : ~_GEN_5 & taskBuf_1_aMergeTask_meta_clients;
+        taskBuf_1_aMergeTask_meta_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aMergeTask_meta_alias
+            : ~_GEN_5 & taskBuf_1_aMergeTask_meta_alias;
+        taskBuf_1_aMergeTask_meta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aMergeTask_meta_prefetch
+            : ~_GEN_5 & taskBuf_1_aMergeTask_meta_prefetch;
+        taskBuf_1_aMergeTask_meta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aMergeTask_meta_accessed
+            : ~_GEN_5 & taskBuf_1_aMergeTask_meta_accessed;
+        taskBuf_1_aMergeTask_meta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aMergeTask_meta_tagErr
+            : ~_GEN_5 & taskBuf_1_aMergeTask_meta_tagErr;
+        taskBuf_1_aMergeTask_meta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_aMergeTask_meta_dataErr
+            : ~_GEN_5 & taskBuf_1_aMergeTask_meta_dataErr;
+        taskBuf_1_snpHitRelease <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitRelease
+            : ~_GEN_5 & taskBuf_1_snpHitRelease;
+        taskBuf_1_snpHitReleaseToInval <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseToInval
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseToInval;
+        taskBuf_1_snpHitReleaseToClean <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseToClean
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseToClean;
+        taskBuf_1_snpHitReleaseWithData <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseWithData
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseWithData;
+        taskBuf_1_snpHitReleaseMeta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseMeta_dirty
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseMeta_dirty;
+        taskBuf_1_snpHitReleaseMeta_clients <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseMeta_clients
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseMeta_clients;
+        taskBuf_1_snpHitReleaseMeta_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseMeta_alias
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseMeta_alias;
+        taskBuf_1_snpHitReleaseMeta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseMeta_prefetch
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseMeta_prefetch;
+        taskBuf_1_snpHitReleaseMeta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseMeta_accessed
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseMeta_accessed;
+        taskBuf_1_snpHitReleaseMeta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseMeta_tagErr
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseMeta_tagErr;
+        taskBuf_1_snpHitReleaseMeta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_snpHitReleaseMeta_dataErr
+            : ~_GEN_5 & taskBuf_1_snpHitReleaseMeta_dataErr;
+        taskBuf_1_retToSrc <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_retToSrc
+            : ~_GEN_5 & taskBuf_1_retToSrc;
+        taskBuf_1_likelyshared <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_likelyshared
+            : ~_GEN_5 & taskBuf_1_likelyshared;
+        taskBuf_1_expCompAck <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_expCompAck
+            : ~_GEN_5 & taskBuf_1_expCompAck;
+        taskBuf_1_allowRetry <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_allowRetry
+            : ~_GEN_5 & taskBuf_1_allowRetry;
+        taskBuf_1_memAttr_allocate <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_memAttr_allocate
+            : ~_GEN_5 & taskBuf_1_memAttr_allocate;
+        taskBuf_1_memAttr_cacheable <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_memAttr_cacheable
+            : ~_GEN_5 & taskBuf_1_memAttr_cacheable;
+        taskBuf_1_memAttr_device <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_memAttr_device
+            : ~_GEN_5 & taskBuf_1_memAttr_device;
+        taskBuf_1_memAttr_ewa <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_memAttr_ewa
+            : ~_GEN_5 & taskBuf_1_memAttr_ewa;
+        taskBuf_1_traceTag <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_17 & taskBuf_1_traceTag
+            : ~_GEN_5 & taskBuf_1_traceTag;
+        taskBuf_2_alias <=
+          io_c_bits_opcode[0] ? ~_GEN_20 & taskBuf_2_alias : ~_GEN_8 & taskBuf_2_alias;
+        taskBuf_2_isKeyword <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_isKeyword
+            : ~_GEN_8 & taskBuf_2_isKeyword;
+        taskBuf_2_needProbeAckData <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_needProbeAckData
+            : ~_GEN_8 & taskBuf_2_needProbeAckData;
+        taskBuf_2_mshrTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_mshrTask
+            : ~_GEN_8 & taskBuf_2_mshrTask;
+        taskBuf_2_aliasTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aliasTask
+            : ~_GEN_8 & taskBuf_2_aliasTask;
+        taskBuf_2_useProbeData <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_useProbeData
+            : ~_GEN_8 & taskBuf_2_useProbeData;
+        taskBuf_2_mshrRetry <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_mshrRetry
+            : ~_GEN_8 & taskBuf_2_mshrRetry;
+        taskBuf_2_readProbeDataDown <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_readProbeDataDown
+            : ~_GEN_8 & taskBuf_2_readProbeDataDown;
+        taskBuf_2_fromL2pft <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_fromL2pft
+            : ~_GEN_8 & taskBuf_2_fromL2pft;
+        taskBuf_2_needHint <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_needHint
+            : ~_GEN_8 & taskBuf_2_needHint;
+        taskBuf_2_dirty <=
+          io_c_bits_opcode[0] ? ~_GEN_20 & taskBuf_2_dirty : ~_GEN_8 & taskBuf_2_dirty;
+        taskBuf_2_meta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_meta_dirty
+            : ~_GEN_8 & taskBuf_2_meta_dirty;
+        taskBuf_2_meta_clients <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_meta_clients
+            : ~_GEN_8 & taskBuf_2_meta_clients;
+        taskBuf_2_meta_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_meta_alias
+            : ~_GEN_8 & taskBuf_2_meta_alias;
+        taskBuf_2_meta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_meta_prefetch
+            : ~_GEN_8 & taskBuf_2_meta_prefetch;
+        taskBuf_2_meta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_meta_accessed
+            : ~_GEN_8 & taskBuf_2_meta_accessed;
+        taskBuf_2_meta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_meta_tagErr
+            : ~_GEN_8 & taskBuf_2_meta_tagErr;
+        taskBuf_2_meta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_meta_dataErr
+            : ~_GEN_8 & taskBuf_2_meta_dataErr;
+        taskBuf_2_metaWen <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_metaWen
+            : ~_GEN_8 & taskBuf_2_metaWen;
+        taskBuf_2_tagWen <=
+          io_c_bits_opcode[0] ? ~_GEN_20 & taskBuf_2_tagWen : ~_GEN_8 & taskBuf_2_tagWen;
+        taskBuf_2_dsWen <=
+          io_c_bits_opcode[0] ? ~_GEN_20 & taskBuf_2_dsWen : ~_GEN_8 & taskBuf_2_dsWen;
+        taskBuf_2_replTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_replTask
+            : ~_GEN_8 & taskBuf_2_replTask;
+        taskBuf_2_cmoTask <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_cmoTask
+            : ~_GEN_8 & taskBuf_2_cmoTask;
+        taskBuf_2_cmoAll <=
+          io_c_bits_opcode[0] ? ~_GEN_20 & taskBuf_2_cmoAll : ~_GEN_8 & taskBuf_2_cmoAll;
+        taskBuf_2_mergeA <=
+          io_c_bits_opcode[0] ? ~_GEN_20 & taskBuf_2_mergeA : ~_GEN_8 & taskBuf_2_mergeA;
+        taskBuf_2_aMergeTask_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aMergeTask_alias
+            : ~_GEN_8 & taskBuf_2_aMergeTask_alias;
+        taskBuf_2_aMergeTask_isKeyword <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aMergeTask_isKeyword
+            : ~_GEN_8 & taskBuf_2_aMergeTask_isKeyword;
+        taskBuf_2_aMergeTask_meta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aMergeTask_meta_dirty
+            : ~_GEN_8 & taskBuf_2_aMergeTask_meta_dirty;
+        taskBuf_2_aMergeTask_meta_clients <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aMergeTask_meta_clients
+            : ~_GEN_8 & taskBuf_2_aMergeTask_meta_clients;
+        taskBuf_2_aMergeTask_meta_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aMergeTask_meta_alias
+            : ~_GEN_8 & taskBuf_2_aMergeTask_meta_alias;
+        taskBuf_2_aMergeTask_meta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aMergeTask_meta_prefetch
+            : ~_GEN_8 & taskBuf_2_aMergeTask_meta_prefetch;
+        taskBuf_2_aMergeTask_meta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aMergeTask_meta_accessed
+            : ~_GEN_8 & taskBuf_2_aMergeTask_meta_accessed;
+        taskBuf_2_aMergeTask_meta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aMergeTask_meta_tagErr
+            : ~_GEN_8 & taskBuf_2_aMergeTask_meta_tagErr;
+        taskBuf_2_aMergeTask_meta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_aMergeTask_meta_dataErr
+            : ~_GEN_8 & taskBuf_2_aMergeTask_meta_dataErr;
+        taskBuf_2_snpHitRelease <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitRelease
+            : ~_GEN_8 & taskBuf_2_snpHitRelease;
+        taskBuf_2_snpHitReleaseToInval <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseToInval
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseToInval;
+        taskBuf_2_snpHitReleaseToClean <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseToClean
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseToClean;
+        taskBuf_2_snpHitReleaseWithData <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseWithData
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseWithData;
+        taskBuf_2_snpHitReleaseMeta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseMeta_dirty
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseMeta_dirty;
+        taskBuf_2_snpHitReleaseMeta_clients <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseMeta_clients
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseMeta_clients;
+        taskBuf_2_snpHitReleaseMeta_alias <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseMeta_alias
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseMeta_alias;
+        taskBuf_2_snpHitReleaseMeta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseMeta_prefetch
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseMeta_prefetch;
+        taskBuf_2_snpHitReleaseMeta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseMeta_accessed
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseMeta_accessed;
+        taskBuf_2_snpHitReleaseMeta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseMeta_tagErr
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseMeta_tagErr;
+        taskBuf_2_snpHitReleaseMeta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_snpHitReleaseMeta_dataErr
+            : ~_GEN_8 & taskBuf_2_snpHitReleaseMeta_dataErr;
+        taskBuf_2_retToSrc <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_retToSrc
+            : ~_GEN_8 & taskBuf_2_retToSrc;
+        taskBuf_2_likelyshared <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_likelyshared
+            : ~_GEN_8 & taskBuf_2_likelyshared;
+        taskBuf_2_expCompAck <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_expCompAck
+            : ~_GEN_8 & taskBuf_2_expCompAck;
+        taskBuf_2_allowRetry <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_allowRetry
+            : ~_GEN_8 & taskBuf_2_allowRetry;
+        taskBuf_2_memAttr_allocate <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_memAttr_allocate
+            : ~_GEN_8 & taskBuf_2_memAttr_allocate;
+        taskBuf_2_memAttr_cacheable <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_memAttr_cacheable
+            : ~_GEN_8 & taskBuf_2_memAttr_cacheable;
+        taskBuf_2_memAttr_device <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_memAttr_device
+            : ~_GEN_8 & taskBuf_2_memAttr_device;
+        taskBuf_2_memAttr_ewa <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_memAttr_ewa
+            : ~_GEN_8 & taskBuf_2_memAttr_ewa;
+        taskBuf_2_traceTag <=
+          io_c_bits_opcode[0]
+            ? ~_GEN_20 & taskBuf_2_traceTag
+            : ~_GEN_8 & taskBuf_2_traceTag;
+        taskBuf_3_alias <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_alias
+            : ~(&nextPtr) & taskBuf_3_alias;
+        taskBuf_3_isKeyword <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_isKeyword
+            : ~(&nextPtr) & taskBuf_3_isKeyword;
+        taskBuf_3_needProbeAckData <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_needProbeAckData
+            : ~(&nextPtr) & taskBuf_3_needProbeAckData;
+        taskBuf_3_mshrTask <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_mshrTask
+            : ~(&nextPtr) & taskBuf_3_mshrTask;
+        taskBuf_3_aliasTask <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aliasTask
+            : ~(&nextPtr) & taskBuf_3_aliasTask;
+        taskBuf_3_useProbeData <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_useProbeData
+            : ~(&nextPtr) & taskBuf_3_useProbeData;
+        taskBuf_3_mshrRetry <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_mshrRetry
+            : ~(&nextPtr) & taskBuf_3_mshrRetry;
+        taskBuf_3_readProbeDataDown <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_readProbeDataDown
+            : ~(&nextPtr) & taskBuf_3_readProbeDataDown;
+        taskBuf_3_fromL2pft <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_fromL2pft
+            : ~(&nextPtr) & taskBuf_3_fromL2pft;
+        taskBuf_3_needHint <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_needHint
+            : ~(&nextPtr) & taskBuf_3_needHint;
+        taskBuf_3_dirty <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_dirty
+            : ~(&nextPtr) & taskBuf_3_dirty;
+        taskBuf_3_meta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_meta_dirty
+            : ~(&nextPtr) & taskBuf_3_meta_dirty;
+        taskBuf_3_meta_clients <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_meta_clients
+            : ~(&nextPtr) & taskBuf_3_meta_clients;
+        taskBuf_3_meta_alias <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_meta_alias
+            : ~(&nextPtr) & taskBuf_3_meta_alias;
+        taskBuf_3_meta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_meta_prefetch
+            : ~(&nextPtr) & taskBuf_3_meta_prefetch;
+        taskBuf_3_meta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_meta_accessed
+            : ~(&nextPtr) & taskBuf_3_meta_accessed;
+        taskBuf_3_meta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_meta_tagErr
+            : ~(&nextPtr) & taskBuf_3_meta_tagErr;
+        taskBuf_3_meta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_meta_dataErr
+            : ~(&nextPtr) & taskBuf_3_meta_dataErr;
+        taskBuf_3_metaWen <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_metaWen
+            : ~(&nextPtr) & taskBuf_3_metaWen;
+        taskBuf_3_tagWen <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_tagWen
+            : ~(&nextPtr) & taskBuf_3_tagWen;
+        taskBuf_3_dsWen <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_dsWen
+            : ~(&nextPtr) & taskBuf_3_dsWen;
+        taskBuf_3_replTask <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_replTask
+            : ~(&nextPtr) & taskBuf_3_replTask;
+        taskBuf_3_cmoTask <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_cmoTask
+            : ~(&nextPtr) & taskBuf_3_cmoTask;
+        taskBuf_3_cmoAll <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_cmoAll
+            : ~(&nextPtr) & taskBuf_3_cmoAll;
+        taskBuf_3_mergeA <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_mergeA
+            : ~(&nextPtr) & taskBuf_3_mergeA;
+        taskBuf_3_aMergeTask_alias <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aMergeTask_alias
+            : ~(&nextPtr) & taskBuf_3_aMergeTask_alias;
+        taskBuf_3_aMergeTask_isKeyword <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aMergeTask_isKeyword
+            : ~(&nextPtr) & taskBuf_3_aMergeTask_isKeyword;
+        taskBuf_3_aMergeTask_meta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aMergeTask_meta_dirty
+            : ~(&nextPtr) & taskBuf_3_aMergeTask_meta_dirty;
+        taskBuf_3_aMergeTask_meta_clients <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aMergeTask_meta_clients
+            : ~(&nextPtr) & taskBuf_3_aMergeTask_meta_clients;
+        taskBuf_3_aMergeTask_meta_alias <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aMergeTask_meta_alias
+            : ~(&nextPtr) & taskBuf_3_aMergeTask_meta_alias;
+        taskBuf_3_aMergeTask_meta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aMergeTask_meta_prefetch
+            : ~(&nextPtr) & taskBuf_3_aMergeTask_meta_prefetch;
+        taskBuf_3_aMergeTask_meta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aMergeTask_meta_accessed
+            : ~(&nextPtr) & taskBuf_3_aMergeTask_meta_accessed;
+        taskBuf_3_aMergeTask_meta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aMergeTask_meta_tagErr
+            : ~(&nextPtr) & taskBuf_3_aMergeTask_meta_tagErr;
+        taskBuf_3_aMergeTask_meta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_aMergeTask_meta_dataErr
+            : ~(&nextPtr) & taskBuf_3_aMergeTask_meta_dataErr;
+        taskBuf_3_snpHitRelease <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitRelease
+            : ~(&nextPtr) & taskBuf_3_snpHitRelease;
+        taskBuf_3_snpHitReleaseToInval <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseToInval
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseToInval;
+        taskBuf_3_snpHitReleaseToClean <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseToClean
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseToClean;
+        taskBuf_3_snpHitReleaseWithData <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseWithData
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseWithData;
+        taskBuf_3_snpHitReleaseMeta_dirty <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseMeta_dirty
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseMeta_dirty;
+        taskBuf_3_snpHitReleaseMeta_clients <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseMeta_clients
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseMeta_clients;
+        taskBuf_3_snpHitReleaseMeta_alias <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseMeta_alias
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseMeta_alias;
+        taskBuf_3_snpHitReleaseMeta_prefetch <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseMeta_prefetch
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseMeta_prefetch;
+        taskBuf_3_snpHitReleaseMeta_accessed <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseMeta_accessed
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseMeta_accessed;
+        taskBuf_3_snpHitReleaseMeta_tagErr <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseMeta_tagErr
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseMeta_tagErr;
+        taskBuf_3_snpHitReleaseMeta_dataErr <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_snpHitReleaseMeta_dataErr
+            : ~(&nextPtr) & taskBuf_3_snpHitReleaseMeta_dataErr;
+        taskBuf_3_retToSrc <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_retToSrc
+            : ~(&nextPtr) & taskBuf_3_retToSrc;
+        taskBuf_3_likelyshared <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_likelyshared
+            : ~(&nextPtr) & taskBuf_3_likelyshared;
+        taskBuf_3_expCompAck <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_expCompAck
+            : ~(&nextPtr) & taskBuf_3_expCompAck;
+        taskBuf_3_allowRetry <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_allowRetry
+            : ~(&nextPtr) & taskBuf_3_allowRetry;
+        taskBuf_3_memAttr_allocate <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_memAttr_allocate
+            : ~(&nextPtr) & taskBuf_3_memAttr_allocate;
+        taskBuf_3_memAttr_cacheable <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_memAttr_cacheable
+            : ~(&nextPtr) & taskBuf_3_memAttr_cacheable;
+        taskBuf_3_memAttr_device <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_memAttr_device
+            : ~(&nextPtr) & taskBuf_3_memAttr_device;
+        taskBuf_3_memAttr_ewa <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_memAttr_ewa
+            : ~(&nextPtr) & taskBuf_3_memAttr_ewa;
+        taskBuf_3_traceTag <=
+          io_c_bits_opcode[0]
+            ? ~(&nextPtrReg) & taskBuf_3_traceTag
+            : ~(&nextPtr) & taskBuf_3_traceTag;
+      end
+      if (_GEN_27) begin
+        taskBuf_0_opcode <= _GEN_26;
+        taskBuf_0_param <= io_c_bits_param;
+        taskBuf_0_size <= io_c_bits_size;
+        taskBuf_0_sourceId <= io_c_bits_source;
+        taskBuf_0_wayMask <= 8'hFF;
+      end
+      if (_GEN_25 & (io_c_bits_opcode[0] ? _GEN_17 : _GEN_5)) begin
+        taskBuf_1_channel <= 3'h4;
+        taskBuf_1_opcode <= _GEN_26;
+        taskBuf_1_param <= io_c_bits_param;
+        taskBuf_1_size <= io_c_bits_size;
+        taskBuf_1_sourceId <= io_c_bits_source;
+        taskBuf_1_wayMask <= 8'hFF;
+      end
+      if (_GEN_25 & (io_c_bits_opcode[0] ? _GEN_20 : _GEN_8)) begin
+        taskBuf_2_channel <= 3'h4;
+        taskBuf_2_opcode <= _GEN_26;
+        taskBuf_2_param <= io_c_bits_param;
+        taskBuf_2_size <= io_c_bits_size;
+        taskBuf_2_sourceId <= io_c_bits_source;
+        taskBuf_2_wayMask <= 8'hFF;
+      end
+      if (_GEN_25 & (io_c_bits_opcode[0] ? (&nextPtrReg) : (&nextPtr))) begin
+        taskBuf_3_channel <= 3'h4;
+        taskBuf_3_opcode <= _GEN_26;
+        taskBuf_3_param <= io_c_bits_param;
+        taskBuf_3_size <= io_c_bits_size;
+        taskBuf_3_sourceId <= io_c_bits_source;
+        taskBuf_3_wayMask <= 8'hFF;
+      end
+      taskValids_0 <=
+        ~(_taskArb_io_in_0_ready & taskValids_0)
+        & (_GEN_25
+             ? (io_c_bits_opcode[0] ? _GEN_13 | taskValids_0 : _GEN_2 | taskValids_0)
+             : taskValids_0);
+      taskValids_1 <=
+        ~(_taskArb_io_in_1_ready & taskValids_1)
+        & (_GEN_25
+             ? (io_c_bits_opcode[0] ? _GEN_17 | taskValids_1 : _GEN_5 | taskValids_1)
+             : taskValids_1);
+      taskValids_2 <=
+        ~(_taskArb_io_in_2_ready & taskValids_2)
+        & (_GEN_25
+             ? (io_c_bits_opcode[0] ? _GEN_20 | taskValids_2 : _GEN_8 | taskValids_2)
+             : taskValids_2);
+      taskValids_3 <=
+        ~(_taskArb_io_in_3_ready & taskValids_3)
+        & (_GEN_25
+             ? (io_c_bits_opcode[0]
+                  ? (&nextPtrReg) | taskValids_3
+                  : (&nextPtr) | taskValids_3)
+             : taskValids_3);
+      if (_nextPtrReg_T & io_c_bits_opcode[1] & ~r_counter & io_c_bits_opcode[0])
+        nextPtrReg <= nextPtr;
+      if (io_c_valid & _io_releaseBufWrite_valid_T & ~r_counter)
+        probeAckDataBuf <= io_c_bits_data;
+      io_refillBufWrite_valid_REG <=
+        _io_refillBufWrite_valid_T & _taskArb_io_out_bits_opcode == 4'h7
+        & (|{_newdataMask_WIRE_15,
+             _newdataMask_WIRE_14,
+             _newdataMask_WIRE_13,
+             _newdataMask_WIRE_12,
+             _newdataMask_WIRE_11,
+             _newdataMask_WIRE_10,
+             _newdataMask_WIRE_9,
+             _newdataMask_WIRE_8,
+             _newdataMask_WIRE_7,
+             _newdataMask_WIRE_6,
+             _newdataMask_WIRE_5,
+             _newdataMask_WIRE_4,
+             _newdataMask_WIRE_3,
+             _newdataMask_WIRE_2,
+             _newdataMask_WIRE_1,
+             io_msInfo_0_valid & io_msInfo_0_bits_set == _taskArb_io_out_bits_set
+               & io_msInfo_0_bits_reqTag == _taskArb_io_out_bits_tag
+               & io_msInfo_0_bits_blockRefill});
+    end
+  end // always @(posedge, posedge)
+  wire [6:0]        _io_refillBufWrite_bits_id_T_1 =
+    {_newdataMask_WIRE_15,
+     _newdataMask_WIRE_14,
+     _newdataMask_WIRE_13,
+     _newdataMask_WIRE_12,
+     _newdataMask_WIRE_11,
+     _newdataMask_WIRE_10,
+     _newdataMask_WIRE_9}
+    | {_newdataMask_WIRE_7,
+       _newdataMask_WIRE_6,
+       _newdataMask_WIRE_5,
+       _newdataMask_WIRE_4,
+       _newdataMask_WIRE_3,
+       _newdataMask_WIRE_2,
+       _newdataMask_WIRE_1};
+  wire [2:0]        _io_refillBufWrite_bits_id_T_3 =
+    _io_refillBufWrite_bits_id_T_1[6:4] | _io_refillBufWrite_bits_id_T_1[2:0];
+  always @(posedge clock) begin
+    io_refillBufWrite_bits_id_REG <=
+      {|{_newdataMask_WIRE_15,
+         _newdataMask_WIRE_14,
+         _newdataMask_WIRE_13,
+         _newdataMask_WIRE_12,
+         _newdataMask_WIRE_11,
+         _newdataMask_WIRE_10,
+         _newdataMask_WIRE_9,
+         _newdataMask_WIRE_8},
+       |(_io_refillBufWrite_bits_id_T_1[6:3]),
+       |(_io_refillBufWrite_bits_id_T_3[2:1]),
+       _io_refillBufWrite_bits_id_T_3[2] | _io_refillBufWrite_bits_id_T_3[0]};
+    io_refillBufWrite_bits_data_data_REG <= _taskArb_io_out_bits_bufIdx;
+    if (_io_refillBufWrite_valid_T) begin
+      r_0 <= _GEN[_taskArb_io_out_bits_bufIdx];
+      r_1 <= _GEN_0[_taskArb_io_out_bits_bufIdx];
+    end
+    REG_0 <= r_0;
+    REG_1 <= r_1;
+    REG_1_0 <= _io_refillBufWrite_valid_T;
+    REG_2 <= _taskArb_io_out_bits_bufIdx;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:160];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [7:0] i = 8'h0; i < 8'hA1; i += 8'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        r_counter = _RANDOM[8'h0][0];
+        dataBuf_0_0 =
+          {_RANDOM[8'h0][31:1],
+           _RANDOM[8'h1],
+           _RANDOM[8'h2],
+           _RANDOM[8'h3],
+           _RANDOM[8'h4],
+           _RANDOM[8'h5],
+           _RANDOM[8'h6],
+           _RANDOM[8'h7],
+           _RANDOM[8'h8][0]};
+        dataBuf_0_1 =
+          {_RANDOM[8'h8][31:1],
+           _RANDOM[8'h9],
+           _RANDOM[8'hA],
+           _RANDOM[8'hB],
+           _RANDOM[8'hC],
+           _RANDOM[8'hD],
+           _RANDOM[8'hE],
+           _RANDOM[8'hF],
+           _RANDOM[8'h10][0]};
+        dataBuf_1_0 =
+          {_RANDOM[8'h10][31:1],
+           _RANDOM[8'h11],
+           _RANDOM[8'h12],
+           _RANDOM[8'h13],
+           _RANDOM[8'h14],
+           _RANDOM[8'h15],
+           _RANDOM[8'h16],
+           _RANDOM[8'h17],
+           _RANDOM[8'h18][0]};
+        dataBuf_1_1 =
+          {_RANDOM[8'h18][31:1],
+           _RANDOM[8'h19],
+           _RANDOM[8'h1A],
+           _RANDOM[8'h1B],
+           _RANDOM[8'h1C],
+           _RANDOM[8'h1D],
+           _RANDOM[8'h1E],
+           _RANDOM[8'h1F],
+           _RANDOM[8'h20][0]};
+        dataBuf_2_0 =
+          {_RANDOM[8'h20][31:1],
+           _RANDOM[8'h21],
+           _RANDOM[8'h22],
+           _RANDOM[8'h23],
+           _RANDOM[8'h24],
+           _RANDOM[8'h25],
+           _RANDOM[8'h26],
+           _RANDOM[8'h27],
+           _RANDOM[8'h28][0]};
+        dataBuf_2_1 =
+          {_RANDOM[8'h28][31:1],
+           _RANDOM[8'h29],
+           _RANDOM[8'h2A],
+           _RANDOM[8'h2B],
+           _RANDOM[8'h2C],
+           _RANDOM[8'h2D],
+           _RANDOM[8'h2E],
+           _RANDOM[8'h2F],
+           _RANDOM[8'h30][0]};
+        dataBuf_3_0 =
+          {_RANDOM[8'h30][31:1],
+           _RANDOM[8'h31],
+           _RANDOM[8'h32],
+           _RANDOM[8'h33],
+           _RANDOM[8'h34],
+           _RANDOM[8'h35],
+           _RANDOM[8'h36],
+           _RANDOM[8'h37],
+           _RANDOM[8'h38][0]};
+        dataBuf_3_1 =
+          {_RANDOM[8'h38][31:1],
+           _RANDOM[8'h39],
+           _RANDOM[8'h3A],
+           _RANDOM[8'h3B],
+           _RANDOM[8'h3C],
+           _RANDOM[8'h3D],
+           _RANDOM[8'h3E],
+           _RANDOM[8'h3F],
+           _RANDOM[8'h40][0]};
+        beatValids_0_0 = _RANDOM[8'h40][1];
+        beatValids_0_1 = _RANDOM[8'h40][2];
+        beatValids_1_0 = _RANDOM[8'h40][3];
+        beatValids_1_1 = _RANDOM[8'h40][4];
+        beatValids_2_0 = _RANDOM[8'h40][5];
+        beatValids_2_1 = _RANDOM[8'h40][6];
+        beatValids_3_0 = _RANDOM[8'h40][7];
+        beatValids_3_1 = _RANDOM[8'h40][8];
+        taskBuf_0_channel = _RANDOM[8'h40][11:9];
+        taskBuf_0_set = _RANDOM[8'h40][22:15];
+        taskBuf_0_tag = {_RANDOM[8'h40][31:23], _RANDOM[8'h41][24:0]};
+        taskBuf_0_off = _RANDOM[8'h41][30:25];
+        taskBuf_0_alias = _RANDOM[8'h41][31];
+        taskBuf_0_isKeyword = _RANDOM[8'h43][12];
+        taskBuf_0_opcode = _RANDOM[8'h43][16:13];
+        taskBuf_0_param = _RANDOM[8'h43][19:17];
+        taskBuf_0_size = _RANDOM[8'h43][22:20];
+        taskBuf_0_sourceId = _RANDOM[8'h43][29:23];
+        taskBuf_0_bufIdx = _RANDOM[8'h43][31:30];
+        taskBuf_0_needProbeAckData = _RANDOM[8'h44][0];
+        taskBuf_0_denied = _RANDOM[8'h44][1];
+        taskBuf_0_corrupt = _RANDOM[8'h44][2];
+        taskBuf_0_mshrTask = _RANDOM[8'h44][3];
+        taskBuf_0_aliasTask = _RANDOM[8'h44][12];
+        taskBuf_0_useProbeData = _RANDOM[8'h44][13];
+        taskBuf_0_mshrRetry = _RANDOM[8'h44][14];
+        taskBuf_0_readProbeDataDown = _RANDOM[8'h44][15];
+        taskBuf_0_fromL2pft = _RANDOM[8'h44][16];
+        taskBuf_0_needHint = _RANDOM[8'h44][17];
+        taskBuf_0_dirty = _RANDOM[8'h44][18];
+        taskBuf_0_meta_dirty = _RANDOM[8'h44][22];
+        taskBuf_0_meta_clients = _RANDOM[8'h44][25];
+        taskBuf_0_meta_alias = _RANDOM[8'h44][26];
+        taskBuf_0_meta_prefetch = _RANDOM[8'h44][27];
+        taskBuf_0_meta_accessed = _RANDOM[8'h45][0];
+        taskBuf_0_meta_tagErr = _RANDOM[8'h45][1];
+        taskBuf_0_meta_dataErr = _RANDOM[8'h45][2];
+        taskBuf_0_metaWen = _RANDOM[8'h45][3];
+        taskBuf_0_tagWen = _RANDOM[8'h45][4];
+        taskBuf_0_dsWen = _RANDOM[8'h45][5];
+        taskBuf_0_wayMask = _RANDOM[8'h45][13:6];
+        taskBuf_0_replTask = _RANDOM[8'h45][14];
+        taskBuf_0_cmoTask = _RANDOM[8'h45][15];
+        taskBuf_0_cmoAll = _RANDOM[8'h45][16];
+        taskBuf_0_mergeA = _RANDOM[8'h45][22];
+        taskBuf_0_aMergeTask_alias = _RANDOM[8'h45][29];
+        taskBuf_0_aMergeTask_isKeyword = _RANDOM[8'h47][10];
+        taskBuf_0_aMergeTask_meta_dirty = _RANDOM[8'h47][24];
+        taskBuf_0_aMergeTask_meta_clients = _RANDOM[8'h47][27];
+        taskBuf_0_aMergeTask_meta_alias = _RANDOM[8'h47][28];
+        taskBuf_0_aMergeTask_meta_prefetch = _RANDOM[8'h47][29];
+        taskBuf_0_aMergeTask_meta_accessed = _RANDOM[8'h48][2];
+        taskBuf_0_aMergeTask_meta_tagErr = _RANDOM[8'h48][3];
+        taskBuf_0_aMergeTask_meta_dataErr = _RANDOM[8'h48][4];
+        taskBuf_0_snpHitRelease = _RANDOM[8'h48][5];
+        taskBuf_0_snpHitReleaseToInval = _RANDOM[8'h48][6];
+        taskBuf_0_snpHitReleaseToClean = _RANDOM[8'h48][7];
+        taskBuf_0_snpHitReleaseWithData = _RANDOM[8'h48][8];
+        taskBuf_0_snpHitReleaseMeta_dirty = _RANDOM[8'h48][17];
+        taskBuf_0_snpHitReleaseMeta_clients = _RANDOM[8'h48][20];
+        taskBuf_0_snpHitReleaseMeta_alias = _RANDOM[8'h48][21];
+        taskBuf_0_snpHitReleaseMeta_prefetch = _RANDOM[8'h48][22];
+        taskBuf_0_snpHitReleaseMeta_accessed = _RANDOM[8'h48][27];
+        taskBuf_0_snpHitReleaseMeta_tagErr = _RANDOM[8'h48][28];
+        taskBuf_0_snpHitReleaseMeta_dataErr = _RANDOM[8'h48][29];
+        taskBuf_0_retToSrc = _RANDOM[8'h4B][31];
+        taskBuf_0_likelyshared = _RANDOM[8'h4C][0];
+        taskBuf_0_expCompAck = _RANDOM[8'h4C][1];
+        taskBuf_0_allowRetry = _RANDOM[8'h4C][2];
+        taskBuf_0_memAttr_allocate = _RANDOM[8'h4C][3];
+        taskBuf_0_memAttr_cacheable = _RANDOM[8'h4C][4];
+        taskBuf_0_memAttr_device = _RANDOM[8'h4C][5];
+        taskBuf_0_memAttr_ewa = _RANDOM[8'h4C][6];
+        taskBuf_0_traceTag = _RANDOM[8'h4C][7];
+        taskBuf_1_channel = _RANDOM[8'h4C][10:8];
+        taskBuf_1_set = _RANDOM[8'h4C][21:14];
+        taskBuf_1_tag = {_RANDOM[8'h4C][31:22], _RANDOM[8'h4D][23:0]};
+        taskBuf_1_off = _RANDOM[8'h4D][29:24];
+        taskBuf_1_alias = _RANDOM[8'h4D][30];
+        taskBuf_1_isKeyword = _RANDOM[8'h4F][11];
+        taskBuf_1_opcode = _RANDOM[8'h4F][15:12];
+        taskBuf_1_param = _RANDOM[8'h4F][18:16];
+        taskBuf_1_size = _RANDOM[8'h4F][21:19];
+        taskBuf_1_sourceId = _RANDOM[8'h4F][28:22];
+        taskBuf_1_bufIdx = _RANDOM[8'h4F][30:29];
+        taskBuf_1_needProbeAckData = _RANDOM[8'h4F][31];
+        taskBuf_1_denied = _RANDOM[8'h50][0];
+        taskBuf_1_corrupt = _RANDOM[8'h50][1];
+        taskBuf_1_mshrTask = _RANDOM[8'h50][2];
+        taskBuf_1_aliasTask = _RANDOM[8'h50][11];
+        taskBuf_1_useProbeData = _RANDOM[8'h50][12];
+        taskBuf_1_mshrRetry = _RANDOM[8'h50][13];
+        taskBuf_1_readProbeDataDown = _RANDOM[8'h50][14];
+        taskBuf_1_fromL2pft = _RANDOM[8'h50][15];
+        taskBuf_1_needHint = _RANDOM[8'h50][16];
+        taskBuf_1_dirty = _RANDOM[8'h50][17];
+        taskBuf_1_meta_dirty = _RANDOM[8'h50][21];
+        taskBuf_1_meta_clients = _RANDOM[8'h50][24];
+        taskBuf_1_meta_alias = _RANDOM[8'h50][25];
+        taskBuf_1_meta_prefetch = _RANDOM[8'h50][26];
+        taskBuf_1_meta_accessed = _RANDOM[8'h50][31];
+        taskBuf_1_meta_tagErr = _RANDOM[8'h51][0];
+        taskBuf_1_meta_dataErr = _RANDOM[8'h51][1];
+        taskBuf_1_metaWen = _RANDOM[8'h51][2];
+        taskBuf_1_tagWen = _RANDOM[8'h51][3];
+        taskBuf_1_dsWen = _RANDOM[8'h51][4];
+        taskBuf_1_wayMask = _RANDOM[8'h51][12:5];
+        taskBuf_1_replTask = _RANDOM[8'h51][13];
+        taskBuf_1_cmoTask = _RANDOM[8'h51][14];
+        taskBuf_1_cmoAll = _RANDOM[8'h51][15];
+        taskBuf_1_mergeA = _RANDOM[8'h51][21];
+        taskBuf_1_aMergeTask_alias = _RANDOM[8'h51][28];
+        taskBuf_1_aMergeTask_isKeyword = _RANDOM[8'h53][9];
+        taskBuf_1_aMergeTask_meta_dirty = _RANDOM[8'h53][23];
+        taskBuf_1_aMergeTask_meta_clients = _RANDOM[8'h53][26];
+        taskBuf_1_aMergeTask_meta_alias = _RANDOM[8'h53][27];
+        taskBuf_1_aMergeTask_meta_prefetch = _RANDOM[8'h53][28];
+        taskBuf_1_aMergeTask_meta_accessed = _RANDOM[8'h54][1];
+        taskBuf_1_aMergeTask_meta_tagErr = _RANDOM[8'h54][2];
+        taskBuf_1_aMergeTask_meta_dataErr = _RANDOM[8'h54][3];
+        taskBuf_1_snpHitRelease = _RANDOM[8'h54][4];
+        taskBuf_1_snpHitReleaseToInval = _RANDOM[8'h54][5];
+        taskBuf_1_snpHitReleaseToClean = _RANDOM[8'h54][6];
+        taskBuf_1_snpHitReleaseWithData = _RANDOM[8'h54][7];
+        taskBuf_1_snpHitReleaseMeta_dirty = _RANDOM[8'h54][16];
+        taskBuf_1_snpHitReleaseMeta_clients = _RANDOM[8'h54][19];
+        taskBuf_1_snpHitReleaseMeta_alias = _RANDOM[8'h54][20];
+        taskBuf_1_snpHitReleaseMeta_prefetch = _RANDOM[8'h54][21];
+        taskBuf_1_snpHitReleaseMeta_accessed = _RANDOM[8'h54][26];
+        taskBuf_1_snpHitReleaseMeta_tagErr = _RANDOM[8'h54][27];
+        taskBuf_1_snpHitReleaseMeta_dataErr = _RANDOM[8'h54][28];
+        taskBuf_1_retToSrc = _RANDOM[8'h57][30];
+        taskBuf_1_likelyshared = _RANDOM[8'h57][31];
+        taskBuf_1_expCompAck = _RANDOM[8'h58][0];
+        taskBuf_1_allowRetry = _RANDOM[8'h58][1];
+        taskBuf_1_memAttr_allocate = _RANDOM[8'h58][2];
+        taskBuf_1_memAttr_cacheable = _RANDOM[8'h58][3];
+        taskBuf_1_memAttr_device = _RANDOM[8'h58][4];
+        taskBuf_1_memAttr_ewa = _RANDOM[8'h58][5];
+        taskBuf_1_traceTag = _RANDOM[8'h58][6];
+        taskBuf_2_channel = _RANDOM[8'h58][9:7];
+        taskBuf_2_set = _RANDOM[8'h58][20:13];
+        taskBuf_2_tag = {_RANDOM[8'h58][31:21], _RANDOM[8'h59][22:0]};
+        taskBuf_2_off = _RANDOM[8'h59][28:23];
+        taskBuf_2_alias = _RANDOM[8'h59][29];
+        taskBuf_2_isKeyword = _RANDOM[8'h5B][10];
+        taskBuf_2_opcode = _RANDOM[8'h5B][14:11];
+        taskBuf_2_param = _RANDOM[8'h5B][17:15];
+        taskBuf_2_size = _RANDOM[8'h5B][20:18];
+        taskBuf_2_sourceId = _RANDOM[8'h5B][27:21];
+        taskBuf_2_bufIdx = _RANDOM[8'h5B][29:28];
+        taskBuf_2_needProbeAckData = _RANDOM[8'h5B][30];
+        taskBuf_2_denied = _RANDOM[8'h5B][31];
+        taskBuf_2_corrupt = _RANDOM[8'h5C][0];
+        taskBuf_2_mshrTask = _RANDOM[8'h5C][1];
+        taskBuf_2_aliasTask = _RANDOM[8'h5C][10];
+        taskBuf_2_useProbeData = _RANDOM[8'h5C][11];
+        taskBuf_2_mshrRetry = _RANDOM[8'h5C][12];
+        taskBuf_2_readProbeDataDown = _RANDOM[8'h5C][13];
+        taskBuf_2_fromL2pft = _RANDOM[8'h5C][14];
+        taskBuf_2_needHint = _RANDOM[8'h5C][15];
+        taskBuf_2_dirty = _RANDOM[8'h5C][16];
+        taskBuf_2_meta_dirty = _RANDOM[8'h5C][20];
+        taskBuf_2_meta_clients = _RANDOM[8'h5C][23];
+        taskBuf_2_meta_alias = _RANDOM[8'h5C][24];
+        taskBuf_2_meta_prefetch = _RANDOM[8'h5C][25];
+        taskBuf_2_meta_accessed = _RANDOM[8'h5C][30];
+        taskBuf_2_meta_tagErr = _RANDOM[8'h5C][31];
+        taskBuf_2_meta_dataErr = _RANDOM[8'h5D][0];
+        taskBuf_2_metaWen = _RANDOM[8'h5D][1];
+        taskBuf_2_tagWen = _RANDOM[8'h5D][2];
+        taskBuf_2_dsWen = _RANDOM[8'h5D][3];
+        taskBuf_2_wayMask = _RANDOM[8'h5D][11:4];
+        taskBuf_2_replTask = _RANDOM[8'h5D][12];
+        taskBuf_2_cmoTask = _RANDOM[8'h5D][13];
+        taskBuf_2_cmoAll = _RANDOM[8'h5D][14];
+        taskBuf_2_mergeA = _RANDOM[8'h5D][20];
+        taskBuf_2_aMergeTask_alias = _RANDOM[8'h5D][27];
+        taskBuf_2_aMergeTask_isKeyword = _RANDOM[8'h5F][8];
+        taskBuf_2_aMergeTask_meta_dirty = _RANDOM[8'h5F][22];
+        taskBuf_2_aMergeTask_meta_clients = _RANDOM[8'h5F][25];
+        taskBuf_2_aMergeTask_meta_alias = _RANDOM[8'h5F][26];
+        taskBuf_2_aMergeTask_meta_prefetch = _RANDOM[8'h5F][27];
+        taskBuf_2_aMergeTask_meta_accessed = _RANDOM[8'h60][0];
+        taskBuf_2_aMergeTask_meta_tagErr = _RANDOM[8'h60][1];
+        taskBuf_2_aMergeTask_meta_dataErr = _RANDOM[8'h60][2];
+        taskBuf_2_snpHitRelease = _RANDOM[8'h60][3];
+        taskBuf_2_snpHitReleaseToInval = _RANDOM[8'h60][4];
+        taskBuf_2_snpHitReleaseToClean = _RANDOM[8'h60][5];
+        taskBuf_2_snpHitReleaseWithData = _RANDOM[8'h60][6];
+        taskBuf_2_snpHitReleaseMeta_dirty = _RANDOM[8'h60][15];
+        taskBuf_2_snpHitReleaseMeta_clients = _RANDOM[8'h60][18];
+        taskBuf_2_snpHitReleaseMeta_alias = _RANDOM[8'h60][19];
+        taskBuf_2_snpHitReleaseMeta_prefetch = _RANDOM[8'h60][20];
+        taskBuf_2_snpHitReleaseMeta_accessed = _RANDOM[8'h60][25];
+        taskBuf_2_snpHitReleaseMeta_tagErr = _RANDOM[8'h60][26];
+        taskBuf_2_snpHitReleaseMeta_dataErr = _RANDOM[8'h60][27];
+        taskBuf_2_retToSrc = _RANDOM[8'h63][29];
+        taskBuf_2_likelyshared = _RANDOM[8'h63][30];
+        taskBuf_2_expCompAck = _RANDOM[8'h63][31];
+        taskBuf_2_allowRetry = _RANDOM[8'h64][0];
+        taskBuf_2_memAttr_allocate = _RANDOM[8'h64][1];
+        taskBuf_2_memAttr_cacheable = _RANDOM[8'h64][2];
+        taskBuf_2_memAttr_device = _RANDOM[8'h64][3];
+        taskBuf_2_memAttr_ewa = _RANDOM[8'h64][4];
+        taskBuf_2_traceTag = _RANDOM[8'h64][5];
+        taskBuf_3_channel = _RANDOM[8'h64][8:6];
+        taskBuf_3_set = _RANDOM[8'h64][19:12];
+        taskBuf_3_tag = {_RANDOM[8'h64][31:20], _RANDOM[8'h65][21:0]};
+        taskBuf_3_off = _RANDOM[8'h65][27:22];
+        taskBuf_3_alias = _RANDOM[8'h65][28];
+        taskBuf_3_isKeyword = _RANDOM[8'h67][9];
+        taskBuf_3_opcode = _RANDOM[8'h67][13:10];
+        taskBuf_3_param = _RANDOM[8'h67][16:14];
+        taskBuf_3_size = _RANDOM[8'h67][19:17];
+        taskBuf_3_sourceId = _RANDOM[8'h67][26:20];
+        taskBuf_3_bufIdx = _RANDOM[8'h67][28:27];
+        taskBuf_3_needProbeAckData = _RANDOM[8'h67][29];
+        taskBuf_3_denied = _RANDOM[8'h67][30];
+        taskBuf_3_corrupt = _RANDOM[8'h67][31];
+        taskBuf_3_mshrTask = _RANDOM[8'h68][0];
+        taskBuf_3_aliasTask = _RANDOM[8'h68][9];
+        taskBuf_3_useProbeData = _RANDOM[8'h68][10];
+        taskBuf_3_mshrRetry = _RANDOM[8'h68][11];
+        taskBuf_3_readProbeDataDown = _RANDOM[8'h68][12];
+        taskBuf_3_fromL2pft = _RANDOM[8'h68][13];
+        taskBuf_3_needHint = _RANDOM[8'h68][14];
+        taskBuf_3_dirty = _RANDOM[8'h68][15];
+        taskBuf_3_meta_dirty = _RANDOM[8'h68][19];
+        taskBuf_3_meta_clients = _RANDOM[8'h68][22];
+        taskBuf_3_meta_alias = _RANDOM[8'h68][23];
+        taskBuf_3_meta_prefetch = _RANDOM[8'h68][24];
+        taskBuf_3_meta_accessed = _RANDOM[8'h68][29];
+        taskBuf_3_meta_tagErr = _RANDOM[8'h68][30];
+        taskBuf_3_meta_dataErr = _RANDOM[8'h68][31];
+        taskBuf_3_metaWen = _RANDOM[8'h69][0];
+        taskBuf_3_tagWen = _RANDOM[8'h69][1];
+        taskBuf_3_dsWen = _RANDOM[8'h69][2];
+        taskBuf_3_wayMask = _RANDOM[8'h69][10:3];
+        taskBuf_3_replTask = _RANDOM[8'h69][11];
+        taskBuf_3_cmoTask = _RANDOM[8'h69][12];
+        taskBuf_3_cmoAll = _RANDOM[8'h69][13];
+        taskBuf_3_mergeA = _RANDOM[8'h69][19];
+        taskBuf_3_aMergeTask_alias = _RANDOM[8'h69][26];
+        taskBuf_3_aMergeTask_isKeyword = _RANDOM[8'h6B][7];
+        taskBuf_3_aMergeTask_meta_dirty = _RANDOM[8'h6B][21];
+        taskBuf_3_aMergeTask_meta_clients = _RANDOM[8'h6B][24];
+        taskBuf_3_aMergeTask_meta_alias = _RANDOM[8'h6B][25];
+        taskBuf_3_aMergeTask_meta_prefetch = _RANDOM[8'h6B][26];
+        taskBuf_3_aMergeTask_meta_accessed = _RANDOM[8'h6B][31];
+        taskBuf_3_aMergeTask_meta_tagErr = _RANDOM[8'h6C][0];
+        taskBuf_3_aMergeTask_meta_dataErr = _RANDOM[8'h6C][1];
+        taskBuf_3_snpHitRelease = _RANDOM[8'h6C][2];
+        taskBuf_3_snpHitReleaseToInval = _RANDOM[8'h6C][3];
+        taskBuf_3_snpHitReleaseToClean = _RANDOM[8'h6C][4];
+        taskBuf_3_snpHitReleaseWithData = _RANDOM[8'h6C][5];
+        taskBuf_3_snpHitReleaseMeta_dirty = _RANDOM[8'h6C][14];
+        taskBuf_3_snpHitReleaseMeta_clients = _RANDOM[8'h6C][17];
+        taskBuf_3_snpHitReleaseMeta_alias = _RANDOM[8'h6C][18];
+        taskBuf_3_snpHitReleaseMeta_prefetch = _RANDOM[8'h6C][19];
+        taskBuf_3_snpHitReleaseMeta_accessed = _RANDOM[8'h6C][24];
+        taskBuf_3_snpHitReleaseMeta_tagErr = _RANDOM[8'h6C][25];
+        taskBuf_3_snpHitReleaseMeta_dataErr = _RANDOM[8'h6C][26];
+        taskBuf_3_retToSrc = _RANDOM[8'h6F][28];
+        taskBuf_3_likelyshared = _RANDOM[8'h6F][29];
+        taskBuf_3_expCompAck = _RANDOM[8'h6F][30];
+        taskBuf_3_allowRetry = _RANDOM[8'h6F][31];
+        taskBuf_3_memAttr_allocate = _RANDOM[8'h70][0];
+        taskBuf_3_memAttr_cacheable = _RANDOM[8'h70][1];
+        taskBuf_3_memAttr_device = _RANDOM[8'h70][2];
+        taskBuf_3_memAttr_ewa = _RANDOM[8'h70][3];
+        taskBuf_3_traceTag = _RANDOM[8'h70][4];
+        taskValids_0 = _RANDOM[8'h70][5];
+        taskValids_1 = _RANDOM[8'h70][6];
+        taskValids_2 = _RANDOM[8'h70][7];
+        taskValids_3 = _RANDOM[8'h70][8];
+        nextPtrReg = _RANDOM[8'h78][10:9];
+        probeAckDataBuf =
+          {_RANDOM[8'h78][31:11],
+           _RANDOM[8'h79],
+           _RANDOM[8'h7A],
+           _RANDOM[8'h7B],
+           _RANDOM[8'h7C],
+           _RANDOM[8'h7D],
+           _RANDOM[8'h7E],
+           _RANDOM[8'h7F],
+           _RANDOM[8'h80][10:0]};
+        io_refillBufWrite_valid_REG = _RANDOM[8'h80][11];
+        io_refillBufWrite_bits_id_REG = _RANDOM[8'h80][15:12];
+        io_refillBufWrite_bits_data_data_REG = _RANDOM[8'h80][17:16];
+        r_0 =
+          {_RANDOM[8'h80][31:18],
+           _RANDOM[8'h81],
+           _RANDOM[8'h82],
+           _RANDOM[8'h83],
+           _RANDOM[8'h84],
+           _RANDOM[8'h85],
+           _RANDOM[8'h86],
+           _RANDOM[8'h87],
+           _RANDOM[8'h88][17:0]};
+        r_1 =
+          {_RANDOM[8'h88][31:18],
+           _RANDOM[8'h89],
+           _RANDOM[8'h8A],
+           _RANDOM[8'h8B],
+           _RANDOM[8'h8C],
+           _RANDOM[8'h8D],
+           _RANDOM[8'h8E],
+           _RANDOM[8'h8F],
+           _RANDOM[8'h90][17:0]};
+        REG_0 =
+          {_RANDOM[8'h90][31:18],
+           _RANDOM[8'h91],
+           _RANDOM[8'h92],
+           _RANDOM[8'h93],
+           _RANDOM[8'h94],
+           _RANDOM[8'h95],
+           _RANDOM[8'h96],
+           _RANDOM[8'h97],
+           _RANDOM[8'h98][17:0]};
+        REG_1 =
+          {_RANDOM[8'h98][31:18],
+           _RANDOM[8'h99],
+           _RANDOM[8'h9A],
+           _RANDOM[8'h9B],
+           _RANDOM[8'h9C],
+           _RANDOM[8'h9D],
+           _RANDOM[8'h9E],
+           _RANDOM[8'h9F],
+           _RANDOM[8'hA0][17:0]};
+        REG_1_0 = _RANDOM[8'hA0][18];
+        REG_2 = _RANDOM[8'hA0][20:19];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        r_counter = 1'h0;
+        dataBuf_0_0 = 256'h0;
+        dataBuf_0_1 = 256'h0;
+        dataBuf_1_0 = 256'h0;
+        dataBuf_1_1 = 256'h0;
+        dataBuf_2_0 = 256'h0;
+        dataBuf_2_1 = 256'h0;
+        dataBuf_3_0 = 256'h0;
+        dataBuf_3_1 = 256'h0;
+        beatValids_0_0 = 1'h0;
+        beatValids_0_1 = 1'h0;
+        beatValids_1_0 = 1'h0;
+        beatValids_1_1 = 1'h0;
+        beatValids_2_0 = 1'h0;
+        beatValids_2_1 = 1'h0;
+        beatValids_3_0 = 1'h0;
+        beatValids_3_1 = 1'h0;
+        taskBuf_0_channel = 3'h0;
+        taskBuf_0_set = 8'h0;
+        taskBuf_0_tag = 34'h0;
+        taskBuf_0_off = 6'h0;
+        taskBuf_0_alias = 1'h0;
+        taskBuf_0_isKeyword = 1'h0;
+        taskBuf_0_opcode = 4'h0;
+        taskBuf_0_param = 3'h0;
+        taskBuf_0_size = 3'h0;
+        taskBuf_0_sourceId = 7'h0;
+        taskBuf_0_bufIdx = 2'h0;
+        taskBuf_0_needProbeAckData = 1'h0;
+        taskBuf_0_denied = 1'h0;
+        taskBuf_0_corrupt = 1'h0;
+        taskBuf_0_mshrTask = 1'h0;
+        taskBuf_0_aliasTask = 1'h0;
+        taskBuf_0_useProbeData = 1'h0;
+        taskBuf_0_mshrRetry = 1'h0;
+        taskBuf_0_readProbeDataDown = 1'h0;
+        taskBuf_0_fromL2pft = 1'h0;
+        taskBuf_0_needHint = 1'h0;
+        taskBuf_0_dirty = 1'h0;
+        taskBuf_0_meta_dirty = 1'h0;
+        taskBuf_0_meta_clients = 1'h0;
+        taskBuf_0_meta_alias = 1'h0;
+        taskBuf_0_meta_prefetch = 1'h0;
+        taskBuf_0_meta_accessed = 1'h0;
+        taskBuf_0_meta_tagErr = 1'h0;
+        taskBuf_0_meta_dataErr = 1'h0;
+        taskBuf_0_metaWen = 1'h0;
+        taskBuf_0_tagWen = 1'h0;
+        taskBuf_0_dsWen = 1'h0;
+        taskBuf_0_wayMask = 8'h0;
+        taskBuf_0_replTask = 1'h0;
+        taskBuf_0_cmoTask = 1'h0;
+        taskBuf_0_cmoAll = 1'h0;
+        taskBuf_0_mergeA = 1'h0;
+        taskBuf_0_aMergeTask_alias = 1'h0;
+        taskBuf_0_aMergeTask_isKeyword = 1'h0;
+        taskBuf_0_aMergeTask_meta_dirty = 1'h0;
+        taskBuf_0_aMergeTask_meta_clients = 1'h0;
+        taskBuf_0_aMergeTask_meta_alias = 1'h0;
+        taskBuf_0_aMergeTask_meta_prefetch = 1'h0;
+        taskBuf_0_aMergeTask_meta_accessed = 1'h0;
+        taskBuf_0_aMergeTask_meta_tagErr = 1'h0;
+        taskBuf_0_aMergeTask_meta_dataErr = 1'h0;
+        taskBuf_0_snpHitRelease = 1'h0;
+        taskBuf_0_snpHitReleaseToInval = 1'h0;
+        taskBuf_0_snpHitReleaseToClean = 1'h0;
+        taskBuf_0_snpHitReleaseWithData = 1'h0;
+        taskBuf_0_snpHitReleaseMeta_dirty = 1'h0;
+        taskBuf_0_snpHitReleaseMeta_clients = 1'h0;
+        taskBuf_0_snpHitReleaseMeta_alias = 1'h0;
+        taskBuf_0_snpHitReleaseMeta_prefetch = 1'h0;
+        taskBuf_0_snpHitReleaseMeta_accessed = 1'h0;
+        taskBuf_0_snpHitReleaseMeta_tagErr = 1'h0;
+        taskBuf_0_snpHitReleaseMeta_dataErr = 1'h0;
+        taskBuf_0_retToSrc = 1'h0;
+        taskBuf_0_likelyshared = 1'h0;
+        taskBuf_0_expCompAck = 1'h0;
+        taskBuf_0_allowRetry = 1'h0;
+        taskBuf_0_memAttr_allocate = 1'h0;
+        taskBuf_0_memAttr_cacheable = 1'h0;
+        taskBuf_0_memAttr_device = 1'h0;
+        taskBuf_0_memAttr_ewa = 1'h0;
+        taskBuf_0_traceTag = 1'h0;
+        taskBuf_1_channel = 3'h0;
+        taskBuf_1_set = 8'h0;
+        taskBuf_1_tag = 34'h0;
+        taskBuf_1_off = 6'h0;
+        taskBuf_1_alias = 1'h0;
+        taskBuf_1_isKeyword = 1'h0;
+        taskBuf_1_opcode = 4'h0;
+        taskBuf_1_param = 3'h0;
+        taskBuf_1_size = 3'h0;
+        taskBuf_1_sourceId = 7'h0;
+        taskBuf_1_bufIdx = 2'h0;
+        taskBuf_1_needProbeAckData = 1'h0;
+        taskBuf_1_denied = 1'h0;
+        taskBuf_1_corrupt = 1'h0;
+        taskBuf_1_mshrTask = 1'h0;
+        taskBuf_1_aliasTask = 1'h0;
+        taskBuf_1_useProbeData = 1'h0;
+        taskBuf_1_mshrRetry = 1'h0;
+        taskBuf_1_readProbeDataDown = 1'h0;
+        taskBuf_1_fromL2pft = 1'h0;
+        taskBuf_1_needHint = 1'h0;
+        taskBuf_1_dirty = 1'h0;
+        taskBuf_1_meta_dirty = 1'h0;
+        taskBuf_1_meta_clients = 1'h0;
+        taskBuf_1_meta_alias = 1'h0;
+        taskBuf_1_meta_prefetch = 1'h0;
+        taskBuf_1_meta_accessed = 1'h0;
+        taskBuf_1_meta_tagErr = 1'h0;
+        taskBuf_1_meta_dataErr = 1'h0;
+        taskBuf_1_metaWen = 1'h0;
+        taskBuf_1_tagWen = 1'h0;
+        taskBuf_1_dsWen = 1'h0;
+        taskBuf_1_wayMask = 8'h0;
+        taskBuf_1_replTask = 1'h0;
+        taskBuf_1_cmoTask = 1'h0;
+        taskBuf_1_cmoAll = 1'h0;
+        taskBuf_1_mergeA = 1'h0;
+        taskBuf_1_aMergeTask_alias = 1'h0;
+        taskBuf_1_aMergeTask_isKeyword = 1'h0;
+        taskBuf_1_aMergeTask_meta_dirty = 1'h0;
+        taskBuf_1_aMergeTask_meta_clients = 1'h0;
+        taskBuf_1_aMergeTask_meta_alias = 1'h0;
+        taskBuf_1_aMergeTask_meta_prefetch = 1'h0;
+        taskBuf_1_aMergeTask_meta_accessed = 1'h0;
+        taskBuf_1_aMergeTask_meta_tagErr = 1'h0;
+        taskBuf_1_aMergeTask_meta_dataErr = 1'h0;
+        taskBuf_1_snpHitRelease = 1'h0;
+        taskBuf_1_snpHitReleaseToInval = 1'h0;
+        taskBuf_1_snpHitReleaseToClean = 1'h0;
+        taskBuf_1_snpHitReleaseWithData = 1'h0;
+        taskBuf_1_snpHitReleaseMeta_dirty = 1'h0;
+        taskBuf_1_snpHitReleaseMeta_clients = 1'h0;
+        taskBuf_1_snpHitReleaseMeta_alias = 1'h0;
+        taskBuf_1_snpHitReleaseMeta_prefetch = 1'h0;
+        taskBuf_1_snpHitReleaseMeta_accessed = 1'h0;
+        taskBuf_1_snpHitReleaseMeta_tagErr = 1'h0;
+        taskBuf_1_snpHitReleaseMeta_dataErr = 1'h0;
+        taskBuf_1_retToSrc = 1'h0;
+        taskBuf_1_likelyshared = 1'h0;
+        taskBuf_1_expCompAck = 1'h0;
+        taskBuf_1_allowRetry = 1'h0;
+        taskBuf_1_memAttr_allocate = 1'h0;
+        taskBuf_1_memAttr_cacheable = 1'h0;
+        taskBuf_1_memAttr_device = 1'h0;
+        taskBuf_1_memAttr_ewa = 1'h0;
+        taskBuf_1_traceTag = 1'h0;
+        taskBuf_2_channel = 3'h0;
+        taskBuf_2_set = 8'h0;
+        taskBuf_2_tag = 34'h0;
+        taskBuf_2_off = 6'h0;
+        taskBuf_2_alias = 1'h0;
+        taskBuf_2_isKeyword = 1'h0;
+        taskBuf_2_opcode = 4'h0;
+        taskBuf_2_param = 3'h0;
+        taskBuf_2_size = 3'h0;
+        taskBuf_2_sourceId = 7'h0;
+        taskBuf_2_bufIdx = 2'h0;
+        taskBuf_2_needProbeAckData = 1'h0;
+        taskBuf_2_denied = 1'h0;
+        taskBuf_2_corrupt = 1'h0;
+        taskBuf_2_mshrTask = 1'h0;
+        taskBuf_2_aliasTask = 1'h0;
+        taskBuf_2_useProbeData = 1'h0;
+        taskBuf_2_mshrRetry = 1'h0;
+        taskBuf_2_readProbeDataDown = 1'h0;
+        taskBuf_2_fromL2pft = 1'h0;
+        taskBuf_2_needHint = 1'h0;
+        taskBuf_2_dirty = 1'h0;
+        taskBuf_2_meta_dirty = 1'h0;
+        taskBuf_2_meta_clients = 1'h0;
+        taskBuf_2_meta_alias = 1'h0;
+        taskBuf_2_meta_prefetch = 1'h0;
+        taskBuf_2_meta_accessed = 1'h0;
+        taskBuf_2_meta_tagErr = 1'h0;
+        taskBuf_2_meta_dataErr = 1'h0;
+        taskBuf_2_metaWen = 1'h0;
+        taskBuf_2_tagWen = 1'h0;
+        taskBuf_2_dsWen = 1'h0;
+        taskBuf_2_wayMask = 8'h0;
+        taskBuf_2_replTask = 1'h0;
+        taskBuf_2_cmoTask = 1'h0;
+        taskBuf_2_cmoAll = 1'h0;
+        taskBuf_2_mergeA = 1'h0;
+        taskBuf_2_aMergeTask_alias = 1'h0;
+        taskBuf_2_aMergeTask_isKeyword = 1'h0;
+        taskBuf_2_aMergeTask_meta_dirty = 1'h0;
+        taskBuf_2_aMergeTask_meta_clients = 1'h0;
+        taskBuf_2_aMergeTask_meta_alias = 1'h0;
+        taskBuf_2_aMergeTask_meta_prefetch = 1'h0;
+        taskBuf_2_aMergeTask_meta_accessed = 1'h0;
+        taskBuf_2_aMergeTask_meta_tagErr = 1'h0;
+        taskBuf_2_aMergeTask_meta_dataErr = 1'h0;
+        taskBuf_2_snpHitRelease = 1'h0;
+        taskBuf_2_snpHitReleaseToInval = 1'h0;
+        taskBuf_2_snpHitReleaseToClean = 1'h0;
+        taskBuf_2_snpHitReleaseWithData = 1'h0;
+        taskBuf_2_snpHitReleaseMeta_dirty = 1'h0;
+        taskBuf_2_snpHitReleaseMeta_clients = 1'h0;
+        taskBuf_2_snpHitReleaseMeta_alias = 1'h0;
+        taskBuf_2_snpHitReleaseMeta_prefetch = 1'h0;
+        taskBuf_2_snpHitReleaseMeta_accessed = 1'h0;
+        taskBuf_2_snpHitReleaseMeta_tagErr = 1'h0;
+        taskBuf_2_snpHitReleaseMeta_dataErr = 1'h0;
+        taskBuf_2_retToSrc = 1'h0;
+        taskBuf_2_likelyshared = 1'h0;
+        taskBuf_2_expCompAck = 1'h0;
+        taskBuf_2_allowRetry = 1'h0;
+        taskBuf_2_memAttr_allocate = 1'h0;
+        taskBuf_2_memAttr_cacheable = 1'h0;
+        taskBuf_2_memAttr_device = 1'h0;
+        taskBuf_2_memAttr_ewa = 1'h0;
+        taskBuf_2_traceTag = 1'h0;
+        taskBuf_3_channel = 3'h0;
+        taskBuf_3_set = 8'h0;
+        taskBuf_3_tag = 34'h0;
+        taskBuf_3_off = 6'h0;
+        taskBuf_3_alias = 1'h0;
+        taskBuf_3_isKeyword = 1'h0;
+        taskBuf_3_opcode = 4'h0;
+        taskBuf_3_param = 3'h0;
+        taskBuf_3_size = 3'h0;
+        taskBuf_3_sourceId = 7'h0;
+        taskBuf_3_bufIdx = 2'h0;
+        taskBuf_3_needProbeAckData = 1'h0;
+        taskBuf_3_denied = 1'h0;
+        taskBuf_3_corrupt = 1'h0;
+        taskBuf_3_mshrTask = 1'h0;
+        taskBuf_3_aliasTask = 1'h0;
+        taskBuf_3_useProbeData = 1'h0;
+        taskBuf_3_mshrRetry = 1'h0;
+        taskBuf_3_readProbeDataDown = 1'h0;
+        taskBuf_3_fromL2pft = 1'h0;
+        taskBuf_3_needHint = 1'h0;
+        taskBuf_3_dirty = 1'h0;
+        taskBuf_3_meta_dirty = 1'h0;
+        taskBuf_3_meta_clients = 1'h0;
+        taskBuf_3_meta_alias = 1'h0;
+        taskBuf_3_meta_prefetch = 1'h0;
+        taskBuf_3_meta_accessed = 1'h0;
+        taskBuf_3_meta_tagErr = 1'h0;
+        taskBuf_3_meta_dataErr = 1'h0;
+        taskBuf_3_metaWen = 1'h0;
+        taskBuf_3_tagWen = 1'h0;
+        taskBuf_3_dsWen = 1'h0;
+        taskBuf_3_wayMask = 8'h0;
+        taskBuf_3_replTask = 1'h0;
+        taskBuf_3_cmoTask = 1'h0;
+        taskBuf_3_cmoAll = 1'h0;
+        taskBuf_3_mergeA = 1'h0;
+        taskBuf_3_aMergeTask_alias = 1'h0;
+        taskBuf_3_aMergeTask_isKeyword = 1'h0;
+        taskBuf_3_aMergeTask_meta_dirty = 1'h0;
+        taskBuf_3_aMergeTask_meta_clients = 1'h0;
+        taskBuf_3_aMergeTask_meta_alias = 1'h0;
+        taskBuf_3_aMergeTask_meta_prefetch = 1'h0;
+        taskBuf_3_aMergeTask_meta_accessed = 1'h0;
+        taskBuf_3_aMergeTask_meta_tagErr = 1'h0;
+        taskBuf_3_aMergeTask_meta_dataErr = 1'h0;
+        taskBuf_3_snpHitRelease = 1'h0;
+        taskBuf_3_snpHitReleaseToInval = 1'h0;
+        taskBuf_3_snpHitReleaseToClean = 1'h0;
+        taskBuf_3_snpHitReleaseWithData = 1'h0;
+        taskBuf_3_snpHitReleaseMeta_dirty = 1'h0;
+        taskBuf_3_snpHitReleaseMeta_clients = 1'h0;
+        taskBuf_3_snpHitReleaseMeta_alias = 1'h0;
+        taskBuf_3_snpHitReleaseMeta_prefetch = 1'h0;
+        taskBuf_3_snpHitReleaseMeta_accessed = 1'h0;
+        taskBuf_3_snpHitReleaseMeta_tagErr = 1'h0;
+        taskBuf_3_snpHitReleaseMeta_dataErr = 1'h0;
+        taskBuf_3_retToSrc = 1'h0;
+        taskBuf_3_likelyshared = 1'h0;
+        taskBuf_3_expCompAck = 1'h0;
+        taskBuf_3_allowRetry = 1'h0;
+        taskBuf_3_memAttr_allocate = 1'h0;
+        taskBuf_3_memAttr_cacheable = 1'h0;
+        taskBuf_3_memAttr_device = 1'h0;
+        taskBuf_3_memAttr_ewa = 1'h0;
+        taskBuf_3_traceTag = 1'h0;
+        taskValids_0 = 1'h0;
+        taskValids_1 = 1'h0;
+        taskValids_2 = 1'h0;
+        taskValids_3 = 1'h0;
+        nextPtrReg = 2'h0;
+        probeAckDataBuf = 256'h0;
+        io_refillBufWrite_valid_REG = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  TwoLevelRRArbiter_4 taskArb (
+    .clock                                      (clock),
+    .reset                                      (reset),
+    .io_in_0_ready                              (_taskArb_io_in_0_ready),
+    .io_in_0_valid                              (taskValids_0),
+    .io_in_0_bits_channel                       (taskBuf_0_channel),
+    .io_in_0_bits_txChannel                     (3'h0),
+    .io_in_0_bits_set                           (taskBuf_0_set),
+    .io_in_0_bits_tag                           (taskBuf_0_tag),
+    .io_in_0_bits_off                           (taskBuf_0_off),
+    .io_in_0_bits_alias                         (taskBuf_0_alias),
+    .io_in_0_bits_vaddr                         (44'h0),
+    .io_in_0_bits_isKeyword                     (taskBuf_0_isKeyword),
+    .io_in_0_bits_opcode                        (taskBuf_0_opcode),
+    .io_in_0_bits_param                         (taskBuf_0_param),
+    .io_in_0_bits_size                          (taskBuf_0_size),
+    .io_in_0_bits_sourceId                      (taskBuf_0_sourceId),
+    .io_in_0_bits_bufIdx                        (taskBuf_0_bufIdx),
+    .io_in_0_bits_needProbeAckData              (taskBuf_0_needProbeAckData),
+    .io_in_0_bits_denied                        (taskBuf_0_denied),
+    .io_in_0_bits_corrupt                       (taskBuf_0_corrupt),
+    .io_in_0_bits_mshrTask                      (taskBuf_0_mshrTask),
+    .io_in_0_bits_mshrId                        (8'h0),
+    .io_in_0_bits_aliasTask                     (taskBuf_0_aliasTask),
+    .io_in_0_bits_useProbeData                  (taskBuf_0_useProbeData),
+    .io_in_0_bits_mshrRetry                     (taskBuf_0_mshrRetry),
+    .io_in_0_bits_readProbeDataDown             (taskBuf_0_readProbeDataDown),
+    .io_in_0_bits_fromL2pft                     (taskBuf_0_fromL2pft),
+    .io_in_0_bits_needHint                      (taskBuf_0_needHint),
+    .io_in_0_bits_dirty                         (taskBuf_0_dirty),
+    .io_in_0_bits_way                           (3'h0),
+    .io_in_0_bits_meta_dirty                    (taskBuf_0_meta_dirty),
+    .io_in_0_bits_meta_state                    (2'h0),
+    .io_in_0_bits_meta_clients                  (taskBuf_0_meta_clients),
+    .io_in_0_bits_meta_alias                    (taskBuf_0_meta_alias),
+    .io_in_0_bits_meta_prefetch                 (taskBuf_0_meta_prefetch),
+    .io_in_0_bits_meta_prefetchSrc              (4'h0),
+    .io_in_0_bits_meta_accessed                 (taskBuf_0_meta_accessed),
+    .io_in_0_bits_meta_tagErr                   (taskBuf_0_meta_tagErr),
+    .io_in_0_bits_meta_dataErr                  (taskBuf_0_meta_dataErr),
+    .io_in_0_bits_metaWen                       (taskBuf_0_metaWen),
+    .io_in_0_bits_tagWen                        (taskBuf_0_tagWen),
+    .io_in_0_bits_dsWen                         (taskBuf_0_dsWen),
+    .io_in_0_bits_wayMask                       (taskBuf_0_wayMask),
+    .io_in_0_bits_replTask                      (taskBuf_0_replTask),
+    .io_in_0_bits_cmoTask                       (taskBuf_0_cmoTask),
+    .io_in_0_bits_cmoAll                        (taskBuf_0_cmoAll),
+    .io_in_0_bits_reqSource                     (5'h0),
+    .io_in_0_bits_mergeA                        (taskBuf_0_mergeA),
+    .io_in_0_bits_aMergeTask_off                (6'h0),
+    .io_in_0_bits_aMergeTask_alias              (taskBuf_0_aMergeTask_alias),
+    .io_in_0_bits_aMergeTask_vaddr              (44'h0),
+    .io_in_0_bits_aMergeTask_isKeyword          (taskBuf_0_aMergeTask_isKeyword),
+    .io_in_0_bits_aMergeTask_opcode             (3'h0),
+    .io_in_0_bits_aMergeTask_param              (3'h0),
+    .io_in_0_bits_aMergeTask_sourceId           (7'h0),
+    .io_in_0_bits_aMergeTask_meta_dirty         (taskBuf_0_aMergeTask_meta_dirty),
+    .io_in_0_bits_aMergeTask_meta_state         (2'h0),
+    .io_in_0_bits_aMergeTask_meta_clients       (taskBuf_0_aMergeTask_meta_clients),
+    .io_in_0_bits_aMergeTask_meta_alias         (taskBuf_0_aMergeTask_meta_alias),
+    .io_in_0_bits_aMergeTask_meta_prefetch      (taskBuf_0_aMergeTask_meta_prefetch),
+    .io_in_0_bits_aMergeTask_meta_prefetchSrc   (4'h0),
+    .io_in_0_bits_aMergeTask_meta_accessed      (taskBuf_0_aMergeTask_meta_accessed),
+    .io_in_0_bits_aMergeTask_meta_tagErr        (taskBuf_0_aMergeTask_meta_tagErr),
+    .io_in_0_bits_aMergeTask_meta_dataErr       (taskBuf_0_aMergeTask_meta_dataErr),
+    .io_in_0_bits_snpHitRelease                 (taskBuf_0_snpHitRelease),
+    .io_in_0_bits_snpHitReleaseToInval          (taskBuf_0_snpHitReleaseToInval),
+    .io_in_0_bits_snpHitReleaseToClean          (taskBuf_0_snpHitReleaseToClean),
+    .io_in_0_bits_snpHitReleaseWithData         (taskBuf_0_snpHitReleaseWithData),
+    .io_in_0_bits_snpHitReleaseIdx              (8'h0),
+    .io_in_0_bits_snpHitReleaseMeta_dirty       (taskBuf_0_snpHitReleaseMeta_dirty),
+    .io_in_0_bits_snpHitReleaseMeta_state       (2'h0),
+    .io_in_0_bits_snpHitReleaseMeta_clients     (taskBuf_0_snpHitReleaseMeta_clients),
+    .io_in_0_bits_snpHitReleaseMeta_alias       (taskBuf_0_snpHitReleaseMeta_alias),
+    .io_in_0_bits_snpHitReleaseMeta_prefetch    (taskBuf_0_snpHitReleaseMeta_prefetch),
+    .io_in_0_bits_snpHitReleaseMeta_prefetchSrc (4'h0),
+    .io_in_0_bits_snpHitReleaseMeta_accessed    (taskBuf_0_snpHitReleaseMeta_accessed),
+    .io_in_0_bits_snpHitReleaseMeta_tagErr      (taskBuf_0_snpHitReleaseMeta_tagErr),
+    .io_in_0_bits_snpHitReleaseMeta_dataErr     (taskBuf_0_snpHitReleaseMeta_dataErr),
+    .io_in_0_bits_tgtID                         (11'h0),
+    .io_in_0_bits_srcID                         (11'h0),
+    .io_in_0_bits_txnID                         (12'h0),
+    .io_in_0_bits_homeNID                       (11'h0),
+    .io_in_0_bits_dbID                          (12'h0),
+    .io_in_0_bits_fwdNID                        (11'h0),
+    .io_in_0_bits_fwdTxnID                      (12'h0),
+    .io_in_0_bits_chiOpcode                     (7'h0),
+    .io_in_0_bits_resp                          (3'h0),
+    .io_in_0_bits_fwdState                      (3'h0),
+    .io_in_0_bits_pCrdType                      (4'h0),
+    .io_in_0_bits_retToSrc                      (taskBuf_0_retToSrc),
+    .io_in_0_bits_likelyshared                  (taskBuf_0_likelyshared),
+    .io_in_0_bits_expCompAck                    (taskBuf_0_expCompAck),
+    .io_in_0_bits_allowRetry                    (taskBuf_0_allowRetry),
+    .io_in_0_bits_memAttr_allocate              (taskBuf_0_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable             (taskBuf_0_memAttr_cacheable),
+    .io_in_0_bits_memAttr_device                (taskBuf_0_memAttr_device),
+    .io_in_0_bits_memAttr_ewa                   (taskBuf_0_memAttr_ewa),
+    .io_in_0_bits_traceTag                      (taskBuf_0_traceTag),
+    .io_in_1_ready                              (_taskArb_io_in_1_ready),
+    .io_in_1_valid                              (taskValids_1),
+    .io_in_1_bits_channel                       (taskBuf_1_channel),
+    .io_in_1_bits_txChannel                     (3'h0),
+    .io_in_1_bits_set                           (taskBuf_1_set),
+    .io_in_1_bits_tag                           (taskBuf_1_tag),
+    .io_in_1_bits_off                           (taskBuf_1_off),
+    .io_in_1_bits_alias                         (taskBuf_1_alias),
+    .io_in_1_bits_vaddr                         (44'h0),
+    .io_in_1_bits_isKeyword                     (taskBuf_1_isKeyword),
+    .io_in_1_bits_opcode                        (taskBuf_1_opcode),
+    .io_in_1_bits_param                         (taskBuf_1_param),
+    .io_in_1_bits_size                          (taskBuf_1_size),
+    .io_in_1_bits_sourceId                      (taskBuf_1_sourceId),
+    .io_in_1_bits_bufIdx                        (taskBuf_1_bufIdx),
+    .io_in_1_bits_needProbeAckData              (taskBuf_1_needProbeAckData),
+    .io_in_1_bits_denied                        (taskBuf_1_denied),
+    .io_in_1_bits_corrupt                       (taskBuf_1_corrupt),
+    .io_in_1_bits_mshrTask                      (taskBuf_1_mshrTask),
+    .io_in_1_bits_mshrId                        (8'h0),
+    .io_in_1_bits_aliasTask                     (taskBuf_1_aliasTask),
+    .io_in_1_bits_useProbeData                  (taskBuf_1_useProbeData),
+    .io_in_1_bits_mshrRetry                     (taskBuf_1_mshrRetry),
+    .io_in_1_bits_readProbeDataDown             (taskBuf_1_readProbeDataDown),
+    .io_in_1_bits_fromL2pft                     (taskBuf_1_fromL2pft),
+    .io_in_1_bits_needHint                      (taskBuf_1_needHint),
+    .io_in_1_bits_dirty                         (taskBuf_1_dirty),
+    .io_in_1_bits_way                           (3'h0),
+    .io_in_1_bits_meta_dirty                    (taskBuf_1_meta_dirty),
+    .io_in_1_bits_meta_state                    (2'h0),
+    .io_in_1_bits_meta_clients                  (taskBuf_1_meta_clients),
+    .io_in_1_bits_meta_alias                    (taskBuf_1_meta_alias),
+    .io_in_1_bits_meta_prefetch                 (taskBuf_1_meta_prefetch),
+    .io_in_1_bits_meta_prefetchSrc              (4'h0),
+    .io_in_1_bits_meta_accessed                 (taskBuf_1_meta_accessed),
+    .io_in_1_bits_meta_tagErr                   (taskBuf_1_meta_tagErr),
+    .io_in_1_bits_meta_dataErr                  (taskBuf_1_meta_dataErr),
+    .io_in_1_bits_metaWen                       (taskBuf_1_metaWen),
+    .io_in_1_bits_tagWen                        (taskBuf_1_tagWen),
+    .io_in_1_bits_dsWen                         (taskBuf_1_dsWen),
+    .io_in_1_bits_wayMask                       (taskBuf_1_wayMask),
+    .io_in_1_bits_replTask                      (taskBuf_1_replTask),
+    .io_in_1_bits_cmoTask                       (taskBuf_1_cmoTask),
+    .io_in_1_bits_cmoAll                        (taskBuf_1_cmoAll),
+    .io_in_1_bits_reqSource                     (5'h0),
+    .io_in_1_bits_mergeA                        (taskBuf_1_mergeA),
+    .io_in_1_bits_aMergeTask_off                (6'h0),
+    .io_in_1_bits_aMergeTask_alias              (taskBuf_1_aMergeTask_alias),
+    .io_in_1_bits_aMergeTask_vaddr              (44'h0),
+    .io_in_1_bits_aMergeTask_isKeyword          (taskBuf_1_aMergeTask_isKeyword),
+    .io_in_1_bits_aMergeTask_opcode             (3'h0),
+    .io_in_1_bits_aMergeTask_param              (3'h0),
+    .io_in_1_bits_aMergeTask_sourceId           (7'h0),
+    .io_in_1_bits_aMergeTask_meta_dirty         (taskBuf_1_aMergeTask_meta_dirty),
+    .io_in_1_bits_aMergeTask_meta_state         (2'h0),
+    .io_in_1_bits_aMergeTask_meta_clients       (taskBuf_1_aMergeTask_meta_clients),
+    .io_in_1_bits_aMergeTask_meta_alias         (taskBuf_1_aMergeTask_meta_alias),
+    .io_in_1_bits_aMergeTask_meta_prefetch      (taskBuf_1_aMergeTask_meta_prefetch),
+    .io_in_1_bits_aMergeTask_meta_prefetchSrc   (4'h0),
+    .io_in_1_bits_aMergeTask_meta_accessed      (taskBuf_1_aMergeTask_meta_accessed),
+    .io_in_1_bits_aMergeTask_meta_tagErr        (taskBuf_1_aMergeTask_meta_tagErr),
+    .io_in_1_bits_aMergeTask_meta_dataErr       (taskBuf_1_aMergeTask_meta_dataErr),
+    .io_in_1_bits_snpHitRelease                 (taskBuf_1_snpHitRelease),
+    .io_in_1_bits_snpHitReleaseToInval          (taskBuf_1_snpHitReleaseToInval),
+    .io_in_1_bits_snpHitReleaseToClean          (taskBuf_1_snpHitReleaseToClean),
+    .io_in_1_bits_snpHitReleaseWithData         (taskBuf_1_snpHitReleaseWithData),
+    .io_in_1_bits_snpHitReleaseIdx              (8'h0),
+    .io_in_1_bits_snpHitReleaseMeta_dirty       (taskBuf_1_snpHitReleaseMeta_dirty),
+    .io_in_1_bits_snpHitReleaseMeta_state       (2'h0),
+    .io_in_1_bits_snpHitReleaseMeta_clients     (taskBuf_1_snpHitReleaseMeta_clients),
+    .io_in_1_bits_snpHitReleaseMeta_alias       (taskBuf_1_snpHitReleaseMeta_alias),
+    .io_in_1_bits_snpHitReleaseMeta_prefetch    (taskBuf_1_snpHitReleaseMeta_prefetch),
+    .io_in_1_bits_snpHitReleaseMeta_prefetchSrc (4'h0),
+    .io_in_1_bits_snpHitReleaseMeta_accessed    (taskBuf_1_snpHitReleaseMeta_accessed),
+    .io_in_1_bits_snpHitReleaseMeta_tagErr      (taskBuf_1_snpHitReleaseMeta_tagErr),
+    .io_in_1_bits_snpHitReleaseMeta_dataErr     (taskBuf_1_snpHitReleaseMeta_dataErr),
+    .io_in_1_bits_tgtID                         (11'h0),
+    .io_in_1_bits_srcID                         (11'h0),
+    .io_in_1_bits_txnID                         (12'h0),
+    .io_in_1_bits_homeNID                       (11'h0),
+    .io_in_1_bits_dbID                          (12'h0),
+    .io_in_1_bits_fwdNID                        (11'h0),
+    .io_in_1_bits_fwdTxnID                      (12'h0),
+    .io_in_1_bits_chiOpcode                     (7'h0),
+    .io_in_1_bits_resp                          (3'h0),
+    .io_in_1_bits_fwdState                      (3'h0),
+    .io_in_1_bits_pCrdType                      (4'h0),
+    .io_in_1_bits_retToSrc                      (taskBuf_1_retToSrc),
+    .io_in_1_bits_likelyshared                  (taskBuf_1_likelyshared),
+    .io_in_1_bits_expCompAck                    (taskBuf_1_expCompAck),
+    .io_in_1_bits_allowRetry                    (taskBuf_1_allowRetry),
+    .io_in_1_bits_memAttr_allocate              (taskBuf_1_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable             (taskBuf_1_memAttr_cacheable),
+    .io_in_1_bits_memAttr_device                (taskBuf_1_memAttr_device),
+    .io_in_1_bits_memAttr_ewa                   (taskBuf_1_memAttr_ewa),
+    .io_in_1_bits_traceTag                      (taskBuf_1_traceTag),
+    .io_in_2_ready                              (_taskArb_io_in_2_ready),
+    .io_in_2_valid                              (taskValids_2),
+    .io_in_2_bits_channel                       (taskBuf_2_channel),
+    .io_in_2_bits_txChannel                     (3'h0),
+    .io_in_2_bits_set                           (taskBuf_2_set),
+    .io_in_2_bits_tag                           (taskBuf_2_tag),
+    .io_in_2_bits_off                           (taskBuf_2_off),
+    .io_in_2_bits_alias                         (taskBuf_2_alias),
+    .io_in_2_bits_vaddr                         (44'h0),
+    .io_in_2_bits_isKeyword                     (taskBuf_2_isKeyword),
+    .io_in_2_bits_opcode                        (taskBuf_2_opcode),
+    .io_in_2_bits_param                         (taskBuf_2_param),
+    .io_in_2_bits_size                          (taskBuf_2_size),
+    .io_in_2_bits_sourceId                      (taskBuf_2_sourceId),
+    .io_in_2_bits_bufIdx                        (taskBuf_2_bufIdx),
+    .io_in_2_bits_needProbeAckData              (taskBuf_2_needProbeAckData),
+    .io_in_2_bits_denied                        (taskBuf_2_denied),
+    .io_in_2_bits_corrupt                       (taskBuf_2_corrupt),
+    .io_in_2_bits_mshrTask                      (taskBuf_2_mshrTask),
+    .io_in_2_bits_mshrId                        (8'h0),
+    .io_in_2_bits_aliasTask                     (taskBuf_2_aliasTask),
+    .io_in_2_bits_useProbeData                  (taskBuf_2_useProbeData),
+    .io_in_2_bits_mshrRetry                     (taskBuf_2_mshrRetry),
+    .io_in_2_bits_readProbeDataDown             (taskBuf_2_readProbeDataDown),
+    .io_in_2_bits_fromL2pft                     (taskBuf_2_fromL2pft),
+    .io_in_2_bits_needHint                      (taskBuf_2_needHint),
+    .io_in_2_bits_dirty                         (taskBuf_2_dirty),
+    .io_in_2_bits_way                           (3'h0),
+    .io_in_2_bits_meta_dirty                    (taskBuf_2_meta_dirty),
+    .io_in_2_bits_meta_state                    (2'h0),
+    .io_in_2_bits_meta_clients                  (taskBuf_2_meta_clients),
+    .io_in_2_bits_meta_alias                    (taskBuf_2_meta_alias),
+    .io_in_2_bits_meta_prefetch                 (taskBuf_2_meta_prefetch),
+    .io_in_2_bits_meta_prefetchSrc              (4'h0),
+    .io_in_2_bits_meta_accessed                 (taskBuf_2_meta_accessed),
+    .io_in_2_bits_meta_tagErr                   (taskBuf_2_meta_tagErr),
+    .io_in_2_bits_meta_dataErr                  (taskBuf_2_meta_dataErr),
+    .io_in_2_bits_metaWen                       (taskBuf_2_metaWen),
+    .io_in_2_bits_tagWen                        (taskBuf_2_tagWen),
+    .io_in_2_bits_dsWen                         (taskBuf_2_dsWen),
+    .io_in_2_bits_wayMask                       (taskBuf_2_wayMask),
+    .io_in_2_bits_replTask                      (taskBuf_2_replTask),
+    .io_in_2_bits_cmoTask                       (taskBuf_2_cmoTask),
+    .io_in_2_bits_cmoAll                        (taskBuf_2_cmoAll),
+    .io_in_2_bits_reqSource                     (5'h0),
+    .io_in_2_bits_mergeA                        (taskBuf_2_mergeA),
+    .io_in_2_bits_aMergeTask_off                (6'h0),
+    .io_in_2_bits_aMergeTask_alias              (taskBuf_2_aMergeTask_alias),
+    .io_in_2_bits_aMergeTask_vaddr              (44'h0),
+    .io_in_2_bits_aMergeTask_isKeyword          (taskBuf_2_aMergeTask_isKeyword),
+    .io_in_2_bits_aMergeTask_opcode             (3'h0),
+    .io_in_2_bits_aMergeTask_param              (3'h0),
+    .io_in_2_bits_aMergeTask_sourceId           (7'h0),
+    .io_in_2_bits_aMergeTask_meta_dirty         (taskBuf_2_aMergeTask_meta_dirty),
+    .io_in_2_bits_aMergeTask_meta_state         (2'h0),
+    .io_in_2_bits_aMergeTask_meta_clients       (taskBuf_2_aMergeTask_meta_clients),
+    .io_in_2_bits_aMergeTask_meta_alias         (taskBuf_2_aMergeTask_meta_alias),
+    .io_in_2_bits_aMergeTask_meta_prefetch      (taskBuf_2_aMergeTask_meta_prefetch),
+    .io_in_2_bits_aMergeTask_meta_prefetchSrc   (4'h0),
+    .io_in_2_bits_aMergeTask_meta_accessed      (taskBuf_2_aMergeTask_meta_accessed),
+    .io_in_2_bits_aMergeTask_meta_tagErr        (taskBuf_2_aMergeTask_meta_tagErr),
+    .io_in_2_bits_aMergeTask_meta_dataErr       (taskBuf_2_aMergeTask_meta_dataErr),
+    .io_in_2_bits_snpHitRelease                 (taskBuf_2_snpHitRelease),
+    .io_in_2_bits_snpHitReleaseToInval          (taskBuf_2_snpHitReleaseToInval),
+    .io_in_2_bits_snpHitReleaseToClean          (taskBuf_2_snpHitReleaseToClean),
+    .io_in_2_bits_snpHitReleaseWithData         (taskBuf_2_snpHitReleaseWithData),
+    .io_in_2_bits_snpHitReleaseIdx              (8'h0),
+    .io_in_2_bits_snpHitReleaseMeta_dirty       (taskBuf_2_snpHitReleaseMeta_dirty),
+    .io_in_2_bits_snpHitReleaseMeta_state       (2'h0),
+    .io_in_2_bits_snpHitReleaseMeta_clients     (taskBuf_2_snpHitReleaseMeta_clients),
+    .io_in_2_bits_snpHitReleaseMeta_alias       (taskBuf_2_snpHitReleaseMeta_alias),
+    .io_in_2_bits_snpHitReleaseMeta_prefetch    (taskBuf_2_snpHitReleaseMeta_prefetch),
+    .io_in_2_bits_snpHitReleaseMeta_prefetchSrc (4'h0),
+    .io_in_2_bits_snpHitReleaseMeta_accessed    (taskBuf_2_snpHitReleaseMeta_accessed),
+    .io_in_2_bits_snpHitReleaseMeta_tagErr      (taskBuf_2_snpHitReleaseMeta_tagErr),
+    .io_in_2_bits_snpHitReleaseMeta_dataErr     (taskBuf_2_snpHitReleaseMeta_dataErr),
+    .io_in_2_bits_tgtID                         (11'h0),
+    .io_in_2_bits_srcID                         (11'h0),
+    .io_in_2_bits_txnID                         (12'h0),
+    .io_in_2_bits_homeNID                       (11'h0),
+    .io_in_2_bits_dbID                          (12'h0),
+    .io_in_2_bits_fwdNID                        (11'h0),
+    .io_in_2_bits_fwdTxnID                      (12'h0),
+    .io_in_2_bits_chiOpcode                     (7'h0),
+    .io_in_2_bits_resp                          (3'h0),
+    .io_in_2_bits_fwdState                      (3'h0),
+    .io_in_2_bits_pCrdType                      (4'h0),
+    .io_in_2_bits_retToSrc                      (taskBuf_2_retToSrc),
+    .io_in_2_bits_likelyshared                  (taskBuf_2_likelyshared),
+    .io_in_2_bits_expCompAck                    (taskBuf_2_expCompAck),
+    .io_in_2_bits_allowRetry                    (taskBuf_2_allowRetry),
+    .io_in_2_bits_memAttr_allocate              (taskBuf_2_memAttr_allocate),
+    .io_in_2_bits_memAttr_cacheable             (taskBuf_2_memAttr_cacheable),
+    .io_in_2_bits_memAttr_device                (taskBuf_2_memAttr_device),
+    .io_in_2_bits_memAttr_ewa                   (taskBuf_2_memAttr_ewa),
+    .io_in_2_bits_traceTag                      (taskBuf_2_traceTag),
+    .io_in_3_ready                              (_taskArb_io_in_3_ready),
+    .io_in_3_valid                              (taskValids_3),
+    .io_in_3_bits_channel                       (taskBuf_3_channel),
+    .io_in_3_bits_txChannel                     (3'h0),
+    .io_in_3_bits_set                           (taskBuf_3_set),
+    .io_in_3_bits_tag                           (taskBuf_3_tag),
+    .io_in_3_bits_off                           (taskBuf_3_off),
+    .io_in_3_bits_alias                         (taskBuf_3_alias),
+    .io_in_3_bits_vaddr                         (44'h0),
+    .io_in_3_bits_isKeyword                     (taskBuf_3_isKeyword),
+    .io_in_3_bits_opcode                        (taskBuf_3_opcode),
+    .io_in_3_bits_param                         (taskBuf_3_param),
+    .io_in_3_bits_size                          (taskBuf_3_size),
+    .io_in_3_bits_sourceId                      (taskBuf_3_sourceId),
+    .io_in_3_bits_bufIdx                        (taskBuf_3_bufIdx),
+    .io_in_3_bits_needProbeAckData              (taskBuf_3_needProbeAckData),
+    .io_in_3_bits_denied                        (taskBuf_3_denied),
+    .io_in_3_bits_corrupt                       (taskBuf_3_corrupt),
+    .io_in_3_bits_mshrTask                      (taskBuf_3_mshrTask),
+    .io_in_3_bits_mshrId                        (8'h0),
+    .io_in_3_bits_aliasTask                     (taskBuf_3_aliasTask),
+    .io_in_3_bits_useProbeData                  (taskBuf_3_useProbeData),
+    .io_in_3_bits_mshrRetry                     (taskBuf_3_mshrRetry),
+    .io_in_3_bits_readProbeDataDown             (taskBuf_3_readProbeDataDown),
+    .io_in_3_bits_fromL2pft                     (taskBuf_3_fromL2pft),
+    .io_in_3_bits_needHint                      (taskBuf_3_needHint),
+    .io_in_3_bits_dirty                         (taskBuf_3_dirty),
+    .io_in_3_bits_way                           (3'h0),
+    .io_in_3_bits_meta_dirty                    (taskBuf_3_meta_dirty),
+    .io_in_3_bits_meta_state                    (2'h0),
+    .io_in_3_bits_meta_clients                  (taskBuf_3_meta_clients),
+    .io_in_3_bits_meta_alias                    (taskBuf_3_meta_alias),
+    .io_in_3_bits_meta_prefetch                 (taskBuf_3_meta_prefetch),
+    .io_in_3_bits_meta_prefetchSrc              (4'h0),
+    .io_in_3_bits_meta_accessed                 (taskBuf_3_meta_accessed),
+    .io_in_3_bits_meta_tagErr                   (taskBuf_3_meta_tagErr),
+    .io_in_3_bits_meta_dataErr                  (taskBuf_3_meta_dataErr),
+    .io_in_3_bits_metaWen                       (taskBuf_3_metaWen),
+    .io_in_3_bits_tagWen                        (taskBuf_3_tagWen),
+    .io_in_3_bits_dsWen                         (taskBuf_3_dsWen),
+    .io_in_3_bits_wayMask                       (taskBuf_3_wayMask),
+    .io_in_3_bits_replTask                      (taskBuf_3_replTask),
+    .io_in_3_bits_cmoTask                       (taskBuf_3_cmoTask),
+    .io_in_3_bits_cmoAll                        (taskBuf_3_cmoAll),
+    .io_in_3_bits_reqSource                     (5'h0),
+    .io_in_3_bits_mergeA                        (taskBuf_3_mergeA),
+    .io_in_3_bits_aMergeTask_off                (6'h0),
+    .io_in_3_bits_aMergeTask_alias              (taskBuf_3_aMergeTask_alias),
+    .io_in_3_bits_aMergeTask_vaddr              (44'h0),
+    .io_in_3_bits_aMergeTask_isKeyword          (taskBuf_3_aMergeTask_isKeyword),
+    .io_in_3_bits_aMergeTask_opcode             (3'h0),
+    .io_in_3_bits_aMergeTask_param              (3'h0),
+    .io_in_3_bits_aMergeTask_sourceId           (7'h0),
+    .io_in_3_bits_aMergeTask_meta_dirty         (taskBuf_3_aMergeTask_meta_dirty),
+    .io_in_3_bits_aMergeTask_meta_state         (2'h0),
+    .io_in_3_bits_aMergeTask_meta_clients       (taskBuf_3_aMergeTask_meta_clients),
+    .io_in_3_bits_aMergeTask_meta_alias         (taskBuf_3_aMergeTask_meta_alias),
+    .io_in_3_bits_aMergeTask_meta_prefetch      (taskBuf_3_aMergeTask_meta_prefetch),
+    .io_in_3_bits_aMergeTask_meta_prefetchSrc   (4'h0),
+    .io_in_3_bits_aMergeTask_meta_accessed      (taskBuf_3_aMergeTask_meta_accessed),
+    .io_in_3_bits_aMergeTask_meta_tagErr        (taskBuf_3_aMergeTask_meta_tagErr),
+    .io_in_3_bits_aMergeTask_meta_dataErr       (taskBuf_3_aMergeTask_meta_dataErr),
+    .io_in_3_bits_snpHitRelease                 (taskBuf_3_snpHitRelease),
+    .io_in_3_bits_snpHitReleaseToInval          (taskBuf_3_snpHitReleaseToInval),
+    .io_in_3_bits_snpHitReleaseToClean          (taskBuf_3_snpHitReleaseToClean),
+    .io_in_3_bits_snpHitReleaseWithData         (taskBuf_3_snpHitReleaseWithData),
+    .io_in_3_bits_snpHitReleaseIdx              (8'h0),
+    .io_in_3_bits_snpHitReleaseMeta_dirty       (taskBuf_3_snpHitReleaseMeta_dirty),
+    .io_in_3_bits_snpHitReleaseMeta_state       (2'h0),
+    .io_in_3_bits_snpHitReleaseMeta_clients     (taskBuf_3_snpHitReleaseMeta_clients),
+    .io_in_3_bits_snpHitReleaseMeta_alias       (taskBuf_3_snpHitReleaseMeta_alias),
+    .io_in_3_bits_snpHitReleaseMeta_prefetch    (taskBuf_3_snpHitReleaseMeta_prefetch),
+    .io_in_3_bits_snpHitReleaseMeta_prefetchSrc (4'h0),
+    .io_in_3_bits_snpHitReleaseMeta_accessed    (taskBuf_3_snpHitReleaseMeta_accessed),
+    .io_in_3_bits_snpHitReleaseMeta_tagErr      (taskBuf_3_snpHitReleaseMeta_tagErr),
+    .io_in_3_bits_snpHitReleaseMeta_dataErr     (taskBuf_3_snpHitReleaseMeta_dataErr),
+    .io_in_3_bits_tgtID                         (11'h0),
+    .io_in_3_bits_srcID                         (11'h0),
+    .io_in_3_bits_txnID                         (12'h0),
+    .io_in_3_bits_homeNID                       (11'h0),
+    .io_in_3_bits_dbID                          (12'h0),
+    .io_in_3_bits_fwdNID                        (11'h0),
+    .io_in_3_bits_fwdTxnID                      (12'h0),
+    .io_in_3_bits_chiOpcode                     (7'h0),
+    .io_in_3_bits_resp                          (3'h0),
+    .io_in_3_bits_fwdState                      (3'h0),
+    .io_in_3_bits_pCrdType                      (4'h0),
+    .io_in_3_bits_retToSrc                      (taskBuf_3_retToSrc),
+    .io_in_3_bits_likelyshared                  (taskBuf_3_likelyshared),
+    .io_in_3_bits_expCompAck                    (taskBuf_3_expCompAck),
+    .io_in_3_bits_allowRetry                    (taskBuf_3_allowRetry),
+    .io_in_3_bits_memAttr_allocate              (taskBuf_3_memAttr_allocate),
+    .io_in_3_bits_memAttr_cacheable             (taskBuf_3_memAttr_cacheable),
+    .io_in_3_bits_memAttr_device                (taskBuf_3_memAttr_device),
+    .io_in_3_bits_memAttr_ewa                   (taskBuf_3_memAttr_ewa),
+    .io_in_3_bits_traceTag                      (taskBuf_3_traceTag),
+    .io_out_ready                               (io_task_ready),
+    .io_out_valid                               (_taskArb_io_out_valid),
+    .io_out_bits_channel                        (io_task_bits_channel),
+    .io_out_bits_txChannel                      (io_task_bits_txChannel),
+    .io_out_bits_set                            (_taskArb_io_out_bits_set),
+    .io_out_bits_tag                            (_taskArb_io_out_bits_tag),
+    .io_out_bits_off                            (io_task_bits_off),
+    .io_out_bits_alias                          (io_task_bits_alias),
+    .io_out_bits_vaddr                          (io_task_bits_vaddr),
+    .io_out_bits_isKeyword                      (io_task_bits_isKeyword),
+    .io_out_bits_opcode                         (_taskArb_io_out_bits_opcode),
+    .io_out_bits_param                          (io_task_bits_param),
+    .io_out_bits_size                           (io_task_bits_size),
+    .io_out_bits_sourceId                       (io_task_bits_sourceId),
+    .io_out_bits_bufIdx                         (_taskArb_io_out_bits_bufIdx),
+    .io_out_bits_needProbeAckData               (io_task_bits_needProbeAckData),
+    .io_out_bits_denied                         (io_task_bits_denied),
+    .io_out_bits_corrupt                        (io_task_bits_corrupt),
+    .io_out_bits_mshrTask                       (io_task_bits_mshrTask),
+    .io_out_bits_mshrId                         (io_task_bits_mshrId),
+    .io_out_bits_aliasTask                      (io_task_bits_aliasTask),
+    .io_out_bits_useProbeData                   (io_task_bits_useProbeData),
+    .io_out_bits_mshrRetry                      (io_task_bits_mshrRetry),
+    .io_out_bits_readProbeDataDown              (io_task_bits_readProbeDataDown),
+    .io_out_bits_fromL2pft                      (io_task_bits_fromL2pft),
+    .io_out_bits_needHint                       (io_task_bits_needHint),
+    .io_out_bits_dirty                          (io_task_bits_dirty),
+    .io_out_bits_way                            (io_task_bits_way),
+    .io_out_bits_meta_dirty                     (io_task_bits_meta_dirty),
+    .io_out_bits_meta_state                     (io_task_bits_meta_state),
+    .io_out_bits_meta_clients                   (io_task_bits_meta_clients),
+    .io_out_bits_meta_alias                     (io_task_bits_meta_alias),
+    .io_out_bits_meta_prefetch                  (io_task_bits_meta_prefetch),
+    .io_out_bits_meta_prefetchSrc               (io_task_bits_meta_prefetchSrc),
+    .io_out_bits_meta_accessed                  (io_task_bits_meta_accessed),
+    .io_out_bits_meta_tagErr                    (io_task_bits_meta_tagErr),
+    .io_out_bits_meta_dataErr                   (io_task_bits_meta_dataErr),
+    .io_out_bits_metaWen                        (io_task_bits_metaWen),
+    .io_out_bits_tagWen                         (io_task_bits_tagWen),
+    .io_out_bits_dsWen                          (io_task_bits_dsWen),
+    .io_out_bits_wayMask                        (io_task_bits_wayMask),
+    .io_out_bits_replTask                       (io_task_bits_replTask),
+    .io_out_bits_cmoTask                        (io_task_bits_cmoTask),
+    .io_out_bits_cmoAll                         (io_task_bits_cmoAll),
+    .io_out_bits_reqSource                      (io_task_bits_reqSource),
+    .io_out_bits_mergeA                         (io_task_bits_mergeA),
+    .io_out_bits_aMergeTask_off                 (io_task_bits_aMergeTask_off),
+    .io_out_bits_aMergeTask_alias               (io_task_bits_aMergeTask_alias),
+    .io_out_bits_aMergeTask_vaddr               (io_task_bits_aMergeTask_vaddr),
+    .io_out_bits_aMergeTask_isKeyword           (io_task_bits_aMergeTask_isKeyword),
+    .io_out_bits_aMergeTask_opcode              (io_task_bits_aMergeTask_opcode),
+    .io_out_bits_aMergeTask_param               (io_task_bits_aMergeTask_param),
+    .io_out_bits_aMergeTask_sourceId            (io_task_bits_aMergeTask_sourceId),
+    .io_out_bits_aMergeTask_meta_dirty          (io_task_bits_aMergeTask_meta_dirty),
+    .io_out_bits_aMergeTask_meta_state          (io_task_bits_aMergeTask_meta_state),
+    .io_out_bits_aMergeTask_meta_clients        (io_task_bits_aMergeTask_meta_clients),
+    .io_out_bits_aMergeTask_meta_alias          (io_task_bits_aMergeTask_meta_alias),
+    .io_out_bits_aMergeTask_meta_prefetch       (io_task_bits_aMergeTask_meta_prefetch),
+    .io_out_bits_aMergeTask_meta_prefetchSrc
+      (io_task_bits_aMergeTask_meta_prefetchSrc),
+    .io_out_bits_aMergeTask_meta_accessed       (io_task_bits_aMergeTask_meta_accessed),
+    .io_out_bits_aMergeTask_meta_tagErr         (io_task_bits_aMergeTask_meta_tagErr),
+    .io_out_bits_aMergeTask_meta_dataErr        (io_task_bits_aMergeTask_meta_dataErr),
+    .io_out_bits_snpHitRelease                  (io_task_bits_snpHitRelease),
+    .io_out_bits_snpHitReleaseToInval           (io_task_bits_snpHitReleaseToInval),
+    .io_out_bits_snpHitReleaseToClean           (io_task_bits_snpHitReleaseToClean),
+    .io_out_bits_snpHitReleaseWithData          (io_task_bits_snpHitReleaseWithData),
+    .io_out_bits_snpHitReleaseIdx               (io_task_bits_snpHitReleaseIdx),
+    .io_out_bits_snpHitReleaseMeta_dirty        (io_task_bits_snpHitReleaseMeta_dirty),
+    .io_out_bits_snpHitReleaseMeta_state        (io_task_bits_snpHitReleaseMeta_state),
+    .io_out_bits_snpHitReleaseMeta_clients      (io_task_bits_snpHitReleaseMeta_clients),
+    .io_out_bits_snpHitReleaseMeta_alias        (io_task_bits_snpHitReleaseMeta_alias),
+    .io_out_bits_snpHitReleaseMeta_prefetch     (io_task_bits_snpHitReleaseMeta_prefetch),
+    .io_out_bits_snpHitReleaseMeta_prefetchSrc
+      (io_task_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_out_bits_snpHitReleaseMeta_accessed     (io_task_bits_snpHitReleaseMeta_accessed),
+    .io_out_bits_snpHitReleaseMeta_tagErr       (io_task_bits_snpHitReleaseMeta_tagErr),
+    .io_out_bits_snpHitReleaseMeta_dataErr      (io_task_bits_snpHitReleaseMeta_dataErr),
+    .io_out_bits_tgtID                          (io_task_bits_tgtID),
+    .io_out_bits_srcID                          (io_task_bits_srcID),
+    .io_out_bits_txnID                          (io_task_bits_txnID),
+    .io_out_bits_homeNID                        (io_task_bits_homeNID),
+    .io_out_bits_dbID                           (io_task_bits_dbID),
+    .io_out_bits_fwdNID                         (io_task_bits_fwdNID),
+    .io_out_bits_fwdTxnID                       (io_task_bits_fwdTxnID),
+    .io_out_bits_chiOpcode                      (io_task_bits_chiOpcode),
+    .io_out_bits_resp                           (io_task_bits_resp),
+    .io_out_bits_fwdState                       (io_task_bits_fwdState),
+    .io_out_bits_pCrdType                       (io_task_bits_pCrdType),
+    .io_out_bits_retToSrc                       (io_task_bits_retToSrc),
+    .io_out_bits_likelyshared                   (io_task_bits_likelyshared),
+    .io_out_bits_expCompAck                     (io_task_bits_expCompAck),
+    .io_out_bits_allowRetry                     (io_task_bits_allowRetry),
+    .io_out_bits_memAttr_allocate               (io_task_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable              (io_task_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device                 (io_task_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa                    (io_task_bits_memAttr_ewa),
+    .io_out_bits_traceTag                       (io_task_bits_traceTag)
+  );
+  assign io_c_ready = io_c_ready_0;
+  assign io_task_valid = _taskArb_io_out_valid;
+  assign io_task_bits_set = _taskArb_io_out_bits_set;
+  assign io_task_bits_tag = _taskArb_io_out_bits_tag;
+  assign io_task_bits_opcode = _taskArb_io_out_bits_opcode;
+  assign io_task_bits_bufIdx = _taskArb_io_out_bits_bufIdx;
+  assign io_resp_valid = io_c_valid & (~r_counter | last) & ~(io_c_bits_opcode[1]);
+  assign io_resp_set = io_c_bits_address[13:6];
+  assign io_resp_tag = io_c_bits_address[47:14];
+  assign io_resp_respInfo_opcode = io_c_bits_opcode;
+  assign io_resp_respInfo_param = io_c_bits_param;
+  assign io_resp_respInfo_last = last;
+  assign io_resp_respInfo_denied =
+    io_c_bits_corrupt & (io_c_bits_opcode == 3'h4 | io_c_bits_opcode == 3'h6);
+  assign io_resp_respInfo_corrupt =
+    io_c_bits_corrupt & (_io_releaseBufWrite_valid_T | (&io_c_bits_opcode));
+  assign io_releaseBufWrite_valid = io_c_valid & _io_releaseBufWrite_valid_T & last;
+  assign io_releaseBufWrite_bits_data_data = {io_c_bits_data, probeAckDataBuf};
+  assign io_bufResp_data_0 = REG_0;
+  assign io_bufResp_data_1 = REG_1;
+  assign io_refillBufWrite_valid = io_refillBufWrite_valid_REG;
+  assign io_refillBufWrite_bits_id = {4'h0, io_refillBufWrite_bits_id_REG};
+  assign io_refillBufWrite_bits_data_data =
+    {_GEN_0[io_refillBufWrite_bits_data_data_REG],
+     _GEN[io_refillBufWrite_bits_data_data_REG]};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/Slice.sv b/flow/designs/src/xiangshan_coupledl2/deps/Slice.sv
new file mode 100644
index 0000000000..362271608f
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/Slice.sv
@@ -0,0 +1,10069 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module Slice(
+  input          clock,
+  input          reset,
+  output         io_in_a_ready,
+  input          io_in_a_valid,
+  input  [3:0]   io_in_a_bits_opcode,
+  input  [2:0]   io_in_a_bits_param,
+  input  [2:0]   io_in_a_bits_size,
+  input  [6:0]   io_in_a_bits_source,
+  input  [47:0]  io_in_a_bits_address,
+  input  [4:0]   io_in_a_bits_user_reqSource,
+  input          io_in_a_bits_user_alias,
+  input  [43:0]  io_in_a_bits_user_vaddr,
+  input          io_in_a_bits_user_needHint,
+  input          io_in_a_bits_echo_isKeyword,
+  input          io_in_a_bits_corrupt,
+  input          io_in_b_ready,
+  output         io_in_b_valid,
+  output [2:0]   io_in_b_bits_opcode,
+  output [1:0]   io_in_b_bits_param,
+  output [47:0]  io_in_b_bits_address,
+  output [255:0] io_in_b_bits_data,
+  output         io_in_c_ready,
+  input          io_in_c_valid,
+  input  [2:0]   io_in_c_bits_opcode,
+  input  [2:0]   io_in_c_bits_param,
+  input  [2:0]   io_in_c_bits_size,
+  input  [6:0]   io_in_c_bits_source,
+  input  [47:0]  io_in_c_bits_address,
+  input  [255:0] io_in_c_bits_data,
+  input          io_in_c_bits_corrupt,
+  input          io_in_d_ready,
+  output         io_in_d_valid,
+  output [3:0]   io_in_d_bits_opcode,
+  output [1:0]   io_in_d_bits_param,
+  output [6:0]   io_in_d_bits_source,
+  output [7:0]   io_in_d_bits_sink,
+  output         io_in_d_bits_denied,
+  output         io_in_d_bits_echo_isKeyword,
+  output [255:0] io_in_d_bits_data,
+  output         io_in_d_bits_corrupt,
+  input          io_in_e_valid,
+  input  [7:0]   io_in_e_bits_sink,
+  input          io_l1Hint_ready,
+  output         io_l1Hint_valid,
+  output [6:0]   io_l1Hint_bits_sourceId,
+  output         io_l1Hint_bits_isKeyword,
+  output         io_l1Hint_bits_hasData,
+  output         io_prefetch_train_valid,
+  output [33:0]  io_prefetch_train_bits_tag,
+  output [7:0]   io_prefetch_train_bits_set,
+  output         io_prefetch_train_bits_needT,
+  output [6:0]   io_prefetch_train_bits_source,
+  output [43:0]  io_prefetch_train_bits_vaddr,
+  output         io_prefetch_train_bits_hit,
+  output         io_prefetch_train_bits_prefetched,
+  output [3:0]   io_prefetch_train_bits_pfsource,
+  output [4:0]   io_prefetch_train_bits_reqsource,
+  output         io_prefetch_req_ready,
+  input          io_prefetch_req_valid,
+  input  [33:0]  io_prefetch_req_bits_tag,
+  input  [7:0]   io_prefetch_req_bits_set,
+  input  [43:0]  io_prefetch_req_bits_vaddr,
+  input          io_prefetch_req_bits_needT,
+  input  [6:0]   io_prefetch_req_bits_source,
+  input  [4:0]   io_prefetch_req_bits_pfSource,
+  input          io_prefetch_resp_ready,
+  output         io_prefetch_resp_valid,
+  output         io_error_valid,
+  output         io_error_bits_valid,
+  output [47:0]  io_error_bits_address,
+  output         io_l2Miss,
+  input          io_out_tx_req_ready,
+  output         io_out_tx_req_valid,
+  output [3:0]   io_out_tx_req_bits_qos,
+  output [10:0]  io_out_tx_req_bits_srcID,
+  output [11:0]  io_out_tx_req_bits_txnID,
+  output [10:0]  io_out_tx_req_bits_returnNID,
+  output         io_out_tx_req_bits_stashNIDValid,
+  output [11:0]  io_out_tx_req_bits_returnTxnID,
+  output [6:0]   io_out_tx_req_bits_opcode,
+  output [47:0]  io_out_tx_req_bits_addr,
+  output         io_out_tx_req_bits_ns,
+  output         io_out_tx_req_bits_likelyshared,
+  output         io_out_tx_req_bits_allowRetry,
+  output [1:0]   io_out_tx_req_bits_order,
+  output [3:0]   io_out_tx_req_bits_pCrdType,
+  output         io_out_tx_req_bits_memAttr_allocate,
+  output         io_out_tx_req_bits_memAttr_cacheable,
+  output         io_out_tx_req_bits_memAttr_device,
+  output         io_out_tx_req_bits_memAttr_ewa,
+  output         io_out_tx_req_bits_snpAttr,
+  output [7:0]   io_out_tx_req_bits_lpIDWithPadding,
+  output         io_out_tx_req_bits_snoopMe,
+  output         io_out_tx_req_bits_expCompAck,
+  output [1:0]   io_out_tx_req_bits_tagOp,
+  output         io_out_tx_req_bits_traceTag,
+  output         io_out_tx_req_bits_mpam_perfMonGroup,
+  output [8:0]   io_out_tx_req_bits_mpam_partID,
+  output         io_out_tx_req_bits_mpam_mpamNS,
+  output [3:0]   io_out_tx_req_bits_rsvdc,
+  input          io_out_tx_rsp_ready,
+  output         io_out_tx_rsp_valid,
+  output [3:0]   io_out_tx_rsp_bits_qos,
+  output [10:0]  io_out_tx_rsp_bits_tgtID,
+  output [10:0]  io_out_tx_rsp_bits_srcID,
+  output [11:0]  io_out_tx_rsp_bits_txnID,
+  output [4:0]   io_out_tx_rsp_bits_opcode,
+  output [1:0]   io_out_tx_rsp_bits_respErr,
+  output [2:0]   io_out_tx_rsp_bits_resp,
+  output [2:0]   io_out_tx_rsp_bits_fwdState,
+  output [2:0]   io_out_tx_rsp_bits_cBusy,
+  output [11:0]  io_out_tx_rsp_bits_dbID,
+  output [3:0]   io_out_tx_rsp_bits_pCrdType,
+  output [1:0]   io_out_tx_rsp_bits_tagOp,
+  output         io_out_tx_rsp_bits_traceTag,
+  input          io_out_tx_dat_ready,
+  output         io_out_tx_dat_valid,
+  output [10:0]  io_out_tx_dat_bits_tgtID,
+  output [10:0]  io_out_tx_dat_bits_srcID,
+  output [11:0]  io_out_tx_dat_bits_txnID,
+  output [10:0]  io_out_tx_dat_bits_homeNID,
+  output [3:0]   io_out_tx_dat_bits_opcode,
+  output [1:0]   io_out_tx_dat_bits_respErr,
+  output [2:0]   io_out_tx_dat_bits_resp,
+  output [3:0]   io_out_tx_dat_bits_dataSource,
+  output [11:0]  io_out_tx_dat_bits_dbID,
+  output [1:0]   io_out_tx_dat_bits_ccID,
+  output [1:0]   io_out_tx_dat_bits_dataID,
+  output         io_out_tx_dat_bits_traceTag,
+  output [31:0]  io_out_tx_dat_bits_be,
+  output [255:0] io_out_tx_dat_bits_data,
+  output [31:0]  io_out_tx_dat_bits_dataCheck,
+  output [3:0]   io_out_tx_dat_bits_poison,
+  input          io_out_rx_rsp_valid,
+  input  [10:0]  io_out_rx_rsp_bits_srcID,
+  input  [11:0]  io_out_rx_rsp_bits_txnID,
+  input  [4:0]   io_out_rx_rsp_bits_opcode,
+  input  [1:0]   io_out_rx_rsp_bits_respErr,
+  input  [2:0]   io_out_rx_rsp_bits_resp,
+  input  [11:0]  io_out_rx_rsp_bits_dbID,
+  input  [3:0]   io_out_rx_rsp_bits_pCrdType,
+  input          io_out_rx_rsp_bits_traceTag,
+  input          io_out_rx_dat_valid,
+  input  [11:0]  io_out_rx_dat_bits_txnID,
+  input  [10:0]  io_out_rx_dat_bits_homeNID,
+  input  [3:0]   io_out_rx_dat_bits_opcode,
+  input  [1:0]   io_out_rx_dat_bits_respErr,
+  input  [2:0]   io_out_rx_dat_bits_resp,
+  input  [11:0]  io_out_rx_dat_bits_dbID,
+  input  [1:0]   io_out_rx_dat_bits_dataID,
+  input          io_out_rx_dat_bits_traceTag,
+  input  [255:0] io_out_rx_dat_bits_data,
+  input  [31:0]  io_out_rx_dat_bits_dataCheck,
+  input  [3:0]   io_out_rx_dat_bits_poison,
+  output         io_out_rx_snp_ready,
+  input          io_out_rx_snp_valid,
+  input  [3:0]   io_out_rx_snp_bits_qos,
+  input  [10:0]  io_out_rx_snp_bits_srcID,
+  input  [11:0]  io_out_rx_snp_bits_txnID,
+  input  [10:0]  io_out_rx_snp_bits_fwdNID,
+  input  [11:0]  io_out_rx_snp_bits_fwdTxnID,
+  input  [4:0]   io_out_rx_snp_bits_opcode,
+  input  [44:0]  io_out_rx_snp_bits_addr,
+  input          io_out_rx_snp_bits_ns,
+  input          io_out_rx_snp_bits_doNotGoToSD,
+  input          io_out_rx_snp_bits_retToSrc,
+  input          io_out_rx_snp_bits_traceTag,
+  input          io_out_rx_snp_bits_mpam_perfMonGroup,
+  input  [8:0]   io_out_rx_snp_bits_mpam_partID,
+  input          io_out_rx_snp_bits_mpam_mpamNS,
+  output         io_pCrd_0_query_valid,
+  output [3:0]   io_pCrd_0_query_bits_pCrdType,
+  output [10:0]  io_pCrd_0_query_bits_srcID,
+  input          io_pCrd_0_grant,
+  output         io_pCrd_1_query_valid,
+  output [3:0]   io_pCrd_1_query_bits_pCrdType,
+  output [10:0]  io_pCrd_1_query_bits_srcID,
+  input          io_pCrd_1_grant,
+  output         io_pCrd_2_query_valid,
+  output [3:0]   io_pCrd_2_query_bits_pCrdType,
+  output [10:0]  io_pCrd_2_query_bits_srcID,
+  input          io_pCrd_2_grant,
+  output         io_pCrd_3_query_valid,
+  output [3:0]   io_pCrd_3_query_bits_pCrdType,
+  output [10:0]  io_pCrd_3_query_bits_srcID,
+  input          io_pCrd_3_grant,
+  output         io_pCrd_4_query_valid,
+  output [3:0]   io_pCrd_4_query_bits_pCrdType,
+  output [10:0]  io_pCrd_4_query_bits_srcID,
+  input          io_pCrd_4_grant,
+  output         io_pCrd_5_query_valid,
+  output [3:0]   io_pCrd_5_query_bits_pCrdType,
+  output [10:0]  io_pCrd_5_query_bits_srcID,
+  input          io_pCrd_5_grant,
+  output         io_pCrd_6_query_valid,
+  output [3:0]   io_pCrd_6_query_bits_pCrdType,
+  output [10:0]  io_pCrd_6_query_bits_srcID,
+  input          io_pCrd_6_grant,
+  output         io_pCrd_7_query_valid,
+  output [3:0]   io_pCrd_7_query_bits_pCrdType,
+  output [10:0]  io_pCrd_7_query_bits_srcID,
+  input          io_pCrd_7_grant,
+  output         io_pCrd_8_query_valid,
+  output [3:0]   io_pCrd_8_query_bits_pCrdType,
+  output [10:0]  io_pCrd_8_query_bits_srcID,
+  input          io_pCrd_8_grant,
+  output         io_pCrd_9_query_valid,
+  output [3:0]   io_pCrd_9_query_bits_pCrdType,
+  output [10:0]  io_pCrd_9_query_bits_srcID,
+  input          io_pCrd_9_grant,
+  output         io_pCrd_10_query_valid,
+  output [3:0]   io_pCrd_10_query_bits_pCrdType,
+  output [10:0]  io_pCrd_10_query_bits_srcID,
+  input          io_pCrd_10_grant,
+  output         io_pCrd_11_query_valid,
+  output [3:0]   io_pCrd_11_query_bits_pCrdType,
+  output [10:0]  io_pCrd_11_query_bits_srcID,
+  input          io_pCrd_11_grant,
+  output         io_pCrd_12_query_valid,
+  output [3:0]   io_pCrd_12_query_bits_pCrdType,
+  output [10:0]  io_pCrd_12_query_bits_srcID,
+  input          io_pCrd_12_grant,
+  output         io_pCrd_13_query_valid,
+  output [3:0]   io_pCrd_13_query_bits_pCrdType,
+  output [10:0]  io_pCrd_13_query_bits_srcID,
+  input          io_pCrd_13_grant,
+  output         io_pCrd_14_query_valid,
+  output [3:0]   io_pCrd_14_query_bits_pCrdType,
+  output [10:0]  io_pCrd_14_query_bits_srcID,
+  input          io_pCrd_14_grant,
+  output         io_pCrd_15_query_valid,
+  output [3:0]   io_pCrd_15_query_bits_pCrdType,
+  output [10:0]  io_pCrd_15_query_bits_srcID,
+  input          io_pCrd_15_grant,
+  output [5:0]   io_perf_0_value,
+  output [5:0]   io_perf_1_value,
+  output [5:0]   io_perf_3_value,
+  output [5:0]   io_perf_4_value,
+  output [5:0]   io_perf_5_value,
+  output [5:0]   io_perf_6_value,
+  output [5:0]   io_perf_7_value,
+  output [5:0]   io_perf_8_value,
+  output [5:0]   io_perf_9_value,
+  output [5:0]   io_perf_10_value,
+  output [5:0]   io_perf_11_value,
+  output [5:0]   io_perf_12_value,
+  output [5:0]   io_perf_13_value,
+  output [5:0]   io_perf_14_value,
+  output [5:0]   io_perf_15_value,
+  output [5:0]   io_perf_16_value,
+  input          sigFromSrams_bore_ram_hold,
+  input          sigFromSrams_bore_ram_bypass,
+  input          sigFromSrams_bore_ram_bp_clken,
+  input          sigFromSrams_bore_ram_aux_clk,
+  input          sigFromSrams_bore_ram_aux_ckbp,
+  input          sigFromSrams_bore_ram_mcp_hold,
+  input          sigFromSrams_bore_cgen,
+  input          sigFromSrams_bore_1_ram_hold,
+  input          sigFromSrams_bore_1_ram_bypass,
+  input          sigFromSrams_bore_1_ram_bp_clken,
+  input          sigFromSrams_bore_1_ram_aux_clk,
+  input          sigFromSrams_bore_1_ram_aux_ckbp,
+  input          sigFromSrams_bore_1_ram_mcp_hold,
+  input          sigFromSrams_bore_1_cgen,
+  input          sigFromSrams_bore_2_ram_hold,
+  input          sigFromSrams_bore_2_ram_bypass,
+  input          sigFromSrams_bore_2_ram_bp_clken,
+  input          sigFromSrams_bore_2_ram_aux_clk,
+  input          sigFromSrams_bore_2_ram_aux_ckbp,
+  input          sigFromSrams_bore_2_ram_mcp_hold,
+  input          sigFromSrams_bore_2_cgen,
+  input          sigFromSrams_bore_3_ram_hold,
+  input          sigFromSrams_bore_3_ram_bypass,
+  input          sigFromSrams_bore_3_ram_bp_clken,
+  input          sigFromSrams_bore_3_ram_aux_clk,
+  input          sigFromSrams_bore_3_ram_aux_ckbp,
+  input          sigFromSrams_bore_3_ram_mcp_hold,
+  input          sigFromSrams_bore_3_cgen,
+  input          sigFromSrams_bore_4_ram_hold,
+  input          sigFromSrams_bore_4_ram_bypass,
+  input          sigFromSrams_bore_4_ram_bp_clken,
+  input          sigFromSrams_bore_4_ram_aux_clk,
+  input          sigFromSrams_bore_4_ram_aux_ckbp,
+  input          sigFromSrams_bore_4_ram_mcp_hold,
+  input          sigFromSrams_bore_4_cgen,
+  input          sigFromSrams_bore_5_ram_hold,
+  input          sigFromSrams_bore_5_ram_bypass,
+  input          sigFromSrams_bore_5_ram_bp_clken,
+  input          sigFromSrams_bore_5_ram_aux_clk,
+  input          sigFromSrams_bore_5_ram_aux_ckbp,
+  input          sigFromSrams_bore_5_ram_mcp_hold,
+  input          sigFromSrams_bore_5_cgen,
+  input          sigFromSrams_bore_6_ram_hold,
+  input          sigFromSrams_bore_6_ram_bypass,
+  input          sigFromSrams_bore_6_ram_bp_clken,
+  input          sigFromSrams_bore_6_ram_aux_clk,
+  input          sigFromSrams_bore_6_ram_aux_ckbp,
+  input          sigFromSrams_bore_6_ram_mcp_hold,
+  input          sigFromSrams_bore_6_cgen,
+  input          sigFromSrams_bore_7_ram_hold,
+  input          sigFromSrams_bore_7_ram_bypass,
+  input          sigFromSrams_bore_7_ram_bp_clken,
+  input          sigFromSrams_bore_7_ram_aux_clk,
+  input          sigFromSrams_bore_7_ram_aux_ckbp,
+  input          sigFromSrams_bore_7_ram_mcp_hold,
+  input          sigFromSrams_bore_7_cgen,
+  input          sigFromSrams_bore_8_ram_hold,
+  input          sigFromSrams_bore_8_ram_bypass,
+  input          sigFromSrams_bore_8_ram_bp_clken,
+  input          sigFromSrams_bore_8_ram_aux_clk,
+  input          sigFromSrams_bore_8_ram_aux_ckbp,
+  input          sigFromSrams_bore_8_ram_mcp_hold,
+  input          sigFromSrams_bore_8_cgen,
+  input  [3:0]   boreChildrenBd_bore_array,
+  input          boreChildrenBd_bore_all,
+  input          boreChildrenBd_bore_req,
+  output         boreChildrenBd_bore_ack,
+  input          boreChildrenBd_bore_writeen,
+  input  [7:0]   boreChildrenBd_bore_be,
+  input  [11:0]  boreChildrenBd_bore_addr,
+  input  [163:0] boreChildrenBd_bore_indata,
+  input          boreChildrenBd_bore_readen,
+  input  [11:0]  boreChildrenBd_bore_addr_rd,
+  output [163:0] boreChildrenBd_bore_outdata
+);
+
+  wire [163:0] bd_outdata;
+  wire         bd_ack;
+  wire [136:0] childBd_1_outdata;
+  wire         childBd_1_ack;
+  wire [163:0] childBd_outdata;
+  wire         childBd_ack;
+  wire         _mshrCtl_io_toReqArb_blockA_s1;
+  wire         _mshrCtl_io_toReqArb_blockB_s1;
+  wire [7:0]   _mshrCtl_io_toMainPipe_mshr_alloc_ptr;
+  wire         _mshrCtl_io_mshrTask_valid;
+  wire [2:0]   _mshrCtl_io_mshrTask_bits_channel;
+  wire [2:0]   _mshrCtl_io_mshrTask_bits_txChannel;
+  wire [7:0]   _mshrCtl_io_mshrTask_bits_set;
+  wire [33:0]  _mshrCtl_io_mshrTask_bits_tag;
+  wire [5:0]   _mshrCtl_io_mshrTask_bits_off;
+  wire         _mshrCtl_io_mshrTask_bits_alias;
+  wire         _mshrCtl_io_mshrTask_bits_isKeyword;
+  wire [3:0]   _mshrCtl_io_mshrTask_bits_opcode;
+  wire [2:0]   _mshrCtl_io_mshrTask_bits_param;
+  wire [2:0]   _mshrCtl_io_mshrTask_bits_size;
+  wire [6:0]   _mshrCtl_io_mshrTask_bits_sourceId;
+  wire         _mshrCtl_io_mshrTask_bits_denied;
+  wire         _mshrCtl_io_mshrTask_bits_corrupt;
+  wire         _mshrCtl_io_mshrTask_bits_mshrTask;
+  wire [7:0]   _mshrCtl_io_mshrTask_bits_mshrId;
+  wire         _mshrCtl_io_mshrTask_bits_aliasTask;
+  wire         _mshrCtl_io_mshrTask_bits_useProbeData;
+  wire         _mshrCtl_io_mshrTask_bits_mshrRetry;
+  wire         _mshrCtl_io_mshrTask_bits_readProbeDataDown;
+  wire         _mshrCtl_io_mshrTask_bits_fromL2pft;
+  wire         _mshrCtl_io_mshrTask_bits_dirty;
+  wire [2:0]   _mshrCtl_io_mshrTask_bits_way;
+  wire         _mshrCtl_io_mshrTask_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_mshrTask_bits_meta_state;
+  wire         _mshrCtl_io_mshrTask_bits_meta_clients;
+  wire         _mshrCtl_io_mshrTask_bits_meta_alias;
+  wire         _mshrCtl_io_mshrTask_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_mshrTask_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_mshrTask_bits_meta_accessed;
+  wire         _mshrCtl_io_mshrTask_bits_meta_tagErr;
+  wire         _mshrCtl_io_mshrTask_bits_meta_dataErr;
+  wire         _mshrCtl_io_mshrTask_bits_metaWen;
+  wire         _mshrCtl_io_mshrTask_bits_tagWen;
+  wire         _mshrCtl_io_mshrTask_bits_dsWen;
+  wire         _mshrCtl_io_mshrTask_bits_replTask;
+  wire         _mshrCtl_io_mshrTask_bits_cmoTask;
+  wire [4:0]   _mshrCtl_io_mshrTask_bits_reqSource;
+  wire         _mshrCtl_io_mshrTask_bits_mergeA;
+  wire [5:0]   _mshrCtl_io_mshrTask_bits_aMergeTask_off;
+  wire         _mshrCtl_io_mshrTask_bits_aMergeTask_alias;
+  wire [43:0]  _mshrCtl_io_mshrTask_bits_aMergeTask_vaddr;
+  wire         _mshrCtl_io_mshrTask_bits_aMergeTask_isKeyword;
+  wire [2:0]   _mshrCtl_io_mshrTask_bits_aMergeTask_opcode;
+  wire [2:0]   _mshrCtl_io_mshrTask_bits_aMergeTask_param;
+  wire [6:0]   _mshrCtl_io_mshrTask_bits_aMergeTask_sourceId;
+  wire         _mshrCtl_io_mshrTask_bits_aMergeTask_meta_dirty;
+  wire [1:0]   _mshrCtl_io_mshrTask_bits_aMergeTask_meta_state;
+  wire         _mshrCtl_io_mshrTask_bits_aMergeTask_meta_clients;
+  wire         _mshrCtl_io_mshrTask_bits_aMergeTask_meta_alias;
+  wire         _mshrCtl_io_mshrTask_bits_aMergeTask_meta_accessed;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitRelease;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseToInval;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseToClean;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseWithData;
+  wire [7:0]   _mshrCtl_io_mshrTask_bits_snpHitReleaseIdx;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]   _mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_state;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_clients;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_alias;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]   _mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_prefetchSrc;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_accessed;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_tagErr;
+  wire         _mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0]  _mshrCtl_io_mshrTask_bits_tgtID;
+  wire [11:0]  _mshrCtl_io_mshrTask_bits_txnID;
+  wire [10:0]  _mshrCtl_io_mshrTask_bits_homeNID;
+  wire [11:0]  _mshrCtl_io_mshrTask_bits_dbID;
+  wire [6:0]   _mshrCtl_io_mshrTask_bits_chiOpcode;
+  wire [2:0]   _mshrCtl_io_mshrTask_bits_resp;
+  wire [2:0]   _mshrCtl_io_mshrTask_bits_fwdState;
+  wire         _mshrCtl_io_mshrTask_bits_retToSrc;
+  wire         _mshrCtl_io_mshrTask_bits_likelyshared;
+  wire         _mshrCtl_io_mshrTask_bits_expCompAck;
+  wire         _mshrCtl_io_mshrTask_bits_allowRetry;
+  wire         _mshrCtl_io_mshrTask_bits_memAttr_allocate;
+  wire         _mshrCtl_io_mshrTask_bits_memAttr_cacheable;
+  wire         _mshrCtl_io_mshrTask_bits_memAttr_ewa;
+  wire         _mshrCtl_io_mshrTask_bits_traceTag;
+  wire         _mshrCtl_io_toTXREQ_valid;
+  wire [3:0]   _mshrCtl_io_toTXREQ_bits_qos;
+  wire [10:0]  _mshrCtl_io_toTXREQ_bits_tgtID;
+  wire [11:0]  _mshrCtl_io_toTXREQ_bits_txnID;
+  wire [6:0]   _mshrCtl_io_toTXREQ_bits_opcode;
+  wire [2:0]   _mshrCtl_io_toTXREQ_bits_size;
+  wire [47:0]  _mshrCtl_io_toTXREQ_bits_addr;
+  wire         _mshrCtl_io_toTXREQ_bits_likelyshared;
+  wire         _mshrCtl_io_toTXREQ_bits_allowRetry;
+  wire [1:0]   _mshrCtl_io_toTXREQ_bits_order;
+  wire [3:0]   _mshrCtl_io_toTXREQ_bits_pCrdType;
+  wire         _mshrCtl_io_toTXREQ_bits_memAttr_allocate;
+  wire         _mshrCtl_io_toTXREQ_bits_memAttr_cacheable;
+  wire         _mshrCtl_io_toTXREQ_bits_memAttr_device;
+  wire         _mshrCtl_io_toTXREQ_bits_memAttr_ewa;
+  wire         _mshrCtl_io_toTXREQ_bits_snpAttr;
+  wire         _mshrCtl_io_toTXREQ_bits_expCompAck;
+  wire         _mshrCtl_io_toTXRSP_valid;
+  wire [10:0]  _mshrCtl_io_toTXRSP_bits_tgtID;
+  wire [11:0]  _mshrCtl_io_toTXRSP_bits_txnID;
+  wire [4:0]   _mshrCtl_io_toTXRSP_bits_opcode;
+  wire         _mshrCtl_io_toTXRSP_bits_traceTag;
+  wire [7:0]   _mshrCtl_io_releaseBufWriteId;
+  wire         _mshrCtl_io_nestedwbDataId_valid;
+  wire [7:0]   _mshrCtl_io_nestedwbDataId_bits;
+  wire         _mshrCtl_io_msInfo_0_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_0_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_0_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_0_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_0_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_0_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_0_bits_willFree;
+  wire         _mshrCtl_io_msInfo_0_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_0_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_0_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_0_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_0_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_0_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_0_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_0_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_0_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_0_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_0_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_0_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_0_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_0_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_0_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_0_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_0_bits_param;
+  wire         _mshrCtl_io_msInfo_0_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_0_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_0_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_0_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_0_bits_s_release;
+  wire         _mshrCtl_io_msInfo_0_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_0_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_0_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_0_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_0_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_0_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_0_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_0_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_1_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_1_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_1_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_1_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_1_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_1_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_1_bits_willFree;
+  wire         _mshrCtl_io_msInfo_1_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_1_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_1_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_1_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_1_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_1_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_1_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_1_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_1_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_1_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_1_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_1_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_1_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_1_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_1_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_1_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_1_bits_param;
+  wire         _mshrCtl_io_msInfo_1_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_1_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_1_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_1_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_1_bits_s_release;
+  wire         _mshrCtl_io_msInfo_1_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_1_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_1_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_1_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_1_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_1_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_1_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_1_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_2_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_2_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_2_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_2_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_2_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_2_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_2_bits_willFree;
+  wire         _mshrCtl_io_msInfo_2_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_2_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_2_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_2_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_2_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_2_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_2_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_2_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_2_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_2_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_2_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_2_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_2_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_2_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_2_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_2_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_2_bits_param;
+  wire         _mshrCtl_io_msInfo_2_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_2_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_2_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_2_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_2_bits_s_release;
+  wire         _mshrCtl_io_msInfo_2_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_2_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_2_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_2_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_2_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_2_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_2_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_2_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_3_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_3_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_3_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_3_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_3_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_3_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_3_bits_willFree;
+  wire         _mshrCtl_io_msInfo_3_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_3_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_3_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_3_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_3_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_3_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_3_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_3_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_3_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_3_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_3_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_3_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_3_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_3_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_3_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_3_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_3_bits_param;
+  wire         _mshrCtl_io_msInfo_3_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_3_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_3_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_3_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_3_bits_s_release;
+  wire         _mshrCtl_io_msInfo_3_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_3_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_3_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_3_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_3_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_3_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_3_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_3_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_4_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_4_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_4_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_4_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_4_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_4_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_4_bits_willFree;
+  wire         _mshrCtl_io_msInfo_4_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_4_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_4_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_4_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_4_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_4_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_4_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_4_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_4_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_4_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_4_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_4_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_4_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_4_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_4_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_4_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_4_bits_param;
+  wire         _mshrCtl_io_msInfo_4_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_4_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_4_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_4_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_4_bits_s_release;
+  wire         _mshrCtl_io_msInfo_4_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_4_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_4_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_4_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_4_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_4_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_4_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_4_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_5_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_5_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_5_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_5_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_5_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_5_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_5_bits_willFree;
+  wire         _mshrCtl_io_msInfo_5_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_5_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_5_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_5_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_5_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_5_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_5_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_5_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_5_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_5_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_5_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_5_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_5_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_5_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_5_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_5_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_5_bits_param;
+  wire         _mshrCtl_io_msInfo_5_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_5_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_5_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_5_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_5_bits_s_release;
+  wire         _mshrCtl_io_msInfo_5_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_5_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_5_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_5_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_5_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_5_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_5_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_5_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_6_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_6_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_6_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_6_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_6_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_6_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_6_bits_willFree;
+  wire         _mshrCtl_io_msInfo_6_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_6_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_6_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_6_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_6_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_6_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_6_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_6_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_6_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_6_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_6_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_6_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_6_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_6_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_6_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_6_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_6_bits_param;
+  wire         _mshrCtl_io_msInfo_6_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_6_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_6_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_6_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_6_bits_s_release;
+  wire         _mshrCtl_io_msInfo_6_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_6_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_6_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_6_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_6_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_6_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_6_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_6_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_7_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_7_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_7_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_7_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_7_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_7_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_7_bits_willFree;
+  wire         _mshrCtl_io_msInfo_7_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_7_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_7_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_7_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_7_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_7_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_7_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_7_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_7_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_7_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_7_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_7_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_7_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_7_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_7_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_7_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_7_bits_param;
+  wire         _mshrCtl_io_msInfo_7_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_7_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_7_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_7_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_7_bits_s_release;
+  wire         _mshrCtl_io_msInfo_7_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_7_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_7_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_7_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_7_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_7_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_7_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_7_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_8_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_8_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_8_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_8_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_8_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_8_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_8_bits_willFree;
+  wire         _mshrCtl_io_msInfo_8_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_8_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_8_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_8_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_8_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_8_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_8_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_8_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_8_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_8_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_8_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_8_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_8_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_8_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_8_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_8_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_8_bits_param;
+  wire         _mshrCtl_io_msInfo_8_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_8_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_8_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_8_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_8_bits_s_release;
+  wire         _mshrCtl_io_msInfo_8_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_8_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_8_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_8_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_8_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_8_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_8_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_8_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_9_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_9_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_9_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_9_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_9_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_9_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_9_bits_willFree;
+  wire         _mshrCtl_io_msInfo_9_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_9_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_9_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_9_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_9_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_9_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_9_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_9_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_9_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_9_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_9_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_9_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_9_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_9_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_9_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_9_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_9_bits_param;
+  wire         _mshrCtl_io_msInfo_9_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_9_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_9_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_9_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_9_bits_s_release;
+  wire         _mshrCtl_io_msInfo_9_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_9_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_9_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_9_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_9_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_9_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_9_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_9_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_10_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_10_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_10_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_10_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_10_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_10_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_10_bits_willFree;
+  wire         _mshrCtl_io_msInfo_10_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_10_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_10_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_10_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_10_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_10_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_10_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_10_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_10_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_10_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_10_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_10_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_10_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_10_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_10_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_10_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_10_bits_param;
+  wire         _mshrCtl_io_msInfo_10_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_10_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_10_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_10_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_10_bits_s_release;
+  wire         _mshrCtl_io_msInfo_10_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_10_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_10_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_10_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_10_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_10_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_10_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_10_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_11_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_11_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_11_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_11_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_11_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_11_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_11_bits_willFree;
+  wire         _mshrCtl_io_msInfo_11_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_11_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_11_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_11_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_11_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_11_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_11_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_11_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_11_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_11_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_11_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_11_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_11_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_11_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_11_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_11_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_11_bits_param;
+  wire         _mshrCtl_io_msInfo_11_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_11_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_11_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_11_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_11_bits_s_release;
+  wire         _mshrCtl_io_msInfo_11_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_11_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_11_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_11_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_11_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_11_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_11_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_11_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_12_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_12_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_12_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_12_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_12_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_12_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_12_bits_willFree;
+  wire         _mshrCtl_io_msInfo_12_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_12_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_12_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_12_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_12_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_12_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_12_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_12_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_12_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_12_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_12_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_12_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_12_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_12_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_12_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_12_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_12_bits_param;
+  wire         _mshrCtl_io_msInfo_12_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_12_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_12_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_12_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_12_bits_s_release;
+  wire         _mshrCtl_io_msInfo_12_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_12_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_12_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_12_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_12_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_12_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_12_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_12_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_13_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_13_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_13_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_13_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_13_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_13_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_13_bits_willFree;
+  wire         _mshrCtl_io_msInfo_13_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_13_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_13_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_13_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_13_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_13_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_13_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_13_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_13_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_13_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_13_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_13_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_13_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_13_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_13_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_13_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_13_bits_param;
+  wire         _mshrCtl_io_msInfo_13_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_13_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_13_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_13_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_13_bits_s_release;
+  wire         _mshrCtl_io_msInfo_13_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_13_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_13_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_13_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_13_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_13_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_13_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_13_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_14_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_14_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_14_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_14_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_14_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_14_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_14_bits_willFree;
+  wire         _mshrCtl_io_msInfo_14_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_14_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_14_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_14_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_14_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_14_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_14_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_14_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_14_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_14_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_14_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_14_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_14_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_14_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_14_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_14_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_14_bits_param;
+  wire         _mshrCtl_io_msInfo_14_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_14_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_14_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_14_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_14_bits_s_release;
+  wire         _mshrCtl_io_msInfo_14_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_14_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_14_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_14_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_14_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_14_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_14_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_14_bits_releaseToClean;
+  wire         _mshrCtl_io_msInfo_15_valid;
+  wire [2:0]   _mshrCtl_io_msInfo_15_bits_channel;
+  wire [7:0]   _mshrCtl_io_msInfo_15_bits_set;
+  wire [2:0]   _mshrCtl_io_msInfo_15_bits_way;
+  wire [33:0]  _mshrCtl_io_msInfo_15_bits_reqTag;
+  wire [4:0]   _mshrCtl_io_msInfo_15_bits_reqSource;
+  wire         _mshrCtl_io_msInfo_15_bits_willFree;
+  wire         _mshrCtl_io_msInfo_15_bits_aliasTask;
+  wire         _mshrCtl_io_msInfo_15_bits_needRelease;
+  wire         _mshrCtl_io_msInfo_15_bits_blockRefill;
+  wire         _mshrCtl_io_msInfo_15_bits_meta_dirty;
+  wire [1:0]   _mshrCtl_io_msInfo_15_bits_meta_state;
+  wire         _mshrCtl_io_msInfo_15_bits_meta_clients;
+  wire         _mshrCtl_io_msInfo_15_bits_meta_alias;
+  wire         _mshrCtl_io_msInfo_15_bits_meta_prefetch;
+  wire [3:0]   _mshrCtl_io_msInfo_15_bits_meta_prefetchSrc;
+  wire         _mshrCtl_io_msInfo_15_bits_meta_accessed;
+  wire         _mshrCtl_io_msInfo_15_bits_meta_tagErr;
+  wire         _mshrCtl_io_msInfo_15_bits_meta_dataErr;
+  wire [33:0]  _mshrCtl_io_msInfo_15_bits_metaTag;
+  wire         _mshrCtl_io_msInfo_15_bits_dirHit;
+  wire         _mshrCtl_io_msInfo_15_bits_isAcqOrPrefetch;
+  wire         _mshrCtl_io_msInfo_15_bits_isPrefetch;
+  wire [2:0]   _mshrCtl_io_msInfo_15_bits_param;
+  wire         _mshrCtl_io_msInfo_15_bits_mergeA;
+  wire         _mshrCtl_io_msInfo_15_bits_w_grantfirst;
+  wire         _mshrCtl_io_msInfo_15_bits_w_grantlast;
+  wire         _mshrCtl_io_msInfo_15_bits_w_grant;
+  wire         _mshrCtl_io_msInfo_15_bits_s_release;
+  wire         _mshrCtl_io_msInfo_15_bits_s_refill;
+  wire         _mshrCtl_io_msInfo_15_bits_s_cmoresp;
+  wire         _mshrCtl_io_msInfo_15_bits_s_cmometaw;
+  wire         _mshrCtl_io_msInfo_15_bits_w_releaseack;
+  wire         _mshrCtl_io_msInfo_15_bits_w_replResp;
+  wire         _mshrCtl_io_msInfo_15_bits_w_rprobeacklast;
+  wire         _mshrCtl_io_msInfo_15_bits_replaceData;
+  wire         _mshrCtl_io_msInfo_15_bits_releaseToClean;
+  wire [5:0]   _mshrCtl_io_perf_0_value;
+  wire [5:0]   _mshrCtl_io_perf_1_value;
+  wire [5:0]   _mshrCtl_io_perf_3_value;
+  wire         _reqBuf_io_in_ready;
+  wire         _reqBuf_io_out_valid;
+  wire [2:0]   _reqBuf_io_out_bits_channel;
+  wire [2:0]   _reqBuf_io_out_bits_txChannel;
+  wire [7:0]   _reqBuf_io_out_bits_set;
+  wire [33:0]  _reqBuf_io_out_bits_tag;
+  wire [5:0]   _reqBuf_io_out_bits_off;
+  wire         _reqBuf_io_out_bits_alias;
+  wire [43:0]  _reqBuf_io_out_bits_vaddr;
+  wire         _reqBuf_io_out_bits_isKeyword;
+  wire [3:0]   _reqBuf_io_out_bits_opcode;
+  wire [2:0]   _reqBuf_io_out_bits_param;
+  wire [2:0]   _reqBuf_io_out_bits_size;
+  wire [6:0]   _reqBuf_io_out_bits_sourceId;
+  wire [1:0]   _reqBuf_io_out_bits_bufIdx;
+  wire         _reqBuf_io_out_bits_needProbeAckData;
+  wire         _reqBuf_io_out_bits_denied;
+  wire         _reqBuf_io_out_bits_corrupt;
+  wire         _reqBuf_io_out_bits_mshrTask;
+  wire [7:0]   _reqBuf_io_out_bits_mshrId;
+  wire         _reqBuf_io_out_bits_aliasTask;
+  wire         _reqBuf_io_out_bits_useProbeData;
+  wire         _reqBuf_io_out_bits_mshrRetry;
+  wire         _reqBuf_io_out_bits_readProbeDataDown;
+  wire         _reqBuf_io_out_bits_fromL2pft;
+  wire         _reqBuf_io_out_bits_needHint;
+  wire         _reqBuf_io_out_bits_dirty;
+  wire [2:0]   _reqBuf_io_out_bits_way;
+  wire         _reqBuf_io_out_bits_meta_dirty;
+  wire [1:0]   _reqBuf_io_out_bits_meta_state;
+  wire         _reqBuf_io_out_bits_meta_clients;
+  wire         _reqBuf_io_out_bits_meta_alias;
+  wire         _reqBuf_io_out_bits_meta_prefetch;
+  wire [3:0]   _reqBuf_io_out_bits_meta_prefetchSrc;
+  wire         _reqBuf_io_out_bits_meta_accessed;
+  wire         _reqBuf_io_out_bits_meta_tagErr;
+  wire         _reqBuf_io_out_bits_meta_dataErr;
+  wire         _reqBuf_io_out_bits_metaWen;
+  wire         _reqBuf_io_out_bits_tagWen;
+  wire         _reqBuf_io_out_bits_dsWen;
+  wire         _reqBuf_io_out_bits_replTask;
+  wire         _reqBuf_io_out_bits_cmoTask;
+  wire         _reqBuf_io_out_bits_cmoAll;
+  wire [4:0]   _reqBuf_io_out_bits_reqSource;
+  wire         _reqBuf_io_out_bits_mergeA;
+  wire [5:0]   _reqBuf_io_out_bits_aMergeTask_off;
+  wire         _reqBuf_io_out_bits_aMergeTask_alias;
+  wire [43:0]  _reqBuf_io_out_bits_aMergeTask_vaddr;
+  wire         _reqBuf_io_out_bits_aMergeTask_isKeyword;
+  wire [2:0]   _reqBuf_io_out_bits_aMergeTask_opcode;
+  wire [2:0]   _reqBuf_io_out_bits_aMergeTask_param;
+  wire [6:0]   _reqBuf_io_out_bits_aMergeTask_sourceId;
+  wire         _reqBuf_io_out_bits_aMergeTask_meta_dirty;
+  wire [1:0]   _reqBuf_io_out_bits_aMergeTask_meta_state;
+  wire         _reqBuf_io_out_bits_aMergeTask_meta_clients;
+  wire         _reqBuf_io_out_bits_aMergeTask_meta_alias;
+  wire         _reqBuf_io_out_bits_aMergeTask_meta_prefetch;
+  wire [3:0]   _reqBuf_io_out_bits_aMergeTask_meta_prefetchSrc;
+  wire         _reqBuf_io_out_bits_aMergeTask_meta_accessed;
+  wire         _reqBuf_io_out_bits_aMergeTask_meta_tagErr;
+  wire         _reqBuf_io_out_bits_aMergeTask_meta_dataErr;
+  wire         _reqBuf_io_out_bits_snpHitRelease;
+  wire         _reqBuf_io_out_bits_snpHitReleaseToInval;
+  wire         _reqBuf_io_out_bits_snpHitReleaseToClean;
+  wire         _reqBuf_io_out_bits_snpHitReleaseWithData;
+  wire [7:0]   _reqBuf_io_out_bits_snpHitReleaseIdx;
+  wire         _reqBuf_io_out_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]   _reqBuf_io_out_bits_snpHitReleaseMeta_state;
+  wire         _reqBuf_io_out_bits_snpHitReleaseMeta_clients;
+  wire         _reqBuf_io_out_bits_snpHitReleaseMeta_alias;
+  wire         _reqBuf_io_out_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]   _reqBuf_io_out_bits_snpHitReleaseMeta_prefetchSrc;
+  wire         _reqBuf_io_out_bits_snpHitReleaseMeta_accessed;
+  wire         _reqBuf_io_out_bits_snpHitReleaseMeta_tagErr;
+  wire         _reqBuf_io_out_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0]  _reqBuf_io_out_bits_tgtID;
+  wire [10:0]  _reqBuf_io_out_bits_srcID;
+  wire [11:0]  _reqBuf_io_out_bits_txnID;
+  wire [10:0]  _reqBuf_io_out_bits_homeNID;
+  wire [11:0]  _reqBuf_io_out_bits_dbID;
+  wire [10:0]  _reqBuf_io_out_bits_fwdNID;
+  wire [11:0]  _reqBuf_io_out_bits_fwdTxnID;
+  wire [6:0]   _reqBuf_io_out_bits_chiOpcode;
+  wire [2:0]   _reqBuf_io_out_bits_resp;
+  wire [2:0]   _reqBuf_io_out_bits_fwdState;
+  wire [3:0]   _reqBuf_io_out_bits_pCrdType;
+  wire         _reqBuf_io_out_bits_retToSrc;
+  wire         _reqBuf_io_out_bits_likelyshared;
+  wire         _reqBuf_io_out_bits_expCompAck;
+  wire         _reqBuf_io_out_bits_allowRetry;
+  wire         _reqBuf_io_out_bits_memAttr_allocate;
+  wire         _reqBuf_io_out_bits_memAttr_cacheable;
+  wire         _reqBuf_io_out_bits_memAttr_device;
+  wire         _reqBuf_io_out_bits_memAttr_ewa;
+  wire         _reqBuf_io_out_bits_traceTag;
+  wire         _reqBuf_io_aMergeTask_valid;
+  wire [15:0]  _reqBuf_io_aMergeTask_bits_idOH;
+  wire [5:0]   _reqBuf_io_aMergeTask_bits_task_off;
+  wire         _reqBuf_io_aMergeTask_bits_task_alias;
+  wire [43:0]  _reqBuf_io_aMergeTask_bits_task_vaddr;
+  wire         _reqBuf_io_aMergeTask_bits_task_isKeyword;
+  wire [3:0]   _reqBuf_io_aMergeTask_bits_task_opcode;
+  wire [2:0]   _reqBuf_io_aMergeTask_bits_task_param;
+  wire [6:0]   _reqBuf_io_aMergeTask_bits_task_sourceId;
+  wire [33:0]  _reqBuf_io_ATag;
+  wire [7:0]   _reqBuf_io_ASet;
+  wire         _mainPipe_io_toReqArb_blockG_s1;
+  wire         _mainPipe_io_toReqArb_blockB_s1;
+  wire         _mainPipe_io_toReqArb_blockC_s1;
+  wire         _mainPipe_io_toReqBuf_0;
+  wire         _mainPipe_io_toReqBuf_1;
+  wire         _mainPipe_io_status_vec_toD_0_valid;
+  wire [2:0]   _mainPipe_io_status_vec_toD_0_bits_channel;
+  wire         _mainPipe_io_status_vec_toD_1_valid;
+  wire [2:0]   _mainPipe_io_status_vec_toD_1_bits_channel;
+  wire         _mainPipe_io_status_vec_toD_2_valid;
+  wire [2:0]   _mainPipe_io_status_vec_toD_2_bits_channel;
+  wire         _mainPipe_io_status_vec_toTX_0_valid;
+  wire [2:0]   _mainPipe_io_status_vec_toTX_0_bits_channel;
+  wire [2:0]   _mainPipe_io_status_vec_toTX_0_bits_txChannel;
+  wire         _mainPipe_io_status_vec_toTX_0_bits_mshrTask;
+  wire         _mainPipe_io_status_vec_toTX_1_valid;
+  wire [2:0]   _mainPipe_io_status_vec_toTX_1_bits_channel;
+  wire [2:0]   _mainPipe_io_status_vec_toTX_1_bits_txChannel;
+  wire         _mainPipe_io_status_vec_toTX_1_bits_mshrTask;
+  wire         _mainPipe_io_status_vec_toTX_2_valid;
+  wire [2:0]   _mainPipe_io_status_vec_toTX_2_bits_channel;
+  wire [2:0]   _mainPipe_io_status_vec_toTX_2_bits_txChannel;
+  wire         _mainPipe_io_status_vec_toTX_2_bits_mshrTask;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_valid;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_hit;
+  wire [33:0]  _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_tag;
+  wire [7:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_set;
+  wire [2:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_way;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dirty;
+  wire [1:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_state;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_clients;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_alias;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetch;
+  wire [3:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_accessed;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_tagErr;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dataErr;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_error;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_acquire;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rprobe;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_pprobe;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_release;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_probeack;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_refill;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_cmoresp;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeackfirst;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeacklast;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeackfirst;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeacklast;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantfirst;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantlast;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grant;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_releaseack;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_replResp;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rcompack;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_dct;
+  wire [2:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_channel;
+  wire [7:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_set;
+  wire [33:0]  _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_tag;
+  wire [5:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_off;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_alias;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_isKeyword;
+  wire [3:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_opcode;
+  wire [2:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_param;
+  wire [6:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_sourceId;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_aliasTask;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_fromL2pft;
+  wire [4:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_reqSource;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitRelease;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToInval;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToClean;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseWithData;
+  wire [7:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseIdx;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty;
+  wire [1:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch;
+  wire [3:0]
+    _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr;
+  wire [10:0]  _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_srcID;
+  wire [11:0]  _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_txnID;
+  wire [10:0]  _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdNID;
+  wire [11:0]  _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdTxnID;
+  wire [6:0]   _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_chiOpcode;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_retToSrc;
+  wire         _mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_traceTag;
+  wire         _mainPipe_io_toDS_en_s3;
+  wire         _mainPipe_io_toDS_req_s3_valid;
+  wire [2:0]   _mainPipe_io_toDS_req_s3_bits_way;
+  wire [7:0]   _mainPipe_io_toDS_req_s3_bits_set;
+  wire         _mainPipe_io_toDS_req_s3_bits_wen;
+  wire [511:0] _mainPipe_io_toDS_wdata_s3_data;
+  wire         _mainPipe_io_toSourceD_valid;
+  wire [2:0]   _mainPipe_io_toSourceD_bits_task_channel;
+  wire [2:0]   _mainPipe_io_toSourceD_bits_task_txChannel;
+  wire [7:0]   _mainPipe_io_toSourceD_bits_task_set;
+  wire [33:0]  _mainPipe_io_toSourceD_bits_task_tag;
+  wire [5:0]   _mainPipe_io_toSourceD_bits_task_off;
+  wire         _mainPipe_io_toSourceD_bits_task_alias;
+  wire [43:0]  _mainPipe_io_toSourceD_bits_task_vaddr;
+  wire         _mainPipe_io_toSourceD_bits_task_isKeyword;
+  wire [3:0]   _mainPipe_io_toSourceD_bits_task_opcode;
+  wire [2:0]   _mainPipe_io_toSourceD_bits_task_param;
+  wire [2:0]   _mainPipe_io_toSourceD_bits_task_size;
+  wire [6:0]   _mainPipe_io_toSourceD_bits_task_sourceId;
+  wire [1:0]   _mainPipe_io_toSourceD_bits_task_bufIdx;
+  wire         _mainPipe_io_toSourceD_bits_task_needProbeAckData;
+  wire         _mainPipe_io_toSourceD_bits_task_denied;
+  wire         _mainPipe_io_toSourceD_bits_task_corrupt;
+  wire         _mainPipe_io_toSourceD_bits_task_mshrTask;
+  wire [7:0]   _mainPipe_io_toSourceD_bits_task_mshrId;
+  wire         _mainPipe_io_toSourceD_bits_task_aliasTask;
+  wire         _mainPipe_io_toSourceD_bits_task_useProbeData;
+  wire         _mainPipe_io_toSourceD_bits_task_mshrRetry;
+  wire         _mainPipe_io_toSourceD_bits_task_readProbeDataDown;
+  wire         _mainPipe_io_toSourceD_bits_task_fromL2pft;
+  wire         _mainPipe_io_toSourceD_bits_task_needHint;
+  wire         _mainPipe_io_toSourceD_bits_task_dirty;
+  wire [2:0]   _mainPipe_io_toSourceD_bits_task_way;
+  wire         _mainPipe_io_toSourceD_bits_task_meta_dirty;
+  wire [1:0]   _mainPipe_io_toSourceD_bits_task_meta_state;
+  wire         _mainPipe_io_toSourceD_bits_task_meta_clients;
+  wire         _mainPipe_io_toSourceD_bits_task_meta_alias;
+  wire         _mainPipe_io_toSourceD_bits_task_meta_prefetch;
+  wire [3:0]   _mainPipe_io_toSourceD_bits_task_meta_prefetchSrc;
+  wire         _mainPipe_io_toSourceD_bits_task_meta_accessed;
+  wire         _mainPipe_io_toSourceD_bits_task_meta_tagErr;
+  wire         _mainPipe_io_toSourceD_bits_task_meta_dataErr;
+  wire         _mainPipe_io_toSourceD_bits_task_metaWen;
+  wire         _mainPipe_io_toSourceD_bits_task_tagWen;
+  wire         _mainPipe_io_toSourceD_bits_task_dsWen;
+  wire [7:0]   _mainPipe_io_toSourceD_bits_task_wayMask;
+  wire         _mainPipe_io_toSourceD_bits_task_replTask;
+  wire         _mainPipe_io_toSourceD_bits_task_cmoTask;
+  wire         _mainPipe_io_toSourceD_bits_task_cmoAll;
+  wire [4:0]   _mainPipe_io_toSourceD_bits_task_reqSource;
+  wire         _mainPipe_io_toSourceD_bits_task_mergeA;
+  wire [5:0]   _mainPipe_io_toSourceD_bits_task_aMergeTask_off;
+  wire         _mainPipe_io_toSourceD_bits_task_aMergeTask_alias;
+  wire [43:0]  _mainPipe_io_toSourceD_bits_task_aMergeTask_vaddr;
+  wire         _mainPipe_io_toSourceD_bits_task_aMergeTask_isKeyword;
+  wire [2:0]   _mainPipe_io_toSourceD_bits_task_aMergeTask_opcode;
+  wire [2:0]   _mainPipe_io_toSourceD_bits_task_aMergeTask_param;
+  wire [6:0]   _mainPipe_io_toSourceD_bits_task_aMergeTask_sourceId;
+  wire         _mainPipe_io_toSourceD_bits_task_aMergeTask_meta_dirty;
+  wire [1:0]   _mainPipe_io_toSourceD_bits_task_aMergeTask_meta_state;
+  wire         _mainPipe_io_toSourceD_bits_task_aMergeTask_meta_clients;
+  wire         _mainPipe_io_toSourceD_bits_task_aMergeTask_meta_alias;
+  wire         _mainPipe_io_toSourceD_bits_task_aMergeTask_meta_prefetch;
+  wire [3:0]   _mainPipe_io_toSourceD_bits_task_aMergeTask_meta_prefetchSrc;
+  wire         _mainPipe_io_toSourceD_bits_task_aMergeTask_meta_accessed;
+  wire         _mainPipe_io_toSourceD_bits_task_aMergeTask_meta_tagErr;
+  wire         _mainPipe_io_toSourceD_bits_task_aMergeTask_meta_dataErr;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitRelease;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseToInval;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseToClean;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseWithData;
+  wire [7:0]   _mainPipe_io_toSourceD_bits_task_snpHitReleaseIdx;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_dirty;
+  wire [1:0]   _mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_state;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_clients;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_alias;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_prefetch;
+  wire [3:0]   _mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_prefetchSrc;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_accessed;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_tagErr;
+  wire         _mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_dataErr;
+  wire [10:0]  _mainPipe_io_toSourceD_bits_task_tgtID;
+  wire [10:0]  _mainPipe_io_toSourceD_bits_task_srcID;
+  wire [11:0]  _mainPipe_io_toSourceD_bits_task_txnID;
+  wire [10:0]  _mainPipe_io_toSourceD_bits_task_homeNID;
+  wire [11:0]  _mainPipe_io_toSourceD_bits_task_dbID;
+  wire [10:0]  _mainPipe_io_toSourceD_bits_task_fwdNID;
+  wire [11:0]  _mainPipe_io_toSourceD_bits_task_fwdTxnID;
+  wire [6:0]   _mainPipe_io_toSourceD_bits_task_chiOpcode;
+  wire [2:0]   _mainPipe_io_toSourceD_bits_task_resp;
+  wire [2:0]   _mainPipe_io_toSourceD_bits_task_fwdState;
+  wire [3:0]   _mainPipe_io_toSourceD_bits_task_pCrdType;
+  wire         _mainPipe_io_toSourceD_bits_task_retToSrc;
+  wire         _mainPipe_io_toSourceD_bits_task_likelyshared;
+  wire         _mainPipe_io_toSourceD_bits_task_expCompAck;
+  wire         _mainPipe_io_toSourceD_bits_task_allowRetry;
+  wire         _mainPipe_io_toSourceD_bits_task_memAttr_allocate;
+  wire         _mainPipe_io_toSourceD_bits_task_memAttr_cacheable;
+  wire         _mainPipe_io_toSourceD_bits_task_memAttr_device;
+  wire         _mainPipe_io_toSourceD_bits_task_memAttr_ewa;
+  wire         _mainPipe_io_toSourceD_bits_task_traceTag;
+  wire [511:0] _mainPipe_io_toSourceD_bits_data_data;
+  wire         _mainPipe_io_toTXREQ_valid;
+  wire [10:0]  _mainPipe_io_toTXREQ_bits_tgtID;
+  wire [10:0]  _mainPipe_io_toTXREQ_bits_srcID;
+  wire [11:0]  _mainPipe_io_toTXREQ_bits_txnID;
+  wire [6:0]   _mainPipe_io_toTXREQ_bits_opcode;
+  wire [47:0]  _mainPipe_io_toTXREQ_bits_addr;
+  wire         _mainPipe_io_toTXREQ_bits_likelyshared;
+  wire         _mainPipe_io_toTXREQ_bits_allowRetry;
+  wire [3:0]   _mainPipe_io_toTXREQ_bits_pCrdType;
+  wire         _mainPipe_io_toTXREQ_bits_memAttr_allocate;
+  wire         _mainPipe_io_toTXREQ_bits_memAttr_cacheable;
+  wire         _mainPipe_io_toTXREQ_bits_memAttr_device;
+  wire         _mainPipe_io_toTXREQ_bits_memAttr_ewa;
+  wire         _mainPipe_io_toTXREQ_bits_expCompAck;
+  wire         _mainPipe_io_toTXRSP_valid;
+  wire         _mainPipe_io_toTXRSP_bits_denied;
+  wire [10:0]  _mainPipe_io_toTXRSP_bits_tgtID;
+  wire [10:0]  _mainPipe_io_toTXRSP_bits_srcID;
+  wire [11:0]  _mainPipe_io_toTXRSP_bits_txnID;
+  wire [11:0]  _mainPipe_io_toTXRSP_bits_dbID;
+  wire [6:0]   _mainPipe_io_toTXRSP_bits_chiOpcode;
+  wire [2:0]   _mainPipe_io_toTXRSP_bits_resp;
+  wire [2:0]   _mainPipe_io_toTXRSP_bits_fwdState;
+  wire [3:0]   _mainPipe_io_toTXRSP_bits_pCrdType;
+  wire         _mainPipe_io_toTXRSP_bits_traceTag;
+  wire         _mainPipe_io_toTXDAT_valid;
+  wire [2:0]   _mainPipe_io_toTXDAT_bits_task_channel;
+  wire [2:0]   _mainPipe_io_toTXDAT_bits_task_txChannel;
+  wire [7:0]   _mainPipe_io_toTXDAT_bits_task_set;
+  wire [33:0]  _mainPipe_io_toTXDAT_bits_task_tag;
+  wire [5:0]   _mainPipe_io_toTXDAT_bits_task_off;
+  wire         _mainPipe_io_toTXDAT_bits_task_alias;
+  wire [43:0]  _mainPipe_io_toTXDAT_bits_task_vaddr;
+  wire         _mainPipe_io_toTXDAT_bits_task_isKeyword;
+  wire [3:0]   _mainPipe_io_toTXDAT_bits_task_opcode;
+  wire [2:0]   _mainPipe_io_toTXDAT_bits_task_param;
+  wire [2:0]   _mainPipe_io_toTXDAT_bits_task_size;
+  wire [6:0]   _mainPipe_io_toTXDAT_bits_task_sourceId;
+  wire [1:0]   _mainPipe_io_toTXDAT_bits_task_bufIdx;
+  wire         _mainPipe_io_toTXDAT_bits_task_needProbeAckData;
+  wire         _mainPipe_io_toTXDAT_bits_task_denied;
+  wire         _mainPipe_io_toTXDAT_bits_task_corrupt;
+  wire         _mainPipe_io_toTXDAT_bits_task_mshrTask;
+  wire [7:0]   _mainPipe_io_toTXDAT_bits_task_mshrId;
+  wire         _mainPipe_io_toTXDAT_bits_task_aliasTask;
+  wire         _mainPipe_io_toTXDAT_bits_task_useProbeData;
+  wire         _mainPipe_io_toTXDAT_bits_task_mshrRetry;
+  wire         _mainPipe_io_toTXDAT_bits_task_readProbeDataDown;
+  wire         _mainPipe_io_toTXDAT_bits_task_fromL2pft;
+  wire         _mainPipe_io_toTXDAT_bits_task_needHint;
+  wire         _mainPipe_io_toTXDAT_bits_task_dirty;
+  wire [2:0]   _mainPipe_io_toTXDAT_bits_task_way;
+  wire         _mainPipe_io_toTXDAT_bits_task_meta_dirty;
+  wire [1:0]   _mainPipe_io_toTXDAT_bits_task_meta_state;
+  wire         _mainPipe_io_toTXDAT_bits_task_meta_clients;
+  wire         _mainPipe_io_toTXDAT_bits_task_meta_alias;
+  wire         _mainPipe_io_toTXDAT_bits_task_meta_prefetch;
+  wire [3:0]   _mainPipe_io_toTXDAT_bits_task_meta_prefetchSrc;
+  wire         _mainPipe_io_toTXDAT_bits_task_meta_accessed;
+  wire         _mainPipe_io_toTXDAT_bits_task_meta_tagErr;
+  wire         _mainPipe_io_toTXDAT_bits_task_meta_dataErr;
+  wire         _mainPipe_io_toTXDAT_bits_task_metaWen;
+  wire         _mainPipe_io_toTXDAT_bits_task_tagWen;
+  wire         _mainPipe_io_toTXDAT_bits_task_dsWen;
+  wire [7:0]   _mainPipe_io_toTXDAT_bits_task_wayMask;
+  wire         _mainPipe_io_toTXDAT_bits_task_replTask;
+  wire         _mainPipe_io_toTXDAT_bits_task_cmoTask;
+  wire         _mainPipe_io_toTXDAT_bits_task_cmoAll;
+  wire [4:0]   _mainPipe_io_toTXDAT_bits_task_reqSource;
+  wire         _mainPipe_io_toTXDAT_bits_task_mergeA;
+  wire [5:0]   _mainPipe_io_toTXDAT_bits_task_aMergeTask_off;
+  wire         _mainPipe_io_toTXDAT_bits_task_aMergeTask_alias;
+  wire [43:0]  _mainPipe_io_toTXDAT_bits_task_aMergeTask_vaddr;
+  wire         _mainPipe_io_toTXDAT_bits_task_aMergeTask_isKeyword;
+  wire [2:0]   _mainPipe_io_toTXDAT_bits_task_aMergeTask_opcode;
+  wire [2:0]   _mainPipe_io_toTXDAT_bits_task_aMergeTask_param;
+  wire [6:0]   _mainPipe_io_toTXDAT_bits_task_aMergeTask_sourceId;
+  wire         _mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_dirty;
+  wire [1:0]   _mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_state;
+  wire         _mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_clients;
+  wire         _mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_alias;
+  wire         _mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_prefetch;
+  wire [3:0]   _mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_prefetchSrc;
+  wire         _mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_accessed;
+  wire         _mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_tagErr;
+  wire         _mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_dataErr;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitRelease;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseToInval;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseToClean;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseWithData;
+  wire [7:0]   _mainPipe_io_toTXDAT_bits_task_snpHitReleaseIdx;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_dirty;
+  wire [1:0]   _mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_state;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_clients;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_alias;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_prefetch;
+  wire [3:0]   _mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_prefetchSrc;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_accessed;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_tagErr;
+  wire         _mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_dataErr;
+  wire [10:0]  _mainPipe_io_toTXDAT_bits_task_tgtID;
+  wire [10:0]  _mainPipe_io_toTXDAT_bits_task_srcID;
+  wire [11:0]  _mainPipe_io_toTXDAT_bits_task_txnID;
+  wire [10:0]  _mainPipe_io_toTXDAT_bits_task_homeNID;
+  wire [11:0]  _mainPipe_io_toTXDAT_bits_task_dbID;
+  wire [10:0]  _mainPipe_io_toTXDAT_bits_task_fwdNID;
+  wire [11:0]  _mainPipe_io_toTXDAT_bits_task_fwdTxnID;
+  wire [6:0]   _mainPipe_io_toTXDAT_bits_task_chiOpcode;
+  wire [2:0]   _mainPipe_io_toTXDAT_bits_task_resp;
+  wire [2:0]   _mainPipe_io_toTXDAT_bits_task_fwdState;
+  wire [3:0]   _mainPipe_io_toTXDAT_bits_task_pCrdType;
+  wire         _mainPipe_io_toTXDAT_bits_task_retToSrc;
+  wire         _mainPipe_io_toTXDAT_bits_task_likelyshared;
+  wire         _mainPipe_io_toTXDAT_bits_task_expCompAck;
+  wire         _mainPipe_io_toTXDAT_bits_task_allowRetry;
+  wire         _mainPipe_io_toTXDAT_bits_task_memAttr_allocate;
+  wire         _mainPipe_io_toTXDAT_bits_task_memAttr_cacheable;
+  wire         _mainPipe_io_toTXDAT_bits_task_memAttr_device;
+  wire         _mainPipe_io_toTXDAT_bits_task_memAttr_ewa;
+  wire         _mainPipe_io_toTXDAT_bits_task_traceTag;
+  wire [511:0] _mainPipe_io_toTXDAT_bits_data_data;
+  wire         _mainPipe_io_metaWReq_valid;
+  wire [7:0]   _mainPipe_io_metaWReq_bits_set;
+  wire [7:0]   _mainPipe_io_metaWReq_bits_wayOH;
+  wire         _mainPipe_io_metaWReq_bits_wmeta_dirty;
+  wire [1:0]   _mainPipe_io_metaWReq_bits_wmeta_state;
+  wire         _mainPipe_io_metaWReq_bits_wmeta_clients;
+  wire         _mainPipe_io_metaWReq_bits_wmeta_alias;
+  wire         _mainPipe_io_metaWReq_bits_wmeta_prefetch;
+  wire [3:0]   _mainPipe_io_metaWReq_bits_wmeta_prefetchSrc;
+  wire         _mainPipe_io_metaWReq_bits_wmeta_accessed;
+  wire         _mainPipe_io_metaWReq_bits_wmeta_tagErr;
+  wire         _mainPipe_io_metaWReq_bits_wmeta_dataErr;
+  wire         _mainPipe_io_tagWReq_valid;
+  wire [7:0]   _mainPipe_io_tagWReq_bits_set;
+  wire [7:0]   _mainPipe_io_tagWReq_bits_wayOH;
+  wire [33:0]  _mainPipe_io_tagWReq_bits_wtag;
+  wire         _mainPipe_io_releaseBufWrite_valid;
+  wire [7:0]   _mainPipe_io_releaseBufWrite_bits_id;
+  wire [511:0] _mainPipe_io_releaseBufWrite_bits_data_data;
+  wire [7:0]   _mainPipe_io_nestedwb_set;
+  wire [33:0]  _mainPipe_io_nestedwb_tag;
+  wire         _mainPipe_io_nestedwb_c_set_dirty;
+  wire         _mainPipe_io_nestedwb_c_set_tip;
+  wire         _mainPipe_io_nestedwb_b_inv_dirty;
+  wire         _mainPipe_io_nestedwb_b_toB;
+  wire         _mainPipe_io_nestedwb_b_toN;
+  wire         _mainPipe_io_nestedwb_b_toClean;
+  wire [511:0] _mainPipe_io_nestedwbData_data;
+  wire         _mainPipe_io_error_valid;
+  wire         _mainPipe_io_error_bits_valid;
+  wire [47:0]  _mainPipe_io_error_bits_address;
+  wire [5:0]   _mainPipe_io_perf_0_value;
+  wire [5:0]   _mainPipe_io_perf_1_value;
+  wire [5:0]   _mainPipe_io_perf_2_value;
+  wire [5:0]   _mainPipe_io_perf_3_value;
+  wire [5:0]   _mainPipe_io_perf_4_value;
+  wire [5:0]   _mainPipe_io_perf_5_value;
+  wire [5:0]   _mainPipe_io_perf_6_value;
+  wire [5:0]   _mainPipe_io_perf_7_value;
+  wire [5:0]   _mainPipe_io_perf_8_value;
+  wire [5:0]   _mainPipe_io_perf_9_value;
+  wire [5:0]   _mainPipe_io_perf_10_value;
+  wire [5:0]   _mainPipe_io_perf_11_value;
+  wire [5:0]   _mainPipe_io_perf_12_value;
+  wire         _reqArb_io_sinkA_ready;
+  wire         _reqArb_io_s1Entrance_valid;
+  wire [7:0]   _reqArb_io_s1Entrance_bits_set;
+  wire         _reqArb_io_sinkB_ready;
+  wire         _reqArb_io_sinkC_ready;
+  wire         _reqArb_io_mshrTask_ready;
+  wire         _reqArb_io_dirRead_s1_valid;
+  wire [33:0]  _reqArb_io_dirRead_s1_bits_tag;
+  wire [7:0]   _reqArb_io_dirRead_s1_bits_set;
+  wire [7:0]   _reqArb_io_dirRead_s1_bits_wayMask;
+  wire [2:0]   _reqArb_io_dirRead_s1_bits_replacerInfo_channel;
+  wire [2:0]   _reqArb_io_dirRead_s1_bits_replacerInfo_opcode;
+  wire [4:0]   _reqArb_io_dirRead_s1_bits_replacerInfo_reqSource;
+  wire         _reqArb_io_dirRead_s1_bits_replacerInfo_refill_prefetch;
+  wire         _reqArb_io_dirRead_s1_bits_refill;
+  wire [7:0]   _reqArb_io_dirRead_s1_bits_mshrId;
+  wire         _reqArb_io_dirRead_s1_bits_cmoAll;
+  wire [2:0]   _reqArb_io_dirRead_s1_bits_cmoWay;
+  wire         _reqArb_io_taskToPipe_s2_valid;
+  wire [2:0]   _reqArb_io_taskToPipe_s2_bits_channel;
+  wire [2:0]   _reqArb_io_taskToPipe_s2_bits_txChannel;
+  wire [7:0]   _reqArb_io_taskToPipe_s2_bits_set;
+  wire [33:0]  _reqArb_io_taskToPipe_s2_bits_tag;
+  wire [5:0]   _reqArb_io_taskToPipe_s2_bits_off;
+  wire         _reqArb_io_taskToPipe_s2_bits_alias;
+  wire [43:0]  _reqArb_io_taskToPipe_s2_bits_vaddr;
+  wire         _reqArb_io_taskToPipe_s2_bits_isKeyword;
+  wire [3:0]   _reqArb_io_taskToPipe_s2_bits_opcode;
+  wire [2:0]   _reqArb_io_taskToPipe_s2_bits_param;
+  wire [2:0]   _reqArb_io_taskToPipe_s2_bits_size;
+  wire [6:0]   _reqArb_io_taskToPipe_s2_bits_sourceId;
+  wire [1:0]   _reqArb_io_taskToPipe_s2_bits_bufIdx;
+  wire         _reqArb_io_taskToPipe_s2_bits_needProbeAckData;
+  wire         _reqArb_io_taskToPipe_s2_bits_denied;
+  wire         _reqArb_io_taskToPipe_s2_bits_corrupt;
+  wire         _reqArb_io_taskToPipe_s2_bits_mshrTask;
+  wire [7:0]   _reqArb_io_taskToPipe_s2_bits_mshrId;
+  wire         _reqArb_io_taskToPipe_s2_bits_aliasTask;
+  wire         _reqArb_io_taskToPipe_s2_bits_useProbeData;
+  wire         _reqArb_io_taskToPipe_s2_bits_mshrRetry;
+  wire         _reqArb_io_taskToPipe_s2_bits_readProbeDataDown;
+  wire         _reqArb_io_taskToPipe_s2_bits_fromL2pft;
+  wire         _reqArb_io_taskToPipe_s2_bits_needHint;
+  wire         _reqArb_io_taskToPipe_s2_bits_dirty;
+  wire [2:0]   _reqArb_io_taskToPipe_s2_bits_way;
+  wire         _reqArb_io_taskToPipe_s2_bits_meta_dirty;
+  wire [1:0]   _reqArb_io_taskToPipe_s2_bits_meta_state;
+  wire         _reqArb_io_taskToPipe_s2_bits_meta_clients;
+  wire         _reqArb_io_taskToPipe_s2_bits_meta_alias;
+  wire         _reqArb_io_taskToPipe_s2_bits_meta_prefetch;
+  wire [3:0]   _reqArb_io_taskToPipe_s2_bits_meta_prefetchSrc;
+  wire         _reqArb_io_taskToPipe_s2_bits_meta_accessed;
+  wire         _reqArb_io_taskToPipe_s2_bits_meta_tagErr;
+  wire         _reqArb_io_taskToPipe_s2_bits_meta_dataErr;
+  wire         _reqArb_io_taskToPipe_s2_bits_metaWen;
+  wire         _reqArb_io_taskToPipe_s2_bits_tagWen;
+  wire         _reqArb_io_taskToPipe_s2_bits_dsWen;
+  wire [7:0]   _reqArb_io_taskToPipe_s2_bits_wayMask;
+  wire         _reqArb_io_taskToPipe_s2_bits_replTask;
+  wire         _reqArb_io_taskToPipe_s2_bits_cmoTask;
+  wire         _reqArb_io_taskToPipe_s2_bits_cmoAll;
+  wire [4:0]   _reqArb_io_taskToPipe_s2_bits_reqSource;
+  wire         _reqArb_io_taskToPipe_s2_bits_mergeA;
+  wire [5:0]   _reqArb_io_taskToPipe_s2_bits_aMergeTask_off;
+  wire         _reqArb_io_taskToPipe_s2_bits_aMergeTask_alias;
+  wire [43:0]  _reqArb_io_taskToPipe_s2_bits_aMergeTask_vaddr;
+  wire         _reqArb_io_taskToPipe_s2_bits_aMergeTask_isKeyword;
+  wire [2:0]   _reqArb_io_taskToPipe_s2_bits_aMergeTask_opcode;
+  wire [2:0]   _reqArb_io_taskToPipe_s2_bits_aMergeTask_param;
+  wire [6:0]   _reqArb_io_taskToPipe_s2_bits_aMergeTask_sourceId;
+  wire         _reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_dirty;
+  wire [1:0]   _reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_state;
+  wire         _reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_clients;
+  wire         _reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_alias;
+  wire         _reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_prefetch;
+  wire [3:0]   _reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_prefetchSrc;
+  wire         _reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_accessed;
+  wire         _reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_tagErr;
+  wire         _reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_dataErr;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitRelease;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseToInval;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseToClean;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseWithData;
+  wire [7:0]   _reqArb_io_taskToPipe_s2_bits_snpHitReleaseIdx;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]   _reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_state;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_clients;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_alias;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]   _reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetchSrc;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_accessed;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_tagErr;
+  wire         _reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0]  _reqArb_io_taskToPipe_s2_bits_tgtID;
+  wire [10:0]  _reqArb_io_taskToPipe_s2_bits_srcID;
+  wire [11:0]  _reqArb_io_taskToPipe_s2_bits_txnID;
+  wire [10:0]  _reqArb_io_taskToPipe_s2_bits_homeNID;
+  wire [11:0]  _reqArb_io_taskToPipe_s2_bits_dbID;
+  wire [10:0]  _reqArb_io_taskToPipe_s2_bits_fwdNID;
+  wire [11:0]  _reqArb_io_taskToPipe_s2_bits_fwdTxnID;
+  wire [6:0]   _reqArb_io_taskToPipe_s2_bits_chiOpcode;
+  wire [2:0]   _reqArb_io_taskToPipe_s2_bits_resp;
+  wire [2:0]   _reqArb_io_taskToPipe_s2_bits_fwdState;
+  wire [3:0]   _reqArb_io_taskToPipe_s2_bits_pCrdType;
+  wire         _reqArb_io_taskToPipe_s2_bits_retToSrc;
+  wire         _reqArb_io_taskToPipe_s2_bits_likelyshared;
+  wire         _reqArb_io_taskToPipe_s2_bits_expCompAck;
+  wire         _reqArb_io_taskToPipe_s2_bits_allowRetry;
+  wire         _reqArb_io_taskToPipe_s2_bits_memAttr_allocate;
+  wire         _reqArb_io_taskToPipe_s2_bits_memAttr_cacheable;
+  wire         _reqArb_io_taskToPipe_s2_bits_memAttr_device;
+  wire         _reqArb_io_taskToPipe_s2_bits_memAttr_ewa;
+  wire         _reqArb_io_taskToPipe_s2_bits_traceTag;
+  wire         _reqArb_io_mshrHintQInfo_valid;
+  wire [2:0]   _reqArb_io_mshrHintQInfo_bits_channel;
+  wire         _reqArb_io_mshrHintQInfo_bits_isKeyword;
+  wire [3:0]   _reqArb_io_mshrHintQInfo_bits_opcode;
+  wire [6:0]   _reqArb_io_mshrHintQInfo_bits_sourceId;
+  wire         _reqArb_io_mshrHintQInfo_bits_mergeA;
+  wire         _reqArb_io_mshrHintQInfo_bits_aMergeTask_isKeyword;
+  wire [2:0]   _reqArb_io_mshrHintQInfo_bits_aMergeTask_opcode;
+  wire [6:0]   _reqArb_io_mshrHintQInfo_bits_aMergeTask_sourceId;
+  wire         _reqArb_io_sinkCHintQInfo_valid;
+  wire [6:0]   _reqArb_io_sinkCHintQInfo_bits_sourceId;
+  wire         _reqArb_io_refillBufRead_s2_valid;
+  wire [7:0]   _reqArb_io_refillBufRead_s2_bits_id;
+  wire         _reqArb_io_releaseBufRead_s2_valid;
+  wire [7:0]   _reqArb_io_releaseBufRead_s2_bits_id;
+  wire [33:0]  _reqArb_io_status_s1_tags_1;
+  wire [7:0]   _reqArb_io_status_s1_sets_0;
+  wire [7:0]   _reqArb_io_status_s1_sets_1;
+  wire [7:0]   _reqArb_io_status_s1_sets_2;
+  wire [7:0]   _reqArb_io_status_s1_sets_3;
+  wire         _reqArb_io_status_vec_1_valid;
+  wire [2:0]   _reqArb_io_status_vec_1_bits_channel;
+  wire         _reqArb_io_status_vec_toTX_1_valid;
+  wire [2:0]   _reqArb_io_status_vec_toTX_1_bits_channel;
+  wire [2:0]   _reqArb_io_status_vec_toTX_1_bits_txChannel;
+  wire         _reqArb_io_status_vec_toTX_1_bits_mshrTask;
+  wire [511:0] _releaseBuf_io_resp_data_data;
+  wire [511:0] _refillBuf_io_resp_data_data;
+  wire         _dataStorage_io_error;
+  wire [511:0] _dataStorage_io_rdata_data;
+  wire         _directory_io_read_ready;
+  wire         _directory_io_resp_bits_hit;
+  wire [33:0]  _directory_io_resp_bits_tag;
+  wire [7:0]   _directory_io_resp_bits_set;
+  wire [2:0]   _directory_io_resp_bits_way;
+  wire         _directory_io_resp_bits_meta_tagErr;
+  wire         _directory_io_resp_bits_meta_dataErr;
+  wire         _directory_io_resp_bits_error;
+  wire         _directory_io_replResp_valid;
+  wire [33:0]  _directory_io_replResp_bits_tag;
+  wire [2:0]   _directory_io_replResp_bits_way;
+  wire         _directory_io_replResp_bits_meta_dirty;
+  wire [1:0]   _directory_io_replResp_bits_meta_state;
+  wire         _directory_io_replResp_bits_meta_clients;
+  wire         _directory_io_replResp_bits_meta_alias;
+  wire         _directory_io_replResp_bits_meta_prefetch;
+  wire [3:0]   _directory_io_replResp_bits_meta_prefetchSrc;
+  wire         _directory_io_replResp_bits_meta_accessed;
+  wire         _directory_io_replResp_bits_meta_tagErr;
+  wire         _directory_io_replResp_bits_meta_dataErr;
+  wire [7:0]   _directory_io_replResp_bits_mshrId;
+  wire         _directory_io_replResp_bits_retry;
+  wire         _directory_io_replResp_bits_validHold;
+  wire         _directory_io_metaOnHit_dirty;
+  wire [1:0]   _directory_io_metaOnHit_state;
+  wire         _directory_io_metaOnHit_clients;
+  wire         _directory_io_metaOnHit_alias;
+  wire         _directory_io_metaOnHit_prefetch;
+  wire [3:0]   _directory_io_metaOnHit_prefetchSrc;
+  wire         _directory_io_metaOnHit_accessed;
+  wire         _directory_io_metaOnHit_tagErr;
+  wire         _directory_io_metaOnHit_dataErr;
+  wire         _directory_io_errOnSnp;
+  wire [7:0]   _directory_io_wayOH;
+  wire [7:0]   _directory_io_replWayOH;
+  wire         _directory_io_retryFastFwd;
+  wire         _rxrsp_io_in_valid;
+  wire [7:0]   _rxrsp_io_in_mshrId;
+  wire [6:0]   _rxrsp_io_in_respInfo_chiOpcode;
+  wire [10:0]  _rxrsp_io_in_respInfo_srcID;
+  wire [11:0]  _rxrsp_io_in_respInfo_dbID;
+  wire [2:0]   _rxrsp_io_in_respInfo_resp;
+  wire [3:0]   _rxrsp_io_in_respInfo_pCrdType;
+  wire [1:0]   _rxrsp_io_in_respInfo_respErr;
+  wire         _rxrsp_io_in_respInfo_traceTag;
+  wire         _rxdat_io_in_valid;
+  wire [7:0]   _rxdat_io_in_mshrId;
+  wire         _rxdat_io_in_respInfo_last;
+  wire         _rxdat_io_in_respInfo_corrupt;
+  wire [6:0]   _rxdat_io_in_respInfo_chiOpcode;
+  wire [10:0]  _rxdat_io_in_respInfo_homeNID;
+  wire [11:0]  _rxdat_io_in_respInfo_dbID;
+  wire [2:0]   _rxdat_io_in_respInfo_resp;
+  wire [1:0]   _rxdat_io_in_respInfo_respErr;
+  wire         _rxdat_io_in_respInfo_traceTag;
+  wire         _rxdat_io_refillBufWrite_valid;
+  wire [7:0]   _rxdat_io_refillBufWrite_bits_id;
+  wire [511:0] _rxdat_io_refillBufWrite_bits_data_data;
+  wire [1:0]   _rxdat_io_refillBufWrite_bits_beatMask;
+  wire         _rxsnp_io_task_valid;
+  wire [7:0]   _rxsnp_io_task_bits_set;
+  wire [33:0]  _rxsnp_io_task_bits_tag;
+  wire [5:0]   _rxsnp_io_task_bits_off;
+  wire         _rxsnp_io_task_bits_snpHitRelease;
+  wire         _rxsnp_io_task_bits_snpHitReleaseToInval;
+  wire         _rxsnp_io_task_bits_snpHitReleaseToClean;
+  wire         _rxsnp_io_task_bits_snpHitReleaseWithData;
+  wire [7:0]   _rxsnp_io_task_bits_snpHitReleaseIdx;
+  wire         _rxsnp_io_task_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]   _rxsnp_io_task_bits_snpHitReleaseMeta_state;
+  wire         _rxsnp_io_task_bits_snpHitReleaseMeta_clients;
+  wire         _rxsnp_io_task_bits_snpHitReleaseMeta_alias;
+  wire         _rxsnp_io_task_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]   _rxsnp_io_task_bits_snpHitReleaseMeta_prefetchSrc;
+  wire         _rxsnp_io_task_bits_snpHitReleaseMeta_accessed;
+  wire         _rxsnp_io_task_bits_snpHitReleaseMeta_tagErr;
+  wire         _rxsnp_io_task_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0]  _rxsnp_io_task_bits_srcID;
+  wire [11:0]  _rxsnp_io_task_bits_txnID;
+  wire [10:0]  _rxsnp_io_task_bits_fwdNID;
+  wire [11:0]  _rxsnp_io_task_bits_fwdTxnID;
+  wire [6:0]   _rxsnp_io_task_bits_chiOpcode;
+  wire         _rxsnp_io_task_bits_retToSrc;
+  wire         _rxsnp_io_task_bits_traceTag;
+  wire         _txrsp_io_mshrRsp_ready;
+  wire         _txrsp_io_toReqArb_blockMSHRReqEntrance;
+  wire         _txrsp_io_toReqArb_blockSinkBReqEntrance;
+  wire         _txdat_io_in_ready;
+  wire         _txdat_io_toReqArb_blockMSHRReqEntrance;
+  wire         _txdat_io_toReqArb_blockSinkBReqEntrance;
+  wire         _txreq_io_mshrReq_ready;
+  wire         _txreq_io_toReqArb_blockMSHRReqEntrance;
+  wire         _grantBuf_io_toReqArb_blockSinkReqEntrance_blockA_s1;
+  wire         _grantBuf_io_toReqArb_blockSinkReqEntrance_blockB_s1;
+  wire         _grantBuf_io_toReqArb_blockSinkReqEntrance_blockC_s1;
+  wire         _grantBuf_io_toReqArb_blockMSHRReqEntrance;
+  wire         _grantBuf_io_grantStatus_0_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_0_set;
+  wire [33:0]  _grantBuf_io_grantStatus_0_tag;
+  wire         _grantBuf_io_grantStatus_1_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_1_set;
+  wire [33:0]  _grantBuf_io_grantStatus_1_tag;
+  wire         _grantBuf_io_grantStatus_2_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_2_set;
+  wire [33:0]  _grantBuf_io_grantStatus_2_tag;
+  wire         _grantBuf_io_grantStatus_3_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_3_set;
+  wire [33:0]  _grantBuf_io_grantStatus_3_tag;
+  wire         _grantBuf_io_grantStatus_4_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_4_set;
+  wire [33:0]  _grantBuf_io_grantStatus_4_tag;
+  wire         _grantBuf_io_grantStatus_5_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_5_set;
+  wire [33:0]  _grantBuf_io_grantStatus_5_tag;
+  wire         _grantBuf_io_grantStatus_6_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_6_set;
+  wire [33:0]  _grantBuf_io_grantStatus_6_tag;
+  wire         _grantBuf_io_grantStatus_7_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_7_set;
+  wire [33:0]  _grantBuf_io_grantStatus_7_tag;
+  wire         _grantBuf_io_grantStatus_8_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_8_set;
+  wire [33:0]  _grantBuf_io_grantStatus_8_tag;
+  wire         _grantBuf_io_grantStatus_9_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_9_set;
+  wire [33:0]  _grantBuf_io_grantStatus_9_tag;
+  wire         _grantBuf_io_grantStatus_10_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_10_set;
+  wire [33:0]  _grantBuf_io_grantStatus_10_tag;
+  wire         _grantBuf_io_grantStatus_11_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_11_set;
+  wire [33:0]  _grantBuf_io_grantStatus_11_tag;
+  wire         _grantBuf_io_grantStatus_12_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_12_set;
+  wire [33:0]  _grantBuf_io_grantStatus_12_tag;
+  wire         _grantBuf_io_grantStatus_13_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_13_set;
+  wire [33:0]  _grantBuf_io_grantStatus_13_tag;
+  wire         _grantBuf_io_grantStatus_14_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_14_set;
+  wire [33:0]  _grantBuf_io_grantStatus_14_tag;
+  wire         _grantBuf_io_grantStatus_15_valid;
+  wire [7:0]   _grantBuf_io_grantStatus_15_set;
+  wire [33:0]  _grantBuf_io_grantStatus_15_tag;
+  wire         _sinkC_io_task_valid;
+  wire [2:0]   _sinkC_io_task_bits_channel;
+  wire [2:0]   _sinkC_io_task_bits_txChannel;
+  wire [7:0]   _sinkC_io_task_bits_set;
+  wire [33:0]  _sinkC_io_task_bits_tag;
+  wire [5:0]   _sinkC_io_task_bits_off;
+  wire         _sinkC_io_task_bits_alias;
+  wire [43:0]  _sinkC_io_task_bits_vaddr;
+  wire         _sinkC_io_task_bits_isKeyword;
+  wire [3:0]   _sinkC_io_task_bits_opcode;
+  wire [2:0]   _sinkC_io_task_bits_param;
+  wire [2:0]   _sinkC_io_task_bits_size;
+  wire [6:0]   _sinkC_io_task_bits_sourceId;
+  wire [1:0]   _sinkC_io_task_bits_bufIdx;
+  wire         _sinkC_io_task_bits_needProbeAckData;
+  wire         _sinkC_io_task_bits_denied;
+  wire         _sinkC_io_task_bits_corrupt;
+  wire         _sinkC_io_task_bits_mshrTask;
+  wire [7:0]   _sinkC_io_task_bits_mshrId;
+  wire         _sinkC_io_task_bits_aliasTask;
+  wire         _sinkC_io_task_bits_useProbeData;
+  wire         _sinkC_io_task_bits_mshrRetry;
+  wire         _sinkC_io_task_bits_readProbeDataDown;
+  wire         _sinkC_io_task_bits_fromL2pft;
+  wire         _sinkC_io_task_bits_needHint;
+  wire         _sinkC_io_task_bits_dirty;
+  wire [2:0]   _sinkC_io_task_bits_way;
+  wire         _sinkC_io_task_bits_meta_dirty;
+  wire [1:0]   _sinkC_io_task_bits_meta_state;
+  wire         _sinkC_io_task_bits_meta_clients;
+  wire         _sinkC_io_task_bits_meta_alias;
+  wire         _sinkC_io_task_bits_meta_prefetch;
+  wire [3:0]   _sinkC_io_task_bits_meta_prefetchSrc;
+  wire         _sinkC_io_task_bits_meta_accessed;
+  wire         _sinkC_io_task_bits_meta_tagErr;
+  wire         _sinkC_io_task_bits_meta_dataErr;
+  wire         _sinkC_io_task_bits_metaWen;
+  wire         _sinkC_io_task_bits_tagWen;
+  wire         _sinkC_io_task_bits_dsWen;
+  wire [7:0]   _sinkC_io_task_bits_wayMask;
+  wire         _sinkC_io_task_bits_replTask;
+  wire         _sinkC_io_task_bits_cmoTask;
+  wire         _sinkC_io_task_bits_cmoAll;
+  wire [4:0]   _sinkC_io_task_bits_reqSource;
+  wire         _sinkC_io_task_bits_mergeA;
+  wire [5:0]   _sinkC_io_task_bits_aMergeTask_off;
+  wire         _sinkC_io_task_bits_aMergeTask_alias;
+  wire [43:0]  _sinkC_io_task_bits_aMergeTask_vaddr;
+  wire         _sinkC_io_task_bits_aMergeTask_isKeyword;
+  wire [2:0]   _sinkC_io_task_bits_aMergeTask_opcode;
+  wire [2:0]   _sinkC_io_task_bits_aMergeTask_param;
+  wire [6:0]   _sinkC_io_task_bits_aMergeTask_sourceId;
+  wire         _sinkC_io_task_bits_aMergeTask_meta_dirty;
+  wire [1:0]   _sinkC_io_task_bits_aMergeTask_meta_state;
+  wire         _sinkC_io_task_bits_aMergeTask_meta_clients;
+  wire         _sinkC_io_task_bits_aMergeTask_meta_alias;
+  wire         _sinkC_io_task_bits_aMergeTask_meta_prefetch;
+  wire [3:0]   _sinkC_io_task_bits_aMergeTask_meta_prefetchSrc;
+  wire         _sinkC_io_task_bits_aMergeTask_meta_accessed;
+  wire         _sinkC_io_task_bits_aMergeTask_meta_tagErr;
+  wire         _sinkC_io_task_bits_aMergeTask_meta_dataErr;
+  wire         _sinkC_io_task_bits_snpHitRelease;
+  wire         _sinkC_io_task_bits_snpHitReleaseToInval;
+  wire         _sinkC_io_task_bits_snpHitReleaseToClean;
+  wire         _sinkC_io_task_bits_snpHitReleaseWithData;
+  wire [7:0]   _sinkC_io_task_bits_snpHitReleaseIdx;
+  wire         _sinkC_io_task_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]   _sinkC_io_task_bits_snpHitReleaseMeta_state;
+  wire         _sinkC_io_task_bits_snpHitReleaseMeta_clients;
+  wire         _sinkC_io_task_bits_snpHitReleaseMeta_alias;
+  wire         _sinkC_io_task_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]   _sinkC_io_task_bits_snpHitReleaseMeta_prefetchSrc;
+  wire         _sinkC_io_task_bits_snpHitReleaseMeta_accessed;
+  wire         _sinkC_io_task_bits_snpHitReleaseMeta_tagErr;
+  wire         _sinkC_io_task_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0]  _sinkC_io_task_bits_tgtID;
+  wire [10:0]  _sinkC_io_task_bits_srcID;
+  wire [11:0]  _sinkC_io_task_bits_txnID;
+  wire [10:0]  _sinkC_io_task_bits_homeNID;
+  wire [11:0]  _sinkC_io_task_bits_dbID;
+  wire [10:0]  _sinkC_io_task_bits_fwdNID;
+  wire [11:0]  _sinkC_io_task_bits_fwdTxnID;
+  wire [6:0]   _sinkC_io_task_bits_chiOpcode;
+  wire [2:0]   _sinkC_io_task_bits_resp;
+  wire [2:0]   _sinkC_io_task_bits_fwdState;
+  wire [3:0]   _sinkC_io_task_bits_pCrdType;
+  wire         _sinkC_io_task_bits_retToSrc;
+  wire         _sinkC_io_task_bits_likelyshared;
+  wire         _sinkC_io_task_bits_expCompAck;
+  wire         _sinkC_io_task_bits_allowRetry;
+  wire         _sinkC_io_task_bits_memAttr_allocate;
+  wire         _sinkC_io_task_bits_memAttr_cacheable;
+  wire         _sinkC_io_task_bits_memAttr_device;
+  wire         _sinkC_io_task_bits_memAttr_ewa;
+  wire         _sinkC_io_task_bits_traceTag;
+  wire         _sinkC_io_resp_valid;
+  wire [7:0]   _sinkC_io_resp_set;
+  wire [33:0]  _sinkC_io_resp_tag;
+  wire [2:0]   _sinkC_io_resp_respInfo_opcode;
+  wire [2:0]   _sinkC_io_resp_respInfo_param;
+  wire         _sinkC_io_resp_respInfo_last;
+  wire         _sinkC_io_resp_respInfo_denied;
+  wire         _sinkC_io_resp_respInfo_corrupt;
+  wire         _sinkC_io_releaseBufWrite_valid;
+  wire [511:0] _sinkC_io_releaseBufWrite_bits_data_data;
+  wire [255:0] _sinkC_io_bufResp_data_0;
+  wire [255:0] _sinkC_io_bufResp_data_1;
+  wire         _sinkC_io_refillBufWrite_valid;
+  wire [7:0]   _sinkC_io_refillBufWrite_bits_id;
+  wire [511:0] _sinkC_io_refillBufWrite_bits_data_data;
+  wire         _sinkA_io_task_valid;
+  wire [7:0]   _sinkA_io_task_bits_set;
+  wire [33:0]  _sinkA_io_task_bits_tag;
+  wire [5:0]   _sinkA_io_task_bits_off;
+  wire         _sinkA_io_task_bits_alias;
+  wire [43:0]  _sinkA_io_task_bits_vaddr;
+  wire         _sinkA_io_task_bits_isKeyword;
+  wire [3:0]   _sinkA_io_task_bits_opcode;
+  wire [2:0]   _sinkA_io_task_bits_param;
+  wire [2:0]   _sinkA_io_task_bits_size;
+  wire [6:0]   _sinkA_io_task_bits_sourceId;
+  wire         _sinkA_io_task_bits_corrupt;
+  wire         _sinkA_io_task_bits_fromL2pft;
+  wire         _sinkA_io_task_bits_needHint;
+  wire [4:0]   _sinkA_io_task_bits_reqSource;
+  wire [3:0]   bd_array = boreChildrenBd_bore_array;
+  wire         bd_all = boreChildrenBd_bore_all;
+  wire         bd_req = boreChildrenBd_bore_req;
+  wire         bd_writeen = boreChildrenBd_bore_writeen;
+  wire [7:0]   bd_be = boreChildrenBd_bore_be;
+  wire [11:0]  bd_addr = boreChildrenBd_bore_addr;
+  wire [163:0] bd_indata = boreChildrenBd_bore_indata;
+  wire         bd_readen = boreChildrenBd_bore_readen;
+  wire [11:0]  bd_addr_rd = boreChildrenBd_bore_addr_rd;
+  reg          mainPipe_io_releaseBufResp_s3_valid_REG;
+  reg          io_error_valid_REG;
+  reg          io_error_bits_REG_valid;
+  reg  [47:0]  io_error_bits_REG_address;
+  reg  [5:0]   io_perf_0_value_REG;
+  reg  [5:0]   io_perf_0_value_REG_1;
+  reg  [5:0]   io_perf_1_value_REG;
+  reg  [5:0]   io_perf_1_value_REG_1;
+  reg  [5:0]   io_perf_3_value_REG;
+  reg  [5:0]   io_perf_3_value_REG_1;
+  reg  [5:0]   io_perf_4_value_REG;
+  reg  [5:0]   io_perf_4_value_REG_1;
+  reg  [5:0]   io_perf_5_value_REG;
+  reg  [5:0]   io_perf_5_value_REG_1;
+  reg  [5:0]   io_perf_6_value_REG;
+  reg  [5:0]   io_perf_6_value_REG_1;
+  reg  [5:0]   io_perf_7_value_REG;
+  reg  [5:0]   io_perf_7_value_REG_1;
+  reg  [5:0]   io_perf_8_value_REG;
+  reg  [5:0]   io_perf_8_value_REG_1;
+  reg  [5:0]   io_perf_9_value_REG;
+  reg  [5:0]   io_perf_9_value_REG_1;
+  reg  [5:0]   io_perf_10_value_REG;
+  reg  [5:0]   io_perf_10_value_REG_1;
+  reg  [5:0]   io_perf_11_value_REG;
+  reg  [5:0]   io_perf_11_value_REG_1;
+  reg  [5:0]   io_perf_12_value_REG;
+  reg  [5:0]   io_perf_12_value_REG_1;
+  reg  [5:0]   io_perf_13_value_REG;
+  reg  [5:0]   io_perf_13_value_REG_1;
+  reg  [5:0]   io_perf_14_value_REG;
+  reg  [5:0]   io_perf_14_value_REG_1;
+  reg  [5:0]   io_perf_15_value_REG;
+  reg  [5:0]   io_perf_15_value_REG_1;
+  reg  [5:0]   io_perf_16_value_REG;
+  reg  [5:0]   io_perf_16_value_REG_1;
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      mainPipe_io_releaseBufResp_s3_valid_REG <= 1'h0;
+      io_error_valid_REG <= 1'h0;
+    end
+    else begin
+      mainPipe_io_releaseBufResp_s3_valid_REG <= _reqArb_io_releaseBufRead_s2_valid;
+      io_error_valid_REG <= _mainPipe_io_error_valid;
+    end
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    io_error_bits_REG_valid <= _mainPipe_io_error_bits_valid;
+    io_error_bits_REG_address <= _mainPipe_io_error_bits_address;
+    io_perf_0_value_REG <= _mshrCtl_io_perf_0_value;
+    io_perf_0_value_REG_1 <= io_perf_0_value_REG;
+    io_perf_1_value_REG <= _mshrCtl_io_perf_1_value;
+    io_perf_1_value_REG_1 <= io_perf_1_value_REG;
+    io_perf_3_value_REG <= _mshrCtl_io_perf_3_value;
+    io_perf_3_value_REG_1 <= io_perf_3_value_REG;
+    io_perf_4_value_REG <= _mainPipe_io_perf_0_value;
+    io_perf_4_value_REG_1 <= io_perf_4_value_REG;
+    io_perf_5_value_REG <= _mainPipe_io_perf_1_value;
+    io_perf_5_value_REG_1 <= io_perf_5_value_REG;
+    io_perf_6_value_REG <= _mainPipe_io_perf_2_value;
+    io_perf_6_value_REG_1 <= io_perf_6_value_REG;
+    io_perf_7_value_REG <= _mainPipe_io_perf_3_value;
+    io_perf_7_value_REG_1 <= io_perf_7_value_REG;
+    io_perf_8_value_REG <= _mainPipe_io_perf_4_value;
+    io_perf_8_value_REG_1 <= io_perf_8_value_REG;
+    io_perf_9_value_REG <= _mainPipe_io_perf_5_value;
+    io_perf_9_value_REG_1 <= io_perf_9_value_REG;
+    io_perf_10_value_REG <= _mainPipe_io_perf_6_value;
+    io_perf_10_value_REG_1 <= io_perf_10_value_REG;
+    io_perf_11_value_REG <= _mainPipe_io_perf_7_value;
+    io_perf_11_value_REG_1 <= io_perf_11_value_REG;
+    io_perf_12_value_REG <= _mainPipe_io_perf_8_value;
+    io_perf_12_value_REG_1 <= io_perf_12_value_REG;
+    io_perf_13_value_REG <= _mainPipe_io_perf_9_value;
+    io_perf_13_value_REG_1 <= io_perf_13_value_REG;
+    io_perf_14_value_REG <= _mainPipe_io_perf_10_value;
+    io_perf_14_value_REG_1 <= io_perf_14_value_REG;
+    io_perf_15_value_REG <= _mainPipe_io_perf_11_value;
+    io_perf_15_value_REG_1 <= io_perf_15_value_REG;
+    io_perf_16_value_REG <= _mainPipe_io_perf_12_value;
+    io_perf_16_value_REG_1 <= io_perf_16_value_REG;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:7];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin
+          _RANDOM[i[2:0]] = `RANDOM;
+        end
+        mainPipe_io_releaseBufResp_s3_valid_REG = _RANDOM[3'h0][1];
+        io_error_valid_REG = _RANDOM[3'h0][2];
+        io_error_bits_REG_valid = _RANDOM[3'h0][3];
+        io_error_bits_REG_address = {_RANDOM[3'h0][31:4], _RANDOM[3'h1][19:0]};
+        io_perf_0_value_REG = _RANDOM[3'h1][25:20];
+        io_perf_0_value_REG_1 = _RANDOM[3'h1][31:26];
+        io_perf_1_value_REG = _RANDOM[3'h2][5:0];
+        io_perf_1_value_REG_1 = _RANDOM[3'h2][11:6];
+        io_perf_3_value_REG = _RANDOM[3'h2][29:24];
+        io_perf_3_value_REG_1 = {_RANDOM[3'h2][31:30], _RANDOM[3'h3][3:0]};
+        io_perf_4_value_REG = _RANDOM[3'h3][9:4];
+        io_perf_4_value_REG_1 = _RANDOM[3'h3][15:10];
+        io_perf_5_value_REG = _RANDOM[3'h3][21:16];
+        io_perf_5_value_REG_1 = _RANDOM[3'h3][27:22];
+        io_perf_6_value_REG = {_RANDOM[3'h3][31:28], _RANDOM[3'h4][1:0]};
+        io_perf_6_value_REG_1 = _RANDOM[3'h4][7:2];
+        io_perf_7_value_REG = _RANDOM[3'h4][13:8];
+        io_perf_7_value_REG_1 = _RANDOM[3'h4][19:14];
+        io_perf_8_value_REG = _RANDOM[3'h4][25:20];
+        io_perf_8_value_REG_1 = _RANDOM[3'h4][31:26];
+        io_perf_9_value_REG = _RANDOM[3'h5][5:0];
+        io_perf_9_value_REG_1 = _RANDOM[3'h5][11:6];
+        io_perf_10_value_REG = _RANDOM[3'h5][17:12];
+        io_perf_10_value_REG_1 = _RANDOM[3'h5][23:18];
+        io_perf_11_value_REG = _RANDOM[3'h5][29:24];
+        io_perf_11_value_REG_1 = {_RANDOM[3'h5][31:30], _RANDOM[3'h6][3:0]};
+        io_perf_12_value_REG = _RANDOM[3'h6][9:4];
+        io_perf_12_value_REG_1 = _RANDOM[3'h6][15:10];
+        io_perf_13_value_REG = _RANDOM[3'h6][21:16];
+        io_perf_13_value_REG_1 = _RANDOM[3'h6][27:22];
+        io_perf_14_value_REG = {_RANDOM[3'h6][31:28], _RANDOM[3'h7][1:0]};
+        io_perf_14_value_REG_1 = _RANDOM[3'h7][7:2];
+        io_perf_15_value_REG = _RANDOM[3'h7][13:8];
+        io_perf_15_value_REG_1 = _RANDOM[3'h7][19:14];
+        io_perf_16_value_REG = _RANDOM[3'h7][25:20];
+        io_perf_16_value_REG_1 = _RANDOM[3'h7][31:26];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        mainPipe_io_releaseBufResp_s3_valid_REG = 1'h0;
+        io_error_valid_REG = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  SinkA sinkA (
+    .io_a_ready                   (io_in_a_ready),
+    .io_a_valid                   (io_in_a_valid),
+    .io_a_bits_opcode             (io_in_a_bits_opcode),
+    .io_a_bits_param              (io_in_a_bits_param),
+    .io_a_bits_size               (io_in_a_bits_size),
+    .io_a_bits_source             (io_in_a_bits_source),
+    .io_a_bits_address            (io_in_a_bits_address),
+    .io_a_bits_user_reqSource     (io_in_a_bits_user_reqSource),
+    .io_a_bits_user_alias         (io_in_a_bits_user_alias),
+    .io_a_bits_user_vaddr         (io_in_a_bits_user_vaddr),
+    .io_a_bits_user_needHint      (io_in_a_bits_user_needHint),
+    .io_a_bits_echo_isKeyword     (io_in_a_bits_echo_isKeyword),
+    .io_a_bits_corrupt            (io_in_a_bits_corrupt),
+    .io_prefetchReq_ready         (io_prefetch_req_ready),
+    .io_prefetchReq_valid         (io_prefetch_req_valid),
+    .io_prefetchReq_bits_tag      (io_prefetch_req_bits_tag),
+    .io_prefetchReq_bits_set      (io_prefetch_req_bits_set),
+    .io_prefetchReq_bits_vaddr    (io_prefetch_req_bits_vaddr),
+    .io_prefetchReq_bits_needT    (io_prefetch_req_bits_needT),
+    .io_prefetchReq_bits_source   (io_prefetch_req_bits_source),
+    .io_prefetchReq_bits_pfSource (io_prefetch_req_bits_pfSource),
+    .io_task_ready                (_reqBuf_io_in_ready),
+    .io_task_valid                (_sinkA_io_task_valid),
+    .io_task_bits_set             (_sinkA_io_task_bits_set),
+    .io_task_bits_tag             (_sinkA_io_task_bits_tag),
+    .io_task_bits_off             (_sinkA_io_task_bits_off),
+    .io_task_bits_alias           (_sinkA_io_task_bits_alias),
+    .io_task_bits_vaddr           (_sinkA_io_task_bits_vaddr),
+    .io_task_bits_isKeyword       (_sinkA_io_task_bits_isKeyword),
+    .io_task_bits_opcode          (_sinkA_io_task_bits_opcode),
+    .io_task_bits_param           (_sinkA_io_task_bits_param),
+    .io_task_bits_size            (_sinkA_io_task_bits_size),
+    .io_task_bits_sourceId        (_sinkA_io_task_bits_sourceId),
+    .io_task_bits_corrupt         (_sinkA_io_task_bits_corrupt),
+    .io_task_bits_fromL2pft       (_sinkA_io_task_bits_fromL2pft),
+    .io_task_bits_needHint        (_sinkA_io_task_bits_needHint),
+    .io_task_bits_reqSource       (_sinkA_io_task_bits_reqSource)
+  );
+  SinkC sinkC (
+    .clock                                      (clock),
+    .reset                                      (reset),
+    .io_c_ready                                 (io_in_c_ready),
+    .io_c_valid                                 (io_in_c_valid),
+    .io_c_bits_opcode                           (io_in_c_bits_opcode),
+    .io_c_bits_param                            (io_in_c_bits_param),
+    .io_c_bits_size                             (io_in_c_bits_size),
+    .io_c_bits_source                           (io_in_c_bits_source),
+    .io_c_bits_address                          (io_in_c_bits_address),
+    .io_c_bits_data                             (io_in_c_bits_data),
+    .io_c_bits_corrupt                          (io_in_c_bits_corrupt),
+    .io_task_ready                              (_reqArb_io_sinkC_ready),
+    .io_task_valid                              (_sinkC_io_task_valid),
+    .io_task_bits_channel                       (_sinkC_io_task_bits_channel),
+    .io_task_bits_txChannel                     (_sinkC_io_task_bits_txChannel),
+    .io_task_bits_set                           (_sinkC_io_task_bits_set),
+    .io_task_bits_tag                           (_sinkC_io_task_bits_tag),
+    .io_task_bits_off                           (_sinkC_io_task_bits_off),
+    .io_task_bits_alias                         (_sinkC_io_task_bits_alias),
+    .io_task_bits_vaddr                         (_sinkC_io_task_bits_vaddr),
+    .io_task_bits_isKeyword                     (_sinkC_io_task_bits_isKeyword),
+    .io_task_bits_opcode                        (_sinkC_io_task_bits_opcode),
+    .io_task_bits_param                         (_sinkC_io_task_bits_param),
+    .io_task_bits_size                          (_sinkC_io_task_bits_size),
+    .io_task_bits_sourceId                      (_sinkC_io_task_bits_sourceId),
+    .io_task_bits_bufIdx                        (_sinkC_io_task_bits_bufIdx),
+    .io_task_bits_needProbeAckData              (_sinkC_io_task_bits_needProbeAckData),
+    .io_task_bits_denied                        (_sinkC_io_task_bits_denied),
+    .io_task_bits_corrupt                       (_sinkC_io_task_bits_corrupt),
+    .io_task_bits_mshrTask                      (_sinkC_io_task_bits_mshrTask),
+    .io_task_bits_mshrId                        (_sinkC_io_task_bits_mshrId),
+    .io_task_bits_aliasTask                     (_sinkC_io_task_bits_aliasTask),
+    .io_task_bits_useProbeData                  (_sinkC_io_task_bits_useProbeData),
+    .io_task_bits_mshrRetry                     (_sinkC_io_task_bits_mshrRetry),
+    .io_task_bits_readProbeDataDown             (_sinkC_io_task_bits_readProbeDataDown),
+    .io_task_bits_fromL2pft                     (_sinkC_io_task_bits_fromL2pft),
+    .io_task_bits_needHint                      (_sinkC_io_task_bits_needHint),
+    .io_task_bits_dirty                         (_sinkC_io_task_bits_dirty),
+    .io_task_bits_way                           (_sinkC_io_task_bits_way),
+    .io_task_bits_meta_dirty                    (_sinkC_io_task_bits_meta_dirty),
+    .io_task_bits_meta_state                    (_sinkC_io_task_bits_meta_state),
+    .io_task_bits_meta_clients                  (_sinkC_io_task_bits_meta_clients),
+    .io_task_bits_meta_alias                    (_sinkC_io_task_bits_meta_alias),
+    .io_task_bits_meta_prefetch                 (_sinkC_io_task_bits_meta_prefetch),
+    .io_task_bits_meta_prefetchSrc              (_sinkC_io_task_bits_meta_prefetchSrc),
+    .io_task_bits_meta_accessed                 (_sinkC_io_task_bits_meta_accessed),
+    .io_task_bits_meta_tagErr                   (_sinkC_io_task_bits_meta_tagErr),
+    .io_task_bits_meta_dataErr                  (_sinkC_io_task_bits_meta_dataErr),
+    .io_task_bits_metaWen                       (_sinkC_io_task_bits_metaWen),
+    .io_task_bits_tagWen                        (_sinkC_io_task_bits_tagWen),
+    .io_task_bits_dsWen                         (_sinkC_io_task_bits_dsWen),
+    .io_task_bits_wayMask                       (_sinkC_io_task_bits_wayMask),
+    .io_task_bits_replTask                      (_sinkC_io_task_bits_replTask),
+    .io_task_bits_cmoTask                       (_sinkC_io_task_bits_cmoTask),
+    .io_task_bits_cmoAll                        (_sinkC_io_task_bits_cmoAll),
+    .io_task_bits_reqSource                     (_sinkC_io_task_bits_reqSource),
+    .io_task_bits_mergeA                        (_sinkC_io_task_bits_mergeA),
+    .io_task_bits_aMergeTask_off                (_sinkC_io_task_bits_aMergeTask_off),
+    .io_task_bits_aMergeTask_alias              (_sinkC_io_task_bits_aMergeTask_alias),
+    .io_task_bits_aMergeTask_vaddr              (_sinkC_io_task_bits_aMergeTask_vaddr),
+    .io_task_bits_aMergeTask_isKeyword
+      (_sinkC_io_task_bits_aMergeTask_isKeyword),
+    .io_task_bits_aMergeTask_opcode             (_sinkC_io_task_bits_aMergeTask_opcode),
+    .io_task_bits_aMergeTask_param              (_sinkC_io_task_bits_aMergeTask_param),
+    .io_task_bits_aMergeTask_sourceId           (_sinkC_io_task_bits_aMergeTask_sourceId),
+    .io_task_bits_aMergeTask_meta_dirty
+      (_sinkC_io_task_bits_aMergeTask_meta_dirty),
+    .io_task_bits_aMergeTask_meta_state
+      (_sinkC_io_task_bits_aMergeTask_meta_state),
+    .io_task_bits_aMergeTask_meta_clients
+      (_sinkC_io_task_bits_aMergeTask_meta_clients),
+    .io_task_bits_aMergeTask_meta_alias
+      (_sinkC_io_task_bits_aMergeTask_meta_alias),
+    .io_task_bits_aMergeTask_meta_prefetch
+      (_sinkC_io_task_bits_aMergeTask_meta_prefetch),
+    .io_task_bits_aMergeTask_meta_prefetchSrc
+      (_sinkC_io_task_bits_aMergeTask_meta_prefetchSrc),
+    .io_task_bits_aMergeTask_meta_accessed
+      (_sinkC_io_task_bits_aMergeTask_meta_accessed),
+    .io_task_bits_aMergeTask_meta_tagErr
+      (_sinkC_io_task_bits_aMergeTask_meta_tagErr),
+    .io_task_bits_aMergeTask_meta_dataErr
+      (_sinkC_io_task_bits_aMergeTask_meta_dataErr),
+    .io_task_bits_snpHitRelease                 (_sinkC_io_task_bits_snpHitRelease),
+    .io_task_bits_snpHitReleaseToInval
+      (_sinkC_io_task_bits_snpHitReleaseToInval),
+    .io_task_bits_snpHitReleaseToClean
+      (_sinkC_io_task_bits_snpHitReleaseToClean),
+    .io_task_bits_snpHitReleaseWithData
+      (_sinkC_io_task_bits_snpHitReleaseWithData),
+    .io_task_bits_snpHitReleaseIdx              (_sinkC_io_task_bits_snpHitReleaseIdx),
+    .io_task_bits_snpHitReleaseMeta_dirty
+      (_sinkC_io_task_bits_snpHitReleaseMeta_dirty),
+    .io_task_bits_snpHitReleaseMeta_state
+      (_sinkC_io_task_bits_snpHitReleaseMeta_state),
+    .io_task_bits_snpHitReleaseMeta_clients
+      (_sinkC_io_task_bits_snpHitReleaseMeta_clients),
+    .io_task_bits_snpHitReleaseMeta_alias
+      (_sinkC_io_task_bits_snpHitReleaseMeta_alias),
+    .io_task_bits_snpHitReleaseMeta_prefetch
+      (_sinkC_io_task_bits_snpHitReleaseMeta_prefetch),
+    .io_task_bits_snpHitReleaseMeta_prefetchSrc
+      (_sinkC_io_task_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_task_bits_snpHitReleaseMeta_accessed
+      (_sinkC_io_task_bits_snpHitReleaseMeta_accessed),
+    .io_task_bits_snpHitReleaseMeta_tagErr
+      (_sinkC_io_task_bits_snpHitReleaseMeta_tagErr),
+    .io_task_bits_snpHitReleaseMeta_dataErr
+      (_sinkC_io_task_bits_snpHitReleaseMeta_dataErr),
+    .io_task_bits_tgtID                         (_sinkC_io_task_bits_tgtID),
+    .io_task_bits_srcID                         (_sinkC_io_task_bits_srcID),
+    .io_task_bits_txnID                         (_sinkC_io_task_bits_txnID),
+    .io_task_bits_homeNID                       (_sinkC_io_task_bits_homeNID),
+    .io_task_bits_dbID                          (_sinkC_io_task_bits_dbID),
+    .io_task_bits_fwdNID                        (_sinkC_io_task_bits_fwdNID),
+    .io_task_bits_fwdTxnID                      (_sinkC_io_task_bits_fwdTxnID),
+    .io_task_bits_chiOpcode                     (_sinkC_io_task_bits_chiOpcode),
+    .io_task_bits_resp                          (_sinkC_io_task_bits_resp),
+    .io_task_bits_fwdState                      (_sinkC_io_task_bits_fwdState),
+    .io_task_bits_pCrdType                      (_sinkC_io_task_bits_pCrdType),
+    .io_task_bits_retToSrc                      (_sinkC_io_task_bits_retToSrc),
+    .io_task_bits_likelyshared                  (_sinkC_io_task_bits_likelyshared),
+    .io_task_bits_expCompAck                    (_sinkC_io_task_bits_expCompAck),
+    .io_task_bits_allowRetry                    (_sinkC_io_task_bits_allowRetry),
+    .io_task_bits_memAttr_allocate              (_sinkC_io_task_bits_memAttr_allocate),
+    .io_task_bits_memAttr_cacheable             (_sinkC_io_task_bits_memAttr_cacheable),
+    .io_task_bits_memAttr_device                (_sinkC_io_task_bits_memAttr_device),
+    .io_task_bits_memAttr_ewa                   (_sinkC_io_task_bits_memAttr_ewa),
+    .io_task_bits_traceTag                      (_sinkC_io_task_bits_traceTag),
+    .io_resp_valid                              (_sinkC_io_resp_valid),
+    .io_resp_set                                (_sinkC_io_resp_set),
+    .io_resp_tag                                (_sinkC_io_resp_tag),
+    .io_resp_respInfo_opcode                    (_sinkC_io_resp_respInfo_opcode),
+    .io_resp_respInfo_param                     (_sinkC_io_resp_respInfo_param),
+    .io_resp_respInfo_last                      (_sinkC_io_resp_respInfo_last),
+    .io_resp_respInfo_denied                    (_sinkC_io_resp_respInfo_denied),
+    .io_resp_respInfo_corrupt                   (_sinkC_io_resp_respInfo_corrupt),
+    .io_releaseBufWrite_valid                   (_sinkC_io_releaseBufWrite_valid),
+    .io_releaseBufWrite_bits_data_data
+      (_sinkC_io_releaseBufWrite_bits_data_data),
+    .io_bufResp_data_0                          (_sinkC_io_bufResp_data_0),
+    .io_bufResp_data_1                          (_sinkC_io_bufResp_data_1),
+    .io_refillBufWrite_valid                    (_sinkC_io_refillBufWrite_valid),
+    .io_refillBufWrite_bits_id                  (_sinkC_io_refillBufWrite_bits_id),
+    .io_refillBufWrite_bits_data_data           (_sinkC_io_refillBufWrite_bits_data_data),
+    .io_msInfo_0_valid                          (_mshrCtl_io_msInfo_0_valid),
+    .io_msInfo_0_bits_set                       (_mshrCtl_io_msInfo_0_bits_set),
+    .io_msInfo_0_bits_reqTag                    (_mshrCtl_io_msInfo_0_bits_reqTag),
+    .io_msInfo_0_bits_blockRefill               (_mshrCtl_io_msInfo_0_bits_blockRefill),
+    .io_msInfo_1_valid                          (_mshrCtl_io_msInfo_1_valid),
+    .io_msInfo_1_bits_set                       (_mshrCtl_io_msInfo_1_bits_set),
+    .io_msInfo_1_bits_reqTag                    (_mshrCtl_io_msInfo_1_bits_reqTag),
+    .io_msInfo_1_bits_blockRefill               (_mshrCtl_io_msInfo_1_bits_blockRefill),
+    .io_msInfo_2_valid                          (_mshrCtl_io_msInfo_2_valid),
+    .io_msInfo_2_bits_set                       (_mshrCtl_io_msInfo_2_bits_set),
+    .io_msInfo_2_bits_reqTag                    (_mshrCtl_io_msInfo_2_bits_reqTag),
+    .io_msInfo_2_bits_blockRefill               (_mshrCtl_io_msInfo_2_bits_blockRefill),
+    .io_msInfo_3_valid                          (_mshrCtl_io_msInfo_3_valid),
+    .io_msInfo_3_bits_set                       (_mshrCtl_io_msInfo_3_bits_set),
+    .io_msInfo_3_bits_reqTag                    (_mshrCtl_io_msInfo_3_bits_reqTag),
+    .io_msInfo_3_bits_blockRefill               (_mshrCtl_io_msInfo_3_bits_blockRefill),
+    .io_msInfo_4_valid                          (_mshrCtl_io_msInfo_4_valid),
+    .io_msInfo_4_bits_set                       (_mshrCtl_io_msInfo_4_bits_set),
+    .io_msInfo_4_bits_reqTag                    (_mshrCtl_io_msInfo_4_bits_reqTag),
+    .io_msInfo_4_bits_blockRefill               (_mshrCtl_io_msInfo_4_bits_blockRefill),
+    .io_msInfo_5_valid                          (_mshrCtl_io_msInfo_5_valid),
+    .io_msInfo_5_bits_set                       (_mshrCtl_io_msInfo_5_bits_set),
+    .io_msInfo_5_bits_reqTag                    (_mshrCtl_io_msInfo_5_bits_reqTag),
+    .io_msInfo_5_bits_blockRefill               (_mshrCtl_io_msInfo_5_bits_blockRefill),
+    .io_msInfo_6_valid                          (_mshrCtl_io_msInfo_6_valid),
+    .io_msInfo_6_bits_set                       (_mshrCtl_io_msInfo_6_bits_set),
+    .io_msInfo_6_bits_reqTag                    (_mshrCtl_io_msInfo_6_bits_reqTag),
+    .io_msInfo_6_bits_blockRefill               (_mshrCtl_io_msInfo_6_bits_blockRefill),
+    .io_msInfo_7_valid                          (_mshrCtl_io_msInfo_7_valid),
+    .io_msInfo_7_bits_set                       (_mshrCtl_io_msInfo_7_bits_set),
+    .io_msInfo_7_bits_reqTag                    (_mshrCtl_io_msInfo_7_bits_reqTag),
+    .io_msInfo_7_bits_blockRefill               (_mshrCtl_io_msInfo_7_bits_blockRefill),
+    .io_msInfo_8_valid                          (_mshrCtl_io_msInfo_8_valid),
+    .io_msInfo_8_bits_set                       (_mshrCtl_io_msInfo_8_bits_set),
+    .io_msInfo_8_bits_reqTag                    (_mshrCtl_io_msInfo_8_bits_reqTag),
+    .io_msInfo_8_bits_blockRefill               (_mshrCtl_io_msInfo_8_bits_blockRefill),
+    .io_msInfo_9_valid                          (_mshrCtl_io_msInfo_9_valid),
+    .io_msInfo_9_bits_set                       (_mshrCtl_io_msInfo_9_bits_set),
+    .io_msInfo_9_bits_reqTag                    (_mshrCtl_io_msInfo_9_bits_reqTag),
+    .io_msInfo_9_bits_blockRefill               (_mshrCtl_io_msInfo_9_bits_blockRefill),
+    .io_msInfo_10_valid                         (_mshrCtl_io_msInfo_10_valid),
+    .io_msInfo_10_bits_set                      (_mshrCtl_io_msInfo_10_bits_set),
+    .io_msInfo_10_bits_reqTag                   (_mshrCtl_io_msInfo_10_bits_reqTag),
+    .io_msInfo_10_bits_blockRefill              (_mshrCtl_io_msInfo_10_bits_blockRefill),
+    .io_msInfo_11_valid                         (_mshrCtl_io_msInfo_11_valid),
+    .io_msInfo_11_bits_set                      (_mshrCtl_io_msInfo_11_bits_set),
+    .io_msInfo_11_bits_reqTag                   (_mshrCtl_io_msInfo_11_bits_reqTag),
+    .io_msInfo_11_bits_blockRefill              (_mshrCtl_io_msInfo_11_bits_blockRefill),
+    .io_msInfo_12_valid                         (_mshrCtl_io_msInfo_12_valid),
+    .io_msInfo_12_bits_set                      (_mshrCtl_io_msInfo_12_bits_set),
+    .io_msInfo_12_bits_reqTag                   (_mshrCtl_io_msInfo_12_bits_reqTag),
+    .io_msInfo_12_bits_blockRefill              (_mshrCtl_io_msInfo_12_bits_blockRefill),
+    .io_msInfo_13_valid                         (_mshrCtl_io_msInfo_13_valid),
+    .io_msInfo_13_bits_set                      (_mshrCtl_io_msInfo_13_bits_set),
+    .io_msInfo_13_bits_reqTag                   (_mshrCtl_io_msInfo_13_bits_reqTag),
+    .io_msInfo_13_bits_blockRefill              (_mshrCtl_io_msInfo_13_bits_blockRefill),
+    .io_msInfo_14_valid                         (_mshrCtl_io_msInfo_14_valid),
+    .io_msInfo_14_bits_set                      (_mshrCtl_io_msInfo_14_bits_set),
+    .io_msInfo_14_bits_reqTag                   (_mshrCtl_io_msInfo_14_bits_reqTag),
+    .io_msInfo_14_bits_blockRefill              (_mshrCtl_io_msInfo_14_bits_blockRefill),
+    .io_msInfo_15_valid                         (_mshrCtl_io_msInfo_15_valid),
+    .io_msInfo_15_bits_set                      (_mshrCtl_io_msInfo_15_bits_set),
+    .io_msInfo_15_bits_reqTag                   (_mshrCtl_io_msInfo_15_bits_reqTag),
+    .io_msInfo_15_bits_blockRefill              (_mshrCtl_io_msInfo_15_bits_blockRefill)
+  );
+  GrantBuffer grantBuf (
+    .clock                                             (clock),
+    .reset                                             (reset),
+    .io_d_task_valid                                   (_mainPipe_io_toSourceD_valid),
+    .io_d_task_bits_task_channel
+      (_mainPipe_io_toSourceD_bits_task_channel),
+    .io_d_task_bits_task_txChannel
+      (_mainPipe_io_toSourceD_bits_task_txChannel),
+    .io_d_task_bits_task_set
+      (_mainPipe_io_toSourceD_bits_task_set),
+    .io_d_task_bits_task_tag
+      (_mainPipe_io_toSourceD_bits_task_tag),
+    .io_d_task_bits_task_off
+      (_mainPipe_io_toSourceD_bits_task_off),
+    .io_d_task_bits_task_alias
+      (_mainPipe_io_toSourceD_bits_task_alias),
+    .io_d_task_bits_task_vaddr
+      (_mainPipe_io_toSourceD_bits_task_vaddr),
+    .io_d_task_bits_task_isKeyword
+      (_mainPipe_io_toSourceD_bits_task_isKeyword),
+    .io_d_task_bits_task_opcode
+      (_mainPipe_io_toSourceD_bits_task_opcode),
+    .io_d_task_bits_task_param
+      (_mainPipe_io_toSourceD_bits_task_param),
+    .io_d_task_bits_task_size
+      (_mainPipe_io_toSourceD_bits_task_size),
+    .io_d_task_bits_task_sourceId
+      (_mainPipe_io_toSourceD_bits_task_sourceId),
+    .io_d_task_bits_task_bufIdx
+      (_mainPipe_io_toSourceD_bits_task_bufIdx),
+    .io_d_task_bits_task_needProbeAckData
+      (_mainPipe_io_toSourceD_bits_task_needProbeAckData),
+    .io_d_task_bits_task_denied
+      (_mainPipe_io_toSourceD_bits_task_denied),
+    .io_d_task_bits_task_corrupt
+      (_mainPipe_io_toSourceD_bits_task_corrupt),
+    .io_d_task_bits_task_mshrTask
+      (_mainPipe_io_toSourceD_bits_task_mshrTask),
+    .io_d_task_bits_task_mshrId
+      (_mainPipe_io_toSourceD_bits_task_mshrId),
+    .io_d_task_bits_task_aliasTask
+      (_mainPipe_io_toSourceD_bits_task_aliasTask),
+    .io_d_task_bits_task_useProbeData
+      (_mainPipe_io_toSourceD_bits_task_useProbeData),
+    .io_d_task_bits_task_mshrRetry
+      (_mainPipe_io_toSourceD_bits_task_mshrRetry),
+    .io_d_task_bits_task_readProbeDataDown
+      (_mainPipe_io_toSourceD_bits_task_readProbeDataDown),
+    .io_d_task_bits_task_fromL2pft
+      (_mainPipe_io_toSourceD_bits_task_fromL2pft),
+    .io_d_task_bits_task_needHint
+      (_mainPipe_io_toSourceD_bits_task_needHint),
+    .io_d_task_bits_task_dirty
+      (_mainPipe_io_toSourceD_bits_task_dirty),
+    .io_d_task_bits_task_way
+      (_mainPipe_io_toSourceD_bits_task_way),
+    .io_d_task_bits_task_meta_dirty
+      (_mainPipe_io_toSourceD_bits_task_meta_dirty),
+    .io_d_task_bits_task_meta_state
+      (_mainPipe_io_toSourceD_bits_task_meta_state),
+    .io_d_task_bits_task_meta_clients
+      (_mainPipe_io_toSourceD_bits_task_meta_clients),
+    .io_d_task_bits_task_meta_alias
+      (_mainPipe_io_toSourceD_bits_task_meta_alias),
+    .io_d_task_bits_task_meta_prefetch
+      (_mainPipe_io_toSourceD_bits_task_meta_prefetch),
+    .io_d_task_bits_task_meta_prefetchSrc
+      (_mainPipe_io_toSourceD_bits_task_meta_prefetchSrc),
+    .io_d_task_bits_task_meta_accessed
+      (_mainPipe_io_toSourceD_bits_task_meta_accessed),
+    .io_d_task_bits_task_meta_tagErr
+      (_mainPipe_io_toSourceD_bits_task_meta_tagErr),
+    .io_d_task_bits_task_meta_dataErr
+      (_mainPipe_io_toSourceD_bits_task_meta_dataErr),
+    .io_d_task_bits_task_metaWen
+      (_mainPipe_io_toSourceD_bits_task_metaWen),
+    .io_d_task_bits_task_tagWen
+      (_mainPipe_io_toSourceD_bits_task_tagWen),
+    .io_d_task_bits_task_dsWen
+      (_mainPipe_io_toSourceD_bits_task_dsWen),
+    .io_d_task_bits_task_wayMask
+      (_mainPipe_io_toSourceD_bits_task_wayMask),
+    .io_d_task_bits_task_replTask
+      (_mainPipe_io_toSourceD_bits_task_replTask),
+    .io_d_task_bits_task_cmoTask
+      (_mainPipe_io_toSourceD_bits_task_cmoTask),
+    .io_d_task_bits_task_cmoAll
+      (_mainPipe_io_toSourceD_bits_task_cmoAll),
+    .io_d_task_bits_task_reqSource
+      (_mainPipe_io_toSourceD_bits_task_reqSource),
+    .io_d_task_bits_task_mergeA
+      (_mainPipe_io_toSourceD_bits_task_mergeA),
+    .io_d_task_bits_task_aMergeTask_off
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_off),
+    .io_d_task_bits_task_aMergeTask_alias
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_alias),
+    .io_d_task_bits_task_aMergeTask_vaddr
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_vaddr),
+    .io_d_task_bits_task_aMergeTask_isKeyword
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_isKeyword),
+    .io_d_task_bits_task_aMergeTask_opcode
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_opcode),
+    .io_d_task_bits_task_aMergeTask_param
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_param),
+    .io_d_task_bits_task_aMergeTask_sourceId
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_sourceId),
+    .io_d_task_bits_task_aMergeTask_meta_dirty
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_dirty),
+    .io_d_task_bits_task_aMergeTask_meta_state
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_state),
+    .io_d_task_bits_task_aMergeTask_meta_clients
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_clients),
+    .io_d_task_bits_task_aMergeTask_meta_alias
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_alias),
+    .io_d_task_bits_task_aMergeTask_meta_prefetch
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_prefetch),
+    .io_d_task_bits_task_aMergeTask_meta_prefetchSrc
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_prefetchSrc),
+    .io_d_task_bits_task_aMergeTask_meta_accessed
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_accessed),
+    .io_d_task_bits_task_aMergeTask_meta_tagErr
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_tagErr),
+    .io_d_task_bits_task_aMergeTask_meta_dataErr
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_dataErr),
+    .io_d_task_bits_task_snpHitRelease
+      (_mainPipe_io_toSourceD_bits_task_snpHitRelease),
+    .io_d_task_bits_task_snpHitReleaseToInval
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseToInval),
+    .io_d_task_bits_task_snpHitReleaseToClean
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseToClean),
+    .io_d_task_bits_task_snpHitReleaseWithData
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseWithData),
+    .io_d_task_bits_task_snpHitReleaseIdx
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseIdx),
+    .io_d_task_bits_task_snpHitReleaseMeta_dirty
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_dirty),
+    .io_d_task_bits_task_snpHitReleaseMeta_state
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_state),
+    .io_d_task_bits_task_snpHitReleaseMeta_clients
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_clients),
+    .io_d_task_bits_task_snpHitReleaseMeta_alias
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_alias),
+    .io_d_task_bits_task_snpHitReleaseMeta_prefetch
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_prefetch),
+    .io_d_task_bits_task_snpHitReleaseMeta_prefetchSrc
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_d_task_bits_task_snpHitReleaseMeta_accessed
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_accessed),
+    .io_d_task_bits_task_snpHitReleaseMeta_tagErr
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_tagErr),
+    .io_d_task_bits_task_snpHitReleaseMeta_dataErr
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_dataErr),
+    .io_d_task_bits_task_tgtID
+      (_mainPipe_io_toSourceD_bits_task_tgtID),
+    .io_d_task_bits_task_srcID
+      (_mainPipe_io_toSourceD_bits_task_srcID),
+    .io_d_task_bits_task_txnID
+      (_mainPipe_io_toSourceD_bits_task_txnID),
+    .io_d_task_bits_task_homeNID
+      (_mainPipe_io_toSourceD_bits_task_homeNID),
+    .io_d_task_bits_task_dbID
+      (_mainPipe_io_toSourceD_bits_task_dbID),
+    .io_d_task_bits_task_fwdNID
+      (_mainPipe_io_toSourceD_bits_task_fwdNID),
+    .io_d_task_bits_task_fwdTxnID
+      (_mainPipe_io_toSourceD_bits_task_fwdTxnID),
+    .io_d_task_bits_task_chiOpcode
+      (_mainPipe_io_toSourceD_bits_task_chiOpcode),
+    .io_d_task_bits_task_resp
+      (_mainPipe_io_toSourceD_bits_task_resp),
+    .io_d_task_bits_task_fwdState
+      (_mainPipe_io_toSourceD_bits_task_fwdState),
+    .io_d_task_bits_task_pCrdType
+      (_mainPipe_io_toSourceD_bits_task_pCrdType),
+    .io_d_task_bits_task_retToSrc
+      (_mainPipe_io_toSourceD_bits_task_retToSrc),
+    .io_d_task_bits_task_likelyshared
+      (_mainPipe_io_toSourceD_bits_task_likelyshared),
+    .io_d_task_bits_task_expCompAck
+      (_mainPipe_io_toSourceD_bits_task_expCompAck),
+    .io_d_task_bits_task_allowRetry
+      (_mainPipe_io_toSourceD_bits_task_allowRetry),
+    .io_d_task_bits_task_memAttr_allocate
+      (_mainPipe_io_toSourceD_bits_task_memAttr_allocate),
+    .io_d_task_bits_task_memAttr_cacheable
+      (_mainPipe_io_toSourceD_bits_task_memAttr_cacheable),
+    .io_d_task_bits_task_memAttr_device
+      (_mainPipe_io_toSourceD_bits_task_memAttr_device),
+    .io_d_task_bits_task_memAttr_ewa
+      (_mainPipe_io_toSourceD_bits_task_memAttr_ewa),
+    .io_d_task_bits_task_traceTag
+      (_mainPipe_io_toSourceD_bits_task_traceTag),
+    .io_d_task_bits_data_data
+      (_mainPipe_io_toSourceD_bits_data_data),
+    .io_d_ready                                        (io_in_d_ready),
+    .io_d_valid                                        (io_in_d_valid),
+    .io_d_bits_opcode                                  (io_in_d_bits_opcode),
+    .io_d_bits_param                                   (io_in_d_bits_param),
+    .io_d_bits_source                                  (io_in_d_bits_source),
+    .io_d_bits_sink                                    (io_in_d_bits_sink),
+    .io_d_bits_denied                                  (io_in_d_bits_denied),
+    .io_d_bits_echo_isKeyword                          (io_in_d_bits_echo_isKeyword),
+    .io_d_bits_data                                    (io_in_d_bits_data),
+    .io_d_bits_corrupt                                 (io_in_d_bits_corrupt),
+    .io_e_valid                                        (io_in_e_valid),
+    .io_e_bits_sink                                    (io_in_e_bits_sink),
+    .io_fromReqArb_status_s1_tags_1                    (_reqArb_io_status_s1_tags_1),
+    .io_fromReqArb_status_s1_sets_1                    (_reqArb_io_status_s1_sets_1),
+    .io_pipeStatusVec_1_valid                          (_reqArb_io_status_vec_1_valid),
+    .io_pipeStatusVec_1_bits_channel
+      (_reqArb_io_status_vec_1_bits_channel),
+    .io_pipeStatusVec_2_valid
+      (_mainPipe_io_status_vec_toD_0_valid),
+    .io_pipeStatusVec_2_bits_channel
+      (_mainPipe_io_status_vec_toD_0_bits_channel),
+    .io_pipeStatusVec_3_valid
+      (_mainPipe_io_status_vec_toD_1_valid),
+    .io_pipeStatusVec_3_bits_channel
+      (_mainPipe_io_status_vec_toD_1_bits_channel),
+    .io_pipeStatusVec_4_valid
+      (_mainPipe_io_status_vec_toD_2_valid),
+    .io_pipeStatusVec_4_bits_channel
+      (_mainPipe_io_status_vec_toD_2_bits_channel),
+    .io_toReqArb_blockSinkReqEntrance_blockA_s1
+      (_grantBuf_io_toReqArb_blockSinkReqEntrance_blockA_s1),
+    .io_toReqArb_blockSinkReqEntrance_blockB_s1
+      (_grantBuf_io_toReqArb_blockSinkReqEntrance_blockB_s1),
+    .io_toReqArb_blockSinkReqEntrance_blockC_s1
+      (_grantBuf_io_toReqArb_blockSinkReqEntrance_blockC_s1),
+    .io_toReqArb_blockMSHRReqEntrance
+      (_grantBuf_io_toReqArb_blockMSHRReqEntrance),
+    .io_prefetchResp_ready                             (io_prefetch_resp_ready),
+    .io_prefetchResp_valid                             (io_prefetch_resp_valid),
+    .io_grantStatus_0_valid                            (_grantBuf_io_grantStatus_0_valid),
+    .io_grantStatus_0_set                              (_grantBuf_io_grantStatus_0_set),
+    .io_grantStatus_0_tag                              (_grantBuf_io_grantStatus_0_tag),
+    .io_grantStatus_1_valid                            (_grantBuf_io_grantStatus_1_valid),
+    .io_grantStatus_1_set                              (_grantBuf_io_grantStatus_1_set),
+    .io_grantStatus_1_tag                              (_grantBuf_io_grantStatus_1_tag),
+    .io_grantStatus_2_valid                            (_grantBuf_io_grantStatus_2_valid),
+    .io_grantStatus_2_set                              (_grantBuf_io_grantStatus_2_set),
+    .io_grantStatus_2_tag                              (_grantBuf_io_grantStatus_2_tag),
+    .io_grantStatus_3_valid                            (_grantBuf_io_grantStatus_3_valid),
+    .io_grantStatus_3_set                              (_grantBuf_io_grantStatus_3_set),
+    .io_grantStatus_3_tag                              (_grantBuf_io_grantStatus_3_tag),
+    .io_grantStatus_4_valid                            (_grantBuf_io_grantStatus_4_valid),
+    .io_grantStatus_4_set                              (_grantBuf_io_grantStatus_4_set),
+    .io_grantStatus_4_tag                              (_grantBuf_io_grantStatus_4_tag),
+    .io_grantStatus_5_valid                            (_grantBuf_io_grantStatus_5_valid),
+    .io_grantStatus_5_set                              (_grantBuf_io_grantStatus_5_set),
+    .io_grantStatus_5_tag                              (_grantBuf_io_grantStatus_5_tag),
+    .io_grantStatus_6_valid                            (_grantBuf_io_grantStatus_6_valid),
+    .io_grantStatus_6_set                              (_grantBuf_io_grantStatus_6_set),
+    .io_grantStatus_6_tag                              (_grantBuf_io_grantStatus_6_tag),
+    .io_grantStatus_7_valid                            (_grantBuf_io_grantStatus_7_valid),
+    .io_grantStatus_7_set                              (_grantBuf_io_grantStatus_7_set),
+    .io_grantStatus_7_tag                              (_grantBuf_io_grantStatus_7_tag),
+    .io_grantStatus_8_valid                            (_grantBuf_io_grantStatus_8_valid),
+    .io_grantStatus_8_set                              (_grantBuf_io_grantStatus_8_set),
+    .io_grantStatus_8_tag                              (_grantBuf_io_grantStatus_8_tag),
+    .io_grantStatus_9_valid                            (_grantBuf_io_grantStatus_9_valid),
+    .io_grantStatus_9_set                              (_grantBuf_io_grantStatus_9_set),
+    .io_grantStatus_9_tag                              (_grantBuf_io_grantStatus_9_tag),
+    .io_grantStatus_10_valid
+      (_grantBuf_io_grantStatus_10_valid),
+    .io_grantStatus_10_set                             (_grantBuf_io_grantStatus_10_set),
+    .io_grantStatus_10_tag                             (_grantBuf_io_grantStatus_10_tag),
+    .io_grantStatus_11_valid
+      (_grantBuf_io_grantStatus_11_valid),
+    .io_grantStatus_11_set                             (_grantBuf_io_grantStatus_11_set),
+    .io_grantStatus_11_tag                             (_grantBuf_io_grantStatus_11_tag),
+    .io_grantStatus_12_valid
+      (_grantBuf_io_grantStatus_12_valid),
+    .io_grantStatus_12_set                             (_grantBuf_io_grantStatus_12_set),
+    .io_grantStatus_12_tag                             (_grantBuf_io_grantStatus_12_tag),
+    .io_grantStatus_13_valid
+      (_grantBuf_io_grantStatus_13_valid),
+    .io_grantStatus_13_set                             (_grantBuf_io_grantStatus_13_set),
+    .io_grantStatus_13_tag                             (_grantBuf_io_grantStatus_13_tag),
+    .io_grantStatus_14_valid
+      (_grantBuf_io_grantStatus_14_valid),
+    .io_grantStatus_14_set                             (_grantBuf_io_grantStatus_14_set),
+    .io_grantStatus_14_tag                             (_grantBuf_io_grantStatus_14_tag),
+    .io_grantStatus_15_valid
+      (_grantBuf_io_grantStatus_15_valid),
+    .io_grantStatus_15_set                             (_grantBuf_io_grantStatus_15_set),
+    .io_grantStatus_15_tag                             (_grantBuf_io_grantStatus_15_tag)
+  );
+  TXREQ txreq (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_pipeReq_valid                  (_mainPipe_io_toTXREQ_valid),
+    .io_pipeReq_bits_tgtID             (_mainPipe_io_toTXREQ_bits_tgtID),
+    .io_pipeReq_bits_srcID             (_mainPipe_io_toTXREQ_bits_srcID),
+    .io_pipeReq_bits_txnID             (_mainPipe_io_toTXREQ_bits_txnID),
+    .io_pipeReq_bits_opcode            (_mainPipe_io_toTXREQ_bits_opcode),
+    .io_pipeReq_bits_addr              (_mainPipe_io_toTXREQ_bits_addr),
+    .io_pipeReq_bits_likelyshared      (_mainPipe_io_toTXREQ_bits_likelyshared),
+    .io_pipeReq_bits_allowRetry        (_mainPipe_io_toTXREQ_bits_allowRetry),
+    .io_pipeReq_bits_pCrdType          (_mainPipe_io_toTXREQ_bits_pCrdType),
+    .io_pipeReq_bits_memAttr_allocate  (_mainPipe_io_toTXREQ_bits_memAttr_allocate),
+    .io_pipeReq_bits_memAttr_cacheable (_mainPipe_io_toTXREQ_bits_memAttr_cacheable),
+    .io_pipeReq_bits_memAttr_device    (_mainPipe_io_toTXREQ_bits_memAttr_device),
+    .io_pipeReq_bits_memAttr_ewa       (_mainPipe_io_toTXREQ_bits_memAttr_ewa),
+    .io_pipeReq_bits_expCompAck        (_mainPipe_io_toTXREQ_bits_expCompAck),
+    .io_mshrReq_ready                  (_txreq_io_mshrReq_ready),
+    .io_mshrReq_valid                  (_mshrCtl_io_toTXREQ_valid),
+    .io_mshrReq_bits_qos               (_mshrCtl_io_toTXREQ_bits_qos),
+    .io_mshrReq_bits_tgtID             (_mshrCtl_io_toTXREQ_bits_tgtID),
+    .io_mshrReq_bits_txnID             (_mshrCtl_io_toTXREQ_bits_txnID),
+    .io_mshrReq_bits_opcode            (_mshrCtl_io_toTXREQ_bits_opcode),
+    .io_mshrReq_bits_size              (_mshrCtl_io_toTXREQ_bits_size),
+    .io_mshrReq_bits_addr              (_mshrCtl_io_toTXREQ_bits_addr),
+    .io_mshrReq_bits_likelyshared      (_mshrCtl_io_toTXREQ_bits_likelyshared),
+    .io_mshrReq_bits_allowRetry        (_mshrCtl_io_toTXREQ_bits_allowRetry),
+    .io_mshrReq_bits_order             (_mshrCtl_io_toTXREQ_bits_order),
+    .io_mshrReq_bits_pCrdType          (_mshrCtl_io_toTXREQ_bits_pCrdType),
+    .io_mshrReq_bits_memAttr_allocate  (_mshrCtl_io_toTXREQ_bits_memAttr_allocate),
+    .io_mshrReq_bits_memAttr_cacheable (_mshrCtl_io_toTXREQ_bits_memAttr_cacheable),
+    .io_mshrReq_bits_memAttr_device    (_mshrCtl_io_toTXREQ_bits_memAttr_device),
+    .io_mshrReq_bits_memAttr_ewa       (_mshrCtl_io_toTXREQ_bits_memAttr_ewa),
+    .io_mshrReq_bits_snpAttr           (_mshrCtl_io_toTXREQ_bits_snpAttr),
+    .io_mshrReq_bits_expCompAck        (_mshrCtl_io_toTXREQ_bits_expCompAck),
+    .io_out_ready                      (io_out_tx_req_ready),
+    .io_out_valid                      (io_out_tx_req_valid),
+    .io_out_bits_qos                   (io_out_tx_req_bits_qos),
+    .io_out_bits_srcID                 (io_out_tx_req_bits_srcID),
+    .io_out_bits_txnID                 (io_out_tx_req_bits_txnID),
+    .io_out_bits_returnNID             (io_out_tx_req_bits_returnNID),
+    .io_out_bits_stashNIDValid         (io_out_tx_req_bits_stashNIDValid),
+    .io_out_bits_returnTxnID           (io_out_tx_req_bits_returnTxnID),
+    .io_out_bits_opcode                (io_out_tx_req_bits_opcode),
+    .io_out_bits_addr                  (io_out_tx_req_bits_addr),
+    .io_out_bits_ns                    (io_out_tx_req_bits_ns),
+    .io_out_bits_likelyshared          (io_out_tx_req_bits_likelyshared),
+    .io_out_bits_allowRetry            (io_out_tx_req_bits_allowRetry),
+    .io_out_bits_order                 (io_out_tx_req_bits_order),
+    .io_out_bits_pCrdType              (io_out_tx_req_bits_pCrdType),
+    .io_out_bits_memAttr_allocate      (io_out_tx_req_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable     (io_out_tx_req_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device        (io_out_tx_req_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa           (io_out_tx_req_bits_memAttr_ewa),
+    .io_out_bits_snpAttr               (io_out_tx_req_bits_snpAttr),
+    .io_out_bits_lpIDWithPadding       (io_out_tx_req_bits_lpIDWithPadding),
+    .io_out_bits_snoopMe               (io_out_tx_req_bits_snoopMe),
+    .io_out_bits_expCompAck            (io_out_tx_req_bits_expCompAck),
+    .io_out_bits_tagOp                 (io_out_tx_req_bits_tagOp),
+    .io_out_bits_traceTag              (io_out_tx_req_bits_traceTag),
+    .io_out_bits_mpam_perfMonGroup     (io_out_tx_req_bits_mpam_perfMonGroup),
+    .io_out_bits_mpam_partID           (io_out_tx_req_bits_mpam_partID),
+    .io_out_bits_mpam_mpamNS           (io_out_tx_req_bits_mpam_mpamNS),
+    .io_out_bits_rsvdc                 (io_out_tx_req_bits_rsvdc),
+    .io_pipeStatusVec_1_valid          (_reqArb_io_status_vec_toTX_1_valid),
+    .io_pipeStatusVec_1_bits_txChannel (_reqArb_io_status_vec_toTX_1_bits_txChannel),
+    .io_pipeStatusVec_1_bits_mshrTask  (_reqArb_io_status_vec_toTX_1_bits_mshrTask),
+    .io_pipeStatusVec_2_valid          (_mainPipe_io_status_vec_toTX_0_valid),
+    .io_pipeStatusVec_2_bits_txChannel (_mainPipe_io_status_vec_toTX_0_bits_txChannel),
+    .io_pipeStatusVec_2_bits_mshrTask  (_mainPipe_io_status_vec_toTX_0_bits_mshrTask),
+    .io_pipeStatusVec_3_valid          (_mainPipe_io_status_vec_toTX_1_valid),
+    .io_pipeStatusVec_3_bits_txChannel (_mainPipe_io_status_vec_toTX_1_bits_txChannel),
+    .io_pipeStatusVec_3_bits_mshrTask  (_mainPipe_io_status_vec_toTX_1_bits_mshrTask),
+    .io_pipeStatusVec_4_valid          (_mainPipe_io_status_vec_toTX_2_valid),
+    .io_pipeStatusVec_4_bits_txChannel (_mainPipe_io_status_vec_toTX_2_bits_txChannel),
+    .io_pipeStatusVec_4_bits_mshrTask  (_mainPipe_io_status_vec_toTX_2_bits_mshrTask),
+    .io_toReqArb_blockMSHRReqEntrance  (_txreq_io_toReqArb_blockMSHRReqEntrance)
+  );
+  TXDAT txdat (
+    .clock                                         (clock),
+    .reset                                         (reset),
+    .io_in_ready                                   (_txdat_io_in_ready),
+    .io_in_valid                                   (_mainPipe_io_toTXDAT_valid),
+    .io_in_bits_task_channel
+      (_mainPipe_io_toTXDAT_bits_task_channel),
+    .io_in_bits_task_txChannel
+      (_mainPipe_io_toTXDAT_bits_task_txChannel),
+    .io_in_bits_task_set                           (_mainPipe_io_toTXDAT_bits_task_set),
+    .io_in_bits_task_tag                           (_mainPipe_io_toTXDAT_bits_task_tag),
+    .io_in_bits_task_off                           (_mainPipe_io_toTXDAT_bits_task_off),
+    .io_in_bits_task_alias                         (_mainPipe_io_toTXDAT_bits_task_alias),
+    .io_in_bits_task_vaddr                         (_mainPipe_io_toTXDAT_bits_task_vaddr),
+    .io_in_bits_task_isKeyword
+      (_mainPipe_io_toTXDAT_bits_task_isKeyword),
+    .io_in_bits_task_opcode
+      (_mainPipe_io_toTXDAT_bits_task_opcode),
+    .io_in_bits_task_param                         (_mainPipe_io_toTXDAT_bits_task_param),
+    .io_in_bits_task_size                          (_mainPipe_io_toTXDAT_bits_task_size),
+    .io_in_bits_task_sourceId
+      (_mainPipe_io_toTXDAT_bits_task_sourceId),
+    .io_in_bits_task_bufIdx
+      (_mainPipe_io_toTXDAT_bits_task_bufIdx),
+    .io_in_bits_task_needProbeAckData
+      (_mainPipe_io_toTXDAT_bits_task_needProbeAckData),
+    .io_in_bits_task_denied
+      (_mainPipe_io_toTXDAT_bits_task_denied),
+    .io_in_bits_task_corrupt
+      (_mainPipe_io_toTXDAT_bits_task_corrupt),
+    .io_in_bits_task_mshrTask
+      (_mainPipe_io_toTXDAT_bits_task_mshrTask),
+    .io_in_bits_task_mshrId
+      (_mainPipe_io_toTXDAT_bits_task_mshrId),
+    .io_in_bits_task_aliasTask
+      (_mainPipe_io_toTXDAT_bits_task_aliasTask),
+    .io_in_bits_task_useProbeData
+      (_mainPipe_io_toTXDAT_bits_task_useProbeData),
+    .io_in_bits_task_mshrRetry
+      (_mainPipe_io_toTXDAT_bits_task_mshrRetry),
+    .io_in_bits_task_readProbeDataDown
+      (_mainPipe_io_toTXDAT_bits_task_readProbeDataDown),
+    .io_in_bits_task_fromL2pft
+      (_mainPipe_io_toTXDAT_bits_task_fromL2pft),
+    .io_in_bits_task_needHint
+      (_mainPipe_io_toTXDAT_bits_task_needHint),
+    .io_in_bits_task_dirty                         (_mainPipe_io_toTXDAT_bits_task_dirty),
+    .io_in_bits_task_way                           (_mainPipe_io_toTXDAT_bits_task_way),
+    .io_in_bits_task_meta_dirty
+      (_mainPipe_io_toTXDAT_bits_task_meta_dirty),
+    .io_in_bits_task_meta_state
+      (_mainPipe_io_toTXDAT_bits_task_meta_state),
+    .io_in_bits_task_meta_clients
+      (_mainPipe_io_toTXDAT_bits_task_meta_clients),
+    .io_in_bits_task_meta_alias
+      (_mainPipe_io_toTXDAT_bits_task_meta_alias),
+    .io_in_bits_task_meta_prefetch
+      (_mainPipe_io_toTXDAT_bits_task_meta_prefetch),
+    .io_in_bits_task_meta_prefetchSrc
+      (_mainPipe_io_toTXDAT_bits_task_meta_prefetchSrc),
+    .io_in_bits_task_meta_accessed
+      (_mainPipe_io_toTXDAT_bits_task_meta_accessed),
+    .io_in_bits_task_meta_tagErr
+      (_mainPipe_io_toTXDAT_bits_task_meta_tagErr),
+    .io_in_bits_task_meta_dataErr
+      (_mainPipe_io_toTXDAT_bits_task_meta_dataErr),
+    .io_in_bits_task_metaWen
+      (_mainPipe_io_toTXDAT_bits_task_metaWen),
+    .io_in_bits_task_tagWen
+      (_mainPipe_io_toTXDAT_bits_task_tagWen),
+    .io_in_bits_task_dsWen                         (_mainPipe_io_toTXDAT_bits_task_dsWen),
+    .io_in_bits_task_wayMask
+      (_mainPipe_io_toTXDAT_bits_task_wayMask),
+    .io_in_bits_task_replTask
+      (_mainPipe_io_toTXDAT_bits_task_replTask),
+    .io_in_bits_task_cmoTask
+      (_mainPipe_io_toTXDAT_bits_task_cmoTask),
+    .io_in_bits_task_cmoAll
+      (_mainPipe_io_toTXDAT_bits_task_cmoAll),
+    .io_in_bits_task_reqSource
+      (_mainPipe_io_toTXDAT_bits_task_reqSource),
+    .io_in_bits_task_mergeA
+      (_mainPipe_io_toTXDAT_bits_task_mergeA),
+    .io_in_bits_task_aMergeTask_off
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_off),
+    .io_in_bits_task_aMergeTask_alias
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_alias),
+    .io_in_bits_task_aMergeTask_vaddr
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_vaddr),
+    .io_in_bits_task_aMergeTask_isKeyword
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_isKeyword),
+    .io_in_bits_task_aMergeTask_opcode
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_opcode),
+    .io_in_bits_task_aMergeTask_param
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_param),
+    .io_in_bits_task_aMergeTask_sourceId
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_sourceId),
+    .io_in_bits_task_aMergeTask_meta_dirty
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_dirty),
+    .io_in_bits_task_aMergeTask_meta_state
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_state),
+    .io_in_bits_task_aMergeTask_meta_clients
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_clients),
+    .io_in_bits_task_aMergeTask_meta_alias
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_alias),
+    .io_in_bits_task_aMergeTask_meta_prefetch
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_prefetch),
+    .io_in_bits_task_aMergeTask_meta_prefetchSrc
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_prefetchSrc),
+    .io_in_bits_task_aMergeTask_meta_accessed
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_accessed),
+    .io_in_bits_task_aMergeTask_meta_tagErr
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_tagErr),
+    .io_in_bits_task_aMergeTask_meta_dataErr
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_dataErr),
+    .io_in_bits_task_snpHitRelease
+      (_mainPipe_io_toTXDAT_bits_task_snpHitRelease),
+    .io_in_bits_task_snpHitReleaseToInval
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseToInval),
+    .io_in_bits_task_snpHitReleaseToClean
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseToClean),
+    .io_in_bits_task_snpHitReleaseWithData
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseWithData),
+    .io_in_bits_task_snpHitReleaseIdx
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseIdx),
+    .io_in_bits_task_snpHitReleaseMeta_dirty
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_dirty),
+    .io_in_bits_task_snpHitReleaseMeta_state
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_state),
+    .io_in_bits_task_snpHitReleaseMeta_clients
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_clients),
+    .io_in_bits_task_snpHitReleaseMeta_alias
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_alias),
+    .io_in_bits_task_snpHitReleaseMeta_prefetch
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_prefetch),
+    .io_in_bits_task_snpHitReleaseMeta_prefetchSrc
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_in_bits_task_snpHitReleaseMeta_accessed
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_accessed),
+    .io_in_bits_task_snpHitReleaseMeta_tagErr
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_tagErr),
+    .io_in_bits_task_snpHitReleaseMeta_dataErr
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_dataErr),
+    .io_in_bits_task_tgtID                         (_mainPipe_io_toTXDAT_bits_task_tgtID),
+    .io_in_bits_task_srcID                         (_mainPipe_io_toTXDAT_bits_task_srcID),
+    .io_in_bits_task_txnID                         (_mainPipe_io_toTXDAT_bits_task_txnID),
+    .io_in_bits_task_homeNID
+      (_mainPipe_io_toTXDAT_bits_task_homeNID),
+    .io_in_bits_task_dbID                          (_mainPipe_io_toTXDAT_bits_task_dbID),
+    .io_in_bits_task_fwdNID
+      (_mainPipe_io_toTXDAT_bits_task_fwdNID),
+    .io_in_bits_task_fwdTxnID
+      (_mainPipe_io_toTXDAT_bits_task_fwdTxnID),
+    .io_in_bits_task_chiOpcode
+      (_mainPipe_io_toTXDAT_bits_task_chiOpcode),
+    .io_in_bits_task_resp                          (_mainPipe_io_toTXDAT_bits_task_resp),
+    .io_in_bits_task_fwdState
+      (_mainPipe_io_toTXDAT_bits_task_fwdState),
+    .io_in_bits_task_pCrdType
+      (_mainPipe_io_toTXDAT_bits_task_pCrdType),
+    .io_in_bits_task_retToSrc
+      (_mainPipe_io_toTXDAT_bits_task_retToSrc),
+    .io_in_bits_task_likelyshared
+      (_mainPipe_io_toTXDAT_bits_task_likelyshared),
+    .io_in_bits_task_expCompAck
+      (_mainPipe_io_toTXDAT_bits_task_expCompAck),
+    .io_in_bits_task_allowRetry
+      (_mainPipe_io_toTXDAT_bits_task_allowRetry),
+    .io_in_bits_task_memAttr_allocate
+      (_mainPipe_io_toTXDAT_bits_task_memAttr_allocate),
+    .io_in_bits_task_memAttr_cacheable
+      (_mainPipe_io_toTXDAT_bits_task_memAttr_cacheable),
+    .io_in_bits_task_memAttr_device
+      (_mainPipe_io_toTXDAT_bits_task_memAttr_device),
+    .io_in_bits_task_memAttr_ewa
+      (_mainPipe_io_toTXDAT_bits_task_memAttr_ewa),
+    .io_in_bits_task_traceTag
+      (_mainPipe_io_toTXDAT_bits_task_traceTag),
+    .io_in_bits_data_data                          (_mainPipe_io_toTXDAT_bits_data_data),
+    .io_out_ready                                  (io_out_tx_dat_ready),
+    .io_out_valid                                  (io_out_tx_dat_valid),
+    .io_out_bits_tgtID                             (io_out_tx_dat_bits_tgtID),
+    .io_out_bits_srcID                             (io_out_tx_dat_bits_srcID),
+    .io_out_bits_txnID                             (io_out_tx_dat_bits_txnID),
+    .io_out_bits_homeNID                           (io_out_tx_dat_bits_homeNID),
+    .io_out_bits_opcode                            (io_out_tx_dat_bits_opcode),
+    .io_out_bits_respErr                           (io_out_tx_dat_bits_respErr),
+    .io_out_bits_resp                              (io_out_tx_dat_bits_resp),
+    .io_out_bits_dataSource                        (io_out_tx_dat_bits_dataSource),
+    .io_out_bits_dbID                              (io_out_tx_dat_bits_dbID),
+    .io_out_bits_ccID                              (io_out_tx_dat_bits_ccID),
+    .io_out_bits_dataID                            (io_out_tx_dat_bits_dataID),
+    .io_out_bits_traceTag                          (io_out_tx_dat_bits_traceTag),
+    .io_out_bits_be                                (io_out_tx_dat_bits_be),
+    .io_out_bits_data                              (io_out_tx_dat_bits_data),
+    .io_out_bits_dataCheck                         (io_out_tx_dat_bits_dataCheck),
+    .io_out_bits_poison                            (io_out_tx_dat_bits_poison),
+    .io_pipeStatusVec_1_valid                      (_reqArb_io_status_vec_toTX_1_valid),
+    .io_pipeStatusVec_1_bits_channel
+      (_reqArb_io_status_vec_toTX_1_bits_channel),
+    .io_pipeStatusVec_1_bits_txChannel
+      (_reqArb_io_status_vec_toTX_1_bits_txChannel),
+    .io_pipeStatusVec_1_bits_mshrTask
+      (_reqArb_io_status_vec_toTX_1_bits_mshrTask),
+    .io_pipeStatusVec_2_valid                      (_mainPipe_io_status_vec_toTX_0_valid),
+    .io_pipeStatusVec_2_bits_channel
+      (_mainPipe_io_status_vec_toTX_0_bits_channel),
+    .io_pipeStatusVec_2_bits_txChannel
+      (_mainPipe_io_status_vec_toTX_0_bits_txChannel),
+    .io_pipeStatusVec_2_bits_mshrTask
+      (_mainPipe_io_status_vec_toTX_0_bits_mshrTask),
+    .io_pipeStatusVec_3_valid                      (_mainPipe_io_status_vec_toTX_1_valid),
+    .io_pipeStatusVec_3_bits_channel
+      (_mainPipe_io_status_vec_toTX_1_bits_channel),
+    .io_pipeStatusVec_3_bits_txChannel
+      (_mainPipe_io_status_vec_toTX_1_bits_txChannel),
+    .io_pipeStatusVec_3_bits_mshrTask
+      (_mainPipe_io_status_vec_toTX_1_bits_mshrTask),
+    .io_pipeStatusVec_4_valid                      (_mainPipe_io_status_vec_toTX_2_valid),
+    .io_pipeStatusVec_4_bits_channel
+      (_mainPipe_io_status_vec_toTX_2_bits_channel),
+    .io_pipeStatusVec_4_bits_txChannel
+      (_mainPipe_io_status_vec_toTX_2_bits_txChannel),
+    .io_pipeStatusVec_4_bits_mshrTask
+      (_mainPipe_io_status_vec_toTX_2_bits_mshrTask),
+    .io_toReqArb_blockMSHRReqEntrance
+      (_txdat_io_toReqArb_blockMSHRReqEntrance),
+    .io_toReqArb_blockSinkBReqEntrance
+      (_txdat_io_toReqArb_blockSinkBReqEntrance)
+  );
+  TXRSP txrsp (
+    .clock                             (clock),
+    .reset                             (reset),
+    .io_pipeRsp_valid                  (_mainPipe_io_toTXRSP_valid),
+    .io_pipeRsp_bits_denied            (_mainPipe_io_toTXRSP_bits_denied),
+    .io_pipeRsp_bits_tgtID             (_mainPipe_io_toTXRSP_bits_tgtID),
+    .io_pipeRsp_bits_srcID             (_mainPipe_io_toTXRSP_bits_srcID),
+    .io_pipeRsp_bits_txnID             (_mainPipe_io_toTXRSP_bits_txnID),
+    .io_pipeRsp_bits_dbID              (_mainPipe_io_toTXRSP_bits_dbID),
+    .io_pipeRsp_bits_chiOpcode         (_mainPipe_io_toTXRSP_bits_chiOpcode),
+    .io_pipeRsp_bits_resp              (_mainPipe_io_toTXRSP_bits_resp),
+    .io_pipeRsp_bits_fwdState          (_mainPipe_io_toTXRSP_bits_fwdState),
+    .io_pipeRsp_bits_pCrdType          (_mainPipe_io_toTXRSP_bits_pCrdType),
+    .io_pipeRsp_bits_traceTag          (_mainPipe_io_toTXRSP_bits_traceTag),
+    .io_mshrRsp_ready                  (_txrsp_io_mshrRsp_ready),
+    .io_mshrRsp_valid                  (_mshrCtl_io_toTXRSP_valid),
+    .io_mshrRsp_bits_tgtID             (_mshrCtl_io_toTXRSP_bits_tgtID),
+    .io_mshrRsp_bits_txnID             (_mshrCtl_io_toTXRSP_bits_txnID),
+    .io_mshrRsp_bits_opcode            (_mshrCtl_io_toTXRSP_bits_opcode),
+    .io_mshrRsp_bits_traceTag          (_mshrCtl_io_toTXRSP_bits_traceTag),
+    .io_out_ready                      (io_out_tx_rsp_ready),
+    .io_out_valid                      (io_out_tx_rsp_valid),
+    .io_out_bits_qos                   (io_out_tx_rsp_bits_qos),
+    .io_out_bits_tgtID                 (io_out_tx_rsp_bits_tgtID),
+    .io_out_bits_srcID                 (io_out_tx_rsp_bits_srcID),
+    .io_out_bits_txnID                 (io_out_tx_rsp_bits_txnID),
+    .io_out_bits_opcode                (io_out_tx_rsp_bits_opcode),
+    .io_out_bits_respErr               (io_out_tx_rsp_bits_respErr),
+    .io_out_bits_resp                  (io_out_tx_rsp_bits_resp),
+    .io_out_bits_fwdState              (io_out_tx_rsp_bits_fwdState),
+    .io_out_bits_cBusy                 (io_out_tx_rsp_bits_cBusy),
+    .io_out_bits_dbID                  (io_out_tx_rsp_bits_dbID),
+    .io_out_bits_pCrdType              (io_out_tx_rsp_bits_pCrdType),
+    .io_out_bits_tagOp                 (io_out_tx_rsp_bits_tagOp),
+    .io_out_bits_traceTag              (io_out_tx_rsp_bits_traceTag),
+    .io_pipeStatusVec_1_valid          (_reqArb_io_status_vec_toTX_1_valid),
+    .io_pipeStatusVec_1_bits_channel   (_reqArb_io_status_vec_toTX_1_bits_channel),
+    .io_pipeStatusVec_1_bits_txChannel (_reqArb_io_status_vec_toTX_1_bits_txChannel),
+    .io_pipeStatusVec_1_bits_mshrTask  (_reqArb_io_status_vec_toTX_1_bits_mshrTask),
+    .io_pipeStatusVec_2_valid          (_mainPipe_io_status_vec_toTX_0_valid),
+    .io_pipeStatusVec_2_bits_channel   (_mainPipe_io_status_vec_toTX_0_bits_channel),
+    .io_pipeStatusVec_2_bits_txChannel (_mainPipe_io_status_vec_toTX_0_bits_txChannel),
+    .io_pipeStatusVec_2_bits_mshrTask  (_mainPipe_io_status_vec_toTX_0_bits_mshrTask),
+    .io_pipeStatusVec_3_valid          (_mainPipe_io_status_vec_toTX_1_valid),
+    .io_pipeStatusVec_3_bits_channel   (_mainPipe_io_status_vec_toTX_1_bits_channel),
+    .io_pipeStatusVec_3_bits_txChannel (_mainPipe_io_status_vec_toTX_1_bits_txChannel),
+    .io_pipeStatusVec_3_bits_mshrTask  (_mainPipe_io_status_vec_toTX_1_bits_mshrTask),
+    .io_pipeStatusVec_4_valid          (_mainPipe_io_status_vec_toTX_2_valid),
+    .io_pipeStatusVec_4_bits_channel   (_mainPipe_io_status_vec_toTX_2_bits_channel),
+    .io_pipeStatusVec_4_bits_txChannel (_mainPipe_io_status_vec_toTX_2_bits_txChannel),
+    .io_pipeStatusVec_4_bits_mshrTask  (_mainPipe_io_status_vec_toTX_2_bits_mshrTask),
+    .io_toReqArb_blockMSHRReqEntrance  (_txrsp_io_toReqArb_blockMSHRReqEntrance),
+    .io_toReqArb_blockSinkBReqEntrance (_txrsp_io_toReqArb_blockSinkBReqEntrance)
+  );
+  RXSNP rxsnp (
+    .clock                                      (clock),
+    .reset                                      (reset),
+    .io_rxsnp_ready                             (io_out_rx_snp_ready),
+    .io_rxsnp_valid                             (io_out_rx_snp_valid),
+    .io_rxsnp_bits_qos                          (io_out_rx_snp_bits_qos),
+    .io_rxsnp_bits_srcID                        (io_out_rx_snp_bits_srcID),
+    .io_rxsnp_bits_txnID                        (io_out_rx_snp_bits_txnID),
+    .io_rxsnp_bits_fwdNID                       (io_out_rx_snp_bits_fwdNID),
+    .io_rxsnp_bits_fwdTxnID                     (io_out_rx_snp_bits_fwdTxnID),
+    .io_rxsnp_bits_opcode                       (io_out_rx_snp_bits_opcode),
+    .io_rxsnp_bits_addr                         (io_out_rx_snp_bits_addr),
+    .io_rxsnp_bits_ns                           (io_out_rx_snp_bits_ns),
+    .io_rxsnp_bits_doNotGoToSD                  (io_out_rx_snp_bits_doNotGoToSD),
+    .io_rxsnp_bits_retToSrc                     (io_out_rx_snp_bits_retToSrc),
+    .io_rxsnp_bits_traceTag                     (io_out_rx_snp_bits_traceTag),
+    .io_rxsnp_bits_mpam_perfMonGroup            (io_out_rx_snp_bits_mpam_perfMonGroup),
+    .io_rxsnp_bits_mpam_partID                  (io_out_rx_snp_bits_mpam_partID),
+    .io_rxsnp_bits_mpam_mpamNS                  (io_out_rx_snp_bits_mpam_mpamNS),
+    .io_task_ready                              (_reqArb_io_sinkB_ready),
+    .io_task_valid                              (_rxsnp_io_task_valid),
+    .io_task_bits_set                           (_rxsnp_io_task_bits_set),
+    .io_task_bits_tag                           (_rxsnp_io_task_bits_tag),
+    .io_task_bits_off                           (_rxsnp_io_task_bits_off),
+    .io_task_bits_snpHitRelease                 (_rxsnp_io_task_bits_snpHitRelease),
+    .io_task_bits_snpHitReleaseToInval
+      (_rxsnp_io_task_bits_snpHitReleaseToInval),
+    .io_task_bits_snpHitReleaseToClean
+      (_rxsnp_io_task_bits_snpHitReleaseToClean),
+    .io_task_bits_snpHitReleaseWithData
+      (_rxsnp_io_task_bits_snpHitReleaseWithData),
+    .io_task_bits_snpHitReleaseIdx              (_rxsnp_io_task_bits_snpHitReleaseIdx),
+    .io_task_bits_snpHitReleaseMeta_dirty
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_dirty),
+    .io_task_bits_snpHitReleaseMeta_state
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_state),
+    .io_task_bits_snpHitReleaseMeta_clients
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_clients),
+    .io_task_bits_snpHitReleaseMeta_alias
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_alias),
+    .io_task_bits_snpHitReleaseMeta_prefetch
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_prefetch),
+    .io_task_bits_snpHitReleaseMeta_prefetchSrc
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_task_bits_snpHitReleaseMeta_accessed
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_accessed),
+    .io_task_bits_snpHitReleaseMeta_tagErr
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_tagErr),
+    .io_task_bits_snpHitReleaseMeta_dataErr
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_dataErr),
+    .io_task_bits_srcID                         (_rxsnp_io_task_bits_srcID),
+    .io_task_bits_txnID                         (_rxsnp_io_task_bits_txnID),
+    .io_task_bits_fwdNID                        (_rxsnp_io_task_bits_fwdNID),
+    .io_task_bits_fwdTxnID                      (_rxsnp_io_task_bits_fwdTxnID),
+    .io_task_bits_chiOpcode                     (_rxsnp_io_task_bits_chiOpcode),
+    .io_task_bits_retToSrc                      (_rxsnp_io_task_bits_retToSrc),
+    .io_task_bits_traceTag                      (_rxsnp_io_task_bits_traceTag),
+    .io_msInfo_0_valid                          (_mshrCtl_io_msInfo_0_valid),
+    .io_msInfo_0_bits_set                       (_mshrCtl_io_msInfo_0_bits_set),
+    .io_msInfo_0_bits_reqTag                    (_mshrCtl_io_msInfo_0_bits_reqTag),
+    .io_msInfo_0_bits_willFree                  (_mshrCtl_io_msInfo_0_bits_willFree),
+    .io_msInfo_0_bits_aliasTask                 (_mshrCtl_io_msInfo_0_bits_aliasTask),
+    .io_msInfo_0_bits_blockRefill               (_mshrCtl_io_msInfo_0_bits_blockRefill),
+    .io_msInfo_0_bits_meta_dirty                (_mshrCtl_io_msInfo_0_bits_meta_dirty),
+    .io_msInfo_0_bits_meta_state                (_mshrCtl_io_msInfo_0_bits_meta_state),
+    .io_msInfo_0_bits_meta_clients              (_mshrCtl_io_msInfo_0_bits_meta_clients),
+    .io_msInfo_0_bits_meta_alias                (_mshrCtl_io_msInfo_0_bits_meta_alias),
+    .io_msInfo_0_bits_meta_prefetch             (_mshrCtl_io_msInfo_0_bits_meta_prefetch),
+    .io_msInfo_0_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_0_bits_meta_prefetchSrc),
+    .io_msInfo_0_bits_meta_accessed             (_mshrCtl_io_msInfo_0_bits_meta_accessed),
+    .io_msInfo_0_bits_meta_tagErr               (_mshrCtl_io_msInfo_0_bits_meta_tagErr),
+    .io_msInfo_0_bits_meta_dataErr              (_mshrCtl_io_msInfo_0_bits_meta_dataErr),
+    .io_msInfo_0_bits_metaTag                   (_mshrCtl_io_msInfo_0_bits_metaTag),
+    .io_msInfo_0_bits_dirHit                    (_mshrCtl_io_msInfo_0_bits_dirHit),
+    .io_msInfo_0_bits_w_grantfirst              (_mshrCtl_io_msInfo_0_bits_w_grantfirst),
+    .io_msInfo_0_bits_s_release                 (_mshrCtl_io_msInfo_0_bits_s_release),
+    .io_msInfo_0_bits_s_cmoresp                 (_mshrCtl_io_msInfo_0_bits_s_cmoresp),
+    .io_msInfo_0_bits_s_cmometaw                (_mshrCtl_io_msInfo_0_bits_s_cmometaw),
+    .io_msInfo_0_bits_w_releaseack              (_mshrCtl_io_msInfo_0_bits_w_releaseack),
+    .io_msInfo_0_bits_w_replResp                (_mshrCtl_io_msInfo_0_bits_w_replResp),
+    .io_msInfo_0_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_0_bits_w_rprobeacklast),
+    .io_msInfo_0_bits_replaceData               (_mshrCtl_io_msInfo_0_bits_replaceData),
+    .io_msInfo_0_bits_releaseToClean
+      (_mshrCtl_io_msInfo_0_bits_releaseToClean),
+    .io_msInfo_1_valid                          (_mshrCtl_io_msInfo_1_valid),
+    .io_msInfo_1_bits_set                       (_mshrCtl_io_msInfo_1_bits_set),
+    .io_msInfo_1_bits_reqTag                    (_mshrCtl_io_msInfo_1_bits_reqTag),
+    .io_msInfo_1_bits_willFree                  (_mshrCtl_io_msInfo_1_bits_willFree),
+    .io_msInfo_1_bits_aliasTask                 (_mshrCtl_io_msInfo_1_bits_aliasTask),
+    .io_msInfo_1_bits_blockRefill               (_mshrCtl_io_msInfo_1_bits_blockRefill),
+    .io_msInfo_1_bits_meta_dirty                (_mshrCtl_io_msInfo_1_bits_meta_dirty),
+    .io_msInfo_1_bits_meta_state                (_mshrCtl_io_msInfo_1_bits_meta_state),
+    .io_msInfo_1_bits_meta_clients              (_mshrCtl_io_msInfo_1_bits_meta_clients),
+    .io_msInfo_1_bits_meta_alias                (_mshrCtl_io_msInfo_1_bits_meta_alias),
+    .io_msInfo_1_bits_meta_prefetch             (_mshrCtl_io_msInfo_1_bits_meta_prefetch),
+    .io_msInfo_1_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_1_bits_meta_prefetchSrc),
+    .io_msInfo_1_bits_meta_accessed             (_mshrCtl_io_msInfo_1_bits_meta_accessed),
+    .io_msInfo_1_bits_meta_tagErr               (_mshrCtl_io_msInfo_1_bits_meta_tagErr),
+    .io_msInfo_1_bits_meta_dataErr              (_mshrCtl_io_msInfo_1_bits_meta_dataErr),
+    .io_msInfo_1_bits_metaTag                   (_mshrCtl_io_msInfo_1_bits_metaTag),
+    .io_msInfo_1_bits_dirHit                    (_mshrCtl_io_msInfo_1_bits_dirHit),
+    .io_msInfo_1_bits_w_grantfirst              (_mshrCtl_io_msInfo_1_bits_w_grantfirst),
+    .io_msInfo_1_bits_s_release                 (_mshrCtl_io_msInfo_1_bits_s_release),
+    .io_msInfo_1_bits_s_cmoresp                 (_mshrCtl_io_msInfo_1_bits_s_cmoresp),
+    .io_msInfo_1_bits_s_cmometaw                (_mshrCtl_io_msInfo_1_bits_s_cmometaw),
+    .io_msInfo_1_bits_w_releaseack              (_mshrCtl_io_msInfo_1_bits_w_releaseack),
+    .io_msInfo_1_bits_w_replResp                (_mshrCtl_io_msInfo_1_bits_w_replResp),
+    .io_msInfo_1_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_1_bits_w_rprobeacklast),
+    .io_msInfo_1_bits_replaceData               (_mshrCtl_io_msInfo_1_bits_replaceData),
+    .io_msInfo_1_bits_releaseToClean
+      (_mshrCtl_io_msInfo_1_bits_releaseToClean),
+    .io_msInfo_2_valid                          (_mshrCtl_io_msInfo_2_valid),
+    .io_msInfo_2_bits_set                       (_mshrCtl_io_msInfo_2_bits_set),
+    .io_msInfo_2_bits_reqTag                    (_mshrCtl_io_msInfo_2_bits_reqTag),
+    .io_msInfo_2_bits_willFree                  (_mshrCtl_io_msInfo_2_bits_willFree),
+    .io_msInfo_2_bits_aliasTask                 (_mshrCtl_io_msInfo_2_bits_aliasTask),
+    .io_msInfo_2_bits_blockRefill               (_mshrCtl_io_msInfo_2_bits_blockRefill),
+    .io_msInfo_2_bits_meta_dirty                (_mshrCtl_io_msInfo_2_bits_meta_dirty),
+    .io_msInfo_2_bits_meta_state                (_mshrCtl_io_msInfo_2_bits_meta_state),
+    .io_msInfo_2_bits_meta_clients              (_mshrCtl_io_msInfo_2_bits_meta_clients),
+    .io_msInfo_2_bits_meta_alias                (_mshrCtl_io_msInfo_2_bits_meta_alias),
+    .io_msInfo_2_bits_meta_prefetch             (_mshrCtl_io_msInfo_2_bits_meta_prefetch),
+    .io_msInfo_2_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_2_bits_meta_prefetchSrc),
+    .io_msInfo_2_bits_meta_accessed             (_mshrCtl_io_msInfo_2_bits_meta_accessed),
+    .io_msInfo_2_bits_meta_tagErr               (_mshrCtl_io_msInfo_2_bits_meta_tagErr),
+    .io_msInfo_2_bits_meta_dataErr              (_mshrCtl_io_msInfo_2_bits_meta_dataErr),
+    .io_msInfo_2_bits_metaTag                   (_mshrCtl_io_msInfo_2_bits_metaTag),
+    .io_msInfo_2_bits_dirHit                    (_mshrCtl_io_msInfo_2_bits_dirHit),
+    .io_msInfo_2_bits_w_grantfirst              (_mshrCtl_io_msInfo_2_bits_w_grantfirst),
+    .io_msInfo_2_bits_s_release                 (_mshrCtl_io_msInfo_2_bits_s_release),
+    .io_msInfo_2_bits_s_cmoresp                 (_mshrCtl_io_msInfo_2_bits_s_cmoresp),
+    .io_msInfo_2_bits_s_cmometaw                (_mshrCtl_io_msInfo_2_bits_s_cmometaw),
+    .io_msInfo_2_bits_w_releaseack              (_mshrCtl_io_msInfo_2_bits_w_releaseack),
+    .io_msInfo_2_bits_w_replResp                (_mshrCtl_io_msInfo_2_bits_w_replResp),
+    .io_msInfo_2_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_2_bits_w_rprobeacklast),
+    .io_msInfo_2_bits_replaceData               (_mshrCtl_io_msInfo_2_bits_replaceData),
+    .io_msInfo_2_bits_releaseToClean
+      (_mshrCtl_io_msInfo_2_bits_releaseToClean),
+    .io_msInfo_3_valid                          (_mshrCtl_io_msInfo_3_valid),
+    .io_msInfo_3_bits_set                       (_mshrCtl_io_msInfo_3_bits_set),
+    .io_msInfo_3_bits_reqTag                    (_mshrCtl_io_msInfo_3_bits_reqTag),
+    .io_msInfo_3_bits_willFree                  (_mshrCtl_io_msInfo_3_bits_willFree),
+    .io_msInfo_3_bits_aliasTask                 (_mshrCtl_io_msInfo_3_bits_aliasTask),
+    .io_msInfo_3_bits_blockRefill               (_mshrCtl_io_msInfo_3_bits_blockRefill),
+    .io_msInfo_3_bits_meta_dirty                (_mshrCtl_io_msInfo_3_bits_meta_dirty),
+    .io_msInfo_3_bits_meta_state                (_mshrCtl_io_msInfo_3_bits_meta_state),
+    .io_msInfo_3_bits_meta_clients              (_mshrCtl_io_msInfo_3_bits_meta_clients),
+    .io_msInfo_3_bits_meta_alias                (_mshrCtl_io_msInfo_3_bits_meta_alias),
+    .io_msInfo_3_bits_meta_prefetch             (_mshrCtl_io_msInfo_3_bits_meta_prefetch),
+    .io_msInfo_3_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_3_bits_meta_prefetchSrc),
+    .io_msInfo_3_bits_meta_accessed             (_mshrCtl_io_msInfo_3_bits_meta_accessed),
+    .io_msInfo_3_bits_meta_tagErr               (_mshrCtl_io_msInfo_3_bits_meta_tagErr),
+    .io_msInfo_3_bits_meta_dataErr              (_mshrCtl_io_msInfo_3_bits_meta_dataErr),
+    .io_msInfo_3_bits_metaTag                   (_mshrCtl_io_msInfo_3_bits_metaTag),
+    .io_msInfo_3_bits_dirHit                    (_mshrCtl_io_msInfo_3_bits_dirHit),
+    .io_msInfo_3_bits_w_grantfirst              (_mshrCtl_io_msInfo_3_bits_w_grantfirst),
+    .io_msInfo_3_bits_s_release                 (_mshrCtl_io_msInfo_3_bits_s_release),
+    .io_msInfo_3_bits_s_cmoresp                 (_mshrCtl_io_msInfo_3_bits_s_cmoresp),
+    .io_msInfo_3_bits_s_cmometaw                (_mshrCtl_io_msInfo_3_bits_s_cmometaw),
+    .io_msInfo_3_bits_w_releaseack              (_mshrCtl_io_msInfo_3_bits_w_releaseack),
+    .io_msInfo_3_bits_w_replResp                (_mshrCtl_io_msInfo_3_bits_w_replResp),
+    .io_msInfo_3_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_3_bits_w_rprobeacklast),
+    .io_msInfo_3_bits_replaceData               (_mshrCtl_io_msInfo_3_bits_replaceData),
+    .io_msInfo_3_bits_releaseToClean
+      (_mshrCtl_io_msInfo_3_bits_releaseToClean),
+    .io_msInfo_4_valid                          (_mshrCtl_io_msInfo_4_valid),
+    .io_msInfo_4_bits_set                       (_mshrCtl_io_msInfo_4_bits_set),
+    .io_msInfo_4_bits_reqTag                    (_mshrCtl_io_msInfo_4_bits_reqTag),
+    .io_msInfo_4_bits_willFree                  (_mshrCtl_io_msInfo_4_bits_willFree),
+    .io_msInfo_4_bits_aliasTask                 (_mshrCtl_io_msInfo_4_bits_aliasTask),
+    .io_msInfo_4_bits_blockRefill               (_mshrCtl_io_msInfo_4_bits_blockRefill),
+    .io_msInfo_4_bits_meta_dirty                (_mshrCtl_io_msInfo_4_bits_meta_dirty),
+    .io_msInfo_4_bits_meta_state                (_mshrCtl_io_msInfo_4_bits_meta_state),
+    .io_msInfo_4_bits_meta_clients              (_mshrCtl_io_msInfo_4_bits_meta_clients),
+    .io_msInfo_4_bits_meta_alias                (_mshrCtl_io_msInfo_4_bits_meta_alias),
+    .io_msInfo_4_bits_meta_prefetch             (_mshrCtl_io_msInfo_4_bits_meta_prefetch),
+    .io_msInfo_4_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_4_bits_meta_prefetchSrc),
+    .io_msInfo_4_bits_meta_accessed             (_mshrCtl_io_msInfo_4_bits_meta_accessed),
+    .io_msInfo_4_bits_meta_tagErr               (_mshrCtl_io_msInfo_4_bits_meta_tagErr),
+    .io_msInfo_4_bits_meta_dataErr              (_mshrCtl_io_msInfo_4_bits_meta_dataErr),
+    .io_msInfo_4_bits_metaTag                   (_mshrCtl_io_msInfo_4_bits_metaTag),
+    .io_msInfo_4_bits_dirHit                    (_mshrCtl_io_msInfo_4_bits_dirHit),
+    .io_msInfo_4_bits_w_grantfirst              (_mshrCtl_io_msInfo_4_bits_w_grantfirst),
+    .io_msInfo_4_bits_s_release                 (_mshrCtl_io_msInfo_4_bits_s_release),
+    .io_msInfo_4_bits_s_cmoresp                 (_mshrCtl_io_msInfo_4_bits_s_cmoresp),
+    .io_msInfo_4_bits_s_cmometaw                (_mshrCtl_io_msInfo_4_bits_s_cmometaw),
+    .io_msInfo_4_bits_w_releaseack              (_mshrCtl_io_msInfo_4_bits_w_releaseack),
+    .io_msInfo_4_bits_w_replResp                (_mshrCtl_io_msInfo_4_bits_w_replResp),
+    .io_msInfo_4_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_4_bits_w_rprobeacklast),
+    .io_msInfo_4_bits_replaceData               (_mshrCtl_io_msInfo_4_bits_replaceData),
+    .io_msInfo_4_bits_releaseToClean
+      (_mshrCtl_io_msInfo_4_bits_releaseToClean),
+    .io_msInfo_5_valid                          (_mshrCtl_io_msInfo_5_valid),
+    .io_msInfo_5_bits_set                       (_mshrCtl_io_msInfo_5_bits_set),
+    .io_msInfo_5_bits_reqTag                    (_mshrCtl_io_msInfo_5_bits_reqTag),
+    .io_msInfo_5_bits_willFree                  (_mshrCtl_io_msInfo_5_bits_willFree),
+    .io_msInfo_5_bits_aliasTask                 (_mshrCtl_io_msInfo_5_bits_aliasTask),
+    .io_msInfo_5_bits_blockRefill               (_mshrCtl_io_msInfo_5_bits_blockRefill),
+    .io_msInfo_5_bits_meta_dirty                (_mshrCtl_io_msInfo_5_bits_meta_dirty),
+    .io_msInfo_5_bits_meta_state                (_mshrCtl_io_msInfo_5_bits_meta_state),
+    .io_msInfo_5_bits_meta_clients              (_mshrCtl_io_msInfo_5_bits_meta_clients),
+    .io_msInfo_5_bits_meta_alias                (_mshrCtl_io_msInfo_5_bits_meta_alias),
+    .io_msInfo_5_bits_meta_prefetch             (_mshrCtl_io_msInfo_5_bits_meta_prefetch),
+    .io_msInfo_5_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_5_bits_meta_prefetchSrc),
+    .io_msInfo_5_bits_meta_accessed             (_mshrCtl_io_msInfo_5_bits_meta_accessed),
+    .io_msInfo_5_bits_meta_tagErr               (_mshrCtl_io_msInfo_5_bits_meta_tagErr),
+    .io_msInfo_5_bits_meta_dataErr              (_mshrCtl_io_msInfo_5_bits_meta_dataErr),
+    .io_msInfo_5_bits_metaTag                   (_mshrCtl_io_msInfo_5_bits_metaTag),
+    .io_msInfo_5_bits_dirHit                    (_mshrCtl_io_msInfo_5_bits_dirHit),
+    .io_msInfo_5_bits_w_grantfirst              (_mshrCtl_io_msInfo_5_bits_w_grantfirst),
+    .io_msInfo_5_bits_s_release                 (_mshrCtl_io_msInfo_5_bits_s_release),
+    .io_msInfo_5_bits_s_cmoresp                 (_mshrCtl_io_msInfo_5_bits_s_cmoresp),
+    .io_msInfo_5_bits_s_cmometaw                (_mshrCtl_io_msInfo_5_bits_s_cmometaw),
+    .io_msInfo_5_bits_w_releaseack              (_mshrCtl_io_msInfo_5_bits_w_releaseack),
+    .io_msInfo_5_bits_w_replResp                (_mshrCtl_io_msInfo_5_bits_w_replResp),
+    .io_msInfo_5_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_5_bits_w_rprobeacklast),
+    .io_msInfo_5_bits_replaceData               (_mshrCtl_io_msInfo_5_bits_replaceData),
+    .io_msInfo_5_bits_releaseToClean
+      (_mshrCtl_io_msInfo_5_bits_releaseToClean),
+    .io_msInfo_6_valid                          (_mshrCtl_io_msInfo_6_valid),
+    .io_msInfo_6_bits_set                       (_mshrCtl_io_msInfo_6_bits_set),
+    .io_msInfo_6_bits_reqTag                    (_mshrCtl_io_msInfo_6_bits_reqTag),
+    .io_msInfo_6_bits_willFree                  (_mshrCtl_io_msInfo_6_bits_willFree),
+    .io_msInfo_6_bits_aliasTask                 (_mshrCtl_io_msInfo_6_bits_aliasTask),
+    .io_msInfo_6_bits_blockRefill               (_mshrCtl_io_msInfo_6_bits_blockRefill),
+    .io_msInfo_6_bits_meta_dirty                (_mshrCtl_io_msInfo_6_bits_meta_dirty),
+    .io_msInfo_6_bits_meta_state                (_mshrCtl_io_msInfo_6_bits_meta_state),
+    .io_msInfo_6_bits_meta_clients              (_mshrCtl_io_msInfo_6_bits_meta_clients),
+    .io_msInfo_6_bits_meta_alias                (_mshrCtl_io_msInfo_6_bits_meta_alias),
+    .io_msInfo_6_bits_meta_prefetch             (_mshrCtl_io_msInfo_6_bits_meta_prefetch),
+    .io_msInfo_6_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_6_bits_meta_prefetchSrc),
+    .io_msInfo_6_bits_meta_accessed             (_mshrCtl_io_msInfo_6_bits_meta_accessed),
+    .io_msInfo_6_bits_meta_tagErr               (_mshrCtl_io_msInfo_6_bits_meta_tagErr),
+    .io_msInfo_6_bits_meta_dataErr              (_mshrCtl_io_msInfo_6_bits_meta_dataErr),
+    .io_msInfo_6_bits_metaTag                   (_mshrCtl_io_msInfo_6_bits_metaTag),
+    .io_msInfo_6_bits_dirHit                    (_mshrCtl_io_msInfo_6_bits_dirHit),
+    .io_msInfo_6_bits_w_grantfirst              (_mshrCtl_io_msInfo_6_bits_w_grantfirst),
+    .io_msInfo_6_bits_s_release                 (_mshrCtl_io_msInfo_6_bits_s_release),
+    .io_msInfo_6_bits_s_cmoresp                 (_mshrCtl_io_msInfo_6_bits_s_cmoresp),
+    .io_msInfo_6_bits_s_cmometaw                (_mshrCtl_io_msInfo_6_bits_s_cmometaw),
+    .io_msInfo_6_bits_w_releaseack              (_mshrCtl_io_msInfo_6_bits_w_releaseack),
+    .io_msInfo_6_bits_w_replResp                (_mshrCtl_io_msInfo_6_bits_w_replResp),
+    .io_msInfo_6_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_6_bits_w_rprobeacklast),
+    .io_msInfo_6_bits_replaceData               (_mshrCtl_io_msInfo_6_bits_replaceData),
+    .io_msInfo_6_bits_releaseToClean
+      (_mshrCtl_io_msInfo_6_bits_releaseToClean),
+    .io_msInfo_7_valid                          (_mshrCtl_io_msInfo_7_valid),
+    .io_msInfo_7_bits_set                       (_mshrCtl_io_msInfo_7_bits_set),
+    .io_msInfo_7_bits_reqTag                    (_mshrCtl_io_msInfo_7_bits_reqTag),
+    .io_msInfo_7_bits_willFree                  (_mshrCtl_io_msInfo_7_bits_willFree),
+    .io_msInfo_7_bits_aliasTask                 (_mshrCtl_io_msInfo_7_bits_aliasTask),
+    .io_msInfo_7_bits_blockRefill               (_mshrCtl_io_msInfo_7_bits_blockRefill),
+    .io_msInfo_7_bits_meta_dirty                (_mshrCtl_io_msInfo_7_bits_meta_dirty),
+    .io_msInfo_7_bits_meta_state                (_mshrCtl_io_msInfo_7_bits_meta_state),
+    .io_msInfo_7_bits_meta_clients              (_mshrCtl_io_msInfo_7_bits_meta_clients),
+    .io_msInfo_7_bits_meta_alias                (_mshrCtl_io_msInfo_7_bits_meta_alias),
+    .io_msInfo_7_bits_meta_prefetch             (_mshrCtl_io_msInfo_7_bits_meta_prefetch),
+    .io_msInfo_7_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_7_bits_meta_prefetchSrc),
+    .io_msInfo_7_bits_meta_accessed             (_mshrCtl_io_msInfo_7_bits_meta_accessed),
+    .io_msInfo_7_bits_meta_tagErr               (_mshrCtl_io_msInfo_7_bits_meta_tagErr),
+    .io_msInfo_7_bits_meta_dataErr              (_mshrCtl_io_msInfo_7_bits_meta_dataErr),
+    .io_msInfo_7_bits_metaTag                   (_mshrCtl_io_msInfo_7_bits_metaTag),
+    .io_msInfo_7_bits_dirHit                    (_mshrCtl_io_msInfo_7_bits_dirHit),
+    .io_msInfo_7_bits_w_grantfirst              (_mshrCtl_io_msInfo_7_bits_w_grantfirst),
+    .io_msInfo_7_bits_s_release                 (_mshrCtl_io_msInfo_7_bits_s_release),
+    .io_msInfo_7_bits_s_cmoresp                 (_mshrCtl_io_msInfo_7_bits_s_cmoresp),
+    .io_msInfo_7_bits_s_cmometaw                (_mshrCtl_io_msInfo_7_bits_s_cmometaw),
+    .io_msInfo_7_bits_w_releaseack              (_mshrCtl_io_msInfo_7_bits_w_releaseack),
+    .io_msInfo_7_bits_w_replResp                (_mshrCtl_io_msInfo_7_bits_w_replResp),
+    .io_msInfo_7_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_7_bits_w_rprobeacklast),
+    .io_msInfo_7_bits_replaceData               (_mshrCtl_io_msInfo_7_bits_replaceData),
+    .io_msInfo_7_bits_releaseToClean
+      (_mshrCtl_io_msInfo_7_bits_releaseToClean),
+    .io_msInfo_8_valid                          (_mshrCtl_io_msInfo_8_valid),
+    .io_msInfo_8_bits_set                       (_mshrCtl_io_msInfo_8_bits_set),
+    .io_msInfo_8_bits_reqTag                    (_mshrCtl_io_msInfo_8_bits_reqTag),
+    .io_msInfo_8_bits_willFree                  (_mshrCtl_io_msInfo_8_bits_willFree),
+    .io_msInfo_8_bits_aliasTask                 (_mshrCtl_io_msInfo_8_bits_aliasTask),
+    .io_msInfo_8_bits_blockRefill               (_mshrCtl_io_msInfo_8_bits_blockRefill),
+    .io_msInfo_8_bits_meta_dirty                (_mshrCtl_io_msInfo_8_bits_meta_dirty),
+    .io_msInfo_8_bits_meta_state                (_mshrCtl_io_msInfo_8_bits_meta_state),
+    .io_msInfo_8_bits_meta_clients              (_mshrCtl_io_msInfo_8_bits_meta_clients),
+    .io_msInfo_8_bits_meta_alias                (_mshrCtl_io_msInfo_8_bits_meta_alias),
+    .io_msInfo_8_bits_meta_prefetch             (_mshrCtl_io_msInfo_8_bits_meta_prefetch),
+    .io_msInfo_8_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_8_bits_meta_prefetchSrc),
+    .io_msInfo_8_bits_meta_accessed             (_mshrCtl_io_msInfo_8_bits_meta_accessed),
+    .io_msInfo_8_bits_meta_tagErr               (_mshrCtl_io_msInfo_8_bits_meta_tagErr),
+    .io_msInfo_8_bits_meta_dataErr              (_mshrCtl_io_msInfo_8_bits_meta_dataErr),
+    .io_msInfo_8_bits_metaTag                   (_mshrCtl_io_msInfo_8_bits_metaTag),
+    .io_msInfo_8_bits_dirHit                    (_mshrCtl_io_msInfo_8_bits_dirHit),
+    .io_msInfo_8_bits_w_grantfirst              (_mshrCtl_io_msInfo_8_bits_w_grantfirst),
+    .io_msInfo_8_bits_s_release                 (_mshrCtl_io_msInfo_8_bits_s_release),
+    .io_msInfo_8_bits_s_cmoresp                 (_mshrCtl_io_msInfo_8_bits_s_cmoresp),
+    .io_msInfo_8_bits_s_cmometaw                (_mshrCtl_io_msInfo_8_bits_s_cmometaw),
+    .io_msInfo_8_bits_w_releaseack              (_mshrCtl_io_msInfo_8_bits_w_releaseack),
+    .io_msInfo_8_bits_w_replResp                (_mshrCtl_io_msInfo_8_bits_w_replResp),
+    .io_msInfo_8_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_8_bits_w_rprobeacklast),
+    .io_msInfo_8_bits_replaceData               (_mshrCtl_io_msInfo_8_bits_replaceData),
+    .io_msInfo_8_bits_releaseToClean
+      (_mshrCtl_io_msInfo_8_bits_releaseToClean),
+    .io_msInfo_9_valid                          (_mshrCtl_io_msInfo_9_valid),
+    .io_msInfo_9_bits_set                       (_mshrCtl_io_msInfo_9_bits_set),
+    .io_msInfo_9_bits_reqTag                    (_mshrCtl_io_msInfo_9_bits_reqTag),
+    .io_msInfo_9_bits_willFree                  (_mshrCtl_io_msInfo_9_bits_willFree),
+    .io_msInfo_9_bits_aliasTask                 (_mshrCtl_io_msInfo_9_bits_aliasTask),
+    .io_msInfo_9_bits_blockRefill               (_mshrCtl_io_msInfo_9_bits_blockRefill),
+    .io_msInfo_9_bits_meta_dirty                (_mshrCtl_io_msInfo_9_bits_meta_dirty),
+    .io_msInfo_9_bits_meta_state                (_mshrCtl_io_msInfo_9_bits_meta_state),
+    .io_msInfo_9_bits_meta_clients              (_mshrCtl_io_msInfo_9_bits_meta_clients),
+    .io_msInfo_9_bits_meta_alias                (_mshrCtl_io_msInfo_9_bits_meta_alias),
+    .io_msInfo_9_bits_meta_prefetch             (_mshrCtl_io_msInfo_9_bits_meta_prefetch),
+    .io_msInfo_9_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_9_bits_meta_prefetchSrc),
+    .io_msInfo_9_bits_meta_accessed             (_mshrCtl_io_msInfo_9_bits_meta_accessed),
+    .io_msInfo_9_bits_meta_tagErr               (_mshrCtl_io_msInfo_9_bits_meta_tagErr),
+    .io_msInfo_9_bits_meta_dataErr              (_mshrCtl_io_msInfo_9_bits_meta_dataErr),
+    .io_msInfo_9_bits_metaTag                   (_mshrCtl_io_msInfo_9_bits_metaTag),
+    .io_msInfo_9_bits_dirHit                    (_mshrCtl_io_msInfo_9_bits_dirHit),
+    .io_msInfo_9_bits_w_grantfirst              (_mshrCtl_io_msInfo_9_bits_w_grantfirst),
+    .io_msInfo_9_bits_s_release                 (_mshrCtl_io_msInfo_9_bits_s_release),
+    .io_msInfo_9_bits_s_cmoresp                 (_mshrCtl_io_msInfo_9_bits_s_cmoresp),
+    .io_msInfo_9_bits_s_cmometaw                (_mshrCtl_io_msInfo_9_bits_s_cmometaw),
+    .io_msInfo_9_bits_w_releaseack              (_mshrCtl_io_msInfo_9_bits_w_releaseack),
+    .io_msInfo_9_bits_w_replResp                (_mshrCtl_io_msInfo_9_bits_w_replResp),
+    .io_msInfo_9_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_9_bits_w_rprobeacklast),
+    .io_msInfo_9_bits_replaceData               (_mshrCtl_io_msInfo_9_bits_replaceData),
+    .io_msInfo_9_bits_releaseToClean
+      (_mshrCtl_io_msInfo_9_bits_releaseToClean),
+    .io_msInfo_10_valid                         (_mshrCtl_io_msInfo_10_valid),
+    .io_msInfo_10_bits_set                      (_mshrCtl_io_msInfo_10_bits_set),
+    .io_msInfo_10_bits_reqTag                   (_mshrCtl_io_msInfo_10_bits_reqTag),
+    .io_msInfo_10_bits_willFree                 (_mshrCtl_io_msInfo_10_bits_willFree),
+    .io_msInfo_10_bits_aliasTask                (_mshrCtl_io_msInfo_10_bits_aliasTask),
+    .io_msInfo_10_bits_blockRefill              (_mshrCtl_io_msInfo_10_bits_blockRefill),
+    .io_msInfo_10_bits_meta_dirty               (_mshrCtl_io_msInfo_10_bits_meta_dirty),
+    .io_msInfo_10_bits_meta_state               (_mshrCtl_io_msInfo_10_bits_meta_state),
+    .io_msInfo_10_bits_meta_clients             (_mshrCtl_io_msInfo_10_bits_meta_clients),
+    .io_msInfo_10_bits_meta_alias               (_mshrCtl_io_msInfo_10_bits_meta_alias),
+    .io_msInfo_10_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_10_bits_meta_prefetch),
+    .io_msInfo_10_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_10_bits_meta_prefetchSrc),
+    .io_msInfo_10_bits_meta_accessed
+      (_mshrCtl_io_msInfo_10_bits_meta_accessed),
+    .io_msInfo_10_bits_meta_tagErr              (_mshrCtl_io_msInfo_10_bits_meta_tagErr),
+    .io_msInfo_10_bits_meta_dataErr             (_mshrCtl_io_msInfo_10_bits_meta_dataErr),
+    .io_msInfo_10_bits_metaTag                  (_mshrCtl_io_msInfo_10_bits_metaTag),
+    .io_msInfo_10_bits_dirHit                   (_mshrCtl_io_msInfo_10_bits_dirHit),
+    .io_msInfo_10_bits_w_grantfirst             (_mshrCtl_io_msInfo_10_bits_w_grantfirst),
+    .io_msInfo_10_bits_s_release                (_mshrCtl_io_msInfo_10_bits_s_release),
+    .io_msInfo_10_bits_s_cmoresp                (_mshrCtl_io_msInfo_10_bits_s_cmoresp),
+    .io_msInfo_10_bits_s_cmometaw               (_mshrCtl_io_msInfo_10_bits_s_cmometaw),
+    .io_msInfo_10_bits_w_releaseack             (_mshrCtl_io_msInfo_10_bits_w_releaseack),
+    .io_msInfo_10_bits_w_replResp               (_mshrCtl_io_msInfo_10_bits_w_replResp),
+    .io_msInfo_10_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_10_bits_w_rprobeacklast),
+    .io_msInfo_10_bits_replaceData              (_mshrCtl_io_msInfo_10_bits_replaceData),
+    .io_msInfo_10_bits_releaseToClean
+      (_mshrCtl_io_msInfo_10_bits_releaseToClean),
+    .io_msInfo_11_valid                         (_mshrCtl_io_msInfo_11_valid),
+    .io_msInfo_11_bits_set                      (_mshrCtl_io_msInfo_11_bits_set),
+    .io_msInfo_11_bits_reqTag                   (_mshrCtl_io_msInfo_11_bits_reqTag),
+    .io_msInfo_11_bits_willFree                 (_mshrCtl_io_msInfo_11_bits_willFree),
+    .io_msInfo_11_bits_aliasTask                (_mshrCtl_io_msInfo_11_bits_aliasTask),
+    .io_msInfo_11_bits_blockRefill              (_mshrCtl_io_msInfo_11_bits_blockRefill),
+    .io_msInfo_11_bits_meta_dirty               (_mshrCtl_io_msInfo_11_bits_meta_dirty),
+    .io_msInfo_11_bits_meta_state               (_mshrCtl_io_msInfo_11_bits_meta_state),
+    .io_msInfo_11_bits_meta_clients             (_mshrCtl_io_msInfo_11_bits_meta_clients),
+    .io_msInfo_11_bits_meta_alias               (_mshrCtl_io_msInfo_11_bits_meta_alias),
+    .io_msInfo_11_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_11_bits_meta_prefetch),
+    .io_msInfo_11_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_11_bits_meta_prefetchSrc),
+    .io_msInfo_11_bits_meta_accessed
+      (_mshrCtl_io_msInfo_11_bits_meta_accessed),
+    .io_msInfo_11_bits_meta_tagErr              (_mshrCtl_io_msInfo_11_bits_meta_tagErr),
+    .io_msInfo_11_bits_meta_dataErr             (_mshrCtl_io_msInfo_11_bits_meta_dataErr),
+    .io_msInfo_11_bits_metaTag                  (_mshrCtl_io_msInfo_11_bits_metaTag),
+    .io_msInfo_11_bits_dirHit                   (_mshrCtl_io_msInfo_11_bits_dirHit),
+    .io_msInfo_11_bits_w_grantfirst             (_mshrCtl_io_msInfo_11_bits_w_grantfirst),
+    .io_msInfo_11_bits_s_release                (_mshrCtl_io_msInfo_11_bits_s_release),
+    .io_msInfo_11_bits_s_cmoresp                (_mshrCtl_io_msInfo_11_bits_s_cmoresp),
+    .io_msInfo_11_bits_s_cmometaw               (_mshrCtl_io_msInfo_11_bits_s_cmometaw),
+    .io_msInfo_11_bits_w_releaseack             (_mshrCtl_io_msInfo_11_bits_w_releaseack),
+    .io_msInfo_11_bits_w_replResp               (_mshrCtl_io_msInfo_11_bits_w_replResp),
+    .io_msInfo_11_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_11_bits_w_rprobeacklast),
+    .io_msInfo_11_bits_replaceData              (_mshrCtl_io_msInfo_11_bits_replaceData),
+    .io_msInfo_11_bits_releaseToClean
+      (_mshrCtl_io_msInfo_11_bits_releaseToClean),
+    .io_msInfo_12_valid                         (_mshrCtl_io_msInfo_12_valid),
+    .io_msInfo_12_bits_set                      (_mshrCtl_io_msInfo_12_bits_set),
+    .io_msInfo_12_bits_reqTag                   (_mshrCtl_io_msInfo_12_bits_reqTag),
+    .io_msInfo_12_bits_willFree                 (_mshrCtl_io_msInfo_12_bits_willFree),
+    .io_msInfo_12_bits_aliasTask                (_mshrCtl_io_msInfo_12_bits_aliasTask),
+    .io_msInfo_12_bits_blockRefill              (_mshrCtl_io_msInfo_12_bits_blockRefill),
+    .io_msInfo_12_bits_meta_dirty               (_mshrCtl_io_msInfo_12_bits_meta_dirty),
+    .io_msInfo_12_bits_meta_state               (_mshrCtl_io_msInfo_12_bits_meta_state),
+    .io_msInfo_12_bits_meta_clients             (_mshrCtl_io_msInfo_12_bits_meta_clients),
+    .io_msInfo_12_bits_meta_alias               (_mshrCtl_io_msInfo_12_bits_meta_alias),
+    .io_msInfo_12_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_12_bits_meta_prefetch),
+    .io_msInfo_12_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_12_bits_meta_prefetchSrc),
+    .io_msInfo_12_bits_meta_accessed
+      (_mshrCtl_io_msInfo_12_bits_meta_accessed),
+    .io_msInfo_12_bits_meta_tagErr              (_mshrCtl_io_msInfo_12_bits_meta_tagErr),
+    .io_msInfo_12_bits_meta_dataErr             (_mshrCtl_io_msInfo_12_bits_meta_dataErr),
+    .io_msInfo_12_bits_metaTag                  (_mshrCtl_io_msInfo_12_bits_metaTag),
+    .io_msInfo_12_bits_dirHit                   (_mshrCtl_io_msInfo_12_bits_dirHit),
+    .io_msInfo_12_bits_w_grantfirst             (_mshrCtl_io_msInfo_12_bits_w_grantfirst),
+    .io_msInfo_12_bits_s_release                (_mshrCtl_io_msInfo_12_bits_s_release),
+    .io_msInfo_12_bits_s_cmoresp                (_mshrCtl_io_msInfo_12_bits_s_cmoresp),
+    .io_msInfo_12_bits_s_cmometaw               (_mshrCtl_io_msInfo_12_bits_s_cmometaw),
+    .io_msInfo_12_bits_w_releaseack             (_mshrCtl_io_msInfo_12_bits_w_releaseack),
+    .io_msInfo_12_bits_w_replResp               (_mshrCtl_io_msInfo_12_bits_w_replResp),
+    .io_msInfo_12_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_12_bits_w_rprobeacklast),
+    .io_msInfo_12_bits_replaceData              (_mshrCtl_io_msInfo_12_bits_replaceData),
+    .io_msInfo_12_bits_releaseToClean
+      (_mshrCtl_io_msInfo_12_bits_releaseToClean),
+    .io_msInfo_13_valid                         (_mshrCtl_io_msInfo_13_valid),
+    .io_msInfo_13_bits_set                      (_mshrCtl_io_msInfo_13_bits_set),
+    .io_msInfo_13_bits_reqTag                   (_mshrCtl_io_msInfo_13_bits_reqTag),
+    .io_msInfo_13_bits_willFree                 (_mshrCtl_io_msInfo_13_bits_willFree),
+    .io_msInfo_13_bits_aliasTask                (_mshrCtl_io_msInfo_13_bits_aliasTask),
+    .io_msInfo_13_bits_blockRefill              (_mshrCtl_io_msInfo_13_bits_blockRefill),
+    .io_msInfo_13_bits_meta_dirty               (_mshrCtl_io_msInfo_13_bits_meta_dirty),
+    .io_msInfo_13_bits_meta_state               (_mshrCtl_io_msInfo_13_bits_meta_state),
+    .io_msInfo_13_bits_meta_clients             (_mshrCtl_io_msInfo_13_bits_meta_clients),
+    .io_msInfo_13_bits_meta_alias               (_mshrCtl_io_msInfo_13_bits_meta_alias),
+    .io_msInfo_13_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_13_bits_meta_prefetch),
+    .io_msInfo_13_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_13_bits_meta_prefetchSrc),
+    .io_msInfo_13_bits_meta_accessed
+      (_mshrCtl_io_msInfo_13_bits_meta_accessed),
+    .io_msInfo_13_bits_meta_tagErr              (_mshrCtl_io_msInfo_13_bits_meta_tagErr),
+    .io_msInfo_13_bits_meta_dataErr             (_mshrCtl_io_msInfo_13_bits_meta_dataErr),
+    .io_msInfo_13_bits_metaTag                  (_mshrCtl_io_msInfo_13_bits_metaTag),
+    .io_msInfo_13_bits_dirHit                   (_mshrCtl_io_msInfo_13_bits_dirHit),
+    .io_msInfo_13_bits_w_grantfirst             (_mshrCtl_io_msInfo_13_bits_w_grantfirst),
+    .io_msInfo_13_bits_s_release                (_mshrCtl_io_msInfo_13_bits_s_release),
+    .io_msInfo_13_bits_s_cmoresp                (_mshrCtl_io_msInfo_13_bits_s_cmoresp),
+    .io_msInfo_13_bits_s_cmometaw               (_mshrCtl_io_msInfo_13_bits_s_cmometaw),
+    .io_msInfo_13_bits_w_releaseack             (_mshrCtl_io_msInfo_13_bits_w_releaseack),
+    .io_msInfo_13_bits_w_replResp               (_mshrCtl_io_msInfo_13_bits_w_replResp),
+    .io_msInfo_13_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_13_bits_w_rprobeacklast),
+    .io_msInfo_13_bits_replaceData              (_mshrCtl_io_msInfo_13_bits_replaceData),
+    .io_msInfo_13_bits_releaseToClean
+      (_mshrCtl_io_msInfo_13_bits_releaseToClean),
+    .io_msInfo_14_valid                         (_mshrCtl_io_msInfo_14_valid),
+    .io_msInfo_14_bits_set                      (_mshrCtl_io_msInfo_14_bits_set),
+    .io_msInfo_14_bits_reqTag                   (_mshrCtl_io_msInfo_14_bits_reqTag),
+    .io_msInfo_14_bits_willFree                 (_mshrCtl_io_msInfo_14_bits_willFree),
+    .io_msInfo_14_bits_aliasTask                (_mshrCtl_io_msInfo_14_bits_aliasTask),
+    .io_msInfo_14_bits_blockRefill              (_mshrCtl_io_msInfo_14_bits_blockRefill),
+    .io_msInfo_14_bits_meta_dirty               (_mshrCtl_io_msInfo_14_bits_meta_dirty),
+    .io_msInfo_14_bits_meta_state               (_mshrCtl_io_msInfo_14_bits_meta_state),
+    .io_msInfo_14_bits_meta_clients             (_mshrCtl_io_msInfo_14_bits_meta_clients),
+    .io_msInfo_14_bits_meta_alias               (_mshrCtl_io_msInfo_14_bits_meta_alias),
+    .io_msInfo_14_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_14_bits_meta_prefetch),
+    .io_msInfo_14_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_14_bits_meta_prefetchSrc),
+    .io_msInfo_14_bits_meta_accessed
+      (_mshrCtl_io_msInfo_14_bits_meta_accessed),
+    .io_msInfo_14_bits_meta_tagErr              (_mshrCtl_io_msInfo_14_bits_meta_tagErr),
+    .io_msInfo_14_bits_meta_dataErr             (_mshrCtl_io_msInfo_14_bits_meta_dataErr),
+    .io_msInfo_14_bits_metaTag                  (_mshrCtl_io_msInfo_14_bits_metaTag),
+    .io_msInfo_14_bits_dirHit                   (_mshrCtl_io_msInfo_14_bits_dirHit),
+    .io_msInfo_14_bits_w_grantfirst             (_mshrCtl_io_msInfo_14_bits_w_grantfirst),
+    .io_msInfo_14_bits_s_release                (_mshrCtl_io_msInfo_14_bits_s_release),
+    .io_msInfo_14_bits_s_cmoresp                (_mshrCtl_io_msInfo_14_bits_s_cmoresp),
+    .io_msInfo_14_bits_s_cmometaw               (_mshrCtl_io_msInfo_14_bits_s_cmometaw),
+    .io_msInfo_14_bits_w_releaseack             (_mshrCtl_io_msInfo_14_bits_w_releaseack),
+    .io_msInfo_14_bits_w_replResp               (_mshrCtl_io_msInfo_14_bits_w_replResp),
+    .io_msInfo_14_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_14_bits_w_rprobeacklast),
+    .io_msInfo_14_bits_replaceData              (_mshrCtl_io_msInfo_14_bits_replaceData),
+    .io_msInfo_14_bits_releaseToClean
+      (_mshrCtl_io_msInfo_14_bits_releaseToClean),
+    .io_msInfo_15_valid                         (_mshrCtl_io_msInfo_15_valid),
+    .io_msInfo_15_bits_set                      (_mshrCtl_io_msInfo_15_bits_set),
+    .io_msInfo_15_bits_reqTag                   (_mshrCtl_io_msInfo_15_bits_reqTag),
+    .io_msInfo_15_bits_willFree                 (_mshrCtl_io_msInfo_15_bits_willFree),
+    .io_msInfo_15_bits_aliasTask                (_mshrCtl_io_msInfo_15_bits_aliasTask),
+    .io_msInfo_15_bits_blockRefill              (_mshrCtl_io_msInfo_15_bits_blockRefill),
+    .io_msInfo_15_bits_meta_dirty               (_mshrCtl_io_msInfo_15_bits_meta_dirty),
+    .io_msInfo_15_bits_meta_state               (_mshrCtl_io_msInfo_15_bits_meta_state),
+    .io_msInfo_15_bits_meta_clients             (_mshrCtl_io_msInfo_15_bits_meta_clients),
+    .io_msInfo_15_bits_meta_alias               (_mshrCtl_io_msInfo_15_bits_meta_alias),
+    .io_msInfo_15_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_15_bits_meta_prefetch),
+    .io_msInfo_15_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_15_bits_meta_prefetchSrc),
+    .io_msInfo_15_bits_meta_accessed
+      (_mshrCtl_io_msInfo_15_bits_meta_accessed),
+    .io_msInfo_15_bits_meta_tagErr              (_mshrCtl_io_msInfo_15_bits_meta_tagErr),
+    .io_msInfo_15_bits_meta_dataErr             (_mshrCtl_io_msInfo_15_bits_meta_dataErr),
+    .io_msInfo_15_bits_metaTag                  (_mshrCtl_io_msInfo_15_bits_metaTag),
+    .io_msInfo_15_bits_dirHit                   (_mshrCtl_io_msInfo_15_bits_dirHit),
+    .io_msInfo_15_bits_w_grantfirst             (_mshrCtl_io_msInfo_15_bits_w_grantfirst),
+    .io_msInfo_15_bits_s_release                (_mshrCtl_io_msInfo_15_bits_s_release),
+    .io_msInfo_15_bits_s_cmoresp                (_mshrCtl_io_msInfo_15_bits_s_cmoresp),
+    .io_msInfo_15_bits_s_cmometaw               (_mshrCtl_io_msInfo_15_bits_s_cmometaw),
+    .io_msInfo_15_bits_w_releaseack             (_mshrCtl_io_msInfo_15_bits_w_releaseack),
+    .io_msInfo_15_bits_w_replResp               (_mshrCtl_io_msInfo_15_bits_w_replResp),
+    .io_msInfo_15_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_15_bits_w_rprobeacklast),
+    .io_msInfo_15_bits_replaceData              (_mshrCtl_io_msInfo_15_bits_replaceData),
+    .io_msInfo_15_bits_releaseToClean
+      (_mshrCtl_io_msInfo_15_bits_releaseToClean)
+  );
+  RXDAT rxdat (
+    .io_out_valid                     (io_out_rx_dat_valid),
+    .io_out_bits_txnID                (io_out_rx_dat_bits_txnID),
+    .io_out_bits_homeNID              (io_out_rx_dat_bits_homeNID),
+    .io_out_bits_opcode               (io_out_rx_dat_bits_opcode),
+    .io_out_bits_respErr              (io_out_rx_dat_bits_respErr),
+    .io_out_bits_resp                 (io_out_rx_dat_bits_resp),
+    .io_out_bits_dbID                 (io_out_rx_dat_bits_dbID),
+    .io_out_bits_dataID               (io_out_rx_dat_bits_dataID),
+    .io_out_bits_traceTag             (io_out_rx_dat_bits_traceTag),
+    .io_out_bits_data                 (io_out_rx_dat_bits_data),
+    .io_out_bits_dataCheck            (io_out_rx_dat_bits_dataCheck),
+    .io_out_bits_poison               (io_out_rx_dat_bits_poison),
+    .io_in_valid                      (_rxdat_io_in_valid),
+    .io_in_mshrId                     (_rxdat_io_in_mshrId),
+    .io_in_respInfo_last              (_rxdat_io_in_respInfo_last),
+    .io_in_respInfo_corrupt           (_rxdat_io_in_respInfo_corrupt),
+    .io_in_respInfo_chiOpcode         (_rxdat_io_in_respInfo_chiOpcode),
+    .io_in_respInfo_homeNID           (_rxdat_io_in_respInfo_homeNID),
+    .io_in_respInfo_dbID              (_rxdat_io_in_respInfo_dbID),
+    .io_in_respInfo_resp              (_rxdat_io_in_respInfo_resp),
+    .io_in_respInfo_respErr           (_rxdat_io_in_respInfo_respErr),
+    .io_in_respInfo_traceTag          (_rxdat_io_in_respInfo_traceTag),
+    .io_refillBufWrite_valid          (_rxdat_io_refillBufWrite_valid),
+    .io_refillBufWrite_bits_id        (_rxdat_io_refillBufWrite_bits_id),
+    .io_refillBufWrite_bits_data_data (_rxdat_io_refillBufWrite_bits_data_data),
+    .io_refillBufWrite_bits_beatMask  (_rxdat_io_refillBufWrite_bits_beatMask)
+  );
+  RXRSP rxrsp (
+    .io_out_valid             (io_out_rx_rsp_valid),
+    .io_out_bits_srcID        (io_out_rx_rsp_bits_srcID),
+    .io_out_bits_txnID        (io_out_rx_rsp_bits_txnID),
+    .io_out_bits_opcode       (io_out_rx_rsp_bits_opcode),
+    .io_out_bits_respErr      (io_out_rx_rsp_bits_respErr),
+    .io_out_bits_resp         (io_out_rx_rsp_bits_resp),
+    .io_out_bits_dbID         (io_out_rx_rsp_bits_dbID),
+    .io_out_bits_pCrdType     (io_out_rx_rsp_bits_pCrdType),
+    .io_out_bits_traceTag     (io_out_rx_rsp_bits_traceTag),
+    .io_in_valid              (_rxrsp_io_in_valid),
+    .io_in_mshrId             (_rxrsp_io_in_mshrId),
+    .io_in_respInfo_chiOpcode (_rxrsp_io_in_respInfo_chiOpcode),
+    .io_in_respInfo_srcID     (_rxrsp_io_in_respInfo_srcID),
+    .io_in_respInfo_dbID      (_rxrsp_io_in_respInfo_dbID),
+    .io_in_respInfo_resp      (_rxrsp_io_in_respInfo_resp),
+    .io_in_respInfo_pCrdType  (_rxrsp_io_in_respInfo_pCrdType),
+    .io_in_respInfo_respErr   (_rxrsp_io_in_respInfo_respErr),
+    .io_in_respInfo_traceTag  (_rxrsp_io_in_respInfo_traceTag)
+  );
+  wire [2:0]   childBd_array;
+  wire         childBd_all;
+  wire         childBd_req;
+  wire         childBd_writeen;
+  wire [7:0]   childBd_be;
+  wire [8:0]   childBd_addr;
+  wire [163:0] childBd_indata;
+  wire         childBd_readen;
+  wire [8:0]   childBd_addr_rd;
+  Directory directory (
+    .clock                                     (clock),
+    .reset                                     (reset),
+    .io_read_ready                             (_directory_io_read_ready),
+    .io_read_valid                             (_reqArb_io_dirRead_s1_valid),
+    .io_read_bits_tag                          (_reqArb_io_dirRead_s1_bits_tag),
+    .io_read_bits_set                          (_reqArb_io_dirRead_s1_bits_set),
+    .io_read_bits_wayMask                      (_reqArb_io_dirRead_s1_bits_wayMask),
+    .io_read_bits_replacerInfo_channel
+      (_reqArb_io_dirRead_s1_bits_replacerInfo_channel),
+    .io_read_bits_replacerInfo_opcode
+      (_reqArb_io_dirRead_s1_bits_replacerInfo_opcode),
+    .io_read_bits_replacerInfo_reqSource
+      (_reqArb_io_dirRead_s1_bits_replacerInfo_reqSource),
+    .io_read_bits_replacerInfo_refill_prefetch
+      (_reqArb_io_dirRead_s1_bits_replacerInfo_refill_prefetch),
+    .io_read_bits_refill                       (_reqArb_io_dirRead_s1_bits_refill),
+    .io_read_bits_mshrId                       (_reqArb_io_dirRead_s1_bits_mshrId),
+    .io_read_bits_cmoAll                       (_reqArb_io_dirRead_s1_bits_cmoAll),
+    .io_read_bits_cmoWay                       (_reqArb_io_dirRead_s1_bits_cmoWay),
+    .io_resp_valid                             (/* unused */),
+    .io_resp_bits_hit                          (_directory_io_resp_bits_hit),
+    .io_resp_bits_tag                          (_directory_io_resp_bits_tag),
+    .io_resp_bits_set                          (_directory_io_resp_bits_set),
+    .io_resp_bits_way                          (_directory_io_resp_bits_way),
+    .io_resp_bits_meta_dirty                   (/* unused */),
+    .io_resp_bits_meta_state                   (/* unused */),
+    .io_resp_bits_meta_clients                 (/* unused */),
+    .io_resp_bits_meta_alias                   (/* unused */),
+    .io_resp_bits_meta_prefetch                (/* unused */),
+    .io_resp_bits_meta_prefetchSrc             (/* unused */),
+    .io_resp_bits_meta_accessed                (/* unused */),
+    .io_resp_bits_meta_tagErr                  (_directory_io_resp_bits_meta_tagErr),
+    .io_resp_bits_meta_dataErr                 (_directory_io_resp_bits_meta_dataErr),
+    .io_resp_bits_error                        (_directory_io_resp_bits_error),
+    .io_resp_bits_replacerInfo_channel         (/* unused */),
+    .io_resp_bits_replacerInfo_opcode          (/* unused */),
+    .io_resp_bits_replacerInfo_reqSource       (/* unused */),
+    .io_resp_bits_replacerInfo_refill_prefetch (/* unused */),
+    .io_metaWReq_valid                         (_mainPipe_io_metaWReq_valid),
+    .io_metaWReq_bits_set                      (_mainPipe_io_metaWReq_bits_set),
+    .io_metaWReq_bits_wayOH                    (_mainPipe_io_metaWReq_bits_wayOH),
+    .io_metaWReq_bits_wmeta_dirty              (_mainPipe_io_metaWReq_bits_wmeta_dirty),
+    .io_metaWReq_bits_wmeta_state              (_mainPipe_io_metaWReq_bits_wmeta_state),
+    .io_metaWReq_bits_wmeta_clients            (_mainPipe_io_metaWReq_bits_wmeta_clients),
+    .io_metaWReq_bits_wmeta_alias              (_mainPipe_io_metaWReq_bits_wmeta_alias),
+    .io_metaWReq_bits_wmeta_prefetch
+      (_mainPipe_io_metaWReq_bits_wmeta_prefetch),
+    .io_metaWReq_bits_wmeta_prefetchSrc
+      (_mainPipe_io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_metaWReq_bits_wmeta_accessed
+      (_mainPipe_io_metaWReq_bits_wmeta_accessed),
+    .io_metaWReq_bits_wmeta_tagErr             (_mainPipe_io_metaWReq_bits_wmeta_tagErr),
+    .io_metaWReq_bits_wmeta_dataErr            (_mainPipe_io_metaWReq_bits_wmeta_dataErr),
+    .io_tagWReq_valid                          (_mainPipe_io_tagWReq_valid),
+    .io_tagWReq_bits_set                       (_mainPipe_io_tagWReq_bits_set),
+    .io_tagWReq_bits_wayOH                     (_mainPipe_io_tagWReq_bits_wayOH),
+    .io_tagWReq_bits_wtag                      (_mainPipe_io_tagWReq_bits_wtag),
+    .io_replResp_valid                         (_directory_io_replResp_valid),
+    .io_replResp_bits_tag                      (_directory_io_replResp_bits_tag),
+    .io_replResp_bits_set                      (/* unused */),
+    .io_replResp_bits_way                      (_directory_io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty               (_directory_io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state               (_directory_io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients             (_directory_io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias               (_directory_io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (_directory_io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (_directory_io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (_directory_io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr              (_directory_io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr             (_directory_io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_mshrId                   (_directory_io_replResp_bits_mshrId),
+    .io_replResp_bits_retry                    (_directory_io_replResp_bits_retry),
+    .io_replResp_bits_validHold                (_directory_io_replResp_bits_validHold),
+    .io_msInfo_0_valid                         (_mshrCtl_io_msInfo_0_valid),
+    .io_msInfo_0_bits_channel                  (_mshrCtl_io_msInfo_0_bits_channel),
+    .io_msInfo_0_bits_set                      (_mshrCtl_io_msInfo_0_bits_set),
+    .io_msInfo_0_bits_way                      (_mshrCtl_io_msInfo_0_bits_way),
+    .io_msInfo_0_bits_reqTag                   (_mshrCtl_io_msInfo_0_bits_reqTag),
+    .io_msInfo_0_bits_reqSource                (_mshrCtl_io_msInfo_0_bits_reqSource),
+    .io_msInfo_0_bits_willFree                 (_mshrCtl_io_msInfo_0_bits_willFree),
+    .io_msInfo_0_bits_aliasTask                (_mshrCtl_io_msInfo_0_bits_aliasTask),
+    .io_msInfo_0_bits_needRelease              (_mshrCtl_io_msInfo_0_bits_needRelease),
+    .io_msInfo_0_bits_blockRefill              (_mshrCtl_io_msInfo_0_bits_blockRefill),
+    .io_msInfo_0_bits_meta_dirty               (_mshrCtl_io_msInfo_0_bits_meta_dirty),
+    .io_msInfo_0_bits_meta_state               (_mshrCtl_io_msInfo_0_bits_meta_state),
+    .io_msInfo_0_bits_meta_clients             (_mshrCtl_io_msInfo_0_bits_meta_clients),
+    .io_msInfo_0_bits_meta_alias               (_mshrCtl_io_msInfo_0_bits_meta_alias),
+    .io_msInfo_0_bits_meta_prefetch            (_mshrCtl_io_msInfo_0_bits_meta_prefetch),
+    .io_msInfo_0_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_0_bits_meta_prefetchSrc),
+    .io_msInfo_0_bits_meta_accessed            (_mshrCtl_io_msInfo_0_bits_meta_accessed),
+    .io_msInfo_0_bits_meta_tagErr              (_mshrCtl_io_msInfo_0_bits_meta_tagErr),
+    .io_msInfo_0_bits_meta_dataErr             (_mshrCtl_io_msInfo_0_bits_meta_dataErr),
+    .io_msInfo_0_bits_metaTag                  (_mshrCtl_io_msInfo_0_bits_metaTag),
+    .io_msInfo_0_bits_dirHit                   (_mshrCtl_io_msInfo_0_bits_dirHit),
+    .io_msInfo_0_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_0_bits_isAcqOrPrefetch),
+    .io_msInfo_0_bits_isPrefetch               (_mshrCtl_io_msInfo_0_bits_isPrefetch),
+    .io_msInfo_0_bits_param                    (_mshrCtl_io_msInfo_0_bits_param),
+    .io_msInfo_0_bits_mergeA                   (_mshrCtl_io_msInfo_0_bits_mergeA),
+    .io_msInfo_0_bits_w_grantfirst             (_mshrCtl_io_msInfo_0_bits_w_grantfirst),
+    .io_msInfo_0_bits_w_grantlast              (_mshrCtl_io_msInfo_0_bits_w_grantlast),
+    .io_msInfo_0_bits_w_grant                  (_mshrCtl_io_msInfo_0_bits_w_grant),
+    .io_msInfo_0_bits_s_release                (_mshrCtl_io_msInfo_0_bits_s_release),
+    .io_msInfo_0_bits_s_refill                 (_mshrCtl_io_msInfo_0_bits_s_refill),
+    .io_msInfo_0_bits_s_cmoresp                (_mshrCtl_io_msInfo_0_bits_s_cmoresp),
+    .io_msInfo_0_bits_s_cmometaw               (_mshrCtl_io_msInfo_0_bits_s_cmometaw),
+    .io_msInfo_0_bits_w_releaseack             (_mshrCtl_io_msInfo_0_bits_w_releaseack),
+    .io_msInfo_0_bits_w_replResp               (_mshrCtl_io_msInfo_0_bits_w_replResp),
+    .io_msInfo_0_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_0_bits_w_rprobeacklast),
+    .io_msInfo_0_bits_replaceData              (_mshrCtl_io_msInfo_0_bits_replaceData),
+    .io_msInfo_0_bits_releaseToClean           (_mshrCtl_io_msInfo_0_bits_releaseToClean),
+    .io_msInfo_1_valid                         (_mshrCtl_io_msInfo_1_valid),
+    .io_msInfo_1_bits_channel                  (_mshrCtl_io_msInfo_1_bits_channel),
+    .io_msInfo_1_bits_set                      (_mshrCtl_io_msInfo_1_bits_set),
+    .io_msInfo_1_bits_way                      (_mshrCtl_io_msInfo_1_bits_way),
+    .io_msInfo_1_bits_reqTag                   (_mshrCtl_io_msInfo_1_bits_reqTag),
+    .io_msInfo_1_bits_reqSource                (_mshrCtl_io_msInfo_1_bits_reqSource),
+    .io_msInfo_1_bits_willFree                 (_mshrCtl_io_msInfo_1_bits_willFree),
+    .io_msInfo_1_bits_aliasTask                (_mshrCtl_io_msInfo_1_bits_aliasTask),
+    .io_msInfo_1_bits_needRelease              (_mshrCtl_io_msInfo_1_bits_needRelease),
+    .io_msInfo_1_bits_blockRefill              (_mshrCtl_io_msInfo_1_bits_blockRefill),
+    .io_msInfo_1_bits_meta_dirty               (_mshrCtl_io_msInfo_1_bits_meta_dirty),
+    .io_msInfo_1_bits_meta_state               (_mshrCtl_io_msInfo_1_bits_meta_state),
+    .io_msInfo_1_bits_meta_clients             (_mshrCtl_io_msInfo_1_bits_meta_clients),
+    .io_msInfo_1_bits_meta_alias               (_mshrCtl_io_msInfo_1_bits_meta_alias),
+    .io_msInfo_1_bits_meta_prefetch            (_mshrCtl_io_msInfo_1_bits_meta_prefetch),
+    .io_msInfo_1_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_1_bits_meta_prefetchSrc),
+    .io_msInfo_1_bits_meta_accessed            (_mshrCtl_io_msInfo_1_bits_meta_accessed),
+    .io_msInfo_1_bits_meta_tagErr              (_mshrCtl_io_msInfo_1_bits_meta_tagErr),
+    .io_msInfo_1_bits_meta_dataErr             (_mshrCtl_io_msInfo_1_bits_meta_dataErr),
+    .io_msInfo_1_bits_metaTag                  (_mshrCtl_io_msInfo_1_bits_metaTag),
+    .io_msInfo_1_bits_dirHit                   (_mshrCtl_io_msInfo_1_bits_dirHit),
+    .io_msInfo_1_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_1_bits_isAcqOrPrefetch),
+    .io_msInfo_1_bits_isPrefetch               (_mshrCtl_io_msInfo_1_bits_isPrefetch),
+    .io_msInfo_1_bits_param                    (_mshrCtl_io_msInfo_1_bits_param),
+    .io_msInfo_1_bits_mergeA                   (_mshrCtl_io_msInfo_1_bits_mergeA),
+    .io_msInfo_1_bits_w_grantfirst             (_mshrCtl_io_msInfo_1_bits_w_grantfirst),
+    .io_msInfo_1_bits_w_grantlast              (_mshrCtl_io_msInfo_1_bits_w_grantlast),
+    .io_msInfo_1_bits_w_grant                  (_mshrCtl_io_msInfo_1_bits_w_grant),
+    .io_msInfo_1_bits_s_release                (_mshrCtl_io_msInfo_1_bits_s_release),
+    .io_msInfo_1_bits_s_refill                 (_mshrCtl_io_msInfo_1_bits_s_refill),
+    .io_msInfo_1_bits_s_cmoresp                (_mshrCtl_io_msInfo_1_bits_s_cmoresp),
+    .io_msInfo_1_bits_s_cmometaw               (_mshrCtl_io_msInfo_1_bits_s_cmometaw),
+    .io_msInfo_1_bits_w_releaseack             (_mshrCtl_io_msInfo_1_bits_w_releaseack),
+    .io_msInfo_1_bits_w_replResp               (_mshrCtl_io_msInfo_1_bits_w_replResp),
+    .io_msInfo_1_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_1_bits_w_rprobeacklast),
+    .io_msInfo_1_bits_replaceData              (_mshrCtl_io_msInfo_1_bits_replaceData),
+    .io_msInfo_1_bits_releaseToClean           (_mshrCtl_io_msInfo_1_bits_releaseToClean),
+    .io_msInfo_2_valid                         (_mshrCtl_io_msInfo_2_valid),
+    .io_msInfo_2_bits_channel                  (_mshrCtl_io_msInfo_2_bits_channel),
+    .io_msInfo_2_bits_set                      (_mshrCtl_io_msInfo_2_bits_set),
+    .io_msInfo_2_bits_way                      (_mshrCtl_io_msInfo_2_bits_way),
+    .io_msInfo_2_bits_reqTag                   (_mshrCtl_io_msInfo_2_bits_reqTag),
+    .io_msInfo_2_bits_reqSource                (_mshrCtl_io_msInfo_2_bits_reqSource),
+    .io_msInfo_2_bits_willFree                 (_mshrCtl_io_msInfo_2_bits_willFree),
+    .io_msInfo_2_bits_aliasTask                (_mshrCtl_io_msInfo_2_bits_aliasTask),
+    .io_msInfo_2_bits_needRelease              (_mshrCtl_io_msInfo_2_bits_needRelease),
+    .io_msInfo_2_bits_blockRefill              (_mshrCtl_io_msInfo_2_bits_blockRefill),
+    .io_msInfo_2_bits_meta_dirty               (_mshrCtl_io_msInfo_2_bits_meta_dirty),
+    .io_msInfo_2_bits_meta_state               (_mshrCtl_io_msInfo_2_bits_meta_state),
+    .io_msInfo_2_bits_meta_clients             (_mshrCtl_io_msInfo_2_bits_meta_clients),
+    .io_msInfo_2_bits_meta_alias               (_mshrCtl_io_msInfo_2_bits_meta_alias),
+    .io_msInfo_2_bits_meta_prefetch            (_mshrCtl_io_msInfo_2_bits_meta_prefetch),
+    .io_msInfo_2_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_2_bits_meta_prefetchSrc),
+    .io_msInfo_2_bits_meta_accessed            (_mshrCtl_io_msInfo_2_bits_meta_accessed),
+    .io_msInfo_2_bits_meta_tagErr              (_mshrCtl_io_msInfo_2_bits_meta_tagErr),
+    .io_msInfo_2_bits_meta_dataErr             (_mshrCtl_io_msInfo_2_bits_meta_dataErr),
+    .io_msInfo_2_bits_metaTag                  (_mshrCtl_io_msInfo_2_bits_metaTag),
+    .io_msInfo_2_bits_dirHit                   (_mshrCtl_io_msInfo_2_bits_dirHit),
+    .io_msInfo_2_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_2_bits_isAcqOrPrefetch),
+    .io_msInfo_2_bits_isPrefetch               (_mshrCtl_io_msInfo_2_bits_isPrefetch),
+    .io_msInfo_2_bits_param                    (_mshrCtl_io_msInfo_2_bits_param),
+    .io_msInfo_2_bits_mergeA                   (_mshrCtl_io_msInfo_2_bits_mergeA),
+    .io_msInfo_2_bits_w_grantfirst             (_mshrCtl_io_msInfo_2_bits_w_grantfirst),
+    .io_msInfo_2_bits_w_grantlast              (_mshrCtl_io_msInfo_2_bits_w_grantlast),
+    .io_msInfo_2_bits_w_grant                  (_mshrCtl_io_msInfo_2_bits_w_grant),
+    .io_msInfo_2_bits_s_release                (_mshrCtl_io_msInfo_2_bits_s_release),
+    .io_msInfo_2_bits_s_refill                 (_mshrCtl_io_msInfo_2_bits_s_refill),
+    .io_msInfo_2_bits_s_cmoresp                (_mshrCtl_io_msInfo_2_bits_s_cmoresp),
+    .io_msInfo_2_bits_s_cmometaw               (_mshrCtl_io_msInfo_2_bits_s_cmometaw),
+    .io_msInfo_2_bits_w_releaseack             (_mshrCtl_io_msInfo_2_bits_w_releaseack),
+    .io_msInfo_2_bits_w_replResp               (_mshrCtl_io_msInfo_2_bits_w_replResp),
+    .io_msInfo_2_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_2_bits_w_rprobeacklast),
+    .io_msInfo_2_bits_replaceData              (_mshrCtl_io_msInfo_2_bits_replaceData),
+    .io_msInfo_2_bits_releaseToClean           (_mshrCtl_io_msInfo_2_bits_releaseToClean),
+    .io_msInfo_3_valid                         (_mshrCtl_io_msInfo_3_valid),
+    .io_msInfo_3_bits_channel                  (_mshrCtl_io_msInfo_3_bits_channel),
+    .io_msInfo_3_bits_set                      (_mshrCtl_io_msInfo_3_bits_set),
+    .io_msInfo_3_bits_way                      (_mshrCtl_io_msInfo_3_bits_way),
+    .io_msInfo_3_bits_reqTag                   (_mshrCtl_io_msInfo_3_bits_reqTag),
+    .io_msInfo_3_bits_reqSource                (_mshrCtl_io_msInfo_3_bits_reqSource),
+    .io_msInfo_3_bits_willFree                 (_mshrCtl_io_msInfo_3_bits_willFree),
+    .io_msInfo_3_bits_aliasTask                (_mshrCtl_io_msInfo_3_bits_aliasTask),
+    .io_msInfo_3_bits_needRelease              (_mshrCtl_io_msInfo_3_bits_needRelease),
+    .io_msInfo_3_bits_blockRefill              (_mshrCtl_io_msInfo_3_bits_blockRefill),
+    .io_msInfo_3_bits_meta_dirty               (_mshrCtl_io_msInfo_3_bits_meta_dirty),
+    .io_msInfo_3_bits_meta_state               (_mshrCtl_io_msInfo_3_bits_meta_state),
+    .io_msInfo_3_bits_meta_clients             (_mshrCtl_io_msInfo_3_bits_meta_clients),
+    .io_msInfo_3_bits_meta_alias               (_mshrCtl_io_msInfo_3_bits_meta_alias),
+    .io_msInfo_3_bits_meta_prefetch            (_mshrCtl_io_msInfo_3_bits_meta_prefetch),
+    .io_msInfo_3_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_3_bits_meta_prefetchSrc),
+    .io_msInfo_3_bits_meta_accessed            (_mshrCtl_io_msInfo_3_bits_meta_accessed),
+    .io_msInfo_3_bits_meta_tagErr              (_mshrCtl_io_msInfo_3_bits_meta_tagErr),
+    .io_msInfo_3_bits_meta_dataErr             (_mshrCtl_io_msInfo_3_bits_meta_dataErr),
+    .io_msInfo_3_bits_metaTag                  (_mshrCtl_io_msInfo_3_bits_metaTag),
+    .io_msInfo_3_bits_dirHit                   (_mshrCtl_io_msInfo_3_bits_dirHit),
+    .io_msInfo_3_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_3_bits_isAcqOrPrefetch),
+    .io_msInfo_3_bits_isPrefetch               (_mshrCtl_io_msInfo_3_bits_isPrefetch),
+    .io_msInfo_3_bits_param                    (_mshrCtl_io_msInfo_3_bits_param),
+    .io_msInfo_3_bits_mergeA                   (_mshrCtl_io_msInfo_3_bits_mergeA),
+    .io_msInfo_3_bits_w_grantfirst             (_mshrCtl_io_msInfo_3_bits_w_grantfirst),
+    .io_msInfo_3_bits_w_grantlast              (_mshrCtl_io_msInfo_3_bits_w_grantlast),
+    .io_msInfo_3_bits_w_grant                  (_mshrCtl_io_msInfo_3_bits_w_grant),
+    .io_msInfo_3_bits_s_release                (_mshrCtl_io_msInfo_3_bits_s_release),
+    .io_msInfo_3_bits_s_refill                 (_mshrCtl_io_msInfo_3_bits_s_refill),
+    .io_msInfo_3_bits_s_cmoresp                (_mshrCtl_io_msInfo_3_bits_s_cmoresp),
+    .io_msInfo_3_bits_s_cmometaw               (_mshrCtl_io_msInfo_3_bits_s_cmometaw),
+    .io_msInfo_3_bits_w_releaseack             (_mshrCtl_io_msInfo_3_bits_w_releaseack),
+    .io_msInfo_3_bits_w_replResp               (_mshrCtl_io_msInfo_3_bits_w_replResp),
+    .io_msInfo_3_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_3_bits_w_rprobeacklast),
+    .io_msInfo_3_bits_replaceData              (_mshrCtl_io_msInfo_3_bits_replaceData),
+    .io_msInfo_3_bits_releaseToClean           (_mshrCtl_io_msInfo_3_bits_releaseToClean),
+    .io_msInfo_4_valid                         (_mshrCtl_io_msInfo_4_valid),
+    .io_msInfo_4_bits_channel                  (_mshrCtl_io_msInfo_4_bits_channel),
+    .io_msInfo_4_bits_set                      (_mshrCtl_io_msInfo_4_bits_set),
+    .io_msInfo_4_bits_way                      (_mshrCtl_io_msInfo_4_bits_way),
+    .io_msInfo_4_bits_reqTag                   (_mshrCtl_io_msInfo_4_bits_reqTag),
+    .io_msInfo_4_bits_reqSource                (_mshrCtl_io_msInfo_4_bits_reqSource),
+    .io_msInfo_4_bits_willFree                 (_mshrCtl_io_msInfo_4_bits_willFree),
+    .io_msInfo_4_bits_aliasTask                (_mshrCtl_io_msInfo_4_bits_aliasTask),
+    .io_msInfo_4_bits_needRelease              (_mshrCtl_io_msInfo_4_bits_needRelease),
+    .io_msInfo_4_bits_blockRefill              (_mshrCtl_io_msInfo_4_bits_blockRefill),
+    .io_msInfo_4_bits_meta_dirty               (_mshrCtl_io_msInfo_4_bits_meta_dirty),
+    .io_msInfo_4_bits_meta_state               (_mshrCtl_io_msInfo_4_bits_meta_state),
+    .io_msInfo_4_bits_meta_clients             (_mshrCtl_io_msInfo_4_bits_meta_clients),
+    .io_msInfo_4_bits_meta_alias               (_mshrCtl_io_msInfo_4_bits_meta_alias),
+    .io_msInfo_4_bits_meta_prefetch            (_mshrCtl_io_msInfo_4_bits_meta_prefetch),
+    .io_msInfo_4_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_4_bits_meta_prefetchSrc),
+    .io_msInfo_4_bits_meta_accessed            (_mshrCtl_io_msInfo_4_bits_meta_accessed),
+    .io_msInfo_4_bits_meta_tagErr              (_mshrCtl_io_msInfo_4_bits_meta_tagErr),
+    .io_msInfo_4_bits_meta_dataErr             (_mshrCtl_io_msInfo_4_bits_meta_dataErr),
+    .io_msInfo_4_bits_metaTag                  (_mshrCtl_io_msInfo_4_bits_metaTag),
+    .io_msInfo_4_bits_dirHit                   (_mshrCtl_io_msInfo_4_bits_dirHit),
+    .io_msInfo_4_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_4_bits_isAcqOrPrefetch),
+    .io_msInfo_4_bits_isPrefetch               (_mshrCtl_io_msInfo_4_bits_isPrefetch),
+    .io_msInfo_4_bits_param                    (_mshrCtl_io_msInfo_4_bits_param),
+    .io_msInfo_4_bits_mergeA                   (_mshrCtl_io_msInfo_4_bits_mergeA),
+    .io_msInfo_4_bits_w_grantfirst             (_mshrCtl_io_msInfo_4_bits_w_grantfirst),
+    .io_msInfo_4_bits_w_grantlast              (_mshrCtl_io_msInfo_4_bits_w_grantlast),
+    .io_msInfo_4_bits_w_grant                  (_mshrCtl_io_msInfo_4_bits_w_grant),
+    .io_msInfo_4_bits_s_release                (_mshrCtl_io_msInfo_4_bits_s_release),
+    .io_msInfo_4_bits_s_refill                 (_mshrCtl_io_msInfo_4_bits_s_refill),
+    .io_msInfo_4_bits_s_cmoresp                (_mshrCtl_io_msInfo_4_bits_s_cmoresp),
+    .io_msInfo_4_bits_s_cmometaw               (_mshrCtl_io_msInfo_4_bits_s_cmometaw),
+    .io_msInfo_4_bits_w_releaseack             (_mshrCtl_io_msInfo_4_bits_w_releaseack),
+    .io_msInfo_4_bits_w_replResp               (_mshrCtl_io_msInfo_4_bits_w_replResp),
+    .io_msInfo_4_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_4_bits_w_rprobeacklast),
+    .io_msInfo_4_bits_replaceData              (_mshrCtl_io_msInfo_4_bits_replaceData),
+    .io_msInfo_4_bits_releaseToClean           (_mshrCtl_io_msInfo_4_bits_releaseToClean),
+    .io_msInfo_5_valid                         (_mshrCtl_io_msInfo_5_valid),
+    .io_msInfo_5_bits_channel                  (_mshrCtl_io_msInfo_5_bits_channel),
+    .io_msInfo_5_bits_set                      (_mshrCtl_io_msInfo_5_bits_set),
+    .io_msInfo_5_bits_way                      (_mshrCtl_io_msInfo_5_bits_way),
+    .io_msInfo_5_bits_reqTag                   (_mshrCtl_io_msInfo_5_bits_reqTag),
+    .io_msInfo_5_bits_reqSource                (_mshrCtl_io_msInfo_5_bits_reqSource),
+    .io_msInfo_5_bits_willFree                 (_mshrCtl_io_msInfo_5_bits_willFree),
+    .io_msInfo_5_bits_aliasTask                (_mshrCtl_io_msInfo_5_bits_aliasTask),
+    .io_msInfo_5_bits_needRelease              (_mshrCtl_io_msInfo_5_bits_needRelease),
+    .io_msInfo_5_bits_blockRefill              (_mshrCtl_io_msInfo_5_bits_blockRefill),
+    .io_msInfo_5_bits_meta_dirty               (_mshrCtl_io_msInfo_5_bits_meta_dirty),
+    .io_msInfo_5_bits_meta_state               (_mshrCtl_io_msInfo_5_bits_meta_state),
+    .io_msInfo_5_bits_meta_clients             (_mshrCtl_io_msInfo_5_bits_meta_clients),
+    .io_msInfo_5_bits_meta_alias               (_mshrCtl_io_msInfo_5_bits_meta_alias),
+    .io_msInfo_5_bits_meta_prefetch            (_mshrCtl_io_msInfo_5_bits_meta_prefetch),
+    .io_msInfo_5_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_5_bits_meta_prefetchSrc),
+    .io_msInfo_5_bits_meta_accessed            (_mshrCtl_io_msInfo_5_bits_meta_accessed),
+    .io_msInfo_5_bits_meta_tagErr              (_mshrCtl_io_msInfo_5_bits_meta_tagErr),
+    .io_msInfo_5_bits_meta_dataErr             (_mshrCtl_io_msInfo_5_bits_meta_dataErr),
+    .io_msInfo_5_bits_metaTag                  (_mshrCtl_io_msInfo_5_bits_metaTag),
+    .io_msInfo_5_bits_dirHit                   (_mshrCtl_io_msInfo_5_bits_dirHit),
+    .io_msInfo_5_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_5_bits_isAcqOrPrefetch),
+    .io_msInfo_5_bits_isPrefetch               (_mshrCtl_io_msInfo_5_bits_isPrefetch),
+    .io_msInfo_5_bits_param                    (_mshrCtl_io_msInfo_5_bits_param),
+    .io_msInfo_5_bits_mergeA                   (_mshrCtl_io_msInfo_5_bits_mergeA),
+    .io_msInfo_5_bits_w_grantfirst             (_mshrCtl_io_msInfo_5_bits_w_grantfirst),
+    .io_msInfo_5_bits_w_grantlast              (_mshrCtl_io_msInfo_5_bits_w_grantlast),
+    .io_msInfo_5_bits_w_grant                  (_mshrCtl_io_msInfo_5_bits_w_grant),
+    .io_msInfo_5_bits_s_release                (_mshrCtl_io_msInfo_5_bits_s_release),
+    .io_msInfo_5_bits_s_refill                 (_mshrCtl_io_msInfo_5_bits_s_refill),
+    .io_msInfo_5_bits_s_cmoresp                (_mshrCtl_io_msInfo_5_bits_s_cmoresp),
+    .io_msInfo_5_bits_s_cmometaw               (_mshrCtl_io_msInfo_5_bits_s_cmometaw),
+    .io_msInfo_5_bits_w_releaseack             (_mshrCtl_io_msInfo_5_bits_w_releaseack),
+    .io_msInfo_5_bits_w_replResp               (_mshrCtl_io_msInfo_5_bits_w_replResp),
+    .io_msInfo_5_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_5_bits_w_rprobeacklast),
+    .io_msInfo_5_bits_replaceData              (_mshrCtl_io_msInfo_5_bits_replaceData),
+    .io_msInfo_5_bits_releaseToClean           (_mshrCtl_io_msInfo_5_bits_releaseToClean),
+    .io_msInfo_6_valid                         (_mshrCtl_io_msInfo_6_valid),
+    .io_msInfo_6_bits_channel                  (_mshrCtl_io_msInfo_6_bits_channel),
+    .io_msInfo_6_bits_set                      (_mshrCtl_io_msInfo_6_bits_set),
+    .io_msInfo_6_bits_way                      (_mshrCtl_io_msInfo_6_bits_way),
+    .io_msInfo_6_bits_reqTag                   (_mshrCtl_io_msInfo_6_bits_reqTag),
+    .io_msInfo_6_bits_reqSource                (_mshrCtl_io_msInfo_6_bits_reqSource),
+    .io_msInfo_6_bits_willFree                 (_mshrCtl_io_msInfo_6_bits_willFree),
+    .io_msInfo_6_bits_aliasTask                (_mshrCtl_io_msInfo_6_bits_aliasTask),
+    .io_msInfo_6_bits_needRelease              (_mshrCtl_io_msInfo_6_bits_needRelease),
+    .io_msInfo_6_bits_blockRefill              (_mshrCtl_io_msInfo_6_bits_blockRefill),
+    .io_msInfo_6_bits_meta_dirty               (_mshrCtl_io_msInfo_6_bits_meta_dirty),
+    .io_msInfo_6_bits_meta_state               (_mshrCtl_io_msInfo_6_bits_meta_state),
+    .io_msInfo_6_bits_meta_clients             (_mshrCtl_io_msInfo_6_bits_meta_clients),
+    .io_msInfo_6_bits_meta_alias               (_mshrCtl_io_msInfo_6_bits_meta_alias),
+    .io_msInfo_6_bits_meta_prefetch            (_mshrCtl_io_msInfo_6_bits_meta_prefetch),
+    .io_msInfo_6_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_6_bits_meta_prefetchSrc),
+    .io_msInfo_6_bits_meta_accessed            (_mshrCtl_io_msInfo_6_bits_meta_accessed),
+    .io_msInfo_6_bits_meta_tagErr              (_mshrCtl_io_msInfo_6_bits_meta_tagErr),
+    .io_msInfo_6_bits_meta_dataErr             (_mshrCtl_io_msInfo_6_bits_meta_dataErr),
+    .io_msInfo_6_bits_metaTag                  (_mshrCtl_io_msInfo_6_bits_metaTag),
+    .io_msInfo_6_bits_dirHit                   (_mshrCtl_io_msInfo_6_bits_dirHit),
+    .io_msInfo_6_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_6_bits_isAcqOrPrefetch),
+    .io_msInfo_6_bits_isPrefetch               (_mshrCtl_io_msInfo_6_bits_isPrefetch),
+    .io_msInfo_6_bits_param                    (_mshrCtl_io_msInfo_6_bits_param),
+    .io_msInfo_6_bits_mergeA                   (_mshrCtl_io_msInfo_6_bits_mergeA),
+    .io_msInfo_6_bits_w_grantfirst             (_mshrCtl_io_msInfo_6_bits_w_grantfirst),
+    .io_msInfo_6_bits_w_grantlast              (_mshrCtl_io_msInfo_6_bits_w_grantlast),
+    .io_msInfo_6_bits_w_grant                  (_mshrCtl_io_msInfo_6_bits_w_grant),
+    .io_msInfo_6_bits_s_release                (_mshrCtl_io_msInfo_6_bits_s_release),
+    .io_msInfo_6_bits_s_refill                 (_mshrCtl_io_msInfo_6_bits_s_refill),
+    .io_msInfo_6_bits_s_cmoresp                (_mshrCtl_io_msInfo_6_bits_s_cmoresp),
+    .io_msInfo_6_bits_s_cmometaw               (_mshrCtl_io_msInfo_6_bits_s_cmometaw),
+    .io_msInfo_6_bits_w_releaseack             (_mshrCtl_io_msInfo_6_bits_w_releaseack),
+    .io_msInfo_6_bits_w_replResp               (_mshrCtl_io_msInfo_6_bits_w_replResp),
+    .io_msInfo_6_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_6_bits_w_rprobeacklast),
+    .io_msInfo_6_bits_replaceData              (_mshrCtl_io_msInfo_6_bits_replaceData),
+    .io_msInfo_6_bits_releaseToClean           (_mshrCtl_io_msInfo_6_bits_releaseToClean),
+    .io_msInfo_7_valid                         (_mshrCtl_io_msInfo_7_valid),
+    .io_msInfo_7_bits_channel                  (_mshrCtl_io_msInfo_7_bits_channel),
+    .io_msInfo_7_bits_set                      (_mshrCtl_io_msInfo_7_bits_set),
+    .io_msInfo_7_bits_way                      (_mshrCtl_io_msInfo_7_bits_way),
+    .io_msInfo_7_bits_reqTag                   (_mshrCtl_io_msInfo_7_bits_reqTag),
+    .io_msInfo_7_bits_reqSource                (_mshrCtl_io_msInfo_7_bits_reqSource),
+    .io_msInfo_7_bits_willFree                 (_mshrCtl_io_msInfo_7_bits_willFree),
+    .io_msInfo_7_bits_aliasTask                (_mshrCtl_io_msInfo_7_bits_aliasTask),
+    .io_msInfo_7_bits_needRelease              (_mshrCtl_io_msInfo_7_bits_needRelease),
+    .io_msInfo_7_bits_blockRefill              (_mshrCtl_io_msInfo_7_bits_blockRefill),
+    .io_msInfo_7_bits_meta_dirty               (_mshrCtl_io_msInfo_7_bits_meta_dirty),
+    .io_msInfo_7_bits_meta_state               (_mshrCtl_io_msInfo_7_bits_meta_state),
+    .io_msInfo_7_bits_meta_clients             (_mshrCtl_io_msInfo_7_bits_meta_clients),
+    .io_msInfo_7_bits_meta_alias               (_mshrCtl_io_msInfo_7_bits_meta_alias),
+    .io_msInfo_7_bits_meta_prefetch            (_mshrCtl_io_msInfo_7_bits_meta_prefetch),
+    .io_msInfo_7_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_7_bits_meta_prefetchSrc),
+    .io_msInfo_7_bits_meta_accessed            (_mshrCtl_io_msInfo_7_bits_meta_accessed),
+    .io_msInfo_7_bits_meta_tagErr              (_mshrCtl_io_msInfo_7_bits_meta_tagErr),
+    .io_msInfo_7_bits_meta_dataErr             (_mshrCtl_io_msInfo_7_bits_meta_dataErr),
+    .io_msInfo_7_bits_metaTag                  (_mshrCtl_io_msInfo_7_bits_metaTag),
+    .io_msInfo_7_bits_dirHit                   (_mshrCtl_io_msInfo_7_bits_dirHit),
+    .io_msInfo_7_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_7_bits_isAcqOrPrefetch),
+    .io_msInfo_7_bits_isPrefetch               (_mshrCtl_io_msInfo_7_bits_isPrefetch),
+    .io_msInfo_7_bits_param                    (_mshrCtl_io_msInfo_7_bits_param),
+    .io_msInfo_7_bits_mergeA                   (_mshrCtl_io_msInfo_7_bits_mergeA),
+    .io_msInfo_7_bits_w_grantfirst             (_mshrCtl_io_msInfo_7_bits_w_grantfirst),
+    .io_msInfo_7_bits_w_grantlast              (_mshrCtl_io_msInfo_7_bits_w_grantlast),
+    .io_msInfo_7_bits_w_grant                  (_mshrCtl_io_msInfo_7_bits_w_grant),
+    .io_msInfo_7_bits_s_release                (_mshrCtl_io_msInfo_7_bits_s_release),
+    .io_msInfo_7_bits_s_refill                 (_mshrCtl_io_msInfo_7_bits_s_refill),
+    .io_msInfo_7_bits_s_cmoresp                (_mshrCtl_io_msInfo_7_bits_s_cmoresp),
+    .io_msInfo_7_bits_s_cmometaw               (_mshrCtl_io_msInfo_7_bits_s_cmometaw),
+    .io_msInfo_7_bits_w_releaseack             (_mshrCtl_io_msInfo_7_bits_w_releaseack),
+    .io_msInfo_7_bits_w_replResp               (_mshrCtl_io_msInfo_7_bits_w_replResp),
+    .io_msInfo_7_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_7_bits_w_rprobeacklast),
+    .io_msInfo_7_bits_replaceData              (_mshrCtl_io_msInfo_7_bits_replaceData),
+    .io_msInfo_7_bits_releaseToClean           (_mshrCtl_io_msInfo_7_bits_releaseToClean),
+    .io_msInfo_8_valid                         (_mshrCtl_io_msInfo_8_valid),
+    .io_msInfo_8_bits_channel                  (_mshrCtl_io_msInfo_8_bits_channel),
+    .io_msInfo_8_bits_set                      (_mshrCtl_io_msInfo_8_bits_set),
+    .io_msInfo_8_bits_way                      (_mshrCtl_io_msInfo_8_bits_way),
+    .io_msInfo_8_bits_reqTag                   (_mshrCtl_io_msInfo_8_bits_reqTag),
+    .io_msInfo_8_bits_reqSource                (_mshrCtl_io_msInfo_8_bits_reqSource),
+    .io_msInfo_8_bits_willFree                 (_mshrCtl_io_msInfo_8_bits_willFree),
+    .io_msInfo_8_bits_aliasTask                (_mshrCtl_io_msInfo_8_bits_aliasTask),
+    .io_msInfo_8_bits_needRelease              (_mshrCtl_io_msInfo_8_bits_needRelease),
+    .io_msInfo_8_bits_blockRefill              (_mshrCtl_io_msInfo_8_bits_blockRefill),
+    .io_msInfo_8_bits_meta_dirty               (_mshrCtl_io_msInfo_8_bits_meta_dirty),
+    .io_msInfo_8_bits_meta_state               (_mshrCtl_io_msInfo_8_bits_meta_state),
+    .io_msInfo_8_bits_meta_clients             (_mshrCtl_io_msInfo_8_bits_meta_clients),
+    .io_msInfo_8_bits_meta_alias               (_mshrCtl_io_msInfo_8_bits_meta_alias),
+    .io_msInfo_8_bits_meta_prefetch            (_mshrCtl_io_msInfo_8_bits_meta_prefetch),
+    .io_msInfo_8_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_8_bits_meta_prefetchSrc),
+    .io_msInfo_8_bits_meta_accessed            (_mshrCtl_io_msInfo_8_bits_meta_accessed),
+    .io_msInfo_8_bits_meta_tagErr              (_mshrCtl_io_msInfo_8_bits_meta_tagErr),
+    .io_msInfo_8_bits_meta_dataErr             (_mshrCtl_io_msInfo_8_bits_meta_dataErr),
+    .io_msInfo_8_bits_metaTag                  (_mshrCtl_io_msInfo_8_bits_metaTag),
+    .io_msInfo_8_bits_dirHit                   (_mshrCtl_io_msInfo_8_bits_dirHit),
+    .io_msInfo_8_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_8_bits_isAcqOrPrefetch),
+    .io_msInfo_8_bits_isPrefetch               (_mshrCtl_io_msInfo_8_bits_isPrefetch),
+    .io_msInfo_8_bits_param                    (_mshrCtl_io_msInfo_8_bits_param),
+    .io_msInfo_8_bits_mergeA                   (_mshrCtl_io_msInfo_8_bits_mergeA),
+    .io_msInfo_8_bits_w_grantfirst             (_mshrCtl_io_msInfo_8_bits_w_grantfirst),
+    .io_msInfo_8_bits_w_grantlast              (_mshrCtl_io_msInfo_8_bits_w_grantlast),
+    .io_msInfo_8_bits_w_grant                  (_mshrCtl_io_msInfo_8_bits_w_grant),
+    .io_msInfo_8_bits_s_release                (_mshrCtl_io_msInfo_8_bits_s_release),
+    .io_msInfo_8_bits_s_refill                 (_mshrCtl_io_msInfo_8_bits_s_refill),
+    .io_msInfo_8_bits_s_cmoresp                (_mshrCtl_io_msInfo_8_bits_s_cmoresp),
+    .io_msInfo_8_bits_s_cmometaw               (_mshrCtl_io_msInfo_8_bits_s_cmometaw),
+    .io_msInfo_8_bits_w_releaseack             (_mshrCtl_io_msInfo_8_bits_w_releaseack),
+    .io_msInfo_8_bits_w_replResp               (_mshrCtl_io_msInfo_8_bits_w_replResp),
+    .io_msInfo_8_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_8_bits_w_rprobeacklast),
+    .io_msInfo_8_bits_replaceData              (_mshrCtl_io_msInfo_8_bits_replaceData),
+    .io_msInfo_8_bits_releaseToClean           (_mshrCtl_io_msInfo_8_bits_releaseToClean),
+    .io_msInfo_9_valid                         (_mshrCtl_io_msInfo_9_valid),
+    .io_msInfo_9_bits_channel                  (_mshrCtl_io_msInfo_9_bits_channel),
+    .io_msInfo_9_bits_set                      (_mshrCtl_io_msInfo_9_bits_set),
+    .io_msInfo_9_bits_way                      (_mshrCtl_io_msInfo_9_bits_way),
+    .io_msInfo_9_bits_reqTag                   (_mshrCtl_io_msInfo_9_bits_reqTag),
+    .io_msInfo_9_bits_reqSource                (_mshrCtl_io_msInfo_9_bits_reqSource),
+    .io_msInfo_9_bits_willFree                 (_mshrCtl_io_msInfo_9_bits_willFree),
+    .io_msInfo_9_bits_aliasTask                (_mshrCtl_io_msInfo_9_bits_aliasTask),
+    .io_msInfo_9_bits_needRelease              (_mshrCtl_io_msInfo_9_bits_needRelease),
+    .io_msInfo_9_bits_blockRefill              (_mshrCtl_io_msInfo_9_bits_blockRefill),
+    .io_msInfo_9_bits_meta_dirty               (_mshrCtl_io_msInfo_9_bits_meta_dirty),
+    .io_msInfo_9_bits_meta_state               (_mshrCtl_io_msInfo_9_bits_meta_state),
+    .io_msInfo_9_bits_meta_clients             (_mshrCtl_io_msInfo_9_bits_meta_clients),
+    .io_msInfo_9_bits_meta_alias               (_mshrCtl_io_msInfo_9_bits_meta_alias),
+    .io_msInfo_9_bits_meta_prefetch            (_mshrCtl_io_msInfo_9_bits_meta_prefetch),
+    .io_msInfo_9_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_9_bits_meta_prefetchSrc),
+    .io_msInfo_9_bits_meta_accessed            (_mshrCtl_io_msInfo_9_bits_meta_accessed),
+    .io_msInfo_9_bits_meta_tagErr              (_mshrCtl_io_msInfo_9_bits_meta_tagErr),
+    .io_msInfo_9_bits_meta_dataErr             (_mshrCtl_io_msInfo_9_bits_meta_dataErr),
+    .io_msInfo_9_bits_metaTag                  (_mshrCtl_io_msInfo_9_bits_metaTag),
+    .io_msInfo_9_bits_dirHit                   (_mshrCtl_io_msInfo_9_bits_dirHit),
+    .io_msInfo_9_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_9_bits_isAcqOrPrefetch),
+    .io_msInfo_9_bits_isPrefetch               (_mshrCtl_io_msInfo_9_bits_isPrefetch),
+    .io_msInfo_9_bits_param                    (_mshrCtl_io_msInfo_9_bits_param),
+    .io_msInfo_9_bits_mergeA                   (_mshrCtl_io_msInfo_9_bits_mergeA),
+    .io_msInfo_9_bits_w_grantfirst             (_mshrCtl_io_msInfo_9_bits_w_grantfirst),
+    .io_msInfo_9_bits_w_grantlast              (_mshrCtl_io_msInfo_9_bits_w_grantlast),
+    .io_msInfo_9_bits_w_grant                  (_mshrCtl_io_msInfo_9_bits_w_grant),
+    .io_msInfo_9_bits_s_release                (_mshrCtl_io_msInfo_9_bits_s_release),
+    .io_msInfo_9_bits_s_refill                 (_mshrCtl_io_msInfo_9_bits_s_refill),
+    .io_msInfo_9_bits_s_cmoresp                (_mshrCtl_io_msInfo_9_bits_s_cmoresp),
+    .io_msInfo_9_bits_s_cmometaw               (_mshrCtl_io_msInfo_9_bits_s_cmometaw),
+    .io_msInfo_9_bits_w_releaseack             (_mshrCtl_io_msInfo_9_bits_w_releaseack),
+    .io_msInfo_9_bits_w_replResp               (_mshrCtl_io_msInfo_9_bits_w_replResp),
+    .io_msInfo_9_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_9_bits_w_rprobeacklast),
+    .io_msInfo_9_bits_replaceData              (_mshrCtl_io_msInfo_9_bits_replaceData),
+    .io_msInfo_9_bits_releaseToClean           (_mshrCtl_io_msInfo_9_bits_releaseToClean),
+    .io_msInfo_10_valid                        (_mshrCtl_io_msInfo_10_valid),
+    .io_msInfo_10_bits_channel                 (_mshrCtl_io_msInfo_10_bits_channel),
+    .io_msInfo_10_bits_set                     (_mshrCtl_io_msInfo_10_bits_set),
+    .io_msInfo_10_bits_way                     (_mshrCtl_io_msInfo_10_bits_way),
+    .io_msInfo_10_bits_reqTag                  (_mshrCtl_io_msInfo_10_bits_reqTag),
+    .io_msInfo_10_bits_reqSource               (_mshrCtl_io_msInfo_10_bits_reqSource),
+    .io_msInfo_10_bits_willFree                (_mshrCtl_io_msInfo_10_bits_willFree),
+    .io_msInfo_10_bits_aliasTask               (_mshrCtl_io_msInfo_10_bits_aliasTask),
+    .io_msInfo_10_bits_needRelease             (_mshrCtl_io_msInfo_10_bits_needRelease),
+    .io_msInfo_10_bits_blockRefill             (_mshrCtl_io_msInfo_10_bits_blockRefill),
+    .io_msInfo_10_bits_meta_dirty              (_mshrCtl_io_msInfo_10_bits_meta_dirty),
+    .io_msInfo_10_bits_meta_state              (_mshrCtl_io_msInfo_10_bits_meta_state),
+    .io_msInfo_10_bits_meta_clients            (_mshrCtl_io_msInfo_10_bits_meta_clients),
+    .io_msInfo_10_bits_meta_alias              (_mshrCtl_io_msInfo_10_bits_meta_alias),
+    .io_msInfo_10_bits_meta_prefetch           (_mshrCtl_io_msInfo_10_bits_meta_prefetch),
+    .io_msInfo_10_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_10_bits_meta_prefetchSrc),
+    .io_msInfo_10_bits_meta_accessed           (_mshrCtl_io_msInfo_10_bits_meta_accessed),
+    .io_msInfo_10_bits_meta_tagErr             (_mshrCtl_io_msInfo_10_bits_meta_tagErr),
+    .io_msInfo_10_bits_meta_dataErr            (_mshrCtl_io_msInfo_10_bits_meta_dataErr),
+    .io_msInfo_10_bits_metaTag                 (_mshrCtl_io_msInfo_10_bits_metaTag),
+    .io_msInfo_10_bits_dirHit                  (_mshrCtl_io_msInfo_10_bits_dirHit),
+    .io_msInfo_10_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_10_bits_isAcqOrPrefetch),
+    .io_msInfo_10_bits_isPrefetch              (_mshrCtl_io_msInfo_10_bits_isPrefetch),
+    .io_msInfo_10_bits_param                   (_mshrCtl_io_msInfo_10_bits_param),
+    .io_msInfo_10_bits_mergeA                  (_mshrCtl_io_msInfo_10_bits_mergeA),
+    .io_msInfo_10_bits_w_grantfirst            (_mshrCtl_io_msInfo_10_bits_w_grantfirst),
+    .io_msInfo_10_bits_w_grantlast             (_mshrCtl_io_msInfo_10_bits_w_grantlast),
+    .io_msInfo_10_bits_w_grant                 (_mshrCtl_io_msInfo_10_bits_w_grant),
+    .io_msInfo_10_bits_s_release               (_mshrCtl_io_msInfo_10_bits_s_release),
+    .io_msInfo_10_bits_s_refill                (_mshrCtl_io_msInfo_10_bits_s_refill),
+    .io_msInfo_10_bits_s_cmoresp               (_mshrCtl_io_msInfo_10_bits_s_cmoresp),
+    .io_msInfo_10_bits_s_cmometaw              (_mshrCtl_io_msInfo_10_bits_s_cmometaw),
+    .io_msInfo_10_bits_w_releaseack            (_mshrCtl_io_msInfo_10_bits_w_releaseack),
+    .io_msInfo_10_bits_w_replResp              (_mshrCtl_io_msInfo_10_bits_w_replResp),
+    .io_msInfo_10_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_10_bits_w_rprobeacklast),
+    .io_msInfo_10_bits_replaceData             (_mshrCtl_io_msInfo_10_bits_replaceData),
+    .io_msInfo_10_bits_releaseToClean
+      (_mshrCtl_io_msInfo_10_bits_releaseToClean),
+    .io_msInfo_11_valid                        (_mshrCtl_io_msInfo_11_valid),
+    .io_msInfo_11_bits_channel                 (_mshrCtl_io_msInfo_11_bits_channel),
+    .io_msInfo_11_bits_set                     (_mshrCtl_io_msInfo_11_bits_set),
+    .io_msInfo_11_bits_way                     (_mshrCtl_io_msInfo_11_bits_way),
+    .io_msInfo_11_bits_reqTag                  (_mshrCtl_io_msInfo_11_bits_reqTag),
+    .io_msInfo_11_bits_reqSource               (_mshrCtl_io_msInfo_11_bits_reqSource),
+    .io_msInfo_11_bits_willFree                (_mshrCtl_io_msInfo_11_bits_willFree),
+    .io_msInfo_11_bits_aliasTask               (_mshrCtl_io_msInfo_11_bits_aliasTask),
+    .io_msInfo_11_bits_needRelease             (_mshrCtl_io_msInfo_11_bits_needRelease),
+    .io_msInfo_11_bits_blockRefill             (_mshrCtl_io_msInfo_11_bits_blockRefill),
+    .io_msInfo_11_bits_meta_dirty              (_mshrCtl_io_msInfo_11_bits_meta_dirty),
+    .io_msInfo_11_bits_meta_state              (_mshrCtl_io_msInfo_11_bits_meta_state),
+    .io_msInfo_11_bits_meta_clients            (_mshrCtl_io_msInfo_11_bits_meta_clients),
+    .io_msInfo_11_bits_meta_alias              (_mshrCtl_io_msInfo_11_bits_meta_alias),
+    .io_msInfo_11_bits_meta_prefetch           (_mshrCtl_io_msInfo_11_bits_meta_prefetch),
+    .io_msInfo_11_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_11_bits_meta_prefetchSrc),
+    .io_msInfo_11_bits_meta_accessed           (_mshrCtl_io_msInfo_11_bits_meta_accessed),
+    .io_msInfo_11_bits_meta_tagErr             (_mshrCtl_io_msInfo_11_bits_meta_tagErr),
+    .io_msInfo_11_bits_meta_dataErr            (_mshrCtl_io_msInfo_11_bits_meta_dataErr),
+    .io_msInfo_11_bits_metaTag                 (_mshrCtl_io_msInfo_11_bits_metaTag),
+    .io_msInfo_11_bits_dirHit                  (_mshrCtl_io_msInfo_11_bits_dirHit),
+    .io_msInfo_11_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_11_bits_isAcqOrPrefetch),
+    .io_msInfo_11_bits_isPrefetch              (_mshrCtl_io_msInfo_11_bits_isPrefetch),
+    .io_msInfo_11_bits_param                   (_mshrCtl_io_msInfo_11_bits_param),
+    .io_msInfo_11_bits_mergeA                  (_mshrCtl_io_msInfo_11_bits_mergeA),
+    .io_msInfo_11_bits_w_grantfirst            (_mshrCtl_io_msInfo_11_bits_w_grantfirst),
+    .io_msInfo_11_bits_w_grantlast             (_mshrCtl_io_msInfo_11_bits_w_grantlast),
+    .io_msInfo_11_bits_w_grant                 (_mshrCtl_io_msInfo_11_bits_w_grant),
+    .io_msInfo_11_bits_s_release               (_mshrCtl_io_msInfo_11_bits_s_release),
+    .io_msInfo_11_bits_s_refill                (_mshrCtl_io_msInfo_11_bits_s_refill),
+    .io_msInfo_11_bits_s_cmoresp               (_mshrCtl_io_msInfo_11_bits_s_cmoresp),
+    .io_msInfo_11_bits_s_cmometaw              (_mshrCtl_io_msInfo_11_bits_s_cmometaw),
+    .io_msInfo_11_bits_w_releaseack            (_mshrCtl_io_msInfo_11_bits_w_releaseack),
+    .io_msInfo_11_bits_w_replResp              (_mshrCtl_io_msInfo_11_bits_w_replResp),
+    .io_msInfo_11_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_11_bits_w_rprobeacklast),
+    .io_msInfo_11_bits_replaceData             (_mshrCtl_io_msInfo_11_bits_replaceData),
+    .io_msInfo_11_bits_releaseToClean
+      (_mshrCtl_io_msInfo_11_bits_releaseToClean),
+    .io_msInfo_12_valid                        (_mshrCtl_io_msInfo_12_valid),
+    .io_msInfo_12_bits_channel                 (_mshrCtl_io_msInfo_12_bits_channel),
+    .io_msInfo_12_bits_set                     (_mshrCtl_io_msInfo_12_bits_set),
+    .io_msInfo_12_bits_way                     (_mshrCtl_io_msInfo_12_bits_way),
+    .io_msInfo_12_bits_reqTag                  (_mshrCtl_io_msInfo_12_bits_reqTag),
+    .io_msInfo_12_bits_reqSource               (_mshrCtl_io_msInfo_12_bits_reqSource),
+    .io_msInfo_12_bits_willFree                (_mshrCtl_io_msInfo_12_bits_willFree),
+    .io_msInfo_12_bits_aliasTask               (_mshrCtl_io_msInfo_12_bits_aliasTask),
+    .io_msInfo_12_bits_needRelease             (_mshrCtl_io_msInfo_12_bits_needRelease),
+    .io_msInfo_12_bits_blockRefill             (_mshrCtl_io_msInfo_12_bits_blockRefill),
+    .io_msInfo_12_bits_meta_dirty              (_mshrCtl_io_msInfo_12_bits_meta_dirty),
+    .io_msInfo_12_bits_meta_state              (_mshrCtl_io_msInfo_12_bits_meta_state),
+    .io_msInfo_12_bits_meta_clients            (_mshrCtl_io_msInfo_12_bits_meta_clients),
+    .io_msInfo_12_bits_meta_alias              (_mshrCtl_io_msInfo_12_bits_meta_alias),
+    .io_msInfo_12_bits_meta_prefetch           (_mshrCtl_io_msInfo_12_bits_meta_prefetch),
+    .io_msInfo_12_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_12_bits_meta_prefetchSrc),
+    .io_msInfo_12_bits_meta_accessed           (_mshrCtl_io_msInfo_12_bits_meta_accessed),
+    .io_msInfo_12_bits_meta_tagErr             (_mshrCtl_io_msInfo_12_bits_meta_tagErr),
+    .io_msInfo_12_bits_meta_dataErr            (_mshrCtl_io_msInfo_12_bits_meta_dataErr),
+    .io_msInfo_12_bits_metaTag                 (_mshrCtl_io_msInfo_12_bits_metaTag),
+    .io_msInfo_12_bits_dirHit                  (_mshrCtl_io_msInfo_12_bits_dirHit),
+    .io_msInfo_12_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_12_bits_isAcqOrPrefetch),
+    .io_msInfo_12_bits_isPrefetch              (_mshrCtl_io_msInfo_12_bits_isPrefetch),
+    .io_msInfo_12_bits_param                   (_mshrCtl_io_msInfo_12_bits_param),
+    .io_msInfo_12_bits_mergeA                  (_mshrCtl_io_msInfo_12_bits_mergeA),
+    .io_msInfo_12_bits_w_grantfirst            (_mshrCtl_io_msInfo_12_bits_w_grantfirst),
+    .io_msInfo_12_bits_w_grantlast             (_mshrCtl_io_msInfo_12_bits_w_grantlast),
+    .io_msInfo_12_bits_w_grant                 (_mshrCtl_io_msInfo_12_bits_w_grant),
+    .io_msInfo_12_bits_s_release               (_mshrCtl_io_msInfo_12_bits_s_release),
+    .io_msInfo_12_bits_s_refill                (_mshrCtl_io_msInfo_12_bits_s_refill),
+    .io_msInfo_12_bits_s_cmoresp               (_mshrCtl_io_msInfo_12_bits_s_cmoresp),
+    .io_msInfo_12_bits_s_cmometaw              (_mshrCtl_io_msInfo_12_bits_s_cmometaw),
+    .io_msInfo_12_bits_w_releaseack            (_mshrCtl_io_msInfo_12_bits_w_releaseack),
+    .io_msInfo_12_bits_w_replResp              (_mshrCtl_io_msInfo_12_bits_w_replResp),
+    .io_msInfo_12_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_12_bits_w_rprobeacklast),
+    .io_msInfo_12_bits_replaceData             (_mshrCtl_io_msInfo_12_bits_replaceData),
+    .io_msInfo_12_bits_releaseToClean
+      (_mshrCtl_io_msInfo_12_bits_releaseToClean),
+    .io_msInfo_13_valid                        (_mshrCtl_io_msInfo_13_valid),
+    .io_msInfo_13_bits_channel                 (_mshrCtl_io_msInfo_13_bits_channel),
+    .io_msInfo_13_bits_set                     (_mshrCtl_io_msInfo_13_bits_set),
+    .io_msInfo_13_bits_way                     (_mshrCtl_io_msInfo_13_bits_way),
+    .io_msInfo_13_bits_reqTag                  (_mshrCtl_io_msInfo_13_bits_reqTag),
+    .io_msInfo_13_bits_reqSource               (_mshrCtl_io_msInfo_13_bits_reqSource),
+    .io_msInfo_13_bits_willFree                (_mshrCtl_io_msInfo_13_bits_willFree),
+    .io_msInfo_13_bits_aliasTask               (_mshrCtl_io_msInfo_13_bits_aliasTask),
+    .io_msInfo_13_bits_needRelease             (_mshrCtl_io_msInfo_13_bits_needRelease),
+    .io_msInfo_13_bits_blockRefill             (_mshrCtl_io_msInfo_13_bits_blockRefill),
+    .io_msInfo_13_bits_meta_dirty              (_mshrCtl_io_msInfo_13_bits_meta_dirty),
+    .io_msInfo_13_bits_meta_state              (_mshrCtl_io_msInfo_13_bits_meta_state),
+    .io_msInfo_13_bits_meta_clients            (_mshrCtl_io_msInfo_13_bits_meta_clients),
+    .io_msInfo_13_bits_meta_alias              (_mshrCtl_io_msInfo_13_bits_meta_alias),
+    .io_msInfo_13_bits_meta_prefetch           (_mshrCtl_io_msInfo_13_bits_meta_prefetch),
+    .io_msInfo_13_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_13_bits_meta_prefetchSrc),
+    .io_msInfo_13_bits_meta_accessed           (_mshrCtl_io_msInfo_13_bits_meta_accessed),
+    .io_msInfo_13_bits_meta_tagErr             (_mshrCtl_io_msInfo_13_bits_meta_tagErr),
+    .io_msInfo_13_bits_meta_dataErr            (_mshrCtl_io_msInfo_13_bits_meta_dataErr),
+    .io_msInfo_13_bits_metaTag                 (_mshrCtl_io_msInfo_13_bits_metaTag),
+    .io_msInfo_13_bits_dirHit                  (_mshrCtl_io_msInfo_13_bits_dirHit),
+    .io_msInfo_13_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_13_bits_isAcqOrPrefetch),
+    .io_msInfo_13_bits_isPrefetch              (_mshrCtl_io_msInfo_13_bits_isPrefetch),
+    .io_msInfo_13_bits_param                   (_mshrCtl_io_msInfo_13_bits_param),
+    .io_msInfo_13_bits_mergeA                  (_mshrCtl_io_msInfo_13_bits_mergeA),
+    .io_msInfo_13_bits_w_grantfirst            (_mshrCtl_io_msInfo_13_bits_w_grantfirst),
+    .io_msInfo_13_bits_w_grantlast             (_mshrCtl_io_msInfo_13_bits_w_grantlast),
+    .io_msInfo_13_bits_w_grant                 (_mshrCtl_io_msInfo_13_bits_w_grant),
+    .io_msInfo_13_bits_s_release               (_mshrCtl_io_msInfo_13_bits_s_release),
+    .io_msInfo_13_bits_s_refill                (_mshrCtl_io_msInfo_13_bits_s_refill),
+    .io_msInfo_13_bits_s_cmoresp               (_mshrCtl_io_msInfo_13_bits_s_cmoresp),
+    .io_msInfo_13_bits_s_cmometaw              (_mshrCtl_io_msInfo_13_bits_s_cmometaw),
+    .io_msInfo_13_bits_w_releaseack            (_mshrCtl_io_msInfo_13_bits_w_releaseack),
+    .io_msInfo_13_bits_w_replResp              (_mshrCtl_io_msInfo_13_bits_w_replResp),
+    .io_msInfo_13_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_13_bits_w_rprobeacklast),
+    .io_msInfo_13_bits_replaceData             (_mshrCtl_io_msInfo_13_bits_replaceData),
+    .io_msInfo_13_bits_releaseToClean
+      (_mshrCtl_io_msInfo_13_bits_releaseToClean),
+    .io_msInfo_14_valid                        (_mshrCtl_io_msInfo_14_valid),
+    .io_msInfo_14_bits_channel                 (_mshrCtl_io_msInfo_14_bits_channel),
+    .io_msInfo_14_bits_set                     (_mshrCtl_io_msInfo_14_bits_set),
+    .io_msInfo_14_bits_way                     (_mshrCtl_io_msInfo_14_bits_way),
+    .io_msInfo_14_bits_reqTag                  (_mshrCtl_io_msInfo_14_bits_reqTag),
+    .io_msInfo_14_bits_reqSource               (_mshrCtl_io_msInfo_14_bits_reqSource),
+    .io_msInfo_14_bits_willFree                (_mshrCtl_io_msInfo_14_bits_willFree),
+    .io_msInfo_14_bits_aliasTask               (_mshrCtl_io_msInfo_14_bits_aliasTask),
+    .io_msInfo_14_bits_needRelease             (_mshrCtl_io_msInfo_14_bits_needRelease),
+    .io_msInfo_14_bits_blockRefill             (_mshrCtl_io_msInfo_14_bits_blockRefill),
+    .io_msInfo_14_bits_meta_dirty              (_mshrCtl_io_msInfo_14_bits_meta_dirty),
+    .io_msInfo_14_bits_meta_state              (_mshrCtl_io_msInfo_14_bits_meta_state),
+    .io_msInfo_14_bits_meta_clients            (_mshrCtl_io_msInfo_14_bits_meta_clients),
+    .io_msInfo_14_bits_meta_alias              (_mshrCtl_io_msInfo_14_bits_meta_alias),
+    .io_msInfo_14_bits_meta_prefetch           (_mshrCtl_io_msInfo_14_bits_meta_prefetch),
+    .io_msInfo_14_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_14_bits_meta_prefetchSrc),
+    .io_msInfo_14_bits_meta_accessed           (_mshrCtl_io_msInfo_14_bits_meta_accessed),
+    .io_msInfo_14_bits_meta_tagErr             (_mshrCtl_io_msInfo_14_bits_meta_tagErr),
+    .io_msInfo_14_bits_meta_dataErr            (_mshrCtl_io_msInfo_14_bits_meta_dataErr),
+    .io_msInfo_14_bits_metaTag                 (_mshrCtl_io_msInfo_14_bits_metaTag),
+    .io_msInfo_14_bits_dirHit                  (_mshrCtl_io_msInfo_14_bits_dirHit),
+    .io_msInfo_14_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_14_bits_isAcqOrPrefetch),
+    .io_msInfo_14_bits_isPrefetch              (_mshrCtl_io_msInfo_14_bits_isPrefetch),
+    .io_msInfo_14_bits_param                   (_mshrCtl_io_msInfo_14_bits_param),
+    .io_msInfo_14_bits_mergeA                  (_mshrCtl_io_msInfo_14_bits_mergeA),
+    .io_msInfo_14_bits_w_grantfirst            (_mshrCtl_io_msInfo_14_bits_w_grantfirst),
+    .io_msInfo_14_bits_w_grantlast             (_mshrCtl_io_msInfo_14_bits_w_grantlast),
+    .io_msInfo_14_bits_w_grant                 (_mshrCtl_io_msInfo_14_bits_w_grant),
+    .io_msInfo_14_bits_s_release               (_mshrCtl_io_msInfo_14_bits_s_release),
+    .io_msInfo_14_bits_s_refill                (_mshrCtl_io_msInfo_14_bits_s_refill),
+    .io_msInfo_14_bits_s_cmoresp               (_mshrCtl_io_msInfo_14_bits_s_cmoresp),
+    .io_msInfo_14_bits_s_cmometaw              (_mshrCtl_io_msInfo_14_bits_s_cmometaw),
+    .io_msInfo_14_bits_w_releaseack            (_mshrCtl_io_msInfo_14_bits_w_releaseack),
+    .io_msInfo_14_bits_w_replResp              (_mshrCtl_io_msInfo_14_bits_w_replResp),
+    .io_msInfo_14_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_14_bits_w_rprobeacklast),
+    .io_msInfo_14_bits_replaceData             (_mshrCtl_io_msInfo_14_bits_replaceData),
+    .io_msInfo_14_bits_releaseToClean
+      (_mshrCtl_io_msInfo_14_bits_releaseToClean),
+    .io_msInfo_15_valid                        (_mshrCtl_io_msInfo_15_valid),
+    .io_msInfo_15_bits_channel                 (_mshrCtl_io_msInfo_15_bits_channel),
+    .io_msInfo_15_bits_set                     (_mshrCtl_io_msInfo_15_bits_set),
+    .io_msInfo_15_bits_way                     (_mshrCtl_io_msInfo_15_bits_way),
+    .io_msInfo_15_bits_reqTag                  (_mshrCtl_io_msInfo_15_bits_reqTag),
+    .io_msInfo_15_bits_reqSource               (_mshrCtl_io_msInfo_15_bits_reqSource),
+    .io_msInfo_15_bits_willFree                (_mshrCtl_io_msInfo_15_bits_willFree),
+    .io_msInfo_15_bits_aliasTask               (_mshrCtl_io_msInfo_15_bits_aliasTask),
+    .io_msInfo_15_bits_needRelease             (_mshrCtl_io_msInfo_15_bits_needRelease),
+    .io_msInfo_15_bits_blockRefill             (_mshrCtl_io_msInfo_15_bits_blockRefill),
+    .io_msInfo_15_bits_meta_dirty              (_mshrCtl_io_msInfo_15_bits_meta_dirty),
+    .io_msInfo_15_bits_meta_state              (_mshrCtl_io_msInfo_15_bits_meta_state),
+    .io_msInfo_15_bits_meta_clients            (_mshrCtl_io_msInfo_15_bits_meta_clients),
+    .io_msInfo_15_bits_meta_alias              (_mshrCtl_io_msInfo_15_bits_meta_alias),
+    .io_msInfo_15_bits_meta_prefetch           (_mshrCtl_io_msInfo_15_bits_meta_prefetch),
+    .io_msInfo_15_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_15_bits_meta_prefetchSrc),
+    .io_msInfo_15_bits_meta_accessed           (_mshrCtl_io_msInfo_15_bits_meta_accessed),
+    .io_msInfo_15_bits_meta_tagErr             (_mshrCtl_io_msInfo_15_bits_meta_tagErr),
+    .io_msInfo_15_bits_meta_dataErr            (_mshrCtl_io_msInfo_15_bits_meta_dataErr),
+    .io_msInfo_15_bits_metaTag                 (_mshrCtl_io_msInfo_15_bits_metaTag),
+    .io_msInfo_15_bits_dirHit                  (_mshrCtl_io_msInfo_15_bits_dirHit),
+    .io_msInfo_15_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_15_bits_isAcqOrPrefetch),
+    .io_msInfo_15_bits_isPrefetch              (_mshrCtl_io_msInfo_15_bits_isPrefetch),
+    .io_msInfo_15_bits_param                   (_mshrCtl_io_msInfo_15_bits_param),
+    .io_msInfo_15_bits_mergeA                  (_mshrCtl_io_msInfo_15_bits_mergeA),
+    .io_msInfo_15_bits_w_grantfirst            (_mshrCtl_io_msInfo_15_bits_w_grantfirst),
+    .io_msInfo_15_bits_w_grantlast             (_mshrCtl_io_msInfo_15_bits_w_grantlast),
+    .io_msInfo_15_bits_w_grant                 (_mshrCtl_io_msInfo_15_bits_w_grant),
+    .io_msInfo_15_bits_s_release               (_mshrCtl_io_msInfo_15_bits_s_release),
+    .io_msInfo_15_bits_s_refill                (_mshrCtl_io_msInfo_15_bits_s_refill),
+    .io_msInfo_15_bits_s_cmoresp               (_mshrCtl_io_msInfo_15_bits_s_cmoresp),
+    .io_msInfo_15_bits_s_cmometaw              (_mshrCtl_io_msInfo_15_bits_s_cmometaw),
+    .io_msInfo_15_bits_w_releaseack            (_mshrCtl_io_msInfo_15_bits_w_releaseack),
+    .io_msInfo_15_bits_w_replResp              (_mshrCtl_io_msInfo_15_bits_w_replResp),
+    .io_msInfo_15_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_15_bits_w_rprobeacklast),
+    .io_msInfo_15_bits_replaceData             (_mshrCtl_io_msInfo_15_bits_replaceData),
+    .io_msInfo_15_bits_releaseToClean
+      (_mshrCtl_io_msInfo_15_bits_releaseToClean),
+    .io_metaOnHit_dirty                        (_directory_io_metaOnHit_dirty),
+    .io_metaOnHit_state                        (_directory_io_metaOnHit_state),
+    .io_metaOnHit_clients                      (_directory_io_metaOnHit_clients),
+    .io_metaOnHit_alias                        (_directory_io_metaOnHit_alias),
+    .io_metaOnHit_prefetch                     (_directory_io_metaOnHit_prefetch),
+    .io_metaOnHit_prefetchSrc                  (_directory_io_metaOnHit_prefetchSrc),
+    .io_metaOnHit_accessed                     (_directory_io_metaOnHit_accessed),
+    .io_metaOnHit_tagErr                       (_directory_io_metaOnHit_tagErr),
+    .io_metaOnHit_dataErr                      (_directory_io_metaOnHit_dataErr),
+    .io_errOnSnp                               (_directory_io_errOnSnp),
+    .io_wayOH                                  (_directory_io_wayOH),
+    .io_replWayOH                              (_directory_io_replWayOH),
+    .io_cmoHitInvalid                          (/* unused */),
+    .io_retryFastFwd                           (_directory_io_retryFastFwd),
+    .boreChildrenBd_bore_array                 (childBd_array),
+    .boreChildrenBd_bore_all                   (childBd_all),
+    .boreChildrenBd_bore_req                   (childBd_req),
+    .boreChildrenBd_bore_ack                   (childBd_ack),
+    .boreChildrenBd_bore_writeen               (childBd_writeen),
+    .boreChildrenBd_bore_be                    (childBd_be),
+    .boreChildrenBd_bore_addr                  (childBd_addr),
+    .boreChildrenBd_bore_indata                (childBd_indata),
+    .boreChildrenBd_bore_readen                (childBd_readen),
+    .boreChildrenBd_bore_addr_rd               (childBd_addr_rd),
+    .boreChildrenBd_bore_outdata               (childBd_outdata),
+    .sigFromSrams_bore_ram_hold                (sigFromSrams_bore_ram_hold),
+    .sigFromSrams_bore_ram_bypass              (sigFromSrams_bore_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken            (sigFromSrams_bore_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk             (sigFromSrams_bore_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp            (sigFromSrams_bore_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold            (sigFromSrams_bore_ram_mcp_hold),
+    .sigFromSrams_bore_cgen                    (sigFromSrams_bore_cgen),
+    .sigFromSrams_bore_1_ram_hold              (sigFromSrams_bore_1_ram_hold),
+    .sigFromSrams_bore_1_ram_bypass            (sigFromSrams_bore_1_ram_bypass),
+    .sigFromSrams_bore_1_ram_bp_clken          (sigFromSrams_bore_1_ram_bp_clken),
+    .sigFromSrams_bore_1_ram_aux_clk           (sigFromSrams_bore_1_ram_aux_clk),
+    .sigFromSrams_bore_1_ram_aux_ckbp          (sigFromSrams_bore_1_ram_aux_ckbp),
+    .sigFromSrams_bore_1_ram_mcp_hold          (sigFromSrams_bore_1_ram_mcp_hold),
+    .sigFromSrams_bore_1_cgen                  (sigFromSrams_bore_1_cgen),
+    .sigFromSrams_bore_2_ram_hold              (sigFromSrams_bore_2_ram_hold),
+    .sigFromSrams_bore_2_ram_bypass            (sigFromSrams_bore_2_ram_bypass),
+    .sigFromSrams_bore_2_ram_bp_clken          (sigFromSrams_bore_2_ram_bp_clken),
+    .sigFromSrams_bore_2_ram_aux_clk           (sigFromSrams_bore_2_ram_aux_clk),
+    .sigFromSrams_bore_2_ram_aux_ckbp          (sigFromSrams_bore_2_ram_aux_ckbp),
+    .sigFromSrams_bore_2_ram_mcp_hold          (sigFromSrams_bore_2_ram_mcp_hold),
+    .sigFromSrams_bore_2_cgen                  (sigFromSrams_bore_2_cgen),
+    .sigFromSrams_bore_3_ram_hold              (sigFromSrams_bore_3_ram_hold),
+    .sigFromSrams_bore_3_ram_bypass            (sigFromSrams_bore_3_ram_bypass),
+    .sigFromSrams_bore_3_ram_bp_clken          (sigFromSrams_bore_3_ram_bp_clken),
+    .sigFromSrams_bore_3_ram_aux_clk           (sigFromSrams_bore_3_ram_aux_clk),
+    .sigFromSrams_bore_3_ram_aux_ckbp          (sigFromSrams_bore_3_ram_aux_ckbp),
+    .sigFromSrams_bore_3_ram_mcp_hold          (sigFromSrams_bore_3_ram_mcp_hold),
+    .sigFromSrams_bore_3_cgen                  (sigFromSrams_bore_3_cgen),
+    .sigFromSrams_bore_4_ram_hold              (sigFromSrams_bore_4_ram_hold),
+    .sigFromSrams_bore_4_ram_bypass            (sigFromSrams_bore_4_ram_bypass),
+    .sigFromSrams_bore_4_ram_bp_clken          (sigFromSrams_bore_4_ram_bp_clken),
+    .sigFromSrams_bore_4_ram_aux_clk           (sigFromSrams_bore_4_ram_aux_clk),
+    .sigFromSrams_bore_4_ram_aux_ckbp          (sigFromSrams_bore_4_ram_aux_ckbp),
+    .sigFromSrams_bore_4_ram_mcp_hold          (sigFromSrams_bore_4_ram_mcp_hold),
+    .sigFromSrams_bore_4_cgen                  (sigFromSrams_bore_4_cgen)
+  );
+  wire [3:0]   childBd_1_array;
+  wire         childBd_1_all;
+  wire         childBd_1_req;
+  wire         childBd_1_writeen;
+  wire         childBd_1_be;
+  wire [11:0]  childBd_1_addr;
+  wire [136:0] childBd_1_indata;
+  wire         childBd_1_readen;
+  wire [11:0]  childBd_1_addr_rd;
+  DataStorage dataStorage (
+    .clock                            (clock),
+    .reset                            (reset),
+    .io_en                            (_mainPipe_io_toDS_en_s3),
+    .io_error                         (_dataStorage_io_error),
+    .io_req_valid                     (_mainPipe_io_toDS_req_s3_valid),
+    .io_req_bits_way                  (_mainPipe_io_toDS_req_s3_bits_way),
+    .io_req_bits_set                  (_mainPipe_io_toDS_req_s3_bits_set),
+    .io_req_bits_wen                  (_mainPipe_io_toDS_req_s3_bits_wen),
+    .io_rdata_data                    (_dataStorage_io_rdata_data),
+    .io_wdata_data                    (_mainPipe_io_toDS_wdata_s3_data),
+    .boreChildrenBd_bore_array        (childBd_1_array),
+    .boreChildrenBd_bore_all          (childBd_1_all),
+    .boreChildrenBd_bore_req          (childBd_1_req),
+    .boreChildrenBd_bore_ack          (childBd_1_ack),
+    .boreChildrenBd_bore_writeen      (childBd_1_writeen),
+    .boreChildrenBd_bore_be           (childBd_1_be),
+    .boreChildrenBd_bore_addr         (childBd_1_addr),
+    .boreChildrenBd_bore_indata       (childBd_1_indata),
+    .boreChildrenBd_bore_readen       (childBd_1_readen),
+    .boreChildrenBd_bore_addr_rd      (childBd_1_addr_rd),
+    .boreChildrenBd_bore_outdata      (childBd_1_outdata),
+    .sigFromSrams_bore_ram_hold       (sigFromSrams_bore_5_ram_hold),
+    .sigFromSrams_bore_ram_bypass     (sigFromSrams_bore_5_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken   (sigFromSrams_bore_5_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk    (sigFromSrams_bore_5_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp   (sigFromSrams_bore_5_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold   (sigFromSrams_bore_5_ram_mcp_hold),
+    .sigFromSrams_bore_cgen           (sigFromSrams_bore_5_cgen),
+    .sigFromSrams_bore_1_ram_hold     (sigFromSrams_bore_6_ram_hold),
+    .sigFromSrams_bore_1_ram_bypass   (sigFromSrams_bore_6_ram_bypass),
+    .sigFromSrams_bore_1_ram_bp_clken (sigFromSrams_bore_6_ram_bp_clken),
+    .sigFromSrams_bore_1_ram_aux_clk  (sigFromSrams_bore_6_ram_aux_clk),
+    .sigFromSrams_bore_1_ram_aux_ckbp (sigFromSrams_bore_6_ram_aux_ckbp),
+    .sigFromSrams_bore_1_ram_mcp_hold (sigFromSrams_bore_6_ram_mcp_hold),
+    .sigFromSrams_bore_1_cgen         (sigFromSrams_bore_6_cgen),
+    .sigFromSrams_bore_2_ram_hold     (sigFromSrams_bore_7_ram_hold),
+    .sigFromSrams_bore_2_ram_bypass   (sigFromSrams_bore_7_ram_bypass),
+    .sigFromSrams_bore_2_ram_bp_clken (sigFromSrams_bore_7_ram_bp_clken),
+    .sigFromSrams_bore_2_ram_aux_clk  (sigFromSrams_bore_7_ram_aux_clk),
+    .sigFromSrams_bore_2_ram_aux_ckbp (sigFromSrams_bore_7_ram_aux_ckbp),
+    .sigFromSrams_bore_2_ram_mcp_hold (sigFromSrams_bore_7_ram_mcp_hold),
+    .sigFromSrams_bore_2_cgen         (sigFromSrams_bore_7_cgen),
+    .sigFromSrams_bore_3_ram_hold     (sigFromSrams_bore_8_ram_hold),
+    .sigFromSrams_bore_3_ram_bypass   (sigFromSrams_bore_8_ram_bypass),
+    .sigFromSrams_bore_3_ram_bp_clken (sigFromSrams_bore_8_ram_bp_clken),
+    .sigFromSrams_bore_3_ram_aux_clk  (sigFromSrams_bore_8_ram_aux_clk),
+    .sigFromSrams_bore_3_ram_aux_ckbp (sigFromSrams_bore_8_ram_aux_ckbp),
+    .sigFromSrams_bore_3_ram_mcp_hold (sigFromSrams_bore_8_ram_mcp_hold),
+    .sigFromSrams_bore_3_cgen         (sigFromSrams_bore_8_cgen)
+  );
+  MSHRBuffer refillBuf (
+    .clock                 (clock),
+    .reset                 (reset),
+    .io_r_valid            (_reqArb_io_refillBufRead_s2_valid),
+    .io_r_bits_id          (_reqArb_io_refillBufRead_s2_bits_id),
+    .io_resp_data_data     (_refillBuf_io_resp_data_data),
+    .io_w_0_valid          (_rxdat_io_refillBufWrite_valid),
+    .io_w_0_bits_id        (_rxdat_io_refillBufWrite_bits_id),
+    .io_w_0_bits_data_data (_rxdat_io_refillBufWrite_bits_data_data),
+    .io_w_0_bits_beatMask  (_rxdat_io_refillBufWrite_bits_beatMask),
+    .io_w_1_valid          (_sinkC_io_refillBufWrite_valid),
+    .io_w_1_bits_id        (_sinkC_io_refillBufWrite_bits_id),
+    .io_w_1_bits_data_data (_sinkC_io_refillBufWrite_bits_data_data)
+  );
+  MSHRBuffer_1 releaseBuf (
+    .clock                 (clock),
+    .reset                 (reset),
+    .io_r_valid            (_reqArb_io_releaseBufRead_s2_valid),
+    .io_r_bits_id          (_reqArb_io_releaseBufRead_s2_bits_id),
+    .io_resp_data_data     (_releaseBuf_io_resp_data_data),
+    .io_w_0_valid          (_mshrCtl_io_nestedwbDataId_valid),
+    .io_w_0_bits_id        (_mshrCtl_io_nestedwbDataId_bits),
+    .io_w_0_bits_data_data (_mainPipe_io_nestedwbData_data),
+    .io_w_1_valid          (_sinkC_io_releaseBufWrite_valid),
+    .io_w_1_bits_id        (_mshrCtl_io_releaseBufWriteId),
+    .io_w_1_bits_data_data (_sinkC_io_releaseBufWrite_bits_data_data),
+    .io_w_2_valid          (_mainPipe_io_releaseBufWrite_valid),
+    .io_w_2_bits_id        (_mainPipe_io_releaseBufWrite_bits_id),
+    .io_w_2_bits_data_data (_mainPipe_io_releaseBufWrite_bits_data_data)
+  );
+  RequestArb reqArb (
+    .clock                                                (clock),
+    .reset                                                (reset),
+    .io_sinkA_ready                                       (_reqArb_io_sinkA_ready),
+    .io_sinkA_valid                                       (_reqBuf_io_out_valid),
+    .io_sinkA_bits_channel                                (_reqBuf_io_out_bits_channel),
+    .io_sinkA_bits_txChannel                              (_reqBuf_io_out_bits_txChannel),
+    .io_sinkA_bits_set                                    (_reqBuf_io_out_bits_set),
+    .io_sinkA_bits_tag                                    (_reqBuf_io_out_bits_tag),
+    .io_sinkA_bits_off                                    (_reqBuf_io_out_bits_off),
+    .io_sinkA_bits_alias                                  (_reqBuf_io_out_bits_alias),
+    .io_sinkA_bits_vaddr                                  (_reqBuf_io_out_bits_vaddr),
+    .io_sinkA_bits_isKeyword                              (_reqBuf_io_out_bits_isKeyword),
+    .io_sinkA_bits_opcode                                 (_reqBuf_io_out_bits_opcode),
+    .io_sinkA_bits_param                                  (_reqBuf_io_out_bits_param),
+    .io_sinkA_bits_size                                   (_reqBuf_io_out_bits_size),
+    .io_sinkA_bits_sourceId                               (_reqBuf_io_out_bits_sourceId),
+    .io_sinkA_bits_bufIdx                                 (_reqBuf_io_out_bits_bufIdx),
+    .io_sinkA_bits_needProbeAckData
+      (_reqBuf_io_out_bits_needProbeAckData),
+    .io_sinkA_bits_denied                                 (_reqBuf_io_out_bits_denied),
+    .io_sinkA_bits_corrupt                                (_reqBuf_io_out_bits_corrupt),
+    .io_sinkA_bits_mshrTask                               (_reqBuf_io_out_bits_mshrTask),
+    .io_sinkA_bits_mshrId                                 (_reqBuf_io_out_bits_mshrId),
+    .io_sinkA_bits_aliasTask                              (_reqBuf_io_out_bits_aliasTask),
+    .io_sinkA_bits_useProbeData
+      (_reqBuf_io_out_bits_useProbeData),
+    .io_sinkA_bits_mshrRetry                              (_reqBuf_io_out_bits_mshrRetry),
+    .io_sinkA_bits_readProbeDataDown
+      (_reqBuf_io_out_bits_readProbeDataDown),
+    .io_sinkA_bits_fromL2pft                              (_reqBuf_io_out_bits_fromL2pft),
+    .io_sinkA_bits_needHint                               (_reqBuf_io_out_bits_needHint),
+    .io_sinkA_bits_dirty                                  (_reqBuf_io_out_bits_dirty),
+    .io_sinkA_bits_way                                    (_reqBuf_io_out_bits_way),
+    .io_sinkA_bits_meta_dirty
+      (_reqBuf_io_out_bits_meta_dirty),
+    .io_sinkA_bits_meta_state
+      (_reqBuf_io_out_bits_meta_state),
+    .io_sinkA_bits_meta_clients
+      (_reqBuf_io_out_bits_meta_clients),
+    .io_sinkA_bits_meta_alias
+      (_reqBuf_io_out_bits_meta_alias),
+    .io_sinkA_bits_meta_prefetch
+      (_reqBuf_io_out_bits_meta_prefetch),
+    .io_sinkA_bits_meta_prefetchSrc
+      (_reqBuf_io_out_bits_meta_prefetchSrc),
+    .io_sinkA_bits_meta_accessed
+      (_reqBuf_io_out_bits_meta_accessed),
+    .io_sinkA_bits_meta_tagErr
+      (_reqBuf_io_out_bits_meta_tagErr),
+    .io_sinkA_bits_meta_dataErr
+      (_reqBuf_io_out_bits_meta_dataErr),
+    .io_sinkA_bits_metaWen                                (_reqBuf_io_out_bits_metaWen),
+    .io_sinkA_bits_tagWen                                 (_reqBuf_io_out_bits_tagWen),
+    .io_sinkA_bits_dsWen                                  (_reqBuf_io_out_bits_dsWen),
+    .io_sinkA_bits_wayMask                                (8'hFF),
+    .io_sinkA_bits_replTask                               (_reqBuf_io_out_bits_replTask),
+    .io_sinkA_bits_cmoTask                                (_reqBuf_io_out_bits_cmoTask),
+    .io_sinkA_bits_cmoAll                                 (_reqBuf_io_out_bits_cmoAll),
+    .io_sinkA_bits_reqSource                              (_reqBuf_io_out_bits_reqSource),
+    .io_sinkA_bits_mergeA                                 (_reqBuf_io_out_bits_mergeA),
+    .io_sinkA_bits_aMergeTask_off
+      (_reqBuf_io_out_bits_aMergeTask_off),
+    .io_sinkA_bits_aMergeTask_alias
+      (_reqBuf_io_out_bits_aMergeTask_alias),
+    .io_sinkA_bits_aMergeTask_vaddr
+      (_reqBuf_io_out_bits_aMergeTask_vaddr),
+    .io_sinkA_bits_aMergeTask_isKeyword
+      (_reqBuf_io_out_bits_aMergeTask_isKeyword),
+    .io_sinkA_bits_aMergeTask_opcode
+      (_reqBuf_io_out_bits_aMergeTask_opcode),
+    .io_sinkA_bits_aMergeTask_param
+      (_reqBuf_io_out_bits_aMergeTask_param),
+    .io_sinkA_bits_aMergeTask_sourceId
+      (_reqBuf_io_out_bits_aMergeTask_sourceId),
+    .io_sinkA_bits_aMergeTask_meta_dirty
+      (_reqBuf_io_out_bits_aMergeTask_meta_dirty),
+    .io_sinkA_bits_aMergeTask_meta_state
+      (_reqBuf_io_out_bits_aMergeTask_meta_state),
+    .io_sinkA_bits_aMergeTask_meta_clients
+      (_reqBuf_io_out_bits_aMergeTask_meta_clients),
+    .io_sinkA_bits_aMergeTask_meta_alias
+      (_reqBuf_io_out_bits_aMergeTask_meta_alias),
+    .io_sinkA_bits_aMergeTask_meta_prefetch
+      (_reqBuf_io_out_bits_aMergeTask_meta_prefetch),
+    .io_sinkA_bits_aMergeTask_meta_prefetchSrc
+      (_reqBuf_io_out_bits_aMergeTask_meta_prefetchSrc),
+    .io_sinkA_bits_aMergeTask_meta_accessed
+      (_reqBuf_io_out_bits_aMergeTask_meta_accessed),
+    .io_sinkA_bits_aMergeTask_meta_tagErr
+      (_reqBuf_io_out_bits_aMergeTask_meta_tagErr),
+    .io_sinkA_bits_aMergeTask_meta_dataErr
+      (_reqBuf_io_out_bits_aMergeTask_meta_dataErr),
+    .io_sinkA_bits_snpHitRelease
+      (_reqBuf_io_out_bits_snpHitRelease),
+    .io_sinkA_bits_snpHitReleaseToInval
+      (_reqBuf_io_out_bits_snpHitReleaseToInval),
+    .io_sinkA_bits_snpHitReleaseToClean
+      (_reqBuf_io_out_bits_snpHitReleaseToClean),
+    .io_sinkA_bits_snpHitReleaseWithData
+      (_reqBuf_io_out_bits_snpHitReleaseWithData),
+    .io_sinkA_bits_snpHitReleaseIdx
+      (_reqBuf_io_out_bits_snpHitReleaseIdx),
+    .io_sinkA_bits_snpHitReleaseMeta_dirty
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_dirty),
+    .io_sinkA_bits_snpHitReleaseMeta_state
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_state),
+    .io_sinkA_bits_snpHitReleaseMeta_clients
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_clients),
+    .io_sinkA_bits_snpHitReleaseMeta_alias
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_alias),
+    .io_sinkA_bits_snpHitReleaseMeta_prefetch
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_prefetch),
+    .io_sinkA_bits_snpHitReleaseMeta_prefetchSrc
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_sinkA_bits_snpHitReleaseMeta_accessed
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_accessed),
+    .io_sinkA_bits_snpHitReleaseMeta_tagErr
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_tagErr),
+    .io_sinkA_bits_snpHitReleaseMeta_dataErr
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_dataErr),
+    .io_sinkA_bits_tgtID                                  (_reqBuf_io_out_bits_tgtID),
+    .io_sinkA_bits_srcID                                  (_reqBuf_io_out_bits_srcID),
+    .io_sinkA_bits_txnID                                  (_reqBuf_io_out_bits_txnID),
+    .io_sinkA_bits_homeNID                                (_reqBuf_io_out_bits_homeNID),
+    .io_sinkA_bits_dbID                                   (_reqBuf_io_out_bits_dbID),
+    .io_sinkA_bits_fwdNID                                 (_reqBuf_io_out_bits_fwdNID),
+    .io_sinkA_bits_fwdTxnID                               (_reqBuf_io_out_bits_fwdTxnID),
+    .io_sinkA_bits_chiOpcode                              (_reqBuf_io_out_bits_chiOpcode),
+    .io_sinkA_bits_resp                                   (_reqBuf_io_out_bits_resp),
+    .io_sinkA_bits_fwdState                               (_reqBuf_io_out_bits_fwdState),
+    .io_sinkA_bits_pCrdType                               (_reqBuf_io_out_bits_pCrdType),
+    .io_sinkA_bits_retToSrc                               (_reqBuf_io_out_bits_retToSrc),
+    .io_sinkA_bits_likelyshared
+      (_reqBuf_io_out_bits_likelyshared),
+    .io_sinkA_bits_expCompAck
+      (_reqBuf_io_out_bits_expCompAck),
+    .io_sinkA_bits_allowRetry
+      (_reqBuf_io_out_bits_allowRetry),
+    .io_sinkA_bits_memAttr_allocate
+      (_reqBuf_io_out_bits_memAttr_allocate),
+    .io_sinkA_bits_memAttr_cacheable
+      (_reqBuf_io_out_bits_memAttr_cacheable),
+    .io_sinkA_bits_memAttr_device
+      (_reqBuf_io_out_bits_memAttr_device),
+    .io_sinkA_bits_memAttr_ewa
+      (_reqBuf_io_out_bits_memAttr_ewa),
+    .io_sinkA_bits_traceTag                               (_reqBuf_io_out_bits_traceTag),
+    .io_ATag                                              (_reqBuf_io_ATag),
+    .io_ASet                                              (_reqBuf_io_ASet),
+    .io_s1Entrance_valid                                  (_reqArb_io_s1Entrance_valid),
+    .io_s1Entrance_bits_set
+      (_reqArb_io_s1Entrance_bits_set),
+    .io_sinkB_ready                                       (_reqArb_io_sinkB_ready),
+    .io_sinkB_valid                                       (_rxsnp_io_task_valid),
+    .io_sinkB_bits_channel                                (3'h2),
+    .io_sinkB_bits_txChannel                              (3'h0),
+    .io_sinkB_bits_set                                    (_rxsnp_io_task_bits_set),
+    .io_sinkB_bits_tag                                    (_rxsnp_io_task_bits_tag),
+    .io_sinkB_bits_off                                    (_rxsnp_io_task_bits_off),
+    .io_sinkB_bits_alias                                  (1'h0),
+    .io_sinkB_bits_vaddr                                  (44'h0),
+    .io_sinkB_bits_isKeyword                              (1'h0),
+    .io_sinkB_bits_opcode                                 (4'h0),
+    .io_sinkB_bits_param                                  (3'h0),
+    .io_sinkB_bits_size                                   (3'h6),
+    .io_sinkB_bits_sourceId                               (7'h0),
+    .io_sinkB_bits_bufIdx                                 (2'h0),
+    .io_sinkB_bits_needProbeAckData                       (1'h0),
+    .io_sinkB_bits_denied                                 (1'h0),
+    .io_sinkB_bits_corrupt                                (1'h0),
+    .io_sinkB_bits_mshrTask                               (1'h0),
+    .io_sinkB_bits_mshrId                                 (8'h0),
+    .io_sinkB_bits_aliasTask                              (1'h0),
+    .io_sinkB_bits_useProbeData                           (1'h0),
+    .io_sinkB_bits_mshrRetry                              (1'h0),
+    .io_sinkB_bits_readProbeDataDown                      (1'h0),
+    .io_sinkB_bits_fromL2pft                              (1'h0),
+    .io_sinkB_bits_needHint                               (1'h0),
+    .io_sinkB_bits_dirty                                  (1'h0),
+    .io_sinkB_bits_way                                    (3'h0),
+    .io_sinkB_bits_meta_dirty                             (1'h0),
+    .io_sinkB_bits_meta_state                             (2'h0),
+    .io_sinkB_bits_meta_clients                           (1'h0),
+    .io_sinkB_bits_meta_alias                             (1'h0),
+    .io_sinkB_bits_meta_prefetch                          (1'h0),
+    .io_sinkB_bits_meta_prefetchSrc                       (4'h0),
+    .io_sinkB_bits_meta_accessed                          (1'h0),
+    .io_sinkB_bits_meta_tagErr                            (1'h0),
+    .io_sinkB_bits_meta_dataErr                           (1'h0),
+    .io_sinkB_bits_metaWen                                (1'h0),
+    .io_sinkB_bits_tagWen                                 (1'h0),
+    .io_sinkB_bits_dsWen                                  (1'h0),
+    .io_sinkB_bits_wayMask                                (8'hFF),
+    .io_sinkB_bits_replTask                               (1'h0),
+    .io_sinkB_bits_cmoTask                                (1'h0),
+    .io_sinkB_bits_cmoAll                                 (1'h0),
+    .io_sinkB_bits_reqSource                              (5'h0),
+    .io_sinkB_bits_mergeA                                 (1'h0),
+    .io_sinkB_bits_aMergeTask_off                         (6'h0),
+    .io_sinkB_bits_aMergeTask_alias                       (1'h0),
+    .io_sinkB_bits_aMergeTask_vaddr                       (44'h0),
+    .io_sinkB_bits_aMergeTask_isKeyword                   (1'h0),
+    .io_sinkB_bits_aMergeTask_opcode                      (3'h0),
+    .io_sinkB_bits_aMergeTask_param                       (3'h0),
+    .io_sinkB_bits_aMergeTask_sourceId                    (7'h0),
+    .io_sinkB_bits_aMergeTask_meta_dirty                  (1'h0),
+    .io_sinkB_bits_aMergeTask_meta_state                  (2'h0),
+    .io_sinkB_bits_aMergeTask_meta_clients                (1'h0),
+    .io_sinkB_bits_aMergeTask_meta_alias                  (1'h0),
+    .io_sinkB_bits_aMergeTask_meta_prefetch               (1'h0),
+    .io_sinkB_bits_aMergeTask_meta_prefetchSrc            (4'h0),
+    .io_sinkB_bits_aMergeTask_meta_accessed               (1'h0),
+    .io_sinkB_bits_aMergeTask_meta_tagErr                 (1'h0),
+    .io_sinkB_bits_aMergeTask_meta_dataErr                (1'h0),
+    .io_sinkB_bits_snpHitRelease
+      (_rxsnp_io_task_bits_snpHitRelease),
+    .io_sinkB_bits_snpHitReleaseToInval
+      (_rxsnp_io_task_bits_snpHitReleaseToInval),
+    .io_sinkB_bits_snpHitReleaseToClean
+      (_rxsnp_io_task_bits_snpHitReleaseToClean),
+    .io_sinkB_bits_snpHitReleaseWithData
+      (_rxsnp_io_task_bits_snpHitReleaseWithData),
+    .io_sinkB_bits_snpHitReleaseIdx
+      (_rxsnp_io_task_bits_snpHitReleaseIdx),
+    .io_sinkB_bits_snpHitReleaseMeta_dirty
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_dirty),
+    .io_sinkB_bits_snpHitReleaseMeta_state
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_state),
+    .io_sinkB_bits_snpHitReleaseMeta_clients
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_clients),
+    .io_sinkB_bits_snpHitReleaseMeta_alias
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_alias),
+    .io_sinkB_bits_snpHitReleaseMeta_prefetch
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_prefetch),
+    .io_sinkB_bits_snpHitReleaseMeta_prefetchSrc
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_sinkB_bits_snpHitReleaseMeta_accessed
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_accessed),
+    .io_sinkB_bits_snpHitReleaseMeta_tagErr
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_tagErr),
+    .io_sinkB_bits_snpHitReleaseMeta_dataErr
+      (_rxsnp_io_task_bits_snpHitReleaseMeta_dataErr),
+    .io_sinkB_bits_tgtID                                  (11'h0),
+    .io_sinkB_bits_srcID                                  (_rxsnp_io_task_bits_srcID),
+    .io_sinkB_bits_txnID                                  (_rxsnp_io_task_bits_txnID),
+    .io_sinkB_bits_homeNID                                (11'h0),
+    .io_sinkB_bits_dbID                                   (12'h0),
+    .io_sinkB_bits_fwdNID                                 (_rxsnp_io_task_bits_fwdNID),
+    .io_sinkB_bits_fwdTxnID                               (_rxsnp_io_task_bits_fwdTxnID),
+    .io_sinkB_bits_chiOpcode                              (_rxsnp_io_task_bits_chiOpcode),
+    .io_sinkB_bits_resp                                   (3'h0),
+    .io_sinkB_bits_fwdState                               (3'h0),
+    .io_sinkB_bits_pCrdType                               (4'h0),
+    .io_sinkB_bits_retToSrc                               (_rxsnp_io_task_bits_retToSrc),
+    .io_sinkB_bits_likelyshared                           (1'h0),
+    .io_sinkB_bits_expCompAck                             (1'h0),
+    .io_sinkB_bits_allowRetry                             (1'h0),
+    .io_sinkB_bits_memAttr_allocate                       (1'h0),
+    .io_sinkB_bits_memAttr_cacheable                      (1'h0),
+    .io_sinkB_bits_memAttr_device                         (1'h0),
+    .io_sinkB_bits_memAttr_ewa                            (1'h0),
+    .io_sinkB_bits_traceTag                               (_rxsnp_io_task_bits_traceTag),
+    .io_sinkC_ready                                       (_reqArb_io_sinkC_ready),
+    .io_sinkC_valid                                       (_sinkC_io_task_valid),
+    .io_sinkC_bits_channel                                (_sinkC_io_task_bits_channel),
+    .io_sinkC_bits_txChannel                              (_sinkC_io_task_bits_txChannel),
+    .io_sinkC_bits_set                                    (_sinkC_io_task_bits_set),
+    .io_sinkC_bits_tag                                    (_sinkC_io_task_bits_tag),
+    .io_sinkC_bits_off                                    (_sinkC_io_task_bits_off),
+    .io_sinkC_bits_alias                                  (_sinkC_io_task_bits_alias),
+    .io_sinkC_bits_vaddr                                  (_sinkC_io_task_bits_vaddr),
+    .io_sinkC_bits_isKeyword                              (_sinkC_io_task_bits_isKeyword),
+    .io_sinkC_bits_opcode                                 (_sinkC_io_task_bits_opcode),
+    .io_sinkC_bits_param                                  (_sinkC_io_task_bits_param),
+    .io_sinkC_bits_size                                   (_sinkC_io_task_bits_size),
+    .io_sinkC_bits_sourceId                               (_sinkC_io_task_bits_sourceId),
+    .io_sinkC_bits_bufIdx                                 (_sinkC_io_task_bits_bufIdx),
+    .io_sinkC_bits_needProbeAckData
+      (_sinkC_io_task_bits_needProbeAckData),
+    .io_sinkC_bits_denied                                 (_sinkC_io_task_bits_denied),
+    .io_sinkC_bits_corrupt                                (_sinkC_io_task_bits_corrupt),
+    .io_sinkC_bits_mshrTask                               (_sinkC_io_task_bits_mshrTask),
+    .io_sinkC_bits_mshrId                                 (_sinkC_io_task_bits_mshrId),
+    .io_sinkC_bits_aliasTask                              (_sinkC_io_task_bits_aliasTask),
+    .io_sinkC_bits_useProbeData
+      (_sinkC_io_task_bits_useProbeData),
+    .io_sinkC_bits_mshrRetry                              (_sinkC_io_task_bits_mshrRetry),
+    .io_sinkC_bits_readProbeDataDown
+      (_sinkC_io_task_bits_readProbeDataDown),
+    .io_sinkC_bits_fromL2pft                              (_sinkC_io_task_bits_fromL2pft),
+    .io_sinkC_bits_needHint                               (_sinkC_io_task_bits_needHint),
+    .io_sinkC_bits_dirty                                  (_sinkC_io_task_bits_dirty),
+    .io_sinkC_bits_way                                    (_sinkC_io_task_bits_way),
+    .io_sinkC_bits_meta_dirty
+      (_sinkC_io_task_bits_meta_dirty),
+    .io_sinkC_bits_meta_state
+      (_sinkC_io_task_bits_meta_state),
+    .io_sinkC_bits_meta_clients
+      (_sinkC_io_task_bits_meta_clients),
+    .io_sinkC_bits_meta_alias
+      (_sinkC_io_task_bits_meta_alias),
+    .io_sinkC_bits_meta_prefetch
+      (_sinkC_io_task_bits_meta_prefetch),
+    .io_sinkC_bits_meta_prefetchSrc
+      (_sinkC_io_task_bits_meta_prefetchSrc),
+    .io_sinkC_bits_meta_accessed
+      (_sinkC_io_task_bits_meta_accessed),
+    .io_sinkC_bits_meta_tagErr
+      (_sinkC_io_task_bits_meta_tagErr),
+    .io_sinkC_bits_meta_dataErr
+      (_sinkC_io_task_bits_meta_dataErr),
+    .io_sinkC_bits_metaWen                                (_sinkC_io_task_bits_metaWen),
+    .io_sinkC_bits_tagWen                                 (_sinkC_io_task_bits_tagWen),
+    .io_sinkC_bits_dsWen                                  (_sinkC_io_task_bits_dsWen),
+    .io_sinkC_bits_wayMask                                (_sinkC_io_task_bits_wayMask),
+    .io_sinkC_bits_replTask                               (_sinkC_io_task_bits_replTask),
+    .io_sinkC_bits_cmoTask                                (_sinkC_io_task_bits_cmoTask),
+    .io_sinkC_bits_cmoAll                                 (_sinkC_io_task_bits_cmoAll),
+    .io_sinkC_bits_reqSource                              (_sinkC_io_task_bits_reqSource),
+    .io_sinkC_bits_mergeA                                 (_sinkC_io_task_bits_mergeA),
+    .io_sinkC_bits_aMergeTask_off
+      (_sinkC_io_task_bits_aMergeTask_off),
+    .io_sinkC_bits_aMergeTask_alias
+      (_sinkC_io_task_bits_aMergeTask_alias),
+    .io_sinkC_bits_aMergeTask_vaddr
+      (_sinkC_io_task_bits_aMergeTask_vaddr),
+    .io_sinkC_bits_aMergeTask_isKeyword
+      (_sinkC_io_task_bits_aMergeTask_isKeyword),
+    .io_sinkC_bits_aMergeTask_opcode
+      (_sinkC_io_task_bits_aMergeTask_opcode),
+    .io_sinkC_bits_aMergeTask_param
+      (_sinkC_io_task_bits_aMergeTask_param),
+    .io_sinkC_bits_aMergeTask_sourceId
+      (_sinkC_io_task_bits_aMergeTask_sourceId),
+    .io_sinkC_bits_aMergeTask_meta_dirty
+      (_sinkC_io_task_bits_aMergeTask_meta_dirty),
+    .io_sinkC_bits_aMergeTask_meta_state
+      (_sinkC_io_task_bits_aMergeTask_meta_state),
+    .io_sinkC_bits_aMergeTask_meta_clients
+      (_sinkC_io_task_bits_aMergeTask_meta_clients),
+    .io_sinkC_bits_aMergeTask_meta_alias
+      (_sinkC_io_task_bits_aMergeTask_meta_alias),
+    .io_sinkC_bits_aMergeTask_meta_prefetch
+      (_sinkC_io_task_bits_aMergeTask_meta_prefetch),
+    .io_sinkC_bits_aMergeTask_meta_prefetchSrc
+      (_sinkC_io_task_bits_aMergeTask_meta_prefetchSrc),
+    .io_sinkC_bits_aMergeTask_meta_accessed
+      (_sinkC_io_task_bits_aMergeTask_meta_accessed),
+    .io_sinkC_bits_aMergeTask_meta_tagErr
+      (_sinkC_io_task_bits_aMergeTask_meta_tagErr),
+    .io_sinkC_bits_aMergeTask_meta_dataErr
+      (_sinkC_io_task_bits_aMergeTask_meta_dataErr),
+    .io_sinkC_bits_snpHitRelease
+      (_sinkC_io_task_bits_snpHitRelease),
+    .io_sinkC_bits_snpHitReleaseToInval
+      (_sinkC_io_task_bits_snpHitReleaseToInval),
+    .io_sinkC_bits_snpHitReleaseToClean
+      (_sinkC_io_task_bits_snpHitReleaseToClean),
+    .io_sinkC_bits_snpHitReleaseWithData
+      (_sinkC_io_task_bits_snpHitReleaseWithData),
+    .io_sinkC_bits_snpHitReleaseIdx
+      (_sinkC_io_task_bits_snpHitReleaseIdx),
+    .io_sinkC_bits_snpHitReleaseMeta_dirty
+      (_sinkC_io_task_bits_snpHitReleaseMeta_dirty),
+    .io_sinkC_bits_snpHitReleaseMeta_state
+      (_sinkC_io_task_bits_snpHitReleaseMeta_state),
+    .io_sinkC_bits_snpHitReleaseMeta_clients
+      (_sinkC_io_task_bits_snpHitReleaseMeta_clients),
+    .io_sinkC_bits_snpHitReleaseMeta_alias
+      (_sinkC_io_task_bits_snpHitReleaseMeta_alias),
+    .io_sinkC_bits_snpHitReleaseMeta_prefetch
+      (_sinkC_io_task_bits_snpHitReleaseMeta_prefetch),
+    .io_sinkC_bits_snpHitReleaseMeta_prefetchSrc
+      (_sinkC_io_task_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_sinkC_bits_snpHitReleaseMeta_accessed
+      (_sinkC_io_task_bits_snpHitReleaseMeta_accessed),
+    .io_sinkC_bits_snpHitReleaseMeta_tagErr
+      (_sinkC_io_task_bits_snpHitReleaseMeta_tagErr),
+    .io_sinkC_bits_snpHitReleaseMeta_dataErr
+      (_sinkC_io_task_bits_snpHitReleaseMeta_dataErr),
+    .io_sinkC_bits_tgtID                                  (_sinkC_io_task_bits_tgtID),
+    .io_sinkC_bits_srcID                                  (_sinkC_io_task_bits_srcID),
+    .io_sinkC_bits_txnID                                  (_sinkC_io_task_bits_txnID),
+    .io_sinkC_bits_homeNID                                (_sinkC_io_task_bits_homeNID),
+    .io_sinkC_bits_dbID                                   (_sinkC_io_task_bits_dbID),
+    .io_sinkC_bits_fwdNID                                 (_sinkC_io_task_bits_fwdNID),
+    .io_sinkC_bits_fwdTxnID                               (_sinkC_io_task_bits_fwdTxnID),
+    .io_sinkC_bits_chiOpcode                              (_sinkC_io_task_bits_chiOpcode),
+    .io_sinkC_bits_resp                                   (_sinkC_io_task_bits_resp),
+    .io_sinkC_bits_fwdState                               (_sinkC_io_task_bits_fwdState),
+    .io_sinkC_bits_pCrdType                               (_sinkC_io_task_bits_pCrdType),
+    .io_sinkC_bits_retToSrc                               (_sinkC_io_task_bits_retToSrc),
+    .io_sinkC_bits_likelyshared
+      (_sinkC_io_task_bits_likelyshared),
+    .io_sinkC_bits_expCompAck
+      (_sinkC_io_task_bits_expCompAck),
+    .io_sinkC_bits_allowRetry
+      (_sinkC_io_task_bits_allowRetry),
+    .io_sinkC_bits_memAttr_allocate
+      (_sinkC_io_task_bits_memAttr_allocate),
+    .io_sinkC_bits_memAttr_cacheable
+      (_sinkC_io_task_bits_memAttr_cacheable),
+    .io_sinkC_bits_memAttr_device
+      (_sinkC_io_task_bits_memAttr_device),
+    .io_sinkC_bits_memAttr_ewa
+      (_sinkC_io_task_bits_memAttr_ewa),
+    .io_sinkC_bits_traceTag                               (_sinkC_io_task_bits_traceTag),
+    .io_mshrTask_ready                                    (_reqArb_io_mshrTask_ready),
+    .io_mshrTask_valid                                    (_mshrCtl_io_mshrTask_valid),
+    .io_mshrTask_bits_channel
+      (_mshrCtl_io_mshrTask_bits_channel),
+    .io_mshrTask_bits_txChannel
+      (_mshrCtl_io_mshrTask_bits_txChannel),
+    .io_mshrTask_bits_set                                 (_mshrCtl_io_mshrTask_bits_set),
+    .io_mshrTask_bits_tag                                 (_mshrCtl_io_mshrTask_bits_tag),
+    .io_mshrTask_bits_off                                 (_mshrCtl_io_mshrTask_bits_off),
+    .io_mshrTask_bits_alias
+      (_mshrCtl_io_mshrTask_bits_alias),
+    .io_mshrTask_bits_vaddr                               (44'h0),
+    .io_mshrTask_bits_isKeyword
+      (_mshrCtl_io_mshrTask_bits_isKeyword),
+    .io_mshrTask_bits_opcode
+      (_mshrCtl_io_mshrTask_bits_opcode),
+    .io_mshrTask_bits_param
+      (_mshrCtl_io_mshrTask_bits_param),
+    .io_mshrTask_bits_size
+      (_mshrCtl_io_mshrTask_bits_size),
+    .io_mshrTask_bits_sourceId
+      (_mshrCtl_io_mshrTask_bits_sourceId),
+    .io_mshrTask_bits_bufIdx                              (2'h0),
+    .io_mshrTask_bits_needProbeAckData                    (1'h0),
+    .io_mshrTask_bits_denied
+      (_mshrCtl_io_mshrTask_bits_denied),
+    .io_mshrTask_bits_corrupt
+      (_mshrCtl_io_mshrTask_bits_corrupt),
+    .io_mshrTask_bits_mshrTask
+      (_mshrCtl_io_mshrTask_bits_mshrTask),
+    .io_mshrTask_bits_mshrId
+      (_mshrCtl_io_mshrTask_bits_mshrId),
+    .io_mshrTask_bits_aliasTask
+      (_mshrCtl_io_mshrTask_bits_aliasTask),
+    .io_mshrTask_bits_useProbeData
+      (_mshrCtl_io_mshrTask_bits_useProbeData),
+    .io_mshrTask_bits_mshrRetry
+      (_mshrCtl_io_mshrTask_bits_mshrRetry),
+    .io_mshrTask_bits_readProbeDataDown
+      (_mshrCtl_io_mshrTask_bits_readProbeDataDown),
+    .io_mshrTask_bits_fromL2pft
+      (_mshrCtl_io_mshrTask_bits_fromL2pft),
+    .io_mshrTask_bits_needHint                            (1'h0),
+    .io_mshrTask_bits_dirty
+      (_mshrCtl_io_mshrTask_bits_dirty),
+    .io_mshrTask_bits_way                                 (_mshrCtl_io_mshrTask_bits_way),
+    .io_mshrTask_bits_meta_dirty
+      (_mshrCtl_io_mshrTask_bits_meta_dirty),
+    .io_mshrTask_bits_meta_state
+      (_mshrCtl_io_mshrTask_bits_meta_state),
+    .io_mshrTask_bits_meta_clients
+      (_mshrCtl_io_mshrTask_bits_meta_clients),
+    .io_mshrTask_bits_meta_alias
+      (_mshrCtl_io_mshrTask_bits_meta_alias),
+    .io_mshrTask_bits_meta_prefetch
+      (_mshrCtl_io_mshrTask_bits_meta_prefetch),
+    .io_mshrTask_bits_meta_prefetchSrc
+      (_mshrCtl_io_mshrTask_bits_meta_prefetchSrc),
+    .io_mshrTask_bits_meta_accessed
+      (_mshrCtl_io_mshrTask_bits_meta_accessed),
+    .io_mshrTask_bits_meta_tagErr
+      (_mshrCtl_io_mshrTask_bits_meta_tagErr),
+    .io_mshrTask_bits_meta_dataErr
+      (_mshrCtl_io_mshrTask_bits_meta_dataErr),
+    .io_mshrTask_bits_metaWen
+      (_mshrCtl_io_mshrTask_bits_metaWen),
+    .io_mshrTask_bits_tagWen
+      (_mshrCtl_io_mshrTask_bits_tagWen),
+    .io_mshrTask_bits_dsWen
+      (_mshrCtl_io_mshrTask_bits_dsWen),
+    .io_mshrTask_bits_wayMask                             (8'h0),
+    .io_mshrTask_bits_replTask
+      (_mshrCtl_io_mshrTask_bits_replTask),
+    .io_mshrTask_bits_cmoTask
+      (_mshrCtl_io_mshrTask_bits_cmoTask),
+    .io_mshrTask_bits_cmoAll                              (1'h0),
+    .io_mshrTask_bits_reqSource
+      (_mshrCtl_io_mshrTask_bits_reqSource),
+    .io_mshrTask_bits_mergeA
+      (_mshrCtl_io_mshrTask_bits_mergeA),
+    .io_mshrTask_bits_aMergeTask_off
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_off),
+    .io_mshrTask_bits_aMergeTask_alias
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_alias),
+    .io_mshrTask_bits_aMergeTask_vaddr
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_vaddr),
+    .io_mshrTask_bits_aMergeTask_isKeyword
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_isKeyword),
+    .io_mshrTask_bits_aMergeTask_opcode
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_opcode),
+    .io_mshrTask_bits_aMergeTask_param
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_param),
+    .io_mshrTask_bits_aMergeTask_sourceId
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_sourceId),
+    .io_mshrTask_bits_aMergeTask_meta_dirty
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_dirty),
+    .io_mshrTask_bits_aMergeTask_meta_state
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_state),
+    .io_mshrTask_bits_aMergeTask_meta_clients
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_clients),
+    .io_mshrTask_bits_aMergeTask_meta_alias
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_alias),
+    .io_mshrTask_bits_aMergeTask_meta_prefetch            (1'h0),
+    .io_mshrTask_bits_aMergeTask_meta_prefetchSrc         (4'h0),
+    .io_mshrTask_bits_aMergeTask_meta_accessed
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_accessed),
+    .io_mshrTask_bits_aMergeTask_meta_tagErr              (1'h0),
+    .io_mshrTask_bits_aMergeTask_meta_dataErr             (1'h0),
+    .io_mshrTask_bits_snpHitRelease
+      (_mshrCtl_io_mshrTask_bits_snpHitRelease),
+    .io_mshrTask_bits_snpHitReleaseToInval
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseToInval),
+    .io_mshrTask_bits_snpHitReleaseToClean
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseToClean),
+    .io_mshrTask_bits_snpHitReleaseWithData
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseWithData),
+    .io_mshrTask_bits_snpHitReleaseIdx
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseIdx),
+    .io_mshrTask_bits_snpHitReleaseMeta_dirty
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_dirty),
+    .io_mshrTask_bits_snpHitReleaseMeta_state
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_state),
+    .io_mshrTask_bits_snpHitReleaseMeta_clients
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_clients),
+    .io_mshrTask_bits_snpHitReleaseMeta_alias
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_alias),
+    .io_mshrTask_bits_snpHitReleaseMeta_prefetch
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_prefetch),
+    .io_mshrTask_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_mshrTask_bits_snpHitReleaseMeta_accessed
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_accessed),
+    .io_mshrTask_bits_snpHitReleaseMeta_tagErr
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_tagErr),
+    .io_mshrTask_bits_snpHitReleaseMeta_dataErr
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_dataErr),
+    .io_mshrTask_bits_tgtID
+      (_mshrCtl_io_mshrTask_bits_tgtID),
+    .io_mshrTask_bits_srcID                               (11'h0),
+    .io_mshrTask_bits_txnID
+      (_mshrCtl_io_mshrTask_bits_txnID),
+    .io_mshrTask_bits_homeNID
+      (_mshrCtl_io_mshrTask_bits_homeNID),
+    .io_mshrTask_bits_dbID
+      (_mshrCtl_io_mshrTask_bits_dbID),
+    .io_mshrTask_bits_fwdNID                              (11'h0),
+    .io_mshrTask_bits_fwdTxnID                            (12'h0),
+    .io_mshrTask_bits_chiOpcode
+      (_mshrCtl_io_mshrTask_bits_chiOpcode),
+    .io_mshrTask_bits_resp
+      (_mshrCtl_io_mshrTask_bits_resp),
+    .io_mshrTask_bits_fwdState
+      (_mshrCtl_io_mshrTask_bits_fwdState),
+    .io_mshrTask_bits_pCrdType                            (4'h0),
+    .io_mshrTask_bits_retToSrc
+      (_mshrCtl_io_mshrTask_bits_retToSrc),
+    .io_mshrTask_bits_likelyshared
+      (_mshrCtl_io_mshrTask_bits_likelyshared),
+    .io_mshrTask_bits_expCompAck
+      (_mshrCtl_io_mshrTask_bits_expCompAck),
+    .io_mshrTask_bits_allowRetry
+      (_mshrCtl_io_mshrTask_bits_allowRetry),
+    .io_mshrTask_bits_memAttr_allocate
+      (_mshrCtl_io_mshrTask_bits_memAttr_allocate),
+    .io_mshrTask_bits_memAttr_cacheable
+      (_mshrCtl_io_mshrTask_bits_memAttr_cacheable),
+    .io_mshrTask_bits_memAttr_device                      (1'h0),
+    .io_mshrTask_bits_memAttr_ewa
+      (_mshrCtl_io_mshrTask_bits_memAttr_ewa),
+    .io_mshrTask_bits_traceTag
+      (_mshrCtl_io_mshrTask_bits_traceTag),
+    .io_dirRead_s1_ready                                  (_directory_io_read_ready),
+    .io_dirRead_s1_valid                                  (_reqArb_io_dirRead_s1_valid),
+    .io_dirRead_s1_bits_tag
+      (_reqArb_io_dirRead_s1_bits_tag),
+    .io_dirRead_s1_bits_set
+      (_reqArb_io_dirRead_s1_bits_set),
+    .io_dirRead_s1_bits_wayMask
+      (_reqArb_io_dirRead_s1_bits_wayMask),
+    .io_dirRead_s1_bits_replacerInfo_channel
+      (_reqArb_io_dirRead_s1_bits_replacerInfo_channel),
+    .io_dirRead_s1_bits_replacerInfo_opcode
+      (_reqArb_io_dirRead_s1_bits_replacerInfo_opcode),
+    .io_dirRead_s1_bits_replacerInfo_reqSource
+      (_reqArb_io_dirRead_s1_bits_replacerInfo_reqSource),
+    .io_dirRead_s1_bits_replacerInfo_refill_prefetch
+      (_reqArb_io_dirRead_s1_bits_replacerInfo_refill_prefetch),
+    .io_dirRead_s1_bits_refill
+      (_reqArb_io_dirRead_s1_bits_refill),
+    .io_dirRead_s1_bits_mshrId
+      (_reqArb_io_dirRead_s1_bits_mshrId),
+    .io_dirRead_s1_bits_cmoAll
+      (_reqArb_io_dirRead_s1_bits_cmoAll),
+    .io_dirRead_s1_bits_cmoWay
+      (_reqArb_io_dirRead_s1_bits_cmoWay),
+    .io_taskToPipe_s2_valid
+      (_reqArb_io_taskToPipe_s2_valid),
+    .io_taskToPipe_s2_bits_channel
+      (_reqArb_io_taskToPipe_s2_bits_channel),
+    .io_taskToPipe_s2_bits_txChannel
+      (_reqArb_io_taskToPipe_s2_bits_txChannel),
+    .io_taskToPipe_s2_bits_set
+      (_reqArb_io_taskToPipe_s2_bits_set),
+    .io_taskToPipe_s2_bits_tag
+      (_reqArb_io_taskToPipe_s2_bits_tag),
+    .io_taskToPipe_s2_bits_off
+      (_reqArb_io_taskToPipe_s2_bits_off),
+    .io_taskToPipe_s2_bits_alias
+      (_reqArb_io_taskToPipe_s2_bits_alias),
+    .io_taskToPipe_s2_bits_vaddr
+      (_reqArb_io_taskToPipe_s2_bits_vaddr),
+    .io_taskToPipe_s2_bits_isKeyword
+      (_reqArb_io_taskToPipe_s2_bits_isKeyword),
+    .io_taskToPipe_s2_bits_opcode
+      (_reqArb_io_taskToPipe_s2_bits_opcode),
+    .io_taskToPipe_s2_bits_param
+      (_reqArb_io_taskToPipe_s2_bits_param),
+    .io_taskToPipe_s2_bits_size
+      (_reqArb_io_taskToPipe_s2_bits_size),
+    .io_taskToPipe_s2_bits_sourceId
+      (_reqArb_io_taskToPipe_s2_bits_sourceId),
+    .io_taskToPipe_s2_bits_bufIdx
+      (_reqArb_io_taskToPipe_s2_bits_bufIdx),
+    .io_taskToPipe_s2_bits_needProbeAckData
+      (_reqArb_io_taskToPipe_s2_bits_needProbeAckData),
+    .io_taskToPipe_s2_bits_denied
+      (_reqArb_io_taskToPipe_s2_bits_denied),
+    .io_taskToPipe_s2_bits_corrupt
+      (_reqArb_io_taskToPipe_s2_bits_corrupt),
+    .io_taskToPipe_s2_bits_mshrTask
+      (_reqArb_io_taskToPipe_s2_bits_mshrTask),
+    .io_taskToPipe_s2_bits_mshrId
+      (_reqArb_io_taskToPipe_s2_bits_mshrId),
+    .io_taskToPipe_s2_bits_aliasTask
+      (_reqArb_io_taskToPipe_s2_bits_aliasTask),
+    .io_taskToPipe_s2_bits_useProbeData
+      (_reqArb_io_taskToPipe_s2_bits_useProbeData),
+    .io_taskToPipe_s2_bits_mshrRetry
+      (_reqArb_io_taskToPipe_s2_bits_mshrRetry),
+    .io_taskToPipe_s2_bits_readProbeDataDown
+      (_reqArb_io_taskToPipe_s2_bits_readProbeDataDown),
+    .io_taskToPipe_s2_bits_fromL2pft
+      (_reqArb_io_taskToPipe_s2_bits_fromL2pft),
+    .io_taskToPipe_s2_bits_needHint
+      (_reqArb_io_taskToPipe_s2_bits_needHint),
+    .io_taskToPipe_s2_bits_dirty
+      (_reqArb_io_taskToPipe_s2_bits_dirty),
+    .io_taskToPipe_s2_bits_way
+      (_reqArb_io_taskToPipe_s2_bits_way),
+    .io_taskToPipe_s2_bits_meta_dirty
+      (_reqArb_io_taskToPipe_s2_bits_meta_dirty),
+    .io_taskToPipe_s2_bits_meta_state
+      (_reqArb_io_taskToPipe_s2_bits_meta_state),
+    .io_taskToPipe_s2_bits_meta_clients
+      (_reqArb_io_taskToPipe_s2_bits_meta_clients),
+    .io_taskToPipe_s2_bits_meta_alias
+      (_reqArb_io_taskToPipe_s2_bits_meta_alias),
+    .io_taskToPipe_s2_bits_meta_prefetch
+      (_reqArb_io_taskToPipe_s2_bits_meta_prefetch),
+    .io_taskToPipe_s2_bits_meta_prefetchSrc
+      (_reqArb_io_taskToPipe_s2_bits_meta_prefetchSrc),
+    .io_taskToPipe_s2_bits_meta_accessed
+      (_reqArb_io_taskToPipe_s2_bits_meta_accessed),
+    .io_taskToPipe_s2_bits_meta_tagErr
+      (_reqArb_io_taskToPipe_s2_bits_meta_tagErr),
+    .io_taskToPipe_s2_bits_meta_dataErr
+      (_reqArb_io_taskToPipe_s2_bits_meta_dataErr),
+    .io_taskToPipe_s2_bits_metaWen
+      (_reqArb_io_taskToPipe_s2_bits_metaWen),
+    .io_taskToPipe_s2_bits_tagWen
+      (_reqArb_io_taskToPipe_s2_bits_tagWen),
+    .io_taskToPipe_s2_bits_dsWen
+      (_reqArb_io_taskToPipe_s2_bits_dsWen),
+    .io_taskToPipe_s2_bits_wayMask
+      (_reqArb_io_taskToPipe_s2_bits_wayMask),
+    .io_taskToPipe_s2_bits_replTask
+      (_reqArb_io_taskToPipe_s2_bits_replTask),
+    .io_taskToPipe_s2_bits_cmoTask
+      (_reqArb_io_taskToPipe_s2_bits_cmoTask),
+    .io_taskToPipe_s2_bits_cmoAll
+      (_reqArb_io_taskToPipe_s2_bits_cmoAll),
+    .io_taskToPipe_s2_bits_reqSource
+      (_reqArb_io_taskToPipe_s2_bits_reqSource),
+    .io_taskToPipe_s2_bits_mergeA
+      (_reqArb_io_taskToPipe_s2_bits_mergeA),
+    .io_taskToPipe_s2_bits_aMergeTask_off
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_off),
+    .io_taskToPipe_s2_bits_aMergeTask_alias
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_alias),
+    .io_taskToPipe_s2_bits_aMergeTask_vaddr
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_vaddr),
+    .io_taskToPipe_s2_bits_aMergeTask_isKeyword
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_isKeyword),
+    .io_taskToPipe_s2_bits_aMergeTask_opcode
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_opcode),
+    .io_taskToPipe_s2_bits_aMergeTask_param
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_param),
+    .io_taskToPipe_s2_bits_aMergeTask_sourceId
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_sourceId),
+    .io_taskToPipe_s2_bits_aMergeTask_meta_dirty
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_dirty),
+    .io_taskToPipe_s2_bits_aMergeTask_meta_state
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_state),
+    .io_taskToPipe_s2_bits_aMergeTask_meta_clients
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_clients),
+    .io_taskToPipe_s2_bits_aMergeTask_meta_alias
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_alias),
+    .io_taskToPipe_s2_bits_aMergeTask_meta_prefetch
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_prefetch),
+    .io_taskToPipe_s2_bits_aMergeTask_meta_prefetchSrc
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_prefetchSrc),
+    .io_taskToPipe_s2_bits_aMergeTask_meta_accessed
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_accessed),
+    .io_taskToPipe_s2_bits_aMergeTask_meta_tagErr
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_tagErr),
+    .io_taskToPipe_s2_bits_aMergeTask_meta_dataErr
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_dataErr),
+    .io_taskToPipe_s2_bits_snpHitRelease
+      (_reqArb_io_taskToPipe_s2_bits_snpHitRelease),
+    .io_taskToPipe_s2_bits_snpHitReleaseToInval
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseToInval),
+    .io_taskToPipe_s2_bits_snpHitReleaseToClean
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseToClean),
+    .io_taskToPipe_s2_bits_snpHitReleaseWithData
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseWithData),
+    .io_taskToPipe_s2_bits_snpHitReleaseIdx
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseIdx),
+    .io_taskToPipe_s2_bits_snpHitReleaseMeta_dirty
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_dirty),
+    .io_taskToPipe_s2_bits_snpHitReleaseMeta_state
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_state),
+    .io_taskToPipe_s2_bits_snpHitReleaseMeta_clients
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_clients),
+    .io_taskToPipe_s2_bits_snpHitReleaseMeta_alias
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_alias),
+    .io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetch
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetch),
+    .io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetchSrc
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_taskToPipe_s2_bits_snpHitReleaseMeta_accessed
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_accessed),
+    .io_taskToPipe_s2_bits_snpHitReleaseMeta_tagErr
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_tagErr),
+    .io_taskToPipe_s2_bits_snpHitReleaseMeta_dataErr
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_dataErr),
+    .io_taskToPipe_s2_bits_tgtID
+      (_reqArb_io_taskToPipe_s2_bits_tgtID),
+    .io_taskToPipe_s2_bits_srcID
+      (_reqArb_io_taskToPipe_s2_bits_srcID),
+    .io_taskToPipe_s2_bits_txnID
+      (_reqArb_io_taskToPipe_s2_bits_txnID),
+    .io_taskToPipe_s2_bits_homeNID
+      (_reqArb_io_taskToPipe_s2_bits_homeNID),
+    .io_taskToPipe_s2_bits_dbID
+      (_reqArb_io_taskToPipe_s2_bits_dbID),
+    .io_taskToPipe_s2_bits_fwdNID
+      (_reqArb_io_taskToPipe_s2_bits_fwdNID),
+    .io_taskToPipe_s2_bits_fwdTxnID
+      (_reqArb_io_taskToPipe_s2_bits_fwdTxnID),
+    .io_taskToPipe_s2_bits_chiOpcode
+      (_reqArb_io_taskToPipe_s2_bits_chiOpcode),
+    .io_taskToPipe_s2_bits_resp
+      (_reqArb_io_taskToPipe_s2_bits_resp),
+    .io_taskToPipe_s2_bits_fwdState
+      (_reqArb_io_taskToPipe_s2_bits_fwdState),
+    .io_taskToPipe_s2_bits_pCrdType
+      (_reqArb_io_taskToPipe_s2_bits_pCrdType),
+    .io_taskToPipe_s2_bits_retToSrc
+      (_reqArb_io_taskToPipe_s2_bits_retToSrc),
+    .io_taskToPipe_s2_bits_likelyshared
+      (_reqArb_io_taskToPipe_s2_bits_likelyshared),
+    .io_taskToPipe_s2_bits_expCompAck
+      (_reqArb_io_taskToPipe_s2_bits_expCompAck),
+    .io_taskToPipe_s2_bits_allowRetry
+      (_reqArb_io_taskToPipe_s2_bits_allowRetry),
+    .io_taskToPipe_s2_bits_memAttr_allocate
+      (_reqArb_io_taskToPipe_s2_bits_memAttr_allocate),
+    .io_taskToPipe_s2_bits_memAttr_cacheable
+      (_reqArb_io_taskToPipe_s2_bits_memAttr_cacheable),
+    .io_taskToPipe_s2_bits_memAttr_device
+      (_reqArb_io_taskToPipe_s2_bits_memAttr_device),
+    .io_taskToPipe_s2_bits_memAttr_ewa
+      (_reqArb_io_taskToPipe_s2_bits_memAttr_ewa),
+    .io_taskToPipe_s2_bits_traceTag
+      (_reqArb_io_taskToPipe_s2_bits_traceTag),
+    .io_mshrHintQInfo_valid
+      (_reqArb_io_mshrHintQInfo_valid),
+    .io_mshrHintQInfo_bits_channel
+      (_reqArb_io_mshrHintQInfo_bits_channel),
+    .io_mshrHintQInfo_bits_txChannel                      (/* unused */),
+    .io_mshrHintQInfo_bits_set                            (/* unused */),
+    .io_mshrHintQInfo_bits_tag                            (/* unused */),
+    .io_mshrHintQInfo_bits_off                            (/* unused */),
+    .io_mshrHintQInfo_bits_alias                          (/* unused */),
+    .io_mshrHintQInfo_bits_vaddr                          (/* unused */),
+    .io_mshrHintQInfo_bits_isKeyword
+      (_reqArb_io_mshrHintQInfo_bits_isKeyword),
+    .io_mshrHintQInfo_bits_opcode
+      (_reqArb_io_mshrHintQInfo_bits_opcode),
+    .io_mshrHintQInfo_bits_param                          (/* unused */),
+    .io_mshrHintQInfo_bits_size                           (/* unused */),
+    .io_mshrHintQInfo_bits_sourceId
+      (_reqArb_io_mshrHintQInfo_bits_sourceId),
+    .io_mshrHintQInfo_bits_bufIdx                         (/* unused */),
+    .io_mshrHintQInfo_bits_needProbeAckData               (/* unused */),
+    .io_mshrHintQInfo_bits_denied                         (/* unused */),
+    .io_mshrHintQInfo_bits_corrupt                        (/* unused */),
+    .io_mshrHintQInfo_bits_mshrTask                       (/* unused */),
+    .io_mshrHintQInfo_bits_mshrId                         (/* unused */),
+    .io_mshrHintQInfo_bits_aliasTask                      (/* unused */),
+    .io_mshrHintQInfo_bits_useProbeData                   (/* unused */),
+    .io_mshrHintQInfo_bits_mshrRetry                      (/* unused */),
+    .io_mshrHintQInfo_bits_readProbeDataDown              (/* unused */),
+    .io_mshrHintQInfo_bits_fromL2pft                      (/* unused */),
+    .io_mshrHintQInfo_bits_needHint                       (/* unused */),
+    .io_mshrHintQInfo_bits_dirty                          (/* unused */),
+    .io_mshrHintQInfo_bits_way                            (/* unused */),
+    .io_mshrHintQInfo_bits_meta_dirty                     (/* unused */),
+    .io_mshrHintQInfo_bits_meta_state                     (/* unused */),
+    .io_mshrHintQInfo_bits_meta_clients                   (/* unused */),
+    .io_mshrHintQInfo_bits_meta_alias                     (/* unused */),
+    .io_mshrHintQInfo_bits_meta_prefetch                  (/* unused */),
+    .io_mshrHintQInfo_bits_meta_prefetchSrc               (/* unused */),
+    .io_mshrHintQInfo_bits_meta_accessed                  (/* unused */),
+    .io_mshrHintQInfo_bits_meta_tagErr                    (/* unused */),
+    .io_mshrHintQInfo_bits_meta_dataErr                   (/* unused */),
+    .io_mshrHintQInfo_bits_metaWen                        (/* unused */),
+    .io_mshrHintQInfo_bits_tagWen                         (/* unused */),
+    .io_mshrHintQInfo_bits_dsWen                          (/* unused */),
+    .io_mshrHintQInfo_bits_wayMask                        (/* unused */),
+    .io_mshrHintQInfo_bits_replTask                       (/* unused */),
+    .io_mshrHintQInfo_bits_cmoTask                        (/* unused */),
+    .io_mshrHintQInfo_bits_cmoAll                         (/* unused */),
+    .io_mshrHintQInfo_bits_reqSource                      (/* unused */),
+    .io_mshrHintQInfo_bits_mergeA
+      (_reqArb_io_mshrHintQInfo_bits_mergeA),
+    .io_mshrHintQInfo_bits_aMergeTask_off                 (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_alias               (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_vaddr               (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_isKeyword
+      (_reqArb_io_mshrHintQInfo_bits_aMergeTask_isKeyword),
+    .io_mshrHintQInfo_bits_aMergeTask_opcode
+      (_reqArb_io_mshrHintQInfo_bits_aMergeTask_opcode),
+    .io_mshrHintQInfo_bits_aMergeTask_param               (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_sourceId
+      (_reqArb_io_mshrHintQInfo_bits_aMergeTask_sourceId),
+    .io_mshrHintQInfo_bits_aMergeTask_meta_dirty          (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_meta_state          (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_meta_clients        (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_meta_alias          (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_meta_prefetch       (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_meta_prefetchSrc    (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_meta_accessed       (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_meta_tagErr         (/* unused */),
+    .io_mshrHintQInfo_bits_aMergeTask_meta_dataErr        (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitRelease                  (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseToInval           (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseToClean           (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseWithData          (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseIdx               (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseMeta_dirty        (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseMeta_state        (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseMeta_clients      (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseMeta_alias        (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseMeta_prefetch     (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseMeta_prefetchSrc  (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseMeta_accessed     (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseMeta_tagErr       (/* unused */),
+    .io_mshrHintQInfo_bits_snpHitReleaseMeta_dataErr      (/* unused */),
+    .io_mshrHintQInfo_bits_tgtID                          (/* unused */),
+    .io_mshrHintQInfo_bits_srcID                          (/* unused */),
+    .io_mshrHintQInfo_bits_txnID                          (/* unused */),
+    .io_mshrHintQInfo_bits_homeNID                        (/* unused */),
+    .io_mshrHintQInfo_bits_dbID                           (/* unused */),
+    .io_mshrHintQInfo_bits_fwdNID                         (/* unused */),
+    .io_mshrHintQInfo_bits_fwdTxnID                       (/* unused */),
+    .io_mshrHintQInfo_bits_chiOpcode                      (/* unused */),
+    .io_mshrHintQInfo_bits_resp                           (/* unused */),
+    .io_mshrHintQInfo_bits_fwdState                       (/* unused */),
+    .io_mshrHintQInfo_bits_pCrdType                       (/* unused */),
+    .io_mshrHintQInfo_bits_retToSrc                       (/* unused */),
+    .io_mshrHintQInfo_bits_likelyshared                   (/* unused */),
+    .io_mshrHintQInfo_bits_expCompAck                     (/* unused */),
+    .io_mshrHintQInfo_bits_allowRetry                     (/* unused */),
+    .io_mshrHintQInfo_bits_memAttr_allocate               (/* unused */),
+    .io_mshrHintQInfo_bits_memAttr_cacheable              (/* unused */),
+    .io_mshrHintQInfo_bits_memAttr_device                 (/* unused */),
+    .io_mshrHintQInfo_bits_memAttr_ewa                    (/* unused */),
+    .io_mshrHintQInfo_bits_traceTag                       (/* unused */),
+    .io_sinkCHintQInfo_valid
+      (_reqArb_io_sinkCHintQInfo_valid),
+    .io_sinkCHintQInfo_bits_channel                       (/* unused */),
+    .io_sinkCHintQInfo_bits_txChannel                     (/* unused */),
+    .io_sinkCHintQInfo_bits_set                           (/* unused */),
+    .io_sinkCHintQInfo_bits_tag                           (/* unused */),
+    .io_sinkCHintQInfo_bits_off                           (/* unused */),
+    .io_sinkCHintQInfo_bits_alias                         (/* unused */),
+    .io_sinkCHintQInfo_bits_vaddr                         (/* unused */),
+    .io_sinkCHintQInfo_bits_isKeyword                     (/* unused */),
+    .io_sinkCHintQInfo_bits_opcode                        (/* unused */),
+    .io_sinkCHintQInfo_bits_param                         (/* unused */),
+    .io_sinkCHintQInfo_bits_size                          (/* unused */),
+    .io_sinkCHintQInfo_bits_sourceId
+      (_reqArb_io_sinkCHintQInfo_bits_sourceId),
+    .io_sinkCHintQInfo_bits_bufIdx                        (/* unused */),
+    .io_sinkCHintQInfo_bits_needProbeAckData              (/* unused */),
+    .io_sinkCHintQInfo_bits_denied                        (/* unused */),
+    .io_sinkCHintQInfo_bits_corrupt                       (/* unused */),
+    .io_sinkCHintQInfo_bits_mshrTask                      (/* unused */),
+    .io_sinkCHintQInfo_bits_mshrId                        (/* unused */),
+    .io_sinkCHintQInfo_bits_aliasTask                     (/* unused */),
+    .io_sinkCHintQInfo_bits_useProbeData                  (/* unused */),
+    .io_sinkCHintQInfo_bits_mshrRetry                     (/* unused */),
+    .io_sinkCHintQInfo_bits_readProbeDataDown             (/* unused */),
+    .io_sinkCHintQInfo_bits_fromL2pft                     (/* unused */),
+    .io_sinkCHintQInfo_bits_needHint                      (/* unused */),
+    .io_sinkCHintQInfo_bits_dirty                         (/* unused */),
+    .io_sinkCHintQInfo_bits_way                           (/* unused */),
+    .io_sinkCHintQInfo_bits_meta_dirty                    (/* unused */),
+    .io_sinkCHintQInfo_bits_meta_state                    (/* unused */),
+    .io_sinkCHintQInfo_bits_meta_clients                  (/* unused */),
+    .io_sinkCHintQInfo_bits_meta_alias                    (/* unused */),
+    .io_sinkCHintQInfo_bits_meta_prefetch                 (/* unused */),
+    .io_sinkCHintQInfo_bits_meta_prefetchSrc              (/* unused */),
+    .io_sinkCHintQInfo_bits_meta_accessed                 (/* unused */),
+    .io_sinkCHintQInfo_bits_meta_tagErr                   (/* unused */),
+    .io_sinkCHintQInfo_bits_meta_dataErr                  (/* unused */),
+    .io_sinkCHintQInfo_bits_metaWen                       (/* unused */),
+    .io_sinkCHintQInfo_bits_tagWen                        (/* unused */),
+    .io_sinkCHintQInfo_bits_dsWen                         (/* unused */),
+    .io_sinkCHintQInfo_bits_wayMask                       (/* unused */),
+    .io_sinkCHintQInfo_bits_replTask                      (/* unused */),
+    .io_sinkCHintQInfo_bits_cmoTask                       (/* unused */),
+    .io_sinkCHintQInfo_bits_cmoAll                        (/* unused */),
+    .io_sinkCHintQInfo_bits_reqSource                     (/* unused */),
+    .io_sinkCHintQInfo_bits_mergeA                        (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_off                (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_alias              (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_vaddr              (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_isKeyword          (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_opcode             (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_param              (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_sourceId           (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_meta_dirty         (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_meta_state         (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_meta_clients       (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_meta_alias         (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_meta_prefetch      (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_meta_prefetchSrc   (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_meta_accessed      (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_meta_tagErr        (/* unused */),
+    .io_sinkCHintQInfo_bits_aMergeTask_meta_dataErr       (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitRelease                 (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseToInval          (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseToClean          (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseWithData         (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseIdx              (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseMeta_dirty       (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseMeta_state       (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseMeta_clients     (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseMeta_alias       (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseMeta_prefetch    (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseMeta_prefetchSrc (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseMeta_accessed    (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseMeta_tagErr      (/* unused */),
+    .io_sinkCHintQInfo_bits_snpHitReleaseMeta_dataErr     (/* unused */),
+    .io_sinkCHintQInfo_bits_tgtID                         (/* unused */),
+    .io_sinkCHintQInfo_bits_srcID                         (/* unused */),
+    .io_sinkCHintQInfo_bits_txnID                         (/* unused */),
+    .io_sinkCHintQInfo_bits_homeNID                       (/* unused */),
+    .io_sinkCHintQInfo_bits_dbID                          (/* unused */),
+    .io_sinkCHintQInfo_bits_fwdNID                        (/* unused */),
+    .io_sinkCHintQInfo_bits_fwdTxnID                      (/* unused */),
+    .io_sinkCHintQInfo_bits_chiOpcode                     (/* unused */),
+    .io_sinkCHintQInfo_bits_resp                          (/* unused */),
+    .io_sinkCHintQInfo_bits_fwdState                      (/* unused */),
+    .io_sinkCHintQInfo_bits_pCrdType                      (/* unused */),
+    .io_sinkCHintQInfo_bits_retToSrc                      (/* unused */),
+    .io_sinkCHintQInfo_bits_likelyshared                  (/* unused */),
+    .io_sinkCHintQInfo_bits_expCompAck                    (/* unused */),
+    .io_sinkCHintQInfo_bits_allowRetry                    (/* unused */),
+    .io_sinkCHintQInfo_bits_memAttr_allocate              (/* unused */),
+    .io_sinkCHintQInfo_bits_memAttr_cacheable             (/* unused */),
+    .io_sinkCHintQInfo_bits_memAttr_device                (/* unused */),
+    .io_sinkCHintQInfo_bits_memAttr_ewa                   (/* unused */),
+    .io_sinkCHintQInfo_bits_traceTag                      (/* unused */),
+    .io_refillBufRead_s2_valid
+      (_reqArb_io_refillBufRead_s2_valid),
+    .io_refillBufRead_s2_bits_id
+      (_reqArb_io_refillBufRead_s2_bits_id),
+    .io_releaseBufRead_s2_valid
+      (_reqArb_io_releaseBufRead_s2_valid),
+    .io_releaseBufRead_s2_bits_id
+      (_reqArb_io_releaseBufRead_s2_bits_id),
+    .io_status_s1_tags_0                                  (/* unused */),
+    .io_status_s1_tags_1                                  (_reqArb_io_status_s1_tags_1),
+    .io_status_s1_tags_2                                  (/* unused */),
+    .io_status_s1_tags_3                                  (/* unused */),
+    .io_status_s1_sets_0                                  (_reqArb_io_status_s1_sets_0),
+    .io_status_s1_sets_1                                  (_reqArb_io_status_s1_sets_1),
+    .io_status_s1_sets_2                                  (_reqArb_io_status_s1_sets_2),
+    .io_status_s1_sets_3                                  (_reqArb_io_status_s1_sets_3),
+    .io_status_vec_0_valid                                (/* unused */),
+    .io_status_vec_0_bits_channel                         (/* unused */),
+    .io_status_vec_1_valid                                (_reqArb_io_status_vec_1_valid),
+    .io_status_vec_1_bits_channel
+      (_reqArb_io_status_vec_1_bits_channel),
+    .io_status_vec_toTX_0_valid                           (/* unused */),
+    .io_status_vec_toTX_0_bits_channel                    (/* unused */),
+    .io_status_vec_toTX_0_bits_txChannel                  (/* unused */),
+    .io_status_vec_toTX_0_bits_mshrTask                   (/* unused */),
+    .io_status_vec_toTX_1_valid
+      (_reqArb_io_status_vec_toTX_1_valid),
+    .io_status_vec_toTX_1_bits_channel
+      (_reqArb_io_status_vec_toTX_1_bits_channel),
+    .io_status_vec_toTX_1_bits_txChannel
+      (_reqArb_io_status_vec_toTX_1_bits_txChannel),
+    .io_status_vec_toTX_1_bits_mshrTask
+      (_reqArb_io_status_vec_toTX_1_bits_mshrTask),
+    .io_fromMSHRCtl_blockG_s1                             (1'h0),
+    .io_fromMSHRCtl_blockA_s1
+      (_mshrCtl_io_toReqArb_blockA_s1),
+    .io_fromMSHRCtl_blockB_s1
+      (_mshrCtl_io_toReqArb_blockB_s1),
+    .io_fromMSHRCtl_blockC_s1                             (1'h0),
+    .io_fromMainPipe_blockG_s1
+      (_mainPipe_io_toReqArb_blockG_s1),
+    .io_fromMainPipe_blockA_s1                            (1'h0),
+    .io_fromMainPipe_blockB_s1
+      (_mainPipe_io_toReqArb_blockB_s1),
+    .io_fromMainPipe_blockC_s1
+      (_mainPipe_io_toReqArb_blockC_s1),
+    .io_fromGrantBuffer_blockSinkReqEntrance_blockG_s1    (1'h0),
+    .io_fromGrantBuffer_blockSinkReqEntrance_blockA_s1
+      (_grantBuf_io_toReqArb_blockSinkReqEntrance_blockA_s1),
+    .io_fromGrantBuffer_blockSinkReqEntrance_blockB_s1
+      (_grantBuf_io_toReqArb_blockSinkReqEntrance_blockB_s1),
+    .io_fromGrantBuffer_blockSinkReqEntrance_blockC_s1
+      (_grantBuf_io_toReqArb_blockSinkReqEntrance_blockC_s1),
+    .io_fromGrantBuffer_blockMSHRReqEntrance
+      (_grantBuf_io_toReqArb_blockMSHRReqEntrance),
+    .io_fromTXDAT_blockMSHRReqEntrance
+      (_txdat_io_toReqArb_blockMSHRReqEntrance),
+    .io_fromTXDAT_blockSinkBReqEntrance
+      (_txdat_io_toReqArb_blockSinkBReqEntrance),
+    .io_fromTXRSP_blockMSHRReqEntrance
+      (_txrsp_io_toReqArb_blockMSHRReqEntrance),
+    .io_fromTXRSP_blockSinkBReqEntrance
+      (_txrsp_io_toReqArb_blockSinkBReqEntrance),
+    .io_fromTXREQ_blockMSHRReqEntrance
+      (_txreq_io_toReqArb_blockMSHRReqEntrance),
+    .io_msInfo_0_valid                                    (_mshrCtl_io_msInfo_0_valid),
+    .io_msInfo_0_bits_channel
+      (_mshrCtl_io_msInfo_0_bits_channel),
+    .io_msInfo_0_bits_set                                 (_mshrCtl_io_msInfo_0_bits_set),
+    .io_msInfo_0_bits_way                                 (_mshrCtl_io_msInfo_0_bits_way),
+    .io_msInfo_0_bits_reqTag
+      (_mshrCtl_io_msInfo_0_bits_reqTag),
+    .io_msInfo_0_bits_reqSource
+      (_mshrCtl_io_msInfo_0_bits_reqSource),
+    .io_msInfo_0_bits_willFree
+      (_mshrCtl_io_msInfo_0_bits_willFree),
+    .io_msInfo_0_bits_aliasTask
+      (_mshrCtl_io_msInfo_0_bits_aliasTask),
+    .io_msInfo_0_bits_needRelease
+      (_mshrCtl_io_msInfo_0_bits_needRelease),
+    .io_msInfo_0_bits_blockRefill
+      (_mshrCtl_io_msInfo_0_bits_blockRefill),
+    .io_msInfo_0_bits_meta_dirty
+      (_mshrCtl_io_msInfo_0_bits_meta_dirty),
+    .io_msInfo_0_bits_meta_state
+      (_mshrCtl_io_msInfo_0_bits_meta_state),
+    .io_msInfo_0_bits_meta_clients
+      (_mshrCtl_io_msInfo_0_bits_meta_clients),
+    .io_msInfo_0_bits_meta_alias
+      (_mshrCtl_io_msInfo_0_bits_meta_alias),
+    .io_msInfo_0_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_0_bits_meta_prefetch),
+    .io_msInfo_0_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_0_bits_meta_prefetchSrc),
+    .io_msInfo_0_bits_meta_accessed
+      (_mshrCtl_io_msInfo_0_bits_meta_accessed),
+    .io_msInfo_0_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_0_bits_meta_tagErr),
+    .io_msInfo_0_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_0_bits_meta_dataErr),
+    .io_msInfo_0_bits_metaTag
+      (_mshrCtl_io_msInfo_0_bits_metaTag),
+    .io_msInfo_0_bits_dirHit
+      (_mshrCtl_io_msInfo_0_bits_dirHit),
+    .io_msInfo_0_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_0_bits_isAcqOrPrefetch),
+    .io_msInfo_0_bits_isPrefetch
+      (_mshrCtl_io_msInfo_0_bits_isPrefetch),
+    .io_msInfo_0_bits_param
+      (_mshrCtl_io_msInfo_0_bits_param),
+    .io_msInfo_0_bits_mergeA
+      (_mshrCtl_io_msInfo_0_bits_mergeA),
+    .io_msInfo_0_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_0_bits_w_grantfirst),
+    .io_msInfo_0_bits_w_grantlast
+      (_mshrCtl_io_msInfo_0_bits_w_grantlast),
+    .io_msInfo_0_bits_w_grant
+      (_mshrCtl_io_msInfo_0_bits_w_grant),
+    .io_msInfo_0_bits_s_release
+      (_mshrCtl_io_msInfo_0_bits_s_release),
+    .io_msInfo_0_bits_s_refill
+      (_mshrCtl_io_msInfo_0_bits_s_refill),
+    .io_msInfo_0_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_0_bits_s_cmoresp),
+    .io_msInfo_0_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_0_bits_s_cmometaw),
+    .io_msInfo_0_bits_w_releaseack
+      (_mshrCtl_io_msInfo_0_bits_w_releaseack),
+    .io_msInfo_0_bits_w_replResp
+      (_mshrCtl_io_msInfo_0_bits_w_replResp),
+    .io_msInfo_0_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_0_bits_w_rprobeacklast),
+    .io_msInfo_0_bits_replaceData
+      (_mshrCtl_io_msInfo_0_bits_replaceData),
+    .io_msInfo_0_bits_releaseToClean
+      (_mshrCtl_io_msInfo_0_bits_releaseToClean),
+    .io_msInfo_1_valid                                    (_mshrCtl_io_msInfo_1_valid),
+    .io_msInfo_1_bits_channel
+      (_mshrCtl_io_msInfo_1_bits_channel),
+    .io_msInfo_1_bits_set                                 (_mshrCtl_io_msInfo_1_bits_set),
+    .io_msInfo_1_bits_way                                 (_mshrCtl_io_msInfo_1_bits_way),
+    .io_msInfo_1_bits_reqTag
+      (_mshrCtl_io_msInfo_1_bits_reqTag),
+    .io_msInfo_1_bits_reqSource
+      (_mshrCtl_io_msInfo_1_bits_reqSource),
+    .io_msInfo_1_bits_willFree
+      (_mshrCtl_io_msInfo_1_bits_willFree),
+    .io_msInfo_1_bits_aliasTask
+      (_mshrCtl_io_msInfo_1_bits_aliasTask),
+    .io_msInfo_1_bits_needRelease
+      (_mshrCtl_io_msInfo_1_bits_needRelease),
+    .io_msInfo_1_bits_blockRefill
+      (_mshrCtl_io_msInfo_1_bits_blockRefill),
+    .io_msInfo_1_bits_meta_dirty
+      (_mshrCtl_io_msInfo_1_bits_meta_dirty),
+    .io_msInfo_1_bits_meta_state
+      (_mshrCtl_io_msInfo_1_bits_meta_state),
+    .io_msInfo_1_bits_meta_clients
+      (_mshrCtl_io_msInfo_1_bits_meta_clients),
+    .io_msInfo_1_bits_meta_alias
+      (_mshrCtl_io_msInfo_1_bits_meta_alias),
+    .io_msInfo_1_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_1_bits_meta_prefetch),
+    .io_msInfo_1_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_1_bits_meta_prefetchSrc),
+    .io_msInfo_1_bits_meta_accessed
+      (_mshrCtl_io_msInfo_1_bits_meta_accessed),
+    .io_msInfo_1_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_1_bits_meta_tagErr),
+    .io_msInfo_1_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_1_bits_meta_dataErr),
+    .io_msInfo_1_bits_metaTag
+      (_mshrCtl_io_msInfo_1_bits_metaTag),
+    .io_msInfo_1_bits_dirHit
+      (_mshrCtl_io_msInfo_1_bits_dirHit),
+    .io_msInfo_1_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_1_bits_isAcqOrPrefetch),
+    .io_msInfo_1_bits_isPrefetch
+      (_mshrCtl_io_msInfo_1_bits_isPrefetch),
+    .io_msInfo_1_bits_param
+      (_mshrCtl_io_msInfo_1_bits_param),
+    .io_msInfo_1_bits_mergeA
+      (_mshrCtl_io_msInfo_1_bits_mergeA),
+    .io_msInfo_1_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_1_bits_w_grantfirst),
+    .io_msInfo_1_bits_w_grantlast
+      (_mshrCtl_io_msInfo_1_bits_w_grantlast),
+    .io_msInfo_1_bits_w_grant
+      (_mshrCtl_io_msInfo_1_bits_w_grant),
+    .io_msInfo_1_bits_s_release
+      (_mshrCtl_io_msInfo_1_bits_s_release),
+    .io_msInfo_1_bits_s_refill
+      (_mshrCtl_io_msInfo_1_bits_s_refill),
+    .io_msInfo_1_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_1_bits_s_cmoresp),
+    .io_msInfo_1_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_1_bits_s_cmometaw),
+    .io_msInfo_1_bits_w_releaseack
+      (_mshrCtl_io_msInfo_1_bits_w_releaseack),
+    .io_msInfo_1_bits_w_replResp
+      (_mshrCtl_io_msInfo_1_bits_w_replResp),
+    .io_msInfo_1_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_1_bits_w_rprobeacklast),
+    .io_msInfo_1_bits_replaceData
+      (_mshrCtl_io_msInfo_1_bits_replaceData),
+    .io_msInfo_1_bits_releaseToClean
+      (_mshrCtl_io_msInfo_1_bits_releaseToClean),
+    .io_msInfo_2_valid                                    (_mshrCtl_io_msInfo_2_valid),
+    .io_msInfo_2_bits_channel
+      (_mshrCtl_io_msInfo_2_bits_channel),
+    .io_msInfo_2_bits_set                                 (_mshrCtl_io_msInfo_2_bits_set),
+    .io_msInfo_2_bits_way                                 (_mshrCtl_io_msInfo_2_bits_way),
+    .io_msInfo_2_bits_reqTag
+      (_mshrCtl_io_msInfo_2_bits_reqTag),
+    .io_msInfo_2_bits_reqSource
+      (_mshrCtl_io_msInfo_2_bits_reqSource),
+    .io_msInfo_2_bits_willFree
+      (_mshrCtl_io_msInfo_2_bits_willFree),
+    .io_msInfo_2_bits_aliasTask
+      (_mshrCtl_io_msInfo_2_bits_aliasTask),
+    .io_msInfo_2_bits_needRelease
+      (_mshrCtl_io_msInfo_2_bits_needRelease),
+    .io_msInfo_2_bits_blockRefill
+      (_mshrCtl_io_msInfo_2_bits_blockRefill),
+    .io_msInfo_2_bits_meta_dirty
+      (_mshrCtl_io_msInfo_2_bits_meta_dirty),
+    .io_msInfo_2_bits_meta_state
+      (_mshrCtl_io_msInfo_2_bits_meta_state),
+    .io_msInfo_2_bits_meta_clients
+      (_mshrCtl_io_msInfo_2_bits_meta_clients),
+    .io_msInfo_2_bits_meta_alias
+      (_mshrCtl_io_msInfo_2_bits_meta_alias),
+    .io_msInfo_2_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_2_bits_meta_prefetch),
+    .io_msInfo_2_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_2_bits_meta_prefetchSrc),
+    .io_msInfo_2_bits_meta_accessed
+      (_mshrCtl_io_msInfo_2_bits_meta_accessed),
+    .io_msInfo_2_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_2_bits_meta_tagErr),
+    .io_msInfo_2_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_2_bits_meta_dataErr),
+    .io_msInfo_2_bits_metaTag
+      (_mshrCtl_io_msInfo_2_bits_metaTag),
+    .io_msInfo_2_bits_dirHit
+      (_mshrCtl_io_msInfo_2_bits_dirHit),
+    .io_msInfo_2_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_2_bits_isAcqOrPrefetch),
+    .io_msInfo_2_bits_isPrefetch
+      (_mshrCtl_io_msInfo_2_bits_isPrefetch),
+    .io_msInfo_2_bits_param
+      (_mshrCtl_io_msInfo_2_bits_param),
+    .io_msInfo_2_bits_mergeA
+      (_mshrCtl_io_msInfo_2_bits_mergeA),
+    .io_msInfo_2_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_2_bits_w_grantfirst),
+    .io_msInfo_2_bits_w_grantlast
+      (_mshrCtl_io_msInfo_2_bits_w_grantlast),
+    .io_msInfo_2_bits_w_grant
+      (_mshrCtl_io_msInfo_2_bits_w_grant),
+    .io_msInfo_2_bits_s_release
+      (_mshrCtl_io_msInfo_2_bits_s_release),
+    .io_msInfo_2_bits_s_refill
+      (_mshrCtl_io_msInfo_2_bits_s_refill),
+    .io_msInfo_2_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_2_bits_s_cmoresp),
+    .io_msInfo_2_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_2_bits_s_cmometaw),
+    .io_msInfo_2_bits_w_releaseack
+      (_mshrCtl_io_msInfo_2_bits_w_releaseack),
+    .io_msInfo_2_bits_w_replResp
+      (_mshrCtl_io_msInfo_2_bits_w_replResp),
+    .io_msInfo_2_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_2_bits_w_rprobeacklast),
+    .io_msInfo_2_bits_replaceData
+      (_mshrCtl_io_msInfo_2_bits_replaceData),
+    .io_msInfo_2_bits_releaseToClean
+      (_mshrCtl_io_msInfo_2_bits_releaseToClean),
+    .io_msInfo_3_valid                                    (_mshrCtl_io_msInfo_3_valid),
+    .io_msInfo_3_bits_channel
+      (_mshrCtl_io_msInfo_3_bits_channel),
+    .io_msInfo_3_bits_set                                 (_mshrCtl_io_msInfo_3_bits_set),
+    .io_msInfo_3_bits_way                                 (_mshrCtl_io_msInfo_3_bits_way),
+    .io_msInfo_3_bits_reqTag
+      (_mshrCtl_io_msInfo_3_bits_reqTag),
+    .io_msInfo_3_bits_reqSource
+      (_mshrCtl_io_msInfo_3_bits_reqSource),
+    .io_msInfo_3_bits_willFree
+      (_mshrCtl_io_msInfo_3_bits_willFree),
+    .io_msInfo_3_bits_aliasTask
+      (_mshrCtl_io_msInfo_3_bits_aliasTask),
+    .io_msInfo_3_bits_needRelease
+      (_mshrCtl_io_msInfo_3_bits_needRelease),
+    .io_msInfo_3_bits_blockRefill
+      (_mshrCtl_io_msInfo_3_bits_blockRefill),
+    .io_msInfo_3_bits_meta_dirty
+      (_mshrCtl_io_msInfo_3_bits_meta_dirty),
+    .io_msInfo_3_bits_meta_state
+      (_mshrCtl_io_msInfo_3_bits_meta_state),
+    .io_msInfo_3_bits_meta_clients
+      (_mshrCtl_io_msInfo_3_bits_meta_clients),
+    .io_msInfo_3_bits_meta_alias
+      (_mshrCtl_io_msInfo_3_bits_meta_alias),
+    .io_msInfo_3_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_3_bits_meta_prefetch),
+    .io_msInfo_3_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_3_bits_meta_prefetchSrc),
+    .io_msInfo_3_bits_meta_accessed
+      (_mshrCtl_io_msInfo_3_bits_meta_accessed),
+    .io_msInfo_3_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_3_bits_meta_tagErr),
+    .io_msInfo_3_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_3_bits_meta_dataErr),
+    .io_msInfo_3_bits_metaTag
+      (_mshrCtl_io_msInfo_3_bits_metaTag),
+    .io_msInfo_3_bits_dirHit
+      (_mshrCtl_io_msInfo_3_bits_dirHit),
+    .io_msInfo_3_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_3_bits_isAcqOrPrefetch),
+    .io_msInfo_3_bits_isPrefetch
+      (_mshrCtl_io_msInfo_3_bits_isPrefetch),
+    .io_msInfo_3_bits_param
+      (_mshrCtl_io_msInfo_3_bits_param),
+    .io_msInfo_3_bits_mergeA
+      (_mshrCtl_io_msInfo_3_bits_mergeA),
+    .io_msInfo_3_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_3_bits_w_grantfirst),
+    .io_msInfo_3_bits_w_grantlast
+      (_mshrCtl_io_msInfo_3_bits_w_grantlast),
+    .io_msInfo_3_bits_w_grant
+      (_mshrCtl_io_msInfo_3_bits_w_grant),
+    .io_msInfo_3_bits_s_release
+      (_mshrCtl_io_msInfo_3_bits_s_release),
+    .io_msInfo_3_bits_s_refill
+      (_mshrCtl_io_msInfo_3_bits_s_refill),
+    .io_msInfo_3_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_3_bits_s_cmoresp),
+    .io_msInfo_3_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_3_bits_s_cmometaw),
+    .io_msInfo_3_bits_w_releaseack
+      (_mshrCtl_io_msInfo_3_bits_w_releaseack),
+    .io_msInfo_3_bits_w_replResp
+      (_mshrCtl_io_msInfo_3_bits_w_replResp),
+    .io_msInfo_3_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_3_bits_w_rprobeacklast),
+    .io_msInfo_3_bits_replaceData
+      (_mshrCtl_io_msInfo_3_bits_replaceData),
+    .io_msInfo_3_bits_releaseToClean
+      (_mshrCtl_io_msInfo_3_bits_releaseToClean),
+    .io_msInfo_4_valid                                    (_mshrCtl_io_msInfo_4_valid),
+    .io_msInfo_4_bits_channel
+      (_mshrCtl_io_msInfo_4_bits_channel),
+    .io_msInfo_4_bits_set                                 (_mshrCtl_io_msInfo_4_bits_set),
+    .io_msInfo_4_bits_way                                 (_mshrCtl_io_msInfo_4_bits_way),
+    .io_msInfo_4_bits_reqTag
+      (_mshrCtl_io_msInfo_4_bits_reqTag),
+    .io_msInfo_4_bits_reqSource
+      (_mshrCtl_io_msInfo_4_bits_reqSource),
+    .io_msInfo_4_bits_willFree
+      (_mshrCtl_io_msInfo_4_bits_willFree),
+    .io_msInfo_4_bits_aliasTask
+      (_mshrCtl_io_msInfo_4_bits_aliasTask),
+    .io_msInfo_4_bits_needRelease
+      (_mshrCtl_io_msInfo_4_bits_needRelease),
+    .io_msInfo_4_bits_blockRefill
+      (_mshrCtl_io_msInfo_4_bits_blockRefill),
+    .io_msInfo_4_bits_meta_dirty
+      (_mshrCtl_io_msInfo_4_bits_meta_dirty),
+    .io_msInfo_4_bits_meta_state
+      (_mshrCtl_io_msInfo_4_bits_meta_state),
+    .io_msInfo_4_bits_meta_clients
+      (_mshrCtl_io_msInfo_4_bits_meta_clients),
+    .io_msInfo_4_bits_meta_alias
+      (_mshrCtl_io_msInfo_4_bits_meta_alias),
+    .io_msInfo_4_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_4_bits_meta_prefetch),
+    .io_msInfo_4_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_4_bits_meta_prefetchSrc),
+    .io_msInfo_4_bits_meta_accessed
+      (_mshrCtl_io_msInfo_4_bits_meta_accessed),
+    .io_msInfo_4_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_4_bits_meta_tagErr),
+    .io_msInfo_4_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_4_bits_meta_dataErr),
+    .io_msInfo_4_bits_metaTag
+      (_mshrCtl_io_msInfo_4_bits_metaTag),
+    .io_msInfo_4_bits_dirHit
+      (_mshrCtl_io_msInfo_4_bits_dirHit),
+    .io_msInfo_4_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_4_bits_isAcqOrPrefetch),
+    .io_msInfo_4_bits_isPrefetch
+      (_mshrCtl_io_msInfo_4_bits_isPrefetch),
+    .io_msInfo_4_bits_param
+      (_mshrCtl_io_msInfo_4_bits_param),
+    .io_msInfo_4_bits_mergeA
+      (_mshrCtl_io_msInfo_4_bits_mergeA),
+    .io_msInfo_4_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_4_bits_w_grantfirst),
+    .io_msInfo_4_bits_w_grantlast
+      (_mshrCtl_io_msInfo_4_bits_w_grantlast),
+    .io_msInfo_4_bits_w_grant
+      (_mshrCtl_io_msInfo_4_bits_w_grant),
+    .io_msInfo_4_bits_s_release
+      (_mshrCtl_io_msInfo_4_bits_s_release),
+    .io_msInfo_4_bits_s_refill
+      (_mshrCtl_io_msInfo_4_bits_s_refill),
+    .io_msInfo_4_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_4_bits_s_cmoresp),
+    .io_msInfo_4_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_4_bits_s_cmometaw),
+    .io_msInfo_4_bits_w_releaseack
+      (_mshrCtl_io_msInfo_4_bits_w_releaseack),
+    .io_msInfo_4_bits_w_replResp
+      (_mshrCtl_io_msInfo_4_bits_w_replResp),
+    .io_msInfo_4_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_4_bits_w_rprobeacklast),
+    .io_msInfo_4_bits_replaceData
+      (_mshrCtl_io_msInfo_4_bits_replaceData),
+    .io_msInfo_4_bits_releaseToClean
+      (_mshrCtl_io_msInfo_4_bits_releaseToClean),
+    .io_msInfo_5_valid                                    (_mshrCtl_io_msInfo_5_valid),
+    .io_msInfo_5_bits_channel
+      (_mshrCtl_io_msInfo_5_bits_channel),
+    .io_msInfo_5_bits_set                                 (_mshrCtl_io_msInfo_5_bits_set),
+    .io_msInfo_5_bits_way                                 (_mshrCtl_io_msInfo_5_bits_way),
+    .io_msInfo_5_bits_reqTag
+      (_mshrCtl_io_msInfo_5_bits_reqTag),
+    .io_msInfo_5_bits_reqSource
+      (_mshrCtl_io_msInfo_5_bits_reqSource),
+    .io_msInfo_5_bits_willFree
+      (_mshrCtl_io_msInfo_5_bits_willFree),
+    .io_msInfo_5_bits_aliasTask
+      (_mshrCtl_io_msInfo_5_bits_aliasTask),
+    .io_msInfo_5_bits_needRelease
+      (_mshrCtl_io_msInfo_5_bits_needRelease),
+    .io_msInfo_5_bits_blockRefill
+      (_mshrCtl_io_msInfo_5_bits_blockRefill),
+    .io_msInfo_5_bits_meta_dirty
+      (_mshrCtl_io_msInfo_5_bits_meta_dirty),
+    .io_msInfo_5_bits_meta_state
+      (_mshrCtl_io_msInfo_5_bits_meta_state),
+    .io_msInfo_5_bits_meta_clients
+      (_mshrCtl_io_msInfo_5_bits_meta_clients),
+    .io_msInfo_5_bits_meta_alias
+      (_mshrCtl_io_msInfo_5_bits_meta_alias),
+    .io_msInfo_5_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_5_bits_meta_prefetch),
+    .io_msInfo_5_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_5_bits_meta_prefetchSrc),
+    .io_msInfo_5_bits_meta_accessed
+      (_mshrCtl_io_msInfo_5_bits_meta_accessed),
+    .io_msInfo_5_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_5_bits_meta_tagErr),
+    .io_msInfo_5_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_5_bits_meta_dataErr),
+    .io_msInfo_5_bits_metaTag
+      (_mshrCtl_io_msInfo_5_bits_metaTag),
+    .io_msInfo_5_bits_dirHit
+      (_mshrCtl_io_msInfo_5_bits_dirHit),
+    .io_msInfo_5_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_5_bits_isAcqOrPrefetch),
+    .io_msInfo_5_bits_isPrefetch
+      (_mshrCtl_io_msInfo_5_bits_isPrefetch),
+    .io_msInfo_5_bits_param
+      (_mshrCtl_io_msInfo_5_bits_param),
+    .io_msInfo_5_bits_mergeA
+      (_mshrCtl_io_msInfo_5_bits_mergeA),
+    .io_msInfo_5_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_5_bits_w_grantfirst),
+    .io_msInfo_5_bits_w_grantlast
+      (_mshrCtl_io_msInfo_5_bits_w_grantlast),
+    .io_msInfo_5_bits_w_grant
+      (_mshrCtl_io_msInfo_5_bits_w_grant),
+    .io_msInfo_5_bits_s_release
+      (_mshrCtl_io_msInfo_5_bits_s_release),
+    .io_msInfo_5_bits_s_refill
+      (_mshrCtl_io_msInfo_5_bits_s_refill),
+    .io_msInfo_5_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_5_bits_s_cmoresp),
+    .io_msInfo_5_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_5_bits_s_cmometaw),
+    .io_msInfo_5_bits_w_releaseack
+      (_mshrCtl_io_msInfo_5_bits_w_releaseack),
+    .io_msInfo_5_bits_w_replResp
+      (_mshrCtl_io_msInfo_5_bits_w_replResp),
+    .io_msInfo_5_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_5_bits_w_rprobeacklast),
+    .io_msInfo_5_bits_replaceData
+      (_mshrCtl_io_msInfo_5_bits_replaceData),
+    .io_msInfo_5_bits_releaseToClean
+      (_mshrCtl_io_msInfo_5_bits_releaseToClean),
+    .io_msInfo_6_valid                                    (_mshrCtl_io_msInfo_6_valid),
+    .io_msInfo_6_bits_channel
+      (_mshrCtl_io_msInfo_6_bits_channel),
+    .io_msInfo_6_bits_set                                 (_mshrCtl_io_msInfo_6_bits_set),
+    .io_msInfo_6_bits_way                                 (_mshrCtl_io_msInfo_6_bits_way),
+    .io_msInfo_6_bits_reqTag
+      (_mshrCtl_io_msInfo_6_bits_reqTag),
+    .io_msInfo_6_bits_reqSource
+      (_mshrCtl_io_msInfo_6_bits_reqSource),
+    .io_msInfo_6_bits_willFree
+      (_mshrCtl_io_msInfo_6_bits_willFree),
+    .io_msInfo_6_bits_aliasTask
+      (_mshrCtl_io_msInfo_6_bits_aliasTask),
+    .io_msInfo_6_bits_needRelease
+      (_mshrCtl_io_msInfo_6_bits_needRelease),
+    .io_msInfo_6_bits_blockRefill
+      (_mshrCtl_io_msInfo_6_bits_blockRefill),
+    .io_msInfo_6_bits_meta_dirty
+      (_mshrCtl_io_msInfo_6_bits_meta_dirty),
+    .io_msInfo_6_bits_meta_state
+      (_mshrCtl_io_msInfo_6_bits_meta_state),
+    .io_msInfo_6_bits_meta_clients
+      (_mshrCtl_io_msInfo_6_bits_meta_clients),
+    .io_msInfo_6_bits_meta_alias
+      (_mshrCtl_io_msInfo_6_bits_meta_alias),
+    .io_msInfo_6_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_6_bits_meta_prefetch),
+    .io_msInfo_6_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_6_bits_meta_prefetchSrc),
+    .io_msInfo_6_bits_meta_accessed
+      (_mshrCtl_io_msInfo_6_bits_meta_accessed),
+    .io_msInfo_6_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_6_bits_meta_tagErr),
+    .io_msInfo_6_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_6_bits_meta_dataErr),
+    .io_msInfo_6_bits_metaTag
+      (_mshrCtl_io_msInfo_6_bits_metaTag),
+    .io_msInfo_6_bits_dirHit
+      (_mshrCtl_io_msInfo_6_bits_dirHit),
+    .io_msInfo_6_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_6_bits_isAcqOrPrefetch),
+    .io_msInfo_6_bits_isPrefetch
+      (_mshrCtl_io_msInfo_6_bits_isPrefetch),
+    .io_msInfo_6_bits_param
+      (_mshrCtl_io_msInfo_6_bits_param),
+    .io_msInfo_6_bits_mergeA
+      (_mshrCtl_io_msInfo_6_bits_mergeA),
+    .io_msInfo_6_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_6_bits_w_grantfirst),
+    .io_msInfo_6_bits_w_grantlast
+      (_mshrCtl_io_msInfo_6_bits_w_grantlast),
+    .io_msInfo_6_bits_w_grant
+      (_mshrCtl_io_msInfo_6_bits_w_grant),
+    .io_msInfo_6_bits_s_release
+      (_mshrCtl_io_msInfo_6_bits_s_release),
+    .io_msInfo_6_bits_s_refill
+      (_mshrCtl_io_msInfo_6_bits_s_refill),
+    .io_msInfo_6_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_6_bits_s_cmoresp),
+    .io_msInfo_6_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_6_bits_s_cmometaw),
+    .io_msInfo_6_bits_w_releaseack
+      (_mshrCtl_io_msInfo_6_bits_w_releaseack),
+    .io_msInfo_6_bits_w_replResp
+      (_mshrCtl_io_msInfo_6_bits_w_replResp),
+    .io_msInfo_6_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_6_bits_w_rprobeacklast),
+    .io_msInfo_6_bits_replaceData
+      (_mshrCtl_io_msInfo_6_bits_replaceData),
+    .io_msInfo_6_bits_releaseToClean
+      (_mshrCtl_io_msInfo_6_bits_releaseToClean),
+    .io_msInfo_7_valid                                    (_mshrCtl_io_msInfo_7_valid),
+    .io_msInfo_7_bits_channel
+      (_mshrCtl_io_msInfo_7_bits_channel),
+    .io_msInfo_7_bits_set                                 (_mshrCtl_io_msInfo_7_bits_set),
+    .io_msInfo_7_bits_way                                 (_mshrCtl_io_msInfo_7_bits_way),
+    .io_msInfo_7_bits_reqTag
+      (_mshrCtl_io_msInfo_7_bits_reqTag),
+    .io_msInfo_7_bits_reqSource
+      (_mshrCtl_io_msInfo_7_bits_reqSource),
+    .io_msInfo_7_bits_willFree
+      (_mshrCtl_io_msInfo_7_bits_willFree),
+    .io_msInfo_7_bits_aliasTask
+      (_mshrCtl_io_msInfo_7_bits_aliasTask),
+    .io_msInfo_7_bits_needRelease
+      (_mshrCtl_io_msInfo_7_bits_needRelease),
+    .io_msInfo_7_bits_blockRefill
+      (_mshrCtl_io_msInfo_7_bits_blockRefill),
+    .io_msInfo_7_bits_meta_dirty
+      (_mshrCtl_io_msInfo_7_bits_meta_dirty),
+    .io_msInfo_7_bits_meta_state
+      (_mshrCtl_io_msInfo_7_bits_meta_state),
+    .io_msInfo_7_bits_meta_clients
+      (_mshrCtl_io_msInfo_7_bits_meta_clients),
+    .io_msInfo_7_bits_meta_alias
+      (_mshrCtl_io_msInfo_7_bits_meta_alias),
+    .io_msInfo_7_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_7_bits_meta_prefetch),
+    .io_msInfo_7_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_7_bits_meta_prefetchSrc),
+    .io_msInfo_7_bits_meta_accessed
+      (_mshrCtl_io_msInfo_7_bits_meta_accessed),
+    .io_msInfo_7_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_7_bits_meta_tagErr),
+    .io_msInfo_7_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_7_bits_meta_dataErr),
+    .io_msInfo_7_bits_metaTag
+      (_mshrCtl_io_msInfo_7_bits_metaTag),
+    .io_msInfo_7_bits_dirHit
+      (_mshrCtl_io_msInfo_7_bits_dirHit),
+    .io_msInfo_7_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_7_bits_isAcqOrPrefetch),
+    .io_msInfo_7_bits_isPrefetch
+      (_mshrCtl_io_msInfo_7_bits_isPrefetch),
+    .io_msInfo_7_bits_param
+      (_mshrCtl_io_msInfo_7_bits_param),
+    .io_msInfo_7_bits_mergeA
+      (_mshrCtl_io_msInfo_7_bits_mergeA),
+    .io_msInfo_7_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_7_bits_w_grantfirst),
+    .io_msInfo_7_bits_w_grantlast
+      (_mshrCtl_io_msInfo_7_bits_w_grantlast),
+    .io_msInfo_7_bits_w_grant
+      (_mshrCtl_io_msInfo_7_bits_w_grant),
+    .io_msInfo_7_bits_s_release
+      (_mshrCtl_io_msInfo_7_bits_s_release),
+    .io_msInfo_7_bits_s_refill
+      (_mshrCtl_io_msInfo_7_bits_s_refill),
+    .io_msInfo_7_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_7_bits_s_cmoresp),
+    .io_msInfo_7_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_7_bits_s_cmometaw),
+    .io_msInfo_7_bits_w_releaseack
+      (_mshrCtl_io_msInfo_7_bits_w_releaseack),
+    .io_msInfo_7_bits_w_replResp
+      (_mshrCtl_io_msInfo_7_bits_w_replResp),
+    .io_msInfo_7_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_7_bits_w_rprobeacklast),
+    .io_msInfo_7_bits_replaceData
+      (_mshrCtl_io_msInfo_7_bits_replaceData),
+    .io_msInfo_7_bits_releaseToClean
+      (_mshrCtl_io_msInfo_7_bits_releaseToClean),
+    .io_msInfo_8_valid                                    (_mshrCtl_io_msInfo_8_valid),
+    .io_msInfo_8_bits_channel
+      (_mshrCtl_io_msInfo_8_bits_channel),
+    .io_msInfo_8_bits_set                                 (_mshrCtl_io_msInfo_8_bits_set),
+    .io_msInfo_8_bits_way                                 (_mshrCtl_io_msInfo_8_bits_way),
+    .io_msInfo_8_bits_reqTag
+      (_mshrCtl_io_msInfo_8_bits_reqTag),
+    .io_msInfo_8_bits_reqSource
+      (_mshrCtl_io_msInfo_8_bits_reqSource),
+    .io_msInfo_8_bits_willFree
+      (_mshrCtl_io_msInfo_8_bits_willFree),
+    .io_msInfo_8_bits_aliasTask
+      (_mshrCtl_io_msInfo_8_bits_aliasTask),
+    .io_msInfo_8_bits_needRelease
+      (_mshrCtl_io_msInfo_8_bits_needRelease),
+    .io_msInfo_8_bits_blockRefill
+      (_mshrCtl_io_msInfo_8_bits_blockRefill),
+    .io_msInfo_8_bits_meta_dirty
+      (_mshrCtl_io_msInfo_8_bits_meta_dirty),
+    .io_msInfo_8_bits_meta_state
+      (_mshrCtl_io_msInfo_8_bits_meta_state),
+    .io_msInfo_8_bits_meta_clients
+      (_mshrCtl_io_msInfo_8_bits_meta_clients),
+    .io_msInfo_8_bits_meta_alias
+      (_mshrCtl_io_msInfo_8_bits_meta_alias),
+    .io_msInfo_8_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_8_bits_meta_prefetch),
+    .io_msInfo_8_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_8_bits_meta_prefetchSrc),
+    .io_msInfo_8_bits_meta_accessed
+      (_mshrCtl_io_msInfo_8_bits_meta_accessed),
+    .io_msInfo_8_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_8_bits_meta_tagErr),
+    .io_msInfo_8_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_8_bits_meta_dataErr),
+    .io_msInfo_8_bits_metaTag
+      (_mshrCtl_io_msInfo_8_bits_metaTag),
+    .io_msInfo_8_bits_dirHit
+      (_mshrCtl_io_msInfo_8_bits_dirHit),
+    .io_msInfo_8_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_8_bits_isAcqOrPrefetch),
+    .io_msInfo_8_bits_isPrefetch
+      (_mshrCtl_io_msInfo_8_bits_isPrefetch),
+    .io_msInfo_8_bits_param
+      (_mshrCtl_io_msInfo_8_bits_param),
+    .io_msInfo_8_bits_mergeA
+      (_mshrCtl_io_msInfo_8_bits_mergeA),
+    .io_msInfo_8_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_8_bits_w_grantfirst),
+    .io_msInfo_8_bits_w_grantlast
+      (_mshrCtl_io_msInfo_8_bits_w_grantlast),
+    .io_msInfo_8_bits_w_grant
+      (_mshrCtl_io_msInfo_8_bits_w_grant),
+    .io_msInfo_8_bits_s_release
+      (_mshrCtl_io_msInfo_8_bits_s_release),
+    .io_msInfo_8_bits_s_refill
+      (_mshrCtl_io_msInfo_8_bits_s_refill),
+    .io_msInfo_8_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_8_bits_s_cmoresp),
+    .io_msInfo_8_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_8_bits_s_cmometaw),
+    .io_msInfo_8_bits_w_releaseack
+      (_mshrCtl_io_msInfo_8_bits_w_releaseack),
+    .io_msInfo_8_bits_w_replResp
+      (_mshrCtl_io_msInfo_8_bits_w_replResp),
+    .io_msInfo_8_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_8_bits_w_rprobeacklast),
+    .io_msInfo_8_bits_replaceData
+      (_mshrCtl_io_msInfo_8_bits_replaceData),
+    .io_msInfo_8_bits_releaseToClean
+      (_mshrCtl_io_msInfo_8_bits_releaseToClean),
+    .io_msInfo_9_valid                                    (_mshrCtl_io_msInfo_9_valid),
+    .io_msInfo_9_bits_channel
+      (_mshrCtl_io_msInfo_9_bits_channel),
+    .io_msInfo_9_bits_set                                 (_mshrCtl_io_msInfo_9_bits_set),
+    .io_msInfo_9_bits_way                                 (_mshrCtl_io_msInfo_9_bits_way),
+    .io_msInfo_9_bits_reqTag
+      (_mshrCtl_io_msInfo_9_bits_reqTag),
+    .io_msInfo_9_bits_reqSource
+      (_mshrCtl_io_msInfo_9_bits_reqSource),
+    .io_msInfo_9_bits_willFree
+      (_mshrCtl_io_msInfo_9_bits_willFree),
+    .io_msInfo_9_bits_aliasTask
+      (_mshrCtl_io_msInfo_9_bits_aliasTask),
+    .io_msInfo_9_bits_needRelease
+      (_mshrCtl_io_msInfo_9_bits_needRelease),
+    .io_msInfo_9_bits_blockRefill
+      (_mshrCtl_io_msInfo_9_bits_blockRefill),
+    .io_msInfo_9_bits_meta_dirty
+      (_mshrCtl_io_msInfo_9_bits_meta_dirty),
+    .io_msInfo_9_bits_meta_state
+      (_mshrCtl_io_msInfo_9_bits_meta_state),
+    .io_msInfo_9_bits_meta_clients
+      (_mshrCtl_io_msInfo_9_bits_meta_clients),
+    .io_msInfo_9_bits_meta_alias
+      (_mshrCtl_io_msInfo_9_bits_meta_alias),
+    .io_msInfo_9_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_9_bits_meta_prefetch),
+    .io_msInfo_9_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_9_bits_meta_prefetchSrc),
+    .io_msInfo_9_bits_meta_accessed
+      (_mshrCtl_io_msInfo_9_bits_meta_accessed),
+    .io_msInfo_9_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_9_bits_meta_tagErr),
+    .io_msInfo_9_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_9_bits_meta_dataErr),
+    .io_msInfo_9_bits_metaTag
+      (_mshrCtl_io_msInfo_9_bits_metaTag),
+    .io_msInfo_9_bits_dirHit
+      (_mshrCtl_io_msInfo_9_bits_dirHit),
+    .io_msInfo_9_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_9_bits_isAcqOrPrefetch),
+    .io_msInfo_9_bits_isPrefetch
+      (_mshrCtl_io_msInfo_9_bits_isPrefetch),
+    .io_msInfo_9_bits_param
+      (_mshrCtl_io_msInfo_9_bits_param),
+    .io_msInfo_9_bits_mergeA
+      (_mshrCtl_io_msInfo_9_bits_mergeA),
+    .io_msInfo_9_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_9_bits_w_grantfirst),
+    .io_msInfo_9_bits_w_grantlast
+      (_mshrCtl_io_msInfo_9_bits_w_grantlast),
+    .io_msInfo_9_bits_w_grant
+      (_mshrCtl_io_msInfo_9_bits_w_grant),
+    .io_msInfo_9_bits_s_release
+      (_mshrCtl_io_msInfo_9_bits_s_release),
+    .io_msInfo_9_bits_s_refill
+      (_mshrCtl_io_msInfo_9_bits_s_refill),
+    .io_msInfo_9_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_9_bits_s_cmoresp),
+    .io_msInfo_9_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_9_bits_s_cmometaw),
+    .io_msInfo_9_bits_w_releaseack
+      (_mshrCtl_io_msInfo_9_bits_w_releaseack),
+    .io_msInfo_9_bits_w_replResp
+      (_mshrCtl_io_msInfo_9_bits_w_replResp),
+    .io_msInfo_9_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_9_bits_w_rprobeacklast),
+    .io_msInfo_9_bits_replaceData
+      (_mshrCtl_io_msInfo_9_bits_replaceData),
+    .io_msInfo_9_bits_releaseToClean
+      (_mshrCtl_io_msInfo_9_bits_releaseToClean),
+    .io_msInfo_10_valid                                   (_mshrCtl_io_msInfo_10_valid),
+    .io_msInfo_10_bits_channel
+      (_mshrCtl_io_msInfo_10_bits_channel),
+    .io_msInfo_10_bits_set
+      (_mshrCtl_io_msInfo_10_bits_set),
+    .io_msInfo_10_bits_way
+      (_mshrCtl_io_msInfo_10_bits_way),
+    .io_msInfo_10_bits_reqTag
+      (_mshrCtl_io_msInfo_10_bits_reqTag),
+    .io_msInfo_10_bits_reqSource
+      (_mshrCtl_io_msInfo_10_bits_reqSource),
+    .io_msInfo_10_bits_willFree
+      (_mshrCtl_io_msInfo_10_bits_willFree),
+    .io_msInfo_10_bits_aliasTask
+      (_mshrCtl_io_msInfo_10_bits_aliasTask),
+    .io_msInfo_10_bits_needRelease
+      (_mshrCtl_io_msInfo_10_bits_needRelease),
+    .io_msInfo_10_bits_blockRefill
+      (_mshrCtl_io_msInfo_10_bits_blockRefill),
+    .io_msInfo_10_bits_meta_dirty
+      (_mshrCtl_io_msInfo_10_bits_meta_dirty),
+    .io_msInfo_10_bits_meta_state
+      (_mshrCtl_io_msInfo_10_bits_meta_state),
+    .io_msInfo_10_bits_meta_clients
+      (_mshrCtl_io_msInfo_10_bits_meta_clients),
+    .io_msInfo_10_bits_meta_alias
+      (_mshrCtl_io_msInfo_10_bits_meta_alias),
+    .io_msInfo_10_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_10_bits_meta_prefetch),
+    .io_msInfo_10_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_10_bits_meta_prefetchSrc),
+    .io_msInfo_10_bits_meta_accessed
+      (_mshrCtl_io_msInfo_10_bits_meta_accessed),
+    .io_msInfo_10_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_10_bits_meta_tagErr),
+    .io_msInfo_10_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_10_bits_meta_dataErr),
+    .io_msInfo_10_bits_metaTag
+      (_mshrCtl_io_msInfo_10_bits_metaTag),
+    .io_msInfo_10_bits_dirHit
+      (_mshrCtl_io_msInfo_10_bits_dirHit),
+    .io_msInfo_10_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_10_bits_isAcqOrPrefetch),
+    .io_msInfo_10_bits_isPrefetch
+      (_mshrCtl_io_msInfo_10_bits_isPrefetch),
+    .io_msInfo_10_bits_param
+      (_mshrCtl_io_msInfo_10_bits_param),
+    .io_msInfo_10_bits_mergeA
+      (_mshrCtl_io_msInfo_10_bits_mergeA),
+    .io_msInfo_10_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_10_bits_w_grantfirst),
+    .io_msInfo_10_bits_w_grantlast
+      (_mshrCtl_io_msInfo_10_bits_w_grantlast),
+    .io_msInfo_10_bits_w_grant
+      (_mshrCtl_io_msInfo_10_bits_w_grant),
+    .io_msInfo_10_bits_s_release
+      (_mshrCtl_io_msInfo_10_bits_s_release),
+    .io_msInfo_10_bits_s_refill
+      (_mshrCtl_io_msInfo_10_bits_s_refill),
+    .io_msInfo_10_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_10_bits_s_cmoresp),
+    .io_msInfo_10_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_10_bits_s_cmometaw),
+    .io_msInfo_10_bits_w_releaseack
+      (_mshrCtl_io_msInfo_10_bits_w_releaseack),
+    .io_msInfo_10_bits_w_replResp
+      (_mshrCtl_io_msInfo_10_bits_w_replResp),
+    .io_msInfo_10_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_10_bits_w_rprobeacklast),
+    .io_msInfo_10_bits_replaceData
+      (_mshrCtl_io_msInfo_10_bits_replaceData),
+    .io_msInfo_10_bits_releaseToClean
+      (_mshrCtl_io_msInfo_10_bits_releaseToClean),
+    .io_msInfo_11_valid                                   (_mshrCtl_io_msInfo_11_valid),
+    .io_msInfo_11_bits_channel
+      (_mshrCtl_io_msInfo_11_bits_channel),
+    .io_msInfo_11_bits_set
+      (_mshrCtl_io_msInfo_11_bits_set),
+    .io_msInfo_11_bits_way
+      (_mshrCtl_io_msInfo_11_bits_way),
+    .io_msInfo_11_bits_reqTag
+      (_mshrCtl_io_msInfo_11_bits_reqTag),
+    .io_msInfo_11_bits_reqSource
+      (_mshrCtl_io_msInfo_11_bits_reqSource),
+    .io_msInfo_11_bits_willFree
+      (_mshrCtl_io_msInfo_11_bits_willFree),
+    .io_msInfo_11_bits_aliasTask
+      (_mshrCtl_io_msInfo_11_bits_aliasTask),
+    .io_msInfo_11_bits_needRelease
+      (_mshrCtl_io_msInfo_11_bits_needRelease),
+    .io_msInfo_11_bits_blockRefill
+      (_mshrCtl_io_msInfo_11_bits_blockRefill),
+    .io_msInfo_11_bits_meta_dirty
+      (_mshrCtl_io_msInfo_11_bits_meta_dirty),
+    .io_msInfo_11_bits_meta_state
+      (_mshrCtl_io_msInfo_11_bits_meta_state),
+    .io_msInfo_11_bits_meta_clients
+      (_mshrCtl_io_msInfo_11_bits_meta_clients),
+    .io_msInfo_11_bits_meta_alias
+      (_mshrCtl_io_msInfo_11_bits_meta_alias),
+    .io_msInfo_11_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_11_bits_meta_prefetch),
+    .io_msInfo_11_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_11_bits_meta_prefetchSrc),
+    .io_msInfo_11_bits_meta_accessed
+      (_mshrCtl_io_msInfo_11_bits_meta_accessed),
+    .io_msInfo_11_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_11_bits_meta_tagErr),
+    .io_msInfo_11_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_11_bits_meta_dataErr),
+    .io_msInfo_11_bits_metaTag
+      (_mshrCtl_io_msInfo_11_bits_metaTag),
+    .io_msInfo_11_bits_dirHit
+      (_mshrCtl_io_msInfo_11_bits_dirHit),
+    .io_msInfo_11_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_11_bits_isAcqOrPrefetch),
+    .io_msInfo_11_bits_isPrefetch
+      (_mshrCtl_io_msInfo_11_bits_isPrefetch),
+    .io_msInfo_11_bits_param
+      (_mshrCtl_io_msInfo_11_bits_param),
+    .io_msInfo_11_bits_mergeA
+      (_mshrCtl_io_msInfo_11_bits_mergeA),
+    .io_msInfo_11_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_11_bits_w_grantfirst),
+    .io_msInfo_11_bits_w_grantlast
+      (_mshrCtl_io_msInfo_11_bits_w_grantlast),
+    .io_msInfo_11_bits_w_grant
+      (_mshrCtl_io_msInfo_11_bits_w_grant),
+    .io_msInfo_11_bits_s_release
+      (_mshrCtl_io_msInfo_11_bits_s_release),
+    .io_msInfo_11_bits_s_refill
+      (_mshrCtl_io_msInfo_11_bits_s_refill),
+    .io_msInfo_11_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_11_bits_s_cmoresp),
+    .io_msInfo_11_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_11_bits_s_cmometaw),
+    .io_msInfo_11_bits_w_releaseack
+      (_mshrCtl_io_msInfo_11_bits_w_releaseack),
+    .io_msInfo_11_bits_w_replResp
+      (_mshrCtl_io_msInfo_11_bits_w_replResp),
+    .io_msInfo_11_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_11_bits_w_rprobeacklast),
+    .io_msInfo_11_bits_replaceData
+      (_mshrCtl_io_msInfo_11_bits_replaceData),
+    .io_msInfo_11_bits_releaseToClean
+      (_mshrCtl_io_msInfo_11_bits_releaseToClean),
+    .io_msInfo_12_valid                                   (_mshrCtl_io_msInfo_12_valid),
+    .io_msInfo_12_bits_channel
+      (_mshrCtl_io_msInfo_12_bits_channel),
+    .io_msInfo_12_bits_set
+      (_mshrCtl_io_msInfo_12_bits_set),
+    .io_msInfo_12_bits_way
+      (_mshrCtl_io_msInfo_12_bits_way),
+    .io_msInfo_12_bits_reqTag
+      (_mshrCtl_io_msInfo_12_bits_reqTag),
+    .io_msInfo_12_bits_reqSource
+      (_mshrCtl_io_msInfo_12_bits_reqSource),
+    .io_msInfo_12_bits_willFree
+      (_mshrCtl_io_msInfo_12_bits_willFree),
+    .io_msInfo_12_bits_aliasTask
+      (_mshrCtl_io_msInfo_12_bits_aliasTask),
+    .io_msInfo_12_bits_needRelease
+      (_mshrCtl_io_msInfo_12_bits_needRelease),
+    .io_msInfo_12_bits_blockRefill
+      (_mshrCtl_io_msInfo_12_bits_blockRefill),
+    .io_msInfo_12_bits_meta_dirty
+      (_mshrCtl_io_msInfo_12_bits_meta_dirty),
+    .io_msInfo_12_bits_meta_state
+      (_mshrCtl_io_msInfo_12_bits_meta_state),
+    .io_msInfo_12_bits_meta_clients
+      (_mshrCtl_io_msInfo_12_bits_meta_clients),
+    .io_msInfo_12_bits_meta_alias
+      (_mshrCtl_io_msInfo_12_bits_meta_alias),
+    .io_msInfo_12_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_12_bits_meta_prefetch),
+    .io_msInfo_12_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_12_bits_meta_prefetchSrc),
+    .io_msInfo_12_bits_meta_accessed
+      (_mshrCtl_io_msInfo_12_bits_meta_accessed),
+    .io_msInfo_12_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_12_bits_meta_tagErr),
+    .io_msInfo_12_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_12_bits_meta_dataErr),
+    .io_msInfo_12_bits_metaTag
+      (_mshrCtl_io_msInfo_12_bits_metaTag),
+    .io_msInfo_12_bits_dirHit
+      (_mshrCtl_io_msInfo_12_bits_dirHit),
+    .io_msInfo_12_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_12_bits_isAcqOrPrefetch),
+    .io_msInfo_12_bits_isPrefetch
+      (_mshrCtl_io_msInfo_12_bits_isPrefetch),
+    .io_msInfo_12_bits_param
+      (_mshrCtl_io_msInfo_12_bits_param),
+    .io_msInfo_12_bits_mergeA
+      (_mshrCtl_io_msInfo_12_bits_mergeA),
+    .io_msInfo_12_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_12_bits_w_grantfirst),
+    .io_msInfo_12_bits_w_grantlast
+      (_mshrCtl_io_msInfo_12_bits_w_grantlast),
+    .io_msInfo_12_bits_w_grant
+      (_mshrCtl_io_msInfo_12_bits_w_grant),
+    .io_msInfo_12_bits_s_release
+      (_mshrCtl_io_msInfo_12_bits_s_release),
+    .io_msInfo_12_bits_s_refill
+      (_mshrCtl_io_msInfo_12_bits_s_refill),
+    .io_msInfo_12_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_12_bits_s_cmoresp),
+    .io_msInfo_12_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_12_bits_s_cmometaw),
+    .io_msInfo_12_bits_w_releaseack
+      (_mshrCtl_io_msInfo_12_bits_w_releaseack),
+    .io_msInfo_12_bits_w_replResp
+      (_mshrCtl_io_msInfo_12_bits_w_replResp),
+    .io_msInfo_12_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_12_bits_w_rprobeacklast),
+    .io_msInfo_12_bits_replaceData
+      (_mshrCtl_io_msInfo_12_bits_replaceData),
+    .io_msInfo_12_bits_releaseToClean
+      (_mshrCtl_io_msInfo_12_bits_releaseToClean),
+    .io_msInfo_13_valid                                   (_mshrCtl_io_msInfo_13_valid),
+    .io_msInfo_13_bits_channel
+      (_mshrCtl_io_msInfo_13_bits_channel),
+    .io_msInfo_13_bits_set
+      (_mshrCtl_io_msInfo_13_bits_set),
+    .io_msInfo_13_bits_way
+      (_mshrCtl_io_msInfo_13_bits_way),
+    .io_msInfo_13_bits_reqTag
+      (_mshrCtl_io_msInfo_13_bits_reqTag),
+    .io_msInfo_13_bits_reqSource
+      (_mshrCtl_io_msInfo_13_bits_reqSource),
+    .io_msInfo_13_bits_willFree
+      (_mshrCtl_io_msInfo_13_bits_willFree),
+    .io_msInfo_13_bits_aliasTask
+      (_mshrCtl_io_msInfo_13_bits_aliasTask),
+    .io_msInfo_13_bits_needRelease
+      (_mshrCtl_io_msInfo_13_bits_needRelease),
+    .io_msInfo_13_bits_blockRefill
+      (_mshrCtl_io_msInfo_13_bits_blockRefill),
+    .io_msInfo_13_bits_meta_dirty
+      (_mshrCtl_io_msInfo_13_bits_meta_dirty),
+    .io_msInfo_13_bits_meta_state
+      (_mshrCtl_io_msInfo_13_bits_meta_state),
+    .io_msInfo_13_bits_meta_clients
+      (_mshrCtl_io_msInfo_13_bits_meta_clients),
+    .io_msInfo_13_bits_meta_alias
+      (_mshrCtl_io_msInfo_13_bits_meta_alias),
+    .io_msInfo_13_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_13_bits_meta_prefetch),
+    .io_msInfo_13_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_13_bits_meta_prefetchSrc),
+    .io_msInfo_13_bits_meta_accessed
+      (_mshrCtl_io_msInfo_13_bits_meta_accessed),
+    .io_msInfo_13_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_13_bits_meta_tagErr),
+    .io_msInfo_13_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_13_bits_meta_dataErr),
+    .io_msInfo_13_bits_metaTag
+      (_mshrCtl_io_msInfo_13_bits_metaTag),
+    .io_msInfo_13_bits_dirHit
+      (_mshrCtl_io_msInfo_13_bits_dirHit),
+    .io_msInfo_13_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_13_bits_isAcqOrPrefetch),
+    .io_msInfo_13_bits_isPrefetch
+      (_mshrCtl_io_msInfo_13_bits_isPrefetch),
+    .io_msInfo_13_bits_param
+      (_mshrCtl_io_msInfo_13_bits_param),
+    .io_msInfo_13_bits_mergeA
+      (_mshrCtl_io_msInfo_13_bits_mergeA),
+    .io_msInfo_13_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_13_bits_w_grantfirst),
+    .io_msInfo_13_bits_w_grantlast
+      (_mshrCtl_io_msInfo_13_bits_w_grantlast),
+    .io_msInfo_13_bits_w_grant
+      (_mshrCtl_io_msInfo_13_bits_w_grant),
+    .io_msInfo_13_bits_s_release
+      (_mshrCtl_io_msInfo_13_bits_s_release),
+    .io_msInfo_13_bits_s_refill
+      (_mshrCtl_io_msInfo_13_bits_s_refill),
+    .io_msInfo_13_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_13_bits_s_cmoresp),
+    .io_msInfo_13_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_13_bits_s_cmometaw),
+    .io_msInfo_13_bits_w_releaseack
+      (_mshrCtl_io_msInfo_13_bits_w_releaseack),
+    .io_msInfo_13_bits_w_replResp
+      (_mshrCtl_io_msInfo_13_bits_w_replResp),
+    .io_msInfo_13_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_13_bits_w_rprobeacklast),
+    .io_msInfo_13_bits_replaceData
+      (_mshrCtl_io_msInfo_13_bits_replaceData),
+    .io_msInfo_13_bits_releaseToClean
+      (_mshrCtl_io_msInfo_13_bits_releaseToClean),
+    .io_msInfo_14_valid                                   (_mshrCtl_io_msInfo_14_valid),
+    .io_msInfo_14_bits_channel
+      (_mshrCtl_io_msInfo_14_bits_channel),
+    .io_msInfo_14_bits_set
+      (_mshrCtl_io_msInfo_14_bits_set),
+    .io_msInfo_14_bits_way
+      (_mshrCtl_io_msInfo_14_bits_way),
+    .io_msInfo_14_bits_reqTag
+      (_mshrCtl_io_msInfo_14_bits_reqTag),
+    .io_msInfo_14_bits_reqSource
+      (_mshrCtl_io_msInfo_14_bits_reqSource),
+    .io_msInfo_14_bits_willFree
+      (_mshrCtl_io_msInfo_14_bits_willFree),
+    .io_msInfo_14_bits_aliasTask
+      (_mshrCtl_io_msInfo_14_bits_aliasTask),
+    .io_msInfo_14_bits_needRelease
+      (_mshrCtl_io_msInfo_14_bits_needRelease),
+    .io_msInfo_14_bits_blockRefill
+      (_mshrCtl_io_msInfo_14_bits_blockRefill),
+    .io_msInfo_14_bits_meta_dirty
+      (_mshrCtl_io_msInfo_14_bits_meta_dirty),
+    .io_msInfo_14_bits_meta_state
+      (_mshrCtl_io_msInfo_14_bits_meta_state),
+    .io_msInfo_14_bits_meta_clients
+      (_mshrCtl_io_msInfo_14_bits_meta_clients),
+    .io_msInfo_14_bits_meta_alias
+      (_mshrCtl_io_msInfo_14_bits_meta_alias),
+    .io_msInfo_14_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_14_bits_meta_prefetch),
+    .io_msInfo_14_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_14_bits_meta_prefetchSrc),
+    .io_msInfo_14_bits_meta_accessed
+      (_mshrCtl_io_msInfo_14_bits_meta_accessed),
+    .io_msInfo_14_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_14_bits_meta_tagErr),
+    .io_msInfo_14_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_14_bits_meta_dataErr),
+    .io_msInfo_14_bits_metaTag
+      (_mshrCtl_io_msInfo_14_bits_metaTag),
+    .io_msInfo_14_bits_dirHit
+      (_mshrCtl_io_msInfo_14_bits_dirHit),
+    .io_msInfo_14_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_14_bits_isAcqOrPrefetch),
+    .io_msInfo_14_bits_isPrefetch
+      (_mshrCtl_io_msInfo_14_bits_isPrefetch),
+    .io_msInfo_14_bits_param
+      (_mshrCtl_io_msInfo_14_bits_param),
+    .io_msInfo_14_bits_mergeA
+      (_mshrCtl_io_msInfo_14_bits_mergeA),
+    .io_msInfo_14_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_14_bits_w_grantfirst),
+    .io_msInfo_14_bits_w_grantlast
+      (_mshrCtl_io_msInfo_14_bits_w_grantlast),
+    .io_msInfo_14_bits_w_grant
+      (_mshrCtl_io_msInfo_14_bits_w_grant),
+    .io_msInfo_14_bits_s_release
+      (_mshrCtl_io_msInfo_14_bits_s_release),
+    .io_msInfo_14_bits_s_refill
+      (_mshrCtl_io_msInfo_14_bits_s_refill),
+    .io_msInfo_14_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_14_bits_s_cmoresp),
+    .io_msInfo_14_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_14_bits_s_cmometaw),
+    .io_msInfo_14_bits_w_releaseack
+      (_mshrCtl_io_msInfo_14_bits_w_releaseack),
+    .io_msInfo_14_bits_w_replResp
+      (_mshrCtl_io_msInfo_14_bits_w_replResp),
+    .io_msInfo_14_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_14_bits_w_rprobeacklast),
+    .io_msInfo_14_bits_replaceData
+      (_mshrCtl_io_msInfo_14_bits_replaceData),
+    .io_msInfo_14_bits_releaseToClean
+      (_mshrCtl_io_msInfo_14_bits_releaseToClean),
+    .io_msInfo_15_valid                                   (_mshrCtl_io_msInfo_15_valid),
+    .io_msInfo_15_bits_channel
+      (_mshrCtl_io_msInfo_15_bits_channel),
+    .io_msInfo_15_bits_set
+      (_mshrCtl_io_msInfo_15_bits_set),
+    .io_msInfo_15_bits_way
+      (_mshrCtl_io_msInfo_15_bits_way),
+    .io_msInfo_15_bits_reqTag
+      (_mshrCtl_io_msInfo_15_bits_reqTag),
+    .io_msInfo_15_bits_reqSource
+      (_mshrCtl_io_msInfo_15_bits_reqSource),
+    .io_msInfo_15_bits_willFree
+      (_mshrCtl_io_msInfo_15_bits_willFree),
+    .io_msInfo_15_bits_aliasTask
+      (_mshrCtl_io_msInfo_15_bits_aliasTask),
+    .io_msInfo_15_bits_needRelease
+      (_mshrCtl_io_msInfo_15_bits_needRelease),
+    .io_msInfo_15_bits_blockRefill
+      (_mshrCtl_io_msInfo_15_bits_blockRefill),
+    .io_msInfo_15_bits_meta_dirty
+      (_mshrCtl_io_msInfo_15_bits_meta_dirty),
+    .io_msInfo_15_bits_meta_state
+      (_mshrCtl_io_msInfo_15_bits_meta_state),
+    .io_msInfo_15_bits_meta_clients
+      (_mshrCtl_io_msInfo_15_bits_meta_clients),
+    .io_msInfo_15_bits_meta_alias
+      (_mshrCtl_io_msInfo_15_bits_meta_alias),
+    .io_msInfo_15_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_15_bits_meta_prefetch),
+    .io_msInfo_15_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_15_bits_meta_prefetchSrc),
+    .io_msInfo_15_bits_meta_accessed
+      (_mshrCtl_io_msInfo_15_bits_meta_accessed),
+    .io_msInfo_15_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_15_bits_meta_tagErr),
+    .io_msInfo_15_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_15_bits_meta_dataErr),
+    .io_msInfo_15_bits_metaTag
+      (_mshrCtl_io_msInfo_15_bits_metaTag),
+    .io_msInfo_15_bits_dirHit
+      (_mshrCtl_io_msInfo_15_bits_dirHit),
+    .io_msInfo_15_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_15_bits_isAcqOrPrefetch),
+    .io_msInfo_15_bits_isPrefetch
+      (_mshrCtl_io_msInfo_15_bits_isPrefetch),
+    .io_msInfo_15_bits_param
+      (_mshrCtl_io_msInfo_15_bits_param),
+    .io_msInfo_15_bits_mergeA
+      (_mshrCtl_io_msInfo_15_bits_mergeA),
+    .io_msInfo_15_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_15_bits_w_grantfirst),
+    .io_msInfo_15_bits_w_grantlast
+      (_mshrCtl_io_msInfo_15_bits_w_grantlast),
+    .io_msInfo_15_bits_w_grant
+      (_mshrCtl_io_msInfo_15_bits_w_grant),
+    .io_msInfo_15_bits_s_release
+      (_mshrCtl_io_msInfo_15_bits_s_release),
+    .io_msInfo_15_bits_s_refill
+      (_mshrCtl_io_msInfo_15_bits_s_refill),
+    .io_msInfo_15_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_15_bits_s_cmoresp),
+    .io_msInfo_15_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_15_bits_s_cmometaw),
+    .io_msInfo_15_bits_w_releaseack
+      (_mshrCtl_io_msInfo_15_bits_w_releaseack),
+    .io_msInfo_15_bits_w_replResp
+      (_mshrCtl_io_msInfo_15_bits_w_replResp),
+    .io_msInfo_15_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_15_bits_w_rprobeacklast),
+    .io_msInfo_15_bits_replaceData
+      (_mshrCtl_io_msInfo_15_bits_replaceData),
+    .io_msInfo_15_bits_releaseToClean
+      (_mshrCtl_io_msInfo_15_bits_releaseToClean)
+  );
+  MainPipe_1 mainPipe (
+    .clock                                                              (clock),
+    .reset                                                              (reset),
+    .io_taskFromArb_s2_valid
+      (_reqArb_io_taskToPipe_s2_valid),
+    .io_taskFromArb_s2_bits_channel
+      (_reqArb_io_taskToPipe_s2_bits_channel),
+    .io_taskFromArb_s2_bits_txChannel
+      (_reqArb_io_taskToPipe_s2_bits_txChannel),
+    .io_taskFromArb_s2_bits_set
+      (_reqArb_io_taskToPipe_s2_bits_set),
+    .io_taskFromArb_s2_bits_tag
+      (_reqArb_io_taskToPipe_s2_bits_tag),
+    .io_taskFromArb_s2_bits_off
+      (_reqArb_io_taskToPipe_s2_bits_off),
+    .io_taskFromArb_s2_bits_alias
+      (_reqArb_io_taskToPipe_s2_bits_alias),
+    .io_taskFromArb_s2_bits_vaddr
+      (_reqArb_io_taskToPipe_s2_bits_vaddr),
+    .io_taskFromArb_s2_bits_isKeyword
+      (_reqArb_io_taskToPipe_s2_bits_isKeyword),
+    .io_taskFromArb_s2_bits_opcode
+      (_reqArb_io_taskToPipe_s2_bits_opcode),
+    .io_taskFromArb_s2_bits_param
+      (_reqArb_io_taskToPipe_s2_bits_param),
+    .io_taskFromArb_s2_bits_size
+      (_reqArb_io_taskToPipe_s2_bits_size),
+    .io_taskFromArb_s2_bits_sourceId
+      (_reqArb_io_taskToPipe_s2_bits_sourceId),
+    .io_taskFromArb_s2_bits_bufIdx
+      (_reqArb_io_taskToPipe_s2_bits_bufIdx),
+    .io_taskFromArb_s2_bits_needProbeAckData
+      (_reqArb_io_taskToPipe_s2_bits_needProbeAckData),
+    .io_taskFromArb_s2_bits_denied
+      (_reqArb_io_taskToPipe_s2_bits_denied),
+    .io_taskFromArb_s2_bits_corrupt
+      (_reqArb_io_taskToPipe_s2_bits_corrupt),
+    .io_taskFromArb_s2_bits_mshrTask
+      (_reqArb_io_taskToPipe_s2_bits_mshrTask),
+    .io_taskFromArb_s2_bits_mshrId
+      (_reqArb_io_taskToPipe_s2_bits_mshrId),
+    .io_taskFromArb_s2_bits_aliasTask
+      (_reqArb_io_taskToPipe_s2_bits_aliasTask),
+    .io_taskFromArb_s2_bits_useProbeData
+      (_reqArb_io_taskToPipe_s2_bits_useProbeData),
+    .io_taskFromArb_s2_bits_mshrRetry
+      (_reqArb_io_taskToPipe_s2_bits_mshrRetry),
+    .io_taskFromArb_s2_bits_readProbeDataDown
+      (_reqArb_io_taskToPipe_s2_bits_readProbeDataDown),
+    .io_taskFromArb_s2_bits_fromL2pft
+      (_reqArb_io_taskToPipe_s2_bits_fromL2pft),
+    .io_taskFromArb_s2_bits_needHint
+      (_reqArb_io_taskToPipe_s2_bits_needHint),
+    .io_taskFromArb_s2_bits_dirty
+      (_reqArb_io_taskToPipe_s2_bits_dirty),
+    .io_taskFromArb_s2_bits_way
+      (_reqArb_io_taskToPipe_s2_bits_way),
+    .io_taskFromArb_s2_bits_meta_dirty
+      (_reqArb_io_taskToPipe_s2_bits_meta_dirty),
+    .io_taskFromArb_s2_bits_meta_state
+      (_reqArb_io_taskToPipe_s2_bits_meta_state),
+    .io_taskFromArb_s2_bits_meta_clients
+      (_reqArb_io_taskToPipe_s2_bits_meta_clients),
+    .io_taskFromArb_s2_bits_meta_alias
+      (_reqArb_io_taskToPipe_s2_bits_meta_alias),
+    .io_taskFromArb_s2_bits_meta_prefetch
+      (_reqArb_io_taskToPipe_s2_bits_meta_prefetch),
+    .io_taskFromArb_s2_bits_meta_prefetchSrc
+      (_reqArb_io_taskToPipe_s2_bits_meta_prefetchSrc),
+    .io_taskFromArb_s2_bits_meta_accessed
+      (_reqArb_io_taskToPipe_s2_bits_meta_accessed),
+    .io_taskFromArb_s2_bits_meta_tagErr
+      (_reqArb_io_taskToPipe_s2_bits_meta_tagErr),
+    .io_taskFromArb_s2_bits_meta_dataErr
+      (_reqArb_io_taskToPipe_s2_bits_meta_dataErr),
+    .io_taskFromArb_s2_bits_metaWen
+      (_reqArb_io_taskToPipe_s2_bits_metaWen),
+    .io_taskFromArb_s2_bits_tagWen
+      (_reqArb_io_taskToPipe_s2_bits_tagWen),
+    .io_taskFromArb_s2_bits_dsWen
+      (_reqArb_io_taskToPipe_s2_bits_dsWen),
+    .io_taskFromArb_s2_bits_wayMask
+      (_reqArb_io_taskToPipe_s2_bits_wayMask),
+    .io_taskFromArb_s2_bits_replTask
+      (_reqArb_io_taskToPipe_s2_bits_replTask),
+    .io_taskFromArb_s2_bits_cmoTask
+      (_reqArb_io_taskToPipe_s2_bits_cmoTask),
+    .io_taskFromArb_s2_bits_cmoAll
+      (_reqArb_io_taskToPipe_s2_bits_cmoAll),
+    .io_taskFromArb_s2_bits_reqSource
+      (_reqArb_io_taskToPipe_s2_bits_reqSource),
+    .io_taskFromArb_s2_bits_mergeA
+      (_reqArb_io_taskToPipe_s2_bits_mergeA),
+    .io_taskFromArb_s2_bits_aMergeTask_off
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_off),
+    .io_taskFromArb_s2_bits_aMergeTask_alias
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_alias),
+    .io_taskFromArb_s2_bits_aMergeTask_vaddr
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_vaddr),
+    .io_taskFromArb_s2_bits_aMergeTask_isKeyword
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_isKeyword),
+    .io_taskFromArb_s2_bits_aMergeTask_opcode
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_opcode),
+    .io_taskFromArb_s2_bits_aMergeTask_param
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_param),
+    .io_taskFromArb_s2_bits_aMergeTask_sourceId
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_sourceId),
+    .io_taskFromArb_s2_bits_aMergeTask_meta_dirty
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_dirty),
+    .io_taskFromArb_s2_bits_aMergeTask_meta_state
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_state),
+    .io_taskFromArb_s2_bits_aMergeTask_meta_clients
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_clients),
+    .io_taskFromArb_s2_bits_aMergeTask_meta_alias
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_alias),
+    .io_taskFromArb_s2_bits_aMergeTask_meta_prefetch
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_prefetch),
+    .io_taskFromArb_s2_bits_aMergeTask_meta_prefetchSrc
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_prefetchSrc),
+    .io_taskFromArb_s2_bits_aMergeTask_meta_accessed
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_accessed),
+    .io_taskFromArb_s2_bits_aMergeTask_meta_tagErr
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_tagErr),
+    .io_taskFromArb_s2_bits_aMergeTask_meta_dataErr
+      (_reqArb_io_taskToPipe_s2_bits_aMergeTask_meta_dataErr),
+    .io_taskFromArb_s2_bits_snpHitRelease
+      (_reqArb_io_taskToPipe_s2_bits_snpHitRelease),
+    .io_taskFromArb_s2_bits_snpHitReleaseToInval
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseToInval),
+    .io_taskFromArb_s2_bits_snpHitReleaseToClean
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseToClean),
+    .io_taskFromArb_s2_bits_snpHitReleaseWithData
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseWithData),
+    .io_taskFromArb_s2_bits_snpHitReleaseIdx
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseIdx),
+    .io_taskFromArb_s2_bits_snpHitReleaseMeta_dirty
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_dirty),
+    .io_taskFromArb_s2_bits_snpHitReleaseMeta_state
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_state),
+    .io_taskFromArb_s2_bits_snpHitReleaseMeta_clients
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_clients),
+    .io_taskFromArb_s2_bits_snpHitReleaseMeta_alias
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_alias),
+    .io_taskFromArb_s2_bits_snpHitReleaseMeta_prefetch
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetch),
+    .io_taskFromArb_s2_bits_snpHitReleaseMeta_prefetchSrc
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_taskFromArb_s2_bits_snpHitReleaseMeta_accessed
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_accessed),
+    .io_taskFromArb_s2_bits_snpHitReleaseMeta_tagErr
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_tagErr),
+    .io_taskFromArb_s2_bits_snpHitReleaseMeta_dataErr
+      (_reqArb_io_taskToPipe_s2_bits_snpHitReleaseMeta_dataErr),
+    .io_taskFromArb_s2_bits_tgtID
+      (_reqArb_io_taskToPipe_s2_bits_tgtID),
+    .io_taskFromArb_s2_bits_srcID
+      (_reqArb_io_taskToPipe_s2_bits_srcID),
+    .io_taskFromArb_s2_bits_txnID
+      (_reqArb_io_taskToPipe_s2_bits_txnID),
+    .io_taskFromArb_s2_bits_homeNID
+      (_reqArb_io_taskToPipe_s2_bits_homeNID),
+    .io_taskFromArb_s2_bits_dbID
+      (_reqArb_io_taskToPipe_s2_bits_dbID),
+    .io_taskFromArb_s2_bits_fwdNID
+      (_reqArb_io_taskToPipe_s2_bits_fwdNID),
+    .io_taskFromArb_s2_bits_fwdTxnID
+      (_reqArb_io_taskToPipe_s2_bits_fwdTxnID),
+    .io_taskFromArb_s2_bits_chiOpcode
+      (_reqArb_io_taskToPipe_s2_bits_chiOpcode),
+    .io_taskFromArb_s2_bits_resp
+      (_reqArb_io_taskToPipe_s2_bits_resp),
+    .io_taskFromArb_s2_bits_fwdState
+      (_reqArb_io_taskToPipe_s2_bits_fwdState),
+    .io_taskFromArb_s2_bits_pCrdType
+      (_reqArb_io_taskToPipe_s2_bits_pCrdType),
+    .io_taskFromArb_s2_bits_retToSrc
+      (_reqArb_io_taskToPipe_s2_bits_retToSrc),
+    .io_taskFromArb_s2_bits_likelyshared
+      (_reqArb_io_taskToPipe_s2_bits_likelyshared),
+    .io_taskFromArb_s2_bits_expCompAck
+      (_reqArb_io_taskToPipe_s2_bits_expCompAck),
+    .io_taskFromArb_s2_bits_allowRetry
+      (_reqArb_io_taskToPipe_s2_bits_allowRetry),
+    .io_taskFromArb_s2_bits_memAttr_allocate
+      (_reqArb_io_taskToPipe_s2_bits_memAttr_allocate),
+    .io_taskFromArb_s2_bits_memAttr_cacheable
+      (_reqArb_io_taskToPipe_s2_bits_memAttr_cacheable),
+    .io_taskFromArb_s2_bits_memAttr_device
+      (_reqArb_io_taskToPipe_s2_bits_memAttr_device),
+    .io_taskFromArb_s2_bits_memAttr_ewa
+      (_reqArb_io_taskToPipe_s2_bits_memAttr_ewa),
+    .io_taskFromArb_s2_bits_traceTag
+      (_reqArb_io_taskToPipe_s2_bits_traceTag),
+    .io_mshrHintQInfo_valid
+      (_reqArb_io_mshrHintQInfo_valid),
+    .io_mshrHintQInfo_bits_channel
+      (_reqArb_io_mshrHintQInfo_bits_channel),
+    .io_mshrHintQInfo_bits_isKeyword
+      (_reqArb_io_mshrHintQInfo_bits_isKeyword),
+    .io_mshrHintQInfo_bits_opcode
+      (_reqArb_io_mshrHintQInfo_bits_opcode),
+    .io_mshrHintQInfo_bits_sourceId
+      (_reqArb_io_mshrHintQInfo_bits_sourceId),
+    .io_mshrHintQInfo_bits_mergeA
+      (_reqArb_io_mshrHintQInfo_bits_mergeA),
+    .io_mshrHintQInfo_bits_aMergeTask_isKeyword
+      (_reqArb_io_mshrHintQInfo_bits_aMergeTask_isKeyword),
+    .io_mshrHintQInfo_bits_aMergeTask_opcode
+      (_reqArb_io_mshrHintQInfo_bits_aMergeTask_opcode),
+    .io_mshrHintQInfo_bits_aMergeTask_sourceId
+      (_reqArb_io_mshrHintQInfo_bits_aMergeTask_sourceId),
+    .io_sinkCHintQInfo_valid
+      (_reqArb_io_sinkCHintQInfo_valid),
+    .io_sinkCHintQInfo_bits_sourceId
+      (_reqArb_io_sinkCHintQInfo_bits_sourceId),
+    .io_fromReqArb_status_s1_tags_1
+      (_reqArb_io_status_s1_tags_1),
+    .io_fromReqArb_status_s1_sets_0
+      (_reqArb_io_status_s1_sets_0),
+    .io_fromReqArb_status_s1_sets_1
+      (_reqArb_io_status_s1_sets_1),
+    .io_fromReqArb_status_s1_sets_2
+      (_reqArb_io_status_s1_sets_2),
+    .io_fromReqArb_status_s1_sets_3
+      (_reqArb_io_status_s1_sets_3),
+    .io_toReqArb_blockG_s1
+      (_mainPipe_io_toReqArb_blockG_s1),
+    .io_toReqArb_blockB_s1
+      (_mainPipe_io_toReqArb_blockB_s1),
+    .io_toReqArb_blockC_s1
+      (_mainPipe_io_toReqArb_blockC_s1),
+    .io_toReqBuf_0
+      (_mainPipe_io_toReqBuf_0),
+    .io_toReqBuf_1
+      (_mainPipe_io_toReqBuf_1),
+    .io_status_vec_toD_0_valid
+      (_mainPipe_io_status_vec_toD_0_valid),
+    .io_status_vec_toD_0_bits_channel
+      (_mainPipe_io_status_vec_toD_0_bits_channel),
+    .io_status_vec_toD_1_valid
+      (_mainPipe_io_status_vec_toD_1_valid),
+    .io_status_vec_toD_1_bits_channel
+      (_mainPipe_io_status_vec_toD_1_bits_channel),
+    .io_status_vec_toD_2_valid
+      (_mainPipe_io_status_vec_toD_2_valid),
+    .io_status_vec_toD_2_bits_channel
+      (_mainPipe_io_status_vec_toD_2_bits_channel),
+    .io_status_vec_toTX_0_valid
+      (_mainPipe_io_status_vec_toTX_0_valid),
+    .io_status_vec_toTX_0_bits_channel
+      (_mainPipe_io_status_vec_toTX_0_bits_channel),
+    .io_status_vec_toTX_0_bits_txChannel
+      (_mainPipe_io_status_vec_toTX_0_bits_txChannel),
+    .io_status_vec_toTX_0_bits_mshrTask
+      (_mainPipe_io_status_vec_toTX_0_bits_mshrTask),
+    .io_status_vec_toTX_1_valid
+      (_mainPipe_io_status_vec_toTX_1_valid),
+    .io_status_vec_toTX_1_bits_channel
+      (_mainPipe_io_status_vec_toTX_1_bits_channel),
+    .io_status_vec_toTX_1_bits_txChannel
+      (_mainPipe_io_status_vec_toTX_1_bits_txChannel),
+    .io_status_vec_toTX_1_bits_mshrTask
+      (_mainPipe_io_status_vec_toTX_1_bits_mshrTask),
+    .io_status_vec_toTX_2_valid
+      (_mainPipe_io_status_vec_toTX_2_valid),
+    .io_status_vec_toTX_2_bits_channel
+      (_mainPipe_io_status_vec_toTX_2_bits_channel),
+    .io_status_vec_toTX_2_bits_txChannel
+      (_mainPipe_io_status_vec_toTX_2_bits_txChannel),
+    .io_status_vec_toTX_2_bits_mshrTask
+      (_mainPipe_io_status_vec_toTX_2_bits_mshrTask),
+    .io_dirResp_s3_hit
+      (_directory_io_resp_bits_hit),
+    .io_dirResp_s3_tag
+      (_directory_io_resp_bits_tag),
+    .io_dirResp_s3_set
+      (_directory_io_resp_bits_set),
+    .io_dirResp_s3_way
+      (_directory_io_resp_bits_way),
+    .io_dirResp_s3_meta_tagErr
+      (_directory_io_resp_bits_meta_tagErr),
+    .io_dirResp_s3_meta_dataErr
+      (_directory_io_resp_bits_meta_dataErr),
+    .io_dirResp_s3_error
+      (_directory_io_resp_bits_error),
+    .io_metaOnHit_s3_dirty
+      (_directory_io_metaOnHit_dirty),
+    .io_metaOnHit_s3_state
+      (_directory_io_metaOnHit_state),
+    .io_metaOnHit_s3_clients
+      (_directory_io_metaOnHit_clients),
+    .io_metaOnHit_s3_alias
+      (_directory_io_metaOnHit_alias),
+    .io_metaOnHit_s3_prefetch
+      (_directory_io_metaOnHit_prefetch),
+    .io_metaOnHit_s3_prefetchSrc
+      (_directory_io_metaOnHit_prefetchSrc),
+    .io_metaOnHit_s3_accessed
+      (_directory_io_metaOnHit_accessed),
+    .io_metaOnHit_s3_tagErr
+      (_directory_io_metaOnHit_tagErr),
+    .io_metaOnHit_s3_dataErr
+      (_directory_io_metaOnHit_dataErr),
+    .io_errOnSnp_s3
+      (_directory_io_errOnSnp),
+    .io_dirWayOH_s3
+      (_directory_io_wayOH),
+    .io_dirReplWayOH_s3
+      (_directory_io_replWayOH),
+    .io_replResp_bits_way
+      (_directory_io_replResp_bits_way),
+    .io_replResp_bits_meta_state
+      (_directory_io_replResp_bits_meta_state),
+    .io_replResp_bits_retry
+      (_directory_io_replResp_bits_retry),
+    .io_replResp_bits_validHold
+      (_directory_io_replResp_bits_validHold),
+    .io_retryFastFwd_s2
+      (_directory_io_retryFastFwd),
+    .io_toMSHRCtl_mshr_alloc_s3_valid
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_valid),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_hit
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_hit),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_tag
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_tag),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_set
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_set),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_way
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_way),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dirty
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_state
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_clients
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_alias
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetch
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_accessed
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_tagErr
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dataErr
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_error
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_error),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_s_acquire
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_acquire),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rprobe
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_s_pprobe
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_s_release
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_release),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_s_probeack
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_probeack),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_s_refill
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_refill),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_s_cmoresp
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeackfirst
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeacklast
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeackfirst
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeacklast
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantfirst
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantlast
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grant
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grant),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_w_releaseack
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_w_replResp
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_replResp),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rcompack
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_state_s_dct
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_dct),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_channel
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_channel),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_set
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_set),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_tag
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_tag),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_off
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_off),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_alias
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_alias),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_isKeyword
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_isKeyword),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_opcode
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_opcode),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_param
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_param),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_sourceId
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_sourceId),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_aliasTask
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_aliasTask),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_fromL2pft
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_reqSource
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_reqSource),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitRelease
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToInval
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToClean
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseWithData
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseIdx
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_srcID
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_srcID),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_txnID
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_txnID),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdNID
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdNID),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdTxnID
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_chiOpcode
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_retToSrc
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_retToSrc),
+    .io_toMSHRCtl_mshr_alloc_s3_bits_task_traceTag
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_traceTag),
+    .io_fromMSHRCtl_mshr_alloc_ptr
+      (_mshrCtl_io_toMainPipe_mshr_alloc_ptr),
+    .io_bufResp_data_0
+      (_sinkC_io_bufResp_data_0),
+    .io_bufResp_data_1
+      (_sinkC_io_bufResp_data_1),
+    .io_refillBufResp_s3_bits_data
+      (_refillBuf_io_resp_data_data),
+    .io_releaseBufResp_s3_valid
+      (mainPipe_io_releaseBufResp_s3_valid_REG),
+    .io_releaseBufResp_s3_bits_data
+      (_releaseBuf_io_resp_data_data),
+    .io_toDS_en_s3
+      (_mainPipe_io_toDS_en_s3),
+    .io_toDS_req_s3_valid
+      (_mainPipe_io_toDS_req_s3_valid),
+    .io_toDS_req_s3_bits_way
+      (_mainPipe_io_toDS_req_s3_bits_way),
+    .io_toDS_req_s3_bits_set
+      (_mainPipe_io_toDS_req_s3_bits_set),
+    .io_toDS_req_s3_bits_wen
+      (_mainPipe_io_toDS_req_s3_bits_wen),
+    .io_toDS_rdata_s5_data
+      (_dataStorage_io_rdata_data),
+    .io_toDS_wdata_s3_data
+      (_mainPipe_io_toDS_wdata_s3_data),
+    .io_toDS_error_s5
+      (_dataStorage_io_error),
+    .io_toSourceD_valid
+      (_mainPipe_io_toSourceD_valid),
+    .io_toSourceD_bits_task_channel
+      (_mainPipe_io_toSourceD_bits_task_channel),
+    .io_toSourceD_bits_task_txChannel
+      (_mainPipe_io_toSourceD_bits_task_txChannel),
+    .io_toSourceD_bits_task_set
+      (_mainPipe_io_toSourceD_bits_task_set),
+    .io_toSourceD_bits_task_tag
+      (_mainPipe_io_toSourceD_bits_task_tag),
+    .io_toSourceD_bits_task_off
+      (_mainPipe_io_toSourceD_bits_task_off),
+    .io_toSourceD_bits_task_alias
+      (_mainPipe_io_toSourceD_bits_task_alias),
+    .io_toSourceD_bits_task_vaddr
+      (_mainPipe_io_toSourceD_bits_task_vaddr),
+    .io_toSourceD_bits_task_isKeyword
+      (_mainPipe_io_toSourceD_bits_task_isKeyword),
+    .io_toSourceD_bits_task_opcode
+      (_mainPipe_io_toSourceD_bits_task_opcode),
+    .io_toSourceD_bits_task_param
+      (_mainPipe_io_toSourceD_bits_task_param),
+    .io_toSourceD_bits_task_size
+      (_mainPipe_io_toSourceD_bits_task_size),
+    .io_toSourceD_bits_task_sourceId
+      (_mainPipe_io_toSourceD_bits_task_sourceId),
+    .io_toSourceD_bits_task_bufIdx
+      (_mainPipe_io_toSourceD_bits_task_bufIdx),
+    .io_toSourceD_bits_task_needProbeAckData
+      (_mainPipe_io_toSourceD_bits_task_needProbeAckData),
+    .io_toSourceD_bits_task_denied
+      (_mainPipe_io_toSourceD_bits_task_denied),
+    .io_toSourceD_bits_task_corrupt
+      (_mainPipe_io_toSourceD_bits_task_corrupt),
+    .io_toSourceD_bits_task_mshrTask
+      (_mainPipe_io_toSourceD_bits_task_mshrTask),
+    .io_toSourceD_bits_task_mshrId
+      (_mainPipe_io_toSourceD_bits_task_mshrId),
+    .io_toSourceD_bits_task_aliasTask
+      (_mainPipe_io_toSourceD_bits_task_aliasTask),
+    .io_toSourceD_bits_task_useProbeData
+      (_mainPipe_io_toSourceD_bits_task_useProbeData),
+    .io_toSourceD_bits_task_mshrRetry
+      (_mainPipe_io_toSourceD_bits_task_mshrRetry),
+    .io_toSourceD_bits_task_readProbeDataDown
+      (_mainPipe_io_toSourceD_bits_task_readProbeDataDown),
+    .io_toSourceD_bits_task_fromL2pft
+      (_mainPipe_io_toSourceD_bits_task_fromL2pft),
+    .io_toSourceD_bits_task_needHint
+      (_mainPipe_io_toSourceD_bits_task_needHint),
+    .io_toSourceD_bits_task_dirty
+      (_mainPipe_io_toSourceD_bits_task_dirty),
+    .io_toSourceD_bits_task_way
+      (_mainPipe_io_toSourceD_bits_task_way),
+    .io_toSourceD_bits_task_meta_dirty
+      (_mainPipe_io_toSourceD_bits_task_meta_dirty),
+    .io_toSourceD_bits_task_meta_state
+      (_mainPipe_io_toSourceD_bits_task_meta_state),
+    .io_toSourceD_bits_task_meta_clients
+      (_mainPipe_io_toSourceD_bits_task_meta_clients),
+    .io_toSourceD_bits_task_meta_alias
+      (_mainPipe_io_toSourceD_bits_task_meta_alias),
+    .io_toSourceD_bits_task_meta_prefetch
+      (_mainPipe_io_toSourceD_bits_task_meta_prefetch),
+    .io_toSourceD_bits_task_meta_prefetchSrc
+      (_mainPipe_io_toSourceD_bits_task_meta_prefetchSrc),
+    .io_toSourceD_bits_task_meta_accessed
+      (_mainPipe_io_toSourceD_bits_task_meta_accessed),
+    .io_toSourceD_bits_task_meta_tagErr
+      (_mainPipe_io_toSourceD_bits_task_meta_tagErr),
+    .io_toSourceD_bits_task_meta_dataErr
+      (_mainPipe_io_toSourceD_bits_task_meta_dataErr),
+    .io_toSourceD_bits_task_metaWen
+      (_mainPipe_io_toSourceD_bits_task_metaWen),
+    .io_toSourceD_bits_task_tagWen
+      (_mainPipe_io_toSourceD_bits_task_tagWen),
+    .io_toSourceD_bits_task_dsWen
+      (_mainPipe_io_toSourceD_bits_task_dsWen),
+    .io_toSourceD_bits_task_wayMask
+      (_mainPipe_io_toSourceD_bits_task_wayMask),
+    .io_toSourceD_bits_task_replTask
+      (_mainPipe_io_toSourceD_bits_task_replTask),
+    .io_toSourceD_bits_task_cmoTask
+      (_mainPipe_io_toSourceD_bits_task_cmoTask),
+    .io_toSourceD_bits_task_cmoAll
+      (_mainPipe_io_toSourceD_bits_task_cmoAll),
+    .io_toSourceD_bits_task_reqSource
+      (_mainPipe_io_toSourceD_bits_task_reqSource),
+    .io_toSourceD_bits_task_mergeA
+      (_mainPipe_io_toSourceD_bits_task_mergeA),
+    .io_toSourceD_bits_task_aMergeTask_off
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_off),
+    .io_toSourceD_bits_task_aMergeTask_alias
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_alias),
+    .io_toSourceD_bits_task_aMergeTask_vaddr
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_vaddr),
+    .io_toSourceD_bits_task_aMergeTask_isKeyword
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_isKeyword),
+    .io_toSourceD_bits_task_aMergeTask_opcode
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_opcode),
+    .io_toSourceD_bits_task_aMergeTask_param
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_param),
+    .io_toSourceD_bits_task_aMergeTask_sourceId
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_sourceId),
+    .io_toSourceD_bits_task_aMergeTask_meta_dirty
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_dirty),
+    .io_toSourceD_bits_task_aMergeTask_meta_state
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_state),
+    .io_toSourceD_bits_task_aMergeTask_meta_clients
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_clients),
+    .io_toSourceD_bits_task_aMergeTask_meta_alias
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_alias),
+    .io_toSourceD_bits_task_aMergeTask_meta_prefetch
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_prefetch),
+    .io_toSourceD_bits_task_aMergeTask_meta_prefetchSrc
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_prefetchSrc),
+    .io_toSourceD_bits_task_aMergeTask_meta_accessed
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_accessed),
+    .io_toSourceD_bits_task_aMergeTask_meta_tagErr
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_tagErr),
+    .io_toSourceD_bits_task_aMergeTask_meta_dataErr
+      (_mainPipe_io_toSourceD_bits_task_aMergeTask_meta_dataErr),
+    .io_toSourceD_bits_task_snpHitRelease
+      (_mainPipe_io_toSourceD_bits_task_snpHitRelease),
+    .io_toSourceD_bits_task_snpHitReleaseToInval
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseToInval),
+    .io_toSourceD_bits_task_snpHitReleaseToClean
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseToClean),
+    .io_toSourceD_bits_task_snpHitReleaseWithData
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseWithData),
+    .io_toSourceD_bits_task_snpHitReleaseIdx
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseIdx),
+    .io_toSourceD_bits_task_snpHitReleaseMeta_dirty
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_dirty),
+    .io_toSourceD_bits_task_snpHitReleaseMeta_state
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_state),
+    .io_toSourceD_bits_task_snpHitReleaseMeta_clients
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_clients),
+    .io_toSourceD_bits_task_snpHitReleaseMeta_alias
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_alias),
+    .io_toSourceD_bits_task_snpHitReleaseMeta_prefetch
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_prefetch),
+    .io_toSourceD_bits_task_snpHitReleaseMeta_prefetchSrc
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_toSourceD_bits_task_snpHitReleaseMeta_accessed
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_accessed),
+    .io_toSourceD_bits_task_snpHitReleaseMeta_tagErr
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_tagErr),
+    .io_toSourceD_bits_task_snpHitReleaseMeta_dataErr
+      (_mainPipe_io_toSourceD_bits_task_snpHitReleaseMeta_dataErr),
+    .io_toSourceD_bits_task_tgtID
+      (_mainPipe_io_toSourceD_bits_task_tgtID),
+    .io_toSourceD_bits_task_srcID
+      (_mainPipe_io_toSourceD_bits_task_srcID),
+    .io_toSourceD_bits_task_txnID
+      (_mainPipe_io_toSourceD_bits_task_txnID),
+    .io_toSourceD_bits_task_homeNID
+      (_mainPipe_io_toSourceD_bits_task_homeNID),
+    .io_toSourceD_bits_task_dbID
+      (_mainPipe_io_toSourceD_bits_task_dbID),
+    .io_toSourceD_bits_task_fwdNID
+      (_mainPipe_io_toSourceD_bits_task_fwdNID),
+    .io_toSourceD_bits_task_fwdTxnID
+      (_mainPipe_io_toSourceD_bits_task_fwdTxnID),
+    .io_toSourceD_bits_task_chiOpcode
+      (_mainPipe_io_toSourceD_bits_task_chiOpcode),
+    .io_toSourceD_bits_task_resp
+      (_mainPipe_io_toSourceD_bits_task_resp),
+    .io_toSourceD_bits_task_fwdState
+      (_mainPipe_io_toSourceD_bits_task_fwdState),
+    .io_toSourceD_bits_task_pCrdType
+      (_mainPipe_io_toSourceD_bits_task_pCrdType),
+    .io_toSourceD_bits_task_retToSrc
+      (_mainPipe_io_toSourceD_bits_task_retToSrc),
+    .io_toSourceD_bits_task_likelyshared
+      (_mainPipe_io_toSourceD_bits_task_likelyshared),
+    .io_toSourceD_bits_task_expCompAck
+      (_mainPipe_io_toSourceD_bits_task_expCompAck),
+    .io_toSourceD_bits_task_allowRetry
+      (_mainPipe_io_toSourceD_bits_task_allowRetry),
+    .io_toSourceD_bits_task_memAttr_allocate
+      (_mainPipe_io_toSourceD_bits_task_memAttr_allocate),
+    .io_toSourceD_bits_task_memAttr_cacheable
+      (_mainPipe_io_toSourceD_bits_task_memAttr_cacheable),
+    .io_toSourceD_bits_task_memAttr_device
+      (_mainPipe_io_toSourceD_bits_task_memAttr_device),
+    .io_toSourceD_bits_task_memAttr_ewa
+      (_mainPipe_io_toSourceD_bits_task_memAttr_ewa),
+    .io_toSourceD_bits_task_traceTag
+      (_mainPipe_io_toSourceD_bits_task_traceTag),
+    .io_toSourceD_bits_data_data
+      (_mainPipe_io_toSourceD_bits_data_data),
+    .io_toTXREQ_valid
+      (_mainPipe_io_toTXREQ_valid),
+    .io_toTXREQ_bits_tgtID
+      (_mainPipe_io_toTXREQ_bits_tgtID),
+    .io_toTXREQ_bits_srcID
+      (_mainPipe_io_toTXREQ_bits_srcID),
+    .io_toTXREQ_bits_txnID
+      (_mainPipe_io_toTXREQ_bits_txnID),
+    .io_toTXREQ_bits_opcode
+      (_mainPipe_io_toTXREQ_bits_opcode),
+    .io_toTXREQ_bits_addr
+      (_mainPipe_io_toTXREQ_bits_addr),
+    .io_toTXREQ_bits_likelyshared
+      (_mainPipe_io_toTXREQ_bits_likelyshared),
+    .io_toTXREQ_bits_allowRetry
+      (_mainPipe_io_toTXREQ_bits_allowRetry),
+    .io_toTXREQ_bits_pCrdType
+      (_mainPipe_io_toTXREQ_bits_pCrdType),
+    .io_toTXREQ_bits_memAttr_allocate
+      (_mainPipe_io_toTXREQ_bits_memAttr_allocate),
+    .io_toTXREQ_bits_memAttr_cacheable
+      (_mainPipe_io_toTXREQ_bits_memAttr_cacheable),
+    .io_toTXREQ_bits_memAttr_device
+      (_mainPipe_io_toTXREQ_bits_memAttr_device),
+    .io_toTXREQ_bits_memAttr_ewa
+      (_mainPipe_io_toTXREQ_bits_memAttr_ewa),
+    .io_toTXREQ_bits_expCompAck
+      (_mainPipe_io_toTXREQ_bits_expCompAck),
+    .io_toTXRSP_valid
+      (_mainPipe_io_toTXRSP_valid),
+    .io_toTXRSP_bits_denied
+      (_mainPipe_io_toTXRSP_bits_denied),
+    .io_toTXRSP_bits_tgtID
+      (_mainPipe_io_toTXRSP_bits_tgtID),
+    .io_toTXRSP_bits_srcID
+      (_mainPipe_io_toTXRSP_bits_srcID),
+    .io_toTXRSP_bits_txnID
+      (_mainPipe_io_toTXRSP_bits_txnID),
+    .io_toTXRSP_bits_dbID
+      (_mainPipe_io_toTXRSP_bits_dbID),
+    .io_toTXRSP_bits_chiOpcode
+      (_mainPipe_io_toTXRSP_bits_chiOpcode),
+    .io_toTXRSP_bits_resp
+      (_mainPipe_io_toTXRSP_bits_resp),
+    .io_toTXRSP_bits_fwdState
+      (_mainPipe_io_toTXRSP_bits_fwdState),
+    .io_toTXRSP_bits_pCrdType
+      (_mainPipe_io_toTXRSP_bits_pCrdType),
+    .io_toTXRSP_bits_traceTag
+      (_mainPipe_io_toTXRSP_bits_traceTag),
+    .io_toTXDAT_ready
+      (_txdat_io_in_ready),
+    .io_toTXDAT_valid
+      (_mainPipe_io_toTXDAT_valid),
+    .io_toTXDAT_bits_task_channel
+      (_mainPipe_io_toTXDAT_bits_task_channel),
+    .io_toTXDAT_bits_task_txChannel
+      (_mainPipe_io_toTXDAT_bits_task_txChannel),
+    .io_toTXDAT_bits_task_set
+      (_mainPipe_io_toTXDAT_bits_task_set),
+    .io_toTXDAT_bits_task_tag
+      (_mainPipe_io_toTXDAT_bits_task_tag),
+    .io_toTXDAT_bits_task_off
+      (_mainPipe_io_toTXDAT_bits_task_off),
+    .io_toTXDAT_bits_task_alias
+      (_mainPipe_io_toTXDAT_bits_task_alias),
+    .io_toTXDAT_bits_task_vaddr
+      (_mainPipe_io_toTXDAT_bits_task_vaddr),
+    .io_toTXDAT_bits_task_isKeyword
+      (_mainPipe_io_toTXDAT_bits_task_isKeyword),
+    .io_toTXDAT_bits_task_opcode
+      (_mainPipe_io_toTXDAT_bits_task_opcode),
+    .io_toTXDAT_bits_task_param
+      (_mainPipe_io_toTXDAT_bits_task_param),
+    .io_toTXDAT_bits_task_size
+      (_mainPipe_io_toTXDAT_bits_task_size),
+    .io_toTXDAT_bits_task_sourceId
+      (_mainPipe_io_toTXDAT_bits_task_sourceId),
+    .io_toTXDAT_bits_task_bufIdx
+      (_mainPipe_io_toTXDAT_bits_task_bufIdx),
+    .io_toTXDAT_bits_task_needProbeAckData
+      (_mainPipe_io_toTXDAT_bits_task_needProbeAckData),
+    .io_toTXDAT_bits_task_denied
+      (_mainPipe_io_toTXDAT_bits_task_denied),
+    .io_toTXDAT_bits_task_corrupt
+      (_mainPipe_io_toTXDAT_bits_task_corrupt),
+    .io_toTXDAT_bits_task_mshrTask
+      (_mainPipe_io_toTXDAT_bits_task_mshrTask),
+    .io_toTXDAT_bits_task_mshrId
+      (_mainPipe_io_toTXDAT_bits_task_mshrId),
+    .io_toTXDAT_bits_task_aliasTask
+      (_mainPipe_io_toTXDAT_bits_task_aliasTask),
+    .io_toTXDAT_bits_task_useProbeData
+      (_mainPipe_io_toTXDAT_bits_task_useProbeData),
+    .io_toTXDAT_bits_task_mshrRetry
+      (_mainPipe_io_toTXDAT_bits_task_mshrRetry),
+    .io_toTXDAT_bits_task_readProbeDataDown
+      (_mainPipe_io_toTXDAT_bits_task_readProbeDataDown),
+    .io_toTXDAT_bits_task_fromL2pft
+      (_mainPipe_io_toTXDAT_bits_task_fromL2pft),
+    .io_toTXDAT_bits_task_needHint
+      (_mainPipe_io_toTXDAT_bits_task_needHint),
+    .io_toTXDAT_bits_task_dirty
+      (_mainPipe_io_toTXDAT_bits_task_dirty),
+    .io_toTXDAT_bits_task_way
+      (_mainPipe_io_toTXDAT_bits_task_way),
+    .io_toTXDAT_bits_task_meta_dirty
+      (_mainPipe_io_toTXDAT_bits_task_meta_dirty),
+    .io_toTXDAT_bits_task_meta_state
+      (_mainPipe_io_toTXDAT_bits_task_meta_state),
+    .io_toTXDAT_bits_task_meta_clients
+      (_mainPipe_io_toTXDAT_bits_task_meta_clients),
+    .io_toTXDAT_bits_task_meta_alias
+      (_mainPipe_io_toTXDAT_bits_task_meta_alias),
+    .io_toTXDAT_bits_task_meta_prefetch
+      (_mainPipe_io_toTXDAT_bits_task_meta_prefetch),
+    .io_toTXDAT_bits_task_meta_prefetchSrc
+      (_mainPipe_io_toTXDAT_bits_task_meta_prefetchSrc),
+    .io_toTXDAT_bits_task_meta_accessed
+      (_mainPipe_io_toTXDAT_bits_task_meta_accessed),
+    .io_toTXDAT_bits_task_meta_tagErr
+      (_mainPipe_io_toTXDAT_bits_task_meta_tagErr),
+    .io_toTXDAT_bits_task_meta_dataErr
+      (_mainPipe_io_toTXDAT_bits_task_meta_dataErr),
+    .io_toTXDAT_bits_task_metaWen
+      (_mainPipe_io_toTXDAT_bits_task_metaWen),
+    .io_toTXDAT_bits_task_tagWen
+      (_mainPipe_io_toTXDAT_bits_task_tagWen),
+    .io_toTXDAT_bits_task_dsWen
+      (_mainPipe_io_toTXDAT_bits_task_dsWen),
+    .io_toTXDAT_bits_task_wayMask
+      (_mainPipe_io_toTXDAT_bits_task_wayMask),
+    .io_toTXDAT_bits_task_replTask
+      (_mainPipe_io_toTXDAT_bits_task_replTask),
+    .io_toTXDAT_bits_task_cmoTask
+      (_mainPipe_io_toTXDAT_bits_task_cmoTask),
+    .io_toTXDAT_bits_task_cmoAll
+      (_mainPipe_io_toTXDAT_bits_task_cmoAll),
+    .io_toTXDAT_bits_task_reqSource
+      (_mainPipe_io_toTXDAT_bits_task_reqSource),
+    .io_toTXDAT_bits_task_mergeA
+      (_mainPipe_io_toTXDAT_bits_task_mergeA),
+    .io_toTXDAT_bits_task_aMergeTask_off
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_off),
+    .io_toTXDAT_bits_task_aMergeTask_alias
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_alias),
+    .io_toTXDAT_bits_task_aMergeTask_vaddr
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_vaddr),
+    .io_toTXDAT_bits_task_aMergeTask_isKeyword
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_isKeyword),
+    .io_toTXDAT_bits_task_aMergeTask_opcode
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_opcode),
+    .io_toTXDAT_bits_task_aMergeTask_param
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_param),
+    .io_toTXDAT_bits_task_aMergeTask_sourceId
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_sourceId),
+    .io_toTXDAT_bits_task_aMergeTask_meta_dirty
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_dirty),
+    .io_toTXDAT_bits_task_aMergeTask_meta_state
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_state),
+    .io_toTXDAT_bits_task_aMergeTask_meta_clients
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_clients),
+    .io_toTXDAT_bits_task_aMergeTask_meta_alias
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_alias),
+    .io_toTXDAT_bits_task_aMergeTask_meta_prefetch
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_prefetch),
+    .io_toTXDAT_bits_task_aMergeTask_meta_prefetchSrc
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_prefetchSrc),
+    .io_toTXDAT_bits_task_aMergeTask_meta_accessed
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_accessed),
+    .io_toTXDAT_bits_task_aMergeTask_meta_tagErr
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_tagErr),
+    .io_toTXDAT_bits_task_aMergeTask_meta_dataErr
+      (_mainPipe_io_toTXDAT_bits_task_aMergeTask_meta_dataErr),
+    .io_toTXDAT_bits_task_snpHitRelease
+      (_mainPipe_io_toTXDAT_bits_task_snpHitRelease),
+    .io_toTXDAT_bits_task_snpHitReleaseToInval
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseToInval),
+    .io_toTXDAT_bits_task_snpHitReleaseToClean
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseToClean),
+    .io_toTXDAT_bits_task_snpHitReleaseWithData
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseWithData),
+    .io_toTXDAT_bits_task_snpHitReleaseIdx
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseIdx),
+    .io_toTXDAT_bits_task_snpHitReleaseMeta_dirty
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_dirty),
+    .io_toTXDAT_bits_task_snpHitReleaseMeta_state
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_state),
+    .io_toTXDAT_bits_task_snpHitReleaseMeta_clients
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_clients),
+    .io_toTXDAT_bits_task_snpHitReleaseMeta_alias
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_alias),
+    .io_toTXDAT_bits_task_snpHitReleaseMeta_prefetch
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_prefetch),
+    .io_toTXDAT_bits_task_snpHitReleaseMeta_prefetchSrc
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_toTXDAT_bits_task_snpHitReleaseMeta_accessed
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_accessed),
+    .io_toTXDAT_bits_task_snpHitReleaseMeta_tagErr
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_tagErr),
+    .io_toTXDAT_bits_task_snpHitReleaseMeta_dataErr
+      (_mainPipe_io_toTXDAT_bits_task_snpHitReleaseMeta_dataErr),
+    .io_toTXDAT_bits_task_tgtID
+      (_mainPipe_io_toTXDAT_bits_task_tgtID),
+    .io_toTXDAT_bits_task_srcID
+      (_mainPipe_io_toTXDAT_bits_task_srcID),
+    .io_toTXDAT_bits_task_txnID
+      (_mainPipe_io_toTXDAT_bits_task_txnID),
+    .io_toTXDAT_bits_task_homeNID
+      (_mainPipe_io_toTXDAT_bits_task_homeNID),
+    .io_toTXDAT_bits_task_dbID
+      (_mainPipe_io_toTXDAT_bits_task_dbID),
+    .io_toTXDAT_bits_task_fwdNID
+      (_mainPipe_io_toTXDAT_bits_task_fwdNID),
+    .io_toTXDAT_bits_task_fwdTxnID
+      (_mainPipe_io_toTXDAT_bits_task_fwdTxnID),
+    .io_toTXDAT_bits_task_chiOpcode
+      (_mainPipe_io_toTXDAT_bits_task_chiOpcode),
+    .io_toTXDAT_bits_task_resp
+      (_mainPipe_io_toTXDAT_bits_task_resp),
+    .io_toTXDAT_bits_task_fwdState
+      (_mainPipe_io_toTXDAT_bits_task_fwdState),
+    .io_toTXDAT_bits_task_pCrdType
+      (_mainPipe_io_toTXDAT_bits_task_pCrdType),
+    .io_toTXDAT_bits_task_retToSrc
+      (_mainPipe_io_toTXDAT_bits_task_retToSrc),
+    .io_toTXDAT_bits_task_likelyshared
+      (_mainPipe_io_toTXDAT_bits_task_likelyshared),
+    .io_toTXDAT_bits_task_expCompAck
+      (_mainPipe_io_toTXDAT_bits_task_expCompAck),
+    .io_toTXDAT_bits_task_allowRetry
+      (_mainPipe_io_toTXDAT_bits_task_allowRetry),
+    .io_toTXDAT_bits_task_memAttr_allocate
+      (_mainPipe_io_toTXDAT_bits_task_memAttr_allocate),
+    .io_toTXDAT_bits_task_memAttr_cacheable
+      (_mainPipe_io_toTXDAT_bits_task_memAttr_cacheable),
+    .io_toTXDAT_bits_task_memAttr_device
+      (_mainPipe_io_toTXDAT_bits_task_memAttr_device),
+    .io_toTXDAT_bits_task_memAttr_ewa
+      (_mainPipe_io_toTXDAT_bits_task_memAttr_ewa),
+    .io_toTXDAT_bits_task_traceTag
+      (_mainPipe_io_toTXDAT_bits_task_traceTag),
+    .io_toTXDAT_bits_data_data
+      (_mainPipe_io_toTXDAT_bits_data_data),
+    .io_metaWReq_valid
+      (_mainPipe_io_metaWReq_valid),
+    .io_metaWReq_bits_set
+      (_mainPipe_io_metaWReq_bits_set),
+    .io_metaWReq_bits_wayOH
+      (_mainPipe_io_metaWReq_bits_wayOH),
+    .io_metaWReq_bits_wmeta_dirty
+      (_mainPipe_io_metaWReq_bits_wmeta_dirty),
+    .io_metaWReq_bits_wmeta_state
+      (_mainPipe_io_metaWReq_bits_wmeta_state),
+    .io_metaWReq_bits_wmeta_clients
+      (_mainPipe_io_metaWReq_bits_wmeta_clients),
+    .io_metaWReq_bits_wmeta_alias
+      (_mainPipe_io_metaWReq_bits_wmeta_alias),
+    .io_metaWReq_bits_wmeta_prefetch
+      (_mainPipe_io_metaWReq_bits_wmeta_prefetch),
+    .io_metaWReq_bits_wmeta_prefetchSrc
+      (_mainPipe_io_metaWReq_bits_wmeta_prefetchSrc),
+    .io_metaWReq_bits_wmeta_accessed
+      (_mainPipe_io_metaWReq_bits_wmeta_accessed),
+    .io_metaWReq_bits_wmeta_tagErr
+      (_mainPipe_io_metaWReq_bits_wmeta_tagErr),
+    .io_metaWReq_bits_wmeta_dataErr
+      (_mainPipe_io_metaWReq_bits_wmeta_dataErr),
+    .io_tagWReq_valid
+      (_mainPipe_io_tagWReq_valid),
+    .io_tagWReq_bits_set
+      (_mainPipe_io_tagWReq_bits_set),
+    .io_tagWReq_bits_wayOH
+      (_mainPipe_io_tagWReq_bits_wayOH),
+    .io_tagWReq_bits_wtag
+      (_mainPipe_io_tagWReq_bits_wtag),
+    .io_releaseBufWrite_valid
+      (_mainPipe_io_releaseBufWrite_valid),
+    .io_releaseBufWrite_bits_id
+      (_mainPipe_io_releaseBufWrite_bits_id),
+    .io_releaseBufWrite_bits_data_data
+      (_mainPipe_io_releaseBufWrite_bits_data_data),
+    .io_nestedwb_set
+      (_mainPipe_io_nestedwb_set),
+    .io_nestedwb_tag
+      (_mainPipe_io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty
+      (_mainPipe_io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip
+      (_mainPipe_io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty
+      (_mainPipe_io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB
+      (_mainPipe_io_nestedwb_b_toB),
+    .io_nestedwb_b_toN
+      (_mainPipe_io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean
+      (_mainPipe_io_nestedwb_b_toClean),
+    .io_nestedwbData_data
+      (_mainPipe_io_nestedwbData_data),
+    .io_l1Hint_ready                                                    (io_l1Hint_ready),
+    .io_l1Hint_valid                                                    (io_l1Hint_valid),
+    .io_l1Hint_bits_sourceId
+      (io_l1Hint_bits_sourceId),
+    .io_l1Hint_bits_isKeyword
+      (io_l1Hint_bits_isKeyword),
+    .io_l1Hint_bits_hasData
+      (io_l1Hint_bits_hasData),
+    .io_prefetchTrain_valid
+      (io_prefetch_train_valid),
+    .io_prefetchTrain_bits_tag
+      (io_prefetch_train_bits_tag),
+    .io_prefetchTrain_bits_set
+      (io_prefetch_train_bits_set),
+    .io_prefetchTrain_bits_needT
+      (io_prefetch_train_bits_needT),
+    .io_prefetchTrain_bits_source
+      (io_prefetch_train_bits_source),
+    .io_prefetchTrain_bits_vaddr
+      (io_prefetch_train_bits_vaddr),
+    .io_prefetchTrain_bits_hit
+      (io_prefetch_train_bits_hit),
+    .io_prefetchTrain_bits_prefetched
+      (io_prefetch_train_bits_prefetched),
+    .io_prefetchTrain_bits_pfsource
+      (io_prefetch_train_bits_pfsource),
+    .io_prefetchTrain_bits_reqsource
+      (io_prefetch_train_bits_reqsource),
+    .io_error_valid
+      (_mainPipe_io_error_valid),
+    .io_error_bits_valid
+      (_mainPipe_io_error_bits_valid),
+    .io_error_bits_address
+      (_mainPipe_io_error_bits_address),
+    .io_perf_0_value
+      (_mainPipe_io_perf_0_value),
+    .io_perf_1_value
+      (_mainPipe_io_perf_1_value),
+    .io_perf_2_value
+      (_mainPipe_io_perf_2_value),
+    .io_perf_3_value
+      (_mainPipe_io_perf_3_value),
+    .io_perf_4_value
+      (_mainPipe_io_perf_4_value),
+    .io_perf_5_value
+      (_mainPipe_io_perf_5_value),
+    .io_perf_6_value
+      (_mainPipe_io_perf_6_value),
+    .io_perf_7_value
+      (_mainPipe_io_perf_7_value),
+    .io_perf_8_value
+      (_mainPipe_io_perf_8_value),
+    .io_perf_9_value
+      (_mainPipe_io_perf_9_value),
+    .io_perf_10_value
+      (_mainPipe_io_perf_10_value),
+    .io_perf_11_value
+      (_mainPipe_io_perf_11_value),
+    .io_perf_12_value
+      (_mainPipe_io_perf_12_value)
+  );
+  RequestBuffer reqBuf (
+    .clock                                     (clock),
+    .reset                                     (reset),
+    .io_in_ready                               (_reqBuf_io_in_ready),
+    .io_in_valid                               (_sinkA_io_task_valid),
+    .io_in_bits_set                            (_sinkA_io_task_bits_set),
+    .io_in_bits_tag                            (_sinkA_io_task_bits_tag),
+    .io_in_bits_off                            (_sinkA_io_task_bits_off),
+    .io_in_bits_alias                          (_sinkA_io_task_bits_alias),
+    .io_in_bits_vaddr                          (_sinkA_io_task_bits_vaddr),
+    .io_in_bits_isKeyword                      (_sinkA_io_task_bits_isKeyword),
+    .io_in_bits_opcode                         (_sinkA_io_task_bits_opcode),
+    .io_in_bits_param                          (_sinkA_io_task_bits_param),
+    .io_in_bits_size                           (_sinkA_io_task_bits_size),
+    .io_in_bits_sourceId                       (_sinkA_io_task_bits_sourceId),
+    .io_in_bits_corrupt                        (_sinkA_io_task_bits_corrupt),
+    .io_in_bits_fromL2pft                      (_sinkA_io_task_bits_fromL2pft),
+    .io_in_bits_needHint                       (_sinkA_io_task_bits_needHint),
+    .io_in_bits_reqSource                      (_sinkA_io_task_bits_reqSource),
+    .io_out_ready                              (_reqArb_io_sinkA_ready),
+    .io_out_valid                              (_reqBuf_io_out_valid),
+    .io_out_bits_channel                       (_reqBuf_io_out_bits_channel),
+    .io_out_bits_txChannel                     (_reqBuf_io_out_bits_txChannel),
+    .io_out_bits_set                           (_reqBuf_io_out_bits_set),
+    .io_out_bits_tag                           (_reqBuf_io_out_bits_tag),
+    .io_out_bits_off                           (_reqBuf_io_out_bits_off),
+    .io_out_bits_alias                         (_reqBuf_io_out_bits_alias),
+    .io_out_bits_vaddr                         (_reqBuf_io_out_bits_vaddr),
+    .io_out_bits_isKeyword                     (_reqBuf_io_out_bits_isKeyword),
+    .io_out_bits_opcode                        (_reqBuf_io_out_bits_opcode),
+    .io_out_bits_param                         (_reqBuf_io_out_bits_param),
+    .io_out_bits_size                          (_reqBuf_io_out_bits_size),
+    .io_out_bits_sourceId                      (_reqBuf_io_out_bits_sourceId),
+    .io_out_bits_bufIdx                        (_reqBuf_io_out_bits_bufIdx),
+    .io_out_bits_needProbeAckData              (_reqBuf_io_out_bits_needProbeAckData),
+    .io_out_bits_denied                        (_reqBuf_io_out_bits_denied),
+    .io_out_bits_corrupt                       (_reqBuf_io_out_bits_corrupt),
+    .io_out_bits_mshrTask                      (_reqBuf_io_out_bits_mshrTask),
+    .io_out_bits_mshrId                        (_reqBuf_io_out_bits_mshrId),
+    .io_out_bits_aliasTask                     (_reqBuf_io_out_bits_aliasTask),
+    .io_out_bits_useProbeData                  (_reqBuf_io_out_bits_useProbeData),
+    .io_out_bits_mshrRetry                     (_reqBuf_io_out_bits_mshrRetry),
+    .io_out_bits_readProbeDataDown             (_reqBuf_io_out_bits_readProbeDataDown),
+    .io_out_bits_fromL2pft                     (_reqBuf_io_out_bits_fromL2pft),
+    .io_out_bits_needHint                      (_reqBuf_io_out_bits_needHint),
+    .io_out_bits_dirty                         (_reqBuf_io_out_bits_dirty),
+    .io_out_bits_way                           (_reqBuf_io_out_bits_way),
+    .io_out_bits_meta_dirty                    (_reqBuf_io_out_bits_meta_dirty),
+    .io_out_bits_meta_state                    (_reqBuf_io_out_bits_meta_state),
+    .io_out_bits_meta_clients                  (_reqBuf_io_out_bits_meta_clients),
+    .io_out_bits_meta_alias                    (_reqBuf_io_out_bits_meta_alias),
+    .io_out_bits_meta_prefetch                 (_reqBuf_io_out_bits_meta_prefetch),
+    .io_out_bits_meta_prefetchSrc              (_reqBuf_io_out_bits_meta_prefetchSrc),
+    .io_out_bits_meta_accessed                 (_reqBuf_io_out_bits_meta_accessed),
+    .io_out_bits_meta_tagErr                   (_reqBuf_io_out_bits_meta_tagErr),
+    .io_out_bits_meta_dataErr                  (_reqBuf_io_out_bits_meta_dataErr),
+    .io_out_bits_metaWen                       (_reqBuf_io_out_bits_metaWen),
+    .io_out_bits_tagWen                        (_reqBuf_io_out_bits_tagWen),
+    .io_out_bits_dsWen                         (_reqBuf_io_out_bits_dsWen),
+    .io_out_bits_replTask                      (_reqBuf_io_out_bits_replTask),
+    .io_out_bits_cmoTask                       (_reqBuf_io_out_bits_cmoTask),
+    .io_out_bits_cmoAll                        (_reqBuf_io_out_bits_cmoAll),
+    .io_out_bits_reqSource                     (_reqBuf_io_out_bits_reqSource),
+    .io_out_bits_mergeA                        (_reqBuf_io_out_bits_mergeA),
+    .io_out_bits_aMergeTask_off                (_reqBuf_io_out_bits_aMergeTask_off),
+    .io_out_bits_aMergeTask_alias              (_reqBuf_io_out_bits_aMergeTask_alias),
+    .io_out_bits_aMergeTask_vaddr              (_reqBuf_io_out_bits_aMergeTask_vaddr),
+    .io_out_bits_aMergeTask_isKeyword          (_reqBuf_io_out_bits_aMergeTask_isKeyword),
+    .io_out_bits_aMergeTask_opcode             (_reqBuf_io_out_bits_aMergeTask_opcode),
+    .io_out_bits_aMergeTask_param              (_reqBuf_io_out_bits_aMergeTask_param),
+    .io_out_bits_aMergeTask_sourceId           (_reqBuf_io_out_bits_aMergeTask_sourceId),
+    .io_out_bits_aMergeTask_meta_dirty
+      (_reqBuf_io_out_bits_aMergeTask_meta_dirty),
+    .io_out_bits_aMergeTask_meta_state
+      (_reqBuf_io_out_bits_aMergeTask_meta_state),
+    .io_out_bits_aMergeTask_meta_clients
+      (_reqBuf_io_out_bits_aMergeTask_meta_clients),
+    .io_out_bits_aMergeTask_meta_alias
+      (_reqBuf_io_out_bits_aMergeTask_meta_alias),
+    .io_out_bits_aMergeTask_meta_prefetch
+      (_reqBuf_io_out_bits_aMergeTask_meta_prefetch),
+    .io_out_bits_aMergeTask_meta_prefetchSrc
+      (_reqBuf_io_out_bits_aMergeTask_meta_prefetchSrc),
+    .io_out_bits_aMergeTask_meta_accessed
+      (_reqBuf_io_out_bits_aMergeTask_meta_accessed),
+    .io_out_bits_aMergeTask_meta_tagErr
+      (_reqBuf_io_out_bits_aMergeTask_meta_tagErr),
+    .io_out_bits_aMergeTask_meta_dataErr
+      (_reqBuf_io_out_bits_aMergeTask_meta_dataErr),
+    .io_out_bits_snpHitRelease                 (_reqBuf_io_out_bits_snpHitRelease),
+    .io_out_bits_snpHitReleaseToInval          (_reqBuf_io_out_bits_snpHitReleaseToInval),
+    .io_out_bits_snpHitReleaseToClean          (_reqBuf_io_out_bits_snpHitReleaseToClean),
+    .io_out_bits_snpHitReleaseWithData
+      (_reqBuf_io_out_bits_snpHitReleaseWithData),
+    .io_out_bits_snpHitReleaseIdx              (_reqBuf_io_out_bits_snpHitReleaseIdx),
+    .io_out_bits_snpHitReleaseMeta_dirty
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_dirty),
+    .io_out_bits_snpHitReleaseMeta_state
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_state),
+    .io_out_bits_snpHitReleaseMeta_clients
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_clients),
+    .io_out_bits_snpHitReleaseMeta_alias
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_alias),
+    .io_out_bits_snpHitReleaseMeta_prefetch
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_prefetch),
+    .io_out_bits_snpHitReleaseMeta_prefetchSrc
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_out_bits_snpHitReleaseMeta_accessed
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_accessed),
+    .io_out_bits_snpHitReleaseMeta_tagErr
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_tagErr),
+    .io_out_bits_snpHitReleaseMeta_dataErr
+      (_reqBuf_io_out_bits_snpHitReleaseMeta_dataErr),
+    .io_out_bits_tgtID                         (_reqBuf_io_out_bits_tgtID),
+    .io_out_bits_srcID                         (_reqBuf_io_out_bits_srcID),
+    .io_out_bits_txnID                         (_reqBuf_io_out_bits_txnID),
+    .io_out_bits_homeNID                       (_reqBuf_io_out_bits_homeNID),
+    .io_out_bits_dbID                          (_reqBuf_io_out_bits_dbID),
+    .io_out_bits_fwdNID                        (_reqBuf_io_out_bits_fwdNID),
+    .io_out_bits_fwdTxnID                      (_reqBuf_io_out_bits_fwdTxnID),
+    .io_out_bits_chiOpcode                     (_reqBuf_io_out_bits_chiOpcode),
+    .io_out_bits_resp                          (_reqBuf_io_out_bits_resp),
+    .io_out_bits_fwdState                      (_reqBuf_io_out_bits_fwdState),
+    .io_out_bits_pCrdType                      (_reqBuf_io_out_bits_pCrdType),
+    .io_out_bits_retToSrc                      (_reqBuf_io_out_bits_retToSrc),
+    .io_out_bits_likelyshared                  (_reqBuf_io_out_bits_likelyshared),
+    .io_out_bits_expCompAck                    (_reqBuf_io_out_bits_expCompAck),
+    .io_out_bits_allowRetry                    (_reqBuf_io_out_bits_allowRetry),
+    .io_out_bits_memAttr_allocate              (_reqBuf_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable             (_reqBuf_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device                (_reqBuf_io_out_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa                   (_reqBuf_io_out_bits_memAttr_ewa),
+    .io_out_bits_traceTag                      (_reqBuf_io_out_bits_traceTag),
+    .io_mshrInfo_0_valid                       (_mshrCtl_io_msInfo_0_valid),
+    .io_mshrInfo_0_bits_channel                (_mshrCtl_io_msInfo_0_bits_channel),
+    .io_mshrInfo_0_bits_set                    (_mshrCtl_io_msInfo_0_bits_set),
+    .io_mshrInfo_0_bits_reqTag                 (_mshrCtl_io_msInfo_0_bits_reqTag),
+    .io_mshrInfo_0_bits_willFree               (_mshrCtl_io_msInfo_0_bits_willFree),
+    .io_mshrInfo_0_bits_needRelease            (_mshrCtl_io_msInfo_0_bits_needRelease),
+    .io_mshrInfo_0_bits_metaTag                (_mshrCtl_io_msInfo_0_bits_metaTag),
+    .io_mshrInfo_0_bits_dirHit                 (_mshrCtl_io_msInfo_0_bits_dirHit),
+    .io_mshrInfo_0_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_0_bits_isAcqOrPrefetch),
+    .io_mshrInfo_0_bits_isPrefetch             (_mshrCtl_io_msInfo_0_bits_isPrefetch),
+    .io_mshrInfo_0_bits_param                  (_mshrCtl_io_msInfo_0_bits_param),
+    .io_mshrInfo_0_bits_mergeA                 (_mshrCtl_io_msInfo_0_bits_mergeA),
+    .io_mshrInfo_0_bits_w_grantlast            (_mshrCtl_io_msInfo_0_bits_w_grantlast),
+    .io_mshrInfo_0_bits_w_grant                (_mshrCtl_io_msInfo_0_bits_w_grant),
+    .io_mshrInfo_1_valid                       (_mshrCtl_io_msInfo_1_valid),
+    .io_mshrInfo_1_bits_channel                (_mshrCtl_io_msInfo_1_bits_channel),
+    .io_mshrInfo_1_bits_set                    (_mshrCtl_io_msInfo_1_bits_set),
+    .io_mshrInfo_1_bits_reqTag                 (_mshrCtl_io_msInfo_1_bits_reqTag),
+    .io_mshrInfo_1_bits_willFree               (_mshrCtl_io_msInfo_1_bits_willFree),
+    .io_mshrInfo_1_bits_needRelease            (_mshrCtl_io_msInfo_1_bits_needRelease),
+    .io_mshrInfo_1_bits_metaTag                (_mshrCtl_io_msInfo_1_bits_metaTag),
+    .io_mshrInfo_1_bits_dirHit                 (_mshrCtl_io_msInfo_1_bits_dirHit),
+    .io_mshrInfo_1_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_1_bits_isAcqOrPrefetch),
+    .io_mshrInfo_1_bits_isPrefetch             (_mshrCtl_io_msInfo_1_bits_isPrefetch),
+    .io_mshrInfo_1_bits_param                  (_mshrCtl_io_msInfo_1_bits_param),
+    .io_mshrInfo_1_bits_mergeA                 (_mshrCtl_io_msInfo_1_bits_mergeA),
+    .io_mshrInfo_1_bits_w_grantlast            (_mshrCtl_io_msInfo_1_bits_w_grantlast),
+    .io_mshrInfo_1_bits_w_grant                (_mshrCtl_io_msInfo_1_bits_w_grant),
+    .io_mshrInfo_2_valid                       (_mshrCtl_io_msInfo_2_valid),
+    .io_mshrInfo_2_bits_channel                (_mshrCtl_io_msInfo_2_bits_channel),
+    .io_mshrInfo_2_bits_set                    (_mshrCtl_io_msInfo_2_bits_set),
+    .io_mshrInfo_2_bits_reqTag                 (_mshrCtl_io_msInfo_2_bits_reqTag),
+    .io_mshrInfo_2_bits_willFree               (_mshrCtl_io_msInfo_2_bits_willFree),
+    .io_mshrInfo_2_bits_needRelease            (_mshrCtl_io_msInfo_2_bits_needRelease),
+    .io_mshrInfo_2_bits_metaTag                (_mshrCtl_io_msInfo_2_bits_metaTag),
+    .io_mshrInfo_2_bits_dirHit                 (_mshrCtl_io_msInfo_2_bits_dirHit),
+    .io_mshrInfo_2_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_2_bits_isAcqOrPrefetch),
+    .io_mshrInfo_2_bits_isPrefetch             (_mshrCtl_io_msInfo_2_bits_isPrefetch),
+    .io_mshrInfo_2_bits_param                  (_mshrCtl_io_msInfo_2_bits_param),
+    .io_mshrInfo_2_bits_mergeA                 (_mshrCtl_io_msInfo_2_bits_mergeA),
+    .io_mshrInfo_2_bits_w_grantlast            (_mshrCtl_io_msInfo_2_bits_w_grantlast),
+    .io_mshrInfo_2_bits_w_grant                (_mshrCtl_io_msInfo_2_bits_w_grant),
+    .io_mshrInfo_3_valid                       (_mshrCtl_io_msInfo_3_valid),
+    .io_mshrInfo_3_bits_channel                (_mshrCtl_io_msInfo_3_bits_channel),
+    .io_mshrInfo_3_bits_set                    (_mshrCtl_io_msInfo_3_bits_set),
+    .io_mshrInfo_3_bits_reqTag                 (_mshrCtl_io_msInfo_3_bits_reqTag),
+    .io_mshrInfo_3_bits_willFree               (_mshrCtl_io_msInfo_3_bits_willFree),
+    .io_mshrInfo_3_bits_needRelease            (_mshrCtl_io_msInfo_3_bits_needRelease),
+    .io_mshrInfo_3_bits_metaTag                (_mshrCtl_io_msInfo_3_bits_metaTag),
+    .io_mshrInfo_3_bits_dirHit                 (_mshrCtl_io_msInfo_3_bits_dirHit),
+    .io_mshrInfo_3_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_3_bits_isAcqOrPrefetch),
+    .io_mshrInfo_3_bits_isPrefetch             (_mshrCtl_io_msInfo_3_bits_isPrefetch),
+    .io_mshrInfo_3_bits_param                  (_mshrCtl_io_msInfo_3_bits_param),
+    .io_mshrInfo_3_bits_mergeA                 (_mshrCtl_io_msInfo_3_bits_mergeA),
+    .io_mshrInfo_3_bits_w_grantlast            (_mshrCtl_io_msInfo_3_bits_w_grantlast),
+    .io_mshrInfo_3_bits_w_grant                (_mshrCtl_io_msInfo_3_bits_w_grant),
+    .io_mshrInfo_4_valid                       (_mshrCtl_io_msInfo_4_valid),
+    .io_mshrInfo_4_bits_channel                (_mshrCtl_io_msInfo_4_bits_channel),
+    .io_mshrInfo_4_bits_set                    (_mshrCtl_io_msInfo_4_bits_set),
+    .io_mshrInfo_4_bits_reqTag                 (_mshrCtl_io_msInfo_4_bits_reqTag),
+    .io_mshrInfo_4_bits_willFree               (_mshrCtl_io_msInfo_4_bits_willFree),
+    .io_mshrInfo_4_bits_needRelease            (_mshrCtl_io_msInfo_4_bits_needRelease),
+    .io_mshrInfo_4_bits_metaTag                (_mshrCtl_io_msInfo_4_bits_metaTag),
+    .io_mshrInfo_4_bits_dirHit                 (_mshrCtl_io_msInfo_4_bits_dirHit),
+    .io_mshrInfo_4_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_4_bits_isAcqOrPrefetch),
+    .io_mshrInfo_4_bits_isPrefetch             (_mshrCtl_io_msInfo_4_bits_isPrefetch),
+    .io_mshrInfo_4_bits_param                  (_mshrCtl_io_msInfo_4_bits_param),
+    .io_mshrInfo_4_bits_mergeA                 (_mshrCtl_io_msInfo_4_bits_mergeA),
+    .io_mshrInfo_4_bits_w_grantlast            (_mshrCtl_io_msInfo_4_bits_w_grantlast),
+    .io_mshrInfo_4_bits_w_grant                (_mshrCtl_io_msInfo_4_bits_w_grant),
+    .io_mshrInfo_5_valid                       (_mshrCtl_io_msInfo_5_valid),
+    .io_mshrInfo_5_bits_channel                (_mshrCtl_io_msInfo_5_bits_channel),
+    .io_mshrInfo_5_bits_set                    (_mshrCtl_io_msInfo_5_bits_set),
+    .io_mshrInfo_5_bits_reqTag                 (_mshrCtl_io_msInfo_5_bits_reqTag),
+    .io_mshrInfo_5_bits_willFree               (_mshrCtl_io_msInfo_5_bits_willFree),
+    .io_mshrInfo_5_bits_needRelease            (_mshrCtl_io_msInfo_5_bits_needRelease),
+    .io_mshrInfo_5_bits_metaTag                (_mshrCtl_io_msInfo_5_bits_metaTag),
+    .io_mshrInfo_5_bits_dirHit                 (_mshrCtl_io_msInfo_5_bits_dirHit),
+    .io_mshrInfo_5_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_5_bits_isAcqOrPrefetch),
+    .io_mshrInfo_5_bits_isPrefetch             (_mshrCtl_io_msInfo_5_bits_isPrefetch),
+    .io_mshrInfo_5_bits_param                  (_mshrCtl_io_msInfo_5_bits_param),
+    .io_mshrInfo_5_bits_mergeA                 (_mshrCtl_io_msInfo_5_bits_mergeA),
+    .io_mshrInfo_5_bits_w_grantlast            (_mshrCtl_io_msInfo_5_bits_w_grantlast),
+    .io_mshrInfo_5_bits_w_grant                (_mshrCtl_io_msInfo_5_bits_w_grant),
+    .io_mshrInfo_6_valid                       (_mshrCtl_io_msInfo_6_valid),
+    .io_mshrInfo_6_bits_channel                (_mshrCtl_io_msInfo_6_bits_channel),
+    .io_mshrInfo_6_bits_set                    (_mshrCtl_io_msInfo_6_bits_set),
+    .io_mshrInfo_6_bits_reqTag                 (_mshrCtl_io_msInfo_6_bits_reqTag),
+    .io_mshrInfo_6_bits_willFree               (_mshrCtl_io_msInfo_6_bits_willFree),
+    .io_mshrInfo_6_bits_needRelease            (_mshrCtl_io_msInfo_6_bits_needRelease),
+    .io_mshrInfo_6_bits_metaTag                (_mshrCtl_io_msInfo_6_bits_metaTag),
+    .io_mshrInfo_6_bits_dirHit                 (_mshrCtl_io_msInfo_6_bits_dirHit),
+    .io_mshrInfo_6_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_6_bits_isAcqOrPrefetch),
+    .io_mshrInfo_6_bits_isPrefetch             (_mshrCtl_io_msInfo_6_bits_isPrefetch),
+    .io_mshrInfo_6_bits_param                  (_mshrCtl_io_msInfo_6_bits_param),
+    .io_mshrInfo_6_bits_mergeA                 (_mshrCtl_io_msInfo_6_bits_mergeA),
+    .io_mshrInfo_6_bits_w_grantlast            (_mshrCtl_io_msInfo_6_bits_w_grantlast),
+    .io_mshrInfo_6_bits_w_grant                (_mshrCtl_io_msInfo_6_bits_w_grant),
+    .io_mshrInfo_7_valid                       (_mshrCtl_io_msInfo_7_valid),
+    .io_mshrInfo_7_bits_channel                (_mshrCtl_io_msInfo_7_bits_channel),
+    .io_mshrInfo_7_bits_set                    (_mshrCtl_io_msInfo_7_bits_set),
+    .io_mshrInfo_7_bits_reqTag                 (_mshrCtl_io_msInfo_7_bits_reqTag),
+    .io_mshrInfo_7_bits_willFree               (_mshrCtl_io_msInfo_7_bits_willFree),
+    .io_mshrInfo_7_bits_needRelease            (_mshrCtl_io_msInfo_7_bits_needRelease),
+    .io_mshrInfo_7_bits_metaTag                (_mshrCtl_io_msInfo_7_bits_metaTag),
+    .io_mshrInfo_7_bits_dirHit                 (_mshrCtl_io_msInfo_7_bits_dirHit),
+    .io_mshrInfo_7_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_7_bits_isAcqOrPrefetch),
+    .io_mshrInfo_7_bits_isPrefetch             (_mshrCtl_io_msInfo_7_bits_isPrefetch),
+    .io_mshrInfo_7_bits_param                  (_mshrCtl_io_msInfo_7_bits_param),
+    .io_mshrInfo_7_bits_mergeA                 (_mshrCtl_io_msInfo_7_bits_mergeA),
+    .io_mshrInfo_7_bits_w_grantlast            (_mshrCtl_io_msInfo_7_bits_w_grantlast),
+    .io_mshrInfo_7_bits_w_grant                (_mshrCtl_io_msInfo_7_bits_w_grant),
+    .io_mshrInfo_8_valid                       (_mshrCtl_io_msInfo_8_valid),
+    .io_mshrInfo_8_bits_channel                (_mshrCtl_io_msInfo_8_bits_channel),
+    .io_mshrInfo_8_bits_set                    (_mshrCtl_io_msInfo_8_bits_set),
+    .io_mshrInfo_8_bits_reqTag                 (_mshrCtl_io_msInfo_8_bits_reqTag),
+    .io_mshrInfo_8_bits_willFree               (_mshrCtl_io_msInfo_8_bits_willFree),
+    .io_mshrInfo_8_bits_needRelease            (_mshrCtl_io_msInfo_8_bits_needRelease),
+    .io_mshrInfo_8_bits_metaTag                (_mshrCtl_io_msInfo_8_bits_metaTag),
+    .io_mshrInfo_8_bits_dirHit                 (_mshrCtl_io_msInfo_8_bits_dirHit),
+    .io_mshrInfo_8_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_8_bits_isAcqOrPrefetch),
+    .io_mshrInfo_8_bits_isPrefetch             (_mshrCtl_io_msInfo_8_bits_isPrefetch),
+    .io_mshrInfo_8_bits_param                  (_mshrCtl_io_msInfo_8_bits_param),
+    .io_mshrInfo_8_bits_mergeA                 (_mshrCtl_io_msInfo_8_bits_mergeA),
+    .io_mshrInfo_8_bits_w_grantlast            (_mshrCtl_io_msInfo_8_bits_w_grantlast),
+    .io_mshrInfo_8_bits_w_grant                (_mshrCtl_io_msInfo_8_bits_w_grant),
+    .io_mshrInfo_9_valid                       (_mshrCtl_io_msInfo_9_valid),
+    .io_mshrInfo_9_bits_channel                (_mshrCtl_io_msInfo_9_bits_channel),
+    .io_mshrInfo_9_bits_set                    (_mshrCtl_io_msInfo_9_bits_set),
+    .io_mshrInfo_9_bits_reqTag                 (_mshrCtl_io_msInfo_9_bits_reqTag),
+    .io_mshrInfo_9_bits_willFree               (_mshrCtl_io_msInfo_9_bits_willFree),
+    .io_mshrInfo_9_bits_needRelease            (_mshrCtl_io_msInfo_9_bits_needRelease),
+    .io_mshrInfo_9_bits_metaTag                (_mshrCtl_io_msInfo_9_bits_metaTag),
+    .io_mshrInfo_9_bits_dirHit                 (_mshrCtl_io_msInfo_9_bits_dirHit),
+    .io_mshrInfo_9_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_9_bits_isAcqOrPrefetch),
+    .io_mshrInfo_9_bits_isPrefetch             (_mshrCtl_io_msInfo_9_bits_isPrefetch),
+    .io_mshrInfo_9_bits_param                  (_mshrCtl_io_msInfo_9_bits_param),
+    .io_mshrInfo_9_bits_mergeA                 (_mshrCtl_io_msInfo_9_bits_mergeA),
+    .io_mshrInfo_9_bits_w_grantlast            (_mshrCtl_io_msInfo_9_bits_w_grantlast),
+    .io_mshrInfo_9_bits_w_grant                (_mshrCtl_io_msInfo_9_bits_w_grant),
+    .io_mshrInfo_10_valid                      (_mshrCtl_io_msInfo_10_valid),
+    .io_mshrInfo_10_bits_channel               (_mshrCtl_io_msInfo_10_bits_channel),
+    .io_mshrInfo_10_bits_set                   (_mshrCtl_io_msInfo_10_bits_set),
+    .io_mshrInfo_10_bits_reqTag                (_mshrCtl_io_msInfo_10_bits_reqTag),
+    .io_mshrInfo_10_bits_willFree              (_mshrCtl_io_msInfo_10_bits_willFree),
+    .io_mshrInfo_10_bits_needRelease           (_mshrCtl_io_msInfo_10_bits_needRelease),
+    .io_mshrInfo_10_bits_metaTag               (_mshrCtl_io_msInfo_10_bits_metaTag),
+    .io_mshrInfo_10_bits_dirHit                (_mshrCtl_io_msInfo_10_bits_dirHit),
+    .io_mshrInfo_10_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_10_bits_isAcqOrPrefetch),
+    .io_mshrInfo_10_bits_isPrefetch            (_mshrCtl_io_msInfo_10_bits_isPrefetch),
+    .io_mshrInfo_10_bits_param                 (_mshrCtl_io_msInfo_10_bits_param),
+    .io_mshrInfo_10_bits_mergeA                (_mshrCtl_io_msInfo_10_bits_mergeA),
+    .io_mshrInfo_10_bits_w_grantlast           (_mshrCtl_io_msInfo_10_bits_w_grantlast),
+    .io_mshrInfo_10_bits_w_grant               (_mshrCtl_io_msInfo_10_bits_w_grant),
+    .io_mshrInfo_11_valid                      (_mshrCtl_io_msInfo_11_valid),
+    .io_mshrInfo_11_bits_channel               (_mshrCtl_io_msInfo_11_bits_channel),
+    .io_mshrInfo_11_bits_set                   (_mshrCtl_io_msInfo_11_bits_set),
+    .io_mshrInfo_11_bits_reqTag                (_mshrCtl_io_msInfo_11_bits_reqTag),
+    .io_mshrInfo_11_bits_willFree              (_mshrCtl_io_msInfo_11_bits_willFree),
+    .io_mshrInfo_11_bits_needRelease           (_mshrCtl_io_msInfo_11_bits_needRelease),
+    .io_mshrInfo_11_bits_metaTag               (_mshrCtl_io_msInfo_11_bits_metaTag),
+    .io_mshrInfo_11_bits_dirHit                (_mshrCtl_io_msInfo_11_bits_dirHit),
+    .io_mshrInfo_11_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_11_bits_isAcqOrPrefetch),
+    .io_mshrInfo_11_bits_isPrefetch            (_mshrCtl_io_msInfo_11_bits_isPrefetch),
+    .io_mshrInfo_11_bits_param                 (_mshrCtl_io_msInfo_11_bits_param),
+    .io_mshrInfo_11_bits_mergeA                (_mshrCtl_io_msInfo_11_bits_mergeA),
+    .io_mshrInfo_11_bits_w_grantlast           (_mshrCtl_io_msInfo_11_bits_w_grantlast),
+    .io_mshrInfo_11_bits_w_grant               (_mshrCtl_io_msInfo_11_bits_w_grant),
+    .io_mshrInfo_12_valid                      (_mshrCtl_io_msInfo_12_valid),
+    .io_mshrInfo_12_bits_channel               (_mshrCtl_io_msInfo_12_bits_channel),
+    .io_mshrInfo_12_bits_set                   (_mshrCtl_io_msInfo_12_bits_set),
+    .io_mshrInfo_12_bits_reqTag                (_mshrCtl_io_msInfo_12_bits_reqTag),
+    .io_mshrInfo_12_bits_willFree              (_mshrCtl_io_msInfo_12_bits_willFree),
+    .io_mshrInfo_12_bits_needRelease           (_mshrCtl_io_msInfo_12_bits_needRelease),
+    .io_mshrInfo_12_bits_metaTag               (_mshrCtl_io_msInfo_12_bits_metaTag),
+    .io_mshrInfo_12_bits_dirHit                (_mshrCtl_io_msInfo_12_bits_dirHit),
+    .io_mshrInfo_12_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_12_bits_isAcqOrPrefetch),
+    .io_mshrInfo_12_bits_isPrefetch            (_mshrCtl_io_msInfo_12_bits_isPrefetch),
+    .io_mshrInfo_12_bits_param                 (_mshrCtl_io_msInfo_12_bits_param),
+    .io_mshrInfo_12_bits_mergeA                (_mshrCtl_io_msInfo_12_bits_mergeA),
+    .io_mshrInfo_12_bits_w_grantlast           (_mshrCtl_io_msInfo_12_bits_w_grantlast),
+    .io_mshrInfo_12_bits_w_grant               (_mshrCtl_io_msInfo_12_bits_w_grant),
+    .io_mshrInfo_13_valid                      (_mshrCtl_io_msInfo_13_valid),
+    .io_mshrInfo_13_bits_channel               (_mshrCtl_io_msInfo_13_bits_channel),
+    .io_mshrInfo_13_bits_set                   (_mshrCtl_io_msInfo_13_bits_set),
+    .io_mshrInfo_13_bits_reqTag                (_mshrCtl_io_msInfo_13_bits_reqTag),
+    .io_mshrInfo_13_bits_willFree              (_mshrCtl_io_msInfo_13_bits_willFree),
+    .io_mshrInfo_13_bits_needRelease           (_mshrCtl_io_msInfo_13_bits_needRelease),
+    .io_mshrInfo_13_bits_metaTag               (_mshrCtl_io_msInfo_13_bits_metaTag),
+    .io_mshrInfo_13_bits_dirHit                (_mshrCtl_io_msInfo_13_bits_dirHit),
+    .io_mshrInfo_13_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_13_bits_isAcqOrPrefetch),
+    .io_mshrInfo_13_bits_isPrefetch            (_mshrCtl_io_msInfo_13_bits_isPrefetch),
+    .io_mshrInfo_13_bits_param                 (_mshrCtl_io_msInfo_13_bits_param),
+    .io_mshrInfo_13_bits_mergeA                (_mshrCtl_io_msInfo_13_bits_mergeA),
+    .io_mshrInfo_13_bits_w_grantlast           (_mshrCtl_io_msInfo_13_bits_w_grantlast),
+    .io_mshrInfo_13_bits_w_grant               (_mshrCtl_io_msInfo_13_bits_w_grant),
+    .io_mshrInfo_14_valid                      (_mshrCtl_io_msInfo_14_valid),
+    .io_mshrInfo_14_bits_channel               (_mshrCtl_io_msInfo_14_bits_channel),
+    .io_mshrInfo_14_bits_set                   (_mshrCtl_io_msInfo_14_bits_set),
+    .io_mshrInfo_14_bits_reqTag                (_mshrCtl_io_msInfo_14_bits_reqTag),
+    .io_mshrInfo_14_bits_willFree              (_mshrCtl_io_msInfo_14_bits_willFree),
+    .io_mshrInfo_14_bits_needRelease           (_mshrCtl_io_msInfo_14_bits_needRelease),
+    .io_mshrInfo_14_bits_metaTag               (_mshrCtl_io_msInfo_14_bits_metaTag),
+    .io_mshrInfo_14_bits_dirHit                (_mshrCtl_io_msInfo_14_bits_dirHit),
+    .io_mshrInfo_14_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_14_bits_isAcqOrPrefetch),
+    .io_mshrInfo_14_bits_isPrefetch            (_mshrCtl_io_msInfo_14_bits_isPrefetch),
+    .io_mshrInfo_14_bits_param                 (_mshrCtl_io_msInfo_14_bits_param),
+    .io_mshrInfo_14_bits_mergeA                (_mshrCtl_io_msInfo_14_bits_mergeA),
+    .io_mshrInfo_14_bits_w_grantlast           (_mshrCtl_io_msInfo_14_bits_w_grantlast),
+    .io_mshrInfo_14_bits_w_grant               (_mshrCtl_io_msInfo_14_bits_w_grant),
+    .io_mshrInfo_15_valid                      (_mshrCtl_io_msInfo_15_valid),
+    .io_mshrInfo_15_bits_channel               (_mshrCtl_io_msInfo_15_bits_channel),
+    .io_mshrInfo_15_bits_set                   (_mshrCtl_io_msInfo_15_bits_set),
+    .io_mshrInfo_15_bits_reqTag                (_mshrCtl_io_msInfo_15_bits_reqTag),
+    .io_mshrInfo_15_bits_willFree              (_mshrCtl_io_msInfo_15_bits_willFree),
+    .io_mshrInfo_15_bits_needRelease           (_mshrCtl_io_msInfo_15_bits_needRelease),
+    .io_mshrInfo_15_bits_metaTag               (_mshrCtl_io_msInfo_15_bits_metaTag),
+    .io_mshrInfo_15_bits_dirHit                (_mshrCtl_io_msInfo_15_bits_dirHit),
+    .io_mshrInfo_15_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_15_bits_isAcqOrPrefetch),
+    .io_mshrInfo_15_bits_isPrefetch            (_mshrCtl_io_msInfo_15_bits_isPrefetch),
+    .io_mshrInfo_15_bits_param                 (_mshrCtl_io_msInfo_15_bits_param),
+    .io_mshrInfo_15_bits_mergeA                (_mshrCtl_io_msInfo_15_bits_mergeA),
+    .io_mshrInfo_15_bits_w_grantlast           (_mshrCtl_io_msInfo_15_bits_w_grantlast),
+    .io_mshrInfo_15_bits_w_grant               (_mshrCtl_io_msInfo_15_bits_w_grant),
+    .io_aMergeTask_valid                       (_reqBuf_io_aMergeTask_valid),
+    .io_aMergeTask_bits_idOH                   (_reqBuf_io_aMergeTask_bits_idOH),
+    .io_aMergeTask_bits_task_off               (_reqBuf_io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_task_alias             (_reqBuf_io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_task_vaddr             (_reqBuf_io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_task_isKeyword
+      (_reqBuf_io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_task_opcode            (_reqBuf_io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_task_param             (_reqBuf_io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_task_sourceId          (_reqBuf_io_aMergeTask_bits_task_sourceId),
+    .io_mainPipeBlock_0                        (_mainPipe_io_toReqBuf_0),
+    .io_mainPipeBlock_1                        (_mainPipe_io_toReqBuf_1),
+    .io_taskFromArb_s2_valid                   (_reqArb_io_taskToPipe_s2_valid),
+    .io_taskFromArb_s2_bits_channel            (_reqArb_io_taskToPipe_s2_bits_channel),
+    .io_taskFromArb_s2_bits_set                (_reqArb_io_taskToPipe_s2_bits_set),
+    .io_taskFromArb_s2_bits_mshrTask           (_reqArb_io_taskToPipe_s2_bits_mshrTask),
+    .io_ATag                                   (_reqBuf_io_ATag),
+    .io_ASet                                   (_reqBuf_io_ASet),
+    .io_s1Entrance_valid                       (_reqArb_io_s1Entrance_valid),
+    .io_s1Entrance_bits_set                    (_reqArb_io_s1Entrance_bits_set)
+  );
+  MSHRCtl mshrCtl (
+    .clock                                                                 (clock),
+    .reset                                                                 (reset),
+    .io_toReqArb_blockA_s1
+      (_mshrCtl_io_toReqArb_blockA_s1),
+    .io_toReqArb_blockB_s1
+      (_mshrCtl_io_toReqArb_blockB_s1),
+    .io_fromMainPipe_mshr_alloc_s3_valid
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_valid),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_hit
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_hit),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_tag
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_tag),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_set
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_set),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_way
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_way),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dirty
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dirty),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_state
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_state),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_clients
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_clients),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_alias
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_alias),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetch
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetch),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_prefetchSrc),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_accessed
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_accessed),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_tagErr
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_tagErr),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_meta_dataErr
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_meta_dataErr),
+    .io_fromMainPipe_mshr_alloc_s3_bits_dirResult_error
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_dirResult_error),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_s_acquire
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_acquire),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_s_rprobe
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rprobe),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_s_pprobe
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_pprobe),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_s_release
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_release),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_s_probeack
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_probeack),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_s_refill
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_refill),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_s_cmoresp
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_cmoresp),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeackfirst
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeackfirst),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_w_rprobeacklast
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_rprobeacklast),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeackfirst
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeackfirst),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_w_pprobeacklast
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_pprobeacklast),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantfirst
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantfirst),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_w_grantlast
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grantlast),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_w_grant
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_grant),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_w_releaseack
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_releaseack),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_w_replResp
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_w_replResp),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_s_rcompack
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_rcompack),
+    .io_fromMainPipe_mshr_alloc_s3_bits_state_s_dct
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_state_s_dct),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_channel
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_channel),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_set
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_set),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_tag
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_tag),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_off
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_off),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_alias
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_alias),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_isKeyword
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_isKeyword),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_opcode
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_opcode),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_param
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_param),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_sourceId
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_sourceId),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_aliasTask
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_aliasTask),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_fromL2pft
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_fromL2pft),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_reqSource
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_reqSource),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitRelease
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitRelease),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToInval
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToInval),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseToClean
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseToClean),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseWithData
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseWithData),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseIdx
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseIdx),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dirty),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_state),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_clients),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_alias),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetch),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_accessed),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_tagErr),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_snpHitReleaseMeta_dataErr),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_srcID
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_srcID),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_txnID
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_txnID),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_fwdNID
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdNID),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_fwdTxnID
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_fwdTxnID),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_chiOpcode
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_chiOpcode),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_retToSrc
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_retToSrc),
+    .io_fromMainPipe_mshr_alloc_s3_bits_task_traceTag
+      (_mainPipe_io_toMSHRCtl_mshr_alloc_s3_bits_task_traceTag),
+    .io_toMainPipe_mshr_alloc_ptr
+      (_mshrCtl_io_toMainPipe_mshr_alloc_ptr),
+    .io_mshrTask_ready
+      (_reqArb_io_mshrTask_ready),
+    .io_mshrTask_valid
+      (_mshrCtl_io_mshrTask_valid),
+    .io_mshrTask_bits_channel
+      (_mshrCtl_io_mshrTask_bits_channel),
+    .io_mshrTask_bits_txChannel
+      (_mshrCtl_io_mshrTask_bits_txChannel),
+    .io_mshrTask_bits_set
+      (_mshrCtl_io_mshrTask_bits_set),
+    .io_mshrTask_bits_tag
+      (_mshrCtl_io_mshrTask_bits_tag),
+    .io_mshrTask_bits_off
+      (_mshrCtl_io_mshrTask_bits_off),
+    .io_mshrTask_bits_alias
+      (_mshrCtl_io_mshrTask_bits_alias),
+    .io_mshrTask_bits_isKeyword
+      (_mshrCtl_io_mshrTask_bits_isKeyword),
+    .io_mshrTask_bits_opcode
+      (_mshrCtl_io_mshrTask_bits_opcode),
+    .io_mshrTask_bits_param
+      (_mshrCtl_io_mshrTask_bits_param),
+    .io_mshrTask_bits_size
+      (_mshrCtl_io_mshrTask_bits_size),
+    .io_mshrTask_bits_sourceId
+      (_mshrCtl_io_mshrTask_bits_sourceId),
+    .io_mshrTask_bits_denied
+      (_mshrCtl_io_mshrTask_bits_denied),
+    .io_mshrTask_bits_corrupt
+      (_mshrCtl_io_mshrTask_bits_corrupt),
+    .io_mshrTask_bits_mshrTask
+      (_mshrCtl_io_mshrTask_bits_mshrTask),
+    .io_mshrTask_bits_mshrId
+      (_mshrCtl_io_mshrTask_bits_mshrId),
+    .io_mshrTask_bits_aliasTask
+      (_mshrCtl_io_mshrTask_bits_aliasTask),
+    .io_mshrTask_bits_useProbeData
+      (_mshrCtl_io_mshrTask_bits_useProbeData),
+    .io_mshrTask_bits_mshrRetry
+      (_mshrCtl_io_mshrTask_bits_mshrRetry),
+    .io_mshrTask_bits_readProbeDataDown
+      (_mshrCtl_io_mshrTask_bits_readProbeDataDown),
+    .io_mshrTask_bits_fromL2pft
+      (_mshrCtl_io_mshrTask_bits_fromL2pft),
+    .io_mshrTask_bits_dirty
+      (_mshrCtl_io_mshrTask_bits_dirty),
+    .io_mshrTask_bits_way
+      (_mshrCtl_io_mshrTask_bits_way),
+    .io_mshrTask_bits_meta_dirty
+      (_mshrCtl_io_mshrTask_bits_meta_dirty),
+    .io_mshrTask_bits_meta_state
+      (_mshrCtl_io_mshrTask_bits_meta_state),
+    .io_mshrTask_bits_meta_clients
+      (_mshrCtl_io_mshrTask_bits_meta_clients),
+    .io_mshrTask_bits_meta_alias
+      (_mshrCtl_io_mshrTask_bits_meta_alias),
+    .io_mshrTask_bits_meta_prefetch
+      (_mshrCtl_io_mshrTask_bits_meta_prefetch),
+    .io_mshrTask_bits_meta_prefetchSrc
+      (_mshrCtl_io_mshrTask_bits_meta_prefetchSrc),
+    .io_mshrTask_bits_meta_accessed
+      (_mshrCtl_io_mshrTask_bits_meta_accessed),
+    .io_mshrTask_bits_meta_tagErr
+      (_mshrCtl_io_mshrTask_bits_meta_tagErr),
+    .io_mshrTask_bits_meta_dataErr
+      (_mshrCtl_io_mshrTask_bits_meta_dataErr),
+    .io_mshrTask_bits_metaWen
+      (_mshrCtl_io_mshrTask_bits_metaWen),
+    .io_mshrTask_bits_tagWen
+      (_mshrCtl_io_mshrTask_bits_tagWen),
+    .io_mshrTask_bits_dsWen
+      (_mshrCtl_io_mshrTask_bits_dsWen),
+    .io_mshrTask_bits_replTask
+      (_mshrCtl_io_mshrTask_bits_replTask),
+    .io_mshrTask_bits_cmoTask
+      (_mshrCtl_io_mshrTask_bits_cmoTask),
+    .io_mshrTask_bits_reqSource
+      (_mshrCtl_io_mshrTask_bits_reqSource),
+    .io_mshrTask_bits_mergeA
+      (_mshrCtl_io_mshrTask_bits_mergeA),
+    .io_mshrTask_bits_aMergeTask_off
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_off),
+    .io_mshrTask_bits_aMergeTask_alias
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_alias),
+    .io_mshrTask_bits_aMergeTask_vaddr
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_vaddr),
+    .io_mshrTask_bits_aMergeTask_isKeyword
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_isKeyword),
+    .io_mshrTask_bits_aMergeTask_opcode
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_opcode),
+    .io_mshrTask_bits_aMergeTask_param
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_param),
+    .io_mshrTask_bits_aMergeTask_sourceId
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_sourceId),
+    .io_mshrTask_bits_aMergeTask_meta_dirty
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_dirty),
+    .io_mshrTask_bits_aMergeTask_meta_state
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_state),
+    .io_mshrTask_bits_aMergeTask_meta_clients
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_clients),
+    .io_mshrTask_bits_aMergeTask_meta_alias
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_alias),
+    .io_mshrTask_bits_aMergeTask_meta_accessed
+      (_mshrCtl_io_mshrTask_bits_aMergeTask_meta_accessed),
+    .io_mshrTask_bits_snpHitRelease
+      (_mshrCtl_io_mshrTask_bits_snpHitRelease),
+    .io_mshrTask_bits_snpHitReleaseToInval
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseToInval),
+    .io_mshrTask_bits_snpHitReleaseToClean
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseToClean),
+    .io_mshrTask_bits_snpHitReleaseWithData
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseWithData),
+    .io_mshrTask_bits_snpHitReleaseIdx
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseIdx),
+    .io_mshrTask_bits_snpHitReleaseMeta_dirty
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_dirty),
+    .io_mshrTask_bits_snpHitReleaseMeta_state
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_state),
+    .io_mshrTask_bits_snpHitReleaseMeta_clients
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_clients),
+    .io_mshrTask_bits_snpHitReleaseMeta_alias
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_alias),
+    .io_mshrTask_bits_snpHitReleaseMeta_prefetch
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_prefetch),
+    .io_mshrTask_bits_snpHitReleaseMeta_prefetchSrc
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_mshrTask_bits_snpHitReleaseMeta_accessed
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_accessed),
+    .io_mshrTask_bits_snpHitReleaseMeta_tagErr
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_tagErr),
+    .io_mshrTask_bits_snpHitReleaseMeta_dataErr
+      (_mshrCtl_io_mshrTask_bits_snpHitReleaseMeta_dataErr),
+    .io_mshrTask_bits_tgtID
+      (_mshrCtl_io_mshrTask_bits_tgtID),
+    .io_mshrTask_bits_txnID
+      (_mshrCtl_io_mshrTask_bits_txnID),
+    .io_mshrTask_bits_homeNID
+      (_mshrCtl_io_mshrTask_bits_homeNID),
+    .io_mshrTask_bits_dbID
+      (_mshrCtl_io_mshrTask_bits_dbID),
+    .io_mshrTask_bits_chiOpcode
+      (_mshrCtl_io_mshrTask_bits_chiOpcode),
+    .io_mshrTask_bits_resp
+      (_mshrCtl_io_mshrTask_bits_resp),
+    .io_mshrTask_bits_fwdState
+      (_mshrCtl_io_mshrTask_bits_fwdState),
+    .io_mshrTask_bits_retToSrc
+      (_mshrCtl_io_mshrTask_bits_retToSrc),
+    .io_mshrTask_bits_likelyshared
+      (_mshrCtl_io_mshrTask_bits_likelyshared),
+    .io_mshrTask_bits_expCompAck
+      (_mshrCtl_io_mshrTask_bits_expCompAck),
+    .io_mshrTask_bits_allowRetry
+      (_mshrCtl_io_mshrTask_bits_allowRetry),
+    .io_mshrTask_bits_memAttr_allocate
+      (_mshrCtl_io_mshrTask_bits_memAttr_allocate),
+    .io_mshrTask_bits_memAttr_cacheable
+      (_mshrCtl_io_mshrTask_bits_memAttr_cacheable),
+    .io_mshrTask_bits_memAttr_ewa
+      (_mshrCtl_io_mshrTask_bits_memAttr_ewa),
+    .io_mshrTask_bits_traceTag
+      (_mshrCtl_io_mshrTask_bits_traceTag),
+    .io_pipeStatusVec_0_valid
+      (_reqArb_io_status_vec_1_valid),
+    .io_pipeStatusVec_1_valid
+      (_mainPipe_io_status_vec_toD_0_valid),
+    .io_toTXREQ_ready
+      (_txreq_io_mshrReq_ready),
+    .io_toTXREQ_valid
+      (_mshrCtl_io_toTXREQ_valid),
+    .io_toTXREQ_bits_qos
+      (_mshrCtl_io_toTXREQ_bits_qos),
+    .io_toTXREQ_bits_tgtID
+      (_mshrCtl_io_toTXREQ_bits_tgtID),
+    .io_toTXREQ_bits_txnID
+      (_mshrCtl_io_toTXREQ_bits_txnID),
+    .io_toTXREQ_bits_opcode
+      (_mshrCtl_io_toTXREQ_bits_opcode),
+    .io_toTXREQ_bits_size
+      (_mshrCtl_io_toTXREQ_bits_size),
+    .io_toTXREQ_bits_addr
+      (_mshrCtl_io_toTXREQ_bits_addr),
+    .io_toTXREQ_bits_likelyshared
+      (_mshrCtl_io_toTXREQ_bits_likelyshared),
+    .io_toTXREQ_bits_allowRetry
+      (_mshrCtl_io_toTXREQ_bits_allowRetry),
+    .io_toTXREQ_bits_order
+      (_mshrCtl_io_toTXREQ_bits_order),
+    .io_toTXREQ_bits_pCrdType
+      (_mshrCtl_io_toTXREQ_bits_pCrdType),
+    .io_toTXREQ_bits_memAttr_allocate
+      (_mshrCtl_io_toTXREQ_bits_memAttr_allocate),
+    .io_toTXREQ_bits_memAttr_cacheable
+      (_mshrCtl_io_toTXREQ_bits_memAttr_cacheable),
+    .io_toTXREQ_bits_memAttr_device
+      (_mshrCtl_io_toTXREQ_bits_memAttr_device),
+    .io_toTXREQ_bits_memAttr_ewa
+      (_mshrCtl_io_toTXREQ_bits_memAttr_ewa),
+    .io_toTXREQ_bits_snpAttr
+      (_mshrCtl_io_toTXREQ_bits_snpAttr),
+    .io_toTXREQ_bits_expCompAck
+      (_mshrCtl_io_toTXREQ_bits_expCompAck),
+    .io_toTXRSP_ready
+      (_txrsp_io_mshrRsp_ready),
+    .io_toTXRSP_valid
+      (_mshrCtl_io_toTXRSP_valid),
+    .io_toTXRSP_bits_tgtID
+      (_mshrCtl_io_toTXRSP_bits_tgtID),
+    .io_toTXRSP_bits_txnID
+      (_mshrCtl_io_toTXRSP_bits_txnID),
+    .io_toTXRSP_bits_opcode
+      (_mshrCtl_io_toTXRSP_bits_opcode),
+    .io_toTXRSP_bits_traceTag
+      (_mshrCtl_io_toTXRSP_bits_traceTag),
+    .io_toSourceB_ready
+      (io_in_b_ready),
+    .io_toSourceB_valid
+      (io_in_b_valid),
+    .io_toSourceB_bits_opcode
+      (io_in_b_bits_opcode),
+    .io_toSourceB_bits_param
+      (io_in_b_bits_param),
+    .io_toSourceB_bits_address
+      (io_in_b_bits_address),
+    .io_toSourceB_bits_data
+      (io_in_b_bits_data),
+    .io_grantStatus_0_valid
+      (_grantBuf_io_grantStatus_0_valid),
+    .io_grantStatus_0_set
+      (_grantBuf_io_grantStatus_0_set),
+    .io_grantStatus_0_tag
+      (_grantBuf_io_grantStatus_0_tag),
+    .io_grantStatus_1_valid
+      (_grantBuf_io_grantStatus_1_valid),
+    .io_grantStatus_1_set
+      (_grantBuf_io_grantStatus_1_set),
+    .io_grantStatus_1_tag
+      (_grantBuf_io_grantStatus_1_tag),
+    .io_grantStatus_2_valid
+      (_grantBuf_io_grantStatus_2_valid),
+    .io_grantStatus_2_set
+      (_grantBuf_io_grantStatus_2_set),
+    .io_grantStatus_2_tag
+      (_grantBuf_io_grantStatus_2_tag),
+    .io_grantStatus_3_valid
+      (_grantBuf_io_grantStatus_3_valid),
+    .io_grantStatus_3_set
+      (_grantBuf_io_grantStatus_3_set),
+    .io_grantStatus_3_tag
+      (_grantBuf_io_grantStatus_3_tag),
+    .io_grantStatus_4_valid
+      (_grantBuf_io_grantStatus_4_valid),
+    .io_grantStatus_4_set
+      (_grantBuf_io_grantStatus_4_set),
+    .io_grantStatus_4_tag
+      (_grantBuf_io_grantStatus_4_tag),
+    .io_grantStatus_5_valid
+      (_grantBuf_io_grantStatus_5_valid),
+    .io_grantStatus_5_set
+      (_grantBuf_io_grantStatus_5_set),
+    .io_grantStatus_5_tag
+      (_grantBuf_io_grantStatus_5_tag),
+    .io_grantStatus_6_valid
+      (_grantBuf_io_grantStatus_6_valid),
+    .io_grantStatus_6_set
+      (_grantBuf_io_grantStatus_6_set),
+    .io_grantStatus_6_tag
+      (_grantBuf_io_grantStatus_6_tag),
+    .io_grantStatus_7_valid
+      (_grantBuf_io_grantStatus_7_valid),
+    .io_grantStatus_7_set
+      (_grantBuf_io_grantStatus_7_set),
+    .io_grantStatus_7_tag
+      (_grantBuf_io_grantStatus_7_tag),
+    .io_grantStatus_8_valid
+      (_grantBuf_io_grantStatus_8_valid),
+    .io_grantStatus_8_set
+      (_grantBuf_io_grantStatus_8_set),
+    .io_grantStatus_8_tag
+      (_grantBuf_io_grantStatus_8_tag),
+    .io_grantStatus_9_valid
+      (_grantBuf_io_grantStatus_9_valid),
+    .io_grantStatus_9_set
+      (_grantBuf_io_grantStatus_9_set),
+    .io_grantStatus_9_tag
+      (_grantBuf_io_grantStatus_9_tag),
+    .io_grantStatus_10_valid
+      (_grantBuf_io_grantStatus_10_valid),
+    .io_grantStatus_10_set
+      (_grantBuf_io_grantStatus_10_set),
+    .io_grantStatus_10_tag
+      (_grantBuf_io_grantStatus_10_tag),
+    .io_grantStatus_11_valid
+      (_grantBuf_io_grantStatus_11_valid),
+    .io_grantStatus_11_set
+      (_grantBuf_io_grantStatus_11_set),
+    .io_grantStatus_11_tag
+      (_grantBuf_io_grantStatus_11_tag),
+    .io_grantStatus_12_valid
+      (_grantBuf_io_grantStatus_12_valid),
+    .io_grantStatus_12_set
+      (_grantBuf_io_grantStatus_12_set),
+    .io_grantStatus_12_tag
+      (_grantBuf_io_grantStatus_12_tag),
+    .io_grantStatus_13_valid
+      (_grantBuf_io_grantStatus_13_valid),
+    .io_grantStatus_13_set
+      (_grantBuf_io_grantStatus_13_set),
+    .io_grantStatus_13_tag
+      (_grantBuf_io_grantStatus_13_tag),
+    .io_grantStatus_14_valid
+      (_grantBuf_io_grantStatus_14_valid),
+    .io_grantStatus_14_set
+      (_grantBuf_io_grantStatus_14_set),
+    .io_grantStatus_14_tag
+      (_grantBuf_io_grantStatus_14_tag),
+    .io_grantStatus_15_valid
+      (_grantBuf_io_grantStatus_15_valid),
+    .io_grantStatus_15_set
+      (_grantBuf_io_grantStatus_15_set),
+    .io_grantStatus_15_tag
+      (_grantBuf_io_grantStatus_15_tag),
+    .io_resps_sinkC_valid
+      (_sinkC_io_resp_valid),
+    .io_resps_sinkC_set
+      (_sinkC_io_resp_set),
+    .io_resps_sinkC_tag
+      (_sinkC_io_resp_tag),
+    .io_resps_sinkC_respInfo_opcode
+      (_sinkC_io_resp_respInfo_opcode),
+    .io_resps_sinkC_respInfo_param
+      (_sinkC_io_resp_respInfo_param),
+    .io_resps_sinkC_respInfo_last
+      (_sinkC_io_resp_respInfo_last),
+    .io_resps_sinkC_respInfo_denied
+      (_sinkC_io_resp_respInfo_denied),
+    .io_resps_sinkC_respInfo_corrupt
+      (_sinkC_io_resp_respInfo_corrupt),
+    .io_resps_rxrsp_valid
+      (_rxrsp_io_in_valid),
+    .io_resps_rxrsp_mshrId
+      (_rxrsp_io_in_mshrId),
+    .io_resps_rxrsp_respInfo_chiOpcode
+      (_rxrsp_io_in_respInfo_chiOpcode),
+    .io_resps_rxrsp_respInfo_srcID
+      (_rxrsp_io_in_respInfo_srcID),
+    .io_resps_rxrsp_respInfo_dbID
+      (_rxrsp_io_in_respInfo_dbID),
+    .io_resps_rxrsp_respInfo_resp
+      (_rxrsp_io_in_respInfo_resp),
+    .io_resps_rxrsp_respInfo_pCrdType
+      (_rxrsp_io_in_respInfo_pCrdType),
+    .io_resps_rxrsp_respInfo_respErr
+      (_rxrsp_io_in_respInfo_respErr),
+    .io_resps_rxrsp_respInfo_traceTag
+      (_rxrsp_io_in_respInfo_traceTag),
+    .io_resps_rxdat_valid
+      (_rxdat_io_in_valid),
+    .io_resps_rxdat_mshrId
+      (_rxdat_io_in_mshrId),
+    .io_resps_rxdat_respInfo_last
+      (_rxdat_io_in_respInfo_last),
+    .io_resps_rxdat_respInfo_corrupt
+      (_rxdat_io_in_respInfo_corrupt),
+    .io_resps_rxdat_respInfo_chiOpcode
+      (_rxdat_io_in_respInfo_chiOpcode),
+    .io_resps_rxdat_respInfo_homeNID
+      (_rxdat_io_in_respInfo_homeNID),
+    .io_resps_rxdat_respInfo_dbID
+      (_rxdat_io_in_respInfo_dbID),
+    .io_resps_rxdat_respInfo_resp
+      (_rxdat_io_in_respInfo_resp),
+    .io_resps_rxdat_respInfo_respErr
+      (_rxdat_io_in_respInfo_respErr),
+    .io_resps_rxdat_respInfo_traceTag
+      (_rxdat_io_in_respInfo_traceTag),
+    .io_releaseBufWriteId
+      (_mshrCtl_io_releaseBufWriteId),
+    .io_nestedwb_set
+      (_mainPipe_io_nestedwb_set),
+    .io_nestedwb_tag
+      (_mainPipe_io_nestedwb_tag),
+    .io_nestedwb_c_set_dirty
+      (_mainPipe_io_nestedwb_c_set_dirty),
+    .io_nestedwb_c_set_tip
+      (_mainPipe_io_nestedwb_c_set_tip),
+    .io_nestedwb_b_inv_dirty
+      (_mainPipe_io_nestedwb_b_inv_dirty),
+    .io_nestedwb_b_toB
+      (_mainPipe_io_nestedwb_b_toB),
+    .io_nestedwb_b_toN
+      (_mainPipe_io_nestedwb_b_toN),
+    .io_nestedwb_b_toClean
+      (_mainPipe_io_nestedwb_b_toClean),
+    .io_nestedwbDataId_valid
+      (_mshrCtl_io_nestedwbDataId_valid),
+    .io_nestedwbDataId_bits
+      (_mshrCtl_io_nestedwbDataId_bits),
+    .io_msInfo_0_valid
+      (_mshrCtl_io_msInfo_0_valid),
+    .io_msInfo_0_bits_channel
+      (_mshrCtl_io_msInfo_0_bits_channel),
+    .io_msInfo_0_bits_set
+      (_mshrCtl_io_msInfo_0_bits_set),
+    .io_msInfo_0_bits_way
+      (_mshrCtl_io_msInfo_0_bits_way),
+    .io_msInfo_0_bits_reqTag
+      (_mshrCtl_io_msInfo_0_bits_reqTag),
+    .io_msInfo_0_bits_reqSource
+      (_mshrCtl_io_msInfo_0_bits_reqSource),
+    .io_msInfo_0_bits_willFree
+      (_mshrCtl_io_msInfo_0_bits_willFree),
+    .io_msInfo_0_bits_aliasTask
+      (_mshrCtl_io_msInfo_0_bits_aliasTask),
+    .io_msInfo_0_bits_needRelease
+      (_mshrCtl_io_msInfo_0_bits_needRelease),
+    .io_msInfo_0_bits_blockRefill
+      (_mshrCtl_io_msInfo_0_bits_blockRefill),
+    .io_msInfo_0_bits_meta_dirty
+      (_mshrCtl_io_msInfo_0_bits_meta_dirty),
+    .io_msInfo_0_bits_meta_state
+      (_mshrCtl_io_msInfo_0_bits_meta_state),
+    .io_msInfo_0_bits_meta_clients
+      (_mshrCtl_io_msInfo_0_bits_meta_clients),
+    .io_msInfo_0_bits_meta_alias
+      (_mshrCtl_io_msInfo_0_bits_meta_alias),
+    .io_msInfo_0_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_0_bits_meta_prefetch),
+    .io_msInfo_0_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_0_bits_meta_prefetchSrc),
+    .io_msInfo_0_bits_meta_accessed
+      (_mshrCtl_io_msInfo_0_bits_meta_accessed),
+    .io_msInfo_0_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_0_bits_meta_tagErr),
+    .io_msInfo_0_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_0_bits_meta_dataErr),
+    .io_msInfo_0_bits_metaTag
+      (_mshrCtl_io_msInfo_0_bits_metaTag),
+    .io_msInfo_0_bits_dirHit
+      (_mshrCtl_io_msInfo_0_bits_dirHit),
+    .io_msInfo_0_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_0_bits_isAcqOrPrefetch),
+    .io_msInfo_0_bits_isPrefetch
+      (_mshrCtl_io_msInfo_0_bits_isPrefetch),
+    .io_msInfo_0_bits_param
+      (_mshrCtl_io_msInfo_0_bits_param),
+    .io_msInfo_0_bits_mergeA
+      (_mshrCtl_io_msInfo_0_bits_mergeA),
+    .io_msInfo_0_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_0_bits_w_grantfirst),
+    .io_msInfo_0_bits_w_grantlast
+      (_mshrCtl_io_msInfo_0_bits_w_grantlast),
+    .io_msInfo_0_bits_w_grant
+      (_mshrCtl_io_msInfo_0_bits_w_grant),
+    .io_msInfo_0_bits_s_release
+      (_mshrCtl_io_msInfo_0_bits_s_release),
+    .io_msInfo_0_bits_s_refill
+      (_mshrCtl_io_msInfo_0_bits_s_refill),
+    .io_msInfo_0_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_0_bits_s_cmoresp),
+    .io_msInfo_0_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_0_bits_s_cmometaw),
+    .io_msInfo_0_bits_w_releaseack
+      (_mshrCtl_io_msInfo_0_bits_w_releaseack),
+    .io_msInfo_0_bits_w_replResp
+      (_mshrCtl_io_msInfo_0_bits_w_replResp),
+    .io_msInfo_0_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_0_bits_w_rprobeacklast),
+    .io_msInfo_0_bits_replaceData
+      (_mshrCtl_io_msInfo_0_bits_replaceData),
+    .io_msInfo_0_bits_releaseToClean
+      (_mshrCtl_io_msInfo_0_bits_releaseToClean),
+    .io_msInfo_1_valid
+      (_mshrCtl_io_msInfo_1_valid),
+    .io_msInfo_1_bits_channel
+      (_mshrCtl_io_msInfo_1_bits_channel),
+    .io_msInfo_1_bits_set
+      (_mshrCtl_io_msInfo_1_bits_set),
+    .io_msInfo_1_bits_way
+      (_mshrCtl_io_msInfo_1_bits_way),
+    .io_msInfo_1_bits_reqTag
+      (_mshrCtl_io_msInfo_1_bits_reqTag),
+    .io_msInfo_1_bits_reqSource
+      (_mshrCtl_io_msInfo_1_bits_reqSource),
+    .io_msInfo_1_bits_willFree
+      (_mshrCtl_io_msInfo_1_bits_willFree),
+    .io_msInfo_1_bits_aliasTask
+      (_mshrCtl_io_msInfo_1_bits_aliasTask),
+    .io_msInfo_1_bits_needRelease
+      (_mshrCtl_io_msInfo_1_bits_needRelease),
+    .io_msInfo_1_bits_blockRefill
+      (_mshrCtl_io_msInfo_1_bits_blockRefill),
+    .io_msInfo_1_bits_meta_dirty
+      (_mshrCtl_io_msInfo_1_bits_meta_dirty),
+    .io_msInfo_1_bits_meta_state
+      (_mshrCtl_io_msInfo_1_bits_meta_state),
+    .io_msInfo_1_bits_meta_clients
+      (_mshrCtl_io_msInfo_1_bits_meta_clients),
+    .io_msInfo_1_bits_meta_alias
+      (_mshrCtl_io_msInfo_1_bits_meta_alias),
+    .io_msInfo_1_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_1_bits_meta_prefetch),
+    .io_msInfo_1_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_1_bits_meta_prefetchSrc),
+    .io_msInfo_1_bits_meta_accessed
+      (_mshrCtl_io_msInfo_1_bits_meta_accessed),
+    .io_msInfo_1_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_1_bits_meta_tagErr),
+    .io_msInfo_1_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_1_bits_meta_dataErr),
+    .io_msInfo_1_bits_metaTag
+      (_mshrCtl_io_msInfo_1_bits_metaTag),
+    .io_msInfo_1_bits_dirHit
+      (_mshrCtl_io_msInfo_1_bits_dirHit),
+    .io_msInfo_1_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_1_bits_isAcqOrPrefetch),
+    .io_msInfo_1_bits_isPrefetch
+      (_mshrCtl_io_msInfo_1_bits_isPrefetch),
+    .io_msInfo_1_bits_param
+      (_mshrCtl_io_msInfo_1_bits_param),
+    .io_msInfo_1_bits_mergeA
+      (_mshrCtl_io_msInfo_1_bits_mergeA),
+    .io_msInfo_1_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_1_bits_w_grantfirst),
+    .io_msInfo_1_bits_w_grantlast
+      (_mshrCtl_io_msInfo_1_bits_w_grantlast),
+    .io_msInfo_1_bits_w_grant
+      (_mshrCtl_io_msInfo_1_bits_w_grant),
+    .io_msInfo_1_bits_s_release
+      (_mshrCtl_io_msInfo_1_bits_s_release),
+    .io_msInfo_1_bits_s_refill
+      (_mshrCtl_io_msInfo_1_bits_s_refill),
+    .io_msInfo_1_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_1_bits_s_cmoresp),
+    .io_msInfo_1_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_1_bits_s_cmometaw),
+    .io_msInfo_1_bits_w_releaseack
+      (_mshrCtl_io_msInfo_1_bits_w_releaseack),
+    .io_msInfo_1_bits_w_replResp
+      (_mshrCtl_io_msInfo_1_bits_w_replResp),
+    .io_msInfo_1_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_1_bits_w_rprobeacklast),
+    .io_msInfo_1_bits_replaceData
+      (_mshrCtl_io_msInfo_1_bits_replaceData),
+    .io_msInfo_1_bits_releaseToClean
+      (_mshrCtl_io_msInfo_1_bits_releaseToClean),
+    .io_msInfo_2_valid
+      (_mshrCtl_io_msInfo_2_valid),
+    .io_msInfo_2_bits_channel
+      (_mshrCtl_io_msInfo_2_bits_channel),
+    .io_msInfo_2_bits_set
+      (_mshrCtl_io_msInfo_2_bits_set),
+    .io_msInfo_2_bits_way
+      (_mshrCtl_io_msInfo_2_bits_way),
+    .io_msInfo_2_bits_reqTag
+      (_mshrCtl_io_msInfo_2_bits_reqTag),
+    .io_msInfo_2_bits_reqSource
+      (_mshrCtl_io_msInfo_2_bits_reqSource),
+    .io_msInfo_2_bits_willFree
+      (_mshrCtl_io_msInfo_2_bits_willFree),
+    .io_msInfo_2_bits_aliasTask
+      (_mshrCtl_io_msInfo_2_bits_aliasTask),
+    .io_msInfo_2_bits_needRelease
+      (_mshrCtl_io_msInfo_2_bits_needRelease),
+    .io_msInfo_2_bits_blockRefill
+      (_mshrCtl_io_msInfo_2_bits_blockRefill),
+    .io_msInfo_2_bits_meta_dirty
+      (_mshrCtl_io_msInfo_2_bits_meta_dirty),
+    .io_msInfo_2_bits_meta_state
+      (_mshrCtl_io_msInfo_2_bits_meta_state),
+    .io_msInfo_2_bits_meta_clients
+      (_mshrCtl_io_msInfo_2_bits_meta_clients),
+    .io_msInfo_2_bits_meta_alias
+      (_mshrCtl_io_msInfo_2_bits_meta_alias),
+    .io_msInfo_2_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_2_bits_meta_prefetch),
+    .io_msInfo_2_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_2_bits_meta_prefetchSrc),
+    .io_msInfo_2_bits_meta_accessed
+      (_mshrCtl_io_msInfo_2_bits_meta_accessed),
+    .io_msInfo_2_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_2_bits_meta_tagErr),
+    .io_msInfo_2_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_2_bits_meta_dataErr),
+    .io_msInfo_2_bits_metaTag
+      (_mshrCtl_io_msInfo_2_bits_metaTag),
+    .io_msInfo_2_bits_dirHit
+      (_mshrCtl_io_msInfo_2_bits_dirHit),
+    .io_msInfo_2_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_2_bits_isAcqOrPrefetch),
+    .io_msInfo_2_bits_isPrefetch
+      (_mshrCtl_io_msInfo_2_bits_isPrefetch),
+    .io_msInfo_2_bits_param
+      (_mshrCtl_io_msInfo_2_bits_param),
+    .io_msInfo_2_bits_mergeA
+      (_mshrCtl_io_msInfo_2_bits_mergeA),
+    .io_msInfo_2_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_2_bits_w_grantfirst),
+    .io_msInfo_2_bits_w_grantlast
+      (_mshrCtl_io_msInfo_2_bits_w_grantlast),
+    .io_msInfo_2_bits_w_grant
+      (_mshrCtl_io_msInfo_2_bits_w_grant),
+    .io_msInfo_2_bits_s_release
+      (_mshrCtl_io_msInfo_2_bits_s_release),
+    .io_msInfo_2_bits_s_refill
+      (_mshrCtl_io_msInfo_2_bits_s_refill),
+    .io_msInfo_2_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_2_bits_s_cmoresp),
+    .io_msInfo_2_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_2_bits_s_cmometaw),
+    .io_msInfo_2_bits_w_releaseack
+      (_mshrCtl_io_msInfo_2_bits_w_releaseack),
+    .io_msInfo_2_bits_w_replResp
+      (_mshrCtl_io_msInfo_2_bits_w_replResp),
+    .io_msInfo_2_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_2_bits_w_rprobeacklast),
+    .io_msInfo_2_bits_replaceData
+      (_mshrCtl_io_msInfo_2_bits_replaceData),
+    .io_msInfo_2_bits_releaseToClean
+      (_mshrCtl_io_msInfo_2_bits_releaseToClean),
+    .io_msInfo_3_valid
+      (_mshrCtl_io_msInfo_3_valid),
+    .io_msInfo_3_bits_channel
+      (_mshrCtl_io_msInfo_3_bits_channel),
+    .io_msInfo_3_bits_set
+      (_mshrCtl_io_msInfo_3_bits_set),
+    .io_msInfo_3_bits_way
+      (_mshrCtl_io_msInfo_3_bits_way),
+    .io_msInfo_3_bits_reqTag
+      (_mshrCtl_io_msInfo_3_bits_reqTag),
+    .io_msInfo_3_bits_reqSource
+      (_mshrCtl_io_msInfo_3_bits_reqSource),
+    .io_msInfo_3_bits_willFree
+      (_mshrCtl_io_msInfo_3_bits_willFree),
+    .io_msInfo_3_bits_aliasTask
+      (_mshrCtl_io_msInfo_3_bits_aliasTask),
+    .io_msInfo_3_bits_needRelease
+      (_mshrCtl_io_msInfo_3_bits_needRelease),
+    .io_msInfo_3_bits_blockRefill
+      (_mshrCtl_io_msInfo_3_bits_blockRefill),
+    .io_msInfo_3_bits_meta_dirty
+      (_mshrCtl_io_msInfo_3_bits_meta_dirty),
+    .io_msInfo_3_bits_meta_state
+      (_mshrCtl_io_msInfo_3_bits_meta_state),
+    .io_msInfo_3_bits_meta_clients
+      (_mshrCtl_io_msInfo_3_bits_meta_clients),
+    .io_msInfo_3_bits_meta_alias
+      (_mshrCtl_io_msInfo_3_bits_meta_alias),
+    .io_msInfo_3_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_3_bits_meta_prefetch),
+    .io_msInfo_3_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_3_bits_meta_prefetchSrc),
+    .io_msInfo_3_bits_meta_accessed
+      (_mshrCtl_io_msInfo_3_bits_meta_accessed),
+    .io_msInfo_3_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_3_bits_meta_tagErr),
+    .io_msInfo_3_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_3_bits_meta_dataErr),
+    .io_msInfo_3_bits_metaTag
+      (_mshrCtl_io_msInfo_3_bits_metaTag),
+    .io_msInfo_3_bits_dirHit
+      (_mshrCtl_io_msInfo_3_bits_dirHit),
+    .io_msInfo_3_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_3_bits_isAcqOrPrefetch),
+    .io_msInfo_3_bits_isPrefetch
+      (_mshrCtl_io_msInfo_3_bits_isPrefetch),
+    .io_msInfo_3_bits_param
+      (_mshrCtl_io_msInfo_3_bits_param),
+    .io_msInfo_3_bits_mergeA
+      (_mshrCtl_io_msInfo_3_bits_mergeA),
+    .io_msInfo_3_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_3_bits_w_grantfirst),
+    .io_msInfo_3_bits_w_grantlast
+      (_mshrCtl_io_msInfo_3_bits_w_grantlast),
+    .io_msInfo_3_bits_w_grant
+      (_mshrCtl_io_msInfo_3_bits_w_grant),
+    .io_msInfo_3_bits_s_release
+      (_mshrCtl_io_msInfo_3_bits_s_release),
+    .io_msInfo_3_bits_s_refill
+      (_mshrCtl_io_msInfo_3_bits_s_refill),
+    .io_msInfo_3_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_3_bits_s_cmoresp),
+    .io_msInfo_3_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_3_bits_s_cmometaw),
+    .io_msInfo_3_bits_w_releaseack
+      (_mshrCtl_io_msInfo_3_bits_w_releaseack),
+    .io_msInfo_3_bits_w_replResp
+      (_mshrCtl_io_msInfo_3_bits_w_replResp),
+    .io_msInfo_3_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_3_bits_w_rprobeacklast),
+    .io_msInfo_3_bits_replaceData
+      (_mshrCtl_io_msInfo_3_bits_replaceData),
+    .io_msInfo_3_bits_releaseToClean
+      (_mshrCtl_io_msInfo_3_bits_releaseToClean),
+    .io_msInfo_4_valid
+      (_mshrCtl_io_msInfo_4_valid),
+    .io_msInfo_4_bits_channel
+      (_mshrCtl_io_msInfo_4_bits_channel),
+    .io_msInfo_4_bits_set
+      (_mshrCtl_io_msInfo_4_bits_set),
+    .io_msInfo_4_bits_way
+      (_mshrCtl_io_msInfo_4_bits_way),
+    .io_msInfo_4_bits_reqTag
+      (_mshrCtl_io_msInfo_4_bits_reqTag),
+    .io_msInfo_4_bits_reqSource
+      (_mshrCtl_io_msInfo_4_bits_reqSource),
+    .io_msInfo_4_bits_willFree
+      (_mshrCtl_io_msInfo_4_bits_willFree),
+    .io_msInfo_4_bits_aliasTask
+      (_mshrCtl_io_msInfo_4_bits_aliasTask),
+    .io_msInfo_4_bits_needRelease
+      (_mshrCtl_io_msInfo_4_bits_needRelease),
+    .io_msInfo_4_bits_blockRefill
+      (_mshrCtl_io_msInfo_4_bits_blockRefill),
+    .io_msInfo_4_bits_meta_dirty
+      (_mshrCtl_io_msInfo_4_bits_meta_dirty),
+    .io_msInfo_4_bits_meta_state
+      (_mshrCtl_io_msInfo_4_bits_meta_state),
+    .io_msInfo_4_bits_meta_clients
+      (_mshrCtl_io_msInfo_4_bits_meta_clients),
+    .io_msInfo_4_bits_meta_alias
+      (_mshrCtl_io_msInfo_4_bits_meta_alias),
+    .io_msInfo_4_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_4_bits_meta_prefetch),
+    .io_msInfo_4_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_4_bits_meta_prefetchSrc),
+    .io_msInfo_4_bits_meta_accessed
+      (_mshrCtl_io_msInfo_4_bits_meta_accessed),
+    .io_msInfo_4_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_4_bits_meta_tagErr),
+    .io_msInfo_4_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_4_bits_meta_dataErr),
+    .io_msInfo_4_bits_metaTag
+      (_mshrCtl_io_msInfo_4_bits_metaTag),
+    .io_msInfo_4_bits_dirHit
+      (_mshrCtl_io_msInfo_4_bits_dirHit),
+    .io_msInfo_4_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_4_bits_isAcqOrPrefetch),
+    .io_msInfo_4_bits_isPrefetch
+      (_mshrCtl_io_msInfo_4_bits_isPrefetch),
+    .io_msInfo_4_bits_param
+      (_mshrCtl_io_msInfo_4_bits_param),
+    .io_msInfo_4_bits_mergeA
+      (_mshrCtl_io_msInfo_4_bits_mergeA),
+    .io_msInfo_4_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_4_bits_w_grantfirst),
+    .io_msInfo_4_bits_w_grantlast
+      (_mshrCtl_io_msInfo_4_bits_w_grantlast),
+    .io_msInfo_4_bits_w_grant
+      (_mshrCtl_io_msInfo_4_bits_w_grant),
+    .io_msInfo_4_bits_s_release
+      (_mshrCtl_io_msInfo_4_bits_s_release),
+    .io_msInfo_4_bits_s_refill
+      (_mshrCtl_io_msInfo_4_bits_s_refill),
+    .io_msInfo_4_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_4_bits_s_cmoresp),
+    .io_msInfo_4_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_4_bits_s_cmometaw),
+    .io_msInfo_4_bits_w_releaseack
+      (_mshrCtl_io_msInfo_4_bits_w_releaseack),
+    .io_msInfo_4_bits_w_replResp
+      (_mshrCtl_io_msInfo_4_bits_w_replResp),
+    .io_msInfo_4_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_4_bits_w_rprobeacklast),
+    .io_msInfo_4_bits_replaceData
+      (_mshrCtl_io_msInfo_4_bits_replaceData),
+    .io_msInfo_4_bits_releaseToClean
+      (_mshrCtl_io_msInfo_4_bits_releaseToClean),
+    .io_msInfo_5_valid
+      (_mshrCtl_io_msInfo_5_valid),
+    .io_msInfo_5_bits_channel
+      (_mshrCtl_io_msInfo_5_bits_channel),
+    .io_msInfo_5_bits_set
+      (_mshrCtl_io_msInfo_5_bits_set),
+    .io_msInfo_5_bits_way
+      (_mshrCtl_io_msInfo_5_bits_way),
+    .io_msInfo_5_bits_reqTag
+      (_mshrCtl_io_msInfo_5_bits_reqTag),
+    .io_msInfo_5_bits_reqSource
+      (_mshrCtl_io_msInfo_5_bits_reqSource),
+    .io_msInfo_5_bits_willFree
+      (_mshrCtl_io_msInfo_5_bits_willFree),
+    .io_msInfo_5_bits_aliasTask
+      (_mshrCtl_io_msInfo_5_bits_aliasTask),
+    .io_msInfo_5_bits_needRelease
+      (_mshrCtl_io_msInfo_5_bits_needRelease),
+    .io_msInfo_5_bits_blockRefill
+      (_mshrCtl_io_msInfo_5_bits_blockRefill),
+    .io_msInfo_5_bits_meta_dirty
+      (_mshrCtl_io_msInfo_5_bits_meta_dirty),
+    .io_msInfo_5_bits_meta_state
+      (_mshrCtl_io_msInfo_5_bits_meta_state),
+    .io_msInfo_5_bits_meta_clients
+      (_mshrCtl_io_msInfo_5_bits_meta_clients),
+    .io_msInfo_5_bits_meta_alias
+      (_mshrCtl_io_msInfo_5_bits_meta_alias),
+    .io_msInfo_5_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_5_bits_meta_prefetch),
+    .io_msInfo_5_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_5_bits_meta_prefetchSrc),
+    .io_msInfo_5_bits_meta_accessed
+      (_mshrCtl_io_msInfo_5_bits_meta_accessed),
+    .io_msInfo_5_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_5_bits_meta_tagErr),
+    .io_msInfo_5_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_5_bits_meta_dataErr),
+    .io_msInfo_5_bits_metaTag
+      (_mshrCtl_io_msInfo_5_bits_metaTag),
+    .io_msInfo_5_bits_dirHit
+      (_mshrCtl_io_msInfo_5_bits_dirHit),
+    .io_msInfo_5_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_5_bits_isAcqOrPrefetch),
+    .io_msInfo_5_bits_isPrefetch
+      (_mshrCtl_io_msInfo_5_bits_isPrefetch),
+    .io_msInfo_5_bits_param
+      (_mshrCtl_io_msInfo_5_bits_param),
+    .io_msInfo_5_bits_mergeA
+      (_mshrCtl_io_msInfo_5_bits_mergeA),
+    .io_msInfo_5_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_5_bits_w_grantfirst),
+    .io_msInfo_5_bits_w_grantlast
+      (_mshrCtl_io_msInfo_5_bits_w_grantlast),
+    .io_msInfo_5_bits_w_grant
+      (_mshrCtl_io_msInfo_5_bits_w_grant),
+    .io_msInfo_5_bits_s_release
+      (_mshrCtl_io_msInfo_5_bits_s_release),
+    .io_msInfo_5_bits_s_refill
+      (_mshrCtl_io_msInfo_5_bits_s_refill),
+    .io_msInfo_5_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_5_bits_s_cmoresp),
+    .io_msInfo_5_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_5_bits_s_cmometaw),
+    .io_msInfo_5_bits_w_releaseack
+      (_mshrCtl_io_msInfo_5_bits_w_releaseack),
+    .io_msInfo_5_bits_w_replResp
+      (_mshrCtl_io_msInfo_5_bits_w_replResp),
+    .io_msInfo_5_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_5_bits_w_rprobeacklast),
+    .io_msInfo_5_bits_replaceData
+      (_mshrCtl_io_msInfo_5_bits_replaceData),
+    .io_msInfo_5_bits_releaseToClean
+      (_mshrCtl_io_msInfo_5_bits_releaseToClean),
+    .io_msInfo_6_valid
+      (_mshrCtl_io_msInfo_6_valid),
+    .io_msInfo_6_bits_channel
+      (_mshrCtl_io_msInfo_6_bits_channel),
+    .io_msInfo_6_bits_set
+      (_mshrCtl_io_msInfo_6_bits_set),
+    .io_msInfo_6_bits_way
+      (_mshrCtl_io_msInfo_6_bits_way),
+    .io_msInfo_6_bits_reqTag
+      (_mshrCtl_io_msInfo_6_bits_reqTag),
+    .io_msInfo_6_bits_reqSource
+      (_mshrCtl_io_msInfo_6_bits_reqSource),
+    .io_msInfo_6_bits_willFree
+      (_mshrCtl_io_msInfo_6_bits_willFree),
+    .io_msInfo_6_bits_aliasTask
+      (_mshrCtl_io_msInfo_6_bits_aliasTask),
+    .io_msInfo_6_bits_needRelease
+      (_mshrCtl_io_msInfo_6_bits_needRelease),
+    .io_msInfo_6_bits_blockRefill
+      (_mshrCtl_io_msInfo_6_bits_blockRefill),
+    .io_msInfo_6_bits_meta_dirty
+      (_mshrCtl_io_msInfo_6_bits_meta_dirty),
+    .io_msInfo_6_bits_meta_state
+      (_mshrCtl_io_msInfo_6_bits_meta_state),
+    .io_msInfo_6_bits_meta_clients
+      (_mshrCtl_io_msInfo_6_bits_meta_clients),
+    .io_msInfo_6_bits_meta_alias
+      (_mshrCtl_io_msInfo_6_bits_meta_alias),
+    .io_msInfo_6_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_6_bits_meta_prefetch),
+    .io_msInfo_6_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_6_bits_meta_prefetchSrc),
+    .io_msInfo_6_bits_meta_accessed
+      (_mshrCtl_io_msInfo_6_bits_meta_accessed),
+    .io_msInfo_6_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_6_bits_meta_tagErr),
+    .io_msInfo_6_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_6_bits_meta_dataErr),
+    .io_msInfo_6_bits_metaTag
+      (_mshrCtl_io_msInfo_6_bits_metaTag),
+    .io_msInfo_6_bits_dirHit
+      (_mshrCtl_io_msInfo_6_bits_dirHit),
+    .io_msInfo_6_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_6_bits_isAcqOrPrefetch),
+    .io_msInfo_6_bits_isPrefetch
+      (_mshrCtl_io_msInfo_6_bits_isPrefetch),
+    .io_msInfo_6_bits_param
+      (_mshrCtl_io_msInfo_6_bits_param),
+    .io_msInfo_6_bits_mergeA
+      (_mshrCtl_io_msInfo_6_bits_mergeA),
+    .io_msInfo_6_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_6_bits_w_grantfirst),
+    .io_msInfo_6_bits_w_grantlast
+      (_mshrCtl_io_msInfo_6_bits_w_grantlast),
+    .io_msInfo_6_bits_w_grant
+      (_mshrCtl_io_msInfo_6_bits_w_grant),
+    .io_msInfo_6_bits_s_release
+      (_mshrCtl_io_msInfo_6_bits_s_release),
+    .io_msInfo_6_bits_s_refill
+      (_mshrCtl_io_msInfo_6_bits_s_refill),
+    .io_msInfo_6_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_6_bits_s_cmoresp),
+    .io_msInfo_6_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_6_bits_s_cmometaw),
+    .io_msInfo_6_bits_w_releaseack
+      (_mshrCtl_io_msInfo_6_bits_w_releaseack),
+    .io_msInfo_6_bits_w_replResp
+      (_mshrCtl_io_msInfo_6_bits_w_replResp),
+    .io_msInfo_6_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_6_bits_w_rprobeacklast),
+    .io_msInfo_6_bits_replaceData
+      (_mshrCtl_io_msInfo_6_bits_replaceData),
+    .io_msInfo_6_bits_releaseToClean
+      (_mshrCtl_io_msInfo_6_bits_releaseToClean),
+    .io_msInfo_7_valid
+      (_mshrCtl_io_msInfo_7_valid),
+    .io_msInfo_7_bits_channel
+      (_mshrCtl_io_msInfo_7_bits_channel),
+    .io_msInfo_7_bits_set
+      (_mshrCtl_io_msInfo_7_bits_set),
+    .io_msInfo_7_bits_way
+      (_mshrCtl_io_msInfo_7_bits_way),
+    .io_msInfo_7_bits_reqTag
+      (_mshrCtl_io_msInfo_7_bits_reqTag),
+    .io_msInfo_7_bits_reqSource
+      (_mshrCtl_io_msInfo_7_bits_reqSource),
+    .io_msInfo_7_bits_willFree
+      (_mshrCtl_io_msInfo_7_bits_willFree),
+    .io_msInfo_7_bits_aliasTask
+      (_mshrCtl_io_msInfo_7_bits_aliasTask),
+    .io_msInfo_7_bits_needRelease
+      (_mshrCtl_io_msInfo_7_bits_needRelease),
+    .io_msInfo_7_bits_blockRefill
+      (_mshrCtl_io_msInfo_7_bits_blockRefill),
+    .io_msInfo_7_bits_meta_dirty
+      (_mshrCtl_io_msInfo_7_bits_meta_dirty),
+    .io_msInfo_7_bits_meta_state
+      (_mshrCtl_io_msInfo_7_bits_meta_state),
+    .io_msInfo_7_bits_meta_clients
+      (_mshrCtl_io_msInfo_7_bits_meta_clients),
+    .io_msInfo_7_bits_meta_alias
+      (_mshrCtl_io_msInfo_7_bits_meta_alias),
+    .io_msInfo_7_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_7_bits_meta_prefetch),
+    .io_msInfo_7_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_7_bits_meta_prefetchSrc),
+    .io_msInfo_7_bits_meta_accessed
+      (_mshrCtl_io_msInfo_7_bits_meta_accessed),
+    .io_msInfo_7_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_7_bits_meta_tagErr),
+    .io_msInfo_7_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_7_bits_meta_dataErr),
+    .io_msInfo_7_bits_metaTag
+      (_mshrCtl_io_msInfo_7_bits_metaTag),
+    .io_msInfo_7_bits_dirHit
+      (_mshrCtl_io_msInfo_7_bits_dirHit),
+    .io_msInfo_7_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_7_bits_isAcqOrPrefetch),
+    .io_msInfo_7_bits_isPrefetch
+      (_mshrCtl_io_msInfo_7_bits_isPrefetch),
+    .io_msInfo_7_bits_param
+      (_mshrCtl_io_msInfo_7_bits_param),
+    .io_msInfo_7_bits_mergeA
+      (_mshrCtl_io_msInfo_7_bits_mergeA),
+    .io_msInfo_7_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_7_bits_w_grantfirst),
+    .io_msInfo_7_bits_w_grantlast
+      (_mshrCtl_io_msInfo_7_bits_w_grantlast),
+    .io_msInfo_7_bits_w_grant
+      (_mshrCtl_io_msInfo_7_bits_w_grant),
+    .io_msInfo_7_bits_s_release
+      (_mshrCtl_io_msInfo_7_bits_s_release),
+    .io_msInfo_7_bits_s_refill
+      (_mshrCtl_io_msInfo_7_bits_s_refill),
+    .io_msInfo_7_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_7_bits_s_cmoresp),
+    .io_msInfo_7_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_7_bits_s_cmometaw),
+    .io_msInfo_7_bits_w_releaseack
+      (_mshrCtl_io_msInfo_7_bits_w_releaseack),
+    .io_msInfo_7_bits_w_replResp
+      (_mshrCtl_io_msInfo_7_bits_w_replResp),
+    .io_msInfo_7_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_7_bits_w_rprobeacklast),
+    .io_msInfo_7_bits_replaceData
+      (_mshrCtl_io_msInfo_7_bits_replaceData),
+    .io_msInfo_7_bits_releaseToClean
+      (_mshrCtl_io_msInfo_7_bits_releaseToClean),
+    .io_msInfo_8_valid
+      (_mshrCtl_io_msInfo_8_valid),
+    .io_msInfo_8_bits_channel
+      (_mshrCtl_io_msInfo_8_bits_channel),
+    .io_msInfo_8_bits_set
+      (_mshrCtl_io_msInfo_8_bits_set),
+    .io_msInfo_8_bits_way
+      (_mshrCtl_io_msInfo_8_bits_way),
+    .io_msInfo_8_bits_reqTag
+      (_mshrCtl_io_msInfo_8_bits_reqTag),
+    .io_msInfo_8_bits_reqSource
+      (_mshrCtl_io_msInfo_8_bits_reqSource),
+    .io_msInfo_8_bits_willFree
+      (_mshrCtl_io_msInfo_8_bits_willFree),
+    .io_msInfo_8_bits_aliasTask
+      (_mshrCtl_io_msInfo_8_bits_aliasTask),
+    .io_msInfo_8_bits_needRelease
+      (_mshrCtl_io_msInfo_8_bits_needRelease),
+    .io_msInfo_8_bits_blockRefill
+      (_mshrCtl_io_msInfo_8_bits_blockRefill),
+    .io_msInfo_8_bits_meta_dirty
+      (_mshrCtl_io_msInfo_8_bits_meta_dirty),
+    .io_msInfo_8_bits_meta_state
+      (_mshrCtl_io_msInfo_8_bits_meta_state),
+    .io_msInfo_8_bits_meta_clients
+      (_mshrCtl_io_msInfo_8_bits_meta_clients),
+    .io_msInfo_8_bits_meta_alias
+      (_mshrCtl_io_msInfo_8_bits_meta_alias),
+    .io_msInfo_8_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_8_bits_meta_prefetch),
+    .io_msInfo_8_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_8_bits_meta_prefetchSrc),
+    .io_msInfo_8_bits_meta_accessed
+      (_mshrCtl_io_msInfo_8_bits_meta_accessed),
+    .io_msInfo_8_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_8_bits_meta_tagErr),
+    .io_msInfo_8_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_8_bits_meta_dataErr),
+    .io_msInfo_8_bits_metaTag
+      (_mshrCtl_io_msInfo_8_bits_metaTag),
+    .io_msInfo_8_bits_dirHit
+      (_mshrCtl_io_msInfo_8_bits_dirHit),
+    .io_msInfo_8_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_8_bits_isAcqOrPrefetch),
+    .io_msInfo_8_bits_isPrefetch
+      (_mshrCtl_io_msInfo_8_bits_isPrefetch),
+    .io_msInfo_8_bits_param
+      (_mshrCtl_io_msInfo_8_bits_param),
+    .io_msInfo_8_bits_mergeA
+      (_mshrCtl_io_msInfo_8_bits_mergeA),
+    .io_msInfo_8_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_8_bits_w_grantfirst),
+    .io_msInfo_8_bits_w_grantlast
+      (_mshrCtl_io_msInfo_8_bits_w_grantlast),
+    .io_msInfo_8_bits_w_grant
+      (_mshrCtl_io_msInfo_8_bits_w_grant),
+    .io_msInfo_8_bits_s_release
+      (_mshrCtl_io_msInfo_8_bits_s_release),
+    .io_msInfo_8_bits_s_refill
+      (_mshrCtl_io_msInfo_8_bits_s_refill),
+    .io_msInfo_8_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_8_bits_s_cmoresp),
+    .io_msInfo_8_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_8_bits_s_cmometaw),
+    .io_msInfo_8_bits_w_releaseack
+      (_mshrCtl_io_msInfo_8_bits_w_releaseack),
+    .io_msInfo_8_bits_w_replResp
+      (_mshrCtl_io_msInfo_8_bits_w_replResp),
+    .io_msInfo_8_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_8_bits_w_rprobeacklast),
+    .io_msInfo_8_bits_replaceData
+      (_mshrCtl_io_msInfo_8_bits_replaceData),
+    .io_msInfo_8_bits_releaseToClean
+      (_mshrCtl_io_msInfo_8_bits_releaseToClean),
+    .io_msInfo_9_valid
+      (_mshrCtl_io_msInfo_9_valid),
+    .io_msInfo_9_bits_channel
+      (_mshrCtl_io_msInfo_9_bits_channel),
+    .io_msInfo_9_bits_set
+      (_mshrCtl_io_msInfo_9_bits_set),
+    .io_msInfo_9_bits_way
+      (_mshrCtl_io_msInfo_9_bits_way),
+    .io_msInfo_9_bits_reqTag
+      (_mshrCtl_io_msInfo_9_bits_reqTag),
+    .io_msInfo_9_bits_reqSource
+      (_mshrCtl_io_msInfo_9_bits_reqSource),
+    .io_msInfo_9_bits_willFree
+      (_mshrCtl_io_msInfo_9_bits_willFree),
+    .io_msInfo_9_bits_aliasTask
+      (_mshrCtl_io_msInfo_9_bits_aliasTask),
+    .io_msInfo_9_bits_needRelease
+      (_mshrCtl_io_msInfo_9_bits_needRelease),
+    .io_msInfo_9_bits_blockRefill
+      (_mshrCtl_io_msInfo_9_bits_blockRefill),
+    .io_msInfo_9_bits_meta_dirty
+      (_mshrCtl_io_msInfo_9_bits_meta_dirty),
+    .io_msInfo_9_bits_meta_state
+      (_mshrCtl_io_msInfo_9_bits_meta_state),
+    .io_msInfo_9_bits_meta_clients
+      (_mshrCtl_io_msInfo_9_bits_meta_clients),
+    .io_msInfo_9_bits_meta_alias
+      (_mshrCtl_io_msInfo_9_bits_meta_alias),
+    .io_msInfo_9_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_9_bits_meta_prefetch),
+    .io_msInfo_9_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_9_bits_meta_prefetchSrc),
+    .io_msInfo_9_bits_meta_accessed
+      (_mshrCtl_io_msInfo_9_bits_meta_accessed),
+    .io_msInfo_9_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_9_bits_meta_tagErr),
+    .io_msInfo_9_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_9_bits_meta_dataErr),
+    .io_msInfo_9_bits_metaTag
+      (_mshrCtl_io_msInfo_9_bits_metaTag),
+    .io_msInfo_9_bits_dirHit
+      (_mshrCtl_io_msInfo_9_bits_dirHit),
+    .io_msInfo_9_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_9_bits_isAcqOrPrefetch),
+    .io_msInfo_9_bits_isPrefetch
+      (_mshrCtl_io_msInfo_9_bits_isPrefetch),
+    .io_msInfo_9_bits_param
+      (_mshrCtl_io_msInfo_9_bits_param),
+    .io_msInfo_9_bits_mergeA
+      (_mshrCtl_io_msInfo_9_bits_mergeA),
+    .io_msInfo_9_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_9_bits_w_grantfirst),
+    .io_msInfo_9_bits_w_grantlast
+      (_mshrCtl_io_msInfo_9_bits_w_grantlast),
+    .io_msInfo_9_bits_w_grant
+      (_mshrCtl_io_msInfo_9_bits_w_grant),
+    .io_msInfo_9_bits_s_release
+      (_mshrCtl_io_msInfo_9_bits_s_release),
+    .io_msInfo_9_bits_s_refill
+      (_mshrCtl_io_msInfo_9_bits_s_refill),
+    .io_msInfo_9_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_9_bits_s_cmoresp),
+    .io_msInfo_9_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_9_bits_s_cmometaw),
+    .io_msInfo_9_bits_w_releaseack
+      (_mshrCtl_io_msInfo_9_bits_w_releaseack),
+    .io_msInfo_9_bits_w_replResp
+      (_mshrCtl_io_msInfo_9_bits_w_replResp),
+    .io_msInfo_9_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_9_bits_w_rprobeacklast),
+    .io_msInfo_9_bits_replaceData
+      (_mshrCtl_io_msInfo_9_bits_replaceData),
+    .io_msInfo_9_bits_releaseToClean
+      (_mshrCtl_io_msInfo_9_bits_releaseToClean),
+    .io_msInfo_10_valid
+      (_mshrCtl_io_msInfo_10_valid),
+    .io_msInfo_10_bits_channel
+      (_mshrCtl_io_msInfo_10_bits_channel),
+    .io_msInfo_10_bits_set
+      (_mshrCtl_io_msInfo_10_bits_set),
+    .io_msInfo_10_bits_way
+      (_mshrCtl_io_msInfo_10_bits_way),
+    .io_msInfo_10_bits_reqTag
+      (_mshrCtl_io_msInfo_10_bits_reqTag),
+    .io_msInfo_10_bits_reqSource
+      (_mshrCtl_io_msInfo_10_bits_reqSource),
+    .io_msInfo_10_bits_willFree
+      (_mshrCtl_io_msInfo_10_bits_willFree),
+    .io_msInfo_10_bits_aliasTask
+      (_mshrCtl_io_msInfo_10_bits_aliasTask),
+    .io_msInfo_10_bits_needRelease
+      (_mshrCtl_io_msInfo_10_bits_needRelease),
+    .io_msInfo_10_bits_blockRefill
+      (_mshrCtl_io_msInfo_10_bits_blockRefill),
+    .io_msInfo_10_bits_meta_dirty
+      (_mshrCtl_io_msInfo_10_bits_meta_dirty),
+    .io_msInfo_10_bits_meta_state
+      (_mshrCtl_io_msInfo_10_bits_meta_state),
+    .io_msInfo_10_bits_meta_clients
+      (_mshrCtl_io_msInfo_10_bits_meta_clients),
+    .io_msInfo_10_bits_meta_alias
+      (_mshrCtl_io_msInfo_10_bits_meta_alias),
+    .io_msInfo_10_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_10_bits_meta_prefetch),
+    .io_msInfo_10_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_10_bits_meta_prefetchSrc),
+    .io_msInfo_10_bits_meta_accessed
+      (_mshrCtl_io_msInfo_10_bits_meta_accessed),
+    .io_msInfo_10_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_10_bits_meta_tagErr),
+    .io_msInfo_10_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_10_bits_meta_dataErr),
+    .io_msInfo_10_bits_metaTag
+      (_mshrCtl_io_msInfo_10_bits_metaTag),
+    .io_msInfo_10_bits_dirHit
+      (_mshrCtl_io_msInfo_10_bits_dirHit),
+    .io_msInfo_10_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_10_bits_isAcqOrPrefetch),
+    .io_msInfo_10_bits_isPrefetch
+      (_mshrCtl_io_msInfo_10_bits_isPrefetch),
+    .io_msInfo_10_bits_param
+      (_mshrCtl_io_msInfo_10_bits_param),
+    .io_msInfo_10_bits_mergeA
+      (_mshrCtl_io_msInfo_10_bits_mergeA),
+    .io_msInfo_10_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_10_bits_w_grantfirst),
+    .io_msInfo_10_bits_w_grantlast
+      (_mshrCtl_io_msInfo_10_bits_w_grantlast),
+    .io_msInfo_10_bits_w_grant
+      (_mshrCtl_io_msInfo_10_bits_w_grant),
+    .io_msInfo_10_bits_s_release
+      (_mshrCtl_io_msInfo_10_bits_s_release),
+    .io_msInfo_10_bits_s_refill
+      (_mshrCtl_io_msInfo_10_bits_s_refill),
+    .io_msInfo_10_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_10_bits_s_cmoresp),
+    .io_msInfo_10_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_10_bits_s_cmometaw),
+    .io_msInfo_10_bits_w_releaseack
+      (_mshrCtl_io_msInfo_10_bits_w_releaseack),
+    .io_msInfo_10_bits_w_replResp
+      (_mshrCtl_io_msInfo_10_bits_w_replResp),
+    .io_msInfo_10_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_10_bits_w_rprobeacklast),
+    .io_msInfo_10_bits_replaceData
+      (_mshrCtl_io_msInfo_10_bits_replaceData),
+    .io_msInfo_10_bits_releaseToClean
+      (_mshrCtl_io_msInfo_10_bits_releaseToClean),
+    .io_msInfo_11_valid
+      (_mshrCtl_io_msInfo_11_valid),
+    .io_msInfo_11_bits_channel
+      (_mshrCtl_io_msInfo_11_bits_channel),
+    .io_msInfo_11_bits_set
+      (_mshrCtl_io_msInfo_11_bits_set),
+    .io_msInfo_11_bits_way
+      (_mshrCtl_io_msInfo_11_bits_way),
+    .io_msInfo_11_bits_reqTag
+      (_mshrCtl_io_msInfo_11_bits_reqTag),
+    .io_msInfo_11_bits_reqSource
+      (_mshrCtl_io_msInfo_11_bits_reqSource),
+    .io_msInfo_11_bits_willFree
+      (_mshrCtl_io_msInfo_11_bits_willFree),
+    .io_msInfo_11_bits_aliasTask
+      (_mshrCtl_io_msInfo_11_bits_aliasTask),
+    .io_msInfo_11_bits_needRelease
+      (_mshrCtl_io_msInfo_11_bits_needRelease),
+    .io_msInfo_11_bits_blockRefill
+      (_mshrCtl_io_msInfo_11_bits_blockRefill),
+    .io_msInfo_11_bits_meta_dirty
+      (_mshrCtl_io_msInfo_11_bits_meta_dirty),
+    .io_msInfo_11_bits_meta_state
+      (_mshrCtl_io_msInfo_11_bits_meta_state),
+    .io_msInfo_11_bits_meta_clients
+      (_mshrCtl_io_msInfo_11_bits_meta_clients),
+    .io_msInfo_11_bits_meta_alias
+      (_mshrCtl_io_msInfo_11_bits_meta_alias),
+    .io_msInfo_11_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_11_bits_meta_prefetch),
+    .io_msInfo_11_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_11_bits_meta_prefetchSrc),
+    .io_msInfo_11_bits_meta_accessed
+      (_mshrCtl_io_msInfo_11_bits_meta_accessed),
+    .io_msInfo_11_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_11_bits_meta_tagErr),
+    .io_msInfo_11_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_11_bits_meta_dataErr),
+    .io_msInfo_11_bits_metaTag
+      (_mshrCtl_io_msInfo_11_bits_metaTag),
+    .io_msInfo_11_bits_dirHit
+      (_mshrCtl_io_msInfo_11_bits_dirHit),
+    .io_msInfo_11_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_11_bits_isAcqOrPrefetch),
+    .io_msInfo_11_bits_isPrefetch
+      (_mshrCtl_io_msInfo_11_bits_isPrefetch),
+    .io_msInfo_11_bits_param
+      (_mshrCtl_io_msInfo_11_bits_param),
+    .io_msInfo_11_bits_mergeA
+      (_mshrCtl_io_msInfo_11_bits_mergeA),
+    .io_msInfo_11_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_11_bits_w_grantfirst),
+    .io_msInfo_11_bits_w_grantlast
+      (_mshrCtl_io_msInfo_11_bits_w_grantlast),
+    .io_msInfo_11_bits_w_grant
+      (_mshrCtl_io_msInfo_11_bits_w_grant),
+    .io_msInfo_11_bits_s_release
+      (_mshrCtl_io_msInfo_11_bits_s_release),
+    .io_msInfo_11_bits_s_refill
+      (_mshrCtl_io_msInfo_11_bits_s_refill),
+    .io_msInfo_11_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_11_bits_s_cmoresp),
+    .io_msInfo_11_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_11_bits_s_cmometaw),
+    .io_msInfo_11_bits_w_releaseack
+      (_mshrCtl_io_msInfo_11_bits_w_releaseack),
+    .io_msInfo_11_bits_w_replResp
+      (_mshrCtl_io_msInfo_11_bits_w_replResp),
+    .io_msInfo_11_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_11_bits_w_rprobeacklast),
+    .io_msInfo_11_bits_replaceData
+      (_mshrCtl_io_msInfo_11_bits_replaceData),
+    .io_msInfo_11_bits_releaseToClean
+      (_mshrCtl_io_msInfo_11_bits_releaseToClean),
+    .io_msInfo_12_valid
+      (_mshrCtl_io_msInfo_12_valid),
+    .io_msInfo_12_bits_channel
+      (_mshrCtl_io_msInfo_12_bits_channel),
+    .io_msInfo_12_bits_set
+      (_mshrCtl_io_msInfo_12_bits_set),
+    .io_msInfo_12_bits_way
+      (_mshrCtl_io_msInfo_12_bits_way),
+    .io_msInfo_12_bits_reqTag
+      (_mshrCtl_io_msInfo_12_bits_reqTag),
+    .io_msInfo_12_bits_reqSource
+      (_mshrCtl_io_msInfo_12_bits_reqSource),
+    .io_msInfo_12_bits_willFree
+      (_mshrCtl_io_msInfo_12_bits_willFree),
+    .io_msInfo_12_bits_aliasTask
+      (_mshrCtl_io_msInfo_12_bits_aliasTask),
+    .io_msInfo_12_bits_needRelease
+      (_mshrCtl_io_msInfo_12_bits_needRelease),
+    .io_msInfo_12_bits_blockRefill
+      (_mshrCtl_io_msInfo_12_bits_blockRefill),
+    .io_msInfo_12_bits_meta_dirty
+      (_mshrCtl_io_msInfo_12_bits_meta_dirty),
+    .io_msInfo_12_bits_meta_state
+      (_mshrCtl_io_msInfo_12_bits_meta_state),
+    .io_msInfo_12_bits_meta_clients
+      (_mshrCtl_io_msInfo_12_bits_meta_clients),
+    .io_msInfo_12_bits_meta_alias
+      (_mshrCtl_io_msInfo_12_bits_meta_alias),
+    .io_msInfo_12_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_12_bits_meta_prefetch),
+    .io_msInfo_12_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_12_bits_meta_prefetchSrc),
+    .io_msInfo_12_bits_meta_accessed
+      (_mshrCtl_io_msInfo_12_bits_meta_accessed),
+    .io_msInfo_12_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_12_bits_meta_tagErr),
+    .io_msInfo_12_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_12_bits_meta_dataErr),
+    .io_msInfo_12_bits_metaTag
+      (_mshrCtl_io_msInfo_12_bits_metaTag),
+    .io_msInfo_12_bits_dirHit
+      (_mshrCtl_io_msInfo_12_bits_dirHit),
+    .io_msInfo_12_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_12_bits_isAcqOrPrefetch),
+    .io_msInfo_12_bits_isPrefetch
+      (_mshrCtl_io_msInfo_12_bits_isPrefetch),
+    .io_msInfo_12_bits_param
+      (_mshrCtl_io_msInfo_12_bits_param),
+    .io_msInfo_12_bits_mergeA
+      (_mshrCtl_io_msInfo_12_bits_mergeA),
+    .io_msInfo_12_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_12_bits_w_grantfirst),
+    .io_msInfo_12_bits_w_grantlast
+      (_mshrCtl_io_msInfo_12_bits_w_grantlast),
+    .io_msInfo_12_bits_w_grant
+      (_mshrCtl_io_msInfo_12_bits_w_grant),
+    .io_msInfo_12_bits_s_release
+      (_mshrCtl_io_msInfo_12_bits_s_release),
+    .io_msInfo_12_bits_s_refill
+      (_mshrCtl_io_msInfo_12_bits_s_refill),
+    .io_msInfo_12_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_12_bits_s_cmoresp),
+    .io_msInfo_12_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_12_bits_s_cmometaw),
+    .io_msInfo_12_bits_w_releaseack
+      (_mshrCtl_io_msInfo_12_bits_w_releaseack),
+    .io_msInfo_12_bits_w_replResp
+      (_mshrCtl_io_msInfo_12_bits_w_replResp),
+    .io_msInfo_12_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_12_bits_w_rprobeacklast),
+    .io_msInfo_12_bits_replaceData
+      (_mshrCtl_io_msInfo_12_bits_replaceData),
+    .io_msInfo_12_bits_releaseToClean
+      (_mshrCtl_io_msInfo_12_bits_releaseToClean),
+    .io_msInfo_13_valid
+      (_mshrCtl_io_msInfo_13_valid),
+    .io_msInfo_13_bits_channel
+      (_mshrCtl_io_msInfo_13_bits_channel),
+    .io_msInfo_13_bits_set
+      (_mshrCtl_io_msInfo_13_bits_set),
+    .io_msInfo_13_bits_way
+      (_mshrCtl_io_msInfo_13_bits_way),
+    .io_msInfo_13_bits_reqTag
+      (_mshrCtl_io_msInfo_13_bits_reqTag),
+    .io_msInfo_13_bits_reqSource
+      (_mshrCtl_io_msInfo_13_bits_reqSource),
+    .io_msInfo_13_bits_willFree
+      (_mshrCtl_io_msInfo_13_bits_willFree),
+    .io_msInfo_13_bits_aliasTask
+      (_mshrCtl_io_msInfo_13_bits_aliasTask),
+    .io_msInfo_13_bits_needRelease
+      (_mshrCtl_io_msInfo_13_bits_needRelease),
+    .io_msInfo_13_bits_blockRefill
+      (_mshrCtl_io_msInfo_13_bits_blockRefill),
+    .io_msInfo_13_bits_meta_dirty
+      (_mshrCtl_io_msInfo_13_bits_meta_dirty),
+    .io_msInfo_13_bits_meta_state
+      (_mshrCtl_io_msInfo_13_bits_meta_state),
+    .io_msInfo_13_bits_meta_clients
+      (_mshrCtl_io_msInfo_13_bits_meta_clients),
+    .io_msInfo_13_bits_meta_alias
+      (_mshrCtl_io_msInfo_13_bits_meta_alias),
+    .io_msInfo_13_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_13_bits_meta_prefetch),
+    .io_msInfo_13_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_13_bits_meta_prefetchSrc),
+    .io_msInfo_13_bits_meta_accessed
+      (_mshrCtl_io_msInfo_13_bits_meta_accessed),
+    .io_msInfo_13_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_13_bits_meta_tagErr),
+    .io_msInfo_13_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_13_bits_meta_dataErr),
+    .io_msInfo_13_bits_metaTag
+      (_mshrCtl_io_msInfo_13_bits_metaTag),
+    .io_msInfo_13_bits_dirHit
+      (_mshrCtl_io_msInfo_13_bits_dirHit),
+    .io_msInfo_13_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_13_bits_isAcqOrPrefetch),
+    .io_msInfo_13_bits_isPrefetch
+      (_mshrCtl_io_msInfo_13_bits_isPrefetch),
+    .io_msInfo_13_bits_param
+      (_mshrCtl_io_msInfo_13_bits_param),
+    .io_msInfo_13_bits_mergeA
+      (_mshrCtl_io_msInfo_13_bits_mergeA),
+    .io_msInfo_13_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_13_bits_w_grantfirst),
+    .io_msInfo_13_bits_w_grantlast
+      (_mshrCtl_io_msInfo_13_bits_w_grantlast),
+    .io_msInfo_13_bits_w_grant
+      (_mshrCtl_io_msInfo_13_bits_w_grant),
+    .io_msInfo_13_bits_s_release
+      (_mshrCtl_io_msInfo_13_bits_s_release),
+    .io_msInfo_13_bits_s_refill
+      (_mshrCtl_io_msInfo_13_bits_s_refill),
+    .io_msInfo_13_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_13_bits_s_cmoresp),
+    .io_msInfo_13_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_13_bits_s_cmometaw),
+    .io_msInfo_13_bits_w_releaseack
+      (_mshrCtl_io_msInfo_13_bits_w_releaseack),
+    .io_msInfo_13_bits_w_replResp
+      (_mshrCtl_io_msInfo_13_bits_w_replResp),
+    .io_msInfo_13_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_13_bits_w_rprobeacklast),
+    .io_msInfo_13_bits_replaceData
+      (_mshrCtl_io_msInfo_13_bits_replaceData),
+    .io_msInfo_13_bits_releaseToClean
+      (_mshrCtl_io_msInfo_13_bits_releaseToClean),
+    .io_msInfo_14_valid
+      (_mshrCtl_io_msInfo_14_valid),
+    .io_msInfo_14_bits_channel
+      (_mshrCtl_io_msInfo_14_bits_channel),
+    .io_msInfo_14_bits_set
+      (_mshrCtl_io_msInfo_14_bits_set),
+    .io_msInfo_14_bits_way
+      (_mshrCtl_io_msInfo_14_bits_way),
+    .io_msInfo_14_bits_reqTag
+      (_mshrCtl_io_msInfo_14_bits_reqTag),
+    .io_msInfo_14_bits_reqSource
+      (_mshrCtl_io_msInfo_14_bits_reqSource),
+    .io_msInfo_14_bits_willFree
+      (_mshrCtl_io_msInfo_14_bits_willFree),
+    .io_msInfo_14_bits_aliasTask
+      (_mshrCtl_io_msInfo_14_bits_aliasTask),
+    .io_msInfo_14_bits_needRelease
+      (_mshrCtl_io_msInfo_14_bits_needRelease),
+    .io_msInfo_14_bits_blockRefill
+      (_mshrCtl_io_msInfo_14_bits_blockRefill),
+    .io_msInfo_14_bits_meta_dirty
+      (_mshrCtl_io_msInfo_14_bits_meta_dirty),
+    .io_msInfo_14_bits_meta_state
+      (_mshrCtl_io_msInfo_14_bits_meta_state),
+    .io_msInfo_14_bits_meta_clients
+      (_mshrCtl_io_msInfo_14_bits_meta_clients),
+    .io_msInfo_14_bits_meta_alias
+      (_mshrCtl_io_msInfo_14_bits_meta_alias),
+    .io_msInfo_14_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_14_bits_meta_prefetch),
+    .io_msInfo_14_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_14_bits_meta_prefetchSrc),
+    .io_msInfo_14_bits_meta_accessed
+      (_mshrCtl_io_msInfo_14_bits_meta_accessed),
+    .io_msInfo_14_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_14_bits_meta_tagErr),
+    .io_msInfo_14_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_14_bits_meta_dataErr),
+    .io_msInfo_14_bits_metaTag
+      (_mshrCtl_io_msInfo_14_bits_metaTag),
+    .io_msInfo_14_bits_dirHit
+      (_mshrCtl_io_msInfo_14_bits_dirHit),
+    .io_msInfo_14_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_14_bits_isAcqOrPrefetch),
+    .io_msInfo_14_bits_isPrefetch
+      (_mshrCtl_io_msInfo_14_bits_isPrefetch),
+    .io_msInfo_14_bits_param
+      (_mshrCtl_io_msInfo_14_bits_param),
+    .io_msInfo_14_bits_mergeA
+      (_mshrCtl_io_msInfo_14_bits_mergeA),
+    .io_msInfo_14_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_14_bits_w_grantfirst),
+    .io_msInfo_14_bits_w_grantlast
+      (_mshrCtl_io_msInfo_14_bits_w_grantlast),
+    .io_msInfo_14_bits_w_grant
+      (_mshrCtl_io_msInfo_14_bits_w_grant),
+    .io_msInfo_14_bits_s_release
+      (_mshrCtl_io_msInfo_14_bits_s_release),
+    .io_msInfo_14_bits_s_refill
+      (_mshrCtl_io_msInfo_14_bits_s_refill),
+    .io_msInfo_14_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_14_bits_s_cmoresp),
+    .io_msInfo_14_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_14_bits_s_cmometaw),
+    .io_msInfo_14_bits_w_releaseack
+      (_mshrCtl_io_msInfo_14_bits_w_releaseack),
+    .io_msInfo_14_bits_w_replResp
+      (_mshrCtl_io_msInfo_14_bits_w_replResp),
+    .io_msInfo_14_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_14_bits_w_rprobeacklast),
+    .io_msInfo_14_bits_replaceData
+      (_mshrCtl_io_msInfo_14_bits_replaceData),
+    .io_msInfo_14_bits_releaseToClean
+      (_mshrCtl_io_msInfo_14_bits_releaseToClean),
+    .io_msInfo_15_valid
+      (_mshrCtl_io_msInfo_15_valid),
+    .io_msInfo_15_bits_channel
+      (_mshrCtl_io_msInfo_15_bits_channel),
+    .io_msInfo_15_bits_set
+      (_mshrCtl_io_msInfo_15_bits_set),
+    .io_msInfo_15_bits_way
+      (_mshrCtl_io_msInfo_15_bits_way),
+    .io_msInfo_15_bits_reqTag
+      (_mshrCtl_io_msInfo_15_bits_reqTag),
+    .io_msInfo_15_bits_reqSource
+      (_mshrCtl_io_msInfo_15_bits_reqSource),
+    .io_msInfo_15_bits_willFree
+      (_mshrCtl_io_msInfo_15_bits_willFree),
+    .io_msInfo_15_bits_aliasTask
+      (_mshrCtl_io_msInfo_15_bits_aliasTask),
+    .io_msInfo_15_bits_needRelease
+      (_mshrCtl_io_msInfo_15_bits_needRelease),
+    .io_msInfo_15_bits_blockRefill
+      (_mshrCtl_io_msInfo_15_bits_blockRefill),
+    .io_msInfo_15_bits_meta_dirty
+      (_mshrCtl_io_msInfo_15_bits_meta_dirty),
+    .io_msInfo_15_bits_meta_state
+      (_mshrCtl_io_msInfo_15_bits_meta_state),
+    .io_msInfo_15_bits_meta_clients
+      (_mshrCtl_io_msInfo_15_bits_meta_clients),
+    .io_msInfo_15_bits_meta_alias
+      (_mshrCtl_io_msInfo_15_bits_meta_alias),
+    .io_msInfo_15_bits_meta_prefetch
+      (_mshrCtl_io_msInfo_15_bits_meta_prefetch),
+    .io_msInfo_15_bits_meta_prefetchSrc
+      (_mshrCtl_io_msInfo_15_bits_meta_prefetchSrc),
+    .io_msInfo_15_bits_meta_accessed
+      (_mshrCtl_io_msInfo_15_bits_meta_accessed),
+    .io_msInfo_15_bits_meta_tagErr
+      (_mshrCtl_io_msInfo_15_bits_meta_tagErr),
+    .io_msInfo_15_bits_meta_dataErr
+      (_mshrCtl_io_msInfo_15_bits_meta_dataErr),
+    .io_msInfo_15_bits_metaTag
+      (_mshrCtl_io_msInfo_15_bits_metaTag),
+    .io_msInfo_15_bits_dirHit
+      (_mshrCtl_io_msInfo_15_bits_dirHit),
+    .io_msInfo_15_bits_isAcqOrPrefetch
+      (_mshrCtl_io_msInfo_15_bits_isAcqOrPrefetch),
+    .io_msInfo_15_bits_isPrefetch
+      (_mshrCtl_io_msInfo_15_bits_isPrefetch),
+    .io_msInfo_15_bits_param
+      (_mshrCtl_io_msInfo_15_bits_param),
+    .io_msInfo_15_bits_mergeA
+      (_mshrCtl_io_msInfo_15_bits_mergeA),
+    .io_msInfo_15_bits_w_grantfirst
+      (_mshrCtl_io_msInfo_15_bits_w_grantfirst),
+    .io_msInfo_15_bits_w_grantlast
+      (_mshrCtl_io_msInfo_15_bits_w_grantlast),
+    .io_msInfo_15_bits_w_grant
+      (_mshrCtl_io_msInfo_15_bits_w_grant),
+    .io_msInfo_15_bits_s_release
+      (_mshrCtl_io_msInfo_15_bits_s_release),
+    .io_msInfo_15_bits_s_refill
+      (_mshrCtl_io_msInfo_15_bits_s_refill),
+    .io_msInfo_15_bits_s_cmoresp
+      (_mshrCtl_io_msInfo_15_bits_s_cmoresp),
+    .io_msInfo_15_bits_s_cmometaw
+      (_mshrCtl_io_msInfo_15_bits_s_cmometaw),
+    .io_msInfo_15_bits_w_releaseack
+      (_mshrCtl_io_msInfo_15_bits_w_releaseack),
+    .io_msInfo_15_bits_w_replResp
+      (_mshrCtl_io_msInfo_15_bits_w_replResp),
+    .io_msInfo_15_bits_w_rprobeacklast
+      (_mshrCtl_io_msInfo_15_bits_w_rprobeacklast),
+    .io_msInfo_15_bits_replaceData
+      (_mshrCtl_io_msInfo_15_bits_replaceData),
+    .io_msInfo_15_bits_releaseToClean
+      (_mshrCtl_io_msInfo_15_bits_releaseToClean),
+    .io_aMergeTask_valid
+      (_reqBuf_io_aMergeTask_valid),
+    .io_aMergeTask_bits_idOH
+      (_reqBuf_io_aMergeTask_bits_idOH),
+    .io_aMergeTask_bits_task_off
+      (_reqBuf_io_aMergeTask_bits_task_off),
+    .io_aMergeTask_bits_task_alias
+      (_reqBuf_io_aMergeTask_bits_task_alias),
+    .io_aMergeTask_bits_task_vaddr
+      (_reqBuf_io_aMergeTask_bits_task_vaddr),
+    .io_aMergeTask_bits_task_isKeyword
+      (_reqBuf_io_aMergeTask_bits_task_isKeyword),
+    .io_aMergeTask_bits_task_opcode
+      (_reqBuf_io_aMergeTask_bits_task_opcode),
+    .io_aMergeTask_bits_task_param
+      (_reqBuf_io_aMergeTask_bits_task_param),
+    .io_aMergeTask_bits_task_sourceId
+      (_reqBuf_io_aMergeTask_bits_task_sourceId),
+    .io_replResp_valid
+      (_directory_io_replResp_valid),
+    .io_replResp_bits_tag
+      (_directory_io_replResp_bits_tag),
+    .io_replResp_bits_way
+      (_directory_io_replResp_bits_way),
+    .io_replResp_bits_meta_dirty
+      (_directory_io_replResp_bits_meta_dirty),
+    .io_replResp_bits_meta_state
+      (_directory_io_replResp_bits_meta_state),
+    .io_replResp_bits_meta_clients
+      (_directory_io_replResp_bits_meta_clients),
+    .io_replResp_bits_meta_alias
+      (_directory_io_replResp_bits_meta_alias),
+    .io_replResp_bits_meta_prefetch
+      (_directory_io_replResp_bits_meta_prefetch),
+    .io_replResp_bits_meta_prefetchSrc
+      (_directory_io_replResp_bits_meta_prefetchSrc),
+    .io_replResp_bits_meta_accessed
+      (_directory_io_replResp_bits_meta_accessed),
+    .io_replResp_bits_meta_tagErr
+      (_directory_io_replResp_bits_meta_tagErr),
+    .io_replResp_bits_meta_dataErr
+      (_directory_io_replResp_bits_meta_dataErr),
+    .io_replResp_bits_mshrId
+      (_directory_io_replResp_bits_mshrId),
+    .io_replResp_bits_retry
+      (_directory_io_replResp_bits_retry),
+    .io_pCrd_0_query_valid
+      (io_pCrd_0_query_valid),
+    .io_pCrd_0_query_bits_pCrdType
+      (io_pCrd_0_query_bits_pCrdType),
+    .io_pCrd_0_query_bits_srcID
+      (io_pCrd_0_query_bits_srcID),
+    .io_pCrd_0_grant
+      (io_pCrd_0_grant),
+    .io_pCrd_1_query_valid
+      (io_pCrd_1_query_valid),
+    .io_pCrd_1_query_bits_pCrdType
+      (io_pCrd_1_query_bits_pCrdType),
+    .io_pCrd_1_query_bits_srcID
+      (io_pCrd_1_query_bits_srcID),
+    .io_pCrd_1_grant
+      (io_pCrd_1_grant),
+    .io_pCrd_2_query_valid
+      (io_pCrd_2_query_valid),
+    .io_pCrd_2_query_bits_pCrdType
+      (io_pCrd_2_query_bits_pCrdType),
+    .io_pCrd_2_query_bits_srcID
+      (io_pCrd_2_query_bits_srcID),
+    .io_pCrd_2_grant
+      (io_pCrd_2_grant),
+    .io_pCrd_3_query_valid
+      (io_pCrd_3_query_valid),
+    .io_pCrd_3_query_bits_pCrdType
+      (io_pCrd_3_query_bits_pCrdType),
+    .io_pCrd_3_query_bits_srcID
+      (io_pCrd_3_query_bits_srcID),
+    .io_pCrd_3_grant
+      (io_pCrd_3_grant),
+    .io_pCrd_4_query_valid
+      (io_pCrd_4_query_valid),
+    .io_pCrd_4_query_bits_pCrdType
+      (io_pCrd_4_query_bits_pCrdType),
+    .io_pCrd_4_query_bits_srcID
+      (io_pCrd_4_query_bits_srcID),
+    .io_pCrd_4_grant
+      (io_pCrd_4_grant),
+    .io_pCrd_5_query_valid
+      (io_pCrd_5_query_valid),
+    .io_pCrd_5_query_bits_pCrdType
+      (io_pCrd_5_query_bits_pCrdType),
+    .io_pCrd_5_query_bits_srcID
+      (io_pCrd_5_query_bits_srcID),
+    .io_pCrd_5_grant
+      (io_pCrd_5_grant),
+    .io_pCrd_6_query_valid
+      (io_pCrd_6_query_valid),
+    .io_pCrd_6_query_bits_pCrdType
+      (io_pCrd_6_query_bits_pCrdType),
+    .io_pCrd_6_query_bits_srcID
+      (io_pCrd_6_query_bits_srcID),
+    .io_pCrd_6_grant
+      (io_pCrd_6_grant),
+    .io_pCrd_7_query_valid
+      (io_pCrd_7_query_valid),
+    .io_pCrd_7_query_bits_pCrdType
+      (io_pCrd_7_query_bits_pCrdType),
+    .io_pCrd_7_query_bits_srcID
+      (io_pCrd_7_query_bits_srcID),
+    .io_pCrd_7_grant
+      (io_pCrd_7_grant),
+    .io_pCrd_8_query_valid
+      (io_pCrd_8_query_valid),
+    .io_pCrd_8_query_bits_pCrdType
+      (io_pCrd_8_query_bits_pCrdType),
+    .io_pCrd_8_query_bits_srcID
+      (io_pCrd_8_query_bits_srcID),
+    .io_pCrd_8_grant
+      (io_pCrd_8_grant),
+    .io_pCrd_9_query_valid
+      (io_pCrd_9_query_valid),
+    .io_pCrd_9_query_bits_pCrdType
+      (io_pCrd_9_query_bits_pCrdType),
+    .io_pCrd_9_query_bits_srcID
+      (io_pCrd_9_query_bits_srcID),
+    .io_pCrd_9_grant
+      (io_pCrd_9_grant),
+    .io_pCrd_10_query_valid
+      (io_pCrd_10_query_valid),
+    .io_pCrd_10_query_bits_pCrdType
+      (io_pCrd_10_query_bits_pCrdType),
+    .io_pCrd_10_query_bits_srcID
+      (io_pCrd_10_query_bits_srcID),
+    .io_pCrd_10_grant
+      (io_pCrd_10_grant),
+    .io_pCrd_11_query_valid
+      (io_pCrd_11_query_valid),
+    .io_pCrd_11_query_bits_pCrdType
+      (io_pCrd_11_query_bits_pCrdType),
+    .io_pCrd_11_query_bits_srcID
+      (io_pCrd_11_query_bits_srcID),
+    .io_pCrd_11_grant
+      (io_pCrd_11_grant),
+    .io_pCrd_12_query_valid
+      (io_pCrd_12_query_valid),
+    .io_pCrd_12_query_bits_pCrdType
+      (io_pCrd_12_query_bits_pCrdType),
+    .io_pCrd_12_query_bits_srcID
+      (io_pCrd_12_query_bits_srcID),
+    .io_pCrd_12_grant
+      (io_pCrd_12_grant),
+    .io_pCrd_13_query_valid
+      (io_pCrd_13_query_valid),
+    .io_pCrd_13_query_bits_pCrdType
+      (io_pCrd_13_query_bits_pCrdType),
+    .io_pCrd_13_query_bits_srcID
+      (io_pCrd_13_query_bits_srcID),
+    .io_pCrd_13_grant
+      (io_pCrd_13_grant),
+    .io_pCrd_14_query_valid
+      (io_pCrd_14_query_valid),
+    .io_pCrd_14_query_bits_pCrdType
+      (io_pCrd_14_query_bits_pCrdType),
+    .io_pCrd_14_query_bits_srcID
+      (io_pCrd_14_query_bits_srcID),
+    .io_pCrd_14_grant
+      (io_pCrd_14_grant),
+    .io_pCrd_15_query_valid
+      (io_pCrd_15_query_valid),
+    .io_pCrd_15_query_bits_pCrdType
+      (io_pCrd_15_query_bits_pCrdType),
+    .io_pCrd_15_query_bits_srcID
+      (io_pCrd_15_query_bits_srcID),
+    .io_pCrd_15_grant
+      (io_pCrd_15_grant),
+    .io_l2Miss                                                             (io_l2Miss),
+    .io_perf_0_value
+      (_mshrCtl_io_perf_0_value),
+    .io_perf_1_value
+      (_mshrCtl_io_perf_1_value),
+    .io_perf_3_value
+      (_mshrCtl_io_perf_3_value)
+  );
+  L2Slice mbistPl (
+    .clock                    (clock),
+    .reset                    (reset),
+    .mbist_array              (bd_array),
+    .mbist_all                (bd_all),
+    .mbist_req                (bd_req),
+    .mbist_ack                (bd_ack),
+    .mbist_writeen            (bd_writeen),
+    .mbist_be                 (bd_be),
+    .mbist_addr               (bd_addr),
+    .mbist_indata             (bd_indata),
+    .mbist_readen             (bd_readen),
+    .mbist_addr_rd            (bd_addr_rd),
+    .mbist_outdata            (bd_outdata),
+    .toNextPipeline_0_array   (childBd_array),
+    .toNextPipeline_0_all     (childBd_all),
+    .toNextPipeline_0_req     (childBd_req),
+    .toNextPipeline_0_ack     (childBd_ack),
+    .toNextPipeline_0_writeen (childBd_writeen),
+    .toNextPipeline_0_be      (childBd_be),
+    .toNextPipeline_0_addr    (childBd_addr),
+    .toNextPipeline_0_indata  (childBd_indata),
+    .toNextPipeline_0_readen  (childBd_readen),
+    .toNextPipeline_0_addr_rd (childBd_addr_rd),
+    .toNextPipeline_0_outdata (childBd_outdata),
+    .toNextPipeline_1_array   (childBd_1_array),
+    .toNextPipeline_1_all     (childBd_1_all),
+    .toNextPipeline_1_req     (childBd_1_req),
+    .toNextPipeline_1_ack     (childBd_1_ack),
+    .toNextPipeline_1_writeen (childBd_1_writeen),
+    .toNextPipeline_1_be      (childBd_1_be),
+    .toNextPipeline_1_addr    (childBd_1_addr),
+    .toNextPipeline_1_indata  (childBd_1_indata),
+    .toNextPipeline_1_readen  (childBd_1_readen),
+    .toNextPipeline_1_addr_rd (childBd_1_addr_rd),
+    .toNextPipeline_1_outdata (childBd_1_outdata)
+  );
+  assign io_error_valid = io_error_valid_REG;
+  assign io_error_bits_valid = io_error_bits_REG_valid;
+  assign io_error_bits_address = io_error_bits_REG_address;
+  assign io_perf_0_value = io_perf_0_value_REG_1;
+  assign io_perf_1_value = io_perf_1_value_REG_1;
+  assign io_perf_3_value = io_perf_3_value_REG_1;
+  assign io_perf_4_value = io_perf_4_value_REG_1;
+  assign io_perf_5_value = io_perf_5_value_REG_1;
+  assign io_perf_6_value = io_perf_6_value_REG_1;
+  assign io_perf_7_value = io_perf_7_value_REG_1;
+  assign io_perf_8_value = io_perf_8_value_REG_1;
+  assign io_perf_9_value = io_perf_9_value_REG_1;
+  assign io_perf_10_value = io_perf_10_value_REG_1;
+  assign io_perf_11_value = io_perf_11_value_REG_1;
+  assign io_perf_12_value = io_perf_12_value_REG_1;
+  assign io_perf_13_value = io_perf_13_value_REG_1;
+  assign io_perf_14_value = io_perf_14_value_REG_1;
+  assign io_perf_15_value = io_perf_15_value_REG_1;
+  assign io_perf_16_value = io_perf_16_value_REG_1;
+  assign boreChildrenBd_bore_ack = bd_ack;
+  assign boreChildrenBd_bore_outdata = bd_outdata;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SourceB.sv b/flow/designs/src/xiangshan_coupledl2/deps/SourceB.sv
new file mode 100644
index 0000000000..11619d9ca8
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SourceB.sv
@@ -0,0 +1,491 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module SourceB(
+  input          clock,
+  input          reset,
+  input          io_sourceB_ready,
+  output         io_sourceB_valid,
+  output [2:0]   io_sourceB_bits_opcode,
+  output [1:0]   io_sourceB_bits_param,
+  output [47:0]  io_sourceB_bits_address,
+  output [255:0] io_sourceB_bits_data,
+  output         io_task_ready,
+  input          io_task_valid,
+  input  [33:0]  io_task_bits_tag,
+  input  [7:0]   io_task_bits_set,
+  input  [2:0]   io_task_bits_opcode,
+  input  [1:0]   io_task_bits_param,
+  input          io_task_bits_alias,
+  input          io_grantStatus_0_valid,
+  input  [7:0]   io_grantStatus_0_set,
+  input  [33:0]  io_grantStatus_0_tag,
+  input          io_grantStatus_1_valid,
+  input  [7:0]   io_grantStatus_1_set,
+  input  [33:0]  io_grantStatus_1_tag,
+  input          io_grantStatus_2_valid,
+  input  [7:0]   io_grantStatus_2_set,
+  input  [33:0]  io_grantStatus_2_tag,
+  input          io_grantStatus_3_valid,
+  input  [7:0]   io_grantStatus_3_set,
+  input  [33:0]  io_grantStatus_3_tag,
+  input          io_grantStatus_4_valid,
+  input  [7:0]   io_grantStatus_4_set,
+  input  [33:0]  io_grantStatus_4_tag,
+  input          io_grantStatus_5_valid,
+  input  [7:0]   io_grantStatus_5_set,
+  input  [33:0]  io_grantStatus_5_tag,
+  input          io_grantStatus_6_valid,
+  input  [7:0]   io_grantStatus_6_set,
+  input  [33:0]  io_grantStatus_6_tag,
+  input          io_grantStatus_7_valid,
+  input  [7:0]   io_grantStatus_7_set,
+  input  [33:0]  io_grantStatus_7_tag,
+  input          io_grantStatus_8_valid,
+  input  [7:0]   io_grantStatus_8_set,
+  input  [33:0]  io_grantStatus_8_tag,
+  input          io_grantStatus_9_valid,
+  input  [7:0]   io_grantStatus_9_set,
+  input  [33:0]  io_grantStatus_9_tag,
+  input          io_grantStatus_10_valid,
+  input  [7:0]   io_grantStatus_10_set,
+  input  [33:0]  io_grantStatus_10_tag,
+  input          io_grantStatus_11_valid,
+  input  [7:0]   io_grantStatus_11_set,
+  input  [33:0]  io_grantStatus_11_tag,
+  input          io_grantStatus_12_valid,
+  input  [7:0]   io_grantStatus_12_set,
+  input  [33:0]  io_grantStatus_12_tag,
+  input          io_grantStatus_13_valid,
+  input  [7:0]   io_grantStatus_13_set,
+  input  [33:0]  io_grantStatus_13_tag,
+  input          io_grantStatus_14_valid,
+  input  [7:0]   io_grantStatus_14_set,
+  input  [33:0]  io_grantStatus_14_tag,
+  input          io_grantStatus_15_valid,
+  input  [7:0]   io_grantStatus_15_set,
+  input  [33:0]  io_grantStatus_15_tag
+);
+
+  wire        _issueArb_io_in_0_ready;
+  wire        _issueArb_io_in_1_ready;
+  wire        _issueArb_io_in_2_ready;
+  wire        _issueArb_io_in_3_ready;
+  wire [33:0] _issueArb_io_out_bits_tag;
+  wire [7:0]  _issueArb_io_out_bits_set;
+  wire        _issueArb_io_out_bits_alias;
+  reg         probes_0_valid;
+  reg         probes_0_rdy;
+  reg  [6:0]  probes_0_waitG;
+  reg  [33:0] probes_0_task_tag;
+  reg  [7:0]  probes_0_task_set;
+  reg  [2:0]  probes_0_task_opcode;
+  reg  [1:0]  probes_0_task_param;
+  reg         probes_0_task_alias;
+  reg         probes_1_valid;
+  reg         probes_1_rdy;
+  reg  [6:0]  probes_1_waitG;
+  reg  [33:0] probes_1_task_tag;
+  reg  [7:0]  probes_1_task_set;
+  reg  [2:0]  probes_1_task_opcode;
+  reg  [1:0]  probes_1_task_param;
+  reg         probes_1_task_alias;
+  reg         probes_2_valid;
+  reg         probes_2_rdy;
+  reg  [6:0]  probes_2_waitG;
+  reg  [33:0] probes_2_task_tag;
+  reg  [7:0]  probes_2_task_set;
+  reg  [2:0]  probes_2_task_opcode;
+  reg  [1:0]  probes_2_task_param;
+  reg         probes_2_task_alias;
+  reg         probes_3_valid;
+  reg         probes_3_rdy;
+  reg  [6:0]  probes_3_waitG;
+  reg  [33:0] probes_3_task_tag;
+  reg  [7:0]  probes_3_task_set;
+  reg  [2:0]  probes_3_task_opcode;
+  reg  [1:0]  probes_3_task_param;
+  reg         probes_3_task_alias;
+  wire        io_task_ready_0 =
+    {probes_0_valid, probes_1_valid, probes_2_valid, probes_3_valid} != 4'hF;
+  wire        issueArb_io_in_0_valid = probes_0_valid & probes_0_rdy;
+  wire        issueArb_io_in_1_valid = probes_1_valid & probes_1_rdy;
+  wire        issueArb_io_in_2_valid = probes_2_valid & probes_2_rdy;
+  wire        issueArb_io_in_3_valid = probes_3_valid & probes_3_rdy;
+  wire        conflictMask_1 =
+    io_grantStatus_1_valid & io_grantStatus_1_set == io_task_bits_set
+    & io_grantStatus_1_tag == io_task_bits_tag;
+  wire        conflictMask_2 =
+    io_grantStatus_2_valid & io_grantStatus_2_set == io_task_bits_set
+    & io_grantStatus_2_tag == io_task_bits_tag;
+  wire        conflictMask_3 =
+    io_grantStatus_3_valid & io_grantStatus_3_set == io_task_bits_set
+    & io_grantStatus_3_tag == io_task_bits_tag;
+  wire        conflictMask_4 =
+    io_grantStatus_4_valid & io_grantStatus_4_set == io_task_bits_set
+    & io_grantStatus_4_tag == io_task_bits_tag;
+  wire        conflictMask_5 =
+    io_grantStatus_5_valid & io_grantStatus_5_set == io_task_bits_set
+    & io_grantStatus_5_tag == io_task_bits_tag;
+  wire        conflictMask_6 =
+    io_grantStatus_6_valid & io_grantStatus_6_set == io_task_bits_set
+    & io_grantStatus_6_tag == io_task_bits_tag;
+  wire        conflictMask_7 =
+    io_grantStatus_7_valid & io_grantStatus_7_set == io_task_bits_set
+    & io_grantStatus_7_tag == io_task_bits_tag;
+  wire        conflictMask_8 =
+    io_grantStatus_8_valid & io_grantStatus_8_set == io_task_bits_set
+    & io_grantStatus_8_tag == io_task_bits_tag;
+  wire        conflictMask_9 =
+    io_grantStatus_9_valid & io_grantStatus_9_set == io_task_bits_set
+    & io_grantStatus_9_tag == io_task_bits_tag;
+  wire        conflictMask_10 =
+    io_grantStatus_10_valid & io_grantStatus_10_set == io_task_bits_set
+    & io_grantStatus_10_tag == io_task_bits_tag;
+  wire        conflictMask_11 =
+    io_grantStatus_11_valid & io_grantStatus_11_set == io_task_bits_set
+    & io_grantStatus_11_tag == io_task_bits_tag;
+  wire        conflictMask_12 =
+    io_grantStatus_12_valid & io_grantStatus_12_set == io_task_bits_set
+    & io_grantStatus_12_tag == io_task_bits_tag;
+  wire        conflictMask_13 =
+    io_grantStatus_13_valid & io_grantStatus_13_set == io_task_bits_set
+    & io_grantStatus_13_tag == io_task_bits_tag;
+  wire        conflictMask_14 =
+    io_grantStatus_14_valid & io_grantStatus_14_set == io_task_bits_set
+    & io_grantStatus_14_tag == io_task_bits_tag;
+  wire        conflictMask_15 =
+    io_grantStatus_15_valid & io_grantStatus_15_set == io_task_bits_set
+    & io_grantStatus_15_tag == io_task_bits_tag;
+  wire [1:0]  insertIdx =
+    probes_0_valid ? (probes_1_valid ? {1'h1, probes_2_valid} : 2'h1) : 2'h0;
+  wire        alloc = io_task_ready_0 & io_task_valid;
+  wire        _GEN = alloc & insertIdx == 2'h0;
+  wire        _GEN_0 = alloc & insertIdx == 2'h1;
+  wire        _GEN_1 = alloc & insertIdx == 2'h2;
+  wire        _GEN_2 = alloc & (&insertIdx);
+  wire        _probes_rdy_T =
+    {io_grantStatus_0_valid & io_grantStatus_0_set == io_task_bits_set
+       & io_grantStatus_0_tag == io_task_bits_tag,
+     conflictMask_1,
+     conflictMask_2,
+     conflictMask_3,
+     conflictMask_4,
+     conflictMask_5,
+     conflictMask_6,
+     conflictMask_7,
+     conflictMask_8,
+     conflictMask_9,
+     conflictMask_10,
+     conflictMask_11,
+     conflictMask_12,
+     conflictMask_13,
+     conflictMask_14,
+     conflictMask_15} == 16'h0;
+  wire [6:0]  _probes_waitG_T_2 =
+    {conflictMask_15,
+     conflictMask_14,
+     conflictMask_13,
+     conflictMask_12,
+     conflictMask_11,
+     conflictMask_10,
+     conflictMask_9}
+    | {conflictMask_7,
+       conflictMask_6,
+       conflictMask_5,
+       conflictMask_4,
+       conflictMask_3,
+       conflictMask_2,
+       conflictMask_1};
+  wire [2:0]  _probes_waitG_T_4 = _probes_waitG_T_2[6:4] | _probes_waitG_T_2[2:0];
+  wire [6:0]  _GEN_3 =
+    {3'h0,
+     |{conflictMask_15,
+       conflictMask_14,
+       conflictMask_13,
+       conflictMask_12,
+       conflictMask_11,
+       conflictMask_10,
+       conflictMask_9,
+       conflictMask_8},
+     |(_probes_waitG_T_2[6:3]),
+     |(_probes_waitG_T_4[2:1]),
+     _probes_waitG_T_4[2] | _probes_waitG_T_4[0]};
+  wire [15:0] _GEN_4 =
+    {{io_grantStatus_15_valid},
+     {io_grantStatus_14_valid},
+     {io_grantStatus_13_valid},
+     {io_grantStatus_12_valid},
+     {io_grantStatus_11_valid},
+     {io_grantStatus_10_valid},
+     {io_grantStatus_9_valid},
+     {io_grantStatus_8_valid},
+     {io_grantStatus_7_valid},
+     {io_grantStatus_6_valid},
+     {io_grantStatus_5_valid},
+     {io_grantStatus_4_valid},
+     {io_grantStatus_3_valid},
+     {io_grantStatus_2_valid},
+     {io_grantStatus_1_valid},
+     {io_grantStatus_0_valid}};
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      probes_0_valid <= 1'h0;
+      probes_0_rdy <= 1'h0;
+      probes_0_waitG <= 7'h0;
+      probes_0_task_tag <= 34'h0;
+      probes_0_task_set <= 8'h0;
+      probes_0_task_opcode <= 3'h0;
+      probes_0_task_param <= 2'h0;
+      probes_0_task_alias <= 1'h0;
+      probes_1_valid <= 1'h0;
+      probes_1_rdy <= 1'h0;
+      probes_1_waitG <= 7'h0;
+      probes_1_task_tag <= 34'h0;
+      probes_1_task_set <= 8'h0;
+      probes_1_task_opcode <= 3'h0;
+      probes_1_task_param <= 2'h0;
+      probes_1_task_alias <= 1'h0;
+      probes_2_valid <= 1'h0;
+      probes_2_rdy <= 1'h0;
+      probes_2_waitG <= 7'h0;
+      probes_2_task_tag <= 34'h0;
+      probes_2_task_set <= 8'h0;
+      probes_2_task_opcode <= 3'h0;
+      probes_2_task_param <= 2'h0;
+      probes_2_task_alias <= 1'h0;
+      probes_3_valid <= 1'h0;
+      probes_3_rdy <= 1'h0;
+      probes_3_waitG <= 7'h0;
+      probes_3_task_tag <= 34'h0;
+      probes_3_task_set <= 8'h0;
+      probes_3_task_opcode <= 3'h0;
+      probes_3_task_param <= 2'h0;
+      probes_3_task_alias <= 1'h0;
+    end
+    else begin
+      probes_0_valid <=
+        ~(_issueArb_io_in_0_ready & issueArb_io_in_0_valid) & (_GEN | probes_0_valid);
+      probes_0_rdy <=
+        probes_0_valid & ~_GEN_4[probes_0_waitG[3:0]]
+        | (_GEN ? _probes_rdy_T : probes_0_rdy);
+      if (_GEN) begin
+        probes_0_waitG <= _GEN_3;
+        probes_0_task_tag <= io_task_bits_tag;
+        probes_0_task_set <= io_task_bits_set;
+        probes_0_task_opcode <= io_task_bits_opcode;
+        probes_0_task_param <= io_task_bits_param;
+        probes_0_task_alias <= io_task_bits_alias;
+      end
+      probes_1_valid <=
+        ~(_issueArb_io_in_1_ready & issueArb_io_in_1_valid) & (_GEN_0 | probes_1_valid);
+      probes_1_rdy <=
+        probes_1_valid & ~_GEN_4[probes_1_waitG[3:0]]
+        | (_GEN_0 ? _probes_rdy_T : probes_1_rdy);
+      if (_GEN_0) begin
+        probes_1_waitG <= _GEN_3;
+        probes_1_task_tag <= io_task_bits_tag;
+        probes_1_task_set <= io_task_bits_set;
+        probes_1_task_opcode <= io_task_bits_opcode;
+        probes_1_task_param <= io_task_bits_param;
+        probes_1_task_alias <= io_task_bits_alias;
+      end
+      probes_2_valid <=
+        ~(_issueArb_io_in_2_ready & issueArb_io_in_2_valid) & (_GEN_1 | probes_2_valid);
+      probes_2_rdy <=
+        probes_2_valid & ~_GEN_4[probes_2_waitG[3:0]]
+        | (_GEN_1 ? _probes_rdy_T : probes_2_rdy);
+      if (_GEN_1) begin
+        probes_2_waitG <= _GEN_3;
+        probes_2_task_tag <= io_task_bits_tag;
+        probes_2_task_set <= io_task_bits_set;
+        probes_2_task_opcode <= io_task_bits_opcode;
+        probes_2_task_param <= io_task_bits_param;
+        probes_2_task_alias <= io_task_bits_alias;
+      end
+      probes_3_valid <=
+        ~(_issueArb_io_in_3_ready & issueArb_io_in_3_valid) & (_GEN_2 | probes_3_valid);
+      probes_3_rdy <=
+        probes_3_valid & ~_GEN_4[probes_3_waitG[3:0]]
+        | (_GEN_2 ? _probes_rdy_T : probes_3_rdy);
+      if (_GEN_2) begin
+        probes_3_waitG <= _GEN_3;
+        probes_3_task_tag <= io_task_bits_tag;
+        probes_3_task_set <= io_task_bits_set;
+        probes_3_task_opcode <= io_task_bits_opcode;
+        probes_3_task_param <= io_task_bits_param;
+        probes_3_task_alias <= io_task_bits_alias;
+      end
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:7];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin
+          _RANDOM[i[2:0]] = `RANDOM;
+        end
+        probes_0_valid = _RANDOM[3'h0][0];
+        probes_0_rdy = _RANDOM[3'h0][1];
+        probes_0_waitG = _RANDOM[3'h0][8:2];
+        probes_0_task_tag = {_RANDOM[3'h0][31:9], _RANDOM[3'h1][10:0]};
+        probes_0_task_set = _RANDOM[3'h1][18:11];
+        probes_0_task_opcode = _RANDOM[3'h1][27:25];
+        probes_0_task_param = _RANDOM[3'h1][29:28];
+        probes_0_task_alias = _RANDOM[3'h1][30];
+        probes_1_valid = _RANDOM[3'h1][31];
+        probes_1_rdy = _RANDOM[3'h2][0];
+        probes_1_waitG = _RANDOM[3'h2][7:1];
+        probes_1_task_tag = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][9:0]};
+        probes_1_task_set = _RANDOM[3'h3][17:10];
+        probes_1_task_opcode = _RANDOM[3'h3][26:24];
+        probes_1_task_param = _RANDOM[3'h3][28:27];
+        probes_1_task_alias = _RANDOM[3'h3][29];
+        probes_2_valid = _RANDOM[3'h3][30];
+        probes_2_rdy = _RANDOM[3'h3][31];
+        probes_2_waitG = _RANDOM[3'h4][6:0];
+        probes_2_task_tag = {_RANDOM[3'h4][31:7], _RANDOM[3'h5][8:0]};
+        probes_2_task_set = _RANDOM[3'h5][16:9];
+        probes_2_task_opcode = _RANDOM[3'h5][25:23];
+        probes_2_task_param = _RANDOM[3'h5][27:26];
+        probes_2_task_alias = _RANDOM[3'h5][28];
+        probes_3_valid = _RANDOM[3'h5][29];
+        probes_3_rdy = _RANDOM[3'h5][30];
+        probes_3_waitG = {_RANDOM[3'h5][31], _RANDOM[3'h6][5:0]};
+        probes_3_task_tag = {_RANDOM[3'h6][31:6], _RANDOM[3'h7][7:0]};
+        probes_3_task_set = _RANDOM[3'h7][15:8];
+        probes_3_task_opcode = _RANDOM[3'h7][24:22];
+        probes_3_task_param = _RANDOM[3'h7][26:25];
+        probes_3_task_alias = _RANDOM[3'h7][27];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        probes_0_valid = 1'h0;
+        probes_0_rdy = 1'h0;
+        probes_0_waitG = 7'h0;
+        probes_0_task_tag = 34'h0;
+        probes_0_task_set = 8'h0;
+        probes_0_task_opcode = 3'h0;
+        probes_0_task_param = 2'h0;
+        probes_0_task_alias = 1'h0;
+        probes_1_valid = 1'h0;
+        probes_1_rdy = 1'h0;
+        probes_1_waitG = 7'h0;
+        probes_1_task_tag = 34'h0;
+        probes_1_task_set = 8'h0;
+        probes_1_task_opcode = 3'h0;
+        probes_1_task_param = 2'h0;
+        probes_1_task_alias = 1'h0;
+        probes_2_valid = 1'h0;
+        probes_2_rdy = 1'h0;
+        probes_2_waitG = 7'h0;
+        probes_2_task_tag = 34'h0;
+        probes_2_task_set = 8'h0;
+        probes_2_task_opcode = 3'h0;
+        probes_2_task_param = 2'h0;
+        probes_2_task_alias = 1'h0;
+        probes_3_valid = 1'h0;
+        probes_3_rdy = 1'h0;
+        probes_3_waitG = 7'h0;
+        probes_3_task_tag = 34'h0;
+        probes_3_task_set = 8'h0;
+        probes_3_task_opcode = 3'h0;
+        probes_3_task_param = 2'h0;
+        probes_3_task_alias = 1'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  TwoLevelRRArbiter_8 issueArb (
+    .clock               (clock),
+    .reset               (reset),
+    .io_in_0_ready       (_issueArb_io_in_0_ready),
+    .io_in_0_valid       (issueArb_io_in_0_valid),
+    .io_in_0_bits_tag    (probes_0_task_tag),
+    .io_in_0_bits_set    (probes_0_task_set),
+    .io_in_0_bits_opcode (probes_0_task_opcode),
+    .io_in_0_bits_param  (probes_0_task_param),
+    .io_in_0_bits_alias  (probes_0_task_alias),
+    .io_in_1_ready       (_issueArb_io_in_1_ready),
+    .io_in_1_valid       (issueArb_io_in_1_valid),
+    .io_in_1_bits_tag    (probes_1_task_tag),
+    .io_in_1_bits_set    (probes_1_task_set),
+    .io_in_1_bits_opcode (probes_1_task_opcode),
+    .io_in_1_bits_param  (probes_1_task_param),
+    .io_in_1_bits_alias  (probes_1_task_alias),
+    .io_in_2_ready       (_issueArb_io_in_2_ready),
+    .io_in_2_valid       (issueArb_io_in_2_valid),
+    .io_in_2_bits_tag    (probes_2_task_tag),
+    .io_in_2_bits_set    (probes_2_task_set),
+    .io_in_2_bits_opcode (probes_2_task_opcode),
+    .io_in_2_bits_param  (probes_2_task_param),
+    .io_in_2_bits_alias  (probes_2_task_alias),
+    .io_in_3_ready       (_issueArb_io_in_3_ready),
+    .io_in_3_valid       (issueArb_io_in_3_valid),
+    .io_in_3_bits_tag    (probes_3_task_tag),
+    .io_in_3_bits_set    (probes_3_task_set),
+    .io_in_3_bits_opcode (probes_3_task_opcode),
+    .io_in_3_bits_param  (probes_3_task_param),
+    .io_in_3_bits_alias  (probes_3_task_alias),
+    .io_out_ready        (io_sourceB_ready),
+    .io_out_valid        (io_sourceB_valid),
+    .io_out_bits_tag     (_issueArb_io_out_bits_tag),
+    .io_out_bits_set     (_issueArb_io_out_bits_set),
+    .io_out_bits_opcode  (io_sourceB_bits_opcode),
+    .io_out_bits_param   (io_sourceB_bits_param),
+    .io_out_bits_alias   (_issueArb_io_out_bits_alias)
+  );
+  assign io_sourceB_bits_address =
+    {_issueArb_io_out_bits_tag, _issueArb_io_out_bits_set, 6'h0};
+  assign io_sourceB_bits_data = {254'h0, _issueArb_io_out_bits_alias, 1'h0};
+  assign io_task_ready = io_task_ready_0;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/SplittedSRAM_3.sv b/flow/designs/src/xiangshan_coupledl2/deps/SplittedSRAM_3.sv
new file mode 100644
index 0000000000..f73f3fa128
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/SplittedSRAM_3.sv
@@ -0,0 +1,137 @@
+// Generated by CIRCT firtool-1.135.0
+module SplittedSRAM_3(
+  input          clock,
+  input          reset,
+  output         io_r_req_ready,
+  input          io_r_req_valid,
+  input  [7:0]   io_r_req_bits_setIdx,
+  output [40:0]  io_r_resp_data_0,
+  output [40:0]  io_r_resp_data_1,
+  output [40:0]  io_r_resp_data_2,
+  output [40:0]  io_r_resp_data_3,
+  output [40:0]  io_r_resp_data_4,
+  output [40:0]  io_r_resp_data_5,
+  output [40:0]  io_r_resp_data_6,
+  output [40:0]  io_r_resp_data_7,
+  output         io_w_req_ready,
+  input          io_w_req_valid,
+  input  [7:0]   io_w_req_bits_setIdx,
+  input  [40:0]  io_w_req_bits_data_0,
+  input  [40:0]  io_w_req_bits_data_1,
+  input  [40:0]  io_w_req_bits_data_2,
+  input  [40:0]  io_w_req_bits_data_3,
+  input  [40:0]  io_w_req_bits_data_4,
+  input  [40:0]  io_w_req_bits_data_5,
+  input  [40:0]  io_w_req_bits_data_6,
+  input  [40:0]  io_w_req_bits_data_7,
+  input  [7:0]   io_w_req_bits_waymask,
+  input  [8:0]   boreChildrenBd_bore_addr,
+  input  [8:0]   boreChildrenBd_bore_addr_rd,
+  input  [163:0] boreChildrenBd_bore_wdata,
+  input  [3:0]   boreChildrenBd_bore_wmask,
+  input          boreChildrenBd_bore_re,
+  input          boreChildrenBd_bore_we,
+  output [163:0] boreChildrenBd_bore_rdata,
+  input          boreChildrenBd_bore_ack,
+  input          boreChildrenBd_bore_selectedOH,
+  input  [1:0]   boreChildrenBd_bore_array,
+  input  [8:0]   boreChildrenBd_bore_1_addr,
+  input  [8:0]   boreChildrenBd_bore_1_addr_rd,
+  input  [163:0] boreChildrenBd_bore_1_wdata,
+  input  [3:0]   boreChildrenBd_bore_1_wmask,
+  input          boreChildrenBd_bore_1_re,
+  input          boreChildrenBd_bore_1_we,
+  output [163:0] boreChildrenBd_bore_1_rdata,
+  input          boreChildrenBd_bore_1_ack,
+  input          boreChildrenBd_bore_1_selectedOH,
+  input  [1:0]   boreChildrenBd_bore_1_array,
+  input          sigFromSrams_bore_ram_hold,
+  input          sigFromSrams_bore_ram_bypass,
+  input          sigFromSrams_bore_ram_bp_clken,
+  input          sigFromSrams_bore_ram_aux_clk,
+  input          sigFromSrams_bore_ram_aux_ckbp,
+  input          sigFromSrams_bore_ram_mcp_hold,
+  input          sigFromSrams_bore_cgen,
+  input          sigFromSrams_bore_1_ram_hold,
+  input          sigFromSrams_bore_1_ram_bypass,
+  input          sigFromSrams_bore_1_ram_bp_clken,
+  input          sigFromSrams_bore_1_ram_aux_clk,
+  input          sigFromSrams_bore_1_ram_aux_ckbp,
+  input          sigFromSrams_bore_1_ram_mcp_hold,
+  input          sigFromSrams_bore_1_cgen
+);
+
+  SRAMTemplate_241 array_0_0_0 (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_ready                 (io_r_req_ready),
+    .io_r_req_valid                 (io_r_req_valid),
+    .io_r_req_bits_setIdx           (io_r_req_bits_setIdx),
+    .io_r_resp_data_0               (io_r_resp_data_0),
+    .io_r_resp_data_1               (io_r_resp_data_1),
+    .io_r_resp_data_2               (io_r_resp_data_2),
+    .io_r_resp_data_3               (io_r_resp_data_3),
+    .io_w_req_valid                 (io_w_req_valid),
+    .io_w_req_bits_setIdx           (io_w_req_bits_setIdx),
+    .io_w_req_bits_data_0           (io_w_req_bits_data_0),
+    .io_w_req_bits_data_1           (io_w_req_bits_data_1),
+    .io_w_req_bits_data_2           (io_w_req_bits_data_2),
+    .io_w_req_bits_data_3           (io_w_req_bits_data_3),
+    .io_w_req_bits_waymask          (io_w_req_bits_waymask[3:0]),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_cgen),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_array)
+  );
+  SRAMTemplate_241 array_0_1_0 (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_r_req_ready                 (/* unused */),
+    .io_r_req_valid                 (io_r_req_valid),
+    .io_r_req_bits_setIdx           (io_r_req_bits_setIdx),
+    .io_r_resp_data_0               (io_r_resp_data_4),
+    .io_r_resp_data_1               (io_r_resp_data_5),
+    .io_r_resp_data_2               (io_r_resp_data_6),
+    .io_r_resp_data_3               (io_r_resp_data_7),
+    .io_w_req_valid                 (io_w_req_valid),
+    .io_w_req_bits_setIdx           (io_w_req_bits_setIdx),
+    .io_w_req_bits_data_0           (io_w_req_bits_data_4),
+    .io_w_req_bits_data_1           (io_w_req_bits_data_5),
+    .io_w_req_bits_data_2           (io_w_req_bits_data_6),
+    .io_w_req_bits_data_3           (io_w_req_bits_data_7),
+    .io_w_req_bits_waymask          (io_w_req_bits_waymask[7:4]),
+    .io_broadcast_ram_hold          (sigFromSrams_bore_1_ram_hold),
+    .io_broadcast_ram_bypass        (sigFromSrams_bore_1_ram_bypass),
+    .io_broadcast_ram_bp_clken      (sigFromSrams_bore_1_ram_bp_clken),
+    .io_broadcast_ram_aux_clk       (sigFromSrams_bore_1_ram_aux_clk),
+    .io_broadcast_ram_aux_ckbp      (sigFromSrams_bore_1_ram_aux_ckbp),
+    .io_broadcast_ram_mcp_hold      (sigFromSrams_bore_1_ram_mcp_hold),
+    .io_broadcast_ram_ctl           (64'h0),
+    .io_broadcast_cgen              (sigFromSrams_bore_1_cgen),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_1_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_1_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_1_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_1_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_1_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_1_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_1_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_1_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_1_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_1_array)
+  );
+  assign io_w_req_ready = 1'h1;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TXDAT.sv b/flow/designs/src/xiangshan_coupledl2/deps/TXDAT.sv
new file mode 100644
index 0000000000..21a038d1ef
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TXDAT.sv
@@ -0,0 +1,530 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TXDAT(
+  input          clock,
+  input          reset,
+  output         io_in_ready,
+  input          io_in_valid,
+  input  [2:0]   io_in_bits_task_channel,
+  input  [2:0]   io_in_bits_task_txChannel,
+  input  [7:0]   io_in_bits_task_set,
+  input  [33:0]  io_in_bits_task_tag,
+  input  [5:0]   io_in_bits_task_off,
+  input          io_in_bits_task_alias,
+  input  [43:0]  io_in_bits_task_vaddr,
+  input          io_in_bits_task_isKeyword,
+  input  [3:0]   io_in_bits_task_opcode,
+  input  [2:0]   io_in_bits_task_param,
+  input  [2:0]   io_in_bits_task_size,
+  input  [6:0]   io_in_bits_task_sourceId,
+  input  [1:0]   io_in_bits_task_bufIdx,
+  input          io_in_bits_task_needProbeAckData,
+  input          io_in_bits_task_denied,
+  input          io_in_bits_task_corrupt,
+  input          io_in_bits_task_mshrTask,
+  input  [7:0]   io_in_bits_task_mshrId,
+  input          io_in_bits_task_aliasTask,
+  input          io_in_bits_task_useProbeData,
+  input          io_in_bits_task_mshrRetry,
+  input          io_in_bits_task_readProbeDataDown,
+  input          io_in_bits_task_fromL2pft,
+  input          io_in_bits_task_needHint,
+  input          io_in_bits_task_dirty,
+  input  [2:0]   io_in_bits_task_way,
+  input          io_in_bits_task_meta_dirty,
+  input  [1:0]   io_in_bits_task_meta_state,
+  input          io_in_bits_task_meta_clients,
+  input          io_in_bits_task_meta_alias,
+  input          io_in_bits_task_meta_prefetch,
+  input  [3:0]   io_in_bits_task_meta_prefetchSrc,
+  input          io_in_bits_task_meta_accessed,
+  input          io_in_bits_task_meta_tagErr,
+  input          io_in_bits_task_meta_dataErr,
+  input          io_in_bits_task_metaWen,
+  input          io_in_bits_task_tagWen,
+  input          io_in_bits_task_dsWen,
+  input  [7:0]   io_in_bits_task_wayMask,
+  input          io_in_bits_task_replTask,
+  input          io_in_bits_task_cmoTask,
+  input          io_in_bits_task_cmoAll,
+  input  [4:0]   io_in_bits_task_reqSource,
+  input          io_in_bits_task_mergeA,
+  input  [5:0]   io_in_bits_task_aMergeTask_off,
+  input          io_in_bits_task_aMergeTask_alias,
+  input  [43:0]  io_in_bits_task_aMergeTask_vaddr,
+  input          io_in_bits_task_aMergeTask_isKeyword,
+  input  [2:0]   io_in_bits_task_aMergeTask_opcode,
+  input  [2:0]   io_in_bits_task_aMergeTask_param,
+  input  [6:0]   io_in_bits_task_aMergeTask_sourceId,
+  input          io_in_bits_task_aMergeTask_meta_dirty,
+  input  [1:0]   io_in_bits_task_aMergeTask_meta_state,
+  input          io_in_bits_task_aMergeTask_meta_clients,
+  input          io_in_bits_task_aMergeTask_meta_alias,
+  input          io_in_bits_task_aMergeTask_meta_prefetch,
+  input  [3:0]   io_in_bits_task_aMergeTask_meta_prefetchSrc,
+  input          io_in_bits_task_aMergeTask_meta_accessed,
+  input          io_in_bits_task_aMergeTask_meta_tagErr,
+  input          io_in_bits_task_aMergeTask_meta_dataErr,
+  input          io_in_bits_task_snpHitRelease,
+  input          io_in_bits_task_snpHitReleaseToInval,
+  input          io_in_bits_task_snpHitReleaseToClean,
+  input          io_in_bits_task_snpHitReleaseWithData,
+  input  [7:0]   io_in_bits_task_snpHitReleaseIdx,
+  input          io_in_bits_task_snpHitReleaseMeta_dirty,
+  input  [1:0]   io_in_bits_task_snpHitReleaseMeta_state,
+  input          io_in_bits_task_snpHitReleaseMeta_clients,
+  input          io_in_bits_task_snpHitReleaseMeta_alias,
+  input          io_in_bits_task_snpHitReleaseMeta_prefetch,
+  input  [3:0]   io_in_bits_task_snpHitReleaseMeta_prefetchSrc,
+  input          io_in_bits_task_snpHitReleaseMeta_accessed,
+  input          io_in_bits_task_snpHitReleaseMeta_tagErr,
+  input          io_in_bits_task_snpHitReleaseMeta_dataErr,
+  input  [10:0]  io_in_bits_task_tgtID,
+  input  [10:0]  io_in_bits_task_srcID,
+  input  [11:0]  io_in_bits_task_txnID,
+  input  [10:0]  io_in_bits_task_homeNID,
+  input  [11:0]  io_in_bits_task_dbID,
+  input  [10:0]  io_in_bits_task_fwdNID,
+  input  [11:0]  io_in_bits_task_fwdTxnID,
+  input  [6:0]   io_in_bits_task_chiOpcode,
+  input  [2:0]   io_in_bits_task_resp,
+  input  [2:0]   io_in_bits_task_fwdState,
+  input  [3:0]   io_in_bits_task_pCrdType,
+  input          io_in_bits_task_retToSrc,
+  input          io_in_bits_task_likelyshared,
+  input          io_in_bits_task_expCompAck,
+  input          io_in_bits_task_allowRetry,
+  input          io_in_bits_task_memAttr_allocate,
+  input          io_in_bits_task_memAttr_cacheable,
+  input          io_in_bits_task_memAttr_device,
+  input          io_in_bits_task_memAttr_ewa,
+  input          io_in_bits_task_traceTag,
+  input  [511:0] io_in_bits_data_data,
+  input          io_out_ready,
+  output         io_out_valid,
+  output [10:0]  io_out_bits_tgtID,
+  output [10:0]  io_out_bits_srcID,
+  output [11:0]  io_out_bits_txnID,
+  output [10:0]  io_out_bits_homeNID,
+  output [3:0]   io_out_bits_opcode,
+  output [1:0]   io_out_bits_respErr,
+  output [2:0]   io_out_bits_resp,
+  output [3:0]   io_out_bits_dataSource,
+  output [11:0]  io_out_bits_dbID,
+  output [1:0]   io_out_bits_ccID,
+  output [1:0]   io_out_bits_dataID,
+  output         io_out_bits_traceTag,
+  output [31:0]  io_out_bits_be,
+  output [255:0] io_out_bits_data,
+  output [31:0]  io_out_bits_dataCheck,
+  output [3:0]   io_out_bits_poison,
+  input          io_pipeStatusVec_1_valid,
+  input  [2:0]   io_pipeStatusVec_1_bits_channel,
+  input  [2:0]   io_pipeStatusVec_1_bits_txChannel,
+  input          io_pipeStatusVec_1_bits_mshrTask,
+  input          io_pipeStatusVec_2_valid,
+  input  [2:0]   io_pipeStatusVec_2_bits_channel,
+  input  [2:0]   io_pipeStatusVec_2_bits_txChannel,
+  input          io_pipeStatusVec_2_bits_mshrTask,
+  input          io_pipeStatusVec_3_valid,
+  input  [2:0]   io_pipeStatusVec_3_bits_channel,
+  input  [2:0]   io_pipeStatusVec_3_bits_txChannel,
+  input          io_pipeStatusVec_3_bits_mshrTask,
+  input          io_pipeStatusVec_4_valid,
+  input  [2:0]   io_pipeStatusVec_4_bits_channel,
+  input  [2:0]   io_pipeStatusVec_4_bits_txChannel,
+  input          io_pipeStatusVec_4_bits_mshrTask,
+  output         io_toReqArb_blockMSHRReqEntrance,
+  output         io_toReqArb_blockSinkBReqEntrance
+);
+
+  wire [1:0]   beatsOH;
+  wire [255:0] _queueData1_io_deq_bits_data;
+  wire [255:0] _queueData0_io_deq_bits_data;
+  wire         _queue_io_deq_valid;
+  wire [5:0]   _queue_io_deq_bits_off;
+  wire         _queue_io_deq_bits_corrupt;
+  wire [10:0]  _queue_io_deq_bits_tgtID;
+  wire [10:0]  _queue_io_deq_bits_srcID;
+  wire [11:0]  _queue_io_deq_bits_txnID;
+  wire [10:0]  _queue_io_deq_bits_homeNID;
+  wire [11:0]  _queue_io_deq_bits_dbID;
+  wire [6:0]   _queue_io_deq_bits_chiOpcode;
+  wire [2:0]   _queue_io_deq_bits_resp;
+  wire [2:0]   _queue_io_deq_bits_fwdState;
+  wire         _queue_io_deq_bits_traceTag;
+  wire [4:0]   _queue_io_count;
+  wire [4:0]   _inflightCnt_T_30 =
+    5'({3'h0,
+        2'(2'({1'h0,
+               io_pipeStatusVec_4_valid & io_pipeStatusVec_4_bits_txChannel[2]
+                 & (io_pipeStatusVec_4_bits_channel[1]
+                    | io_pipeStatusVec_4_bits_mshrTask)}
+              + {1'h0,
+                 io_pipeStatusVec_3_valid & io_pipeStatusVec_3_bits_txChannel[2]
+                   & (io_pipeStatusVec_3_bits_channel[1]
+                      | io_pipeStatusVec_3_bits_mshrTask)})
+           + 2'({1'h0,
+                 io_pipeStatusVec_2_valid
+                   & (io_pipeStatusVec_2_bits_mshrTask
+                        ? io_pipeStatusVec_2_bits_txChannel[2]
+                        : io_pipeStatusVec_2_bits_channel[1])}
+                + {1'h0,
+                   io_pipeStatusVec_1_valid
+                     & (io_pipeStatusVec_1_bits_mshrTask
+                          ? io_pipeStatusVec_1_bits_txChannel[2]
+                          : io_pipeStatusVec_1_bits_channel[1])}))} + _queue_io_count);
+  reg          beatValids_0;
+  reg          beatValids_1;
+  assign beatsOH = {beatValids_1, beatValids_0};
+  reg  [5:0]   taskR_task_off;
+  reg          taskR_task_corrupt;
+  reg  [10:0]  taskR_task_tgtID;
+  reg  [10:0]  taskR_task_srcID;
+  reg  [11:0]  taskR_task_txnID;
+  reg  [10:0]  taskR_task_homeNID;
+  reg  [11:0]  taskR_task_dbID;
+  reg  [6:0]   taskR_task_chiOpcode;
+  reg  [2:0]   taskR_task_resp;
+  reg  [2:0]   taskR_task_fwdState;
+  reg          taskR_task_traceTag;
+  reg  [511:0] taskR_data_data;
+  wire [255:0] beat = beatValids_0 ? taskR_data_data[255:0] : taskR_data_data[511:256];
+  wire         io_out_bits_deassertBE =
+    taskR_task_chiOpcode == 7'h2 & taskR_task_resp == 3'h0 | taskR_task_chiOpcode == 7'h7;
+  wire         _GEN = ~(|beatsOH) & _queue_io_deq_valid;
+  wire [1:0]   _next_beatsOH_T = ~(beatValids_0 ? 2'h1 : {beatValids_1, 1'h0});
+  wire         _GEN_0 = io_out_ready & (|beatsOH);
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      beatValids_0 <= 1'h0;
+      beatValids_1 <= 1'h0;
+      taskR_task_off <= 6'h0;
+      taskR_task_corrupt <= 1'h0;
+      taskR_task_tgtID <= 11'h0;
+      taskR_task_srcID <= 11'h0;
+      taskR_task_txnID <= 12'h0;
+      taskR_task_homeNID <= 11'h0;
+      taskR_task_dbID <= 12'h0;
+      taskR_task_chiOpcode <= 7'h0;
+      taskR_task_resp <= 3'h0;
+      taskR_task_fwdState <= 3'h0;
+      taskR_task_traceTag <= 1'h0;
+      taskR_data_data <= 512'h0;
+    end
+    else begin
+      beatValids_0 <= _GEN_0 ? beatValids_0 & _next_beatsOH_T[0] : _GEN | beatValids_0;
+      beatValids_1 <= _GEN_0 ? beatValids_1 & _next_beatsOH_T[1] : _GEN | beatValids_1;
+      if (_GEN) begin
+        taskR_task_off <= _queue_io_deq_bits_off;
+        taskR_task_corrupt <= _queue_io_deq_bits_corrupt;
+        taskR_task_tgtID <= _queue_io_deq_bits_tgtID;
+        taskR_task_srcID <= _queue_io_deq_bits_srcID;
+        taskR_task_txnID <= _queue_io_deq_bits_txnID;
+        taskR_task_homeNID <= _queue_io_deq_bits_homeNID;
+        taskR_task_dbID <= _queue_io_deq_bits_dbID;
+        taskR_task_chiOpcode <= _queue_io_deq_bits_chiOpcode;
+        taskR_task_resp <= _queue_io_deq_bits_resp;
+        taskR_task_fwdState <= _queue_io_deq_bits_fwdState;
+        taskR_task_traceTag <= _queue_io_deq_bits_traceTag;
+        taskR_data_data <= {_queueData1_io_deq_bits_data, _queueData0_io_deq_bits_data};
+      end
+    end
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:28];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h1D; i += 5'h1) begin
+          _RANDOM[i] = `RANDOM;
+        end
+        beatValids_0 = _RANDOM[5'h0][0];
+        beatValids_1 = _RANDOM[5'h0][1];
+        taskR_task_off = _RANDOM[5'h1][23:18];
+        taskR_task_corrupt = _RANDOM[5'h3][27];
+        taskR_task_tgtID = {_RANDOM[5'h8][31:23], _RANDOM[5'h9][1:0]};
+        taskR_task_srcID = _RANDOM[5'h9][12:2];
+        taskR_task_txnID = _RANDOM[5'h9][24:13];
+        taskR_task_homeNID = {_RANDOM[5'h9][31:25], _RANDOM[5'hA][3:0]};
+        taskR_task_dbID = _RANDOM[5'hA][15:4];
+        taskR_task_chiOpcode = _RANDOM[5'hB][13:7];
+        taskR_task_resp = _RANDOM[5'hB][16:14];
+        taskR_task_fwdState = _RANDOM[5'hB][19:17];
+        taskR_task_traceTag = _RANDOM[5'hC][0];
+        taskR_data_data =
+          {_RANDOM[5'hC][31:1],
+           _RANDOM[5'hD],
+           _RANDOM[5'hE],
+           _RANDOM[5'hF],
+           _RANDOM[5'h10],
+           _RANDOM[5'h11],
+           _RANDOM[5'h12],
+           _RANDOM[5'h13],
+           _RANDOM[5'h14],
+           _RANDOM[5'h15],
+           _RANDOM[5'h16],
+           _RANDOM[5'h17],
+           _RANDOM[5'h18],
+           _RANDOM[5'h19],
+           _RANDOM[5'h1A],
+           _RANDOM[5'h1B],
+           _RANDOM[5'h1C][0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset) begin
+        beatValids_0 = 1'h0;
+        beatValids_1 = 1'h0;
+        taskR_task_off = 6'h0;
+        taskR_task_corrupt = 1'h0;
+        taskR_task_tgtID = 11'h0;
+        taskR_task_srcID = 11'h0;
+        taskR_task_txnID = 12'h0;
+        taskR_task_homeNID = 11'h0;
+        taskR_task_dbID = 12'h0;
+        taskR_task_chiOpcode = 7'h0;
+        taskR_task_resp = 3'h0;
+        taskR_task_fwdState = 3'h0;
+        taskR_task_traceTag = 1'h0;
+        taskR_data_data = 512'h0;
+      end
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  Queue16_TaskBundle queue (
+    .clock                                     (clock),
+    .reset                                     (reset),
+    .io_enq_ready                              (io_in_ready),
+    .io_enq_valid                              (io_in_valid),
+    .io_enq_bits_channel                       (io_in_bits_task_channel),
+    .io_enq_bits_txChannel                     (io_in_bits_task_txChannel),
+    .io_enq_bits_set                           (io_in_bits_task_set),
+    .io_enq_bits_tag                           (io_in_bits_task_tag),
+    .io_enq_bits_off                           (io_in_bits_task_off),
+    .io_enq_bits_alias                         (io_in_bits_task_alias),
+    .io_enq_bits_vaddr                         (io_in_bits_task_vaddr),
+    .io_enq_bits_isKeyword                     (io_in_bits_task_isKeyword),
+    .io_enq_bits_opcode                        (io_in_bits_task_opcode),
+    .io_enq_bits_param                         (io_in_bits_task_param),
+    .io_enq_bits_size                          (io_in_bits_task_size),
+    .io_enq_bits_sourceId                      (io_in_bits_task_sourceId),
+    .io_enq_bits_bufIdx                        (io_in_bits_task_bufIdx),
+    .io_enq_bits_needProbeAckData              (io_in_bits_task_needProbeAckData),
+    .io_enq_bits_denied                        (io_in_bits_task_denied),
+    .io_enq_bits_corrupt                       (io_in_bits_task_corrupt),
+    .io_enq_bits_mshrTask                      (io_in_bits_task_mshrTask),
+    .io_enq_bits_mshrId                        (io_in_bits_task_mshrId),
+    .io_enq_bits_aliasTask                     (io_in_bits_task_aliasTask),
+    .io_enq_bits_useProbeData                  (io_in_bits_task_useProbeData),
+    .io_enq_bits_mshrRetry                     (io_in_bits_task_mshrRetry),
+    .io_enq_bits_readProbeDataDown             (io_in_bits_task_readProbeDataDown),
+    .io_enq_bits_fromL2pft                     (io_in_bits_task_fromL2pft),
+    .io_enq_bits_needHint                      (io_in_bits_task_needHint),
+    .io_enq_bits_dirty                         (io_in_bits_task_dirty),
+    .io_enq_bits_way                           (io_in_bits_task_way),
+    .io_enq_bits_meta_dirty                    (io_in_bits_task_meta_dirty),
+    .io_enq_bits_meta_state                    (io_in_bits_task_meta_state),
+    .io_enq_bits_meta_clients                  (io_in_bits_task_meta_clients),
+    .io_enq_bits_meta_alias                    (io_in_bits_task_meta_alias),
+    .io_enq_bits_meta_prefetch                 (io_in_bits_task_meta_prefetch),
+    .io_enq_bits_meta_prefetchSrc              (io_in_bits_task_meta_prefetchSrc),
+    .io_enq_bits_meta_accessed                 (io_in_bits_task_meta_accessed),
+    .io_enq_bits_meta_tagErr                   (io_in_bits_task_meta_tagErr),
+    .io_enq_bits_meta_dataErr                  (io_in_bits_task_meta_dataErr),
+    .io_enq_bits_metaWen                       (io_in_bits_task_metaWen),
+    .io_enq_bits_tagWen                        (io_in_bits_task_tagWen),
+    .io_enq_bits_dsWen                         (io_in_bits_task_dsWen),
+    .io_enq_bits_wayMask                       (io_in_bits_task_wayMask),
+    .io_enq_bits_replTask                      (io_in_bits_task_replTask),
+    .io_enq_bits_cmoTask                       (io_in_bits_task_cmoTask),
+    .io_enq_bits_cmoAll                        (io_in_bits_task_cmoAll),
+    .io_enq_bits_reqSource                     (io_in_bits_task_reqSource),
+    .io_enq_bits_mergeA                        (io_in_bits_task_mergeA),
+    .io_enq_bits_aMergeTask_off                (io_in_bits_task_aMergeTask_off),
+    .io_enq_bits_aMergeTask_alias              (io_in_bits_task_aMergeTask_alias),
+    .io_enq_bits_aMergeTask_vaddr              (io_in_bits_task_aMergeTask_vaddr),
+    .io_enq_bits_aMergeTask_isKeyword          (io_in_bits_task_aMergeTask_isKeyword),
+    .io_enq_bits_aMergeTask_opcode             (io_in_bits_task_aMergeTask_opcode),
+    .io_enq_bits_aMergeTask_param              (io_in_bits_task_aMergeTask_param),
+    .io_enq_bits_aMergeTask_sourceId           (io_in_bits_task_aMergeTask_sourceId),
+    .io_enq_bits_aMergeTask_meta_dirty         (io_in_bits_task_aMergeTask_meta_dirty),
+    .io_enq_bits_aMergeTask_meta_state         (io_in_bits_task_aMergeTask_meta_state),
+    .io_enq_bits_aMergeTask_meta_clients       (io_in_bits_task_aMergeTask_meta_clients),
+    .io_enq_bits_aMergeTask_meta_alias         (io_in_bits_task_aMergeTask_meta_alias),
+    .io_enq_bits_aMergeTask_meta_prefetch      (io_in_bits_task_aMergeTask_meta_prefetch),
+    .io_enq_bits_aMergeTask_meta_prefetchSrc
+      (io_in_bits_task_aMergeTask_meta_prefetchSrc),
+    .io_enq_bits_aMergeTask_meta_accessed      (io_in_bits_task_aMergeTask_meta_accessed),
+    .io_enq_bits_aMergeTask_meta_tagErr        (io_in_bits_task_aMergeTask_meta_tagErr),
+    .io_enq_bits_aMergeTask_meta_dataErr       (io_in_bits_task_aMergeTask_meta_dataErr),
+    .io_enq_bits_snpHitRelease                 (io_in_bits_task_snpHitRelease),
+    .io_enq_bits_snpHitReleaseToInval          (io_in_bits_task_snpHitReleaseToInval),
+    .io_enq_bits_snpHitReleaseToClean          (io_in_bits_task_snpHitReleaseToClean),
+    .io_enq_bits_snpHitReleaseWithData         (io_in_bits_task_snpHitReleaseWithData),
+    .io_enq_bits_snpHitReleaseIdx              (io_in_bits_task_snpHitReleaseIdx),
+    .io_enq_bits_snpHitReleaseMeta_dirty       (io_in_bits_task_snpHitReleaseMeta_dirty),
+    .io_enq_bits_snpHitReleaseMeta_state       (io_in_bits_task_snpHitReleaseMeta_state),
+    .io_enq_bits_snpHitReleaseMeta_clients
+      (io_in_bits_task_snpHitReleaseMeta_clients),
+    .io_enq_bits_snpHitReleaseMeta_alias       (io_in_bits_task_snpHitReleaseMeta_alias),
+    .io_enq_bits_snpHitReleaseMeta_prefetch
+      (io_in_bits_task_snpHitReleaseMeta_prefetch),
+    .io_enq_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_bits_task_snpHitReleaseMeta_prefetchSrc),
+    .io_enq_bits_snpHitReleaseMeta_accessed
+      (io_in_bits_task_snpHitReleaseMeta_accessed),
+    .io_enq_bits_snpHitReleaseMeta_tagErr      (io_in_bits_task_snpHitReleaseMeta_tagErr),
+    .io_enq_bits_snpHitReleaseMeta_dataErr
+      (io_in_bits_task_snpHitReleaseMeta_dataErr),
+    .io_enq_bits_tgtID                         (io_in_bits_task_tgtID),
+    .io_enq_bits_srcID                         (io_in_bits_task_srcID),
+    .io_enq_bits_txnID                         (io_in_bits_task_txnID),
+    .io_enq_bits_homeNID                       (io_in_bits_task_homeNID),
+    .io_enq_bits_dbID                          (io_in_bits_task_dbID),
+    .io_enq_bits_fwdNID                        (io_in_bits_task_fwdNID),
+    .io_enq_bits_fwdTxnID                      (io_in_bits_task_fwdTxnID),
+    .io_enq_bits_chiOpcode                     (io_in_bits_task_chiOpcode),
+    .io_enq_bits_resp                          (io_in_bits_task_resp),
+    .io_enq_bits_fwdState                      (io_in_bits_task_fwdState),
+    .io_enq_bits_pCrdType                      (io_in_bits_task_pCrdType),
+    .io_enq_bits_retToSrc                      (io_in_bits_task_retToSrc),
+    .io_enq_bits_likelyshared                  (io_in_bits_task_likelyshared),
+    .io_enq_bits_expCompAck                    (io_in_bits_task_expCompAck),
+    .io_enq_bits_allowRetry                    (io_in_bits_task_allowRetry),
+    .io_enq_bits_memAttr_allocate              (io_in_bits_task_memAttr_allocate),
+    .io_enq_bits_memAttr_cacheable             (io_in_bits_task_memAttr_cacheable),
+    .io_enq_bits_memAttr_device                (io_in_bits_task_memAttr_device),
+    .io_enq_bits_memAttr_ewa                   (io_in_bits_task_memAttr_ewa),
+    .io_enq_bits_traceTag                      (io_in_bits_task_traceTag),
+    .io_deq_ready                              (~(|beatsOH)),
+    .io_deq_valid                              (_queue_io_deq_valid),
+    .io_deq_bits_off                           (_queue_io_deq_bits_off),
+    .io_deq_bits_corrupt                       (_queue_io_deq_bits_corrupt),
+    .io_deq_bits_tgtID                         (_queue_io_deq_bits_tgtID),
+    .io_deq_bits_srcID                         (_queue_io_deq_bits_srcID),
+    .io_deq_bits_txnID                         (_queue_io_deq_bits_txnID),
+    .io_deq_bits_homeNID                       (_queue_io_deq_bits_homeNID),
+    .io_deq_bits_dbID                          (_queue_io_deq_bits_dbID),
+    .io_deq_bits_chiOpcode                     (_queue_io_deq_bits_chiOpcode),
+    .io_deq_bits_resp                          (_queue_io_deq_bits_resp),
+    .io_deq_bits_fwdState                      (_queue_io_deq_bits_fwdState),
+    .io_deq_bits_traceTag                      (_queue_io_deq_bits_traceTag),
+    .io_count                                  (_queue_io_count)
+  );
+  Queue16_DSBeat queueData0 (
+    .clock            (clock),
+    .reset            (reset),
+    .io_enq_valid     (io_in_valid),
+    .io_enq_bits_data (io_in_bits_data_data[255:0]),
+    .io_deq_ready     (~(|beatsOH)),
+    .io_deq_bits_data (_queueData0_io_deq_bits_data)
+  );
+  Queue16_DSBeat queueData1 (
+    .clock            (clock),
+    .reset            (reset),
+    .io_enq_valid     (io_in_valid),
+    .io_enq_bits_data (io_in_bits_data_data[511:256]),
+    .io_deq_ready     (~(|beatsOH)),
+    .io_deq_bits_data (_queueData1_io_deq_bits_data)
+  );
+  assign io_out_valid = |beatsOH;
+  assign io_out_bits_tgtID = taskR_task_tgtID;
+  assign io_out_bits_srcID = taskR_task_srcID;
+  assign io_out_bits_txnID = taskR_task_txnID;
+  assign io_out_bits_homeNID = taskR_task_homeNID;
+  assign io_out_bits_opcode = taskR_task_chiOpcode[3:0];
+  assign io_out_bits_respErr = {taskR_task_corrupt, 1'h0};
+  assign io_out_bits_resp = taskR_task_resp;
+  assign io_out_bits_dataSource = {1'h0, taskR_task_fwdState};
+  assign io_out_bits_dbID = taskR_task_dbID;
+  assign io_out_bits_ccID = taskR_task_off[5:4];
+  assign io_out_bits_dataID = {~beatValids_0, 1'h0};
+  assign io_out_bits_traceTag = taskR_task_traceTag;
+  assign io_out_bits_be = {32{~io_out_bits_deassertBE}};
+  assign io_out_bits_data = {256{~io_out_bits_deassertBE}} & beat;
+  assign io_out_bits_dataCheck =
+    {~(^({8{~io_out_bits_deassertBE}} & beat[255:248])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[247:240])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[239:232])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[231:224])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[223:216])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[215:208])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[207:200])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[199:192])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[191:184])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[183:176])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[175:168])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[167:160])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[159:152])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[151:144])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[143:136])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[135:128])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[127:120])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[119:112])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[111:104])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[103:96])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[95:88])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[87:80])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[79:72])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[71:64])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[63:56])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[55:48])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[47:40])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[39:32])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[31:24])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[23:16])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[15:8])),
+     ~(^({8{~io_out_bits_deassertBE}} & beat[7:0]))};
+  assign io_out_bits_poison = {4{taskR_task_corrupt}};
+  assign io_toReqArb_blockMSHRReqEntrance = _inflightCnt_T_30 > 5'hD;
+  assign io_toReqArb_blockSinkBReqEntrance = _inflightCnt_T_30[4];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TXREQ.sv b/flow/designs/src/xiangshan_coupledl2/deps/TXREQ.sv
new file mode 100644
index 0000000000..4d6b14874f
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TXREQ.sv
@@ -0,0 +1,175 @@
+// Generated by CIRCT firtool-1.135.0
+module TXREQ(
+  input         clock,
+  input         reset,
+  input         io_pipeReq_valid,
+  input  [10:0] io_pipeReq_bits_tgtID,
+  input  [10:0] io_pipeReq_bits_srcID,
+  input  [11:0] io_pipeReq_bits_txnID,
+  input  [6:0]  io_pipeReq_bits_opcode,
+  input  [47:0] io_pipeReq_bits_addr,
+  input         io_pipeReq_bits_likelyshared,
+  input         io_pipeReq_bits_allowRetry,
+  input  [3:0]  io_pipeReq_bits_pCrdType,
+  input         io_pipeReq_bits_memAttr_allocate,
+  input         io_pipeReq_bits_memAttr_cacheable,
+  input         io_pipeReq_bits_memAttr_device,
+  input         io_pipeReq_bits_memAttr_ewa,
+  input         io_pipeReq_bits_expCompAck,
+  output        io_mshrReq_ready,
+  input         io_mshrReq_valid,
+  input  [3:0]  io_mshrReq_bits_qos,
+  input  [10:0] io_mshrReq_bits_tgtID,
+  input  [11:0] io_mshrReq_bits_txnID,
+  input  [6:0]  io_mshrReq_bits_opcode,
+  input  [2:0]  io_mshrReq_bits_size,
+  input  [47:0] io_mshrReq_bits_addr,
+  input         io_mshrReq_bits_likelyshared,
+  input         io_mshrReq_bits_allowRetry,
+  input  [1:0]  io_mshrReq_bits_order,
+  input  [3:0]  io_mshrReq_bits_pCrdType,
+  input         io_mshrReq_bits_memAttr_allocate,
+  input         io_mshrReq_bits_memAttr_cacheable,
+  input         io_mshrReq_bits_memAttr_device,
+  input         io_mshrReq_bits_memAttr_ewa,
+  input         io_mshrReq_bits_snpAttr,
+  input         io_mshrReq_bits_expCompAck,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_qos,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [10:0] io_out_bits_returnNID,
+  output        io_out_bits_stashNIDValid,
+  output [11:0] io_out_bits_returnTxnID,
+  output [6:0]  io_out_bits_opcode,
+  output [47:0] io_out_bits_addr,
+  output        io_out_bits_ns,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_allowRetry,
+  output [1:0]  io_out_bits_order,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_device,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_snpAttr,
+  output [7:0]  io_out_bits_lpIDWithPadding,
+  output        io_out_bits_snoopMe,
+  output        io_out_bits_expCompAck,
+  output [1:0]  io_out_bits_tagOp,
+  output        io_out_bits_traceTag,
+  output        io_out_bits_mpam_perfMonGroup,
+  output [8:0]  io_out_bits_mpam_partID,
+  output        io_out_bits_mpam_mpamNS,
+  output [3:0]  io_out_bits_rsvdc,
+  input         io_pipeStatusVec_1_valid,
+  input  [2:0]  io_pipeStatusVec_1_bits_txChannel,
+  input         io_pipeStatusVec_1_bits_mshrTask,
+  input         io_pipeStatusVec_2_valid,
+  input  [2:0]  io_pipeStatusVec_2_bits_txChannel,
+  input         io_pipeStatusVec_2_bits_mshrTask,
+  input         io_pipeStatusVec_3_valid,
+  input  [2:0]  io_pipeStatusVec_3_bits_txChannel,
+  input         io_pipeStatusVec_3_bits_mshrTask,
+  input         io_pipeStatusVec_4_valid,
+  input  [2:0]  io_pipeStatusVec_4_bits_txChannel,
+  input         io_pipeStatusVec_4_bits_mshrTask,
+  output        io_toReqArb_blockMSHRReqEntrance
+);
+
+  wire [4:0] _queue_io_count;
+  wire [4:0] _inflightCnt_T_27 =
+    5'({2'h0,
+        3'(3'({1'h0,
+               2'({1'h0,
+                   io_pipeStatusVec_4_valid & io_pipeStatusVec_4_bits_mshrTask
+                     & io_pipeStatusVec_4_bits_txChannel[0]}
+                  + {1'h0,
+                     io_pipeStatusVec_3_valid & io_pipeStatusVec_3_bits_mshrTask
+                       & io_pipeStatusVec_3_bits_txChannel[0]})}
+              + 3'({1'h0,
+                    2'({1'h0,
+                        io_pipeStatusVec_2_valid & io_pipeStatusVec_2_bits_mshrTask
+                          & io_pipeStatusVec_2_bits_txChannel[0]}
+                       + {1'h0,
+                          io_pipeStatusVec_1_valid & io_pipeStatusVec_1_bits_mshrTask
+                            & io_pipeStatusVec_1_bits_txChannel[0]})} + 3'h1))
+           - {2'h0,
+              io_pipeStatusVec_1_valid
+                & ~(io_pipeStatusVec_1_bits_mshrTask
+                    & io_pipeStatusVec_1_bits_txChannel[0])})} + _queue_io_count);
+  Queue16_CHIREQ queue (
+    .clock                         (clock),
+    .reset                         (reset),
+    .io_enq_valid
+      (io_pipeReq_valid | io_mshrReq_valid & ~(_inflightCnt_T_27[4])),
+    .io_enq_bits_qos               (io_pipeReq_valid ? 4'hE : io_mshrReq_bits_qos),
+    .io_enq_bits_tgtID
+      (io_pipeReq_valid ? io_pipeReq_bits_tgtID : io_mshrReq_bits_tgtID),
+    .io_enq_bits_srcID             (io_pipeReq_valid ? io_pipeReq_bits_srcID : 11'h0),
+    .io_enq_bits_txnID
+      (io_pipeReq_valid ? io_pipeReq_bits_txnID : io_mshrReq_bits_txnID),
+    .io_enq_bits_opcode
+      (io_pipeReq_valid ? io_pipeReq_bits_opcode : io_mshrReq_bits_opcode),
+    .io_enq_bits_size              (io_pipeReq_valid ? 3'h0 : io_mshrReq_bits_size),
+    .io_enq_bits_addr
+      (io_pipeReq_valid ? io_pipeReq_bits_addr : io_mshrReq_bits_addr),
+    .io_enq_bits_likelyshared
+      (io_pipeReq_valid ? io_pipeReq_bits_likelyshared : io_mshrReq_bits_likelyshared),
+    .io_enq_bits_allowRetry
+      (io_pipeReq_valid ? io_pipeReq_bits_allowRetry : io_mshrReq_bits_allowRetry),
+    .io_enq_bits_order             (io_pipeReq_valid ? 2'h0 : io_mshrReq_bits_order),
+    .io_enq_bits_pCrdType
+      (io_pipeReq_valid ? io_pipeReq_bits_pCrdType : io_mshrReq_bits_pCrdType),
+    .io_enq_bits_memAttr_allocate
+      (io_pipeReq_valid
+         ? io_pipeReq_bits_memAttr_allocate
+         : io_mshrReq_bits_memAttr_allocate),
+    .io_enq_bits_memAttr_cacheable
+      (io_pipeReq_valid
+         ? io_pipeReq_bits_memAttr_cacheable
+         : io_mshrReq_bits_memAttr_cacheable),
+    .io_enq_bits_memAttr_device
+      (io_pipeReq_valid
+         ? io_pipeReq_bits_memAttr_device
+         : io_mshrReq_bits_memAttr_device),
+    .io_enq_bits_memAttr_ewa
+      (io_pipeReq_valid ? io_pipeReq_bits_memAttr_ewa : io_mshrReq_bits_memAttr_ewa),
+    .io_enq_bits_snpAttr           (io_pipeReq_valid | io_mshrReq_bits_snpAttr),
+    .io_enq_bits_expCompAck
+      (io_pipeReq_valid ? io_pipeReq_bits_expCompAck : io_mshrReq_bits_expCompAck),
+    .io_deq_ready                  (io_out_ready),
+    .io_deq_valid                  (io_out_valid),
+    .io_deq_bits_qos               (io_out_bits_qos),
+    .io_deq_bits_srcID             (io_out_bits_srcID),
+    .io_deq_bits_txnID             (io_out_bits_txnID),
+    .io_deq_bits_returnNID         (io_out_bits_returnNID),
+    .io_deq_bits_stashNIDValid     (io_out_bits_stashNIDValid),
+    .io_deq_bits_returnTxnID       (io_out_bits_returnTxnID),
+    .io_deq_bits_opcode            (io_out_bits_opcode),
+    .io_deq_bits_addr              (io_out_bits_addr),
+    .io_deq_bits_ns                (io_out_bits_ns),
+    .io_deq_bits_likelyshared      (io_out_bits_likelyshared),
+    .io_deq_bits_allowRetry        (io_out_bits_allowRetry),
+    .io_deq_bits_order             (io_out_bits_order),
+    .io_deq_bits_pCrdType          (io_out_bits_pCrdType),
+    .io_deq_bits_memAttr_allocate  (io_out_bits_memAttr_allocate),
+    .io_deq_bits_memAttr_cacheable (io_out_bits_memAttr_cacheable),
+    .io_deq_bits_memAttr_device    (io_out_bits_memAttr_device),
+    .io_deq_bits_memAttr_ewa       (io_out_bits_memAttr_ewa),
+    .io_deq_bits_snpAttr           (io_out_bits_snpAttr),
+    .io_deq_bits_lpIDWithPadding   (io_out_bits_lpIDWithPadding),
+    .io_deq_bits_snoopMe           (io_out_bits_snoopMe),
+    .io_deq_bits_expCompAck        (io_out_bits_expCompAck),
+    .io_deq_bits_tagOp             (io_out_bits_tagOp),
+    .io_deq_bits_traceTag          (io_out_bits_traceTag),
+    .io_deq_bits_mpam_perfMonGroup (io_out_bits_mpam_perfMonGroup),
+    .io_deq_bits_mpam_partID       (io_out_bits_mpam_partID),
+    .io_deq_bits_mpam_mpamNS       (io_out_bits_mpam_mpamNS),
+    .io_deq_bits_rsvdc             (io_out_bits_rsvdc),
+    .io_count                      (_queue_io_count)
+  );
+  assign io_mshrReq_ready = ~io_pipeReq_valid & ~(_inflightCnt_T_27[4]);
+  assign io_toReqArb_blockMSHRReqEntrance = _inflightCnt_T_27[4];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TXRSP.sv b/flow/designs/src/xiangshan_coupledl2/deps/TXRSP.sv
new file mode 100644
index 0000000000..040591d4a9
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TXRSP.sv
@@ -0,0 +1,120 @@
+// Generated by CIRCT firtool-1.135.0
+module TXRSP(
+  input         clock,
+  input         reset,
+  input         io_pipeRsp_valid,
+  input         io_pipeRsp_bits_denied,
+  input  [10:0] io_pipeRsp_bits_tgtID,
+  input  [10:0] io_pipeRsp_bits_srcID,
+  input  [11:0] io_pipeRsp_bits_txnID,
+  input  [11:0] io_pipeRsp_bits_dbID,
+  input  [6:0]  io_pipeRsp_bits_chiOpcode,
+  input  [2:0]  io_pipeRsp_bits_resp,
+  input  [2:0]  io_pipeRsp_bits_fwdState,
+  input  [3:0]  io_pipeRsp_bits_pCrdType,
+  input         io_pipeRsp_bits_traceTag,
+  output        io_mshrRsp_ready,
+  input         io_mshrRsp_valid,
+  input  [10:0] io_mshrRsp_bits_tgtID,
+  input  [11:0] io_mshrRsp_bits_txnID,
+  input  [4:0]  io_mshrRsp_bits_opcode,
+  input         io_mshrRsp_bits_traceTag,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_qos,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [4:0]  io_out_bits_opcode,
+  output [1:0]  io_out_bits_respErr,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output [2:0]  io_out_bits_cBusy,
+  output [11:0] io_out_bits_dbID,
+  output [3:0]  io_out_bits_pCrdType,
+  output [1:0]  io_out_bits_tagOp,
+  output        io_out_bits_traceTag,
+  input         io_pipeStatusVec_1_valid,
+  input  [2:0]  io_pipeStatusVec_1_bits_channel,
+  input  [2:0]  io_pipeStatusVec_1_bits_txChannel,
+  input         io_pipeStatusVec_1_bits_mshrTask,
+  input         io_pipeStatusVec_2_valid,
+  input  [2:0]  io_pipeStatusVec_2_bits_channel,
+  input  [2:0]  io_pipeStatusVec_2_bits_txChannel,
+  input         io_pipeStatusVec_2_bits_mshrTask,
+  input         io_pipeStatusVec_3_valid,
+  input  [2:0]  io_pipeStatusVec_3_bits_channel,
+  input  [2:0]  io_pipeStatusVec_3_bits_txChannel,
+  input         io_pipeStatusVec_3_bits_mshrTask,
+  input         io_pipeStatusVec_4_valid,
+  input  [2:0]  io_pipeStatusVec_4_bits_channel,
+  input  [2:0]  io_pipeStatusVec_4_bits_txChannel,
+  input         io_pipeStatusVec_4_bits_mshrTask,
+  output        io_toReqArb_blockMSHRReqEntrance,
+  output        io_toReqArb_blockSinkBReqEntrance
+);
+
+  wire [4:0] _queue_io_count;
+  wire [4:0] _inflightCnt_T_30 =
+    5'({3'h0,
+        2'(2'({1'h0,
+               io_pipeStatusVec_4_valid & io_pipeStatusVec_4_bits_txChannel[1]
+                 & (io_pipeStatusVec_4_bits_channel[1]
+                    | io_pipeStatusVec_4_bits_mshrTask)}
+              + {1'h0,
+                 io_pipeStatusVec_3_valid & io_pipeStatusVec_3_bits_txChannel[1]
+                   & (io_pipeStatusVec_3_bits_channel[1]
+                      | io_pipeStatusVec_3_bits_mshrTask)})
+           + 2'({1'h0,
+                 io_pipeStatusVec_2_valid
+                   & (io_pipeStatusVec_2_bits_mshrTask
+                        ? io_pipeStatusVec_2_bits_txChannel[1]
+                        : io_pipeStatusVec_2_bits_channel[1])}
+                + {1'h0,
+                   io_pipeStatusVec_1_valid
+                     & (io_pipeStatusVec_1_bits_mshrTask
+                          ? io_pipeStatusVec_1_bits_txChannel[1]
+                          : io_pipeStatusVec_1_bits_channel[1])}))} + _queue_io_count);
+  wire       _io_mshrRsp_ready_T_3 = _inflightCnt_T_30 < 5'hE;
+  Queue16_CHIRSP queue (
+    .clock                (clock),
+    .reset                (reset),
+    .io_enq_valid
+      (io_pipeRsp_valid | io_mshrRsp_valid & ~(_inflightCnt_T_30[4])
+       & _io_mshrRsp_ready_T_3),
+    .io_enq_bits_tgtID
+      (io_pipeRsp_valid ? io_pipeRsp_bits_tgtID : io_mshrRsp_bits_tgtID),
+    .io_enq_bits_srcID    (io_pipeRsp_valid ? io_pipeRsp_bits_srcID : 11'h0),
+    .io_enq_bits_txnID
+      (io_pipeRsp_valid ? io_pipeRsp_bits_txnID : io_mshrRsp_bits_txnID),
+    .io_enq_bits_opcode
+      (io_pipeRsp_valid ? io_pipeRsp_bits_chiOpcode[4:0] : io_mshrRsp_bits_opcode),
+    .io_enq_bits_respErr  ({2{io_pipeRsp_valid & io_pipeRsp_bits_denied}}),
+    .io_enq_bits_resp     (io_pipeRsp_valid ? io_pipeRsp_bits_resp : 3'h0),
+    .io_enq_bits_fwdState (io_pipeRsp_valid ? io_pipeRsp_bits_fwdState : 3'h0),
+    .io_enq_bits_dbID     (io_pipeRsp_valid ? io_pipeRsp_bits_dbID : 12'h0),
+    .io_enq_bits_pCrdType (io_pipeRsp_valid ? io_pipeRsp_bits_pCrdType : 4'h0),
+    .io_enq_bits_traceTag
+      (io_pipeRsp_valid ? io_pipeRsp_bits_traceTag : io_mshrRsp_bits_traceTag),
+    .io_deq_ready         (io_out_ready),
+    .io_deq_valid         (io_out_valid),
+    .io_deq_bits_qos      (io_out_bits_qos),
+    .io_deq_bits_tgtID    (io_out_bits_tgtID),
+    .io_deq_bits_srcID    (io_out_bits_srcID),
+    .io_deq_bits_txnID    (io_out_bits_txnID),
+    .io_deq_bits_opcode   (io_out_bits_opcode),
+    .io_deq_bits_respErr  (io_out_bits_respErr),
+    .io_deq_bits_resp     (io_out_bits_resp),
+    .io_deq_bits_fwdState (io_out_bits_fwdState),
+    .io_deq_bits_cBusy    (io_out_bits_cBusy),
+    .io_deq_bits_dbID     (io_out_bits_dbID),
+    .io_deq_bits_pCrdType (io_out_bits_pCrdType),
+    .io_deq_bits_tagOp    (io_out_bits_tagOp),
+    .io_deq_bits_traceTag (io_out_bits_traceTag),
+    .io_count             (_queue_io_count)
+  );
+  assign io_mshrRsp_ready =
+    ~io_pipeRsp_valid & ~(_inflightCnt_T_30[4]) & _io_mshrRsp_ready_T_3;
+  assign io_toReqArb_blockMSHRReqEntrance = _inflightCnt_T_30 > 5'hD;
+  assign io_toReqArb_blockSinkBReqEntrance = _inflightCnt_T_30[4];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_1.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_1.sv
new file mode 100644
index 0000000000..fb9ad90dc3
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_1.sv
@@ -0,0 +1,761 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_1(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [6:0]  io_in_0_bits_opcode,
+  input  [2:0]  io_in_0_bits_size,
+  input  [47:0] io_in_0_bits_addr,
+  input         io_in_0_bits_likelyshared,
+  input         io_in_0_bits_allowRetry,
+  input  [1:0]  io_in_0_bits_order,
+  input  [3:0]  io_in_0_bits_pCrdType,
+  input         io_in_0_bits_memAttr_allocate,
+  input         io_in_0_bits_memAttr_cacheable,
+  input         io_in_0_bits_memAttr_device,
+  input         io_in_0_bits_memAttr_ewa,
+  input         io_in_0_bits_snpAttr,
+  input         io_in_0_bits_expCompAck,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [11:0] io_in_1_bits_txnID,
+  input  [6:0]  io_in_1_bits_opcode,
+  input  [2:0]  io_in_1_bits_size,
+  input  [47:0] io_in_1_bits_addr,
+  input         io_in_1_bits_likelyshared,
+  input         io_in_1_bits_allowRetry,
+  input  [1:0]  io_in_1_bits_order,
+  input  [3:0]  io_in_1_bits_pCrdType,
+  input         io_in_1_bits_memAttr_allocate,
+  input         io_in_1_bits_memAttr_cacheable,
+  input         io_in_1_bits_memAttr_device,
+  input         io_in_1_bits_memAttr_ewa,
+  input         io_in_1_bits_snpAttr,
+  input         io_in_1_bits_expCompAck,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [10:0] io_in_2_bits_tgtID,
+  input  [11:0] io_in_2_bits_txnID,
+  input  [6:0]  io_in_2_bits_opcode,
+  input  [2:0]  io_in_2_bits_size,
+  input  [47:0] io_in_2_bits_addr,
+  input         io_in_2_bits_likelyshared,
+  input         io_in_2_bits_allowRetry,
+  input  [1:0]  io_in_2_bits_order,
+  input  [3:0]  io_in_2_bits_pCrdType,
+  input         io_in_2_bits_memAttr_allocate,
+  input         io_in_2_bits_memAttr_cacheable,
+  input         io_in_2_bits_memAttr_device,
+  input         io_in_2_bits_memAttr_ewa,
+  input         io_in_2_bits_snpAttr,
+  input         io_in_2_bits_expCompAck,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [10:0] io_in_3_bits_tgtID,
+  input  [11:0] io_in_3_bits_txnID,
+  input  [6:0]  io_in_3_bits_opcode,
+  input  [2:0]  io_in_3_bits_size,
+  input  [47:0] io_in_3_bits_addr,
+  input         io_in_3_bits_likelyshared,
+  input         io_in_3_bits_allowRetry,
+  input  [1:0]  io_in_3_bits_order,
+  input  [3:0]  io_in_3_bits_pCrdType,
+  input         io_in_3_bits_memAttr_allocate,
+  input         io_in_3_bits_memAttr_cacheable,
+  input         io_in_3_bits_memAttr_device,
+  input         io_in_3_bits_memAttr_ewa,
+  input         io_in_3_bits_snpAttr,
+  input         io_in_3_bits_expCompAck,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [10:0] io_in_4_bits_tgtID,
+  input  [11:0] io_in_4_bits_txnID,
+  input  [6:0]  io_in_4_bits_opcode,
+  input  [2:0]  io_in_4_bits_size,
+  input  [47:0] io_in_4_bits_addr,
+  input         io_in_4_bits_likelyshared,
+  input         io_in_4_bits_allowRetry,
+  input  [1:0]  io_in_4_bits_order,
+  input  [3:0]  io_in_4_bits_pCrdType,
+  input         io_in_4_bits_memAttr_allocate,
+  input         io_in_4_bits_memAttr_cacheable,
+  input         io_in_4_bits_memAttr_device,
+  input         io_in_4_bits_memAttr_ewa,
+  input         io_in_4_bits_snpAttr,
+  input         io_in_4_bits_expCompAck,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [10:0] io_in_5_bits_tgtID,
+  input  [11:0] io_in_5_bits_txnID,
+  input  [6:0]  io_in_5_bits_opcode,
+  input  [2:0]  io_in_5_bits_size,
+  input  [47:0] io_in_5_bits_addr,
+  input         io_in_5_bits_likelyshared,
+  input         io_in_5_bits_allowRetry,
+  input  [1:0]  io_in_5_bits_order,
+  input  [3:0]  io_in_5_bits_pCrdType,
+  input         io_in_5_bits_memAttr_allocate,
+  input         io_in_5_bits_memAttr_cacheable,
+  input         io_in_5_bits_memAttr_device,
+  input         io_in_5_bits_memAttr_ewa,
+  input         io_in_5_bits_snpAttr,
+  input         io_in_5_bits_expCompAck,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [10:0] io_in_6_bits_tgtID,
+  input  [11:0] io_in_6_bits_txnID,
+  input  [6:0]  io_in_6_bits_opcode,
+  input  [2:0]  io_in_6_bits_size,
+  input  [47:0] io_in_6_bits_addr,
+  input         io_in_6_bits_likelyshared,
+  input         io_in_6_bits_allowRetry,
+  input  [1:0]  io_in_6_bits_order,
+  input  [3:0]  io_in_6_bits_pCrdType,
+  input         io_in_6_bits_memAttr_allocate,
+  input         io_in_6_bits_memAttr_cacheable,
+  input         io_in_6_bits_memAttr_device,
+  input         io_in_6_bits_memAttr_ewa,
+  input         io_in_6_bits_snpAttr,
+  input         io_in_6_bits_expCompAck,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [10:0] io_in_7_bits_tgtID,
+  input  [11:0] io_in_7_bits_txnID,
+  input  [6:0]  io_in_7_bits_opcode,
+  input  [2:0]  io_in_7_bits_size,
+  input  [47:0] io_in_7_bits_addr,
+  input         io_in_7_bits_likelyshared,
+  input         io_in_7_bits_allowRetry,
+  input  [1:0]  io_in_7_bits_order,
+  input  [3:0]  io_in_7_bits_pCrdType,
+  input         io_in_7_bits_memAttr_allocate,
+  input         io_in_7_bits_memAttr_cacheable,
+  input         io_in_7_bits_memAttr_device,
+  input         io_in_7_bits_memAttr_ewa,
+  input         io_in_7_bits_snpAttr,
+  input         io_in_7_bits_expCompAck,
+  output        io_in_8_ready,
+  input         io_in_8_valid,
+  input  [10:0] io_in_8_bits_tgtID,
+  input  [11:0] io_in_8_bits_txnID,
+  input  [6:0]  io_in_8_bits_opcode,
+  input  [2:0]  io_in_8_bits_size,
+  input  [47:0] io_in_8_bits_addr,
+  input         io_in_8_bits_likelyshared,
+  input         io_in_8_bits_allowRetry,
+  input  [1:0]  io_in_8_bits_order,
+  input  [3:0]  io_in_8_bits_pCrdType,
+  input         io_in_8_bits_memAttr_allocate,
+  input         io_in_8_bits_memAttr_cacheable,
+  input         io_in_8_bits_memAttr_device,
+  input         io_in_8_bits_memAttr_ewa,
+  input         io_in_8_bits_snpAttr,
+  input         io_in_8_bits_expCompAck,
+  output        io_in_9_ready,
+  input         io_in_9_valid,
+  input  [10:0] io_in_9_bits_tgtID,
+  input  [11:0] io_in_9_bits_txnID,
+  input  [6:0]  io_in_9_bits_opcode,
+  input  [2:0]  io_in_9_bits_size,
+  input  [47:0] io_in_9_bits_addr,
+  input         io_in_9_bits_likelyshared,
+  input         io_in_9_bits_allowRetry,
+  input  [1:0]  io_in_9_bits_order,
+  input  [3:0]  io_in_9_bits_pCrdType,
+  input         io_in_9_bits_memAttr_allocate,
+  input         io_in_9_bits_memAttr_cacheable,
+  input         io_in_9_bits_memAttr_device,
+  input         io_in_9_bits_memAttr_ewa,
+  input         io_in_9_bits_snpAttr,
+  input         io_in_9_bits_expCompAck,
+  output        io_in_10_ready,
+  input         io_in_10_valid,
+  input  [10:0] io_in_10_bits_tgtID,
+  input  [11:0] io_in_10_bits_txnID,
+  input  [6:0]  io_in_10_bits_opcode,
+  input  [2:0]  io_in_10_bits_size,
+  input  [47:0] io_in_10_bits_addr,
+  input         io_in_10_bits_likelyshared,
+  input         io_in_10_bits_allowRetry,
+  input  [1:0]  io_in_10_bits_order,
+  input  [3:0]  io_in_10_bits_pCrdType,
+  input         io_in_10_bits_memAttr_allocate,
+  input         io_in_10_bits_memAttr_cacheable,
+  input         io_in_10_bits_memAttr_device,
+  input         io_in_10_bits_memAttr_ewa,
+  input         io_in_10_bits_snpAttr,
+  input         io_in_10_bits_expCompAck,
+  output        io_in_11_ready,
+  input         io_in_11_valid,
+  input  [10:0] io_in_11_bits_tgtID,
+  input  [11:0] io_in_11_bits_txnID,
+  input  [6:0]  io_in_11_bits_opcode,
+  input  [2:0]  io_in_11_bits_size,
+  input  [47:0] io_in_11_bits_addr,
+  input         io_in_11_bits_likelyshared,
+  input         io_in_11_bits_allowRetry,
+  input  [1:0]  io_in_11_bits_order,
+  input  [3:0]  io_in_11_bits_pCrdType,
+  input         io_in_11_bits_memAttr_allocate,
+  input         io_in_11_bits_memAttr_cacheable,
+  input         io_in_11_bits_memAttr_device,
+  input         io_in_11_bits_memAttr_ewa,
+  input         io_in_11_bits_snpAttr,
+  input         io_in_11_bits_expCompAck,
+  output        io_in_12_ready,
+  input         io_in_12_valid,
+  input  [10:0] io_in_12_bits_tgtID,
+  input  [11:0] io_in_12_bits_txnID,
+  input  [6:0]  io_in_12_bits_opcode,
+  input  [2:0]  io_in_12_bits_size,
+  input  [47:0] io_in_12_bits_addr,
+  input         io_in_12_bits_likelyshared,
+  input         io_in_12_bits_allowRetry,
+  input  [1:0]  io_in_12_bits_order,
+  input  [3:0]  io_in_12_bits_pCrdType,
+  input         io_in_12_bits_memAttr_allocate,
+  input         io_in_12_bits_memAttr_cacheable,
+  input         io_in_12_bits_memAttr_device,
+  input         io_in_12_bits_memAttr_ewa,
+  input         io_in_12_bits_snpAttr,
+  input         io_in_12_bits_expCompAck,
+  output        io_in_13_ready,
+  input         io_in_13_valid,
+  input  [10:0] io_in_13_bits_tgtID,
+  input  [11:0] io_in_13_bits_txnID,
+  input  [6:0]  io_in_13_bits_opcode,
+  input  [2:0]  io_in_13_bits_size,
+  input  [47:0] io_in_13_bits_addr,
+  input         io_in_13_bits_likelyshared,
+  input         io_in_13_bits_allowRetry,
+  input  [1:0]  io_in_13_bits_order,
+  input  [3:0]  io_in_13_bits_pCrdType,
+  input         io_in_13_bits_memAttr_allocate,
+  input         io_in_13_bits_memAttr_cacheable,
+  input         io_in_13_bits_memAttr_device,
+  input         io_in_13_bits_memAttr_ewa,
+  input         io_in_13_bits_snpAttr,
+  input         io_in_13_bits_expCompAck,
+  output        io_in_14_ready,
+  input         io_in_14_valid,
+  input  [10:0] io_in_14_bits_tgtID,
+  input  [11:0] io_in_14_bits_txnID,
+  input  [6:0]  io_in_14_bits_opcode,
+  input  [2:0]  io_in_14_bits_size,
+  input  [47:0] io_in_14_bits_addr,
+  input         io_in_14_bits_likelyshared,
+  input         io_in_14_bits_allowRetry,
+  input  [1:0]  io_in_14_bits_order,
+  input  [3:0]  io_in_14_bits_pCrdType,
+  input         io_in_14_bits_memAttr_allocate,
+  input         io_in_14_bits_memAttr_cacheable,
+  input         io_in_14_bits_memAttr_device,
+  input         io_in_14_bits_memAttr_ewa,
+  input         io_in_14_bits_snpAttr,
+  input         io_in_14_bits_expCompAck,
+  output        io_in_15_ready,
+  input         io_in_15_valid,
+  input  [10:0] io_in_15_bits_tgtID,
+  input  [11:0] io_in_15_bits_txnID,
+  input  [6:0]  io_in_15_bits_opcode,
+  input  [2:0]  io_in_15_bits_size,
+  input  [47:0] io_in_15_bits_addr,
+  input         io_in_15_bits_likelyshared,
+  input         io_in_15_bits_allowRetry,
+  input  [1:0]  io_in_15_bits_order,
+  input  [3:0]  io_in_15_bits_pCrdType,
+  input         io_in_15_bits_memAttr_allocate,
+  input         io_in_15_bits_memAttr_cacheable,
+  input         io_in_15_bits_memAttr_device,
+  input         io_in_15_bits_memAttr_ewa,
+  input         io_in_15_bits_snpAttr,
+  input         io_in_15_bits_expCompAck,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_qos,
+  output [10:0] io_out_bits_tgtID,
+  output [11:0] io_out_bits_txnID,
+  output [6:0]  io_out_bits_opcode,
+  output [2:0]  io_out_bits_size,
+  output [47:0] io_out_bits_addr,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_allowRetry,
+  output [1:0]  io_out_bits_order,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_device,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_snpAttr,
+  output        io_out_bits_expCompAck
+);
+
+  wire        _highArb_io_out_valid;
+  wire [3:0]  _highArb_io_out_bits_qos;
+  wire [10:0] _highArb_io_out_bits_tgtID;
+  wire [11:0] _highArb_io_out_bits_txnID;
+  wire [6:0]  _highArb_io_out_bits_opcode;
+  wire [2:0]  _highArb_io_out_bits_size;
+  wire [47:0] _highArb_io_out_bits_addr;
+  wire        _highArb_io_out_bits_likelyshared;
+  wire        _highArb_io_out_bits_allowRetry;
+  wire [1:0]  _highArb_io_out_bits_order;
+  wire [3:0]  _highArb_io_out_bits_pCrdType;
+  wire        _highArb_io_out_bits_memAttr_allocate;
+  wire        _highArb_io_out_bits_memAttr_cacheable;
+  wire        _highArb_io_out_bits_memAttr_device;
+  wire        _highArb_io_out_bits_memAttr_ewa;
+  wire        _highArb_io_out_bits_snpAttr;
+  wire        _highArb_io_out_bits_expCompAck;
+  wire        _lowArb_io_out_valid;
+  wire [3:0]  _lowArb_io_out_bits_qos;
+  wire [10:0] _lowArb_io_out_bits_tgtID;
+  wire [11:0] _lowArb_io_out_bits_txnID;
+  wire [6:0]  _lowArb_io_out_bits_opcode;
+  wire [2:0]  _lowArb_io_out_bits_size;
+  wire [47:0] _lowArb_io_out_bits_addr;
+  wire        _lowArb_io_out_bits_likelyshared;
+  wire        _lowArb_io_out_bits_allowRetry;
+  wire [1:0]  _lowArb_io_out_bits_order;
+  wire [3:0]  _lowArb_io_out_bits_pCrdType;
+  wire        _lowArb_io_out_bits_memAttr_allocate;
+  wire        _lowArb_io_out_bits_memAttr_cacheable;
+  wire        _lowArb_io_out_bits_memAttr_device;
+  wire        _lowArb_io_out_bits_memAttr_ewa;
+  wire        _lowArb_io_out_bits_snpAttr;
+  wire        _lowArb_io_out_bits_expCompAck;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_ready & io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_2 lowArb (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_in_0_ready                  (io_in_0_ready),
+    .io_in_0_valid                  (io_in_0_valid),
+    .io_in_0_bits_tgtID             (io_in_0_bits_tgtID),
+    .io_in_0_bits_txnID             (io_in_0_bits_txnID),
+    .io_in_0_bits_opcode            (io_in_0_bits_opcode),
+    .io_in_0_bits_size              (io_in_0_bits_size),
+    .io_in_0_bits_addr              (io_in_0_bits_addr),
+    .io_in_0_bits_likelyshared      (io_in_0_bits_likelyshared),
+    .io_in_0_bits_allowRetry        (io_in_0_bits_allowRetry),
+    .io_in_0_bits_order             (io_in_0_bits_order),
+    .io_in_0_bits_pCrdType          (io_in_0_bits_pCrdType),
+    .io_in_0_bits_memAttr_allocate  (io_in_0_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable (io_in_0_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_device    (io_in_0_bits_memAttr_device),
+    .io_in_0_bits_memAttr_ewa       (io_in_0_bits_memAttr_ewa),
+    .io_in_0_bits_snpAttr           (io_in_0_bits_snpAttr),
+    .io_in_0_bits_expCompAck        (io_in_0_bits_expCompAck),
+    .io_in_1_ready                  (io_in_1_ready),
+    .io_in_1_valid                  (io_in_1_valid),
+    .io_in_1_bits_tgtID             (io_in_1_bits_tgtID),
+    .io_in_1_bits_txnID             (io_in_1_bits_txnID),
+    .io_in_1_bits_opcode            (io_in_1_bits_opcode),
+    .io_in_1_bits_size              (io_in_1_bits_size),
+    .io_in_1_bits_addr              (io_in_1_bits_addr),
+    .io_in_1_bits_likelyshared      (io_in_1_bits_likelyshared),
+    .io_in_1_bits_allowRetry        (io_in_1_bits_allowRetry),
+    .io_in_1_bits_order             (io_in_1_bits_order),
+    .io_in_1_bits_pCrdType          (io_in_1_bits_pCrdType),
+    .io_in_1_bits_memAttr_allocate  (io_in_1_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable (io_in_1_bits_memAttr_cacheable),
+    .io_in_1_bits_memAttr_device    (io_in_1_bits_memAttr_device),
+    .io_in_1_bits_memAttr_ewa       (io_in_1_bits_memAttr_ewa),
+    .io_in_1_bits_snpAttr           (io_in_1_bits_snpAttr),
+    .io_in_1_bits_expCompAck        (io_in_1_bits_expCompAck),
+    .io_in_2_ready                  (io_in_2_ready),
+    .io_in_2_valid                  (io_in_2_valid),
+    .io_in_2_bits_tgtID             (io_in_2_bits_tgtID),
+    .io_in_2_bits_txnID             (io_in_2_bits_txnID),
+    .io_in_2_bits_opcode            (io_in_2_bits_opcode),
+    .io_in_2_bits_size              (io_in_2_bits_size),
+    .io_in_2_bits_addr              (io_in_2_bits_addr),
+    .io_in_2_bits_likelyshared      (io_in_2_bits_likelyshared),
+    .io_in_2_bits_allowRetry        (io_in_2_bits_allowRetry),
+    .io_in_2_bits_order             (io_in_2_bits_order),
+    .io_in_2_bits_pCrdType          (io_in_2_bits_pCrdType),
+    .io_in_2_bits_memAttr_allocate  (io_in_2_bits_memAttr_allocate),
+    .io_in_2_bits_memAttr_cacheable (io_in_2_bits_memAttr_cacheable),
+    .io_in_2_bits_memAttr_device    (io_in_2_bits_memAttr_device),
+    .io_in_2_bits_memAttr_ewa       (io_in_2_bits_memAttr_ewa),
+    .io_in_2_bits_snpAttr           (io_in_2_bits_snpAttr),
+    .io_in_2_bits_expCompAck        (io_in_2_bits_expCompAck),
+    .io_in_3_ready                  (io_in_3_ready),
+    .io_in_3_valid                  (io_in_3_valid),
+    .io_in_3_bits_tgtID             (io_in_3_bits_tgtID),
+    .io_in_3_bits_txnID             (io_in_3_bits_txnID),
+    .io_in_3_bits_opcode            (io_in_3_bits_opcode),
+    .io_in_3_bits_size              (io_in_3_bits_size),
+    .io_in_3_bits_addr              (io_in_3_bits_addr),
+    .io_in_3_bits_likelyshared      (io_in_3_bits_likelyshared),
+    .io_in_3_bits_allowRetry        (io_in_3_bits_allowRetry),
+    .io_in_3_bits_order             (io_in_3_bits_order),
+    .io_in_3_bits_pCrdType          (io_in_3_bits_pCrdType),
+    .io_in_3_bits_memAttr_allocate  (io_in_3_bits_memAttr_allocate),
+    .io_in_3_bits_memAttr_cacheable (io_in_3_bits_memAttr_cacheable),
+    .io_in_3_bits_memAttr_device    (io_in_3_bits_memAttr_device),
+    .io_in_3_bits_memAttr_ewa       (io_in_3_bits_memAttr_ewa),
+    .io_in_3_bits_snpAttr           (io_in_3_bits_snpAttr),
+    .io_in_3_bits_expCompAck        (io_in_3_bits_expCompAck),
+    .io_in_4_ready                  (io_in_4_ready),
+    .io_in_4_valid                  (io_in_4_valid),
+    .io_in_4_bits_tgtID             (io_in_4_bits_tgtID),
+    .io_in_4_bits_txnID             (io_in_4_bits_txnID),
+    .io_in_4_bits_opcode            (io_in_4_bits_opcode),
+    .io_in_4_bits_size              (io_in_4_bits_size),
+    .io_in_4_bits_addr              (io_in_4_bits_addr),
+    .io_in_4_bits_likelyshared      (io_in_4_bits_likelyshared),
+    .io_in_4_bits_allowRetry        (io_in_4_bits_allowRetry),
+    .io_in_4_bits_order             (io_in_4_bits_order),
+    .io_in_4_bits_pCrdType          (io_in_4_bits_pCrdType),
+    .io_in_4_bits_memAttr_allocate  (io_in_4_bits_memAttr_allocate),
+    .io_in_4_bits_memAttr_cacheable (io_in_4_bits_memAttr_cacheable),
+    .io_in_4_bits_memAttr_device    (io_in_4_bits_memAttr_device),
+    .io_in_4_bits_memAttr_ewa       (io_in_4_bits_memAttr_ewa),
+    .io_in_4_bits_snpAttr           (io_in_4_bits_snpAttr),
+    .io_in_4_bits_expCompAck        (io_in_4_bits_expCompAck),
+    .io_in_5_ready                  (io_in_5_ready),
+    .io_in_5_valid                  (io_in_5_valid),
+    .io_in_5_bits_tgtID             (io_in_5_bits_tgtID),
+    .io_in_5_bits_txnID             (io_in_5_bits_txnID),
+    .io_in_5_bits_opcode            (io_in_5_bits_opcode),
+    .io_in_5_bits_size              (io_in_5_bits_size),
+    .io_in_5_bits_addr              (io_in_5_bits_addr),
+    .io_in_5_bits_likelyshared      (io_in_5_bits_likelyshared),
+    .io_in_5_bits_allowRetry        (io_in_5_bits_allowRetry),
+    .io_in_5_bits_order             (io_in_5_bits_order),
+    .io_in_5_bits_pCrdType          (io_in_5_bits_pCrdType),
+    .io_in_5_bits_memAttr_allocate  (io_in_5_bits_memAttr_allocate),
+    .io_in_5_bits_memAttr_cacheable (io_in_5_bits_memAttr_cacheable),
+    .io_in_5_bits_memAttr_device    (io_in_5_bits_memAttr_device),
+    .io_in_5_bits_memAttr_ewa       (io_in_5_bits_memAttr_ewa),
+    .io_in_5_bits_snpAttr           (io_in_5_bits_snpAttr),
+    .io_in_5_bits_expCompAck        (io_in_5_bits_expCompAck),
+    .io_in_6_ready                  (io_in_6_ready),
+    .io_in_6_valid                  (io_in_6_valid),
+    .io_in_6_bits_tgtID             (io_in_6_bits_tgtID),
+    .io_in_6_bits_txnID             (io_in_6_bits_txnID),
+    .io_in_6_bits_opcode            (io_in_6_bits_opcode),
+    .io_in_6_bits_size              (io_in_6_bits_size),
+    .io_in_6_bits_addr              (io_in_6_bits_addr),
+    .io_in_6_bits_likelyshared      (io_in_6_bits_likelyshared),
+    .io_in_6_bits_allowRetry        (io_in_6_bits_allowRetry),
+    .io_in_6_bits_order             (io_in_6_bits_order),
+    .io_in_6_bits_pCrdType          (io_in_6_bits_pCrdType),
+    .io_in_6_bits_memAttr_allocate  (io_in_6_bits_memAttr_allocate),
+    .io_in_6_bits_memAttr_cacheable (io_in_6_bits_memAttr_cacheable),
+    .io_in_6_bits_memAttr_device    (io_in_6_bits_memAttr_device),
+    .io_in_6_bits_memAttr_ewa       (io_in_6_bits_memAttr_ewa),
+    .io_in_6_bits_snpAttr           (io_in_6_bits_snpAttr),
+    .io_in_6_bits_expCompAck        (io_in_6_bits_expCompAck),
+    .io_in_7_ready                  (io_in_7_ready),
+    .io_in_7_valid                  (io_in_7_valid),
+    .io_in_7_bits_tgtID             (io_in_7_bits_tgtID),
+    .io_in_7_bits_txnID             (io_in_7_bits_txnID),
+    .io_in_7_bits_opcode            (io_in_7_bits_opcode),
+    .io_in_7_bits_size              (io_in_7_bits_size),
+    .io_in_7_bits_addr              (io_in_7_bits_addr),
+    .io_in_7_bits_likelyshared      (io_in_7_bits_likelyshared),
+    .io_in_7_bits_allowRetry        (io_in_7_bits_allowRetry),
+    .io_in_7_bits_order             (io_in_7_bits_order),
+    .io_in_7_bits_pCrdType          (io_in_7_bits_pCrdType),
+    .io_in_7_bits_memAttr_allocate  (io_in_7_bits_memAttr_allocate),
+    .io_in_7_bits_memAttr_cacheable (io_in_7_bits_memAttr_cacheable),
+    .io_in_7_bits_memAttr_device    (io_in_7_bits_memAttr_device),
+    .io_in_7_bits_memAttr_ewa       (io_in_7_bits_memAttr_ewa),
+    .io_in_7_bits_snpAttr           (io_in_7_bits_snpAttr),
+    .io_in_7_bits_expCompAck        (io_in_7_bits_expCompAck),
+    .io_out_ready                   (io_out_ready & finalSelLow),
+    .io_out_valid                   (_lowArb_io_out_valid),
+    .io_out_bits_qos                (_lowArb_io_out_bits_qos),
+    .io_out_bits_tgtID              (_lowArb_io_out_bits_tgtID),
+    .io_out_bits_txnID              (_lowArb_io_out_bits_txnID),
+    .io_out_bits_opcode             (_lowArb_io_out_bits_opcode),
+    .io_out_bits_size               (_lowArb_io_out_bits_size),
+    .io_out_bits_addr               (_lowArb_io_out_bits_addr),
+    .io_out_bits_likelyshared       (_lowArb_io_out_bits_likelyshared),
+    .io_out_bits_allowRetry         (_lowArb_io_out_bits_allowRetry),
+    .io_out_bits_order              (_lowArb_io_out_bits_order),
+    .io_out_bits_pCrdType           (_lowArb_io_out_bits_pCrdType),
+    .io_out_bits_memAttr_allocate   (_lowArb_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable  (_lowArb_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device     (_lowArb_io_out_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa        (_lowArb_io_out_bits_memAttr_ewa),
+    .io_out_bits_snpAttr            (_lowArb_io_out_bits_snpAttr),
+    .io_out_bits_expCompAck         (_lowArb_io_out_bits_expCompAck)
+  );
+  FastArbiter_2 highArb (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_in_0_ready                  (io_in_8_ready),
+    .io_in_0_valid                  (io_in_8_valid),
+    .io_in_0_bits_tgtID             (io_in_8_bits_tgtID),
+    .io_in_0_bits_txnID             (io_in_8_bits_txnID),
+    .io_in_0_bits_opcode            (io_in_8_bits_opcode),
+    .io_in_0_bits_size              (io_in_8_bits_size),
+    .io_in_0_bits_addr              (io_in_8_bits_addr),
+    .io_in_0_bits_likelyshared      (io_in_8_bits_likelyshared),
+    .io_in_0_bits_allowRetry        (io_in_8_bits_allowRetry),
+    .io_in_0_bits_order             (io_in_8_bits_order),
+    .io_in_0_bits_pCrdType          (io_in_8_bits_pCrdType),
+    .io_in_0_bits_memAttr_allocate  (io_in_8_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable (io_in_8_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_device    (io_in_8_bits_memAttr_device),
+    .io_in_0_bits_memAttr_ewa       (io_in_8_bits_memAttr_ewa),
+    .io_in_0_bits_snpAttr           (io_in_8_bits_snpAttr),
+    .io_in_0_bits_expCompAck        (io_in_8_bits_expCompAck),
+    .io_in_1_ready                  (io_in_9_ready),
+    .io_in_1_valid                  (io_in_9_valid),
+    .io_in_1_bits_tgtID             (io_in_9_bits_tgtID),
+    .io_in_1_bits_txnID             (io_in_9_bits_txnID),
+    .io_in_1_bits_opcode            (io_in_9_bits_opcode),
+    .io_in_1_bits_size              (io_in_9_bits_size),
+    .io_in_1_bits_addr              (io_in_9_bits_addr),
+    .io_in_1_bits_likelyshared      (io_in_9_bits_likelyshared),
+    .io_in_1_bits_allowRetry        (io_in_9_bits_allowRetry),
+    .io_in_1_bits_order             (io_in_9_bits_order),
+    .io_in_1_bits_pCrdType          (io_in_9_bits_pCrdType),
+    .io_in_1_bits_memAttr_allocate  (io_in_9_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable (io_in_9_bits_memAttr_cacheable),
+    .io_in_1_bits_memAttr_device    (io_in_9_bits_memAttr_device),
+    .io_in_1_bits_memAttr_ewa       (io_in_9_bits_memAttr_ewa),
+    .io_in_1_bits_snpAttr           (io_in_9_bits_snpAttr),
+    .io_in_1_bits_expCompAck        (io_in_9_bits_expCompAck),
+    .io_in_2_ready                  (io_in_10_ready),
+    .io_in_2_valid                  (io_in_10_valid),
+    .io_in_2_bits_tgtID             (io_in_10_bits_tgtID),
+    .io_in_2_bits_txnID             (io_in_10_bits_txnID),
+    .io_in_2_bits_opcode            (io_in_10_bits_opcode),
+    .io_in_2_bits_size              (io_in_10_bits_size),
+    .io_in_2_bits_addr              (io_in_10_bits_addr),
+    .io_in_2_bits_likelyshared      (io_in_10_bits_likelyshared),
+    .io_in_2_bits_allowRetry        (io_in_10_bits_allowRetry),
+    .io_in_2_bits_order             (io_in_10_bits_order),
+    .io_in_2_bits_pCrdType          (io_in_10_bits_pCrdType),
+    .io_in_2_bits_memAttr_allocate  (io_in_10_bits_memAttr_allocate),
+    .io_in_2_bits_memAttr_cacheable (io_in_10_bits_memAttr_cacheable),
+    .io_in_2_bits_memAttr_device    (io_in_10_bits_memAttr_device),
+    .io_in_2_bits_memAttr_ewa       (io_in_10_bits_memAttr_ewa),
+    .io_in_2_bits_snpAttr           (io_in_10_bits_snpAttr),
+    .io_in_2_bits_expCompAck        (io_in_10_bits_expCompAck),
+    .io_in_3_ready                  (io_in_11_ready),
+    .io_in_3_valid                  (io_in_11_valid),
+    .io_in_3_bits_tgtID             (io_in_11_bits_tgtID),
+    .io_in_3_bits_txnID             (io_in_11_bits_txnID),
+    .io_in_3_bits_opcode            (io_in_11_bits_opcode),
+    .io_in_3_bits_size              (io_in_11_bits_size),
+    .io_in_3_bits_addr              (io_in_11_bits_addr),
+    .io_in_3_bits_likelyshared      (io_in_11_bits_likelyshared),
+    .io_in_3_bits_allowRetry        (io_in_11_bits_allowRetry),
+    .io_in_3_bits_order             (io_in_11_bits_order),
+    .io_in_3_bits_pCrdType          (io_in_11_bits_pCrdType),
+    .io_in_3_bits_memAttr_allocate  (io_in_11_bits_memAttr_allocate),
+    .io_in_3_bits_memAttr_cacheable (io_in_11_bits_memAttr_cacheable),
+    .io_in_3_bits_memAttr_device    (io_in_11_bits_memAttr_device),
+    .io_in_3_bits_memAttr_ewa       (io_in_11_bits_memAttr_ewa),
+    .io_in_3_bits_snpAttr           (io_in_11_bits_snpAttr),
+    .io_in_3_bits_expCompAck        (io_in_11_bits_expCompAck),
+    .io_in_4_ready                  (io_in_12_ready),
+    .io_in_4_valid                  (io_in_12_valid),
+    .io_in_4_bits_tgtID             (io_in_12_bits_tgtID),
+    .io_in_4_bits_txnID             (io_in_12_bits_txnID),
+    .io_in_4_bits_opcode            (io_in_12_bits_opcode),
+    .io_in_4_bits_size              (io_in_12_bits_size),
+    .io_in_4_bits_addr              (io_in_12_bits_addr),
+    .io_in_4_bits_likelyshared      (io_in_12_bits_likelyshared),
+    .io_in_4_bits_allowRetry        (io_in_12_bits_allowRetry),
+    .io_in_4_bits_order             (io_in_12_bits_order),
+    .io_in_4_bits_pCrdType          (io_in_12_bits_pCrdType),
+    .io_in_4_bits_memAttr_allocate  (io_in_12_bits_memAttr_allocate),
+    .io_in_4_bits_memAttr_cacheable (io_in_12_bits_memAttr_cacheable),
+    .io_in_4_bits_memAttr_device    (io_in_12_bits_memAttr_device),
+    .io_in_4_bits_memAttr_ewa       (io_in_12_bits_memAttr_ewa),
+    .io_in_4_bits_snpAttr           (io_in_12_bits_snpAttr),
+    .io_in_4_bits_expCompAck        (io_in_12_bits_expCompAck),
+    .io_in_5_ready                  (io_in_13_ready),
+    .io_in_5_valid                  (io_in_13_valid),
+    .io_in_5_bits_tgtID             (io_in_13_bits_tgtID),
+    .io_in_5_bits_txnID             (io_in_13_bits_txnID),
+    .io_in_5_bits_opcode            (io_in_13_bits_opcode),
+    .io_in_5_bits_size              (io_in_13_bits_size),
+    .io_in_5_bits_addr              (io_in_13_bits_addr),
+    .io_in_5_bits_likelyshared      (io_in_13_bits_likelyshared),
+    .io_in_5_bits_allowRetry        (io_in_13_bits_allowRetry),
+    .io_in_5_bits_order             (io_in_13_bits_order),
+    .io_in_5_bits_pCrdType          (io_in_13_bits_pCrdType),
+    .io_in_5_bits_memAttr_allocate  (io_in_13_bits_memAttr_allocate),
+    .io_in_5_bits_memAttr_cacheable (io_in_13_bits_memAttr_cacheable),
+    .io_in_5_bits_memAttr_device    (io_in_13_bits_memAttr_device),
+    .io_in_5_bits_memAttr_ewa       (io_in_13_bits_memAttr_ewa),
+    .io_in_5_bits_snpAttr           (io_in_13_bits_snpAttr),
+    .io_in_5_bits_expCompAck        (io_in_13_bits_expCompAck),
+    .io_in_6_ready                  (io_in_14_ready),
+    .io_in_6_valid                  (io_in_14_valid),
+    .io_in_6_bits_tgtID             (io_in_14_bits_tgtID),
+    .io_in_6_bits_txnID             (io_in_14_bits_txnID),
+    .io_in_6_bits_opcode            (io_in_14_bits_opcode),
+    .io_in_6_bits_size              (io_in_14_bits_size),
+    .io_in_6_bits_addr              (io_in_14_bits_addr),
+    .io_in_6_bits_likelyshared      (io_in_14_bits_likelyshared),
+    .io_in_6_bits_allowRetry        (io_in_14_bits_allowRetry),
+    .io_in_6_bits_order             (io_in_14_bits_order),
+    .io_in_6_bits_pCrdType          (io_in_14_bits_pCrdType),
+    .io_in_6_bits_memAttr_allocate  (io_in_14_bits_memAttr_allocate),
+    .io_in_6_bits_memAttr_cacheable (io_in_14_bits_memAttr_cacheable),
+    .io_in_6_bits_memAttr_device    (io_in_14_bits_memAttr_device),
+    .io_in_6_bits_memAttr_ewa       (io_in_14_bits_memAttr_ewa),
+    .io_in_6_bits_snpAttr           (io_in_14_bits_snpAttr),
+    .io_in_6_bits_expCompAck        (io_in_14_bits_expCompAck),
+    .io_in_7_ready                  (io_in_15_ready),
+    .io_in_7_valid                  (io_in_15_valid),
+    .io_in_7_bits_tgtID             (io_in_15_bits_tgtID),
+    .io_in_7_bits_txnID             (io_in_15_bits_txnID),
+    .io_in_7_bits_opcode            (io_in_15_bits_opcode),
+    .io_in_7_bits_size              (io_in_15_bits_size),
+    .io_in_7_bits_addr              (io_in_15_bits_addr),
+    .io_in_7_bits_likelyshared      (io_in_15_bits_likelyshared),
+    .io_in_7_bits_allowRetry        (io_in_15_bits_allowRetry),
+    .io_in_7_bits_order             (io_in_15_bits_order),
+    .io_in_7_bits_pCrdType          (io_in_15_bits_pCrdType),
+    .io_in_7_bits_memAttr_allocate  (io_in_15_bits_memAttr_allocate),
+    .io_in_7_bits_memAttr_cacheable (io_in_15_bits_memAttr_cacheable),
+    .io_in_7_bits_memAttr_device    (io_in_15_bits_memAttr_device),
+    .io_in_7_bits_memAttr_ewa       (io_in_15_bits_memAttr_ewa),
+    .io_in_7_bits_snpAttr           (io_in_15_bits_snpAttr),
+    .io_in_7_bits_expCompAck        (io_in_15_bits_expCompAck),
+    .io_out_ready                   (io_out_ready & ~finalSelLow),
+    .io_out_valid                   (_highArb_io_out_valid),
+    .io_out_bits_qos                (_highArb_io_out_bits_qos),
+    .io_out_bits_tgtID              (_highArb_io_out_bits_tgtID),
+    .io_out_bits_txnID              (_highArb_io_out_bits_txnID),
+    .io_out_bits_opcode             (_highArb_io_out_bits_opcode),
+    .io_out_bits_size               (_highArb_io_out_bits_size),
+    .io_out_bits_addr               (_highArb_io_out_bits_addr),
+    .io_out_bits_likelyshared       (_highArb_io_out_bits_likelyshared),
+    .io_out_bits_allowRetry         (_highArb_io_out_bits_allowRetry),
+    .io_out_bits_order              (_highArb_io_out_bits_order),
+    .io_out_bits_pCrdType           (_highArb_io_out_bits_pCrdType),
+    .io_out_bits_memAttr_allocate   (_highArb_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable  (_highArb_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device     (_highArb_io_out_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa        (_highArb_io_out_bits_memAttr_ewa),
+    .io_out_bits_snpAttr            (_highArb_io_out_bits_snpAttr),
+    .io_out_bits_expCompAck         (_highArb_io_out_bits_expCompAck)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_qos =
+    finalSelLow ? _lowArb_io_out_bits_qos : _highArb_io_out_bits_qos;
+  assign io_out_bits_tgtID =
+    finalSelLow ? _lowArb_io_out_bits_tgtID : _highArb_io_out_bits_tgtID;
+  assign io_out_bits_txnID =
+    finalSelLow ? _lowArb_io_out_bits_txnID : _highArb_io_out_bits_txnID;
+  assign io_out_bits_opcode =
+    finalSelLow ? _lowArb_io_out_bits_opcode : _highArb_io_out_bits_opcode;
+  assign io_out_bits_size =
+    finalSelLow ? _lowArb_io_out_bits_size : _highArb_io_out_bits_size;
+  assign io_out_bits_addr =
+    finalSelLow ? _lowArb_io_out_bits_addr : _highArb_io_out_bits_addr;
+  assign io_out_bits_likelyshared =
+    finalSelLow ? _lowArb_io_out_bits_likelyshared : _highArb_io_out_bits_likelyshared;
+  assign io_out_bits_allowRetry =
+    finalSelLow ? _lowArb_io_out_bits_allowRetry : _highArb_io_out_bits_allowRetry;
+  assign io_out_bits_order =
+    finalSelLow ? _lowArb_io_out_bits_order : _highArb_io_out_bits_order;
+  assign io_out_bits_pCrdType =
+    finalSelLow ? _lowArb_io_out_bits_pCrdType : _highArb_io_out_bits_pCrdType;
+  assign io_out_bits_memAttr_allocate =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_allocate
+      : _highArb_io_out_bits_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_cacheable
+      : _highArb_io_out_bits_memAttr_cacheable;
+  assign io_out_bits_memAttr_device =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_device
+      : _highArb_io_out_bits_memAttr_device;
+  assign io_out_bits_memAttr_ewa =
+    finalSelLow ? _lowArb_io_out_bits_memAttr_ewa : _highArb_io_out_bits_memAttr_ewa;
+  assign io_out_bits_snpAttr =
+    finalSelLow ? _lowArb_io_out_bits_snpAttr : _highArb_io_out_bits_snpAttr;
+  assign io_out_bits_expCompAck =
+    finalSelLow ? _lowArb_io_out_bits_expCompAck : _highArb_io_out_bits_expCompAck;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_10.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_10.sv
new file mode 100644
index 0000000000..83af24a998
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_10.sv
@@ -0,0 +1,3310 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_10(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [2:0]  io_in_0_bits_channel,
+  input  [2:0]  io_in_0_bits_txChannel,
+  input  [7:0]  io_in_0_bits_set,
+  input  [33:0] io_in_0_bits_tag,
+  input  [5:0]  io_in_0_bits_off,
+  input         io_in_0_bits_alias,
+  input         io_in_0_bits_isKeyword,
+  input  [3:0]  io_in_0_bits_opcode,
+  input  [2:0]  io_in_0_bits_param,
+  input  [2:0]  io_in_0_bits_size,
+  input  [6:0]  io_in_0_bits_sourceId,
+  input         io_in_0_bits_denied,
+  input         io_in_0_bits_corrupt,
+  input         io_in_0_bits_aliasTask,
+  input         io_in_0_bits_useProbeData,
+  input         io_in_0_bits_mshrRetry,
+  input         io_in_0_bits_readProbeDataDown,
+  input         io_in_0_bits_fromL2pft,
+  input         io_in_0_bits_dirty,
+  input  [2:0]  io_in_0_bits_way,
+  input         io_in_0_bits_meta_dirty,
+  input  [1:0]  io_in_0_bits_meta_state,
+  input         io_in_0_bits_meta_clients,
+  input         io_in_0_bits_meta_alias,
+  input         io_in_0_bits_meta_prefetch,
+  input  [3:0]  io_in_0_bits_meta_prefetchSrc,
+  input         io_in_0_bits_meta_accessed,
+  input         io_in_0_bits_meta_tagErr,
+  input         io_in_0_bits_meta_dataErr,
+  input         io_in_0_bits_metaWen,
+  input         io_in_0_bits_tagWen,
+  input         io_in_0_bits_dsWen,
+  input         io_in_0_bits_replTask,
+  input         io_in_0_bits_cmoTask,
+  input  [4:0]  io_in_0_bits_reqSource,
+  input         io_in_0_bits_mergeA,
+  input  [5:0]  io_in_0_bits_aMergeTask_off,
+  input         io_in_0_bits_aMergeTask_alias,
+  input  [43:0] io_in_0_bits_aMergeTask_vaddr,
+  input         io_in_0_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_0_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_0_bits_aMergeTask_param,
+  input  [6:0]  io_in_0_bits_aMergeTask_sourceId,
+  input         io_in_0_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_0_bits_aMergeTask_meta_state,
+  input         io_in_0_bits_aMergeTask_meta_clients,
+  input         io_in_0_bits_aMergeTask_meta_alias,
+  input         io_in_0_bits_aMergeTask_meta_accessed,
+  input         io_in_0_bits_snpHitRelease,
+  input         io_in_0_bits_snpHitReleaseToInval,
+  input         io_in_0_bits_snpHitReleaseToClean,
+  input         io_in_0_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_0_bits_snpHitReleaseIdx,
+  input         io_in_0_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_0_bits_snpHitReleaseMeta_state,
+  input         io_in_0_bits_snpHitReleaseMeta_clients,
+  input         io_in_0_bits_snpHitReleaseMeta_alias,
+  input         io_in_0_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_0_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_0_bits_snpHitReleaseMeta_accessed,
+  input         io_in_0_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_0_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [10:0] io_in_0_bits_homeNID,
+  input  [11:0] io_in_0_bits_dbID,
+  input  [6:0]  io_in_0_bits_chiOpcode,
+  input  [2:0]  io_in_0_bits_resp,
+  input  [2:0]  io_in_0_bits_fwdState,
+  input         io_in_0_bits_retToSrc,
+  input         io_in_0_bits_likelyshared,
+  input         io_in_0_bits_expCompAck,
+  input         io_in_0_bits_allowRetry,
+  input         io_in_0_bits_memAttr_allocate,
+  input         io_in_0_bits_memAttr_cacheable,
+  input         io_in_0_bits_memAttr_ewa,
+  input         io_in_0_bits_traceTag,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [2:0]  io_in_1_bits_channel,
+  input  [2:0]  io_in_1_bits_txChannel,
+  input  [7:0]  io_in_1_bits_set,
+  input  [33:0] io_in_1_bits_tag,
+  input  [5:0]  io_in_1_bits_off,
+  input         io_in_1_bits_alias,
+  input         io_in_1_bits_isKeyword,
+  input  [3:0]  io_in_1_bits_opcode,
+  input  [2:0]  io_in_1_bits_param,
+  input  [2:0]  io_in_1_bits_size,
+  input  [6:0]  io_in_1_bits_sourceId,
+  input         io_in_1_bits_denied,
+  input         io_in_1_bits_corrupt,
+  input         io_in_1_bits_aliasTask,
+  input         io_in_1_bits_useProbeData,
+  input         io_in_1_bits_mshrRetry,
+  input         io_in_1_bits_readProbeDataDown,
+  input         io_in_1_bits_fromL2pft,
+  input         io_in_1_bits_dirty,
+  input  [2:0]  io_in_1_bits_way,
+  input         io_in_1_bits_meta_dirty,
+  input  [1:0]  io_in_1_bits_meta_state,
+  input         io_in_1_bits_meta_clients,
+  input         io_in_1_bits_meta_alias,
+  input         io_in_1_bits_meta_prefetch,
+  input  [3:0]  io_in_1_bits_meta_prefetchSrc,
+  input         io_in_1_bits_meta_accessed,
+  input         io_in_1_bits_meta_tagErr,
+  input         io_in_1_bits_meta_dataErr,
+  input         io_in_1_bits_metaWen,
+  input         io_in_1_bits_tagWen,
+  input         io_in_1_bits_dsWen,
+  input         io_in_1_bits_replTask,
+  input         io_in_1_bits_cmoTask,
+  input  [4:0]  io_in_1_bits_reqSource,
+  input         io_in_1_bits_mergeA,
+  input  [5:0]  io_in_1_bits_aMergeTask_off,
+  input         io_in_1_bits_aMergeTask_alias,
+  input  [43:0] io_in_1_bits_aMergeTask_vaddr,
+  input         io_in_1_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_1_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_1_bits_aMergeTask_param,
+  input  [6:0]  io_in_1_bits_aMergeTask_sourceId,
+  input         io_in_1_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_1_bits_aMergeTask_meta_state,
+  input         io_in_1_bits_aMergeTask_meta_clients,
+  input         io_in_1_bits_aMergeTask_meta_alias,
+  input         io_in_1_bits_aMergeTask_meta_accessed,
+  input         io_in_1_bits_snpHitRelease,
+  input         io_in_1_bits_snpHitReleaseToInval,
+  input         io_in_1_bits_snpHitReleaseToClean,
+  input         io_in_1_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_1_bits_snpHitReleaseIdx,
+  input         io_in_1_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_1_bits_snpHitReleaseMeta_state,
+  input         io_in_1_bits_snpHitReleaseMeta_clients,
+  input         io_in_1_bits_snpHitReleaseMeta_alias,
+  input         io_in_1_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_1_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_1_bits_snpHitReleaseMeta_accessed,
+  input         io_in_1_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_1_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [11:0] io_in_1_bits_txnID,
+  input  [10:0] io_in_1_bits_homeNID,
+  input  [11:0] io_in_1_bits_dbID,
+  input  [6:0]  io_in_1_bits_chiOpcode,
+  input  [2:0]  io_in_1_bits_resp,
+  input  [2:0]  io_in_1_bits_fwdState,
+  input         io_in_1_bits_retToSrc,
+  input         io_in_1_bits_likelyshared,
+  input         io_in_1_bits_expCompAck,
+  input         io_in_1_bits_allowRetry,
+  input         io_in_1_bits_memAttr_allocate,
+  input         io_in_1_bits_memAttr_cacheable,
+  input         io_in_1_bits_memAttr_ewa,
+  input         io_in_1_bits_traceTag,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [2:0]  io_in_2_bits_channel,
+  input  [2:0]  io_in_2_bits_txChannel,
+  input  [7:0]  io_in_2_bits_set,
+  input  [33:0] io_in_2_bits_tag,
+  input  [5:0]  io_in_2_bits_off,
+  input         io_in_2_bits_alias,
+  input         io_in_2_bits_isKeyword,
+  input  [3:0]  io_in_2_bits_opcode,
+  input  [2:0]  io_in_2_bits_param,
+  input  [2:0]  io_in_2_bits_size,
+  input  [6:0]  io_in_2_bits_sourceId,
+  input         io_in_2_bits_denied,
+  input         io_in_2_bits_corrupt,
+  input         io_in_2_bits_aliasTask,
+  input         io_in_2_bits_useProbeData,
+  input         io_in_2_bits_mshrRetry,
+  input         io_in_2_bits_readProbeDataDown,
+  input         io_in_2_bits_fromL2pft,
+  input         io_in_2_bits_dirty,
+  input  [2:0]  io_in_2_bits_way,
+  input         io_in_2_bits_meta_dirty,
+  input  [1:0]  io_in_2_bits_meta_state,
+  input         io_in_2_bits_meta_clients,
+  input         io_in_2_bits_meta_alias,
+  input         io_in_2_bits_meta_prefetch,
+  input  [3:0]  io_in_2_bits_meta_prefetchSrc,
+  input         io_in_2_bits_meta_accessed,
+  input         io_in_2_bits_meta_tagErr,
+  input         io_in_2_bits_meta_dataErr,
+  input         io_in_2_bits_metaWen,
+  input         io_in_2_bits_tagWen,
+  input         io_in_2_bits_dsWen,
+  input         io_in_2_bits_replTask,
+  input         io_in_2_bits_cmoTask,
+  input  [4:0]  io_in_2_bits_reqSource,
+  input         io_in_2_bits_mergeA,
+  input  [5:0]  io_in_2_bits_aMergeTask_off,
+  input         io_in_2_bits_aMergeTask_alias,
+  input  [43:0] io_in_2_bits_aMergeTask_vaddr,
+  input         io_in_2_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_2_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_2_bits_aMergeTask_param,
+  input  [6:0]  io_in_2_bits_aMergeTask_sourceId,
+  input         io_in_2_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_2_bits_aMergeTask_meta_state,
+  input         io_in_2_bits_aMergeTask_meta_clients,
+  input         io_in_2_bits_aMergeTask_meta_alias,
+  input         io_in_2_bits_aMergeTask_meta_accessed,
+  input         io_in_2_bits_snpHitRelease,
+  input         io_in_2_bits_snpHitReleaseToInval,
+  input         io_in_2_bits_snpHitReleaseToClean,
+  input         io_in_2_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_2_bits_snpHitReleaseIdx,
+  input         io_in_2_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_2_bits_snpHitReleaseMeta_state,
+  input         io_in_2_bits_snpHitReleaseMeta_clients,
+  input         io_in_2_bits_snpHitReleaseMeta_alias,
+  input         io_in_2_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_2_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_2_bits_snpHitReleaseMeta_accessed,
+  input         io_in_2_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_2_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_2_bits_tgtID,
+  input  [11:0] io_in_2_bits_txnID,
+  input  [10:0] io_in_2_bits_homeNID,
+  input  [11:0] io_in_2_bits_dbID,
+  input  [6:0]  io_in_2_bits_chiOpcode,
+  input  [2:0]  io_in_2_bits_resp,
+  input  [2:0]  io_in_2_bits_fwdState,
+  input         io_in_2_bits_retToSrc,
+  input         io_in_2_bits_likelyshared,
+  input         io_in_2_bits_expCompAck,
+  input         io_in_2_bits_allowRetry,
+  input         io_in_2_bits_memAttr_allocate,
+  input         io_in_2_bits_memAttr_cacheable,
+  input         io_in_2_bits_memAttr_ewa,
+  input         io_in_2_bits_traceTag,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [2:0]  io_in_3_bits_channel,
+  input  [2:0]  io_in_3_bits_txChannel,
+  input  [7:0]  io_in_3_bits_set,
+  input  [33:0] io_in_3_bits_tag,
+  input  [5:0]  io_in_3_bits_off,
+  input         io_in_3_bits_alias,
+  input         io_in_3_bits_isKeyword,
+  input  [3:0]  io_in_3_bits_opcode,
+  input  [2:0]  io_in_3_bits_param,
+  input  [2:0]  io_in_3_bits_size,
+  input  [6:0]  io_in_3_bits_sourceId,
+  input         io_in_3_bits_denied,
+  input         io_in_3_bits_corrupt,
+  input         io_in_3_bits_aliasTask,
+  input         io_in_3_bits_useProbeData,
+  input         io_in_3_bits_mshrRetry,
+  input         io_in_3_bits_readProbeDataDown,
+  input         io_in_3_bits_fromL2pft,
+  input         io_in_3_bits_dirty,
+  input  [2:0]  io_in_3_bits_way,
+  input         io_in_3_bits_meta_dirty,
+  input  [1:0]  io_in_3_bits_meta_state,
+  input         io_in_3_bits_meta_clients,
+  input         io_in_3_bits_meta_alias,
+  input         io_in_3_bits_meta_prefetch,
+  input  [3:0]  io_in_3_bits_meta_prefetchSrc,
+  input         io_in_3_bits_meta_accessed,
+  input         io_in_3_bits_meta_tagErr,
+  input         io_in_3_bits_meta_dataErr,
+  input         io_in_3_bits_metaWen,
+  input         io_in_3_bits_tagWen,
+  input         io_in_3_bits_dsWen,
+  input         io_in_3_bits_replTask,
+  input         io_in_3_bits_cmoTask,
+  input  [4:0]  io_in_3_bits_reqSource,
+  input         io_in_3_bits_mergeA,
+  input  [5:0]  io_in_3_bits_aMergeTask_off,
+  input         io_in_3_bits_aMergeTask_alias,
+  input  [43:0] io_in_3_bits_aMergeTask_vaddr,
+  input         io_in_3_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_3_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_3_bits_aMergeTask_param,
+  input  [6:0]  io_in_3_bits_aMergeTask_sourceId,
+  input         io_in_3_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_3_bits_aMergeTask_meta_state,
+  input         io_in_3_bits_aMergeTask_meta_clients,
+  input         io_in_3_bits_aMergeTask_meta_alias,
+  input         io_in_3_bits_aMergeTask_meta_accessed,
+  input         io_in_3_bits_snpHitRelease,
+  input         io_in_3_bits_snpHitReleaseToInval,
+  input         io_in_3_bits_snpHitReleaseToClean,
+  input         io_in_3_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_3_bits_snpHitReleaseIdx,
+  input         io_in_3_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_3_bits_snpHitReleaseMeta_state,
+  input         io_in_3_bits_snpHitReleaseMeta_clients,
+  input         io_in_3_bits_snpHitReleaseMeta_alias,
+  input         io_in_3_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_3_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_3_bits_snpHitReleaseMeta_accessed,
+  input         io_in_3_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_3_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_3_bits_tgtID,
+  input  [11:0] io_in_3_bits_txnID,
+  input  [10:0] io_in_3_bits_homeNID,
+  input  [11:0] io_in_3_bits_dbID,
+  input  [6:0]  io_in_3_bits_chiOpcode,
+  input  [2:0]  io_in_3_bits_resp,
+  input  [2:0]  io_in_3_bits_fwdState,
+  input         io_in_3_bits_retToSrc,
+  input         io_in_3_bits_likelyshared,
+  input         io_in_3_bits_expCompAck,
+  input         io_in_3_bits_allowRetry,
+  input         io_in_3_bits_memAttr_allocate,
+  input         io_in_3_bits_memAttr_cacheable,
+  input         io_in_3_bits_memAttr_ewa,
+  input         io_in_3_bits_traceTag,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [2:0]  io_in_4_bits_channel,
+  input  [2:0]  io_in_4_bits_txChannel,
+  input  [7:0]  io_in_4_bits_set,
+  input  [33:0] io_in_4_bits_tag,
+  input  [5:0]  io_in_4_bits_off,
+  input         io_in_4_bits_alias,
+  input         io_in_4_bits_isKeyword,
+  input  [3:0]  io_in_4_bits_opcode,
+  input  [2:0]  io_in_4_bits_param,
+  input  [2:0]  io_in_4_bits_size,
+  input  [6:0]  io_in_4_bits_sourceId,
+  input         io_in_4_bits_denied,
+  input         io_in_4_bits_corrupt,
+  input         io_in_4_bits_aliasTask,
+  input         io_in_4_bits_useProbeData,
+  input         io_in_4_bits_mshrRetry,
+  input         io_in_4_bits_readProbeDataDown,
+  input         io_in_4_bits_fromL2pft,
+  input         io_in_4_bits_dirty,
+  input  [2:0]  io_in_4_bits_way,
+  input         io_in_4_bits_meta_dirty,
+  input  [1:0]  io_in_4_bits_meta_state,
+  input         io_in_4_bits_meta_clients,
+  input         io_in_4_bits_meta_alias,
+  input         io_in_4_bits_meta_prefetch,
+  input  [3:0]  io_in_4_bits_meta_prefetchSrc,
+  input         io_in_4_bits_meta_accessed,
+  input         io_in_4_bits_meta_tagErr,
+  input         io_in_4_bits_meta_dataErr,
+  input         io_in_4_bits_metaWen,
+  input         io_in_4_bits_tagWen,
+  input         io_in_4_bits_dsWen,
+  input         io_in_4_bits_replTask,
+  input         io_in_4_bits_cmoTask,
+  input  [4:0]  io_in_4_bits_reqSource,
+  input         io_in_4_bits_mergeA,
+  input  [5:0]  io_in_4_bits_aMergeTask_off,
+  input         io_in_4_bits_aMergeTask_alias,
+  input  [43:0] io_in_4_bits_aMergeTask_vaddr,
+  input         io_in_4_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_4_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_4_bits_aMergeTask_param,
+  input  [6:0]  io_in_4_bits_aMergeTask_sourceId,
+  input         io_in_4_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_4_bits_aMergeTask_meta_state,
+  input         io_in_4_bits_aMergeTask_meta_clients,
+  input         io_in_4_bits_aMergeTask_meta_alias,
+  input         io_in_4_bits_aMergeTask_meta_accessed,
+  input         io_in_4_bits_snpHitRelease,
+  input         io_in_4_bits_snpHitReleaseToInval,
+  input         io_in_4_bits_snpHitReleaseToClean,
+  input         io_in_4_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_4_bits_snpHitReleaseIdx,
+  input         io_in_4_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_4_bits_snpHitReleaseMeta_state,
+  input         io_in_4_bits_snpHitReleaseMeta_clients,
+  input         io_in_4_bits_snpHitReleaseMeta_alias,
+  input         io_in_4_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_4_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_4_bits_snpHitReleaseMeta_accessed,
+  input         io_in_4_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_4_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_4_bits_tgtID,
+  input  [11:0] io_in_4_bits_txnID,
+  input  [10:0] io_in_4_bits_homeNID,
+  input  [11:0] io_in_4_bits_dbID,
+  input  [6:0]  io_in_4_bits_chiOpcode,
+  input  [2:0]  io_in_4_bits_resp,
+  input  [2:0]  io_in_4_bits_fwdState,
+  input         io_in_4_bits_retToSrc,
+  input         io_in_4_bits_likelyshared,
+  input         io_in_4_bits_expCompAck,
+  input         io_in_4_bits_allowRetry,
+  input         io_in_4_bits_memAttr_allocate,
+  input         io_in_4_bits_memAttr_cacheable,
+  input         io_in_4_bits_memAttr_ewa,
+  input         io_in_4_bits_traceTag,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [2:0]  io_in_5_bits_channel,
+  input  [2:0]  io_in_5_bits_txChannel,
+  input  [7:0]  io_in_5_bits_set,
+  input  [33:0] io_in_5_bits_tag,
+  input  [5:0]  io_in_5_bits_off,
+  input         io_in_5_bits_alias,
+  input         io_in_5_bits_isKeyword,
+  input  [3:0]  io_in_5_bits_opcode,
+  input  [2:0]  io_in_5_bits_param,
+  input  [2:0]  io_in_5_bits_size,
+  input  [6:0]  io_in_5_bits_sourceId,
+  input         io_in_5_bits_denied,
+  input         io_in_5_bits_corrupt,
+  input         io_in_5_bits_aliasTask,
+  input         io_in_5_bits_useProbeData,
+  input         io_in_5_bits_mshrRetry,
+  input         io_in_5_bits_readProbeDataDown,
+  input         io_in_5_bits_fromL2pft,
+  input         io_in_5_bits_dirty,
+  input  [2:0]  io_in_5_bits_way,
+  input         io_in_5_bits_meta_dirty,
+  input  [1:0]  io_in_5_bits_meta_state,
+  input         io_in_5_bits_meta_clients,
+  input         io_in_5_bits_meta_alias,
+  input         io_in_5_bits_meta_prefetch,
+  input  [3:0]  io_in_5_bits_meta_prefetchSrc,
+  input         io_in_5_bits_meta_accessed,
+  input         io_in_5_bits_meta_tagErr,
+  input         io_in_5_bits_meta_dataErr,
+  input         io_in_5_bits_metaWen,
+  input         io_in_5_bits_tagWen,
+  input         io_in_5_bits_dsWen,
+  input         io_in_5_bits_replTask,
+  input         io_in_5_bits_cmoTask,
+  input  [4:0]  io_in_5_bits_reqSource,
+  input         io_in_5_bits_mergeA,
+  input  [5:0]  io_in_5_bits_aMergeTask_off,
+  input         io_in_5_bits_aMergeTask_alias,
+  input  [43:0] io_in_5_bits_aMergeTask_vaddr,
+  input         io_in_5_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_5_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_5_bits_aMergeTask_param,
+  input  [6:0]  io_in_5_bits_aMergeTask_sourceId,
+  input         io_in_5_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_5_bits_aMergeTask_meta_state,
+  input         io_in_5_bits_aMergeTask_meta_clients,
+  input         io_in_5_bits_aMergeTask_meta_alias,
+  input         io_in_5_bits_aMergeTask_meta_accessed,
+  input         io_in_5_bits_snpHitRelease,
+  input         io_in_5_bits_snpHitReleaseToInval,
+  input         io_in_5_bits_snpHitReleaseToClean,
+  input         io_in_5_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_5_bits_snpHitReleaseIdx,
+  input         io_in_5_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_5_bits_snpHitReleaseMeta_state,
+  input         io_in_5_bits_snpHitReleaseMeta_clients,
+  input         io_in_5_bits_snpHitReleaseMeta_alias,
+  input         io_in_5_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_5_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_5_bits_snpHitReleaseMeta_accessed,
+  input         io_in_5_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_5_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_5_bits_tgtID,
+  input  [11:0] io_in_5_bits_txnID,
+  input  [10:0] io_in_5_bits_homeNID,
+  input  [11:0] io_in_5_bits_dbID,
+  input  [6:0]  io_in_5_bits_chiOpcode,
+  input  [2:0]  io_in_5_bits_resp,
+  input  [2:0]  io_in_5_bits_fwdState,
+  input         io_in_5_bits_retToSrc,
+  input         io_in_5_bits_likelyshared,
+  input         io_in_5_bits_expCompAck,
+  input         io_in_5_bits_allowRetry,
+  input         io_in_5_bits_memAttr_allocate,
+  input         io_in_5_bits_memAttr_cacheable,
+  input         io_in_5_bits_memAttr_ewa,
+  input         io_in_5_bits_traceTag,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [2:0]  io_in_6_bits_channel,
+  input  [2:0]  io_in_6_bits_txChannel,
+  input  [7:0]  io_in_6_bits_set,
+  input  [33:0] io_in_6_bits_tag,
+  input  [5:0]  io_in_6_bits_off,
+  input         io_in_6_bits_alias,
+  input         io_in_6_bits_isKeyword,
+  input  [3:0]  io_in_6_bits_opcode,
+  input  [2:0]  io_in_6_bits_param,
+  input  [2:0]  io_in_6_bits_size,
+  input  [6:0]  io_in_6_bits_sourceId,
+  input         io_in_6_bits_denied,
+  input         io_in_6_bits_corrupt,
+  input         io_in_6_bits_aliasTask,
+  input         io_in_6_bits_useProbeData,
+  input         io_in_6_bits_mshrRetry,
+  input         io_in_6_bits_readProbeDataDown,
+  input         io_in_6_bits_fromL2pft,
+  input         io_in_6_bits_dirty,
+  input  [2:0]  io_in_6_bits_way,
+  input         io_in_6_bits_meta_dirty,
+  input  [1:0]  io_in_6_bits_meta_state,
+  input         io_in_6_bits_meta_clients,
+  input         io_in_6_bits_meta_alias,
+  input         io_in_6_bits_meta_prefetch,
+  input  [3:0]  io_in_6_bits_meta_prefetchSrc,
+  input         io_in_6_bits_meta_accessed,
+  input         io_in_6_bits_meta_tagErr,
+  input         io_in_6_bits_meta_dataErr,
+  input         io_in_6_bits_metaWen,
+  input         io_in_6_bits_tagWen,
+  input         io_in_6_bits_dsWen,
+  input         io_in_6_bits_replTask,
+  input         io_in_6_bits_cmoTask,
+  input  [4:0]  io_in_6_bits_reqSource,
+  input         io_in_6_bits_mergeA,
+  input  [5:0]  io_in_6_bits_aMergeTask_off,
+  input         io_in_6_bits_aMergeTask_alias,
+  input  [43:0] io_in_6_bits_aMergeTask_vaddr,
+  input         io_in_6_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_6_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_6_bits_aMergeTask_param,
+  input  [6:0]  io_in_6_bits_aMergeTask_sourceId,
+  input         io_in_6_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_6_bits_aMergeTask_meta_state,
+  input         io_in_6_bits_aMergeTask_meta_clients,
+  input         io_in_6_bits_aMergeTask_meta_alias,
+  input         io_in_6_bits_aMergeTask_meta_accessed,
+  input         io_in_6_bits_snpHitRelease,
+  input         io_in_6_bits_snpHitReleaseToInval,
+  input         io_in_6_bits_snpHitReleaseToClean,
+  input         io_in_6_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_6_bits_snpHitReleaseIdx,
+  input         io_in_6_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_6_bits_snpHitReleaseMeta_state,
+  input         io_in_6_bits_snpHitReleaseMeta_clients,
+  input         io_in_6_bits_snpHitReleaseMeta_alias,
+  input         io_in_6_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_6_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_6_bits_snpHitReleaseMeta_accessed,
+  input         io_in_6_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_6_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_6_bits_tgtID,
+  input  [11:0] io_in_6_bits_txnID,
+  input  [10:0] io_in_6_bits_homeNID,
+  input  [11:0] io_in_6_bits_dbID,
+  input  [6:0]  io_in_6_bits_chiOpcode,
+  input  [2:0]  io_in_6_bits_resp,
+  input  [2:0]  io_in_6_bits_fwdState,
+  input         io_in_6_bits_retToSrc,
+  input         io_in_6_bits_likelyshared,
+  input         io_in_6_bits_expCompAck,
+  input         io_in_6_bits_allowRetry,
+  input         io_in_6_bits_memAttr_allocate,
+  input         io_in_6_bits_memAttr_cacheable,
+  input         io_in_6_bits_memAttr_ewa,
+  input         io_in_6_bits_traceTag,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [2:0]  io_in_7_bits_channel,
+  input  [2:0]  io_in_7_bits_txChannel,
+  input  [7:0]  io_in_7_bits_set,
+  input  [33:0] io_in_7_bits_tag,
+  input  [5:0]  io_in_7_bits_off,
+  input         io_in_7_bits_alias,
+  input         io_in_7_bits_isKeyword,
+  input  [3:0]  io_in_7_bits_opcode,
+  input  [2:0]  io_in_7_bits_param,
+  input  [2:0]  io_in_7_bits_size,
+  input  [6:0]  io_in_7_bits_sourceId,
+  input         io_in_7_bits_denied,
+  input         io_in_7_bits_corrupt,
+  input         io_in_7_bits_aliasTask,
+  input         io_in_7_bits_useProbeData,
+  input         io_in_7_bits_mshrRetry,
+  input         io_in_7_bits_readProbeDataDown,
+  input         io_in_7_bits_fromL2pft,
+  input         io_in_7_bits_dirty,
+  input  [2:0]  io_in_7_bits_way,
+  input         io_in_7_bits_meta_dirty,
+  input  [1:0]  io_in_7_bits_meta_state,
+  input         io_in_7_bits_meta_clients,
+  input         io_in_7_bits_meta_alias,
+  input         io_in_7_bits_meta_prefetch,
+  input  [3:0]  io_in_7_bits_meta_prefetchSrc,
+  input         io_in_7_bits_meta_accessed,
+  input         io_in_7_bits_meta_tagErr,
+  input         io_in_7_bits_meta_dataErr,
+  input         io_in_7_bits_metaWen,
+  input         io_in_7_bits_tagWen,
+  input         io_in_7_bits_dsWen,
+  input         io_in_7_bits_replTask,
+  input         io_in_7_bits_cmoTask,
+  input  [4:0]  io_in_7_bits_reqSource,
+  input         io_in_7_bits_mergeA,
+  input  [5:0]  io_in_7_bits_aMergeTask_off,
+  input         io_in_7_bits_aMergeTask_alias,
+  input  [43:0] io_in_7_bits_aMergeTask_vaddr,
+  input         io_in_7_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_7_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_7_bits_aMergeTask_param,
+  input  [6:0]  io_in_7_bits_aMergeTask_sourceId,
+  input         io_in_7_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_7_bits_aMergeTask_meta_state,
+  input         io_in_7_bits_aMergeTask_meta_clients,
+  input         io_in_7_bits_aMergeTask_meta_alias,
+  input         io_in_7_bits_aMergeTask_meta_accessed,
+  input         io_in_7_bits_snpHitRelease,
+  input         io_in_7_bits_snpHitReleaseToInval,
+  input         io_in_7_bits_snpHitReleaseToClean,
+  input         io_in_7_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_7_bits_snpHitReleaseIdx,
+  input         io_in_7_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_7_bits_snpHitReleaseMeta_state,
+  input         io_in_7_bits_snpHitReleaseMeta_clients,
+  input         io_in_7_bits_snpHitReleaseMeta_alias,
+  input         io_in_7_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_7_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_7_bits_snpHitReleaseMeta_accessed,
+  input         io_in_7_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_7_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_7_bits_tgtID,
+  input  [11:0] io_in_7_bits_txnID,
+  input  [10:0] io_in_7_bits_homeNID,
+  input  [11:0] io_in_7_bits_dbID,
+  input  [6:0]  io_in_7_bits_chiOpcode,
+  input  [2:0]  io_in_7_bits_resp,
+  input  [2:0]  io_in_7_bits_fwdState,
+  input         io_in_7_bits_retToSrc,
+  input         io_in_7_bits_likelyshared,
+  input         io_in_7_bits_expCompAck,
+  input         io_in_7_bits_allowRetry,
+  input         io_in_7_bits_memAttr_allocate,
+  input         io_in_7_bits_memAttr_cacheable,
+  input         io_in_7_bits_memAttr_ewa,
+  input         io_in_7_bits_traceTag,
+  output        io_in_8_ready,
+  input         io_in_8_valid,
+  input  [2:0]  io_in_8_bits_channel,
+  input  [2:0]  io_in_8_bits_txChannel,
+  input  [7:0]  io_in_8_bits_set,
+  input  [33:0] io_in_8_bits_tag,
+  input  [5:0]  io_in_8_bits_off,
+  input         io_in_8_bits_alias,
+  input         io_in_8_bits_isKeyword,
+  input  [3:0]  io_in_8_bits_opcode,
+  input  [2:0]  io_in_8_bits_param,
+  input  [2:0]  io_in_8_bits_size,
+  input  [6:0]  io_in_8_bits_sourceId,
+  input         io_in_8_bits_denied,
+  input         io_in_8_bits_corrupt,
+  input         io_in_8_bits_aliasTask,
+  input         io_in_8_bits_useProbeData,
+  input         io_in_8_bits_mshrRetry,
+  input         io_in_8_bits_readProbeDataDown,
+  input         io_in_8_bits_fromL2pft,
+  input         io_in_8_bits_dirty,
+  input  [2:0]  io_in_8_bits_way,
+  input         io_in_8_bits_meta_dirty,
+  input  [1:0]  io_in_8_bits_meta_state,
+  input         io_in_8_bits_meta_clients,
+  input         io_in_8_bits_meta_alias,
+  input         io_in_8_bits_meta_prefetch,
+  input  [3:0]  io_in_8_bits_meta_prefetchSrc,
+  input         io_in_8_bits_meta_accessed,
+  input         io_in_8_bits_meta_tagErr,
+  input         io_in_8_bits_meta_dataErr,
+  input         io_in_8_bits_metaWen,
+  input         io_in_8_bits_tagWen,
+  input         io_in_8_bits_dsWen,
+  input         io_in_8_bits_replTask,
+  input         io_in_8_bits_cmoTask,
+  input  [4:0]  io_in_8_bits_reqSource,
+  input         io_in_8_bits_mergeA,
+  input  [5:0]  io_in_8_bits_aMergeTask_off,
+  input         io_in_8_bits_aMergeTask_alias,
+  input  [43:0] io_in_8_bits_aMergeTask_vaddr,
+  input         io_in_8_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_8_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_8_bits_aMergeTask_param,
+  input  [6:0]  io_in_8_bits_aMergeTask_sourceId,
+  input         io_in_8_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_8_bits_aMergeTask_meta_state,
+  input         io_in_8_bits_aMergeTask_meta_clients,
+  input         io_in_8_bits_aMergeTask_meta_alias,
+  input         io_in_8_bits_aMergeTask_meta_accessed,
+  input         io_in_8_bits_snpHitRelease,
+  input         io_in_8_bits_snpHitReleaseToInval,
+  input         io_in_8_bits_snpHitReleaseToClean,
+  input         io_in_8_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_8_bits_snpHitReleaseIdx,
+  input         io_in_8_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_8_bits_snpHitReleaseMeta_state,
+  input         io_in_8_bits_snpHitReleaseMeta_clients,
+  input         io_in_8_bits_snpHitReleaseMeta_alias,
+  input         io_in_8_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_8_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_8_bits_snpHitReleaseMeta_accessed,
+  input         io_in_8_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_8_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_8_bits_tgtID,
+  input  [11:0] io_in_8_bits_txnID,
+  input  [10:0] io_in_8_bits_homeNID,
+  input  [11:0] io_in_8_bits_dbID,
+  input  [6:0]  io_in_8_bits_chiOpcode,
+  input  [2:0]  io_in_8_bits_resp,
+  input  [2:0]  io_in_8_bits_fwdState,
+  input         io_in_8_bits_retToSrc,
+  input         io_in_8_bits_likelyshared,
+  input         io_in_8_bits_expCompAck,
+  input         io_in_8_bits_allowRetry,
+  input         io_in_8_bits_memAttr_allocate,
+  input         io_in_8_bits_memAttr_cacheable,
+  input         io_in_8_bits_memAttr_ewa,
+  input         io_in_8_bits_traceTag,
+  output        io_in_9_ready,
+  input         io_in_9_valid,
+  input  [2:0]  io_in_9_bits_channel,
+  input  [2:0]  io_in_9_bits_txChannel,
+  input  [7:0]  io_in_9_bits_set,
+  input  [33:0] io_in_9_bits_tag,
+  input  [5:0]  io_in_9_bits_off,
+  input         io_in_9_bits_alias,
+  input         io_in_9_bits_isKeyword,
+  input  [3:0]  io_in_9_bits_opcode,
+  input  [2:0]  io_in_9_bits_param,
+  input  [2:0]  io_in_9_bits_size,
+  input  [6:0]  io_in_9_bits_sourceId,
+  input         io_in_9_bits_denied,
+  input         io_in_9_bits_corrupt,
+  input         io_in_9_bits_aliasTask,
+  input         io_in_9_bits_useProbeData,
+  input         io_in_9_bits_mshrRetry,
+  input         io_in_9_bits_readProbeDataDown,
+  input         io_in_9_bits_fromL2pft,
+  input         io_in_9_bits_dirty,
+  input  [2:0]  io_in_9_bits_way,
+  input         io_in_9_bits_meta_dirty,
+  input  [1:0]  io_in_9_bits_meta_state,
+  input         io_in_9_bits_meta_clients,
+  input         io_in_9_bits_meta_alias,
+  input         io_in_9_bits_meta_prefetch,
+  input  [3:0]  io_in_9_bits_meta_prefetchSrc,
+  input         io_in_9_bits_meta_accessed,
+  input         io_in_9_bits_meta_tagErr,
+  input         io_in_9_bits_meta_dataErr,
+  input         io_in_9_bits_metaWen,
+  input         io_in_9_bits_tagWen,
+  input         io_in_9_bits_dsWen,
+  input         io_in_9_bits_replTask,
+  input         io_in_9_bits_cmoTask,
+  input  [4:0]  io_in_9_bits_reqSource,
+  input         io_in_9_bits_mergeA,
+  input  [5:0]  io_in_9_bits_aMergeTask_off,
+  input         io_in_9_bits_aMergeTask_alias,
+  input  [43:0] io_in_9_bits_aMergeTask_vaddr,
+  input         io_in_9_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_9_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_9_bits_aMergeTask_param,
+  input  [6:0]  io_in_9_bits_aMergeTask_sourceId,
+  input         io_in_9_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_9_bits_aMergeTask_meta_state,
+  input         io_in_9_bits_aMergeTask_meta_clients,
+  input         io_in_9_bits_aMergeTask_meta_alias,
+  input         io_in_9_bits_aMergeTask_meta_accessed,
+  input         io_in_9_bits_snpHitRelease,
+  input         io_in_9_bits_snpHitReleaseToInval,
+  input         io_in_9_bits_snpHitReleaseToClean,
+  input         io_in_9_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_9_bits_snpHitReleaseIdx,
+  input         io_in_9_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_9_bits_snpHitReleaseMeta_state,
+  input         io_in_9_bits_snpHitReleaseMeta_clients,
+  input         io_in_9_bits_snpHitReleaseMeta_alias,
+  input         io_in_9_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_9_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_9_bits_snpHitReleaseMeta_accessed,
+  input         io_in_9_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_9_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_9_bits_tgtID,
+  input  [11:0] io_in_9_bits_txnID,
+  input  [10:0] io_in_9_bits_homeNID,
+  input  [11:0] io_in_9_bits_dbID,
+  input  [6:0]  io_in_9_bits_chiOpcode,
+  input  [2:0]  io_in_9_bits_resp,
+  input  [2:0]  io_in_9_bits_fwdState,
+  input         io_in_9_bits_retToSrc,
+  input         io_in_9_bits_likelyshared,
+  input         io_in_9_bits_expCompAck,
+  input         io_in_9_bits_allowRetry,
+  input         io_in_9_bits_memAttr_allocate,
+  input         io_in_9_bits_memAttr_cacheable,
+  input         io_in_9_bits_memAttr_ewa,
+  input         io_in_9_bits_traceTag,
+  output        io_in_10_ready,
+  input         io_in_10_valid,
+  input  [2:0]  io_in_10_bits_channel,
+  input  [2:0]  io_in_10_bits_txChannel,
+  input  [7:0]  io_in_10_bits_set,
+  input  [33:0] io_in_10_bits_tag,
+  input  [5:0]  io_in_10_bits_off,
+  input         io_in_10_bits_alias,
+  input         io_in_10_bits_isKeyword,
+  input  [3:0]  io_in_10_bits_opcode,
+  input  [2:0]  io_in_10_bits_param,
+  input  [2:0]  io_in_10_bits_size,
+  input  [6:0]  io_in_10_bits_sourceId,
+  input         io_in_10_bits_denied,
+  input         io_in_10_bits_corrupt,
+  input         io_in_10_bits_aliasTask,
+  input         io_in_10_bits_useProbeData,
+  input         io_in_10_bits_mshrRetry,
+  input         io_in_10_bits_readProbeDataDown,
+  input         io_in_10_bits_fromL2pft,
+  input         io_in_10_bits_dirty,
+  input  [2:0]  io_in_10_bits_way,
+  input         io_in_10_bits_meta_dirty,
+  input  [1:0]  io_in_10_bits_meta_state,
+  input         io_in_10_bits_meta_clients,
+  input         io_in_10_bits_meta_alias,
+  input         io_in_10_bits_meta_prefetch,
+  input  [3:0]  io_in_10_bits_meta_prefetchSrc,
+  input         io_in_10_bits_meta_accessed,
+  input         io_in_10_bits_meta_tagErr,
+  input         io_in_10_bits_meta_dataErr,
+  input         io_in_10_bits_metaWen,
+  input         io_in_10_bits_tagWen,
+  input         io_in_10_bits_dsWen,
+  input         io_in_10_bits_replTask,
+  input         io_in_10_bits_cmoTask,
+  input  [4:0]  io_in_10_bits_reqSource,
+  input         io_in_10_bits_mergeA,
+  input  [5:0]  io_in_10_bits_aMergeTask_off,
+  input         io_in_10_bits_aMergeTask_alias,
+  input  [43:0] io_in_10_bits_aMergeTask_vaddr,
+  input         io_in_10_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_10_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_10_bits_aMergeTask_param,
+  input  [6:0]  io_in_10_bits_aMergeTask_sourceId,
+  input         io_in_10_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_10_bits_aMergeTask_meta_state,
+  input         io_in_10_bits_aMergeTask_meta_clients,
+  input         io_in_10_bits_aMergeTask_meta_alias,
+  input         io_in_10_bits_aMergeTask_meta_accessed,
+  input         io_in_10_bits_snpHitRelease,
+  input         io_in_10_bits_snpHitReleaseToInval,
+  input         io_in_10_bits_snpHitReleaseToClean,
+  input         io_in_10_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_10_bits_snpHitReleaseIdx,
+  input         io_in_10_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_10_bits_snpHitReleaseMeta_state,
+  input         io_in_10_bits_snpHitReleaseMeta_clients,
+  input         io_in_10_bits_snpHitReleaseMeta_alias,
+  input         io_in_10_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_10_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_10_bits_snpHitReleaseMeta_accessed,
+  input         io_in_10_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_10_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_10_bits_tgtID,
+  input  [11:0] io_in_10_bits_txnID,
+  input  [10:0] io_in_10_bits_homeNID,
+  input  [11:0] io_in_10_bits_dbID,
+  input  [6:0]  io_in_10_bits_chiOpcode,
+  input  [2:0]  io_in_10_bits_resp,
+  input  [2:0]  io_in_10_bits_fwdState,
+  input         io_in_10_bits_retToSrc,
+  input         io_in_10_bits_likelyshared,
+  input         io_in_10_bits_expCompAck,
+  input         io_in_10_bits_allowRetry,
+  input         io_in_10_bits_memAttr_allocate,
+  input         io_in_10_bits_memAttr_cacheable,
+  input         io_in_10_bits_memAttr_ewa,
+  input         io_in_10_bits_traceTag,
+  output        io_in_11_ready,
+  input         io_in_11_valid,
+  input  [2:0]  io_in_11_bits_channel,
+  input  [2:0]  io_in_11_bits_txChannel,
+  input  [7:0]  io_in_11_bits_set,
+  input  [33:0] io_in_11_bits_tag,
+  input  [5:0]  io_in_11_bits_off,
+  input         io_in_11_bits_alias,
+  input         io_in_11_bits_isKeyword,
+  input  [3:0]  io_in_11_bits_opcode,
+  input  [2:0]  io_in_11_bits_param,
+  input  [2:0]  io_in_11_bits_size,
+  input  [6:0]  io_in_11_bits_sourceId,
+  input         io_in_11_bits_denied,
+  input         io_in_11_bits_corrupt,
+  input         io_in_11_bits_aliasTask,
+  input         io_in_11_bits_useProbeData,
+  input         io_in_11_bits_mshrRetry,
+  input         io_in_11_bits_readProbeDataDown,
+  input         io_in_11_bits_fromL2pft,
+  input         io_in_11_bits_dirty,
+  input  [2:0]  io_in_11_bits_way,
+  input         io_in_11_bits_meta_dirty,
+  input  [1:0]  io_in_11_bits_meta_state,
+  input         io_in_11_bits_meta_clients,
+  input         io_in_11_bits_meta_alias,
+  input         io_in_11_bits_meta_prefetch,
+  input  [3:0]  io_in_11_bits_meta_prefetchSrc,
+  input         io_in_11_bits_meta_accessed,
+  input         io_in_11_bits_meta_tagErr,
+  input         io_in_11_bits_meta_dataErr,
+  input         io_in_11_bits_metaWen,
+  input         io_in_11_bits_tagWen,
+  input         io_in_11_bits_dsWen,
+  input         io_in_11_bits_replTask,
+  input         io_in_11_bits_cmoTask,
+  input  [4:0]  io_in_11_bits_reqSource,
+  input         io_in_11_bits_mergeA,
+  input  [5:0]  io_in_11_bits_aMergeTask_off,
+  input         io_in_11_bits_aMergeTask_alias,
+  input  [43:0] io_in_11_bits_aMergeTask_vaddr,
+  input         io_in_11_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_11_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_11_bits_aMergeTask_param,
+  input  [6:0]  io_in_11_bits_aMergeTask_sourceId,
+  input         io_in_11_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_11_bits_aMergeTask_meta_state,
+  input         io_in_11_bits_aMergeTask_meta_clients,
+  input         io_in_11_bits_aMergeTask_meta_alias,
+  input         io_in_11_bits_aMergeTask_meta_accessed,
+  input         io_in_11_bits_snpHitRelease,
+  input         io_in_11_bits_snpHitReleaseToInval,
+  input         io_in_11_bits_snpHitReleaseToClean,
+  input         io_in_11_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_11_bits_snpHitReleaseIdx,
+  input         io_in_11_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_11_bits_snpHitReleaseMeta_state,
+  input         io_in_11_bits_snpHitReleaseMeta_clients,
+  input         io_in_11_bits_snpHitReleaseMeta_alias,
+  input         io_in_11_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_11_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_11_bits_snpHitReleaseMeta_accessed,
+  input         io_in_11_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_11_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_11_bits_tgtID,
+  input  [11:0] io_in_11_bits_txnID,
+  input  [10:0] io_in_11_bits_homeNID,
+  input  [11:0] io_in_11_bits_dbID,
+  input  [6:0]  io_in_11_bits_chiOpcode,
+  input  [2:0]  io_in_11_bits_resp,
+  input  [2:0]  io_in_11_bits_fwdState,
+  input         io_in_11_bits_retToSrc,
+  input         io_in_11_bits_likelyshared,
+  input         io_in_11_bits_expCompAck,
+  input         io_in_11_bits_allowRetry,
+  input         io_in_11_bits_memAttr_allocate,
+  input         io_in_11_bits_memAttr_cacheable,
+  input         io_in_11_bits_memAttr_ewa,
+  input         io_in_11_bits_traceTag,
+  output        io_in_12_ready,
+  input         io_in_12_valid,
+  input  [2:0]  io_in_12_bits_channel,
+  input  [2:0]  io_in_12_bits_txChannel,
+  input  [7:0]  io_in_12_bits_set,
+  input  [33:0] io_in_12_bits_tag,
+  input  [5:0]  io_in_12_bits_off,
+  input         io_in_12_bits_alias,
+  input         io_in_12_bits_isKeyword,
+  input  [3:0]  io_in_12_bits_opcode,
+  input  [2:0]  io_in_12_bits_param,
+  input  [2:0]  io_in_12_bits_size,
+  input  [6:0]  io_in_12_bits_sourceId,
+  input         io_in_12_bits_denied,
+  input         io_in_12_bits_corrupt,
+  input         io_in_12_bits_aliasTask,
+  input         io_in_12_bits_useProbeData,
+  input         io_in_12_bits_mshrRetry,
+  input         io_in_12_bits_readProbeDataDown,
+  input         io_in_12_bits_fromL2pft,
+  input         io_in_12_bits_dirty,
+  input  [2:0]  io_in_12_bits_way,
+  input         io_in_12_bits_meta_dirty,
+  input  [1:0]  io_in_12_bits_meta_state,
+  input         io_in_12_bits_meta_clients,
+  input         io_in_12_bits_meta_alias,
+  input         io_in_12_bits_meta_prefetch,
+  input  [3:0]  io_in_12_bits_meta_prefetchSrc,
+  input         io_in_12_bits_meta_accessed,
+  input         io_in_12_bits_meta_tagErr,
+  input         io_in_12_bits_meta_dataErr,
+  input         io_in_12_bits_metaWen,
+  input         io_in_12_bits_tagWen,
+  input         io_in_12_bits_dsWen,
+  input         io_in_12_bits_replTask,
+  input         io_in_12_bits_cmoTask,
+  input  [4:0]  io_in_12_bits_reqSource,
+  input         io_in_12_bits_mergeA,
+  input  [5:0]  io_in_12_bits_aMergeTask_off,
+  input         io_in_12_bits_aMergeTask_alias,
+  input  [43:0] io_in_12_bits_aMergeTask_vaddr,
+  input         io_in_12_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_12_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_12_bits_aMergeTask_param,
+  input  [6:0]  io_in_12_bits_aMergeTask_sourceId,
+  input         io_in_12_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_12_bits_aMergeTask_meta_state,
+  input         io_in_12_bits_aMergeTask_meta_clients,
+  input         io_in_12_bits_aMergeTask_meta_alias,
+  input         io_in_12_bits_aMergeTask_meta_accessed,
+  input         io_in_12_bits_snpHitRelease,
+  input         io_in_12_bits_snpHitReleaseToInval,
+  input         io_in_12_bits_snpHitReleaseToClean,
+  input         io_in_12_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_12_bits_snpHitReleaseIdx,
+  input         io_in_12_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_12_bits_snpHitReleaseMeta_state,
+  input         io_in_12_bits_snpHitReleaseMeta_clients,
+  input         io_in_12_bits_snpHitReleaseMeta_alias,
+  input         io_in_12_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_12_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_12_bits_snpHitReleaseMeta_accessed,
+  input         io_in_12_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_12_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_12_bits_tgtID,
+  input  [11:0] io_in_12_bits_txnID,
+  input  [10:0] io_in_12_bits_homeNID,
+  input  [11:0] io_in_12_bits_dbID,
+  input  [6:0]  io_in_12_bits_chiOpcode,
+  input  [2:0]  io_in_12_bits_resp,
+  input  [2:0]  io_in_12_bits_fwdState,
+  input         io_in_12_bits_retToSrc,
+  input         io_in_12_bits_likelyshared,
+  input         io_in_12_bits_expCompAck,
+  input         io_in_12_bits_allowRetry,
+  input         io_in_12_bits_memAttr_allocate,
+  input         io_in_12_bits_memAttr_cacheable,
+  input         io_in_12_bits_memAttr_ewa,
+  input         io_in_12_bits_traceTag,
+  output        io_in_13_ready,
+  input         io_in_13_valid,
+  input  [2:0]  io_in_13_bits_channel,
+  input  [2:0]  io_in_13_bits_txChannel,
+  input  [7:0]  io_in_13_bits_set,
+  input  [33:0] io_in_13_bits_tag,
+  input  [5:0]  io_in_13_bits_off,
+  input         io_in_13_bits_alias,
+  input         io_in_13_bits_isKeyword,
+  input  [3:0]  io_in_13_bits_opcode,
+  input  [2:0]  io_in_13_bits_param,
+  input  [2:0]  io_in_13_bits_size,
+  input  [6:0]  io_in_13_bits_sourceId,
+  input         io_in_13_bits_denied,
+  input         io_in_13_bits_corrupt,
+  input         io_in_13_bits_aliasTask,
+  input         io_in_13_bits_useProbeData,
+  input         io_in_13_bits_mshrRetry,
+  input         io_in_13_bits_readProbeDataDown,
+  input         io_in_13_bits_fromL2pft,
+  input         io_in_13_bits_dirty,
+  input  [2:0]  io_in_13_bits_way,
+  input         io_in_13_bits_meta_dirty,
+  input  [1:0]  io_in_13_bits_meta_state,
+  input         io_in_13_bits_meta_clients,
+  input         io_in_13_bits_meta_alias,
+  input         io_in_13_bits_meta_prefetch,
+  input  [3:0]  io_in_13_bits_meta_prefetchSrc,
+  input         io_in_13_bits_meta_accessed,
+  input         io_in_13_bits_meta_tagErr,
+  input         io_in_13_bits_meta_dataErr,
+  input         io_in_13_bits_metaWen,
+  input         io_in_13_bits_tagWen,
+  input         io_in_13_bits_dsWen,
+  input         io_in_13_bits_replTask,
+  input         io_in_13_bits_cmoTask,
+  input  [4:0]  io_in_13_bits_reqSource,
+  input         io_in_13_bits_mergeA,
+  input  [5:0]  io_in_13_bits_aMergeTask_off,
+  input         io_in_13_bits_aMergeTask_alias,
+  input  [43:0] io_in_13_bits_aMergeTask_vaddr,
+  input         io_in_13_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_13_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_13_bits_aMergeTask_param,
+  input  [6:0]  io_in_13_bits_aMergeTask_sourceId,
+  input         io_in_13_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_13_bits_aMergeTask_meta_state,
+  input         io_in_13_bits_aMergeTask_meta_clients,
+  input         io_in_13_bits_aMergeTask_meta_alias,
+  input         io_in_13_bits_aMergeTask_meta_accessed,
+  input         io_in_13_bits_snpHitRelease,
+  input         io_in_13_bits_snpHitReleaseToInval,
+  input         io_in_13_bits_snpHitReleaseToClean,
+  input         io_in_13_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_13_bits_snpHitReleaseIdx,
+  input         io_in_13_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_13_bits_snpHitReleaseMeta_state,
+  input         io_in_13_bits_snpHitReleaseMeta_clients,
+  input         io_in_13_bits_snpHitReleaseMeta_alias,
+  input         io_in_13_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_13_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_13_bits_snpHitReleaseMeta_accessed,
+  input         io_in_13_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_13_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_13_bits_tgtID,
+  input  [11:0] io_in_13_bits_txnID,
+  input  [10:0] io_in_13_bits_homeNID,
+  input  [11:0] io_in_13_bits_dbID,
+  input  [6:0]  io_in_13_bits_chiOpcode,
+  input  [2:0]  io_in_13_bits_resp,
+  input  [2:0]  io_in_13_bits_fwdState,
+  input         io_in_13_bits_retToSrc,
+  input         io_in_13_bits_likelyshared,
+  input         io_in_13_bits_expCompAck,
+  input         io_in_13_bits_allowRetry,
+  input         io_in_13_bits_memAttr_allocate,
+  input         io_in_13_bits_memAttr_cacheable,
+  input         io_in_13_bits_memAttr_ewa,
+  input         io_in_13_bits_traceTag,
+  output        io_in_14_ready,
+  input         io_in_14_valid,
+  input  [2:0]  io_in_14_bits_channel,
+  input  [2:0]  io_in_14_bits_txChannel,
+  input  [7:0]  io_in_14_bits_set,
+  input  [33:0] io_in_14_bits_tag,
+  input  [5:0]  io_in_14_bits_off,
+  input         io_in_14_bits_alias,
+  input         io_in_14_bits_isKeyword,
+  input  [3:0]  io_in_14_bits_opcode,
+  input  [2:0]  io_in_14_bits_param,
+  input  [2:0]  io_in_14_bits_size,
+  input  [6:0]  io_in_14_bits_sourceId,
+  input         io_in_14_bits_denied,
+  input         io_in_14_bits_corrupt,
+  input         io_in_14_bits_aliasTask,
+  input         io_in_14_bits_useProbeData,
+  input         io_in_14_bits_mshrRetry,
+  input         io_in_14_bits_readProbeDataDown,
+  input         io_in_14_bits_fromL2pft,
+  input         io_in_14_bits_dirty,
+  input  [2:0]  io_in_14_bits_way,
+  input         io_in_14_bits_meta_dirty,
+  input  [1:0]  io_in_14_bits_meta_state,
+  input         io_in_14_bits_meta_clients,
+  input         io_in_14_bits_meta_alias,
+  input         io_in_14_bits_meta_prefetch,
+  input  [3:0]  io_in_14_bits_meta_prefetchSrc,
+  input         io_in_14_bits_meta_accessed,
+  input         io_in_14_bits_meta_tagErr,
+  input         io_in_14_bits_meta_dataErr,
+  input         io_in_14_bits_metaWen,
+  input         io_in_14_bits_tagWen,
+  input         io_in_14_bits_dsWen,
+  input         io_in_14_bits_replTask,
+  input         io_in_14_bits_cmoTask,
+  input  [4:0]  io_in_14_bits_reqSource,
+  input         io_in_14_bits_mergeA,
+  input  [5:0]  io_in_14_bits_aMergeTask_off,
+  input         io_in_14_bits_aMergeTask_alias,
+  input  [43:0] io_in_14_bits_aMergeTask_vaddr,
+  input         io_in_14_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_14_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_14_bits_aMergeTask_param,
+  input  [6:0]  io_in_14_bits_aMergeTask_sourceId,
+  input         io_in_14_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_14_bits_aMergeTask_meta_state,
+  input         io_in_14_bits_aMergeTask_meta_clients,
+  input         io_in_14_bits_aMergeTask_meta_alias,
+  input         io_in_14_bits_aMergeTask_meta_accessed,
+  input         io_in_14_bits_snpHitRelease,
+  input         io_in_14_bits_snpHitReleaseToInval,
+  input         io_in_14_bits_snpHitReleaseToClean,
+  input         io_in_14_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_14_bits_snpHitReleaseIdx,
+  input         io_in_14_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_14_bits_snpHitReleaseMeta_state,
+  input         io_in_14_bits_snpHitReleaseMeta_clients,
+  input         io_in_14_bits_snpHitReleaseMeta_alias,
+  input         io_in_14_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_14_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_14_bits_snpHitReleaseMeta_accessed,
+  input         io_in_14_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_14_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_14_bits_tgtID,
+  input  [11:0] io_in_14_bits_txnID,
+  input  [10:0] io_in_14_bits_homeNID,
+  input  [11:0] io_in_14_bits_dbID,
+  input  [6:0]  io_in_14_bits_chiOpcode,
+  input  [2:0]  io_in_14_bits_resp,
+  input  [2:0]  io_in_14_bits_fwdState,
+  input         io_in_14_bits_retToSrc,
+  input         io_in_14_bits_likelyshared,
+  input         io_in_14_bits_expCompAck,
+  input         io_in_14_bits_allowRetry,
+  input         io_in_14_bits_memAttr_allocate,
+  input         io_in_14_bits_memAttr_cacheable,
+  input         io_in_14_bits_memAttr_ewa,
+  input         io_in_14_bits_traceTag,
+  output        io_in_15_ready,
+  input         io_in_15_valid,
+  input  [2:0]  io_in_15_bits_channel,
+  input  [2:0]  io_in_15_bits_txChannel,
+  input  [7:0]  io_in_15_bits_set,
+  input  [33:0] io_in_15_bits_tag,
+  input  [5:0]  io_in_15_bits_off,
+  input         io_in_15_bits_alias,
+  input         io_in_15_bits_isKeyword,
+  input  [3:0]  io_in_15_bits_opcode,
+  input  [2:0]  io_in_15_bits_param,
+  input  [2:0]  io_in_15_bits_size,
+  input  [6:0]  io_in_15_bits_sourceId,
+  input         io_in_15_bits_denied,
+  input         io_in_15_bits_corrupt,
+  input         io_in_15_bits_aliasTask,
+  input         io_in_15_bits_useProbeData,
+  input         io_in_15_bits_mshrRetry,
+  input         io_in_15_bits_readProbeDataDown,
+  input         io_in_15_bits_fromL2pft,
+  input         io_in_15_bits_dirty,
+  input  [2:0]  io_in_15_bits_way,
+  input         io_in_15_bits_meta_dirty,
+  input  [1:0]  io_in_15_bits_meta_state,
+  input         io_in_15_bits_meta_clients,
+  input         io_in_15_bits_meta_alias,
+  input         io_in_15_bits_meta_prefetch,
+  input  [3:0]  io_in_15_bits_meta_prefetchSrc,
+  input         io_in_15_bits_meta_accessed,
+  input         io_in_15_bits_meta_tagErr,
+  input         io_in_15_bits_meta_dataErr,
+  input         io_in_15_bits_metaWen,
+  input         io_in_15_bits_tagWen,
+  input         io_in_15_bits_dsWen,
+  input         io_in_15_bits_replTask,
+  input         io_in_15_bits_cmoTask,
+  input  [4:0]  io_in_15_bits_reqSource,
+  input         io_in_15_bits_mergeA,
+  input  [5:0]  io_in_15_bits_aMergeTask_off,
+  input         io_in_15_bits_aMergeTask_alias,
+  input  [43:0] io_in_15_bits_aMergeTask_vaddr,
+  input         io_in_15_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_15_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_15_bits_aMergeTask_param,
+  input  [6:0]  io_in_15_bits_aMergeTask_sourceId,
+  input         io_in_15_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_15_bits_aMergeTask_meta_state,
+  input         io_in_15_bits_aMergeTask_meta_clients,
+  input         io_in_15_bits_aMergeTask_meta_alias,
+  input         io_in_15_bits_aMergeTask_meta_accessed,
+  input         io_in_15_bits_snpHitRelease,
+  input         io_in_15_bits_snpHitReleaseToInval,
+  input         io_in_15_bits_snpHitReleaseToClean,
+  input         io_in_15_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_15_bits_snpHitReleaseIdx,
+  input         io_in_15_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_15_bits_snpHitReleaseMeta_state,
+  input         io_in_15_bits_snpHitReleaseMeta_clients,
+  input         io_in_15_bits_snpHitReleaseMeta_alias,
+  input         io_in_15_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_15_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_15_bits_snpHitReleaseMeta_accessed,
+  input         io_in_15_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_15_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_15_bits_tgtID,
+  input  [11:0] io_in_15_bits_txnID,
+  input  [10:0] io_in_15_bits_homeNID,
+  input  [11:0] io_in_15_bits_dbID,
+  input  [6:0]  io_in_15_bits_chiOpcode,
+  input  [2:0]  io_in_15_bits_resp,
+  input  [2:0]  io_in_15_bits_fwdState,
+  input         io_in_15_bits_retToSrc,
+  input         io_in_15_bits_likelyshared,
+  input         io_in_15_bits_expCompAck,
+  input         io_in_15_bits_allowRetry,
+  input         io_in_15_bits_memAttr_allocate,
+  input         io_in_15_bits_memAttr_cacheable,
+  input         io_in_15_bits_memAttr_ewa,
+  input         io_in_15_bits_traceTag,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [2:0]  io_out_bits_channel,
+  output [2:0]  io_out_bits_txChannel,
+  output [7:0]  io_out_bits_set,
+  output [33:0] io_out_bits_tag,
+  output [5:0]  io_out_bits_off,
+  output        io_out_bits_alias,
+  output        io_out_bits_isKeyword,
+  output [3:0]  io_out_bits_opcode,
+  output [2:0]  io_out_bits_param,
+  output [2:0]  io_out_bits_size,
+  output [6:0]  io_out_bits_sourceId,
+  output        io_out_bits_denied,
+  output        io_out_bits_corrupt,
+  output        io_out_bits_mshrTask,
+  output        io_out_bits_aliasTask,
+  output        io_out_bits_useProbeData,
+  output        io_out_bits_mshrRetry,
+  output        io_out_bits_readProbeDataDown,
+  output        io_out_bits_fromL2pft,
+  output        io_out_bits_dirty,
+  output [2:0]  io_out_bits_way,
+  output        io_out_bits_meta_dirty,
+  output [1:0]  io_out_bits_meta_state,
+  output        io_out_bits_meta_clients,
+  output        io_out_bits_meta_alias,
+  output        io_out_bits_meta_prefetch,
+  output [3:0]  io_out_bits_meta_prefetchSrc,
+  output        io_out_bits_meta_accessed,
+  output        io_out_bits_meta_tagErr,
+  output        io_out_bits_meta_dataErr,
+  output        io_out_bits_metaWen,
+  output        io_out_bits_tagWen,
+  output        io_out_bits_dsWen,
+  output        io_out_bits_replTask,
+  output        io_out_bits_cmoTask,
+  output [4:0]  io_out_bits_reqSource,
+  output        io_out_bits_mergeA,
+  output [5:0]  io_out_bits_aMergeTask_off,
+  output        io_out_bits_aMergeTask_alias,
+  output [43:0] io_out_bits_aMergeTask_vaddr,
+  output        io_out_bits_aMergeTask_isKeyword,
+  output [2:0]  io_out_bits_aMergeTask_opcode,
+  output [2:0]  io_out_bits_aMergeTask_param,
+  output [6:0]  io_out_bits_aMergeTask_sourceId,
+  output        io_out_bits_aMergeTask_meta_dirty,
+  output [1:0]  io_out_bits_aMergeTask_meta_state,
+  output        io_out_bits_aMergeTask_meta_clients,
+  output        io_out_bits_aMergeTask_meta_alias,
+  output        io_out_bits_aMergeTask_meta_accessed,
+  output        io_out_bits_snpHitRelease,
+  output        io_out_bits_snpHitReleaseToInval,
+  output        io_out_bits_snpHitReleaseToClean,
+  output        io_out_bits_snpHitReleaseWithData,
+  output [7:0]  io_out_bits_snpHitReleaseIdx,
+  output        io_out_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_out_bits_snpHitReleaseMeta_state,
+  output        io_out_bits_snpHitReleaseMeta_clients,
+  output        io_out_bits_snpHitReleaseMeta_alias,
+  output        io_out_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_out_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_out_bits_snpHitReleaseMeta_accessed,
+  output        io_out_bits_snpHitReleaseMeta_tagErr,
+  output        io_out_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_out_bits_tgtID,
+  output [11:0] io_out_bits_txnID,
+  output [10:0] io_out_bits_homeNID,
+  output [11:0] io_out_bits_dbID,
+  output [6:0]  io_out_bits_chiOpcode,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output        io_out_bits_retToSrc,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_expCompAck,
+  output        io_out_bits_allowRetry,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_traceTag,
+  output [3:0]  io_chosen
+);
+
+  wire        _highArb_io_out_valid;
+  wire [2:0]  _highArb_io_out_bits_channel;
+  wire [2:0]  _highArb_io_out_bits_txChannel;
+  wire [7:0]  _highArb_io_out_bits_set;
+  wire [33:0] _highArb_io_out_bits_tag;
+  wire [5:0]  _highArb_io_out_bits_off;
+  wire        _highArb_io_out_bits_alias;
+  wire        _highArb_io_out_bits_isKeyword;
+  wire [3:0]  _highArb_io_out_bits_opcode;
+  wire [2:0]  _highArb_io_out_bits_param;
+  wire [2:0]  _highArb_io_out_bits_size;
+  wire [6:0]  _highArb_io_out_bits_sourceId;
+  wire        _highArb_io_out_bits_denied;
+  wire        _highArb_io_out_bits_corrupt;
+  wire        _highArb_io_out_bits_mshrTask;
+  wire        _highArb_io_out_bits_aliasTask;
+  wire        _highArb_io_out_bits_useProbeData;
+  wire        _highArb_io_out_bits_mshrRetry;
+  wire        _highArb_io_out_bits_readProbeDataDown;
+  wire        _highArb_io_out_bits_fromL2pft;
+  wire        _highArb_io_out_bits_dirty;
+  wire [2:0]  _highArb_io_out_bits_way;
+  wire        _highArb_io_out_bits_meta_dirty;
+  wire [1:0]  _highArb_io_out_bits_meta_state;
+  wire        _highArb_io_out_bits_meta_clients;
+  wire        _highArb_io_out_bits_meta_alias;
+  wire        _highArb_io_out_bits_meta_prefetch;
+  wire [3:0]  _highArb_io_out_bits_meta_prefetchSrc;
+  wire        _highArb_io_out_bits_meta_accessed;
+  wire        _highArb_io_out_bits_meta_tagErr;
+  wire        _highArb_io_out_bits_meta_dataErr;
+  wire        _highArb_io_out_bits_metaWen;
+  wire        _highArb_io_out_bits_tagWen;
+  wire        _highArb_io_out_bits_dsWen;
+  wire        _highArb_io_out_bits_replTask;
+  wire        _highArb_io_out_bits_cmoTask;
+  wire [4:0]  _highArb_io_out_bits_reqSource;
+  wire        _highArb_io_out_bits_mergeA;
+  wire [5:0]  _highArb_io_out_bits_aMergeTask_off;
+  wire        _highArb_io_out_bits_aMergeTask_alias;
+  wire [43:0] _highArb_io_out_bits_aMergeTask_vaddr;
+  wire        _highArb_io_out_bits_aMergeTask_isKeyword;
+  wire [2:0]  _highArb_io_out_bits_aMergeTask_opcode;
+  wire [2:0]  _highArb_io_out_bits_aMergeTask_param;
+  wire [6:0]  _highArb_io_out_bits_aMergeTask_sourceId;
+  wire        _highArb_io_out_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _highArb_io_out_bits_aMergeTask_meta_state;
+  wire        _highArb_io_out_bits_aMergeTask_meta_clients;
+  wire        _highArb_io_out_bits_aMergeTask_meta_alias;
+  wire        _highArb_io_out_bits_aMergeTask_meta_accessed;
+  wire        _highArb_io_out_bits_snpHitRelease;
+  wire        _highArb_io_out_bits_snpHitReleaseToInval;
+  wire        _highArb_io_out_bits_snpHitReleaseToClean;
+  wire        _highArb_io_out_bits_snpHitReleaseWithData;
+  wire [7:0]  _highArb_io_out_bits_snpHitReleaseIdx;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _highArb_io_out_bits_snpHitReleaseMeta_state;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_clients;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_alias;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _highArb_io_out_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_accessed;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_tagErr;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _highArb_io_out_bits_tgtID;
+  wire [11:0] _highArb_io_out_bits_txnID;
+  wire [10:0] _highArb_io_out_bits_homeNID;
+  wire [11:0] _highArb_io_out_bits_dbID;
+  wire [6:0]  _highArb_io_out_bits_chiOpcode;
+  wire [2:0]  _highArb_io_out_bits_resp;
+  wire [2:0]  _highArb_io_out_bits_fwdState;
+  wire        _highArb_io_out_bits_retToSrc;
+  wire        _highArb_io_out_bits_likelyshared;
+  wire        _highArb_io_out_bits_expCompAck;
+  wire        _highArb_io_out_bits_allowRetry;
+  wire        _highArb_io_out_bits_memAttr_allocate;
+  wire        _highArb_io_out_bits_memAttr_cacheable;
+  wire        _highArb_io_out_bits_memAttr_ewa;
+  wire        _highArb_io_out_bits_traceTag;
+  wire [7:0]  _highArb_io_chosenOH;
+  wire        _lowArb_io_out_valid;
+  wire [2:0]  _lowArb_io_out_bits_channel;
+  wire [2:0]  _lowArb_io_out_bits_txChannel;
+  wire [7:0]  _lowArb_io_out_bits_set;
+  wire [33:0] _lowArb_io_out_bits_tag;
+  wire [5:0]  _lowArb_io_out_bits_off;
+  wire        _lowArb_io_out_bits_alias;
+  wire        _lowArb_io_out_bits_isKeyword;
+  wire [3:0]  _lowArb_io_out_bits_opcode;
+  wire [2:0]  _lowArb_io_out_bits_param;
+  wire [2:0]  _lowArb_io_out_bits_size;
+  wire [6:0]  _lowArb_io_out_bits_sourceId;
+  wire        _lowArb_io_out_bits_denied;
+  wire        _lowArb_io_out_bits_corrupt;
+  wire        _lowArb_io_out_bits_mshrTask;
+  wire        _lowArb_io_out_bits_aliasTask;
+  wire        _lowArb_io_out_bits_useProbeData;
+  wire        _lowArb_io_out_bits_mshrRetry;
+  wire        _lowArb_io_out_bits_readProbeDataDown;
+  wire        _lowArb_io_out_bits_fromL2pft;
+  wire        _lowArb_io_out_bits_dirty;
+  wire [2:0]  _lowArb_io_out_bits_way;
+  wire        _lowArb_io_out_bits_meta_dirty;
+  wire [1:0]  _lowArb_io_out_bits_meta_state;
+  wire        _lowArb_io_out_bits_meta_clients;
+  wire        _lowArb_io_out_bits_meta_alias;
+  wire        _lowArb_io_out_bits_meta_prefetch;
+  wire [3:0]  _lowArb_io_out_bits_meta_prefetchSrc;
+  wire        _lowArb_io_out_bits_meta_accessed;
+  wire        _lowArb_io_out_bits_meta_tagErr;
+  wire        _lowArb_io_out_bits_meta_dataErr;
+  wire        _lowArb_io_out_bits_metaWen;
+  wire        _lowArb_io_out_bits_tagWen;
+  wire        _lowArb_io_out_bits_dsWen;
+  wire        _lowArb_io_out_bits_replTask;
+  wire        _lowArb_io_out_bits_cmoTask;
+  wire [4:0]  _lowArb_io_out_bits_reqSource;
+  wire        _lowArb_io_out_bits_mergeA;
+  wire [5:0]  _lowArb_io_out_bits_aMergeTask_off;
+  wire        _lowArb_io_out_bits_aMergeTask_alias;
+  wire [43:0] _lowArb_io_out_bits_aMergeTask_vaddr;
+  wire        _lowArb_io_out_bits_aMergeTask_isKeyword;
+  wire [2:0]  _lowArb_io_out_bits_aMergeTask_opcode;
+  wire [2:0]  _lowArb_io_out_bits_aMergeTask_param;
+  wire [6:0]  _lowArb_io_out_bits_aMergeTask_sourceId;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _lowArb_io_out_bits_aMergeTask_meta_state;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_clients;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_alias;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_accessed;
+  wire        _lowArb_io_out_bits_snpHitRelease;
+  wire        _lowArb_io_out_bits_snpHitReleaseToInval;
+  wire        _lowArb_io_out_bits_snpHitReleaseToClean;
+  wire        _lowArb_io_out_bits_snpHitReleaseWithData;
+  wire [7:0]  _lowArb_io_out_bits_snpHitReleaseIdx;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _lowArb_io_out_bits_snpHitReleaseMeta_state;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_clients;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_alias;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _lowArb_io_out_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_accessed;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_tagErr;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _lowArb_io_out_bits_tgtID;
+  wire [11:0] _lowArb_io_out_bits_txnID;
+  wire [10:0] _lowArb_io_out_bits_homeNID;
+  wire [11:0] _lowArb_io_out_bits_dbID;
+  wire [6:0]  _lowArb_io_out_bits_chiOpcode;
+  wire [2:0]  _lowArb_io_out_bits_resp;
+  wire [2:0]  _lowArb_io_out_bits_fwdState;
+  wire        _lowArb_io_out_bits_retToSrc;
+  wire        _lowArb_io_out_bits_likelyshared;
+  wire        _lowArb_io_out_bits_expCompAck;
+  wire        _lowArb_io_out_bits_allowRetry;
+  wire        _lowArb_io_out_bits_memAttr_allocate;
+  wire        _lowArb_io_out_bits_memAttr_cacheable;
+  wire        _lowArb_io_out_bits_memAttr_ewa;
+  wire        _lowArb_io_out_bits_traceTag;
+  wire [7:0]  _lowArb_io_chosenOH;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  wire [7:0]  _io_chosenOH_T_2 = {8{~finalSelLow}} & _highArb_io_chosenOH;
+  wire [6:0]  _io_chosen_T_1 =
+    _io_chosenOH_T_2[7:1] | {7{finalSelLow}} & _lowArb_io_chosenOH[7:1];
+  wire [2:0]  _io_chosen_T_3 = _io_chosen_T_1[6:4] | _io_chosen_T_1[2:0];
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_ready & io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_22 lowArb (
+    .clock                                      (clock),
+    .reset                                      (reset),
+    .io_in_0_ready                              (io_in_0_ready),
+    .io_in_0_valid                              (io_in_0_valid),
+    .io_in_0_bits_channel                       (io_in_0_bits_channel),
+    .io_in_0_bits_txChannel                     (io_in_0_bits_txChannel),
+    .io_in_0_bits_set                           (io_in_0_bits_set),
+    .io_in_0_bits_tag                           (io_in_0_bits_tag),
+    .io_in_0_bits_off                           (io_in_0_bits_off),
+    .io_in_0_bits_alias                         (io_in_0_bits_alias),
+    .io_in_0_bits_isKeyword                     (io_in_0_bits_isKeyword),
+    .io_in_0_bits_opcode                        (io_in_0_bits_opcode),
+    .io_in_0_bits_param                         (io_in_0_bits_param),
+    .io_in_0_bits_size                          (io_in_0_bits_size),
+    .io_in_0_bits_sourceId                      (io_in_0_bits_sourceId),
+    .io_in_0_bits_denied                        (io_in_0_bits_denied),
+    .io_in_0_bits_corrupt                       (io_in_0_bits_corrupt),
+    .io_in_0_bits_aliasTask                     (io_in_0_bits_aliasTask),
+    .io_in_0_bits_useProbeData                  (io_in_0_bits_useProbeData),
+    .io_in_0_bits_mshrRetry                     (io_in_0_bits_mshrRetry),
+    .io_in_0_bits_readProbeDataDown             (io_in_0_bits_readProbeDataDown),
+    .io_in_0_bits_fromL2pft                     (io_in_0_bits_fromL2pft),
+    .io_in_0_bits_dirty                         (io_in_0_bits_dirty),
+    .io_in_0_bits_way                           (io_in_0_bits_way),
+    .io_in_0_bits_meta_dirty                    (io_in_0_bits_meta_dirty),
+    .io_in_0_bits_meta_state                    (io_in_0_bits_meta_state),
+    .io_in_0_bits_meta_clients                  (io_in_0_bits_meta_clients),
+    .io_in_0_bits_meta_alias                    (io_in_0_bits_meta_alias),
+    .io_in_0_bits_meta_prefetch                 (io_in_0_bits_meta_prefetch),
+    .io_in_0_bits_meta_prefetchSrc              (io_in_0_bits_meta_prefetchSrc),
+    .io_in_0_bits_meta_accessed                 (io_in_0_bits_meta_accessed),
+    .io_in_0_bits_meta_tagErr                   (io_in_0_bits_meta_tagErr),
+    .io_in_0_bits_meta_dataErr                  (io_in_0_bits_meta_dataErr),
+    .io_in_0_bits_metaWen                       (io_in_0_bits_metaWen),
+    .io_in_0_bits_tagWen                        (io_in_0_bits_tagWen),
+    .io_in_0_bits_dsWen                         (io_in_0_bits_dsWen),
+    .io_in_0_bits_replTask                      (io_in_0_bits_replTask),
+    .io_in_0_bits_cmoTask                       (io_in_0_bits_cmoTask),
+    .io_in_0_bits_reqSource                     (io_in_0_bits_reqSource),
+    .io_in_0_bits_mergeA                        (io_in_0_bits_mergeA),
+    .io_in_0_bits_aMergeTask_off                (io_in_0_bits_aMergeTask_off),
+    .io_in_0_bits_aMergeTask_alias              (io_in_0_bits_aMergeTask_alias),
+    .io_in_0_bits_aMergeTask_vaddr              (io_in_0_bits_aMergeTask_vaddr),
+    .io_in_0_bits_aMergeTask_isKeyword          (io_in_0_bits_aMergeTask_isKeyword),
+    .io_in_0_bits_aMergeTask_opcode             (io_in_0_bits_aMergeTask_opcode),
+    .io_in_0_bits_aMergeTask_param              (io_in_0_bits_aMergeTask_param),
+    .io_in_0_bits_aMergeTask_sourceId           (io_in_0_bits_aMergeTask_sourceId),
+    .io_in_0_bits_aMergeTask_meta_dirty         (io_in_0_bits_aMergeTask_meta_dirty),
+    .io_in_0_bits_aMergeTask_meta_state         (io_in_0_bits_aMergeTask_meta_state),
+    .io_in_0_bits_aMergeTask_meta_clients       (io_in_0_bits_aMergeTask_meta_clients),
+    .io_in_0_bits_aMergeTask_meta_alias         (io_in_0_bits_aMergeTask_meta_alias),
+    .io_in_0_bits_aMergeTask_meta_accessed      (io_in_0_bits_aMergeTask_meta_accessed),
+    .io_in_0_bits_snpHitRelease                 (io_in_0_bits_snpHitRelease),
+    .io_in_0_bits_snpHitReleaseToInval          (io_in_0_bits_snpHitReleaseToInval),
+    .io_in_0_bits_snpHitReleaseToClean          (io_in_0_bits_snpHitReleaseToClean),
+    .io_in_0_bits_snpHitReleaseWithData         (io_in_0_bits_snpHitReleaseWithData),
+    .io_in_0_bits_snpHitReleaseIdx              (io_in_0_bits_snpHitReleaseIdx),
+    .io_in_0_bits_snpHitReleaseMeta_dirty       (io_in_0_bits_snpHitReleaseMeta_dirty),
+    .io_in_0_bits_snpHitReleaseMeta_state       (io_in_0_bits_snpHitReleaseMeta_state),
+    .io_in_0_bits_snpHitReleaseMeta_clients     (io_in_0_bits_snpHitReleaseMeta_clients),
+    .io_in_0_bits_snpHitReleaseMeta_alias       (io_in_0_bits_snpHitReleaseMeta_alias),
+    .io_in_0_bits_snpHitReleaseMeta_prefetch    (io_in_0_bits_snpHitReleaseMeta_prefetch),
+    .io_in_0_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_0_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_0_bits_snpHitReleaseMeta_accessed    (io_in_0_bits_snpHitReleaseMeta_accessed),
+    .io_in_0_bits_snpHitReleaseMeta_tagErr      (io_in_0_bits_snpHitReleaseMeta_tagErr),
+    .io_in_0_bits_snpHitReleaseMeta_dataErr     (io_in_0_bits_snpHitReleaseMeta_dataErr),
+    .io_in_0_bits_tgtID                         (io_in_0_bits_tgtID),
+    .io_in_0_bits_txnID                         (io_in_0_bits_txnID),
+    .io_in_0_bits_homeNID                       (io_in_0_bits_homeNID),
+    .io_in_0_bits_dbID                          (io_in_0_bits_dbID),
+    .io_in_0_bits_chiOpcode                     (io_in_0_bits_chiOpcode),
+    .io_in_0_bits_resp                          (io_in_0_bits_resp),
+    .io_in_0_bits_fwdState                      (io_in_0_bits_fwdState),
+    .io_in_0_bits_retToSrc                      (io_in_0_bits_retToSrc),
+    .io_in_0_bits_likelyshared                  (io_in_0_bits_likelyshared),
+    .io_in_0_bits_expCompAck                    (io_in_0_bits_expCompAck),
+    .io_in_0_bits_allowRetry                    (io_in_0_bits_allowRetry),
+    .io_in_0_bits_memAttr_allocate              (io_in_0_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable             (io_in_0_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_ewa                   (io_in_0_bits_memAttr_ewa),
+    .io_in_0_bits_traceTag                      (io_in_0_bits_traceTag),
+    .io_in_1_ready                              (io_in_1_ready),
+    .io_in_1_valid                              (io_in_1_valid),
+    .io_in_1_bits_channel                       (io_in_1_bits_channel),
+    .io_in_1_bits_txChannel                     (io_in_1_bits_txChannel),
+    .io_in_1_bits_set                           (io_in_1_bits_set),
+    .io_in_1_bits_tag                           (io_in_1_bits_tag),
+    .io_in_1_bits_off                           (io_in_1_bits_off),
+    .io_in_1_bits_alias                         (io_in_1_bits_alias),
+    .io_in_1_bits_isKeyword                     (io_in_1_bits_isKeyword),
+    .io_in_1_bits_opcode                        (io_in_1_bits_opcode),
+    .io_in_1_bits_param                         (io_in_1_bits_param),
+    .io_in_1_bits_size                          (io_in_1_bits_size),
+    .io_in_1_bits_sourceId                      (io_in_1_bits_sourceId),
+    .io_in_1_bits_denied                        (io_in_1_bits_denied),
+    .io_in_1_bits_corrupt                       (io_in_1_bits_corrupt),
+    .io_in_1_bits_aliasTask                     (io_in_1_bits_aliasTask),
+    .io_in_1_bits_useProbeData                  (io_in_1_bits_useProbeData),
+    .io_in_1_bits_mshrRetry                     (io_in_1_bits_mshrRetry),
+    .io_in_1_bits_readProbeDataDown             (io_in_1_bits_readProbeDataDown),
+    .io_in_1_bits_fromL2pft                     (io_in_1_bits_fromL2pft),
+    .io_in_1_bits_dirty                         (io_in_1_bits_dirty),
+    .io_in_1_bits_way                           (io_in_1_bits_way),
+    .io_in_1_bits_meta_dirty                    (io_in_1_bits_meta_dirty),
+    .io_in_1_bits_meta_state                    (io_in_1_bits_meta_state),
+    .io_in_1_bits_meta_clients                  (io_in_1_bits_meta_clients),
+    .io_in_1_bits_meta_alias                    (io_in_1_bits_meta_alias),
+    .io_in_1_bits_meta_prefetch                 (io_in_1_bits_meta_prefetch),
+    .io_in_1_bits_meta_prefetchSrc              (io_in_1_bits_meta_prefetchSrc),
+    .io_in_1_bits_meta_accessed                 (io_in_1_bits_meta_accessed),
+    .io_in_1_bits_meta_tagErr                   (io_in_1_bits_meta_tagErr),
+    .io_in_1_bits_meta_dataErr                  (io_in_1_bits_meta_dataErr),
+    .io_in_1_bits_metaWen                       (io_in_1_bits_metaWen),
+    .io_in_1_bits_tagWen                        (io_in_1_bits_tagWen),
+    .io_in_1_bits_dsWen                         (io_in_1_bits_dsWen),
+    .io_in_1_bits_replTask                      (io_in_1_bits_replTask),
+    .io_in_1_bits_cmoTask                       (io_in_1_bits_cmoTask),
+    .io_in_1_bits_reqSource                     (io_in_1_bits_reqSource),
+    .io_in_1_bits_mergeA                        (io_in_1_bits_mergeA),
+    .io_in_1_bits_aMergeTask_off                (io_in_1_bits_aMergeTask_off),
+    .io_in_1_bits_aMergeTask_alias              (io_in_1_bits_aMergeTask_alias),
+    .io_in_1_bits_aMergeTask_vaddr              (io_in_1_bits_aMergeTask_vaddr),
+    .io_in_1_bits_aMergeTask_isKeyword          (io_in_1_bits_aMergeTask_isKeyword),
+    .io_in_1_bits_aMergeTask_opcode             (io_in_1_bits_aMergeTask_opcode),
+    .io_in_1_bits_aMergeTask_param              (io_in_1_bits_aMergeTask_param),
+    .io_in_1_bits_aMergeTask_sourceId           (io_in_1_bits_aMergeTask_sourceId),
+    .io_in_1_bits_aMergeTask_meta_dirty         (io_in_1_bits_aMergeTask_meta_dirty),
+    .io_in_1_bits_aMergeTask_meta_state         (io_in_1_bits_aMergeTask_meta_state),
+    .io_in_1_bits_aMergeTask_meta_clients       (io_in_1_bits_aMergeTask_meta_clients),
+    .io_in_1_bits_aMergeTask_meta_alias         (io_in_1_bits_aMergeTask_meta_alias),
+    .io_in_1_bits_aMergeTask_meta_accessed      (io_in_1_bits_aMergeTask_meta_accessed),
+    .io_in_1_bits_snpHitRelease                 (io_in_1_bits_snpHitRelease),
+    .io_in_1_bits_snpHitReleaseToInval          (io_in_1_bits_snpHitReleaseToInval),
+    .io_in_1_bits_snpHitReleaseToClean          (io_in_1_bits_snpHitReleaseToClean),
+    .io_in_1_bits_snpHitReleaseWithData         (io_in_1_bits_snpHitReleaseWithData),
+    .io_in_1_bits_snpHitReleaseIdx              (io_in_1_bits_snpHitReleaseIdx),
+    .io_in_1_bits_snpHitReleaseMeta_dirty       (io_in_1_bits_snpHitReleaseMeta_dirty),
+    .io_in_1_bits_snpHitReleaseMeta_state       (io_in_1_bits_snpHitReleaseMeta_state),
+    .io_in_1_bits_snpHitReleaseMeta_clients     (io_in_1_bits_snpHitReleaseMeta_clients),
+    .io_in_1_bits_snpHitReleaseMeta_alias       (io_in_1_bits_snpHitReleaseMeta_alias),
+    .io_in_1_bits_snpHitReleaseMeta_prefetch    (io_in_1_bits_snpHitReleaseMeta_prefetch),
+    .io_in_1_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_1_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_1_bits_snpHitReleaseMeta_accessed    (io_in_1_bits_snpHitReleaseMeta_accessed),
+    .io_in_1_bits_snpHitReleaseMeta_tagErr      (io_in_1_bits_snpHitReleaseMeta_tagErr),
+    .io_in_1_bits_snpHitReleaseMeta_dataErr     (io_in_1_bits_snpHitReleaseMeta_dataErr),
+    .io_in_1_bits_tgtID                         (io_in_1_bits_tgtID),
+    .io_in_1_bits_txnID                         (io_in_1_bits_txnID),
+    .io_in_1_bits_homeNID                       (io_in_1_bits_homeNID),
+    .io_in_1_bits_dbID                          (io_in_1_bits_dbID),
+    .io_in_1_bits_chiOpcode                     (io_in_1_bits_chiOpcode),
+    .io_in_1_bits_resp                          (io_in_1_bits_resp),
+    .io_in_1_bits_fwdState                      (io_in_1_bits_fwdState),
+    .io_in_1_bits_retToSrc                      (io_in_1_bits_retToSrc),
+    .io_in_1_bits_likelyshared                  (io_in_1_bits_likelyshared),
+    .io_in_1_bits_expCompAck                    (io_in_1_bits_expCompAck),
+    .io_in_1_bits_allowRetry                    (io_in_1_bits_allowRetry),
+    .io_in_1_bits_memAttr_allocate              (io_in_1_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable             (io_in_1_bits_memAttr_cacheable),
+    .io_in_1_bits_memAttr_ewa                   (io_in_1_bits_memAttr_ewa),
+    .io_in_1_bits_traceTag                      (io_in_1_bits_traceTag),
+    .io_in_2_ready                              (io_in_2_ready),
+    .io_in_2_valid                              (io_in_2_valid),
+    .io_in_2_bits_channel                       (io_in_2_bits_channel),
+    .io_in_2_bits_txChannel                     (io_in_2_bits_txChannel),
+    .io_in_2_bits_set                           (io_in_2_bits_set),
+    .io_in_2_bits_tag                           (io_in_2_bits_tag),
+    .io_in_2_bits_off                           (io_in_2_bits_off),
+    .io_in_2_bits_alias                         (io_in_2_bits_alias),
+    .io_in_2_bits_isKeyword                     (io_in_2_bits_isKeyword),
+    .io_in_2_bits_opcode                        (io_in_2_bits_opcode),
+    .io_in_2_bits_param                         (io_in_2_bits_param),
+    .io_in_2_bits_size                          (io_in_2_bits_size),
+    .io_in_2_bits_sourceId                      (io_in_2_bits_sourceId),
+    .io_in_2_bits_denied                        (io_in_2_bits_denied),
+    .io_in_2_bits_corrupt                       (io_in_2_bits_corrupt),
+    .io_in_2_bits_aliasTask                     (io_in_2_bits_aliasTask),
+    .io_in_2_bits_useProbeData                  (io_in_2_bits_useProbeData),
+    .io_in_2_bits_mshrRetry                     (io_in_2_bits_mshrRetry),
+    .io_in_2_bits_readProbeDataDown             (io_in_2_bits_readProbeDataDown),
+    .io_in_2_bits_fromL2pft                     (io_in_2_bits_fromL2pft),
+    .io_in_2_bits_dirty                         (io_in_2_bits_dirty),
+    .io_in_2_bits_way                           (io_in_2_bits_way),
+    .io_in_2_bits_meta_dirty                    (io_in_2_bits_meta_dirty),
+    .io_in_2_bits_meta_state                    (io_in_2_bits_meta_state),
+    .io_in_2_bits_meta_clients                  (io_in_2_bits_meta_clients),
+    .io_in_2_bits_meta_alias                    (io_in_2_bits_meta_alias),
+    .io_in_2_bits_meta_prefetch                 (io_in_2_bits_meta_prefetch),
+    .io_in_2_bits_meta_prefetchSrc              (io_in_2_bits_meta_prefetchSrc),
+    .io_in_2_bits_meta_accessed                 (io_in_2_bits_meta_accessed),
+    .io_in_2_bits_meta_tagErr                   (io_in_2_bits_meta_tagErr),
+    .io_in_2_bits_meta_dataErr                  (io_in_2_bits_meta_dataErr),
+    .io_in_2_bits_metaWen                       (io_in_2_bits_metaWen),
+    .io_in_2_bits_tagWen                        (io_in_2_bits_tagWen),
+    .io_in_2_bits_dsWen                         (io_in_2_bits_dsWen),
+    .io_in_2_bits_replTask                      (io_in_2_bits_replTask),
+    .io_in_2_bits_cmoTask                       (io_in_2_bits_cmoTask),
+    .io_in_2_bits_reqSource                     (io_in_2_bits_reqSource),
+    .io_in_2_bits_mergeA                        (io_in_2_bits_mergeA),
+    .io_in_2_bits_aMergeTask_off                (io_in_2_bits_aMergeTask_off),
+    .io_in_2_bits_aMergeTask_alias              (io_in_2_bits_aMergeTask_alias),
+    .io_in_2_bits_aMergeTask_vaddr              (io_in_2_bits_aMergeTask_vaddr),
+    .io_in_2_bits_aMergeTask_isKeyword          (io_in_2_bits_aMergeTask_isKeyword),
+    .io_in_2_bits_aMergeTask_opcode             (io_in_2_bits_aMergeTask_opcode),
+    .io_in_2_bits_aMergeTask_param              (io_in_2_bits_aMergeTask_param),
+    .io_in_2_bits_aMergeTask_sourceId           (io_in_2_bits_aMergeTask_sourceId),
+    .io_in_2_bits_aMergeTask_meta_dirty         (io_in_2_bits_aMergeTask_meta_dirty),
+    .io_in_2_bits_aMergeTask_meta_state         (io_in_2_bits_aMergeTask_meta_state),
+    .io_in_2_bits_aMergeTask_meta_clients       (io_in_2_bits_aMergeTask_meta_clients),
+    .io_in_2_bits_aMergeTask_meta_alias         (io_in_2_bits_aMergeTask_meta_alias),
+    .io_in_2_bits_aMergeTask_meta_accessed      (io_in_2_bits_aMergeTask_meta_accessed),
+    .io_in_2_bits_snpHitRelease                 (io_in_2_bits_snpHitRelease),
+    .io_in_2_bits_snpHitReleaseToInval          (io_in_2_bits_snpHitReleaseToInval),
+    .io_in_2_bits_snpHitReleaseToClean          (io_in_2_bits_snpHitReleaseToClean),
+    .io_in_2_bits_snpHitReleaseWithData         (io_in_2_bits_snpHitReleaseWithData),
+    .io_in_2_bits_snpHitReleaseIdx              (io_in_2_bits_snpHitReleaseIdx),
+    .io_in_2_bits_snpHitReleaseMeta_dirty       (io_in_2_bits_snpHitReleaseMeta_dirty),
+    .io_in_2_bits_snpHitReleaseMeta_state       (io_in_2_bits_snpHitReleaseMeta_state),
+    .io_in_2_bits_snpHitReleaseMeta_clients     (io_in_2_bits_snpHitReleaseMeta_clients),
+    .io_in_2_bits_snpHitReleaseMeta_alias       (io_in_2_bits_snpHitReleaseMeta_alias),
+    .io_in_2_bits_snpHitReleaseMeta_prefetch    (io_in_2_bits_snpHitReleaseMeta_prefetch),
+    .io_in_2_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_2_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_2_bits_snpHitReleaseMeta_accessed    (io_in_2_bits_snpHitReleaseMeta_accessed),
+    .io_in_2_bits_snpHitReleaseMeta_tagErr      (io_in_2_bits_snpHitReleaseMeta_tagErr),
+    .io_in_2_bits_snpHitReleaseMeta_dataErr     (io_in_2_bits_snpHitReleaseMeta_dataErr),
+    .io_in_2_bits_tgtID                         (io_in_2_bits_tgtID),
+    .io_in_2_bits_txnID                         (io_in_2_bits_txnID),
+    .io_in_2_bits_homeNID                       (io_in_2_bits_homeNID),
+    .io_in_2_bits_dbID                          (io_in_2_bits_dbID),
+    .io_in_2_bits_chiOpcode                     (io_in_2_bits_chiOpcode),
+    .io_in_2_bits_resp                          (io_in_2_bits_resp),
+    .io_in_2_bits_fwdState                      (io_in_2_bits_fwdState),
+    .io_in_2_bits_retToSrc                      (io_in_2_bits_retToSrc),
+    .io_in_2_bits_likelyshared                  (io_in_2_bits_likelyshared),
+    .io_in_2_bits_expCompAck                    (io_in_2_bits_expCompAck),
+    .io_in_2_bits_allowRetry                    (io_in_2_bits_allowRetry),
+    .io_in_2_bits_memAttr_allocate              (io_in_2_bits_memAttr_allocate),
+    .io_in_2_bits_memAttr_cacheable             (io_in_2_bits_memAttr_cacheable),
+    .io_in_2_bits_memAttr_ewa                   (io_in_2_bits_memAttr_ewa),
+    .io_in_2_bits_traceTag                      (io_in_2_bits_traceTag),
+    .io_in_3_ready                              (io_in_3_ready),
+    .io_in_3_valid                              (io_in_3_valid),
+    .io_in_3_bits_channel                       (io_in_3_bits_channel),
+    .io_in_3_bits_txChannel                     (io_in_3_bits_txChannel),
+    .io_in_3_bits_set                           (io_in_3_bits_set),
+    .io_in_3_bits_tag                           (io_in_3_bits_tag),
+    .io_in_3_bits_off                           (io_in_3_bits_off),
+    .io_in_3_bits_alias                         (io_in_3_bits_alias),
+    .io_in_3_bits_isKeyword                     (io_in_3_bits_isKeyword),
+    .io_in_3_bits_opcode                        (io_in_3_bits_opcode),
+    .io_in_3_bits_param                         (io_in_3_bits_param),
+    .io_in_3_bits_size                          (io_in_3_bits_size),
+    .io_in_3_bits_sourceId                      (io_in_3_bits_sourceId),
+    .io_in_3_bits_denied                        (io_in_3_bits_denied),
+    .io_in_3_bits_corrupt                       (io_in_3_bits_corrupt),
+    .io_in_3_bits_aliasTask                     (io_in_3_bits_aliasTask),
+    .io_in_3_bits_useProbeData                  (io_in_3_bits_useProbeData),
+    .io_in_3_bits_mshrRetry                     (io_in_3_bits_mshrRetry),
+    .io_in_3_bits_readProbeDataDown             (io_in_3_bits_readProbeDataDown),
+    .io_in_3_bits_fromL2pft                     (io_in_3_bits_fromL2pft),
+    .io_in_3_bits_dirty                         (io_in_3_bits_dirty),
+    .io_in_3_bits_way                           (io_in_3_bits_way),
+    .io_in_3_bits_meta_dirty                    (io_in_3_bits_meta_dirty),
+    .io_in_3_bits_meta_state                    (io_in_3_bits_meta_state),
+    .io_in_3_bits_meta_clients                  (io_in_3_bits_meta_clients),
+    .io_in_3_bits_meta_alias                    (io_in_3_bits_meta_alias),
+    .io_in_3_bits_meta_prefetch                 (io_in_3_bits_meta_prefetch),
+    .io_in_3_bits_meta_prefetchSrc              (io_in_3_bits_meta_prefetchSrc),
+    .io_in_3_bits_meta_accessed                 (io_in_3_bits_meta_accessed),
+    .io_in_3_bits_meta_tagErr                   (io_in_3_bits_meta_tagErr),
+    .io_in_3_bits_meta_dataErr                  (io_in_3_bits_meta_dataErr),
+    .io_in_3_bits_metaWen                       (io_in_3_bits_metaWen),
+    .io_in_3_bits_tagWen                        (io_in_3_bits_tagWen),
+    .io_in_3_bits_dsWen                         (io_in_3_bits_dsWen),
+    .io_in_3_bits_replTask                      (io_in_3_bits_replTask),
+    .io_in_3_bits_cmoTask                       (io_in_3_bits_cmoTask),
+    .io_in_3_bits_reqSource                     (io_in_3_bits_reqSource),
+    .io_in_3_bits_mergeA                        (io_in_3_bits_mergeA),
+    .io_in_3_bits_aMergeTask_off                (io_in_3_bits_aMergeTask_off),
+    .io_in_3_bits_aMergeTask_alias              (io_in_3_bits_aMergeTask_alias),
+    .io_in_3_bits_aMergeTask_vaddr              (io_in_3_bits_aMergeTask_vaddr),
+    .io_in_3_bits_aMergeTask_isKeyword          (io_in_3_bits_aMergeTask_isKeyword),
+    .io_in_3_bits_aMergeTask_opcode             (io_in_3_bits_aMergeTask_opcode),
+    .io_in_3_bits_aMergeTask_param              (io_in_3_bits_aMergeTask_param),
+    .io_in_3_bits_aMergeTask_sourceId           (io_in_3_bits_aMergeTask_sourceId),
+    .io_in_3_bits_aMergeTask_meta_dirty         (io_in_3_bits_aMergeTask_meta_dirty),
+    .io_in_3_bits_aMergeTask_meta_state         (io_in_3_bits_aMergeTask_meta_state),
+    .io_in_3_bits_aMergeTask_meta_clients       (io_in_3_bits_aMergeTask_meta_clients),
+    .io_in_3_bits_aMergeTask_meta_alias         (io_in_3_bits_aMergeTask_meta_alias),
+    .io_in_3_bits_aMergeTask_meta_accessed      (io_in_3_bits_aMergeTask_meta_accessed),
+    .io_in_3_bits_snpHitRelease                 (io_in_3_bits_snpHitRelease),
+    .io_in_3_bits_snpHitReleaseToInval          (io_in_3_bits_snpHitReleaseToInval),
+    .io_in_3_bits_snpHitReleaseToClean          (io_in_3_bits_snpHitReleaseToClean),
+    .io_in_3_bits_snpHitReleaseWithData         (io_in_3_bits_snpHitReleaseWithData),
+    .io_in_3_bits_snpHitReleaseIdx              (io_in_3_bits_snpHitReleaseIdx),
+    .io_in_3_bits_snpHitReleaseMeta_dirty       (io_in_3_bits_snpHitReleaseMeta_dirty),
+    .io_in_3_bits_snpHitReleaseMeta_state       (io_in_3_bits_snpHitReleaseMeta_state),
+    .io_in_3_bits_snpHitReleaseMeta_clients     (io_in_3_bits_snpHitReleaseMeta_clients),
+    .io_in_3_bits_snpHitReleaseMeta_alias       (io_in_3_bits_snpHitReleaseMeta_alias),
+    .io_in_3_bits_snpHitReleaseMeta_prefetch    (io_in_3_bits_snpHitReleaseMeta_prefetch),
+    .io_in_3_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_3_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_3_bits_snpHitReleaseMeta_accessed    (io_in_3_bits_snpHitReleaseMeta_accessed),
+    .io_in_3_bits_snpHitReleaseMeta_tagErr      (io_in_3_bits_snpHitReleaseMeta_tagErr),
+    .io_in_3_bits_snpHitReleaseMeta_dataErr     (io_in_3_bits_snpHitReleaseMeta_dataErr),
+    .io_in_3_bits_tgtID                         (io_in_3_bits_tgtID),
+    .io_in_3_bits_txnID                         (io_in_3_bits_txnID),
+    .io_in_3_bits_homeNID                       (io_in_3_bits_homeNID),
+    .io_in_3_bits_dbID                          (io_in_3_bits_dbID),
+    .io_in_3_bits_chiOpcode                     (io_in_3_bits_chiOpcode),
+    .io_in_3_bits_resp                          (io_in_3_bits_resp),
+    .io_in_3_bits_fwdState                      (io_in_3_bits_fwdState),
+    .io_in_3_bits_retToSrc                      (io_in_3_bits_retToSrc),
+    .io_in_3_bits_likelyshared                  (io_in_3_bits_likelyshared),
+    .io_in_3_bits_expCompAck                    (io_in_3_bits_expCompAck),
+    .io_in_3_bits_allowRetry                    (io_in_3_bits_allowRetry),
+    .io_in_3_bits_memAttr_allocate              (io_in_3_bits_memAttr_allocate),
+    .io_in_3_bits_memAttr_cacheable             (io_in_3_bits_memAttr_cacheable),
+    .io_in_3_bits_memAttr_ewa                   (io_in_3_bits_memAttr_ewa),
+    .io_in_3_bits_traceTag                      (io_in_3_bits_traceTag),
+    .io_in_4_ready                              (io_in_4_ready),
+    .io_in_4_valid                              (io_in_4_valid),
+    .io_in_4_bits_channel                       (io_in_4_bits_channel),
+    .io_in_4_bits_txChannel                     (io_in_4_bits_txChannel),
+    .io_in_4_bits_set                           (io_in_4_bits_set),
+    .io_in_4_bits_tag                           (io_in_4_bits_tag),
+    .io_in_4_bits_off                           (io_in_4_bits_off),
+    .io_in_4_bits_alias                         (io_in_4_bits_alias),
+    .io_in_4_bits_isKeyword                     (io_in_4_bits_isKeyword),
+    .io_in_4_bits_opcode                        (io_in_4_bits_opcode),
+    .io_in_4_bits_param                         (io_in_4_bits_param),
+    .io_in_4_bits_size                          (io_in_4_bits_size),
+    .io_in_4_bits_sourceId                      (io_in_4_bits_sourceId),
+    .io_in_4_bits_denied                        (io_in_4_bits_denied),
+    .io_in_4_bits_corrupt                       (io_in_4_bits_corrupt),
+    .io_in_4_bits_aliasTask                     (io_in_4_bits_aliasTask),
+    .io_in_4_bits_useProbeData                  (io_in_4_bits_useProbeData),
+    .io_in_4_bits_mshrRetry                     (io_in_4_bits_mshrRetry),
+    .io_in_4_bits_readProbeDataDown             (io_in_4_bits_readProbeDataDown),
+    .io_in_4_bits_fromL2pft                     (io_in_4_bits_fromL2pft),
+    .io_in_4_bits_dirty                         (io_in_4_bits_dirty),
+    .io_in_4_bits_way                           (io_in_4_bits_way),
+    .io_in_4_bits_meta_dirty                    (io_in_4_bits_meta_dirty),
+    .io_in_4_bits_meta_state                    (io_in_4_bits_meta_state),
+    .io_in_4_bits_meta_clients                  (io_in_4_bits_meta_clients),
+    .io_in_4_bits_meta_alias                    (io_in_4_bits_meta_alias),
+    .io_in_4_bits_meta_prefetch                 (io_in_4_bits_meta_prefetch),
+    .io_in_4_bits_meta_prefetchSrc              (io_in_4_bits_meta_prefetchSrc),
+    .io_in_4_bits_meta_accessed                 (io_in_4_bits_meta_accessed),
+    .io_in_4_bits_meta_tagErr                   (io_in_4_bits_meta_tagErr),
+    .io_in_4_bits_meta_dataErr                  (io_in_4_bits_meta_dataErr),
+    .io_in_4_bits_metaWen                       (io_in_4_bits_metaWen),
+    .io_in_4_bits_tagWen                        (io_in_4_bits_tagWen),
+    .io_in_4_bits_dsWen                         (io_in_4_bits_dsWen),
+    .io_in_4_bits_replTask                      (io_in_4_bits_replTask),
+    .io_in_4_bits_cmoTask                       (io_in_4_bits_cmoTask),
+    .io_in_4_bits_reqSource                     (io_in_4_bits_reqSource),
+    .io_in_4_bits_mergeA                        (io_in_4_bits_mergeA),
+    .io_in_4_bits_aMergeTask_off                (io_in_4_bits_aMergeTask_off),
+    .io_in_4_bits_aMergeTask_alias              (io_in_4_bits_aMergeTask_alias),
+    .io_in_4_bits_aMergeTask_vaddr              (io_in_4_bits_aMergeTask_vaddr),
+    .io_in_4_bits_aMergeTask_isKeyword          (io_in_4_bits_aMergeTask_isKeyword),
+    .io_in_4_bits_aMergeTask_opcode             (io_in_4_bits_aMergeTask_opcode),
+    .io_in_4_bits_aMergeTask_param              (io_in_4_bits_aMergeTask_param),
+    .io_in_4_bits_aMergeTask_sourceId           (io_in_4_bits_aMergeTask_sourceId),
+    .io_in_4_bits_aMergeTask_meta_dirty         (io_in_4_bits_aMergeTask_meta_dirty),
+    .io_in_4_bits_aMergeTask_meta_state         (io_in_4_bits_aMergeTask_meta_state),
+    .io_in_4_bits_aMergeTask_meta_clients       (io_in_4_bits_aMergeTask_meta_clients),
+    .io_in_4_bits_aMergeTask_meta_alias         (io_in_4_bits_aMergeTask_meta_alias),
+    .io_in_4_bits_aMergeTask_meta_accessed      (io_in_4_bits_aMergeTask_meta_accessed),
+    .io_in_4_bits_snpHitRelease                 (io_in_4_bits_snpHitRelease),
+    .io_in_4_bits_snpHitReleaseToInval          (io_in_4_bits_snpHitReleaseToInval),
+    .io_in_4_bits_snpHitReleaseToClean          (io_in_4_bits_snpHitReleaseToClean),
+    .io_in_4_bits_snpHitReleaseWithData         (io_in_4_bits_snpHitReleaseWithData),
+    .io_in_4_bits_snpHitReleaseIdx              (io_in_4_bits_snpHitReleaseIdx),
+    .io_in_4_bits_snpHitReleaseMeta_dirty       (io_in_4_bits_snpHitReleaseMeta_dirty),
+    .io_in_4_bits_snpHitReleaseMeta_state       (io_in_4_bits_snpHitReleaseMeta_state),
+    .io_in_4_bits_snpHitReleaseMeta_clients     (io_in_4_bits_snpHitReleaseMeta_clients),
+    .io_in_4_bits_snpHitReleaseMeta_alias       (io_in_4_bits_snpHitReleaseMeta_alias),
+    .io_in_4_bits_snpHitReleaseMeta_prefetch    (io_in_4_bits_snpHitReleaseMeta_prefetch),
+    .io_in_4_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_4_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_4_bits_snpHitReleaseMeta_accessed    (io_in_4_bits_snpHitReleaseMeta_accessed),
+    .io_in_4_bits_snpHitReleaseMeta_tagErr      (io_in_4_bits_snpHitReleaseMeta_tagErr),
+    .io_in_4_bits_snpHitReleaseMeta_dataErr     (io_in_4_bits_snpHitReleaseMeta_dataErr),
+    .io_in_4_bits_tgtID                         (io_in_4_bits_tgtID),
+    .io_in_4_bits_txnID                         (io_in_4_bits_txnID),
+    .io_in_4_bits_homeNID                       (io_in_4_bits_homeNID),
+    .io_in_4_bits_dbID                          (io_in_4_bits_dbID),
+    .io_in_4_bits_chiOpcode                     (io_in_4_bits_chiOpcode),
+    .io_in_4_bits_resp                          (io_in_4_bits_resp),
+    .io_in_4_bits_fwdState                      (io_in_4_bits_fwdState),
+    .io_in_4_bits_retToSrc                      (io_in_4_bits_retToSrc),
+    .io_in_4_bits_likelyshared                  (io_in_4_bits_likelyshared),
+    .io_in_4_bits_expCompAck                    (io_in_4_bits_expCompAck),
+    .io_in_4_bits_allowRetry                    (io_in_4_bits_allowRetry),
+    .io_in_4_bits_memAttr_allocate              (io_in_4_bits_memAttr_allocate),
+    .io_in_4_bits_memAttr_cacheable             (io_in_4_bits_memAttr_cacheable),
+    .io_in_4_bits_memAttr_ewa                   (io_in_4_bits_memAttr_ewa),
+    .io_in_4_bits_traceTag                      (io_in_4_bits_traceTag),
+    .io_in_5_ready                              (io_in_5_ready),
+    .io_in_5_valid                              (io_in_5_valid),
+    .io_in_5_bits_channel                       (io_in_5_bits_channel),
+    .io_in_5_bits_txChannel                     (io_in_5_bits_txChannel),
+    .io_in_5_bits_set                           (io_in_5_bits_set),
+    .io_in_5_bits_tag                           (io_in_5_bits_tag),
+    .io_in_5_bits_off                           (io_in_5_bits_off),
+    .io_in_5_bits_alias                         (io_in_5_bits_alias),
+    .io_in_5_bits_isKeyword                     (io_in_5_bits_isKeyword),
+    .io_in_5_bits_opcode                        (io_in_5_bits_opcode),
+    .io_in_5_bits_param                         (io_in_5_bits_param),
+    .io_in_5_bits_size                          (io_in_5_bits_size),
+    .io_in_5_bits_sourceId                      (io_in_5_bits_sourceId),
+    .io_in_5_bits_denied                        (io_in_5_bits_denied),
+    .io_in_5_bits_corrupt                       (io_in_5_bits_corrupt),
+    .io_in_5_bits_aliasTask                     (io_in_5_bits_aliasTask),
+    .io_in_5_bits_useProbeData                  (io_in_5_bits_useProbeData),
+    .io_in_5_bits_mshrRetry                     (io_in_5_bits_mshrRetry),
+    .io_in_5_bits_readProbeDataDown             (io_in_5_bits_readProbeDataDown),
+    .io_in_5_bits_fromL2pft                     (io_in_5_bits_fromL2pft),
+    .io_in_5_bits_dirty                         (io_in_5_bits_dirty),
+    .io_in_5_bits_way                           (io_in_5_bits_way),
+    .io_in_5_bits_meta_dirty                    (io_in_5_bits_meta_dirty),
+    .io_in_5_bits_meta_state                    (io_in_5_bits_meta_state),
+    .io_in_5_bits_meta_clients                  (io_in_5_bits_meta_clients),
+    .io_in_5_bits_meta_alias                    (io_in_5_bits_meta_alias),
+    .io_in_5_bits_meta_prefetch                 (io_in_5_bits_meta_prefetch),
+    .io_in_5_bits_meta_prefetchSrc              (io_in_5_bits_meta_prefetchSrc),
+    .io_in_5_bits_meta_accessed                 (io_in_5_bits_meta_accessed),
+    .io_in_5_bits_meta_tagErr                   (io_in_5_bits_meta_tagErr),
+    .io_in_5_bits_meta_dataErr                  (io_in_5_bits_meta_dataErr),
+    .io_in_5_bits_metaWen                       (io_in_5_bits_metaWen),
+    .io_in_5_bits_tagWen                        (io_in_5_bits_tagWen),
+    .io_in_5_bits_dsWen                         (io_in_5_bits_dsWen),
+    .io_in_5_bits_replTask                      (io_in_5_bits_replTask),
+    .io_in_5_bits_cmoTask                       (io_in_5_bits_cmoTask),
+    .io_in_5_bits_reqSource                     (io_in_5_bits_reqSource),
+    .io_in_5_bits_mergeA                        (io_in_5_bits_mergeA),
+    .io_in_5_bits_aMergeTask_off                (io_in_5_bits_aMergeTask_off),
+    .io_in_5_bits_aMergeTask_alias              (io_in_5_bits_aMergeTask_alias),
+    .io_in_5_bits_aMergeTask_vaddr              (io_in_5_bits_aMergeTask_vaddr),
+    .io_in_5_bits_aMergeTask_isKeyword          (io_in_5_bits_aMergeTask_isKeyword),
+    .io_in_5_bits_aMergeTask_opcode             (io_in_5_bits_aMergeTask_opcode),
+    .io_in_5_bits_aMergeTask_param              (io_in_5_bits_aMergeTask_param),
+    .io_in_5_bits_aMergeTask_sourceId           (io_in_5_bits_aMergeTask_sourceId),
+    .io_in_5_bits_aMergeTask_meta_dirty         (io_in_5_bits_aMergeTask_meta_dirty),
+    .io_in_5_bits_aMergeTask_meta_state         (io_in_5_bits_aMergeTask_meta_state),
+    .io_in_5_bits_aMergeTask_meta_clients       (io_in_5_bits_aMergeTask_meta_clients),
+    .io_in_5_bits_aMergeTask_meta_alias         (io_in_5_bits_aMergeTask_meta_alias),
+    .io_in_5_bits_aMergeTask_meta_accessed      (io_in_5_bits_aMergeTask_meta_accessed),
+    .io_in_5_bits_snpHitRelease                 (io_in_5_bits_snpHitRelease),
+    .io_in_5_bits_snpHitReleaseToInval          (io_in_5_bits_snpHitReleaseToInval),
+    .io_in_5_bits_snpHitReleaseToClean          (io_in_5_bits_snpHitReleaseToClean),
+    .io_in_5_bits_snpHitReleaseWithData         (io_in_5_bits_snpHitReleaseWithData),
+    .io_in_5_bits_snpHitReleaseIdx              (io_in_5_bits_snpHitReleaseIdx),
+    .io_in_5_bits_snpHitReleaseMeta_dirty       (io_in_5_bits_snpHitReleaseMeta_dirty),
+    .io_in_5_bits_snpHitReleaseMeta_state       (io_in_5_bits_snpHitReleaseMeta_state),
+    .io_in_5_bits_snpHitReleaseMeta_clients     (io_in_5_bits_snpHitReleaseMeta_clients),
+    .io_in_5_bits_snpHitReleaseMeta_alias       (io_in_5_bits_snpHitReleaseMeta_alias),
+    .io_in_5_bits_snpHitReleaseMeta_prefetch    (io_in_5_bits_snpHitReleaseMeta_prefetch),
+    .io_in_5_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_5_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_5_bits_snpHitReleaseMeta_accessed    (io_in_5_bits_snpHitReleaseMeta_accessed),
+    .io_in_5_bits_snpHitReleaseMeta_tagErr      (io_in_5_bits_snpHitReleaseMeta_tagErr),
+    .io_in_5_bits_snpHitReleaseMeta_dataErr     (io_in_5_bits_snpHitReleaseMeta_dataErr),
+    .io_in_5_bits_tgtID                         (io_in_5_bits_tgtID),
+    .io_in_5_bits_txnID                         (io_in_5_bits_txnID),
+    .io_in_5_bits_homeNID                       (io_in_5_bits_homeNID),
+    .io_in_5_bits_dbID                          (io_in_5_bits_dbID),
+    .io_in_5_bits_chiOpcode                     (io_in_5_bits_chiOpcode),
+    .io_in_5_bits_resp                          (io_in_5_bits_resp),
+    .io_in_5_bits_fwdState                      (io_in_5_bits_fwdState),
+    .io_in_5_bits_retToSrc                      (io_in_5_bits_retToSrc),
+    .io_in_5_bits_likelyshared                  (io_in_5_bits_likelyshared),
+    .io_in_5_bits_expCompAck                    (io_in_5_bits_expCompAck),
+    .io_in_5_bits_allowRetry                    (io_in_5_bits_allowRetry),
+    .io_in_5_bits_memAttr_allocate              (io_in_5_bits_memAttr_allocate),
+    .io_in_5_bits_memAttr_cacheable             (io_in_5_bits_memAttr_cacheable),
+    .io_in_5_bits_memAttr_ewa                   (io_in_5_bits_memAttr_ewa),
+    .io_in_5_bits_traceTag                      (io_in_5_bits_traceTag),
+    .io_in_6_ready                              (io_in_6_ready),
+    .io_in_6_valid                              (io_in_6_valid),
+    .io_in_6_bits_channel                       (io_in_6_bits_channel),
+    .io_in_6_bits_txChannel                     (io_in_6_bits_txChannel),
+    .io_in_6_bits_set                           (io_in_6_bits_set),
+    .io_in_6_bits_tag                           (io_in_6_bits_tag),
+    .io_in_6_bits_off                           (io_in_6_bits_off),
+    .io_in_6_bits_alias                         (io_in_6_bits_alias),
+    .io_in_6_bits_isKeyword                     (io_in_6_bits_isKeyword),
+    .io_in_6_bits_opcode                        (io_in_6_bits_opcode),
+    .io_in_6_bits_param                         (io_in_6_bits_param),
+    .io_in_6_bits_size                          (io_in_6_bits_size),
+    .io_in_6_bits_sourceId                      (io_in_6_bits_sourceId),
+    .io_in_6_bits_denied                        (io_in_6_bits_denied),
+    .io_in_6_bits_corrupt                       (io_in_6_bits_corrupt),
+    .io_in_6_bits_aliasTask                     (io_in_6_bits_aliasTask),
+    .io_in_6_bits_useProbeData                  (io_in_6_bits_useProbeData),
+    .io_in_6_bits_mshrRetry                     (io_in_6_bits_mshrRetry),
+    .io_in_6_bits_readProbeDataDown             (io_in_6_bits_readProbeDataDown),
+    .io_in_6_bits_fromL2pft                     (io_in_6_bits_fromL2pft),
+    .io_in_6_bits_dirty                         (io_in_6_bits_dirty),
+    .io_in_6_bits_way                           (io_in_6_bits_way),
+    .io_in_6_bits_meta_dirty                    (io_in_6_bits_meta_dirty),
+    .io_in_6_bits_meta_state                    (io_in_6_bits_meta_state),
+    .io_in_6_bits_meta_clients                  (io_in_6_bits_meta_clients),
+    .io_in_6_bits_meta_alias                    (io_in_6_bits_meta_alias),
+    .io_in_6_bits_meta_prefetch                 (io_in_6_bits_meta_prefetch),
+    .io_in_6_bits_meta_prefetchSrc              (io_in_6_bits_meta_prefetchSrc),
+    .io_in_6_bits_meta_accessed                 (io_in_6_bits_meta_accessed),
+    .io_in_6_bits_meta_tagErr                   (io_in_6_bits_meta_tagErr),
+    .io_in_6_bits_meta_dataErr                  (io_in_6_bits_meta_dataErr),
+    .io_in_6_bits_metaWen                       (io_in_6_bits_metaWen),
+    .io_in_6_bits_tagWen                        (io_in_6_bits_tagWen),
+    .io_in_6_bits_dsWen                         (io_in_6_bits_dsWen),
+    .io_in_6_bits_replTask                      (io_in_6_bits_replTask),
+    .io_in_6_bits_cmoTask                       (io_in_6_bits_cmoTask),
+    .io_in_6_bits_reqSource                     (io_in_6_bits_reqSource),
+    .io_in_6_bits_mergeA                        (io_in_6_bits_mergeA),
+    .io_in_6_bits_aMergeTask_off                (io_in_6_bits_aMergeTask_off),
+    .io_in_6_bits_aMergeTask_alias              (io_in_6_bits_aMergeTask_alias),
+    .io_in_6_bits_aMergeTask_vaddr              (io_in_6_bits_aMergeTask_vaddr),
+    .io_in_6_bits_aMergeTask_isKeyword          (io_in_6_bits_aMergeTask_isKeyword),
+    .io_in_6_bits_aMergeTask_opcode             (io_in_6_bits_aMergeTask_opcode),
+    .io_in_6_bits_aMergeTask_param              (io_in_6_bits_aMergeTask_param),
+    .io_in_6_bits_aMergeTask_sourceId           (io_in_6_bits_aMergeTask_sourceId),
+    .io_in_6_bits_aMergeTask_meta_dirty         (io_in_6_bits_aMergeTask_meta_dirty),
+    .io_in_6_bits_aMergeTask_meta_state         (io_in_6_bits_aMergeTask_meta_state),
+    .io_in_6_bits_aMergeTask_meta_clients       (io_in_6_bits_aMergeTask_meta_clients),
+    .io_in_6_bits_aMergeTask_meta_alias         (io_in_6_bits_aMergeTask_meta_alias),
+    .io_in_6_bits_aMergeTask_meta_accessed      (io_in_6_bits_aMergeTask_meta_accessed),
+    .io_in_6_bits_snpHitRelease                 (io_in_6_bits_snpHitRelease),
+    .io_in_6_bits_snpHitReleaseToInval          (io_in_6_bits_snpHitReleaseToInval),
+    .io_in_6_bits_snpHitReleaseToClean          (io_in_6_bits_snpHitReleaseToClean),
+    .io_in_6_bits_snpHitReleaseWithData         (io_in_6_bits_snpHitReleaseWithData),
+    .io_in_6_bits_snpHitReleaseIdx              (io_in_6_bits_snpHitReleaseIdx),
+    .io_in_6_bits_snpHitReleaseMeta_dirty       (io_in_6_bits_snpHitReleaseMeta_dirty),
+    .io_in_6_bits_snpHitReleaseMeta_state       (io_in_6_bits_snpHitReleaseMeta_state),
+    .io_in_6_bits_snpHitReleaseMeta_clients     (io_in_6_bits_snpHitReleaseMeta_clients),
+    .io_in_6_bits_snpHitReleaseMeta_alias       (io_in_6_bits_snpHitReleaseMeta_alias),
+    .io_in_6_bits_snpHitReleaseMeta_prefetch    (io_in_6_bits_snpHitReleaseMeta_prefetch),
+    .io_in_6_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_6_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_6_bits_snpHitReleaseMeta_accessed    (io_in_6_bits_snpHitReleaseMeta_accessed),
+    .io_in_6_bits_snpHitReleaseMeta_tagErr      (io_in_6_bits_snpHitReleaseMeta_tagErr),
+    .io_in_6_bits_snpHitReleaseMeta_dataErr     (io_in_6_bits_snpHitReleaseMeta_dataErr),
+    .io_in_6_bits_tgtID                         (io_in_6_bits_tgtID),
+    .io_in_6_bits_txnID                         (io_in_6_bits_txnID),
+    .io_in_6_bits_homeNID                       (io_in_6_bits_homeNID),
+    .io_in_6_bits_dbID                          (io_in_6_bits_dbID),
+    .io_in_6_bits_chiOpcode                     (io_in_6_bits_chiOpcode),
+    .io_in_6_bits_resp                          (io_in_6_bits_resp),
+    .io_in_6_bits_fwdState                      (io_in_6_bits_fwdState),
+    .io_in_6_bits_retToSrc                      (io_in_6_bits_retToSrc),
+    .io_in_6_bits_likelyshared                  (io_in_6_bits_likelyshared),
+    .io_in_6_bits_expCompAck                    (io_in_6_bits_expCompAck),
+    .io_in_6_bits_allowRetry                    (io_in_6_bits_allowRetry),
+    .io_in_6_bits_memAttr_allocate              (io_in_6_bits_memAttr_allocate),
+    .io_in_6_bits_memAttr_cacheable             (io_in_6_bits_memAttr_cacheable),
+    .io_in_6_bits_memAttr_ewa                   (io_in_6_bits_memAttr_ewa),
+    .io_in_6_bits_traceTag                      (io_in_6_bits_traceTag),
+    .io_in_7_ready                              (io_in_7_ready),
+    .io_in_7_valid                              (io_in_7_valid),
+    .io_in_7_bits_channel                       (io_in_7_bits_channel),
+    .io_in_7_bits_txChannel                     (io_in_7_bits_txChannel),
+    .io_in_7_bits_set                           (io_in_7_bits_set),
+    .io_in_7_bits_tag                           (io_in_7_bits_tag),
+    .io_in_7_bits_off                           (io_in_7_bits_off),
+    .io_in_7_bits_alias                         (io_in_7_bits_alias),
+    .io_in_7_bits_isKeyword                     (io_in_7_bits_isKeyword),
+    .io_in_7_bits_opcode                        (io_in_7_bits_opcode),
+    .io_in_7_bits_param                         (io_in_7_bits_param),
+    .io_in_7_bits_size                          (io_in_7_bits_size),
+    .io_in_7_bits_sourceId                      (io_in_7_bits_sourceId),
+    .io_in_7_bits_denied                        (io_in_7_bits_denied),
+    .io_in_7_bits_corrupt                       (io_in_7_bits_corrupt),
+    .io_in_7_bits_aliasTask                     (io_in_7_bits_aliasTask),
+    .io_in_7_bits_useProbeData                  (io_in_7_bits_useProbeData),
+    .io_in_7_bits_mshrRetry                     (io_in_7_bits_mshrRetry),
+    .io_in_7_bits_readProbeDataDown             (io_in_7_bits_readProbeDataDown),
+    .io_in_7_bits_fromL2pft                     (io_in_7_bits_fromL2pft),
+    .io_in_7_bits_dirty                         (io_in_7_bits_dirty),
+    .io_in_7_bits_way                           (io_in_7_bits_way),
+    .io_in_7_bits_meta_dirty                    (io_in_7_bits_meta_dirty),
+    .io_in_7_bits_meta_state                    (io_in_7_bits_meta_state),
+    .io_in_7_bits_meta_clients                  (io_in_7_bits_meta_clients),
+    .io_in_7_bits_meta_alias                    (io_in_7_bits_meta_alias),
+    .io_in_7_bits_meta_prefetch                 (io_in_7_bits_meta_prefetch),
+    .io_in_7_bits_meta_prefetchSrc              (io_in_7_bits_meta_prefetchSrc),
+    .io_in_7_bits_meta_accessed                 (io_in_7_bits_meta_accessed),
+    .io_in_7_bits_meta_tagErr                   (io_in_7_bits_meta_tagErr),
+    .io_in_7_bits_meta_dataErr                  (io_in_7_bits_meta_dataErr),
+    .io_in_7_bits_metaWen                       (io_in_7_bits_metaWen),
+    .io_in_7_bits_tagWen                        (io_in_7_bits_tagWen),
+    .io_in_7_bits_dsWen                         (io_in_7_bits_dsWen),
+    .io_in_7_bits_replTask                      (io_in_7_bits_replTask),
+    .io_in_7_bits_cmoTask                       (io_in_7_bits_cmoTask),
+    .io_in_7_bits_reqSource                     (io_in_7_bits_reqSource),
+    .io_in_7_bits_mergeA                        (io_in_7_bits_mergeA),
+    .io_in_7_bits_aMergeTask_off                (io_in_7_bits_aMergeTask_off),
+    .io_in_7_bits_aMergeTask_alias              (io_in_7_bits_aMergeTask_alias),
+    .io_in_7_bits_aMergeTask_vaddr              (io_in_7_bits_aMergeTask_vaddr),
+    .io_in_7_bits_aMergeTask_isKeyword          (io_in_7_bits_aMergeTask_isKeyword),
+    .io_in_7_bits_aMergeTask_opcode             (io_in_7_bits_aMergeTask_opcode),
+    .io_in_7_bits_aMergeTask_param              (io_in_7_bits_aMergeTask_param),
+    .io_in_7_bits_aMergeTask_sourceId           (io_in_7_bits_aMergeTask_sourceId),
+    .io_in_7_bits_aMergeTask_meta_dirty         (io_in_7_bits_aMergeTask_meta_dirty),
+    .io_in_7_bits_aMergeTask_meta_state         (io_in_7_bits_aMergeTask_meta_state),
+    .io_in_7_bits_aMergeTask_meta_clients       (io_in_7_bits_aMergeTask_meta_clients),
+    .io_in_7_bits_aMergeTask_meta_alias         (io_in_7_bits_aMergeTask_meta_alias),
+    .io_in_7_bits_aMergeTask_meta_accessed      (io_in_7_bits_aMergeTask_meta_accessed),
+    .io_in_7_bits_snpHitRelease                 (io_in_7_bits_snpHitRelease),
+    .io_in_7_bits_snpHitReleaseToInval          (io_in_7_bits_snpHitReleaseToInval),
+    .io_in_7_bits_snpHitReleaseToClean          (io_in_7_bits_snpHitReleaseToClean),
+    .io_in_7_bits_snpHitReleaseWithData         (io_in_7_bits_snpHitReleaseWithData),
+    .io_in_7_bits_snpHitReleaseIdx              (io_in_7_bits_snpHitReleaseIdx),
+    .io_in_7_bits_snpHitReleaseMeta_dirty       (io_in_7_bits_snpHitReleaseMeta_dirty),
+    .io_in_7_bits_snpHitReleaseMeta_state       (io_in_7_bits_snpHitReleaseMeta_state),
+    .io_in_7_bits_snpHitReleaseMeta_clients     (io_in_7_bits_snpHitReleaseMeta_clients),
+    .io_in_7_bits_snpHitReleaseMeta_alias       (io_in_7_bits_snpHitReleaseMeta_alias),
+    .io_in_7_bits_snpHitReleaseMeta_prefetch    (io_in_7_bits_snpHitReleaseMeta_prefetch),
+    .io_in_7_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_7_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_7_bits_snpHitReleaseMeta_accessed    (io_in_7_bits_snpHitReleaseMeta_accessed),
+    .io_in_7_bits_snpHitReleaseMeta_tagErr      (io_in_7_bits_snpHitReleaseMeta_tagErr),
+    .io_in_7_bits_snpHitReleaseMeta_dataErr     (io_in_7_bits_snpHitReleaseMeta_dataErr),
+    .io_in_7_bits_tgtID                         (io_in_7_bits_tgtID),
+    .io_in_7_bits_txnID                         (io_in_7_bits_txnID),
+    .io_in_7_bits_homeNID                       (io_in_7_bits_homeNID),
+    .io_in_7_bits_dbID                          (io_in_7_bits_dbID),
+    .io_in_7_bits_chiOpcode                     (io_in_7_bits_chiOpcode),
+    .io_in_7_bits_resp                          (io_in_7_bits_resp),
+    .io_in_7_bits_fwdState                      (io_in_7_bits_fwdState),
+    .io_in_7_bits_retToSrc                      (io_in_7_bits_retToSrc),
+    .io_in_7_bits_likelyshared                  (io_in_7_bits_likelyshared),
+    .io_in_7_bits_expCompAck                    (io_in_7_bits_expCompAck),
+    .io_in_7_bits_allowRetry                    (io_in_7_bits_allowRetry),
+    .io_in_7_bits_memAttr_allocate              (io_in_7_bits_memAttr_allocate),
+    .io_in_7_bits_memAttr_cacheable             (io_in_7_bits_memAttr_cacheable),
+    .io_in_7_bits_memAttr_ewa                   (io_in_7_bits_memAttr_ewa),
+    .io_in_7_bits_traceTag                      (io_in_7_bits_traceTag),
+    .io_out_ready                               (io_out_ready & finalSelLow),
+    .io_out_valid                               (_lowArb_io_out_valid),
+    .io_out_bits_channel                        (_lowArb_io_out_bits_channel),
+    .io_out_bits_txChannel                      (_lowArb_io_out_bits_txChannel),
+    .io_out_bits_set                            (_lowArb_io_out_bits_set),
+    .io_out_bits_tag                            (_lowArb_io_out_bits_tag),
+    .io_out_bits_off                            (_lowArb_io_out_bits_off),
+    .io_out_bits_alias                          (_lowArb_io_out_bits_alias),
+    .io_out_bits_isKeyword                      (_lowArb_io_out_bits_isKeyword),
+    .io_out_bits_opcode                         (_lowArb_io_out_bits_opcode),
+    .io_out_bits_param                          (_lowArb_io_out_bits_param),
+    .io_out_bits_size                           (_lowArb_io_out_bits_size),
+    .io_out_bits_sourceId                       (_lowArb_io_out_bits_sourceId),
+    .io_out_bits_denied                         (_lowArb_io_out_bits_denied),
+    .io_out_bits_corrupt                        (_lowArb_io_out_bits_corrupt),
+    .io_out_bits_mshrTask                       (_lowArb_io_out_bits_mshrTask),
+    .io_out_bits_aliasTask                      (_lowArb_io_out_bits_aliasTask),
+    .io_out_bits_useProbeData                   (_lowArb_io_out_bits_useProbeData),
+    .io_out_bits_mshrRetry                      (_lowArb_io_out_bits_mshrRetry),
+    .io_out_bits_readProbeDataDown              (_lowArb_io_out_bits_readProbeDataDown),
+    .io_out_bits_fromL2pft                      (_lowArb_io_out_bits_fromL2pft),
+    .io_out_bits_dirty                          (_lowArb_io_out_bits_dirty),
+    .io_out_bits_way                            (_lowArb_io_out_bits_way),
+    .io_out_bits_meta_dirty                     (_lowArb_io_out_bits_meta_dirty),
+    .io_out_bits_meta_state                     (_lowArb_io_out_bits_meta_state),
+    .io_out_bits_meta_clients                   (_lowArb_io_out_bits_meta_clients),
+    .io_out_bits_meta_alias                     (_lowArb_io_out_bits_meta_alias),
+    .io_out_bits_meta_prefetch                  (_lowArb_io_out_bits_meta_prefetch),
+    .io_out_bits_meta_prefetchSrc               (_lowArb_io_out_bits_meta_prefetchSrc),
+    .io_out_bits_meta_accessed                  (_lowArb_io_out_bits_meta_accessed),
+    .io_out_bits_meta_tagErr                    (_lowArb_io_out_bits_meta_tagErr),
+    .io_out_bits_meta_dataErr                   (_lowArb_io_out_bits_meta_dataErr),
+    .io_out_bits_metaWen                        (_lowArb_io_out_bits_metaWen),
+    .io_out_bits_tagWen                         (_lowArb_io_out_bits_tagWen),
+    .io_out_bits_dsWen                          (_lowArb_io_out_bits_dsWen),
+    .io_out_bits_replTask                       (_lowArb_io_out_bits_replTask),
+    .io_out_bits_cmoTask                        (_lowArb_io_out_bits_cmoTask),
+    .io_out_bits_reqSource                      (_lowArb_io_out_bits_reqSource),
+    .io_out_bits_mergeA                         (_lowArb_io_out_bits_mergeA),
+    .io_out_bits_aMergeTask_off                 (_lowArb_io_out_bits_aMergeTask_off),
+    .io_out_bits_aMergeTask_alias               (_lowArb_io_out_bits_aMergeTask_alias),
+    .io_out_bits_aMergeTask_vaddr               (_lowArb_io_out_bits_aMergeTask_vaddr),
+    .io_out_bits_aMergeTask_isKeyword
+      (_lowArb_io_out_bits_aMergeTask_isKeyword),
+    .io_out_bits_aMergeTask_opcode              (_lowArb_io_out_bits_aMergeTask_opcode),
+    .io_out_bits_aMergeTask_param               (_lowArb_io_out_bits_aMergeTask_param),
+    .io_out_bits_aMergeTask_sourceId            (_lowArb_io_out_bits_aMergeTask_sourceId),
+    .io_out_bits_aMergeTask_meta_dirty
+      (_lowArb_io_out_bits_aMergeTask_meta_dirty),
+    .io_out_bits_aMergeTask_meta_state
+      (_lowArb_io_out_bits_aMergeTask_meta_state),
+    .io_out_bits_aMergeTask_meta_clients
+      (_lowArb_io_out_bits_aMergeTask_meta_clients),
+    .io_out_bits_aMergeTask_meta_alias
+      (_lowArb_io_out_bits_aMergeTask_meta_alias),
+    .io_out_bits_aMergeTask_meta_accessed
+      (_lowArb_io_out_bits_aMergeTask_meta_accessed),
+    .io_out_bits_snpHitRelease                  (_lowArb_io_out_bits_snpHitRelease),
+    .io_out_bits_snpHitReleaseToInval
+      (_lowArb_io_out_bits_snpHitReleaseToInval),
+    .io_out_bits_snpHitReleaseToClean
+      (_lowArb_io_out_bits_snpHitReleaseToClean),
+    .io_out_bits_snpHitReleaseWithData
+      (_lowArb_io_out_bits_snpHitReleaseWithData),
+    .io_out_bits_snpHitReleaseIdx               (_lowArb_io_out_bits_snpHitReleaseIdx),
+    .io_out_bits_snpHitReleaseMeta_dirty
+      (_lowArb_io_out_bits_snpHitReleaseMeta_dirty),
+    .io_out_bits_snpHitReleaseMeta_state
+      (_lowArb_io_out_bits_snpHitReleaseMeta_state),
+    .io_out_bits_snpHitReleaseMeta_clients
+      (_lowArb_io_out_bits_snpHitReleaseMeta_clients),
+    .io_out_bits_snpHitReleaseMeta_alias
+      (_lowArb_io_out_bits_snpHitReleaseMeta_alias),
+    .io_out_bits_snpHitReleaseMeta_prefetch
+      (_lowArb_io_out_bits_snpHitReleaseMeta_prefetch),
+    .io_out_bits_snpHitReleaseMeta_prefetchSrc
+      (_lowArb_io_out_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_out_bits_snpHitReleaseMeta_accessed
+      (_lowArb_io_out_bits_snpHitReleaseMeta_accessed),
+    .io_out_bits_snpHitReleaseMeta_tagErr
+      (_lowArb_io_out_bits_snpHitReleaseMeta_tagErr),
+    .io_out_bits_snpHitReleaseMeta_dataErr
+      (_lowArb_io_out_bits_snpHitReleaseMeta_dataErr),
+    .io_out_bits_tgtID                          (_lowArb_io_out_bits_tgtID),
+    .io_out_bits_txnID                          (_lowArb_io_out_bits_txnID),
+    .io_out_bits_homeNID                        (_lowArb_io_out_bits_homeNID),
+    .io_out_bits_dbID                           (_lowArb_io_out_bits_dbID),
+    .io_out_bits_chiOpcode                      (_lowArb_io_out_bits_chiOpcode),
+    .io_out_bits_resp                           (_lowArb_io_out_bits_resp),
+    .io_out_bits_fwdState                       (_lowArb_io_out_bits_fwdState),
+    .io_out_bits_retToSrc                       (_lowArb_io_out_bits_retToSrc),
+    .io_out_bits_likelyshared                   (_lowArb_io_out_bits_likelyshared),
+    .io_out_bits_expCompAck                     (_lowArb_io_out_bits_expCompAck),
+    .io_out_bits_allowRetry                     (_lowArb_io_out_bits_allowRetry),
+    .io_out_bits_memAttr_allocate               (_lowArb_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable              (_lowArb_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_ewa                    (_lowArb_io_out_bits_memAttr_ewa),
+    .io_out_bits_traceTag                       (_lowArb_io_out_bits_traceTag),
+    .io_chosenOH                                (_lowArb_io_chosenOH)
+  );
+  FastArbiter_22 highArb (
+    .clock                                      (clock),
+    .reset                                      (reset),
+    .io_in_0_ready                              (io_in_8_ready),
+    .io_in_0_valid                              (io_in_8_valid),
+    .io_in_0_bits_channel                       (io_in_8_bits_channel),
+    .io_in_0_bits_txChannel                     (io_in_8_bits_txChannel),
+    .io_in_0_bits_set                           (io_in_8_bits_set),
+    .io_in_0_bits_tag                           (io_in_8_bits_tag),
+    .io_in_0_bits_off                           (io_in_8_bits_off),
+    .io_in_0_bits_alias                         (io_in_8_bits_alias),
+    .io_in_0_bits_isKeyword                     (io_in_8_bits_isKeyword),
+    .io_in_0_bits_opcode                        (io_in_8_bits_opcode),
+    .io_in_0_bits_param                         (io_in_8_bits_param),
+    .io_in_0_bits_size                          (io_in_8_bits_size),
+    .io_in_0_bits_sourceId                      (io_in_8_bits_sourceId),
+    .io_in_0_bits_denied                        (io_in_8_bits_denied),
+    .io_in_0_bits_corrupt                       (io_in_8_bits_corrupt),
+    .io_in_0_bits_aliasTask                     (io_in_8_bits_aliasTask),
+    .io_in_0_bits_useProbeData                  (io_in_8_bits_useProbeData),
+    .io_in_0_bits_mshrRetry                     (io_in_8_bits_mshrRetry),
+    .io_in_0_bits_readProbeDataDown             (io_in_8_bits_readProbeDataDown),
+    .io_in_0_bits_fromL2pft                     (io_in_8_bits_fromL2pft),
+    .io_in_0_bits_dirty                         (io_in_8_bits_dirty),
+    .io_in_0_bits_way                           (io_in_8_bits_way),
+    .io_in_0_bits_meta_dirty                    (io_in_8_bits_meta_dirty),
+    .io_in_0_bits_meta_state                    (io_in_8_bits_meta_state),
+    .io_in_0_bits_meta_clients                  (io_in_8_bits_meta_clients),
+    .io_in_0_bits_meta_alias                    (io_in_8_bits_meta_alias),
+    .io_in_0_bits_meta_prefetch                 (io_in_8_bits_meta_prefetch),
+    .io_in_0_bits_meta_prefetchSrc              (io_in_8_bits_meta_prefetchSrc),
+    .io_in_0_bits_meta_accessed                 (io_in_8_bits_meta_accessed),
+    .io_in_0_bits_meta_tagErr                   (io_in_8_bits_meta_tagErr),
+    .io_in_0_bits_meta_dataErr                  (io_in_8_bits_meta_dataErr),
+    .io_in_0_bits_metaWen                       (io_in_8_bits_metaWen),
+    .io_in_0_bits_tagWen                        (io_in_8_bits_tagWen),
+    .io_in_0_bits_dsWen                         (io_in_8_bits_dsWen),
+    .io_in_0_bits_replTask                      (io_in_8_bits_replTask),
+    .io_in_0_bits_cmoTask                       (io_in_8_bits_cmoTask),
+    .io_in_0_bits_reqSource                     (io_in_8_bits_reqSource),
+    .io_in_0_bits_mergeA                        (io_in_8_bits_mergeA),
+    .io_in_0_bits_aMergeTask_off                (io_in_8_bits_aMergeTask_off),
+    .io_in_0_bits_aMergeTask_alias              (io_in_8_bits_aMergeTask_alias),
+    .io_in_0_bits_aMergeTask_vaddr              (io_in_8_bits_aMergeTask_vaddr),
+    .io_in_0_bits_aMergeTask_isKeyword          (io_in_8_bits_aMergeTask_isKeyword),
+    .io_in_0_bits_aMergeTask_opcode             (io_in_8_bits_aMergeTask_opcode),
+    .io_in_0_bits_aMergeTask_param              (io_in_8_bits_aMergeTask_param),
+    .io_in_0_bits_aMergeTask_sourceId           (io_in_8_bits_aMergeTask_sourceId),
+    .io_in_0_bits_aMergeTask_meta_dirty         (io_in_8_bits_aMergeTask_meta_dirty),
+    .io_in_0_bits_aMergeTask_meta_state         (io_in_8_bits_aMergeTask_meta_state),
+    .io_in_0_bits_aMergeTask_meta_clients       (io_in_8_bits_aMergeTask_meta_clients),
+    .io_in_0_bits_aMergeTask_meta_alias         (io_in_8_bits_aMergeTask_meta_alias),
+    .io_in_0_bits_aMergeTask_meta_accessed      (io_in_8_bits_aMergeTask_meta_accessed),
+    .io_in_0_bits_snpHitRelease                 (io_in_8_bits_snpHitRelease),
+    .io_in_0_bits_snpHitReleaseToInval          (io_in_8_bits_snpHitReleaseToInval),
+    .io_in_0_bits_snpHitReleaseToClean          (io_in_8_bits_snpHitReleaseToClean),
+    .io_in_0_bits_snpHitReleaseWithData         (io_in_8_bits_snpHitReleaseWithData),
+    .io_in_0_bits_snpHitReleaseIdx              (io_in_8_bits_snpHitReleaseIdx),
+    .io_in_0_bits_snpHitReleaseMeta_dirty       (io_in_8_bits_snpHitReleaseMeta_dirty),
+    .io_in_0_bits_snpHitReleaseMeta_state       (io_in_8_bits_snpHitReleaseMeta_state),
+    .io_in_0_bits_snpHitReleaseMeta_clients     (io_in_8_bits_snpHitReleaseMeta_clients),
+    .io_in_0_bits_snpHitReleaseMeta_alias       (io_in_8_bits_snpHitReleaseMeta_alias),
+    .io_in_0_bits_snpHitReleaseMeta_prefetch    (io_in_8_bits_snpHitReleaseMeta_prefetch),
+    .io_in_0_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_8_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_0_bits_snpHitReleaseMeta_accessed    (io_in_8_bits_snpHitReleaseMeta_accessed),
+    .io_in_0_bits_snpHitReleaseMeta_tagErr      (io_in_8_bits_snpHitReleaseMeta_tagErr),
+    .io_in_0_bits_snpHitReleaseMeta_dataErr     (io_in_8_bits_snpHitReleaseMeta_dataErr),
+    .io_in_0_bits_tgtID                         (io_in_8_bits_tgtID),
+    .io_in_0_bits_txnID                         (io_in_8_bits_txnID),
+    .io_in_0_bits_homeNID                       (io_in_8_bits_homeNID),
+    .io_in_0_bits_dbID                          (io_in_8_bits_dbID),
+    .io_in_0_bits_chiOpcode                     (io_in_8_bits_chiOpcode),
+    .io_in_0_bits_resp                          (io_in_8_bits_resp),
+    .io_in_0_bits_fwdState                      (io_in_8_bits_fwdState),
+    .io_in_0_bits_retToSrc                      (io_in_8_bits_retToSrc),
+    .io_in_0_bits_likelyshared                  (io_in_8_bits_likelyshared),
+    .io_in_0_bits_expCompAck                    (io_in_8_bits_expCompAck),
+    .io_in_0_bits_allowRetry                    (io_in_8_bits_allowRetry),
+    .io_in_0_bits_memAttr_allocate              (io_in_8_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable             (io_in_8_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_ewa                   (io_in_8_bits_memAttr_ewa),
+    .io_in_0_bits_traceTag                      (io_in_8_bits_traceTag),
+    .io_in_1_ready                              (io_in_9_ready),
+    .io_in_1_valid                              (io_in_9_valid),
+    .io_in_1_bits_channel                       (io_in_9_bits_channel),
+    .io_in_1_bits_txChannel                     (io_in_9_bits_txChannel),
+    .io_in_1_bits_set                           (io_in_9_bits_set),
+    .io_in_1_bits_tag                           (io_in_9_bits_tag),
+    .io_in_1_bits_off                           (io_in_9_bits_off),
+    .io_in_1_bits_alias                         (io_in_9_bits_alias),
+    .io_in_1_bits_isKeyword                     (io_in_9_bits_isKeyword),
+    .io_in_1_bits_opcode                        (io_in_9_bits_opcode),
+    .io_in_1_bits_param                         (io_in_9_bits_param),
+    .io_in_1_bits_size                          (io_in_9_bits_size),
+    .io_in_1_bits_sourceId                      (io_in_9_bits_sourceId),
+    .io_in_1_bits_denied                        (io_in_9_bits_denied),
+    .io_in_1_bits_corrupt                       (io_in_9_bits_corrupt),
+    .io_in_1_bits_aliasTask                     (io_in_9_bits_aliasTask),
+    .io_in_1_bits_useProbeData                  (io_in_9_bits_useProbeData),
+    .io_in_1_bits_mshrRetry                     (io_in_9_bits_mshrRetry),
+    .io_in_1_bits_readProbeDataDown             (io_in_9_bits_readProbeDataDown),
+    .io_in_1_bits_fromL2pft                     (io_in_9_bits_fromL2pft),
+    .io_in_1_bits_dirty                         (io_in_9_bits_dirty),
+    .io_in_1_bits_way                           (io_in_9_bits_way),
+    .io_in_1_bits_meta_dirty                    (io_in_9_bits_meta_dirty),
+    .io_in_1_bits_meta_state                    (io_in_9_bits_meta_state),
+    .io_in_1_bits_meta_clients                  (io_in_9_bits_meta_clients),
+    .io_in_1_bits_meta_alias                    (io_in_9_bits_meta_alias),
+    .io_in_1_bits_meta_prefetch                 (io_in_9_bits_meta_prefetch),
+    .io_in_1_bits_meta_prefetchSrc              (io_in_9_bits_meta_prefetchSrc),
+    .io_in_1_bits_meta_accessed                 (io_in_9_bits_meta_accessed),
+    .io_in_1_bits_meta_tagErr                   (io_in_9_bits_meta_tagErr),
+    .io_in_1_bits_meta_dataErr                  (io_in_9_bits_meta_dataErr),
+    .io_in_1_bits_metaWen                       (io_in_9_bits_metaWen),
+    .io_in_1_bits_tagWen                        (io_in_9_bits_tagWen),
+    .io_in_1_bits_dsWen                         (io_in_9_bits_dsWen),
+    .io_in_1_bits_replTask                      (io_in_9_bits_replTask),
+    .io_in_1_bits_cmoTask                       (io_in_9_bits_cmoTask),
+    .io_in_1_bits_reqSource                     (io_in_9_bits_reqSource),
+    .io_in_1_bits_mergeA                        (io_in_9_bits_mergeA),
+    .io_in_1_bits_aMergeTask_off                (io_in_9_bits_aMergeTask_off),
+    .io_in_1_bits_aMergeTask_alias              (io_in_9_bits_aMergeTask_alias),
+    .io_in_1_bits_aMergeTask_vaddr              (io_in_9_bits_aMergeTask_vaddr),
+    .io_in_1_bits_aMergeTask_isKeyword          (io_in_9_bits_aMergeTask_isKeyword),
+    .io_in_1_bits_aMergeTask_opcode             (io_in_9_bits_aMergeTask_opcode),
+    .io_in_1_bits_aMergeTask_param              (io_in_9_bits_aMergeTask_param),
+    .io_in_1_bits_aMergeTask_sourceId           (io_in_9_bits_aMergeTask_sourceId),
+    .io_in_1_bits_aMergeTask_meta_dirty         (io_in_9_bits_aMergeTask_meta_dirty),
+    .io_in_1_bits_aMergeTask_meta_state         (io_in_9_bits_aMergeTask_meta_state),
+    .io_in_1_bits_aMergeTask_meta_clients       (io_in_9_bits_aMergeTask_meta_clients),
+    .io_in_1_bits_aMergeTask_meta_alias         (io_in_9_bits_aMergeTask_meta_alias),
+    .io_in_1_bits_aMergeTask_meta_accessed      (io_in_9_bits_aMergeTask_meta_accessed),
+    .io_in_1_bits_snpHitRelease                 (io_in_9_bits_snpHitRelease),
+    .io_in_1_bits_snpHitReleaseToInval          (io_in_9_bits_snpHitReleaseToInval),
+    .io_in_1_bits_snpHitReleaseToClean          (io_in_9_bits_snpHitReleaseToClean),
+    .io_in_1_bits_snpHitReleaseWithData         (io_in_9_bits_snpHitReleaseWithData),
+    .io_in_1_bits_snpHitReleaseIdx              (io_in_9_bits_snpHitReleaseIdx),
+    .io_in_1_bits_snpHitReleaseMeta_dirty       (io_in_9_bits_snpHitReleaseMeta_dirty),
+    .io_in_1_bits_snpHitReleaseMeta_state       (io_in_9_bits_snpHitReleaseMeta_state),
+    .io_in_1_bits_snpHitReleaseMeta_clients     (io_in_9_bits_snpHitReleaseMeta_clients),
+    .io_in_1_bits_snpHitReleaseMeta_alias       (io_in_9_bits_snpHitReleaseMeta_alias),
+    .io_in_1_bits_snpHitReleaseMeta_prefetch    (io_in_9_bits_snpHitReleaseMeta_prefetch),
+    .io_in_1_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_9_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_1_bits_snpHitReleaseMeta_accessed    (io_in_9_bits_snpHitReleaseMeta_accessed),
+    .io_in_1_bits_snpHitReleaseMeta_tagErr      (io_in_9_bits_snpHitReleaseMeta_tagErr),
+    .io_in_1_bits_snpHitReleaseMeta_dataErr     (io_in_9_bits_snpHitReleaseMeta_dataErr),
+    .io_in_1_bits_tgtID                         (io_in_9_bits_tgtID),
+    .io_in_1_bits_txnID                         (io_in_9_bits_txnID),
+    .io_in_1_bits_homeNID                       (io_in_9_bits_homeNID),
+    .io_in_1_bits_dbID                          (io_in_9_bits_dbID),
+    .io_in_1_bits_chiOpcode                     (io_in_9_bits_chiOpcode),
+    .io_in_1_bits_resp                          (io_in_9_bits_resp),
+    .io_in_1_bits_fwdState                      (io_in_9_bits_fwdState),
+    .io_in_1_bits_retToSrc                      (io_in_9_bits_retToSrc),
+    .io_in_1_bits_likelyshared                  (io_in_9_bits_likelyshared),
+    .io_in_1_bits_expCompAck                    (io_in_9_bits_expCompAck),
+    .io_in_1_bits_allowRetry                    (io_in_9_bits_allowRetry),
+    .io_in_1_bits_memAttr_allocate              (io_in_9_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable             (io_in_9_bits_memAttr_cacheable),
+    .io_in_1_bits_memAttr_ewa                   (io_in_9_bits_memAttr_ewa),
+    .io_in_1_bits_traceTag                      (io_in_9_bits_traceTag),
+    .io_in_2_ready                              (io_in_10_ready),
+    .io_in_2_valid                              (io_in_10_valid),
+    .io_in_2_bits_channel                       (io_in_10_bits_channel),
+    .io_in_2_bits_txChannel                     (io_in_10_bits_txChannel),
+    .io_in_2_bits_set                           (io_in_10_bits_set),
+    .io_in_2_bits_tag                           (io_in_10_bits_tag),
+    .io_in_2_bits_off                           (io_in_10_bits_off),
+    .io_in_2_bits_alias                         (io_in_10_bits_alias),
+    .io_in_2_bits_isKeyword                     (io_in_10_bits_isKeyword),
+    .io_in_2_bits_opcode                        (io_in_10_bits_opcode),
+    .io_in_2_bits_param                         (io_in_10_bits_param),
+    .io_in_2_bits_size                          (io_in_10_bits_size),
+    .io_in_2_bits_sourceId                      (io_in_10_bits_sourceId),
+    .io_in_2_bits_denied                        (io_in_10_bits_denied),
+    .io_in_2_bits_corrupt                       (io_in_10_bits_corrupt),
+    .io_in_2_bits_aliasTask                     (io_in_10_bits_aliasTask),
+    .io_in_2_bits_useProbeData                  (io_in_10_bits_useProbeData),
+    .io_in_2_bits_mshrRetry                     (io_in_10_bits_mshrRetry),
+    .io_in_2_bits_readProbeDataDown             (io_in_10_bits_readProbeDataDown),
+    .io_in_2_bits_fromL2pft                     (io_in_10_bits_fromL2pft),
+    .io_in_2_bits_dirty                         (io_in_10_bits_dirty),
+    .io_in_2_bits_way                           (io_in_10_bits_way),
+    .io_in_2_bits_meta_dirty                    (io_in_10_bits_meta_dirty),
+    .io_in_2_bits_meta_state                    (io_in_10_bits_meta_state),
+    .io_in_2_bits_meta_clients                  (io_in_10_bits_meta_clients),
+    .io_in_2_bits_meta_alias                    (io_in_10_bits_meta_alias),
+    .io_in_2_bits_meta_prefetch                 (io_in_10_bits_meta_prefetch),
+    .io_in_2_bits_meta_prefetchSrc              (io_in_10_bits_meta_prefetchSrc),
+    .io_in_2_bits_meta_accessed                 (io_in_10_bits_meta_accessed),
+    .io_in_2_bits_meta_tagErr                   (io_in_10_bits_meta_tagErr),
+    .io_in_2_bits_meta_dataErr                  (io_in_10_bits_meta_dataErr),
+    .io_in_2_bits_metaWen                       (io_in_10_bits_metaWen),
+    .io_in_2_bits_tagWen                        (io_in_10_bits_tagWen),
+    .io_in_2_bits_dsWen                         (io_in_10_bits_dsWen),
+    .io_in_2_bits_replTask                      (io_in_10_bits_replTask),
+    .io_in_2_bits_cmoTask                       (io_in_10_bits_cmoTask),
+    .io_in_2_bits_reqSource                     (io_in_10_bits_reqSource),
+    .io_in_2_bits_mergeA                        (io_in_10_bits_mergeA),
+    .io_in_2_bits_aMergeTask_off                (io_in_10_bits_aMergeTask_off),
+    .io_in_2_bits_aMergeTask_alias              (io_in_10_bits_aMergeTask_alias),
+    .io_in_2_bits_aMergeTask_vaddr              (io_in_10_bits_aMergeTask_vaddr),
+    .io_in_2_bits_aMergeTask_isKeyword          (io_in_10_bits_aMergeTask_isKeyword),
+    .io_in_2_bits_aMergeTask_opcode             (io_in_10_bits_aMergeTask_opcode),
+    .io_in_2_bits_aMergeTask_param              (io_in_10_bits_aMergeTask_param),
+    .io_in_2_bits_aMergeTask_sourceId           (io_in_10_bits_aMergeTask_sourceId),
+    .io_in_2_bits_aMergeTask_meta_dirty         (io_in_10_bits_aMergeTask_meta_dirty),
+    .io_in_2_bits_aMergeTask_meta_state         (io_in_10_bits_aMergeTask_meta_state),
+    .io_in_2_bits_aMergeTask_meta_clients       (io_in_10_bits_aMergeTask_meta_clients),
+    .io_in_2_bits_aMergeTask_meta_alias         (io_in_10_bits_aMergeTask_meta_alias),
+    .io_in_2_bits_aMergeTask_meta_accessed      (io_in_10_bits_aMergeTask_meta_accessed),
+    .io_in_2_bits_snpHitRelease                 (io_in_10_bits_snpHitRelease),
+    .io_in_2_bits_snpHitReleaseToInval          (io_in_10_bits_snpHitReleaseToInval),
+    .io_in_2_bits_snpHitReleaseToClean          (io_in_10_bits_snpHitReleaseToClean),
+    .io_in_2_bits_snpHitReleaseWithData         (io_in_10_bits_snpHitReleaseWithData),
+    .io_in_2_bits_snpHitReleaseIdx              (io_in_10_bits_snpHitReleaseIdx),
+    .io_in_2_bits_snpHitReleaseMeta_dirty       (io_in_10_bits_snpHitReleaseMeta_dirty),
+    .io_in_2_bits_snpHitReleaseMeta_state       (io_in_10_bits_snpHitReleaseMeta_state),
+    .io_in_2_bits_snpHitReleaseMeta_clients     (io_in_10_bits_snpHitReleaseMeta_clients),
+    .io_in_2_bits_snpHitReleaseMeta_alias       (io_in_10_bits_snpHitReleaseMeta_alias),
+    .io_in_2_bits_snpHitReleaseMeta_prefetch
+      (io_in_10_bits_snpHitReleaseMeta_prefetch),
+    .io_in_2_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_10_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_2_bits_snpHitReleaseMeta_accessed
+      (io_in_10_bits_snpHitReleaseMeta_accessed),
+    .io_in_2_bits_snpHitReleaseMeta_tagErr      (io_in_10_bits_snpHitReleaseMeta_tagErr),
+    .io_in_2_bits_snpHitReleaseMeta_dataErr     (io_in_10_bits_snpHitReleaseMeta_dataErr),
+    .io_in_2_bits_tgtID                         (io_in_10_bits_tgtID),
+    .io_in_2_bits_txnID                         (io_in_10_bits_txnID),
+    .io_in_2_bits_homeNID                       (io_in_10_bits_homeNID),
+    .io_in_2_bits_dbID                          (io_in_10_bits_dbID),
+    .io_in_2_bits_chiOpcode                     (io_in_10_bits_chiOpcode),
+    .io_in_2_bits_resp                          (io_in_10_bits_resp),
+    .io_in_2_bits_fwdState                      (io_in_10_bits_fwdState),
+    .io_in_2_bits_retToSrc                      (io_in_10_bits_retToSrc),
+    .io_in_2_bits_likelyshared                  (io_in_10_bits_likelyshared),
+    .io_in_2_bits_expCompAck                    (io_in_10_bits_expCompAck),
+    .io_in_2_bits_allowRetry                    (io_in_10_bits_allowRetry),
+    .io_in_2_bits_memAttr_allocate              (io_in_10_bits_memAttr_allocate),
+    .io_in_2_bits_memAttr_cacheable             (io_in_10_bits_memAttr_cacheable),
+    .io_in_2_bits_memAttr_ewa                   (io_in_10_bits_memAttr_ewa),
+    .io_in_2_bits_traceTag                      (io_in_10_bits_traceTag),
+    .io_in_3_ready                              (io_in_11_ready),
+    .io_in_3_valid                              (io_in_11_valid),
+    .io_in_3_bits_channel                       (io_in_11_bits_channel),
+    .io_in_3_bits_txChannel                     (io_in_11_bits_txChannel),
+    .io_in_3_bits_set                           (io_in_11_bits_set),
+    .io_in_3_bits_tag                           (io_in_11_bits_tag),
+    .io_in_3_bits_off                           (io_in_11_bits_off),
+    .io_in_3_bits_alias                         (io_in_11_bits_alias),
+    .io_in_3_bits_isKeyword                     (io_in_11_bits_isKeyword),
+    .io_in_3_bits_opcode                        (io_in_11_bits_opcode),
+    .io_in_3_bits_param                         (io_in_11_bits_param),
+    .io_in_3_bits_size                          (io_in_11_bits_size),
+    .io_in_3_bits_sourceId                      (io_in_11_bits_sourceId),
+    .io_in_3_bits_denied                        (io_in_11_bits_denied),
+    .io_in_3_bits_corrupt                       (io_in_11_bits_corrupt),
+    .io_in_3_bits_aliasTask                     (io_in_11_bits_aliasTask),
+    .io_in_3_bits_useProbeData                  (io_in_11_bits_useProbeData),
+    .io_in_3_bits_mshrRetry                     (io_in_11_bits_mshrRetry),
+    .io_in_3_bits_readProbeDataDown             (io_in_11_bits_readProbeDataDown),
+    .io_in_3_bits_fromL2pft                     (io_in_11_bits_fromL2pft),
+    .io_in_3_bits_dirty                         (io_in_11_bits_dirty),
+    .io_in_3_bits_way                           (io_in_11_bits_way),
+    .io_in_3_bits_meta_dirty                    (io_in_11_bits_meta_dirty),
+    .io_in_3_bits_meta_state                    (io_in_11_bits_meta_state),
+    .io_in_3_bits_meta_clients                  (io_in_11_bits_meta_clients),
+    .io_in_3_bits_meta_alias                    (io_in_11_bits_meta_alias),
+    .io_in_3_bits_meta_prefetch                 (io_in_11_bits_meta_prefetch),
+    .io_in_3_bits_meta_prefetchSrc              (io_in_11_bits_meta_prefetchSrc),
+    .io_in_3_bits_meta_accessed                 (io_in_11_bits_meta_accessed),
+    .io_in_3_bits_meta_tagErr                   (io_in_11_bits_meta_tagErr),
+    .io_in_3_bits_meta_dataErr                  (io_in_11_bits_meta_dataErr),
+    .io_in_3_bits_metaWen                       (io_in_11_bits_metaWen),
+    .io_in_3_bits_tagWen                        (io_in_11_bits_tagWen),
+    .io_in_3_bits_dsWen                         (io_in_11_bits_dsWen),
+    .io_in_3_bits_replTask                      (io_in_11_bits_replTask),
+    .io_in_3_bits_cmoTask                       (io_in_11_bits_cmoTask),
+    .io_in_3_bits_reqSource                     (io_in_11_bits_reqSource),
+    .io_in_3_bits_mergeA                        (io_in_11_bits_mergeA),
+    .io_in_3_bits_aMergeTask_off                (io_in_11_bits_aMergeTask_off),
+    .io_in_3_bits_aMergeTask_alias              (io_in_11_bits_aMergeTask_alias),
+    .io_in_3_bits_aMergeTask_vaddr              (io_in_11_bits_aMergeTask_vaddr),
+    .io_in_3_bits_aMergeTask_isKeyword          (io_in_11_bits_aMergeTask_isKeyword),
+    .io_in_3_bits_aMergeTask_opcode             (io_in_11_bits_aMergeTask_opcode),
+    .io_in_3_bits_aMergeTask_param              (io_in_11_bits_aMergeTask_param),
+    .io_in_3_bits_aMergeTask_sourceId           (io_in_11_bits_aMergeTask_sourceId),
+    .io_in_3_bits_aMergeTask_meta_dirty         (io_in_11_bits_aMergeTask_meta_dirty),
+    .io_in_3_bits_aMergeTask_meta_state         (io_in_11_bits_aMergeTask_meta_state),
+    .io_in_3_bits_aMergeTask_meta_clients       (io_in_11_bits_aMergeTask_meta_clients),
+    .io_in_3_bits_aMergeTask_meta_alias         (io_in_11_bits_aMergeTask_meta_alias),
+    .io_in_3_bits_aMergeTask_meta_accessed      (io_in_11_bits_aMergeTask_meta_accessed),
+    .io_in_3_bits_snpHitRelease                 (io_in_11_bits_snpHitRelease),
+    .io_in_3_bits_snpHitReleaseToInval          (io_in_11_bits_snpHitReleaseToInval),
+    .io_in_3_bits_snpHitReleaseToClean          (io_in_11_bits_snpHitReleaseToClean),
+    .io_in_3_bits_snpHitReleaseWithData         (io_in_11_bits_snpHitReleaseWithData),
+    .io_in_3_bits_snpHitReleaseIdx              (io_in_11_bits_snpHitReleaseIdx),
+    .io_in_3_bits_snpHitReleaseMeta_dirty       (io_in_11_bits_snpHitReleaseMeta_dirty),
+    .io_in_3_bits_snpHitReleaseMeta_state       (io_in_11_bits_snpHitReleaseMeta_state),
+    .io_in_3_bits_snpHitReleaseMeta_clients     (io_in_11_bits_snpHitReleaseMeta_clients),
+    .io_in_3_bits_snpHitReleaseMeta_alias       (io_in_11_bits_snpHitReleaseMeta_alias),
+    .io_in_3_bits_snpHitReleaseMeta_prefetch
+      (io_in_11_bits_snpHitReleaseMeta_prefetch),
+    .io_in_3_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_11_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_3_bits_snpHitReleaseMeta_accessed
+      (io_in_11_bits_snpHitReleaseMeta_accessed),
+    .io_in_3_bits_snpHitReleaseMeta_tagErr      (io_in_11_bits_snpHitReleaseMeta_tagErr),
+    .io_in_3_bits_snpHitReleaseMeta_dataErr     (io_in_11_bits_snpHitReleaseMeta_dataErr),
+    .io_in_3_bits_tgtID                         (io_in_11_bits_tgtID),
+    .io_in_3_bits_txnID                         (io_in_11_bits_txnID),
+    .io_in_3_bits_homeNID                       (io_in_11_bits_homeNID),
+    .io_in_3_bits_dbID                          (io_in_11_bits_dbID),
+    .io_in_3_bits_chiOpcode                     (io_in_11_bits_chiOpcode),
+    .io_in_3_bits_resp                          (io_in_11_bits_resp),
+    .io_in_3_bits_fwdState                      (io_in_11_bits_fwdState),
+    .io_in_3_bits_retToSrc                      (io_in_11_bits_retToSrc),
+    .io_in_3_bits_likelyshared                  (io_in_11_bits_likelyshared),
+    .io_in_3_bits_expCompAck                    (io_in_11_bits_expCompAck),
+    .io_in_3_bits_allowRetry                    (io_in_11_bits_allowRetry),
+    .io_in_3_bits_memAttr_allocate              (io_in_11_bits_memAttr_allocate),
+    .io_in_3_bits_memAttr_cacheable             (io_in_11_bits_memAttr_cacheable),
+    .io_in_3_bits_memAttr_ewa                   (io_in_11_bits_memAttr_ewa),
+    .io_in_3_bits_traceTag                      (io_in_11_bits_traceTag),
+    .io_in_4_ready                              (io_in_12_ready),
+    .io_in_4_valid                              (io_in_12_valid),
+    .io_in_4_bits_channel                       (io_in_12_bits_channel),
+    .io_in_4_bits_txChannel                     (io_in_12_bits_txChannel),
+    .io_in_4_bits_set                           (io_in_12_bits_set),
+    .io_in_4_bits_tag                           (io_in_12_bits_tag),
+    .io_in_4_bits_off                           (io_in_12_bits_off),
+    .io_in_4_bits_alias                         (io_in_12_bits_alias),
+    .io_in_4_bits_isKeyword                     (io_in_12_bits_isKeyword),
+    .io_in_4_bits_opcode                        (io_in_12_bits_opcode),
+    .io_in_4_bits_param                         (io_in_12_bits_param),
+    .io_in_4_bits_size                          (io_in_12_bits_size),
+    .io_in_4_bits_sourceId                      (io_in_12_bits_sourceId),
+    .io_in_4_bits_denied                        (io_in_12_bits_denied),
+    .io_in_4_bits_corrupt                       (io_in_12_bits_corrupt),
+    .io_in_4_bits_aliasTask                     (io_in_12_bits_aliasTask),
+    .io_in_4_bits_useProbeData                  (io_in_12_bits_useProbeData),
+    .io_in_4_bits_mshrRetry                     (io_in_12_bits_mshrRetry),
+    .io_in_4_bits_readProbeDataDown             (io_in_12_bits_readProbeDataDown),
+    .io_in_4_bits_fromL2pft                     (io_in_12_bits_fromL2pft),
+    .io_in_4_bits_dirty                         (io_in_12_bits_dirty),
+    .io_in_4_bits_way                           (io_in_12_bits_way),
+    .io_in_4_bits_meta_dirty                    (io_in_12_bits_meta_dirty),
+    .io_in_4_bits_meta_state                    (io_in_12_bits_meta_state),
+    .io_in_4_bits_meta_clients                  (io_in_12_bits_meta_clients),
+    .io_in_4_bits_meta_alias                    (io_in_12_bits_meta_alias),
+    .io_in_4_bits_meta_prefetch                 (io_in_12_bits_meta_prefetch),
+    .io_in_4_bits_meta_prefetchSrc              (io_in_12_bits_meta_prefetchSrc),
+    .io_in_4_bits_meta_accessed                 (io_in_12_bits_meta_accessed),
+    .io_in_4_bits_meta_tagErr                   (io_in_12_bits_meta_tagErr),
+    .io_in_4_bits_meta_dataErr                  (io_in_12_bits_meta_dataErr),
+    .io_in_4_bits_metaWen                       (io_in_12_bits_metaWen),
+    .io_in_4_bits_tagWen                        (io_in_12_bits_tagWen),
+    .io_in_4_bits_dsWen                         (io_in_12_bits_dsWen),
+    .io_in_4_bits_replTask                      (io_in_12_bits_replTask),
+    .io_in_4_bits_cmoTask                       (io_in_12_bits_cmoTask),
+    .io_in_4_bits_reqSource                     (io_in_12_bits_reqSource),
+    .io_in_4_bits_mergeA                        (io_in_12_bits_mergeA),
+    .io_in_4_bits_aMergeTask_off                (io_in_12_bits_aMergeTask_off),
+    .io_in_4_bits_aMergeTask_alias              (io_in_12_bits_aMergeTask_alias),
+    .io_in_4_bits_aMergeTask_vaddr              (io_in_12_bits_aMergeTask_vaddr),
+    .io_in_4_bits_aMergeTask_isKeyword          (io_in_12_bits_aMergeTask_isKeyword),
+    .io_in_4_bits_aMergeTask_opcode             (io_in_12_bits_aMergeTask_opcode),
+    .io_in_4_bits_aMergeTask_param              (io_in_12_bits_aMergeTask_param),
+    .io_in_4_bits_aMergeTask_sourceId           (io_in_12_bits_aMergeTask_sourceId),
+    .io_in_4_bits_aMergeTask_meta_dirty         (io_in_12_bits_aMergeTask_meta_dirty),
+    .io_in_4_bits_aMergeTask_meta_state         (io_in_12_bits_aMergeTask_meta_state),
+    .io_in_4_bits_aMergeTask_meta_clients       (io_in_12_bits_aMergeTask_meta_clients),
+    .io_in_4_bits_aMergeTask_meta_alias         (io_in_12_bits_aMergeTask_meta_alias),
+    .io_in_4_bits_aMergeTask_meta_accessed      (io_in_12_bits_aMergeTask_meta_accessed),
+    .io_in_4_bits_snpHitRelease                 (io_in_12_bits_snpHitRelease),
+    .io_in_4_bits_snpHitReleaseToInval          (io_in_12_bits_snpHitReleaseToInval),
+    .io_in_4_bits_snpHitReleaseToClean          (io_in_12_bits_snpHitReleaseToClean),
+    .io_in_4_bits_snpHitReleaseWithData         (io_in_12_bits_snpHitReleaseWithData),
+    .io_in_4_bits_snpHitReleaseIdx              (io_in_12_bits_snpHitReleaseIdx),
+    .io_in_4_bits_snpHitReleaseMeta_dirty       (io_in_12_bits_snpHitReleaseMeta_dirty),
+    .io_in_4_bits_snpHitReleaseMeta_state       (io_in_12_bits_snpHitReleaseMeta_state),
+    .io_in_4_bits_snpHitReleaseMeta_clients     (io_in_12_bits_snpHitReleaseMeta_clients),
+    .io_in_4_bits_snpHitReleaseMeta_alias       (io_in_12_bits_snpHitReleaseMeta_alias),
+    .io_in_4_bits_snpHitReleaseMeta_prefetch
+      (io_in_12_bits_snpHitReleaseMeta_prefetch),
+    .io_in_4_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_12_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_4_bits_snpHitReleaseMeta_accessed
+      (io_in_12_bits_snpHitReleaseMeta_accessed),
+    .io_in_4_bits_snpHitReleaseMeta_tagErr      (io_in_12_bits_snpHitReleaseMeta_tagErr),
+    .io_in_4_bits_snpHitReleaseMeta_dataErr     (io_in_12_bits_snpHitReleaseMeta_dataErr),
+    .io_in_4_bits_tgtID                         (io_in_12_bits_tgtID),
+    .io_in_4_bits_txnID                         (io_in_12_bits_txnID),
+    .io_in_4_bits_homeNID                       (io_in_12_bits_homeNID),
+    .io_in_4_bits_dbID                          (io_in_12_bits_dbID),
+    .io_in_4_bits_chiOpcode                     (io_in_12_bits_chiOpcode),
+    .io_in_4_bits_resp                          (io_in_12_bits_resp),
+    .io_in_4_bits_fwdState                      (io_in_12_bits_fwdState),
+    .io_in_4_bits_retToSrc                      (io_in_12_bits_retToSrc),
+    .io_in_4_bits_likelyshared                  (io_in_12_bits_likelyshared),
+    .io_in_4_bits_expCompAck                    (io_in_12_bits_expCompAck),
+    .io_in_4_bits_allowRetry                    (io_in_12_bits_allowRetry),
+    .io_in_4_bits_memAttr_allocate              (io_in_12_bits_memAttr_allocate),
+    .io_in_4_bits_memAttr_cacheable             (io_in_12_bits_memAttr_cacheable),
+    .io_in_4_bits_memAttr_ewa                   (io_in_12_bits_memAttr_ewa),
+    .io_in_4_bits_traceTag                      (io_in_12_bits_traceTag),
+    .io_in_5_ready                              (io_in_13_ready),
+    .io_in_5_valid                              (io_in_13_valid),
+    .io_in_5_bits_channel                       (io_in_13_bits_channel),
+    .io_in_5_bits_txChannel                     (io_in_13_bits_txChannel),
+    .io_in_5_bits_set                           (io_in_13_bits_set),
+    .io_in_5_bits_tag                           (io_in_13_bits_tag),
+    .io_in_5_bits_off                           (io_in_13_bits_off),
+    .io_in_5_bits_alias                         (io_in_13_bits_alias),
+    .io_in_5_bits_isKeyword                     (io_in_13_bits_isKeyword),
+    .io_in_5_bits_opcode                        (io_in_13_bits_opcode),
+    .io_in_5_bits_param                         (io_in_13_bits_param),
+    .io_in_5_bits_size                          (io_in_13_bits_size),
+    .io_in_5_bits_sourceId                      (io_in_13_bits_sourceId),
+    .io_in_5_bits_denied                        (io_in_13_bits_denied),
+    .io_in_5_bits_corrupt                       (io_in_13_bits_corrupt),
+    .io_in_5_bits_aliasTask                     (io_in_13_bits_aliasTask),
+    .io_in_5_bits_useProbeData                  (io_in_13_bits_useProbeData),
+    .io_in_5_bits_mshrRetry                     (io_in_13_bits_mshrRetry),
+    .io_in_5_bits_readProbeDataDown             (io_in_13_bits_readProbeDataDown),
+    .io_in_5_bits_fromL2pft                     (io_in_13_bits_fromL2pft),
+    .io_in_5_bits_dirty                         (io_in_13_bits_dirty),
+    .io_in_5_bits_way                           (io_in_13_bits_way),
+    .io_in_5_bits_meta_dirty                    (io_in_13_bits_meta_dirty),
+    .io_in_5_bits_meta_state                    (io_in_13_bits_meta_state),
+    .io_in_5_bits_meta_clients                  (io_in_13_bits_meta_clients),
+    .io_in_5_bits_meta_alias                    (io_in_13_bits_meta_alias),
+    .io_in_5_bits_meta_prefetch                 (io_in_13_bits_meta_prefetch),
+    .io_in_5_bits_meta_prefetchSrc              (io_in_13_bits_meta_prefetchSrc),
+    .io_in_5_bits_meta_accessed                 (io_in_13_bits_meta_accessed),
+    .io_in_5_bits_meta_tagErr                   (io_in_13_bits_meta_tagErr),
+    .io_in_5_bits_meta_dataErr                  (io_in_13_bits_meta_dataErr),
+    .io_in_5_bits_metaWen                       (io_in_13_bits_metaWen),
+    .io_in_5_bits_tagWen                        (io_in_13_bits_tagWen),
+    .io_in_5_bits_dsWen                         (io_in_13_bits_dsWen),
+    .io_in_5_bits_replTask                      (io_in_13_bits_replTask),
+    .io_in_5_bits_cmoTask                       (io_in_13_bits_cmoTask),
+    .io_in_5_bits_reqSource                     (io_in_13_bits_reqSource),
+    .io_in_5_bits_mergeA                        (io_in_13_bits_mergeA),
+    .io_in_5_bits_aMergeTask_off                (io_in_13_bits_aMergeTask_off),
+    .io_in_5_bits_aMergeTask_alias              (io_in_13_bits_aMergeTask_alias),
+    .io_in_5_bits_aMergeTask_vaddr              (io_in_13_bits_aMergeTask_vaddr),
+    .io_in_5_bits_aMergeTask_isKeyword          (io_in_13_bits_aMergeTask_isKeyword),
+    .io_in_5_bits_aMergeTask_opcode             (io_in_13_bits_aMergeTask_opcode),
+    .io_in_5_bits_aMergeTask_param              (io_in_13_bits_aMergeTask_param),
+    .io_in_5_bits_aMergeTask_sourceId           (io_in_13_bits_aMergeTask_sourceId),
+    .io_in_5_bits_aMergeTask_meta_dirty         (io_in_13_bits_aMergeTask_meta_dirty),
+    .io_in_5_bits_aMergeTask_meta_state         (io_in_13_bits_aMergeTask_meta_state),
+    .io_in_5_bits_aMergeTask_meta_clients       (io_in_13_bits_aMergeTask_meta_clients),
+    .io_in_5_bits_aMergeTask_meta_alias         (io_in_13_bits_aMergeTask_meta_alias),
+    .io_in_5_bits_aMergeTask_meta_accessed      (io_in_13_bits_aMergeTask_meta_accessed),
+    .io_in_5_bits_snpHitRelease                 (io_in_13_bits_snpHitRelease),
+    .io_in_5_bits_snpHitReleaseToInval          (io_in_13_bits_snpHitReleaseToInval),
+    .io_in_5_bits_snpHitReleaseToClean          (io_in_13_bits_snpHitReleaseToClean),
+    .io_in_5_bits_snpHitReleaseWithData         (io_in_13_bits_snpHitReleaseWithData),
+    .io_in_5_bits_snpHitReleaseIdx              (io_in_13_bits_snpHitReleaseIdx),
+    .io_in_5_bits_snpHitReleaseMeta_dirty       (io_in_13_bits_snpHitReleaseMeta_dirty),
+    .io_in_5_bits_snpHitReleaseMeta_state       (io_in_13_bits_snpHitReleaseMeta_state),
+    .io_in_5_bits_snpHitReleaseMeta_clients     (io_in_13_bits_snpHitReleaseMeta_clients),
+    .io_in_5_bits_snpHitReleaseMeta_alias       (io_in_13_bits_snpHitReleaseMeta_alias),
+    .io_in_5_bits_snpHitReleaseMeta_prefetch
+      (io_in_13_bits_snpHitReleaseMeta_prefetch),
+    .io_in_5_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_13_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_5_bits_snpHitReleaseMeta_accessed
+      (io_in_13_bits_snpHitReleaseMeta_accessed),
+    .io_in_5_bits_snpHitReleaseMeta_tagErr      (io_in_13_bits_snpHitReleaseMeta_tagErr),
+    .io_in_5_bits_snpHitReleaseMeta_dataErr     (io_in_13_bits_snpHitReleaseMeta_dataErr),
+    .io_in_5_bits_tgtID                         (io_in_13_bits_tgtID),
+    .io_in_5_bits_txnID                         (io_in_13_bits_txnID),
+    .io_in_5_bits_homeNID                       (io_in_13_bits_homeNID),
+    .io_in_5_bits_dbID                          (io_in_13_bits_dbID),
+    .io_in_5_bits_chiOpcode                     (io_in_13_bits_chiOpcode),
+    .io_in_5_bits_resp                          (io_in_13_bits_resp),
+    .io_in_5_bits_fwdState                      (io_in_13_bits_fwdState),
+    .io_in_5_bits_retToSrc                      (io_in_13_bits_retToSrc),
+    .io_in_5_bits_likelyshared                  (io_in_13_bits_likelyshared),
+    .io_in_5_bits_expCompAck                    (io_in_13_bits_expCompAck),
+    .io_in_5_bits_allowRetry                    (io_in_13_bits_allowRetry),
+    .io_in_5_bits_memAttr_allocate              (io_in_13_bits_memAttr_allocate),
+    .io_in_5_bits_memAttr_cacheable             (io_in_13_bits_memAttr_cacheable),
+    .io_in_5_bits_memAttr_ewa                   (io_in_13_bits_memAttr_ewa),
+    .io_in_5_bits_traceTag                      (io_in_13_bits_traceTag),
+    .io_in_6_ready                              (io_in_14_ready),
+    .io_in_6_valid                              (io_in_14_valid),
+    .io_in_6_bits_channel                       (io_in_14_bits_channel),
+    .io_in_6_bits_txChannel                     (io_in_14_bits_txChannel),
+    .io_in_6_bits_set                           (io_in_14_bits_set),
+    .io_in_6_bits_tag                           (io_in_14_bits_tag),
+    .io_in_6_bits_off                           (io_in_14_bits_off),
+    .io_in_6_bits_alias                         (io_in_14_bits_alias),
+    .io_in_6_bits_isKeyword                     (io_in_14_bits_isKeyword),
+    .io_in_6_bits_opcode                        (io_in_14_bits_opcode),
+    .io_in_6_bits_param                         (io_in_14_bits_param),
+    .io_in_6_bits_size                          (io_in_14_bits_size),
+    .io_in_6_bits_sourceId                      (io_in_14_bits_sourceId),
+    .io_in_6_bits_denied                        (io_in_14_bits_denied),
+    .io_in_6_bits_corrupt                       (io_in_14_bits_corrupt),
+    .io_in_6_bits_aliasTask                     (io_in_14_bits_aliasTask),
+    .io_in_6_bits_useProbeData                  (io_in_14_bits_useProbeData),
+    .io_in_6_bits_mshrRetry                     (io_in_14_bits_mshrRetry),
+    .io_in_6_bits_readProbeDataDown             (io_in_14_bits_readProbeDataDown),
+    .io_in_6_bits_fromL2pft                     (io_in_14_bits_fromL2pft),
+    .io_in_6_bits_dirty                         (io_in_14_bits_dirty),
+    .io_in_6_bits_way                           (io_in_14_bits_way),
+    .io_in_6_bits_meta_dirty                    (io_in_14_bits_meta_dirty),
+    .io_in_6_bits_meta_state                    (io_in_14_bits_meta_state),
+    .io_in_6_bits_meta_clients                  (io_in_14_bits_meta_clients),
+    .io_in_6_bits_meta_alias                    (io_in_14_bits_meta_alias),
+    .io_in_6_bits_meta_prefetch                 (io_in_14_bits_meta_prefetch),
+    .io_in_6_bits_meta_prefetchSrc              (io_in_14_bits_meta_prefetchSrc),
+    .io_in_6_bits_meta_accessed                 (io_in_14_bits_meta_accessed),
+    .io_in_6_bits_meta_tagErr                   (io_in_14_bits_meta_tagErr),
+    .io_in_6_bits_meta_dataErr                  (io_in_14_bits_meta_dataErr),
+    .io_in_6_bits_metaWen                       (io_in_14_bits_metaWen),
+    .io_in_6_bits_tagWen                        (io_in_14_bits_tagWen),
+    .io_in_6_bits_dsWen                         (io_in_14_bits_dsWen),
+    .io_in_6_bits_replTask                      (io_in_14_bits_replTask),
+    .io_in_6_bits_cmoTask                       (io_in_14_bits_cmoTask),
+    .io_in_6_bits_reqSource                     (io_in_14_bits_reqSource),
+    .io_in_6_bits_mergeA                        (io_in_14_bits_mergeA),
+    .io_in_6_bits_aMergeTask_off                (io_in_14_bits_aMergeTask_off),
+    .io_in_6_bits_aMergeTask_alias              (io_in_14_bits_aMergeTask_alias),
+    .io_in_6_bits_aMergeTask_vaddr              (io_in_14_bits_aMergeTask_vaddr),
+    .io_in_6_bits_aMergeTask_isKeyword          (io_in_14_bits_aMergeTask_isKeyword),
+    .io_in_6_bits_aMergeTask_opcode             (io_in_14_bits_aMergeTask_opcode),
+    .io_in_6_bits_aMergeTask_param              (io_in_14_bits_aMergeTask_param),
+    .io_in_6_bits_aMergeTask_sourceId           (io_in_14_bits_aMergeTask_sourceId),
+    .io_in_6_bits_aMergeTask_meta_dirty         (io_in_14_bits_aMergeTask_meta_dirty),
+    .io_in_6_bits_aMergeTask_meta_state         (io_in_14_bits_aMergeTask_meta_state),
+    .io_in_6_bits_aMergeTask_meta_clients       (io_in_14_bits_aMergeTask_meta_clients),
+    .io_in_6_bits_aMergeTask_meta_alias         (io_in_14_bits_aMergeTask_meta_alias),
+    .io_in_6_bits_aMergeTask_meta_accessed      (io_in_14_bits_aMergeTask_meta_accessed),
+    .io_in_6_bits_snpHitRelease                 (io_in_14_bits_snpHitRelease),
+    .io_in_6_bits_snpHitReleaseToInval          (io_in_14_bits_snpHitReleaseToInval),
+    .io_in_6_bits_snpHitReleaseToClean          (io_in_14_bits_snpHitReleaseToClean),
+    .io_in_6_bits_snpHitReleaseWithData         (io_in_14_bits_snpHitReleaseWithData),
+    .io_in_6_bits_snpHitReleaseIdx              (io_in_14_bits_snpHitReleaseIdx),
+    .io_in_6_bits_snpHitReleaseMeta_dirty       (io_in_14_bits_snpHitReleaseMeta_dirty),
+    .io_in_6_bits_snpHitReleaseMeta_state       (io_in_14_bits_snpHitReleaseMeta_state),
+    .io_in_6_bits_snpHitReleaseMeta_clients     (io_in_14_bits_snpHitReleaseMeta_clients),
+    .io_in_6_bits_snpHitReleaseMeta_alias       (io_in_14_bits_snpHitReleaseMeta_alias),
+    .io_in_6_bits_snpHitReleaseMeta_prefetch
+      (io_in_14_bits_snpHitReleaseMeta_prefetch),
+    .io_in_6_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_14_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_6_bits_snpHitReleaseMeta_accessed
+      (io_in_14_bits_snpHitReleaseMeta_accessed),
+    .io_in_6_bits_snpHitReleaseMeta_tagErr      (io_in_14_bits_snpHitReleaseMeta_tagErr),
+    .io_in_6_bits_snpHitReleaseMeta_dataErr     (io_in_14_bits_snpHitReleaseMeta_dataErr),
+    .io_in_6_bits_tgtID                         (io_in_14_bits_tgtID),
+    .io_in_6_bits_txnID                         (io_in_14_bits_txnID),
+    .io_in_6_bits_homeNID                       (io_in_14_bits_homeNID),
+    .io_in_6_bits_dbID                          (io_in_14_bits_dbID),
+    .io_in_6_bits_chiOpcode                     (io_in_14_bits_chiOpcode),
+    .io_in_6_bits_resp                          (io_in_14_bits_resp),
+    .io_in_6_bits_fwdState                      (io_in_14_bits_fwdState),
+    .io_in_6_bits_retToSrc                      (io_in_14_bits_retToSrc),
+    .io_in_6_bits_likelyshared                  (io_in_14_bits_likelyshared),
+    .io_in_6_bits_expCompAck                    (io_in_14_bits_expCompAck),
+    .io_in_6_bits_allowRetry                    (io_in_14_bits_allowRetry),
+    .io_in_6_bits_memAttr_allocate              (io_in_14_bits_memAttr_allocate),
+    .io_in_6_bits_memAttr_cacheable             (io_in_14_bits_memAttr_cacheable),
+    .io_in_6_bits_memAttr_ewa                   (io_in_14_bits_memAttr_ewa),
+    .io_in_6_bits_traceTag                      (io_in_14_bits_traceTag),
+    .io_in_7_ready                              (io_in_15_ready),
+    .io_in_7_valid                              (io_in_15_valid),
+    .io_in_7_bits_channel                       (io_in_15_bits_channel),
+    .io_in_7_bits_txChannel                     (io_in_15_bits_txChannel),
+    .io_in_7_bits_set                           (io_in_15_bits_set),
+    .io_in_7_bits_tag                           (io_in_15_bits_tag),
+    .io_in_7_bits_off                           (io_in_15_bits_off),
+    .io_in_7_bits_alias                         (io_in_15_bits_alias),
+    .io_in_7_bits_isKeyword                     (io_in_15_bits_isKeyword),
+    .io_in_7_bits_opcode                        (io_in_15_bits_opcode),
+    .io_in_7_bits_param                         (io_in_15_bits_param),
+    .io_in_7_bits_size                          (io_in_15_bits_size),
+    .io_in_7_bits_sourceId                      (io_in_15_bits_sourceId),
+    .io_in_7_bits_denied                        (io_in_15_bits_denied),
+    .io_in_7_bits_corrupt                       (io_in_15_bits_corrupt),
+    .io_in_7_bits_aliasTask                     (io_in_15_bits_aliasTask),
+    .io_in_7_bits_useProbeData                  (io_in_15_bits_useProbeData),
+    .io_in_7_bits_mshrRetry                     (io_in_15_bits_mshrRetry),
+    .io_in_7_bits_readProbeDataDown             (io_in_15_bits_readProbeDataDown),
+    .io_in_7_bits_fromL2pft                     (io_in_15_bits_fromL2pft),
+    .io_in_7_bits_dirty                         (io_in_15_bits_dirty),
+    .io_in_7_bits_way                           (io_in_15_bits_way),
+    .io_in_7_bits_meta_dirty                    (io_in_15_bits_meta_dirty),
+    .io_in_7_bits_meta_state                    (io_in_15_bits_meta_state),
+    .io_in_7_bits_meta_clients                  (io_in_15_bits_meta_clients),
+    .io_in_7_bits_meta_alias                    (io_in_15_bits_meta_alias),
+    .io_in_7_bits_meta_prefetch                 (io_in_15_bits_meta_prefetch),
+    .io_in_7_bits_meta_prefetchSrc              (io_in_15_bits_meta_prefetchSrc),
+    .io_in_7_bits_meta_accessed                 (io_in_15_bits_meta_accessed),
+    .io_in_7_bits_meta_tagErr                   (io_in_15_bits_meta_tagErr),
+    .io_in_7_bits_meta_dataErr                  (io_in_15_bits_meta_dataErr),
+    .io_in_7_bits_metaWen                       (io_in_15_bits_metaWen),
+    .io_in_7_bits_tagWen                        (io_in_15_bits_tagWen),
+    .io_in_7_bits_dsWen                         (io_in_15_bits_dsWen),
+    .io_in_7_bits_replTask                      (io_in_15_bits_replTask),
+    .io_in_7_bits_cmoTask                       (io_in_15_bits_cmoTask),
+    .io_in_7_bits_reqSource                     (io_in_15_bits_reqSource),
+    .io_in_7_bits_mergeA                        (io_in_15_bits_mergeA),
+    .io_in_7_bits_aMergeTask_off                (io_in_15_bits_aMergeTask_off),
+    .io_in_7_bits_aMergeTask_alias              (io_in_15_bits_aMergeTask_alias),
+    .io_in_7_bits_aMergeTask_vaddr              (io_in_15_bits_aMergeTask_vaddr),
+    .io_in_7_bits_aMergeTask_isKeyword          (io_in_15_bits_aMergeTask_isKeyword),
+    .io_in_7_bits_aMergeTask_opcode             (io_in_15_bits_aMergeTask_opcode),
+    .io_in_7_bits_aMergeTask_param              (io_in_15_bits_aMergeTask_param),
+    .io_in_7_bits_aMergeTask_sourceId           (io_in_15_bits_aMergeTask_sourceId),
+    .io_in_7_bits_aMergeTask_meta_dirty         (io_in_15_bits_aMergeTask_meta_dirty),
+    .io_in_7_bits_aMergeTask_meta_state         (io_in_15_bits_aMergeTask_meta_state),
+    .io_in_7_bits_aMergeTask_meta_clients       (io_in_15_bits_aMergeTask_meta_clients),
+    .io_in_7_bits_aMergeTask_meta_alias         (io_in_15_bits_aMergeTask_meta_alias),
+    .io_in_7_bits_aMergeTask_meta_accessed      (io_in_15_bits_aMergeTask_meta_accessed),
+    .io_in_7_bits_snpHitRelease                 (io_in_15_bits_snpHitRelease),
+    .io_in_7_bits_snpHitReleaseToInval          (io_in_15_bits_snpHitReleaseToInval),
+    .io_in_7_bits_snpHitReleaseToClean          (io_in_15_bits_snpHitReleaseToClean),
+    .io_in_7_bits_snpHitReleaseWithData         (io_in_15_bits_snpHitReleaseWithData),
+    .io_in_7_bits_snpHitReleaseIdx              (io_in_15_bits_snpHitReleaseIdx),
+    .io_in_7_bits_snpHitReleaseMeta_dirty       (io_in_15_bits_snpHitReleaseMeta_dirty),
+    .io_in_7_bits_snpHitReleaseMeta_state       (io_in_15_bits_snpHitReleaseMeta_state),
+    .io_in_7_bits_snpHitReleaseMeta_clients     (io_in_15_bits_snpHitReleaseMeta_clients),
+    .io_in_7_bits_snpHitReleaseMeta_alias       (io_in_15_bits_snpHitReleaseMeta_alias),
+    .io_in_7_bits_snpHitReleaseMeta_prefetch
+      (io_in_15_bits_snpHitReleaseMeta_prefetch),
+    .io_in_7_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_15_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_7_bits_snpHitReleaseMeta_accessed
+      (io_in_15_bits_snpHitReleaseMeta_accessed),
+    .io_in_7_bits_snpHitReleaseMeta_tagErr      (io_in_15_bits_snpHitReleaseMeta_tagErr),
+    .io_in_7_bits_snpHitReleaseMeta_dataErr     (io_in_15_bits_snpHitReleaseMeta_dataErr),
+    .io_in_7_bits_tgtID                         (io_in_15_bits_tgtID),
+    .io_in_7_bits_txnID                         (io_in_15_bits_txnID),
+    .io_in_7_bits_homeNID                       (io_in_15_bits_homeNID),
+    .io_in_7_bits_dbID                          (io_in_15_bits_dbID),
+    .io_in_7_bits_chiOpcode                     (io_in_15_bits_chiOpcode),
+    .io_in_7_bits_resp                          (io_in_15_bits_resp),
+    .io_in_7_bits_fwdState                      (io_in_15_bits_fwdState),
+    .io_in_7_bits_retToSrc                      (io_in_15_bits_retToSrc),
+    .io_in_7_bits_likelyshared                  (io_in_15_bits_likelyshared),
+    .io_in_7_bits_expCompAck                    (io_in_15_bits_expCompAck),
+    .io_in_7_bits_allowRetry                    (io_in_15_bits_allowRetry),
+    .io_in_7_bits_memAttr_allocate              (io_in_15_bits_memAttr_allocate),
+    .io_in_7_bits_memAttr_cacheable             (io_in_15_bits_memAttr_cacheable),
+    .io_in_7_bits_memAttr_ewa                   (io_in_15_bits_memAttr_ewa),
+    .io_in_7_bits_traceTag                      (io_in_15_bits_traceTag),
+    .io_out_ready                               (io_out_ready & ~finalSelLow),
+    .io_out_valid                               (_highArb_io_out_valid),
+    .io_out_bits_channel                        (_highArb_io_out_bits_channel),
+    .io_out_bits_txChannel                      (_highArb_io_out_bits_txChannel),
+    .io_out_bits_set                            (_highArb_io_out_bits_set),
+    .io_out_bits_tag                            (_highArb_io_out_bits_tag),
+    .io_out_bits_off                            (_highArb_io_out_bits_off),
+    .io_out_bits_alias                          (_highArb_io_out_bits_alias),
+    .io_out_bits_isKeyword                      (_highArb_io_out_bits_isKeyword),
+    .io_out_bits_opcode                         (_highArb_io_out_bits_opcode),
+    .io_out_bits_param                          (_highArb_io_out_bits_param),
+    .io_out_bits_size                           (_highArb_io_out_bits_size),
+    .io_out_bits_sourceId                       (_highArb_io_out_bits_sourceId),
+    .io_out_bits_denied                         (_highArb_io_out_bits_denied),
+    .io_out_bits_corrupt                        (_highArb_io_out_bits_corrupt),
+    .io_out_bits_mshrTask                       (_highArb_io_out_bits_mshrTask),
+    .io_out_bits_aliasTask                      (_highArb_io_out_bits_aliasTask),
+    .io_out_bits_useProbeData                   (_highArb_io_out_bits_useProbeData),
+    .io_out_bits_mshrRetry                      (_highArb_io_out_bits_mshrRetry),
+    .io_out_bits_readProbeDataDown              (_highArb_io_out_bits_readProbeDataDown),
+    .io_out_bits_fromL2pft                      (_highArb_io_out_bits_fromL2pft),
+    .io_out_bits_dirty                          (_highArb_io_out_bits_dirty),
+    .io_out_bits_way                            (_highArb_io_out_bits_way),
+    .io_out_bits_meta_dirty                     (_highArb_io_out_bits_meta_dirty),
+    .io_out_bits_meta_state                     (_highArb_io_out_bits_meta_state),
+    .io_out_bits_meta_clients                   (_highArb_io_out_bits_meta_clients),
+    .io_out_bits_meta_alias                     (_highArb_io_out_bits_meta_alias),
+    .io_out_bits_meta_prefetch                  (_highArb_io_out_bits_meta_prefetch),
+    .io_out_bits_meta_prefetchSrc               (_highArb_io_out_bits_meta_prefetchSrc),
+    .io_out_bits_meta_accessed                  (_highArb_io_out_bits_meta_accessed),
+    .io_out_bits_meta_tagErr                    (_highArb_io_out_bits_meta_tagErr),
+    .io_out_bits_meta_dataErr                   (_highArb_io_out_bits_meta_dataErr),
+    .io_out_bits_metaWen                        (_highArb_io_out_bits_metaWen),
+    .io_out_bits_tagWen                         (_highArb_io_out_bits_tagWen),
+    .io_out_bits_dsWen                          (_highArb_io_out_bits_dsWen),
+    .io_out_bits_replTask                       (_highArb_io_out_bits_replTask),
+    .io_out_bits_cmoTask                        (_highArb_io_out_bits_cmoTask),
+    .io_out_bits_reqSource                      (_highArb_io_out_bits_reqSource),
+    .io_out_bits_mergeA                         (_highArb_io_out_bits_mergeA),
+    .io_out_bits_aMergeTask_off                 (_highArb_io_out_bits_aMergeTask_off),
+    .io_out_bits_aMergeTask_alias               (_highArb_io_out_bits_aMergeTask_alias),
+    .io_out_bits_aMergeTask_vaddr               (_highArb_io_out_bits_aMergeTask_vaddr),
+    .io_out_bits_aMergeTask_isKeyword
+      (_highArb_io_out_bits_aMergeTask_isKeyword),
+    .io_out_bits_aMergeTask_opcode              (_highArb_io_out_bits_aMergeTask_opcode),
+    .io_out_bits_aMergeTask_param               (_highArb_io_out_bits_aMergeTask_param),
+    .io_out_bits_aMergeTask_sourceId
+      (_highArb_io_out_bits_aMergeTask_sourceId),
+    .io_out_bits_aMergeTask_meta_dirty
+      (_highArb_io_out_bits_aMergeTask_meta_dirty),
+    .io_out_bits_aMergeTask_meta_state
+      (_highArb_io_out_bits_aMergeTask_meta_state),
+    .io_out_bits_aMergeTask_meta_clients
+      (_highArb_io_out_bits_aMergeTask_meta_clients),
+    .io_out_bits_aMergeTask_meta_alias
+      (_highArb_io_out_bits_aMergeTask_meta_alias),
+    .io_out_bits_aMergeTask_meta_accessed
+      (_highArb_io_out_bits_aMergeTask_meta_accessed),
+    .io_out_bits_snpHitRelease                  (_highArb_io_out_bits_snpHitRelease),
+    .io_out_bits_snpHitReleaseToInval
+      (_highArb_io_out_bits_snpHitReleaseToInval),
+    .io_out_bits_snpHitReleaseToClean
+      (_highArb_io_out_bits_snpHitReleaseToClean),
+    .io_out_bits_snpHitReleaseWithData
+      (_highArb_io_out_bits_snpHitReleaseWithData),
+    .io_out_bits_snpHitReleaseIdx               (_highArb_io_out_bits_snpHitReleaseIdx),
+    .io_out_bits_snpHitReleaseMeta_dirty
+      (_highArb_io_out_bits_snpHitReleaseMeta_dirty),
+    .io_out_bits_snpHitReleaseMeta_state
+      (_highArb_io_out_bits_snpHitReleaseMeta_state),
+    .io_out_bits_snpHitReleaseMeta_clients
+      (_highArb_io_out_bits_snpHitReleaseMeta_clients),
+    .io_out_bits_snpHitReleaseMeta_alias
+      (_highArb_io_out_bits_snpHitReleaseMeta_alias),
+    .io_out_bits_snpHitReleaseMeta_prefetch
+      (_highArb_io_out_bits_snpHitReleaseMeta_prefetch),
+    .io_out_bits_snpHitReleaseMeta_prefetchSrc
+      (_highArb_io_out_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_out_bits_snpHitReleaseMeta_accessed
+      (_highArb_io_out_bits_snpHitReleaseMeta_accessed),
+    .io_out_bits_snpHitReleaseMeta_tagErr
+      (_highArb_io_out_bits_snpHitReleaseMeta_tagErr),
+    .io_out_bits_snpHitReleaseMeta_dataErr
+      (_highArb_io_out_bits_snpHitReleaseMeta_dataErr),
+    .io_out_bits_tgtID                          (_highArb_io_out_bits_tgtID),
+    .io_out_bits_txnID                          (_highArb_io_out_bits_txnID),
+    .io_out_bits_homeNID                        (_highArb_io_out_bits_homeNID),
+    .io_out_bits_dbID                           (_highArb_io_out_bits_dbID),
+    .io_out_bits_chiOpcode                      (_highArb_io_out_bits_chiOpcode),
+    .io_out_bits_resp                           (_highArb_io_out_bits_resp),
+    .io_out_bits_fwdState                       (_highArb_io_out_bits_fwdState),
+    .io_out_bits_retToSrc                       (_highArb_io_out_bits_retToSrc),
+    .io_out_bits_likelyshared                   (_highArb_io_out_bits_likelyshared),
+    .io_out_bits_expCompAck                     (_highArb_io_out_bits_expCompAck),
+    .io_out_bits_allowRetry                     (_highArb_io_out_bits_allowRetry),
+    .io_out_bits_memAttr_allocate               (_highArb_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable              (_highArb_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_ewa                    (_highArb_io_out_bits_memAttr_ewa),
+    .io_out_bits_traceTag                       (_highArb_io_out_bits_traceTag),
+    .io_chosenOH                                (_highArb_io_chosenOH)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_channel =
+    finalSelLow ? _lowArb_io_out_bits_channel : _highArb_io_out_bits_channel;
+  assign io_out_bits_txChannel =
+    finalSelLow ? _lowArb_io_out_bits_txChannel : _highArb_io_out_bits_txChannel;
+  assign io_out_bits_set =
+    finalSelLow ? _lowArb_io_out_bits_set : _highArb_io_out_bits_set;
+  assign io_out_bits_tag =
+    finalSelLow ? _lowArb_io_out_bits_tag : _highArb_io_out_bits_tag;
+  assign io_out_bits_off =
+    finalSelLow ? _lowArb_io_out_bits_off : _highArb_io_out_bits_off;
+  assign io_out_bits_alias =
+    finalSelLow ? _lowArb_io_out_bits_alias : _highArb_io_out_bits_alias;
+  assign io_out_bits_isKeyword =
+    finalSelLow ? _lowArb_io_out_bits_isKeyword : _highArb_io_out_bits_isKeyword;
+  assign io_out_bits_opcode =
+    finalSelLow ? _lowArb_io_out_bits_opcode : _highArb_io_out_bits_opcode;
+  assign io_out_bits_param =
+    finalSelLow ? _lowArb_io_out_bits_param : _highArb_io_out_bits_param;
+  assign io_out_bits_size =
+    finalSelLow ? _lowArb_io_out_bits_size : _highArb_io_out_bits_size;
+  assign io_out_bits_sourceId =
+    finalSelLow ? _lowArb_io_out_bits_sourceId : _highArb_io_out_bits_sourceId;
+  assign io_out_bits_denied =
+    finalSelLow ? _lowArb_io_out_bits_denied : _highArb_io_out_bits_denied;
+  assign io_out_bits_corrupt =
+    finalSelLow ? _lowArb_io_out_bits_corrupt : _highArb_io_out_bits_corrupt;
+  assign io_out_bits_mshrTask =
+    finalSelLow ? _lowArb_io_out_bits_mshrTask : _highArb_io_out_bits_mshrTask;
+  assign io_out_bits_aliasTask =
+    finalSelLow ? _lowArb_io_out_bits_aliasTask : _highArb_io_out_bits_aliasTask;
+  assign io_out_bits_useProbeData =
+    finalSelLow ? _lowArb_io_out_bits_useProbeData : _highArb_io_out_bits_useProbeData;
+  assign io_out_bits_mshrRetry =
+    finalSelLow ? _lowArb_io_out_bits_mshrRetry : _highArb_io_out_bits_mshrRetry;
+  assign io_out_bits_readProbeDataDown =
+    finalSelLow
+      ? _lowArb_io_out_bits_readProbeDataDown
+      : _highArb_io_out_bits_readProbeDataDown;
+  assign io_out_bits_fromL2pft =
+    finalSelLow ? _lowArb_io_out_bits_fromL2pft : _highArb_io_out_bits_fromL2pft;
+  assign io_out_bits_dirty =
+    finalSelLow ? _lowArb_io_out_bits_dirty : _highArb_io_out_bits_dirty;
+  assign io_out_bits_way =
+    finalSelLow ? _lowArb_io_out_bits_way : _highArb_io_out_bits_way;
+  assign io_out_bits_meta_dirty =
+    finalSelLow ? _lowArb_io_out_bits_meta_dirty : _highArb_io_out_bits_meta_dirty;
+  assign io_out_bits_meta_state =
+    finalSelLow ? _lowArb_io_out_bits_meta_state : _highArb_io_out_bits_meta_state;
+  assign io_out_bits_meta_clients =
+    finalSelLow ? _lowArb_io_out_bits_meta_clients : _highArb_io_out_bits_meta_clients;
+  assign io_out_bits_meta_alias =
+    finalSelLow ? _lowArb_io_out_bits_meta_alias : _highArb_io_out_bits_meta_alias;
+  assign io_out_bits_meta_prefetch =
+    finalSelLow ? _lowArb_io_out_bits_meta_prefetch : _highArb_io_out_bits_meta_prefetch;
+  assign io_out_bits_meta_prefetchSrc =
+    finalSelLow
+      ? _lowArb_io_out_bits_meta_prefetchSrc
+      : _highArb_io_out_bits_meta_prefetchSrc;
+  assign io_out_bits_meta_accessed =
+    finalSelLow ? _lowArb_io_out_bits_meta_accessed : _highArb_io_out_bits_meta_accessed;
+  assign io_out_bits_meta_tagErr =
+    finalSelLow ? _lowArb_io_out_bits_meta_tagErr : _highArb_io_out_bits_meta_tagErr;
+  assign io_out_bits_meta_dataErr =
+    finalSelLow ? _lowArb_io_out_bits_meta_dataErr : _highArb_io_out_bits_meta_dataErr;
+  assign io_out_bits_metaWen =
+    finalSelLow ? _lowArb_io_out_bits_metaWen : _highArb_io_out_bits_metaWen;
+  assign io_out_bits_tagWen =
+    finalSelLow ? _lowArb_io_out_bits_tagWen : _highArb_io_out_bits_tagWen;
+  assign io_out_bits_dsWen =
+    finalSelLow ? _lowArb_io_out_bits_dsWen : _highArb_io_out_bits_dsWen;
+  assign io_out_bits_replTask =
+    finalSelLow ? _lowArb_io_out_bits_replTask : _highArb_io_out_bits_replTask;
+  assign io_out_bits_cmoTask =
+    finalSelLow ? _lowArb_io_out_bits_cmoTask : _highArb_io_out_bits_cmoTask;
+  assign io_out_bits_reqSource =
+    finalSelLow ? _lowArb_io_out_bits_reqSource : _highArb_io_out_bits_reqSource;
+  assign io_out_bits_mergeA =
+    finalSelLow ? _lowArb_io_out_bits_mergeA : _highArb_io_out_bits_mergeA;
+  assign io_out_bits_aMergeTask_off =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_off
+      : _highArb_io_out_bits_aMergeTask_off;
+  assign io_out_bits_aMergeTask_alias =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_alias
+      : _highArb_io_out_bits_aMergeTask_alias;
+  assign io_out_bits_aMergeTask_vaddr =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_vaddr
+      : _highArb_io_out_bits_aMergeTask_vaddr;
+  assign io_out_bits_aMergeTask_isKeyword =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_isKeyword
+      : _highArb_io_out_bits_aMergeTask_isKeyword;
+  assign io_out_bits_aMergeTask_opcode =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_opcode
+      : _highArb_io_out_bits_aMergeTask_opcode;
+  assign io_out_bits_aMergeTask_param =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_param
+      : _highArb_io_out_bits_aMergeTask_param;
+  assign io_out_bits_aMergeTask_sourceId =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_sourceId
+      : _highArb_io_out_bits_aMergeTask_sourceId;
+  assign io_out_bits_aMergeTask_meta_dirty =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_dirty
+      : _highArb_io_out_bits_aMergeTask_meta_dirty;
+  assign io_out_bits_aMergeTask_meta_state =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_state
+      : _highArb_io_out_bits_aMergeTask_meta_state;
+  assign io_out_bits_aMergeTask_meta_clients =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_clients
+      : _highArb_io_out_bits_aMergeTask_meta_clients;
+  assign io_out_bits_aMergeTask_meta_alias =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_alias
+      : _highArb_io_out_bits_aMergeTask_meta_alias;
+  assign io_out_bits_aMergeTask_meta_accessed =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_accessed
+      : _highArb_io_out_bits_aMergeTask_meta_accessed;
+  assign io_out_bits_snpHitRelease =
+    finalSelLow ? _lowArb_io_out_bits_snpHitRelease : _highArb_io_out_bits_snpHitRelease;
+  assign io_out_bits_snpHitReleaseToInval =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseToInval
+      : _highArb_io_out_bits_snpHitReleaseToInval;
+  assign io_out_bits_snpHitReleaseToClean =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseToClean
+      : _highArb_io_out_bits_snpHitReleaseToClean;
+  assign io_out_bits_snpHitReleaseWithData =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseWithData
+      : _highArb_io_out_bits_snpHitReleaseWithData;
+  assign io_out_bits_snpHitReleaseIdx =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseIdx
+      : _highArb_io_out_bits_snpHitReleaseIdx;
+  assign io_out_bits_snpHitReleaseMeta_dirty =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_dirty
+      : _highArb_io_out_bits_snpHitReleaseMeta_dirty;
+  assign io_out_bits_snpHitReleaseMeta_state =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_state
+      : _highArb_io_out_bits_snpHitReleaseMeta_state;
+  assign io_out_bits_snpHitReleaseMeta_clients =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_clients
+      : _highArb_io_out_bits_snpHitReleaseMeta_clients;
+  assign io_out_bits_snpHitReleaseMeta_alias =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_alias
+      : _highArb_io_out_bits_snpHitReleaseMeta_alias;
+  assign io_out_bits_snpHitReleaseMeta_prefetch =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_prefetch
+      : _highArb_io_out_bits_snpHitReleaseMeta_prefetch;
+  assign io_out_bits_snpHitReleaseMeta_prefetchSrc =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_prefetchSrc
+      : _highArb_io_out_bits_snpHitReleaseMeta_prefetchSrc;
+  assign io_out_bits_snpHitReleaseMeta_accessed =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_accessed
+      : _highArb_io_out_bits_snpHitReleaseMeta_accessed;
+  assign io_out_bits_snpHitReleaseMeta_tagErr =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_tagErr
+      : _highArb_io_out_bits_snpHitReleaseMeta_tagErr;
+  assign io_out_bits_snpHitReleaseMeta_dataErr =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_dataErr
+      : _highArb_io_out_bits_snpHitReleaseMeta_dataErr;
+  assign io_out_bits_tgtID =
+    finalSelLow ? _lowArb_io_out_bits_tgtID : _highArb_io_out_bits_tgtID;
+  assign io_out_bits_txnID =
+    finalSelLow ? _lowArb_io_out_bits_txnID : _highArb_io_out_bits_txnID;
+  assign io_out_bits_homeNID =
+    finalSelLow ? _lowArb_io_out_bits_homeNID : _highArb_io_out_bits_homeNID;
+  assign io_out_bits_dbID =
+    finalSelLow ? _lowArb_io_out_bits_dbID : _highArb_io_out_bits_dbID;
+  assign io_out_bits_chiOpcode =
+    finalSelLow ? _lowArb_io_out_bits_chiOpcode : _highArb_io_out_bits_chiOpcode;
+  assign io_out_bits_resp =
+    finalSelLow ? _lowArb_io_out_bits_resp : _highArb_io_out_bits_resp;
+  assign io_out_bits_fwdState =
+    finalSelLow ? _lowArb_io_out_bits_fwdState : _highArb_io_out_bits_fwdState;
+  assign io_out_bits_retToSrc =
+    finalSelLow ? _lowArb_io_out_bits_retToSrc : _highArb_io_out_bits_retToSrc;
+  assign io_out_bits_likelyshared =
+    finalSelLow ? _lowArb_io_out_bits_likelyshared : _highArb_io_out_bits_likelyshared;
+  assign io_out_bits_expCompAck =
+    finalSelLow ? _lowArb_io_out_bits_expCompAck : _highArb_io_out_bits_expCompAck;
+  assign io_out_bits_allowRetry =
+    finalSelLow ? _lowArb_io_out_bits_allowRetry : _highArb_io_out_bits_allowRetry;
+  assign io_out_bits_memAttr_allocate =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_allocate
+      : _highArb_io_out_bits_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_cacheable
+      : _highArb_io_out_bits_memAttr_cacheable;
+  assign io_out_bits_memAttr_ewa =
+    finalSelLow ? _lowArb_io_out_bits_memAttr_ewa : _highArb_io_out_bits_memAttr_ewa;
+  assign io_out_bits_traceTag =
+    finalSelLow ? _lowArb_io_out_bits_traceTag : _highArb_io_out_bits_traceTag;
+  assign io_chosen =
+    {|_io_chosenOH_T_2,
+     |(_io_chosen_T_1[6:3]),
+     |(_io_chosen_T_3[2:1]),
+     _io_chosen_T_3[2] | _io_chosen_T_3[0]};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_11.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_11.sv
new file mode 100644
index 0000000000..d08ed9b2b8
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_11.sv
@@ -0,0 +1,424 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_11(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [3:0]  io_in_0_bits_qos,
+  input  [10:0] io_in_0_bits_srcID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [10:0] io_in_0_bits_returnNID,
+  input         io_in_0_bits_stashNIDValid,
+  input  [11:0] io_in_0_bits_returnTxnID,
+  input  [6:0]  io_in_0_bits_opcode,
+  input  [47:0] io_in_0_bits_addr,
+  input         io_in_0_bits_ns,
+  input         io_in_0_bits_likelyshared,
+  input         io_in_0_bits_allowRetry,
+  input  [1:0]  io_in_0_bits_order,
+  input  [3:0]  io_in_0_bits_pCrdType,
+  input         io_in_0_bits_memAttr_allocate,
+  input         io_in_0_bits_memAttr_cacheable,
+  input         io_in_0_bits_memAttr_device,
+  input         io_in_0_bits_memAttr_ewa,
+  input         io_in_0_bits_snpAttr,
+  input  [7:0]  io_in_0_bits_lpIDWithPadding,
+  input         io_in_0_bits_snoopMe,
+  input         io_in_0_bits_expCompAck,
+  input  [1:0]  io_in_0_bits_tagOp,
+  input         io_in_0_bits_traceTag,
+  input         io_in_0_bits_mpam_perfMonGroup,
+  input  [8:0]  io_in_0_bits_mpam_partID,
+  input         io_in_0_bits_mpam_mpamNS,
+  input  [3:0]  io_in_0_bits_rsvdc,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [3:0]  io_in_1_bits_qos,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [10:0] io_in_1_bits_srcID,
+  input  [11:0] io_in_1_bits_txnID,
+  input  [10:0] io_in_1_bits_returnNID,
+  input         io_in_1_bits_stashNIDValid,
+  input  [11:0] io_in_1_bits_returnTxnID,
+  input  [6:0]  io_in_1_bits_opcode,
+  input  [2:0]  io_in_1_bits_size,
+  input  [47:0] io_in_1_bits_addr,
+  input         io_in_1_bits_ns,
+  input         io_in_1_bits_likelyshared,
+  input         io_in_1_bits_allowRetry,
+  input  [1:0]  io_in_1_bits_order,
+  input  [3:0]  io_in_1_bits_pCrdType,
+  input         io_in_1_bits_memAttr_allocate,
+  input         io_in_1_bits_memAttr_cacheable,
+  input         io_in_1_bits_memAttr_device,
+  input         io_in_1_bits_memAttr_ewa,
+  input         io_in_1_bits_snpAttr,
+  input  [7:0]  io_in_1_bits_lpIDWithPadding,
+  input         io_in_1_bits_snoopMe,
+  input         io_in_1_bits_expCompAck,
+  input  [1:0]  io_in_1_bits_tagOp,
+  input         io_in_1_bits_traceTag,
+  input         io_in_1_bits_mpam_perfMonGroup,
+  input  [8:0]  io_in_1_bits_mpam_partID,
+  input         io_in_1_bits_mpam_mpamNS,
+  input  [3:0]  io_in_1_bits_rsvdc,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [3:0]  io_out_bits_qos,
+  output [10:0] io_out_bits_tgtID,
+  output [11:0] io_out_bits_txnID,
+  output [10:0] io_out_bits_returnNID,
+  output        io_out_bits_stashNIDValid,
+  output [11:0] io_out_bits_returnTxnID,
+  output [6:0]  io_out_bits_opcode,
+  output [2:0]  io_out_bits_size,
+  output [47:0] io_out_bits_addr,
+  output        io_out_bits_ns,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_allowRetry,
+  output [1:0]  io_out_bits_order,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_device,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_snpAttr,
+  output [7:0]  io_out_bits_lpIDWithPadding,
+  output        io_out_bits_snoopMe,
+  output        io_out_bits_expCompAck,
+  output [1:0]  io_out_bits_tagOp,
+  output        io_out_bits_traceTag,
+  output        io_out_bits_mpam_perfMonGroup,
+  output [8:0]  io_out_bits_mpam_partID,
+  output        io_out_bits_mpam_mpamNS,
+  output [3:0]  io_out_bits_rsvdc
+);
+
+  wire        _highArb_io_out_valid;
+  wire [3:0]  _highArb_io_out_bits_qos;
+  wire [10:0] _highArb_io_out_bits_tgtID;
+  wire [11:0] _highArb_io_out_bits_txnID;
+  wire [10:0] _highArb_io_out_bits_returnNID;
+  wire        _highArb_io_out_bits_stashNIDValid;
+  wire [11:0] _highArb_io_out_bits_returnTxnID;
+  wire [6:0]  _highArb_io_out_bits_opcode;
+  wire [2:0]  _highArb_io_out_bits_size;
+  wire [47:0] _highArb_io_out_bits_addr;
+  wire        _highArb_io_out_bits_ns;
+  wire        _highArb_io_out_bits_likelyshared;
+  wire        _highArb_io_out_bits_allowRetry;
+  wire [1:0]  _highArb_io_out_bits_order;
+  wire [3:0]  _highArb_io_out_bits_pCrdType;
+  wire        _highArb_io_out_bits_memAttr_allocate;
+  wire        _highArb_io_out_bits_memAttr_cacheable;
+  wire        _highArb_io_out_bits_memAttr_device;
+  wire        _highArb_io_out_bits_memAttr_ewa;
+  wire        _highArb_io_out_bits_snpAttr;
+  wire [7:0]  _highArb_io_out_bits_lpIDWithPadding;
+  wire        _highArb_io_out_bits_snoopMe;
+  wire        _highArb_io_out_bits_expCompAck;
+  wire [1:0]  _highArb_io_out_bits_tagOp;
+  wire        _highArb_io_out_bits_traceTag;
+  wire        _highArb_io_out_bits_mpam_perfMonGroup;
+  wire [8:0]  _highArb_io_out_bits_mpam_partID;
+  wire        _highArb_io_out_bits_mpam_mpamNS;
+  wire [3:0]  _highArb_io_out_bits_rsvdc;
+  wire        _lowArb_io_out_valid;
+  wire [3:0]  _lowArb_io_out_bits_qos;
+  wire [10:0] _lowArb_io_out_bits_tgtID;
+  wire [11:0] _lowArb_io_out_bits_txnID;
+  wire [10:0] _lowArb_io_out_bits_returnNID;
+  wire        _lowArb_io_out_bits_stashNIDValid;
+  wire [11:0] _lowArb_io_out_bits_returnTxnID;
+  wire [6:0]  _lowArb_io_out_bits_opcode;
+  wire [2:0]  _lowArb_io_out_bits_size;
+  wire [47:0] _lowArb_io_out_bits_addr;
+  wire        _lowArb_io_out_bits_ns;
+  wire        _lowArb_io_out_bits_likelyshared;
+  wire        _lowArb_io_out_bits_allowRetry;
+  wire [1:0]  _lowArb_io_out_bits_order;
+  wire [3:0]  _lowArb_io_out_bits_pCrdType;
+  wire        _lowArb_io_out_bits_memAttr_allocate;
+  wire        _lowArb_io_out_bits_memAttr_cacheable;
+  wire        _lowArb_io_out_bits_memAttr_device;
+  wire        _lowArb_io_out_bits_memAttr_ewa;
+  wire        _lowArb_io_out_bits_snpAttr;
+  wire [7:0]  _lowArb_io_out_bits_lpIDWithPadding;
+  wire        _lowArb_io_out_bits_snoopMe;
+  wire        _lowArb_io_out_bits_expCompAck;
+  wire [1:0]  _lowArb_io_out_bits_tagOp;
+  wire        _lowArb_io_out_bits_traceTag;
+  wire        _lowArb_io_out_bits_mpam_perfMonGroup;
+  wire [8:0]  _lowArb_io_out_bits_mpam_partID;
+  wire        _lowArb_io_out_bits_mpam_mpamNS;
+  wire [3:0]  _lowArb_io_out_bits_rsvdc;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_ready & io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_24 lowArb (
+    .io_in_0_ready                  (io_in_0_ready),
+    .io_in_0_valid                  (io_in_0_valid),
+    .io_in_0_bits_qos               (io_in_0_bits_qos),
+    .io_in_0_bits_tgtID             (11'h0),
+    .io_in_0_bits_srcID             (io_in_0_bits_srcID),
+    .io_in_0_bits_txnID             (io_in_0_bits_txnID),
+    .io_in_0_bits_returnNID         (io_in_0_bits_returnNID),
+    .io_in_0_bits_stashNIDValid     (io_in_0_bits_stashNIDValid),
+    .io_in_0_bits_returnTxnID       (io_in_0_bits_returnTxnID),
+    .io_in_0_bits_opcode            (io_in_0_bits_opcode),
+    .io_in_0_bits_size              (3'h6),
+    .io_in_0_bits_addr              (io_in_0_bits_addr),
+    .io_in_0_bits_ns                (io_in_0_bits_ns),
+    .io_in_0_bits_likelyshared      (io_in_0_bits_likelyshared),
+    .io_in_0_bits_allowRetry        (io_in_0_bits_allowRetry),
+    .io_in_0_bits_order             (io_in_0_bits_order),
+    .io_in_0_bits_pCrdType          (io_in_0_bits_pCrdType),
+    .io_in_0_bits_memAttr_allocate  (io_in_0_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable (io_in_0_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_device    (io_in_0_bits_memAttr_device),
+    .io_in_0_bits_memAttr_ewa       (io_in_0_bits_memAttr_ewa),
+    .io_in_0_bits_snpAttr           (io_in_0_bits_snpAttr),
+    .io_in_0_bits_lpIDWithPadding   (io_in_0_bits_lpIDWithPadding),
+    .io_in_0_bits_snoopMe           (io_in_0_bits_snoopMe),
+    .io_in_0_bits_expCompAck        (io_in_0_bits_expCompAck),
+    .io_in_0_bits_tagOp             (io_in_0_bits_tagOp),
+    .io_in_0_bits_traceTag          (io_in_0_bits_traceTag),
+    .io_in_0_bits_mpam_perfMonGroup (io_in_0_bits_mpam_perfMonGroup),
+    .io_in_0_bits_mpam_partID       (io_in_0_bits_mpam_partID),
+    .io_in_0_bits_mpam_mpamNS       (io_in_0_bits_mpam_mpamNS),
+    .io_in_0_bits_rsvdc             (io_in_0_bits_rsvdc),
+    .io_out_ready                   (io_out_ready & finalSelLow),
+    .io_out_valid                   (_lowArb_io_out_valid),
+    .io_out_bits_qos                (_lowArb_io_out_bits_qos),
+    .io_out_bits_tgtID              (_lowArb_io_out_bits_tgtID),
+    .io_out_bits_srcID              (/* unused */),
+    .io_out_bits_txnID              (_lowArb_io_out_bits_txnID),
+    .io_out_bits_returnNID          (_lowArb_io_out_bits_returnNID),
+    .io_out_bits_stashNIDValid      (_lowArb_io_out_bits_stashNIDValid),
+    .io_out_bits_returnTxnID        (_lowArb_io_out_bits_returnTxnID),
+    .io_out_bits_opcode             (_lowArb_io_out_bits_opcode),
+    .io_out_bits_size               (_lowArb_io_out_bits_size),
+    .io_out_bits_addr               (_lowArb_io_out_bits_addr),
+    .io_out_bits_ns                 (_lowArb_io_out_bits_ns),
+    .io_out_bits_likelyshared       (_lowArb_io_out_bits_likelyshared),
+    .io_out_bits_allowRetry         (_lowArb_io_out_bits_allowRetry),
+    .io_out_bits_order              (_lowArb_io_out_bits_order),
+    .io_out_bits_pCrdType           (_lowArb_io_out_bits_pCrdType),
+    .io_out_bits_memAttr_allocate   (_lowArb_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable  (_lowArb_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device     (_lowArb_io_out_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa        (_lowArb_io_out_bits_memAttr_ewa),
+    .io_out_bits_snpAttr            (_lowArb_io_out_bits_snpAttr),
+    .io_out_bits_lpIDWithPadding    (_lowArb_io_out_bits_lpIDWithPadding),
+    .io_out_bits_snoopMe            (_lowArb_io_out_bits_snoopMe),
+    .io_out_bits_expCompAck         (_lowArb_io_out_bits_expCompAck),
+    .io_out_bits_tagOp              (_lowArb_io_out_bits_tagOp),
+    .io_out_bits_traceTag           (_lowArb_io_out_bits_traceTag),
+    .io_out_bits_mpam_perfMonGroup  (_lowArb_io_out_bits_mpam_perfMonGroup),
+    .io_out_bits_mpam_partID        (_lowArb_io_out_bits_mpam_partID),
+    .io_out_bits_mpam_mpamNS        (_lowArb_io_out_bits_mpam_mpamNS),
+    .io_out_bits_rsvdc              (_lowArb_io_out_bits_rsvdc)
+  );
+  FastArbiter_24 highArb (
+    .io_in_0_ready                  (io_in_1_ready),
+    .io_in_0_valid                  (io_in_1_valid),
+    .io_in_0_bits_qos               (io_in_1_bits_qos),
+    .io_in_0_bits_tgtID             (io_in_1_bits_tgtID),
+    .io_in_0_bits_srcID             (io_in_1_bits_srcID),
+    .io_in_0_bits_txnID             (io_in_1_bits_txnID),
+    .io_in_0_bits_returnNID         (io_in_1_bits_returnNID),
+    .io_in_0_bits_stashNIDValid     (io_in_1_bits_stashNIDValid),
+    .io_in_0_bits_returnTxnID       (io_in_1_bits_returnTxnID),
+    .io_in_0_bits_opcode            (io_in_1_bits_opcode),
+    .io_in_0_bits_size              (io_in_1_bits_size),
+    .io_in_0_bits_addr              (io_in_1_bits_addr),
+    .io_in_0_bits_ns                (io_in_1_bits_ns),
+    .io_in_0_bits_likelyshared      (io_in_1_bits_likelyshared),
+    .io_in_0_bits_allowRetry        (io_in_1_bits_allowRetry),
+    .io_in_0_bits_order             (io_in_1_bits_order),
+    .io_in_0_bits_pCrdType          (io_in_1_bits_pCrdType),
+    .io_in_0_bits_memAttr_allocate  (io_in_1_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable (io_in_1_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_device    (io_in_1_bits_memAttr_device),
+    .io_in_0_bits_memAttr_ewa       (io_in_1_bits_memAttr_ewa),
+    .io_in_0_bits_snpAttr           (io_in_1_bits_snpAttr),
+    .io_in_0_bits_lpIDWithPadding   (io_in_1_bits_lpIDWithPadding),
+    .io_in_0_bits_snoopMe           (io_in_1_bits_snoopMe),
+    .io_in_0_bits_expCompAck        (io_in_1_bits_expCompAck),
+    .io_in_0_bits_tagOp             (io_in_1_bits_tagOp),
+    .io_in_0_bits_traceTag          (io_in_1_bits_traceTag),
+    .io_in_0_bits_mpam_perfMonGroup (io_in_1_bits_mpam_perfMonGroup),
+    .io_in_0_bits_mpam_partID       (io_in_1_bits_mpam_partID),
+    .io_in_0_bits_mpam_mpamNS       (io_in_1_bits_mpam_mpamNS),
+    .io_in_0_bits_rsvdc             (io_in_1_bits_rsvdc),
+    .io_out_ready                   (io_out_ready & ~finalSelLow),
+    .io_out_valid                   (_highArb_io_out_valid),
+    .io_out_bits_qos                (_highArb_io_out_bits_qos),
+    .io_out_bits_tgtID              (_highArb_io_out_bits_tgtID),
+    .io_out_bits_srcID              (/* unused */),
+    .io_out_bits_txnID              (_highArb_io_out_bits_txnID),
+    .io_out_bits_returnNID          (_highArb_io_out_bits_returnNID),
+    .io_out_bits_stashNIDValid      (_highArb_io_out_bits_stashNIDValid),
+    .io_out_bits_returnTxnID        (_highArb_io_out_bits_returnTxnID),
+    .io_out_bits_opcode             (_highArb_io_out_bits_opcode),
+    .io_out_bits_size               (_highArb_io_out_bits_size),
+    .io_out_bits_addr               (_highArb_io_out_bits_addr),
+    .io_out_bits_ns                 (_highArb_io_out_bits_ns),
+    .io_out_bits_likelyshared       (_highArb_io_out_bits_likelyshared),
+    .io_out_bits_allowRetry         (_highArb_io_out_bits_allowRetry),
+    .io_out_bits_order              (_highArb_io_out_bits_order),
+    .io_out_bits_pCrdType           (_highArb_io_out_bits_pCrdType),
+    .io_out_bits_memAttr_allocate   (_highArb_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable  (_highArb_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device     (_highArb_io_out_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa        (_highArb_io_out_bits_memAttr_ewa),
+    .io_out_bits_snpAttr            (_highArb_io_out_bits_snpAttr),
+    .io_out_bits_lpIDWithPadding    (_highArb_io_out_bits_lpIDWithPadding),
+    .io_out_bits_snoopMe            (_highArb_io_out_bits_snoopMe),
+    .io_out_bits_expCompAck         (_highArb_io_out_bits_expCompAck),
+    .io_out_bits_tagOp              (_highArb_io_out_bits_tagOp),
+    .io_out_bits_traceTag           (_highArb_io_out_bits_traceTag),
+    .io_out_bits_mpam_perfMonGroup  (_highArb_io_out_bits_mpam_perfMonGroup),
+    .io_out_bits_mpam_partID        (_highArb_io_out_bits_mpam_partID),
+    .io_out_bits_mpam_mpamNS        (_highArb_io_out_bits_mpam_mpamNS),
+    .io_out_bits_rsvdc              (_highArb_io_out_bits_rsvdc)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_qos =
+    finalSelLow ? _lowArb_io_out_bits_qos : _highArb_io_out_bits_qos;
+  assign io_out_bits_tgtID =
+    finalSelLow ? _lowArb_io_out_bits_tgtID : _highArb_io_out_bits_tgtID;
+  assign io_out_bits_txnID =
+    finalSelLow ? _lowArb_io_out_bits_txnID : _highArb_io_out_bits_txnID;
+  assign io_out_bits_returnNID =
+    finalSelLow ? _lowArb_io_out_bits_returnNID : _highArb_io_out_bits_returnNID;
+  assign io_out_bits_stashNIDValid =
+    finalSelLow ? _lowArb_io_out_bits_stashNIDValid : _highArb_io_out_bits_stashNIDValid;
+  assign io_out_bits_returnTxnID =
+    finalSelLow ? _lowArb_io_out_bits_returnTxnID : _highArb_io_out_bits_returnTxnID;
+  assign io_out_bits_opcode =
+    finalSelLow ? _lowArb_io_out_bits_opcode : _highArb_io_out_bits_opcode;
+  assign io_out_bits_size =
+    finalSelLow ? _lowArb_io_out_bits_size : _highArb_io_out_bits_size;
+  assign io_out_bits_addr =
+    finalSelLow ? _lowArb_io_out_bits_addr : _highArb_io_out_bits_addr;
+  assign io_out_bits_ns = finalSelLow ? _lowArb_io_out_bits_ns : _highArb_io_out_bits_ns;
+  assign io_out_bits_likelyshared =
+    finalSelLow ? _lowArb_io_out_bits_likelyshared : _highArb_io_out_bits_likelyshared;
+  assign io_out_bits_allowRetry =
+    finalSelLow ? _lowArb_io_out_bits_allowRetry : _highArb_io_out_bits_allowRetry;
+  assign io_out_bits_order =
+    finalSelLow ? _lowArb_io_out_bits_order : _highArb_io_out_bits_order;
+  assign io_out_bits_pCrdType =
+    finalSelLow ? _lowArb_io_out_bits_pCrdType : _highArb_io_out_bits_pCrdType;
+  assign io_out_bits_memAttr_allocate =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_allocate
+      : _highArb_io_out_bits_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_cacheable
+      : _highArb_io_out_bits_memAttr_cacheable;
+  assign io_out_bits_memAttr_device =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_device
+      : _highArb_io_out_bits_memAttr_device;
+  assign io_out_bits_memAttr_ewa =
+    finalSelLow ? _lowArb_io_out_bits_memAttr_ewa : _highArb_io_out_bits_memAttr_ewa;
+  assign io_out_bits_snpAttr =
+    finalSelLow ? _lowArb_io_out_bits_snpAttr : _highArb_io_out_bits_snpAttr;
+  assign io_out_bits_lpIDWithPadding =
+    finalSelLow
+      ? _lowArb_io_out_bits_lpIDWithPadding
+      : _highArb_io_out_bits_lpIDWithPadding;
+  assign io_out_bits_snoopMe =
+    finalSelLow ? _lowArb_io_out_bits_snoopMe : _highArb_io_out_bits_snoopMe;
+  assign io_out_bits_expCompAck =
+    finalSelLow ? _lowArb_io_out_bits_expCompAck : _highArb_io_out_bits_expCompAck;
+  assign io_out_bits_tagOp =
+    finalSelLow ? _lowArb_io_out_bits_tagOp : _highArb_io_out_bits_tagOp;
+  assign io_out_bits_traceTag =
+    finalSelLow ? _lowArb_io_out_bits_traceTag : _highArb_io_out_bits_traceTag;
+  assign io_out_bits_mpam_perfMonGroup =
+    finalSelLow
+      ? _lowArb_io_out_bits_mpam_perfMonGroup
+      : _highArb_io_out_bits_mpam_perfMonGroup;
+  assign io_out_bits_mpam_partID =
+    finalSelLow ? _lowArb_io_out_bits_mpam_partID : _highArb_io_out_bits_mpam_partID;
+  assign io_out_bits_mpam_mpamNS =
+    finalSelLow ? _lowArb_io_out_bits_mpam_mpamNS : _highArb_io_out_bits_mpam_mpamNS;
+  assign io_out_bits_rsvdc =
+    finalSelLow ? _lowArb_io_out_bits_rsvdc : _highArb_io_out_bits_rsvdc;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_12.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_12.sv
new file mode 100644
index 0000000000..b33e20ec42
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_12.sv
@@ -0,0 +1,226 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_12(
+  input  clock,
+  input  reset,
+  output io_in_0_ready,
+  input  io_in_0_valid,
+  output io_in_1_ready,
+  input  io_in_1_valid,
+  output io_in_2_ready,
+  input  io_in_2_valid,
+  output io_in_3_ready,
+  input  io_in_3_valid,
+  output io_in_4_ready,
+  input  io_in_4_valid,
+  output io_in_5_ready,
+  input  io_in_5_valid,
+  output io_in_6_ready,
+  input  io_in_6_valid,
+  output io_in_7_ready,
+  input  io_in_7_valid,
+  output io_in_8_ready,
+  input  io_in_8_valid,
+  output io_in_9_ready,
+  input  io_in_9_valid,
+  output io_in_10_ready,
+  input  io_in_10_valid,
+  output io_in_11_ready,
+  input  io_in_11_valid,
+  output io_in_12_ready,
+  input  io_in_12_valid,
+  output io_in_13_ready,
+  input  io_in_13_valid,
+  output io_in_14_ready,
+  input  io_in_14_valid,
+  output io_in_15_ready,
+  input  io_in_15_valid,
+  output io_in_16_ready,
+  input  io_in_16_valid,
+  output io_in_17_ready,
+  input  io_in_17_valid,
+  output io_in_18_ready,
+  input  io_in_18_valid,
+  output io_in_19_ready,
+  input  io_in_19_valid,
+  output io_in_20_ready,
+  input  io_in_20_valid,
+  output io_in_21_ready,
+  input  io_in_21_valid,
+  output io_in_22_ready,
+  input  io_in_22_valid,
+  output io_in_23_ready,
+  input  io_in_23_valid,
+  output io_in_24_ready,
+  input  io_in_24_valid,
+  output io_in_25_ready,
+  input  io_in_25_valid,
+  output io_in_26_ready,
+  input  io_in_26_valid,
+  output io_in_27_ready,
+  input  io_in_27_valid,
+  output io_in_28_ready,
+  input  io_in_28_valid,
+  output io_in_29_ready,
+  input  io_in_29_valid,
+  output io_in_30_ready,
+  input  io_in_30_valid,
+  output io_in_31_ready,
+  input  io_in_31_valid,
+  output io_out_valid
+);
+
+  wire _highArb_io_out_valid;
+  wire _lowArb_io_out_valid;
+  reg  selLow;
+  wire finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_28 lowArb (
+    .clock          (clock),
+    .reset          (reset),
+    .io_in_0_ready  (io_in_0_ready),
+    .io_in_0_valid  (io_in_0_valid),
+    .io_in_1_ready  (io_in_1_ready),
+    .io_in_1_valid  (io_in_1_valid),
+    .io_in_2_ready  (io_in_2_ready),
+    .io_in_2_valid  (io_in_2_valid),
+    .io_in_3_ready  (io_in_3_ready),
+    .io_in_3_valid  (io_in_3_valid),
+    .io_in_4_ready  (io_in_4_ready),
+    .io_in_4_valid  (io_in_4_valid),
+    .io_in_5_ready  (io_in_5_ready),
+    .io_in_5_valid  (io_in_5_valid),
+    .io_in_6_ready  (io_in_6_ready),
+    .io_in_6_valid  (io_in_6_valid),
+    .io_in_7_ready  (io_in_7_ready),
+    .io_in_7_valid  (io_in_7_valid),
+    .io_in_8_ready  (io_in_8_ready),
+    .io_in_8_valid  (io_in_8_valid),
+    .io_in_9_ready  (io_in_9_ready),
+    .io_in_9_valid  (io_in_9_valid),
+    .io_in_10_ready (io_in_10_ready),
+    .io_in_10_valid (io_in_10_valid),
+    .io_in_11_ready (io_in_11_ready),
+    .io_in_11_valid (io_in_11_valid),
+    .io_in_12_ready (io_in_12_ready),
+    .io_in_12_valid (io_in_12_valid),
+    .io_in_13_ready (io_in_13_ready),
+    .io_in_13_valid (io_in_13_valid),
+    .io_in_14_ready (io_in_14_ready),
+    .io_in_14_valid (io_in_14_valid),
+    .io_in_15_ready (io_in_15_ready),
+    .io_in_15_valid (io_in_15_valid),
+    .io_out_ready   (finalSelLow),
+    .io_out_valid   (_lowArb_io_out_valid)
+  );
+  FastArbiter_28 highArb (
+    .clock          (clock),
+    .reset          (reset),
+    .io_in_0_ready  (io_in_16_ready),
+    .io_in_0_valid  (io_in_16_valid),
+    .io_in_1_ready  (io_in_17_ready),
+    .io_in_1_valid  (io_in_17_valid),
+    .io_in_2_ready  (io_in_18_ready),
+    .io_in_2_valid  (io_in_18_valid),
+    .io_in_3_ready  (io_in_19_ready),
+    .io_in_3_valid  (io_in_19_valid),
+    .io_in_4_ready  (io_in_20_ready),
+    .io_in_4_valid  (io_in_20_valid),
+    .io_in_5_ready  (io_in_21_ready),
+    .io_in_5_valid  (io_in_21_valid),
+    .io_in_6_ready  (io_in_22_ready),
+    .io_in_6_valid  (io_in_22_valid),
+    .io_in_7_ready  (io_in_23_ready),
+    .io_in_7_valid  (io_in_23_valid),
+    .io_in_8_ready  (io_in_24_ready),
+    .io_in_8_valid  (io_in_24_valid),
+    .io_in_9_ready  (io_in_25_ready),
+    .io_in_9_valid  (io_in_25_valid),
+    .io_in_10_ready (io_in_26_ready),
+    .io_in_10_valid (io_in_26_valid),
+    .io_in_11_ready (io_in_27_ready),
+    .io_in_11_valid (io_in_27_valid),
+    .io_in_12_ready (io_in_28_ready),
+    .io_in_12_valid (io_in_28_valid),
+    .io_in_13_ready (io_in_29_ready),
+    .io_in_13_valid (io_in_29_valid),
+    .io_in_14_ready (io_in_30_ready),
+    .io_in_14_valid (io_in_30_valid),
+    .io_in_15_ready (io_in_31_ready),
+    .io_in_15_valid (io_in_31_valid),
+    .io_out_ready   (~finalSelLow),
+    .io_out_valid   (_highArb_io_out_valid)
+  );
+  assign io_out_valid = io_out_valid_0;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_2.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_2.sv
new file mode 100644
index 0000000000..29ace16339
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_2.sv
@@ -0,0 +1,201 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_2(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [49:0] io_in_0_bits_vaddr,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [49:0] io_in_1_bits_vaddr,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [49:0] io_in_2_bits_vaddr,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [49:0] io_in_3_bits_vaddr,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [49:0] io_in_4_bits_vaddr,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [49:0] io_in_5_bits_vaddr,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [49:0] io_in_6_bits_vaddr,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [49:0] io_in_7_bits_vaddr,
+  output        io_in_8_ready,
+  input         io_in_8_valid,
+  input  [49:0] io_in_8_bits_vaddr,
+  output        io_in_9_ready,
+  input         io_in_9_valid,
+  input  [49:0] io_in_9_bits_vaddr,
+  output        io_in_10_ready,
+  input         io_in_10_valid,
+  input  [49:0] io_in_10_bits_vaddr,
+  output        io_in_11_ready,
+  input         io_in_11_valid,
+  input  [49:0] io_in_11_bits_vaddr,
+  output        io_in_12_ready,
+  input         io_in_12_valid,
+  input  [49:0] io_in_12_bits_vaddr,
+  output        io_in_13_ready,
+  input         io_in_13_valid,
+  input  [49:0] io_in_13_bits_vaddr,
+  output        io_in_14_ready,
+  input         io_in_14_valid,
+  input  [49:0] io_in_14_bits_vaddr,
+  output        io_in_15_ready,
+  input         io_in_15_valid,
+  input  [49:0] io_in_15_bits_vaddr,
+  output        io_out_valid,
+  output [49:0] io_out_bits_vaddr
+);
+
+  wire        _highArb_io_out_valid;
+  wire [49:0] _highArb_io_out_bits_vaddr;
+  wire        _lowArb_io_out_valid;
+  wire [49:0] _lowArb_io_out_bits_vaddr;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_4 lowArb (
+    .clock              (clock),
+    .reset              (reset),
+    .io_in_0_ready      (io_in_0_ready),
+    .io_in_0_valid      (io_in_0_valid),
+    .io_in_0_bits_vaddr (io_in_0_bits_vaddr),
+    .io_in_1_ready      (io_in_1_ready),
+    .io_in_1_valid      (io_in_1_valid),
+    .io_in_1_bits_vaddr (io_in_1_bits_vaddr),
+    .io_in_2_ready      (io_in_2_ready),
+    .io_in_2_valid      (io_in_2_valid),
+    .io_in_2_bits_vaddr (io_in_2_bits_vaddr),
+    .io_in_3_ready      (io_in_3_ready),
+    .io_in_3_valid      (io_in_3_valid),
+    .io_in_3_bits_vaddr (io_in_3_bits_vaddr),
+    .io_in_4_ready      (io_in_4_ready),
+    .io_in_4_valid      (io_in_4_valid),
+    .io_in_4_bits_vaddr (io_in_4_bits_vaddr),
+    .io_in_5_ready      (io_in_5_ready),
+    .io_in_5_valid      (io_in_5_valid),
+    .io_in_5_bits_vaddr (io_in_5_bits_vaddr),
+    .io_in_6_ready      (io_in_6_ready),
+    .io_in_6_valid      (io_in_6_valid),
+    .io_in_6_bits_vaddr (io_in_6_bits_vaddr),
+    .io_in_7_ready      (io_in_7_ready),
+    .io_in_7_valid      (io_in_7_valid),
+    .io_in_7_bits_vaddr (io_in_7_bits_vaddr),
+    .io_out_ready       (finalSelLow),
+    .io_out_valid       (_lowArb_io_out_valid),
+    .io_out_bits_vaddr  (_lowArb_io_out_bits_vaddr)
+  );
+  FastArbiter_4 highArb (
+    .clock              (clock),
+    .reset              (reset),
+    .io_in_0_ready      (io_in_8_ready),
+    .io_in_0_valid      (io_in_8_valid),
+    .io_in_0_bits_vaddr (io_in_8_bits_vaddr),
+    .io_in_1_ready      (io_in_9_ready),
+    .io_in_1_valid      (io_in_9_valid),
+    .io_in_1_bits_vaddr (io_in_9_bits_vaddr),
+    .io_in_2_ready      (io_in_10_ready),
+    .io_in_2_valid      (io_in_10_valid),
+    .io_in_2_bits_vaddr (io_in_10_bits_vaddr),
+    .io_in_3_ready      (io_in_11_ready),
+    .io_in_3_valid      (io_in_11_valid),
+    .io_in_3_bits_vaddr (io_in_11_bits_vaddr),
+    .io_in_4_ready      (io_in_12_ready),
+    .io_in_4_valid      (io_in_12_valid),
+    .io_in_4_bits_vaddr (io_in_12_bits_vaddr),
+    .io_in_5_ready      (io_in_13_ready),
+    .io_in_5_valid      (io_in_13_valid),
+    .io_in_5_bits_vaddr (io_in_13_bits_vaddr),
+    .io_in_6_ready      (io_in_14_ready),
+    .io_in_6_valid      (io_in_14_valid),
+    .io_in_6_bits_vaddr (io_in_14_bits_vaddr),
+    .io_in_7_ready      (io_in_15_ready),
+    .io_in_7_valid      (io_in_15_valid),
+    .io_in_7_bits_vaddr (io_in_15_bits_vaddr),
+    .io_out_ready       (~finalSelLow),
+    .io_out_valid       (_highArb_io_out_valid),
+    .io_out_bits_vaddr  (_highArb_io_out_bits_vaddr)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_vaddr =
+    finalSelLow ? _lowArb_io_out_bits_vaddr : _highArb_io_out_bits_vaddr;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_3.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_3.sv
new file mode 100644
index 0000000000..33d74ae27d
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_3.sv
@@ -0,0 +1,358 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_3(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [33:0] io_in_0_bits_tag,
+  input  [7:0]  io_in_0_bits_set,
+  input  [43:0] io_in_0_bits_vaddr,
+  input         io_in_0_bits_needT,
+  input  [6:0]  io_in_0_bits_source,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [33:0] io_in_1_bits_tag,
+  input  [7:0]  io_in_1_bits_set,
+  input  [43:0] io_in_1_bits_vaddr,
+  input         io_in_1_bits_needT,
+  input  [6:0]  io_in_1_bits_source,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [33:0] io_in_2_bits_tag,
+  input  [7:0]  io_in_2_bits_set,
+  input  [43:0] io_in_2_bits_vaddr,
+  input         io_in_2_bits_needT,
+  input  [6:0]  io_in_2_bits_source,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [33:0] io_in_3_bits_tag,
+  input  [7:0]  io_in_3_bits_set,
+  input  [43:0] io_in_3_bits_vaddr,
+  input         io_in_3_bits_needT,
+  input  [6:0]  io_in_3_bits_source,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [33:0] io_in_4_bits_tag,
+  input  [7:0]  io_in_4_bits_set,
+  input  [43:0] io_in_4_bits_vaddr,
+  input         io_in_4_bits_needT,
+  input  [6:0]  io_in_4_bits_source,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [33:0] io_in_5_bits_tag,
+  input  [7:0]  io_in_5_bits_set,
+  input  [43:0] io_in_5_bits_vaddr,
+  input         io_in_5_bits_needT,
+  input  [6:0]  io_in_5_bits_source,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [33:0] io_in_6_bits_tag,
+  input  [7:0]  io_in_6_bits_set,
+  input  [43:0] io_in_6_bits_vaddr,
+  input         io_in_6_bits_needT,
+  input  [6:0]  io_in_6_bits_source,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [33:0] io_in_7_bits_tag,
+  input  [7:0]  io_in_7_bits_set,
+  input  [43:0] io_in_7_bits_vaddr,
+  input         io_in_7_bits_needT,
+  input  [6:0]  io_in_7_bits_source,
+  output        io_in_8_ready,
+  input         io_in_8_valid,
+  input  [33:0] io_in_8_bits_tag,
+  input  [7:0]  io_in_8_bits_set,
+  input  [43:0] io_in_8_bits_vaddr,
+  input         io_in_8_bits_needT,
+  input  [6:0]  io_in_8_bits_source,
+  output        io_in_9_ready,
+  input         io_in_9_valid,
+  input  [33:0] io_in_9_bits_tag,
+  input  [7:0]  io_in_9_bits_set,
+  input  [43:0] io_in_9_bits_vaddr,
+  input         io_in_9_bits_needT,
+  input  [6:0]  io_in_9_bits_source,
+  output        io_in_10_ready,
+  input         io_in_10_valid,
+  input  [33:0] io_in_10_bits_tag,
+  input  [7:0]  io_in_10_bits_set,
+  input  [43:0] io_in_10_bits_vaddr,
+  input         io_in_10_bits_needT,
+  input  [6:0]  io_in_10_bits_source,
+  output        io_in_11_ready,
+  input         io_in_11_valid,
+  input  [33:0] io_in_11_bits_tag,
+  input  [7:0]  io_in_11_bits_set,
+  input  [43:0] io_in_11_bits_vaddr,
+  input         io_in_11_bits_needT,
+  input  [6:0]  io_in_11_bits_source,
+  output        io_in_12_ready,
+  input         io_in_12_valid,
+  input  [33:0] io_in_12_bits_tag,
+  input  [7:0]  io_in_12_bits_set,
+  input  [43:0] io_in_12_bits_vaddr,
+  input         io_in_12_bits_needT,
+  input  [6:0]  io_in_12_bits_source,
+  output        io_in_13_ready,
+  input         io_in_13_valid,
+  input  [33:0] io_in_13_bits_tag,
+  input  [7:0]  io_in_13_bits_set,
+  input  [43:0] io_in_13_bits_vaddr,
+  input         io_in_13_bits_needT,
+  input  [6:0]  io_in_13_bits_source,
+  output        io_in_14_ready,
+  input         io_in_14_valid,
+  input  [33:0] io_in_14_bits_tag,
+  input  [7:0]  io_in_14_bits_set,
+  input  [43:0] io_in_14_bits_vaddr,
+  input         io_in_14_bits_needT,
+  input  [6:0]  io_in_14_bits_source,
+  output        io_in_15_ready,
+  input         io_in_15_valid,
+  input  [33:0] io_in_15_bits_tag,
+  input  [7:0]  io_in_15_bits_set,
+  input  [43:0] io_in_15_bits_vaddr,
+  input         io_in_15_bits_needT,
+  input  [6:0]  io_in_15_bits_source,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [33:0] io_out_bits_tag,
+  output [7:0]  io_out_bits_set,
+  output [43:0] io_out_bits_vaddr,
+  output        io_out_bits_needT,
+  output [6:0]  io_out_bits_source
+);
+
+  wire        _highArb_io_out_valid;
+  wire [33:0] _highArb_io_out_bits_tag;
+  wire [7:0]  _highArb_io_out_bits_set;
+  wire [43:0] _highArb_io_out_bits_vaddr;
+  wire        _highArb_io_out_bits_needT;
+  wire [6:0]  _highArb_io_out_bits_source;
+  wire        _lowArb_io_out_valid;
+  wire [33:0] _lowArb_io_out_bits_tag;
+  wire [7:0]  _lowArb_io_out_bits_set;
+  wire [43:0] _lowArb_io_out_bits_vaddr;
+  wire        _lowArb_io_out_bits_needT;
+  wire [6:0]  _lowArb_io_out_bits_source;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_ready & io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_6 lowArb (
+    .clock               (clock),
+    .reset               (reset),
+    .io_in_0_ready       (io_in_0_ready),
+    .io_in_0_valid       (io_in_0_valid),
+    .io_in_0_bits_tag    (io_in_0_bits_tag),
+    .io_in_0_bits_set    (io_in_0_bits_set),
+    .io_in_0_bits_vaddr  (io_in_0_bits_vaddr),
+    .io_in_0_bits_needT  (io_in_0_bits_needT),
+    .io_in_0_bits_source (io_in_0_bits_source),
+    .io_in_1_ready       (io_in_1_ready),
+    .io_in_1_valid       (io_in_1_valid),
+    .io_in_1_bits_tag    (io_in_1_bits_tag),
+    .io_in_1_bits_set    (io_in_1_bits_set),
+    .io_in_1_bits_vaddr  (io_in_1_bits_vaddr),
+    .io_in_1_bits_needT  (io_in_1_bits_needT),
+    .io_in_1_bits_source (io_in_1_bits_source),
+    .io_in_2_ready       (io_in_2_ready),
+    .io_in_2_valid       (io_in_2_valid),
+    .io_in_2_bits_tag    (io_in_2_bits_tag),
+    .io_in_2_bits_set    (io_in_2_bits_set),
+    .io_in_2_bits_vaddr  (io_in_2_bits_vaddr),
+    .io_in_2_bits_needT  (io_in_2_bits_needT),
+    .io_in_2_bits_source (io_in_2_bits_source),
+    .io_in_3_ready       (io_in_3_ready),
+    .io_in_3_valid       (io_in_3_valid),
+    .io_in_3_bits_tag    (io_in_3_bits_tag),
+    .io_in_3_bits_set    (io_in_3_bits_set),
+    .io_in_3_bits_vaddr  (io_in_3_bits_vaddr),
+    .io_in_3_bits_needT  (io_in_3_bits_needT),
+    .io_in_3_bits_source (io_in_3_bits_source),
+    .io_in_4_ready       (io_in_4_ready),
+    .io_in_4_valid       (io_in_4_valid),
+    .io_in_4_bits_tag    (io_in_4_bits_tag),
+    .io_in_4_bits_set    (io_in_4_bits_set),
+    .io_in_4_bits_vaddr  (io_in_4_bits_vaddr),
+    .io_in_4_bits_needT  (io_in_4_bits_needT),
+    .io_in_4_bits_source (io_in_4_bits_source),
+    .io_in_5_ready       (io_in_5_ready),
+    .io_in_5_valid       (io_in_5_valid),
+    .io_in_5_bits_tag    (io_in_5_bits_tag),
+    .io_in_5_bits_set    (io_in_5_bits_set),
+    .io_in_5_bits_vaddr  (io_in_5_bits_vaddr),
+    .io_in_5_bits_needT  (io_in_5_bits_needT),
+    .io_in_5_bits_source (io_in_5_bits_source),
+    .io_in_6_ready       (io_in_6_ready),
+    .io_in_6_valid       (io_in_6_valid),
+    .io_in_6_bits_tag    (io_in_6_bits_tag),
+    .io_in_6_bits_set    (io_in_6_bits_set),
+    .io_in_6_bits_vaddr  (io_in_6_bits_vaddr),
+    .io_in_6_bits_needT  (io_in_6_bits_needT),
+    .io_in_6_bits_source (io_in_6_bits_source),
+    .io_in_7_ready       (io_in_7_ready),
+    .io_in_7_valid       (io_in_7_valid),
+    .io_in_7_bits_tag    (io_in_7_bits_tag),
+    .io_in_7_bits_set    (io_in_7_bits_set),
+    .io_in_7_bits_vaddr  (io_in_7_bits_vaddr),
+    .io_in_7_bits_needT  (io_in_7_bits_needT),
+    .io_in_7_bits_source (io_in_7_bits_source),
+    .io_out_ready        (io_out_ready & finalSelLow),
+    .io_out_valid        (_lowArb_io_out_valid),
+    .io_out_bits_tag     (_lowArb_io_out_bits_tag),
+    .io_out_bits_set     (_lowArb_io_out_bits_set),
+    .io_out_bits_vaddr   (_lowArb_io_out_bits_vaddr),
+    .io_out_bits_needT   (_lowArb_io_out_bits_needT),
+    .io_out_bits_source  (_lowArb_io_out_bits_source)
+  );
+  FastArbiter_6 highArb (
+    .clock               (clock),
+    .reset               (reset),
+    .io_in_0_ready       (io_in_8_ready),
+    .io_in_0_valid       (io_in_8_valid),
+    .io_in_0_bits_tag    (io_in_8_bits_tag),
+    .io_in_0_bits_set    (io_in_8_bits_set),
+    .io_in_0_bits_vaddr  (io_in_8_bits_vaddr),
+    .io_in_0_bits_needT  (io_in_8_bits_needT),
+    .io_in_0_bits_source (io_in_8_bits_source),
+    .io_in_1_ready       (io_in_9_ready),
+    .io_in_1_valid       (io_in_9_valid),
+    .io_in_1_bits_tag    (io_in_9_bits_tag),
+    .io_in_1_bits_set    (io_in_9_bits_set),
+    .io_in_1_bits_vaddr  (io_in_9_bits_vaddr),
+    .io_in_1_bits_needT  (io_in_9_bits_needT),
+    .io_in_1_bits_source (io_in_9_bits_source),
+    .io_in_2_ready       (io_in_10_ready),
+    .io_in_2_valid       (io_in_10_valid),
+    .io_in_2_bits_tag    (io_in_10_bits_tag),
+    .io_in_2_bits_set    (io_in_10_bits_set),
+    .io_in_2_bits_vaddr  (io_in_10_bits_vaddr),
+    .io_in_2_bits_needT  (io_in_10_bits_needT),
+    .io_in_2_bits_source (io_in_10_bits_source),
+    .io_in_3_ready       (io_in_11_ready),
+    .io_in_3_valid       (io_in_11_valid),
+    .io_in_3_bits_tag    (io_in_11_bits_tag),
+    .io_in_3_bits_set    (io_in_11_bits_set),
+    .io_in_3_bits_vaddr  (io_in_11_bits_vaddr),
+    .io_in_3_bits_needT  (io_in_11_bits_needT),
+    .io_in_3_bits_source (io_in_11_bits_source),
+    .io_in_4_ready       (io_in_12_ready),
+    .io_in_4_valid       (io_in_12_valid),
+    .io_in_4_bits_tag    (io_in_12_bits_tag),
+    .io_in_4_bits_set    (io_in_12_bits_set),
+    .io_in_4_bits_vaddr  (io_in_12_bits_vaddr),
+    .io_in_4_bits_needT  (io_in_12_bits_needT),
+    .io_in_4_bits_source (io_in_12_bits_source),
+    .io_in_5_ready       (io_in_13_ready),
+    .io_in_5_valid       (io_in_13_valid),
+    .io_in_5_bits_tag    (io_in_13_bits_tag),
+    .io_in_5_bits_set    (io_in_13_bits_set),
+    .io_in_5_bits_vaddr  (io_in_13_bits_vaddr),
+    .io_in_5_bits_needT  (io_in_13_bits_needT),
+    .io_in_5_bits_source (io_in_13_bits_source),
+    .io_in_6_ready       (io_in_14_ready),
+    .io_in_6_valid       (io_in_14_valid),
+    .io_in_6_bits_tag    (io_in_14_bits_tag),
+    .io_in_6_bits_set    (io_in_14_bits_set),
+    .io_in_6_bits_vaddr  (io_in_14_bits_vaddr),
+    .io_in_6_bits_needT  (io_in_14_bits_needT),
+    .io_in_6_bits_source (io_in_14_bits_source),
+    .io_in_7_ready       (io_in_15_ready),
+    .io_in_7_valid       (io_in_15_valid),
+    .io_in_7_bits_tag    (io_in_15_bits_tag),
+    .io_in_7_bits_set    (io_in_15_bits_set),
+    .io_in_7_bits_vaddr  (io_in_15_bits_vaddr),
+    .io_in_7_bits_needT  (io_in_15_bits_needT),
+    .io_in_7_bits_source (io_in_15_bits_source),
+    .io_out_ready        (io_out_ready & ~finalSelLow),
+    .io_out_valid        (_highArb_io_out_valid),
+    .io_out_bits_tag     (_highArb_io_out_bits_tag),
+    .io_out_bits_set     (_highArb_io_out_bits_set),
+    .io_out_bits_vaddr   (_highArb_io_out_bits_vaddr),
+    .io_out_bits_needT   (_highArb_io_out_bits_needT),
+    .io_out_bits_source  (_highArb_io_out_bits_source)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_tag =
+    finalSelLow ? _lowArb_io_out_bits_tag : _highArb_io_out_bits_tag;
+  assign io_out_bits_set =
+    finalSelLow ? _lowArb_io_out_bits_set : _highArb_io_out_bits_set;
+  assign io_out_bits_vaddr =
+    finalSelLow ? _lowArb_io_out_bits_vaddr : _highArb_io_out_bits_vaddr;
+  assign io_out_bits_needT =
+    finalSelLow ? _lowArb_io_out_bits_needT : _highArb_io_out_bits_needT;
+  assign io_out_bits_source =
+    finalSelLow ? _lowArb_io_out_bits_source : _highArb_io_out_bits_source;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_4.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_4.sv
new file mode 100644
index 0000000000..f2cd7d2521
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_4.sv
@@ -0,0 +1,1648 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_4(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [2:0]  io_in_0_bits_channel,
+  input  [2:0]  io_in_0_bits_txChannel,
+  input  [7:0]  io_in_0_bits_set,
+  input  [33:0] io_in_0_bits_tag,
+  input  [5:0]  io_in_0_bits_off,
+  input         io_in_0_bits_alias,
+  input  [43:0] io_in_0_bits_vaddr,
+  input         io_in_0_bits_isKeyword,
+  input  [3:0]  io_in_0_bits_opcode,
+  input  [2:0]  io_in_0_bits_param,
+  input  [2:0]  io_in_0_bits_size,
+  input  [6:0]  io_in_0_bits_sourceId,
+  input  [1:0]  io_in_0_bits_bufIdx,
+  input         io_in_0_bits_needProbeAckData,
+  input         io_in_0_bits_denied,
+  input         io_in_0_bits_corrupt,
+  input         io_in_0_bits_mshrTask,
+  input  [7:0]  io_in_0_bits_mshrId,
+  input         io_in_0_bits_aliasTask,
+  input         io_in_0_bits_useProbeData,
+  input         io_in_0_bits_mshrRetry,
+  input         io_in_0_bits_readProbeDataDown,
+  input         io_in_0_bits_fromL2pft,
+  input         io_in_0_bits_needHint,
+  input         io_in_0_bits_dirty,
+  input  [2:0]  io_in_0_bits_way,
+  input         io_in_0_bits_meta_dirty,
+  input  [1:0]  io_in_0_bits_meta_state,
+  input         io_in_0_bits_meta_clients,
+  input         io_in_0_bits_meta_alias,
+  input         io_in_0_bits_meta_prefetch,
+  input  [3:0]  io_in_0_bits_meta_prefetchSrc,
+  input         io_in_0_bits_meta_accessed,
+  input         io_in_0_bits_meta_tagErr,
+  input         io_in_0_bits_meta_dataErr,
+  input         io_in_0_bits_metaWen,
+  input         io_in_0_bits_tagWen,
+  input         io_in_0_bits_dsWen,
+  input  [7:0]  io_in_0_bits_wayMask,
+  input         io_in_0_bits_replTask,
+  input         io_in_0_bits_cmoTask,
+  input         io_in_0_bits_cmoAll,
+  input  [4:0]  io_in_0_bits_reqSource,
+  input         io_in_0_bits_mergeA,
+  input  [5:0]  io_in_0_bits_aMergeTask_off,
+  input         io_in_0_bits_aMergeTask_alias,
+  input  [43:0] io_in_0_bits_aMergeTask_vaddr,
+  input         io_in_0_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_0_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_0_bits_aMergeTask_param,
+  input  [6:0]  io_in_0_bits_aMergeTask_sourceId,
+  input         io_in_0_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_0_bits_aMergeTask_meta_state,
+  input         io_in_0_bits_aMergeTask_meta_clients,
+  input         io_in_0_bits_aMergeTask_meta_alias,
+  input         io_in_0_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_in_0_bits_aMergeTask_meta_prefetchSrc,
+  input         io_in_0_bits_aMergeTask_meta_accessed,
+  input         io_in_0_bits_aMergeTask_meta_tagErr,
+  input         io_in_0_bits_aMergeTask_meta_dataErr,
+  input         io_in_0_bits_snpHitRelease,
+  input         io_in_0_bits_snpHitReleaseToInval,
+  input         io_in_0_bits_snpHitReleaseToClean,
+  input         io_in_0_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_0_bits_snpHitReleaseIdx,
+  input         io_in_0_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_0_bits_snpHitReleaseMeta_state,
+  input         io_in_0_bits_snpHitReleaseMeta_clients,
+  input         io_in_0_bits_snpHitReleaseMeta_alias,
+  input         io_in_0_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_0_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_0_bits_snpHitReleaseMeta_accessed,
+  input         io_in_0_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_0_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [10:0] io_in_0_bits_srcID,
+  input  [11:0] io_in_0_bits_txnID,
+  input  [10:0] io_in_0_bits_homeNID,
+  input  [11:0] io_in_0_bits_dbID,
+  input  [10:0] io_in_0_bits_fwdNID,
+  input  [11:0] io_in_0_bits_fwdTxnID,
+  input  [6:0]  io_in_0_bits_chiOpcode,
+  input  [2:0]  io_in_0_bits_resp,
+  input  [2:0]  io_in_0_bits_fwdState,
+  input  [3:0]  io_in_0_bits_pCrdType,
+  input         io_in_0_bits_retToSrc,
+  input         io_in_0_bits_likelyshared,
+  input         io_in_0_bits_expCompAck,
+  input         io_in_0_bits_allowRetry,
+  input         io_in_0_bits_memAttr_allocate,
+  input         io_in_0_bits_memAttr_cacheable,
+  input         io_in_0_bits_memAttr_device,
+  input         io_in_0_bits_memAttr_ewa,
+  input         io_in_0_bits_traceTag,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [2:0]  io_in_1_bits_channel,
+  input  [2:0]  io_in_1_bits_txChannel,
+  input  [7:0]  io_in_1_bits_set,
+  input  [33:0] io_in_1_bits_tag,
+  input  [5:0]  io_in_1_bits_off,
+  input         io_in_1_bits_alias,
+  input  [43:0] io_in_1_bits_vaddr,
+  input         io_in_1_bits_isKeyword,
+  input  [3:0]  io_in_1_bits_opcode,
+  input  [2:0]  io_in_1_bits_param,
+  input  [2:0]  io_in_1_bits_size,
+  input  [6:0]  io_in_1_bits_sourceId,
+  input  [1:0]  io_in_1_bits_bufIdx,
+  input         io_in_1_bits_needProbeAckData,
+  input         io_in_1_bits_denied,
+  input         io_in_1_bits_corrupt,
+  input         io_in_1_bits_mshrTask,
+  input  [7:0]  io_in_1_bits_mshrId,
+  input         io_in_1_bits_aliasTask,
+  input         io_in_1_bits_useProbeData,
+  input         io_in_1_bits_mshrRetry,
+  input         io_in_1_bits_readProbeDataDown,
+  input         io_in_1_bits_fromL2pft,
+  input         io_in_1_bits_needHint,
+  input         io_in_1_bits_dirty,
+  input  [2:0]  io_in_1_bits_way,
+  input         io_in_1_bits_meta_dirty,
+  input  [1:0]  io_in_1_bits_meta_state,
+  input         io_in_1_bits_meta_clients,
+  input         io_in_1_bits_meta_alias,
+  input         io_in_1_bits_meta_prefetch,
+  input  [3:0]  io_in_1_bits_meta_prefetchSrc,
+  input         io_in_1_bits_meta_accessed,
+  input         io_in_1_bits_meta_tagErr,
+  input         io_in_1_bits_meta_dataErr,
+  input         io_in_1_bits_metaWen,
+  input         io_in_1_bits_tagWen,
+  input         io_in_1_bits_dsWen,
+  input  [7:0]  io_in_1_bits_wayMask,
+  input         io_in_1_bits_replTask,
+  input         io_in_1_bits_cmoTask,
+  input         io_in_1_bits_cmoAll,
+  input  [4:0]  io_in_1_bits_reqSource,
+  input         io_in_1_bits_mergeA,
+  input  [5:0]  io_in_1_bits_aMergeTask_off,
+  input         io_in_1_bits_aMergeTask_alias,
+  input  [43:0] io_in_1_bits_aMergeTask_vaddr,
+  input         io_in_1_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_1_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_1_bits_aMergeTask_param,
+  input  [6:0]  io_in_1_bits_aMergeTask_sourceId,
+  input         io_in_1_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_1_bits_aMergeTask_meta_state,
+  input         io_in_1_bits_aMergeTask_meta_clients,
+  input         io_in_1_bits_aMergeTask_meta_alias,
+  input         io_in_1_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_in_1_bits_aMergeTask_meta_prefetchSrc,
+  input         io_in_1_bits_aMergeTask_meta_accessed,
+  input         io_in_1_bits_aMergeTask_meta_tagErr,
+  input         io_in_1_bits_aMergeTask_meta_dataErr,
+  input         io_in_1_bits_snpHitRelease,
+  input         io_in_1_bits_snpHitReleaseToInval,
+  input         io_in_1_bits_snpHitReleaseToClean,
+  input         io_in_1_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_1_bits_snpHitReleaseIdx,
+  input         io_in_1_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_1_bits_snpHitReleaseMeta_state,
+  input         io_in_1_bits_snpHitReleaseMeta_clients,
+  input         io_in_1_bits_snpHitReleaseMeta_alias,
+  input         io_in_1_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_1_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_1_bits_snpHitReleaseMeta_accessed,
+  input         io_in_1_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_1_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [10:0] io_in_1_bits_srcID,
+  input  [11:0] io_in_1_bits_txnID,
+  input  [10:0] io_in_1_bits_homeNID,
+  input  [11:0] io_in_1_bits_dbID,
+  input  [10:0] io_in_1_bits_fwdNID,
+  input  [11:0] io_in_1_bits_fwdTxnID,
+  input  [6:0]  io_in_1_bits_chiOpcode,
+  input  [2:0]  io_in_1_bits_resp,
+  input  [2:0]  io_in_1_bits_fwdState,
+  input  [3:0]  io_in_1_bits_pCrdType,
+  input         io_in_1_bits_retToSrc,
+  input         io_in_1_bits_likelyshared,
+  input         io_in_1_bits_expCompAck,
+  input         io_in_1_bits_allowRetry,
+  input         io_in_1_bits_memAttr_allocate,
+  input         io_in_1_bits_memAttr_cacheable,
+  input         io_in_1_bits_memAttr_device,
+  input         io_in_1_bits_memAttr_ewa,
+  input         io_in_1_bits_traceTag,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [2:0]  io_in_2_bits_channel,
+  input  [2:0]  io_in_2_bits_txChannel,
+  input  [7:0]  io_in_2_bits_set,
+  input  [33:0] io_in_2_bits_tag,
+  input  [5:0]  io_in_2_bits_off,
+  input         io_in_2_bits_alias,
+  input  [43:0] io_in_2_bits_vaddr,
+  input         io_in_2_bits_isKeyword,
+  input  [3:0]  io_in_2_bits_opcode,
+  input  [2:0]  io_in_2_bits_param,
+  input  [2:0]  io_in_2_bits_size,
+  input  [6:0]  io_in_2_bits_sourceId,
+  input  [1:0]  io_in_2_bits_bufIdx,
+  input         io_in_2_bits_needProbeAckData,
+  input         io_in_2_bits_denied,
+  input         io_in_2_bits_corrupt,
+  input         io_in_2_bits_mshrTask,
+  input  [7:0]  io_in_2_bits_mshrId,
+  input         io_in_2_bits_aliasTask,
+  input         io_in_2_bits_useProbeData,
+  input         io_in_2_bits_mshrRetry,
+  input         io_in_2_bits_readProbeDataDown,
+  input         io_in_2_bits_fromL2pft,
+  input         io_in_2_bits_needHint,
+  input         io_in_2_bits_dirty,
+  input  [2:0]  io_in_2_bits_way,
+  input         io_in_2_bits_meta_dirty,
+  input  [1:0]  io_in_2_bits_meta_state,
+  input         io_in_2_bits_meta_clients,
+  input         io_in_2_bits_meta_alias,
+  input         io_in_2_bits_meta_prefetch,
+  input  [3:0]  io_in_2_bits_meta_prefetchSrc,
+  input         io_in_2_bits_meta_accessed,
+  input         io_in_2_bits_meta_tagErr,
+  input         io_in_2_bits_meta_dataErr,
+  input         io_in_2_bits_metaWen,
+  input         io_in_2_bits_tagWen,
+  input         io_in_2_bits_dsWen,
+  input  [7:0]  io_in_2_bits_wayMask,
+  input         io_in_2_bits_replTask,
+  input         io_in_2_bits_cmoTask,
+  input         io_in_2_bits_cmoAll,
+  input  [4:0]  io_in_2_bits_reqSource,
+  input         io_in_2_bits_mergeA,
+  input  [5:0]  io_in_2_bits_aMergeTask_off,
+  input         io_in_2_bits_aMergeTask_alias,
+  input  [43:0] io_in_2_bits_aMergeTask_vaddr,
+  input         io_in_2_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_2_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_2_bits_aMergeTask_param,
+  input  [6:0]  io_in_2_bits_aMergeTask_sourceId,
+  input         io_in_2_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_2_bits_aMergeTask_meta_state,
+  input         io_in_2_bits_aMergeTask_meta_clients,
+  input         io_in_2_bits_aMergeTask_meta_alias,
+  input         io_in_2_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_in_2_bits_aMergeTask_meta_prefetchSrc,
+  input         io_in_2_bits_aMergeTask_meta_accessed,
+  input         io_in_2_bits_aMergeTask_meta_tagErr,
+  input         io_in_2_bits_aMergeTask_meta_dataErr,
+  input         io_in_2_bits_snpHitRelease,
+  input         io_in_2_bits_snpHitReleaseToInval,
+  input         io_in_2_bits_snpHitReleaseToClean,
+  input         io_in_2_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_2_bits_snpHitReleaseIdx,
+  input         io_in_2_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_2_bits_snpHitReleaseMeta_state,
+  input         io_in_2_bits_snpHitReleaseMeta_clients,
+  input         io_in_2_bits_snpHitReleaseMeta_alias,
+  input         io_in_2_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_2_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_2_bits_snpHitReleaseMeta_accessed,
+  input         io_in_2_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_2_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_2_bits_tgtID,
+  input  [10:0] io_in_2_bits_srcID,
+  input  [11:0] io_in_2_bits_txnID,
+  input  [10:0] io_in_2_bits_homeNID,
+  input  [11:0] io_in_2_bits_dbID,
+  input  [10:0] io_in_2_bits_fwdNID,
+  input  [11:0] io_in_2_bits_fwdTxnID,
+  input  [6:0]  io_in_2_bits_chiOpcode,
+  input  [2:0]  io_in_2_bits_resp,
+  input  [2:0]  io_in_2_bits_fwdState,
+  input  [3:0]  io_in_2_bits_pCrdType,
+  input         io_in_2_bits_retToSrc,
+  input         io_in_2_bits_likelyshared,
+  input         io_in_2_bits_expCompAck,
+  input         io_in_2_bits_allowRetry,
+  input         io_in_2_bits_memAttr_allocate,
+  input         io_in_2_bits_memAttr_cacheable,
+  input         io_in_2_bits_memAttr_device,
+  input         io_in_2_bits_memAttr_ewa,
+  input         io_in_2_bits_traceTag,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [2:0]  io_in_3_bits_channel,
+  input  [2:0]  io_in_3_bits_txChannel,
+  input  [7:0]  io_in_3_bits_set,
+  input  [33:0] io_in_3_bits_tag,
+  input  [5:0]  io_in_3_bits_off,
+  input         io_in_3_bits_alias,
+  input  [43:0] io_in_3_bits_vaddr,
+  input         io_in_3_bits_isKeyword,
+  input  [3:0]  io_in_3_bits_opcode,
+  input  [2:0]  io_in_3_bits_param,
+  input  [2:0]  io_in_3_bits_size,
+  input  [6:0]  io_in_3_bits_sourceId,
+  input  [1:0]  io_in_3_bits_bufIdx,
+  input         io_in_3_bits_needProbeAckData,
+  input         io_in_3_bits_denied,
+  input         io_in_3_bits_corrupt,
+  input         io_in_3_bits_mshrTask,
+  input  [7:0]  io_in_3_bits_mshrId,
+  input         io_in_3_bits_aliasTask,
+  input         io_in_3_bits_useProbeData,
+  input         io_in_3_bits_mshrRetry,
+  input         io_in_3_bits_readProbeDataDown,
+  input         io_in_3_bits_fromL2pft,
+  input         io_in_3_bits_needHint,
+  input         io_in_3_bits_dirty,
+  input  [2:0]  io_in_3_bits_way,
+  input         io_in_3_bits_meta_dirty,
+  input  [1:0]  io_in_3_bits_meta_state,
+  input         io_in_3_bits_meta_clients,
+  input         io_in_3_bits_meta_alias,
+  input         io_in_3_bits_meta_prefetch,
+  input  [3:0]  io_in_3_bits_meta_prefetchSrc,
+  input         io_in_3_bits_meta_accessed,
+  input         io_in_3_bits_meta_tagErr,
+  input         io_in_3_bits_meta_dataErr,
+  input         io_in_3_bits_metaWen,
+  input         io_in_3_bits_tagWen,
+  input         io_in_3_bits_dsWen,
+  input  [7:0]  io_in_3_bits_wayMask,
+  input         io_in_3_bits_replTask,
+  input         io_in_3_bits_cmoTask,
+  input         io_in_3_bits_cmoAll,
+  input  [4:0]  io_in_3_bits_reqSource,
+  input         io_in_3_bits_mergeA,
+  input  [5:0]  io_in_3_bits_aMergeTask_off,
+  input         io_in_3_bits_aMergeTask_alias,
+  input  [43:0] io_in_3_bits_aMergeTask_vaddr,
+  input         io_in_3_bits_aMergeTask_isKeyword,
+  input  [2:0]  io_in_3_bits_aMergeTask_opcode,
+  input  [2:0]  io_in_3_bits_aMergeTask_param,
+  input  [6:0]  io_in_3_bits_aMergeTask_sourceId,
+  input         io_in_3_bits_aMergeTask_meta_dirty,
+  input  [1:0]  io_in_3_bits_aMergeTask_meta_state,
+  input         io_in_3_bits_aMergeTask_meta_clients,
+  input         io_in_3_bits_aMergeTask_meta_alias,
+  input         io_in_3_bits_aMergeTask_meta_prefetch,
+  input  [3:0]  io_in_3_bits_aMergeTask_meta_prefetchSrc,
+  input         io_in_3_bits_aMergeTask_meta_accessed,
+  input         io_in_3_bits_aMergeTask_meta_tagErr,
+  input         io_in_3_bits_aMergeTask_meta_dataErr,
+  input         io_in_3_bits_snpHitRelease,
+  input         io_in_3_bits_snpHitReleaseToInval,
+  input         io_in_3_bits_snpHitReleaseToClean,
+  input         io_in_3_bits_snpHitReleaseWithData,
+  input  [7:0]  io_in_3_bits_snpHitReleaseIdx,
+  input         io_in_3_bits_snpHitReleaseMeta_dirty,
+  input  [1:0]  io_in_3_bits_snpHitReleaseMeta_state,
+  input         io_in_3_bits_snpHitReleaseMeta_clients,
+  input         io_in_3_bits_snpHitReleaseMeta_alias,
+  input         io_in_3_bits_snpHitReleaseMeta_prefetch,
+  input  [3:0]  io_in_3_bits_snpHitReleaseMeta_prefetchSrc,
+  input         io_in_3_bits_snpHitReleaseMeta_accessed,
+  input         io_in_3_bits_snpHitReleaseMeta_tagErr,
+  input         io_in_3_bits_snpHitReleaseMeta_dataErr,
+  input  [10:0] io_in_3_bits_tgtID,
+  input  [10:0] io_in_3_bits_srcID,
+  input  [11:0] io_in_3_bits_txnID,
+  input  [10:0] io_in_3_bits_homeNID,
+  input  [11:0] io_in_3_bits_dbID,
+  input  [10:0] io_in_3_bits_fwdNID,
+  input  [11:0] io_in_3_bits_fwdTxnID,
+  input  [6:0]  io_in_3_bits_chiOpcode,
+  input  [2:0]  io_in_3_bits_resp,
+  input  [2:0]  io_in_3_bits_fwdState,
+  input  [3:0]  io_in_3_bits_pCrdType,
+  input         io_in_3_bits_retToSrc,
+  input         io_in_3_bits_likelyshared,
+  input         io_in_3_bits_expCompAck,
+  input         io_in_3_bits_allowRetry,
+  input         io_in_3_bits_memAttr_allocate,
+  input         io_in_3_bits_memAttr_cacheable,
+  input         io_in_3_bits_memAttr_device,
+  input         io_in_3_bits_memAttr_ewa,
+  input         io_in_3_bits_traceTag,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [2:0]  io_out_bits_channel,
+  output [2:0]  io_out_bits_txChannel,
+  output [7:0]  io_out_bits_set,
+  output [33:0] io_out_bits_tag,
+  output [5:0]  io_out_bits_off,
+  output        io_out_bits_alias,
+  output [43:0] io_out_bits_vaddr,
+  output        io_out_bits_isKeyword,
+  output [3:0]  io_out_bits_opcode,
+  output [2:0]  io_out_bits_param,
+  output [2:0]  io_out_bits_size,
+  output [6:0]  io_out_bits_sourceId,
+  output [1:0]  io_out_bits_bufIdx,
+  output        io_out_bits_needProbeAckData,
+  output        io_out_bits_denied,
+  output        io_out_bits_corrupt,
+  output        io_out_bits_mshrTask,
+  output [7:0]  io_out_bits_mshrId,
+  output        io_out_bits_aliasTask,
+  output        io_out_bits_useProbeData,
+  output        io_out_bits_mshrRetry,
+  output        io_out_bits_readProbeDataDown,
+  output        io_out_bits_fromL2pft,
+  output        io_out_bits_needHint,
+  output        io_out_bits_dirty,
+  output [2:0]  io_out_bits_way,
+  output        io_out_bits_meta_dirty,
+  output [1:0]  io_out_bits_meta_state,
+  output        io_out_bits_meta_clients,
+  output        io_out_bits_meta_alias,
+  output        io_out_bits_meta_prefetch,
+  output [3:0]  io_out_bits_meta_prefetchSrc,
+  output        io_out_bits_meta_accessed,
+  output        io_out_bits_meta_tagErr,
+  output        io_out_bits_meta_dataErr,
+  output        io_out_bits_metaWen,
+  output        io_out_bits_tagWen,
+  output        io_out_bits_dsWen,
+  output [7:0]  io_out_bits_wayMask,
+  output        io_out_bits_replTask,
+  output        io_out_bits_cmoTask,
+  output        io_out_bits_cmoAll,
+  output [4:0]  io_out_bits_reqSource,
+  output        io_out_bits_mergeA,
+  output [5:0]  io_out_bits_aMergeTask_off,
+  output        io_out_bits_aMergeTask_alias,
+  output [43:0] io_out_bits_aMergeTask_vaddr,
+  output        io_out_bits_aMergeTask_isKeyword,
+  output [2:0]  io_out_bits_aMergeTask_opcode,
+  output [2:0]  io_out_bits_aMergeTask_param,
+  output [6:0]  io_out_bits_aMergeTask_sourceId,
+  output        io_out_bits_aMergeTask_meta_dirty,
+  output [1:0]  io_out_bits_aMergeTask_meta_state,
+  output        io_out_bits_aMergeTask_meta_clients,
+  output        io_out_bits_aMergeTask_meta_alias,
+  output        io_out_bits_aMergeTask_meta_prefetch,
+  output [3:0]  io_out_bits_aMergeTask_meta_prefetchSrc,
+  output        io_out_bits_aMergeTask_meta_accessed,
+  output        io_out_bits_aMergeTask_meta_tagErr,
+  output        io_out_bits_aMergeTask_meta_dataErr,
+  output        io_out_bits_snpHitRelease,
+  output        io_out_bits_snpHitReleaseToInval,
+  output        io_out_bits_snpHitReleaseToClean,
+  output        io_out_bits_snpHitReleaseWithData,
+  output [7:0]  io_out_bits_snpHitReleaseIdx,
+  output        io_out_bits_snpHitReleaseMeta_dirty,
+  output [1:0]  io_out_bits_snpHitReleaseMeta_state,
+  output        io_out_bits_snpHitReleaseMeta_clients,
+  output        io_out_bits_snpHitReleaseMeta_alias,
+  output        io_out_bits_snpHitReleaseMeta_prefetch,
+  output [3:0]  io_out_bits_snpHitReleaseMeta_prefetchSrc,
+  output        io_out_bits_snpHitReleaseMeta_accessed,
+  output        io_out_bits_snpHitReleaseMeta_tagErr,
+  output        io_out_bits_snpHitReleaseMeta_dataErr,
+  output [10:0] io_out_bits_tgtID,
+  output [10:0] io_out_bits_srcID,
+  output [11:0] io_out_bits_txnID,
+  output [10:0] io_out_bits_homeNID,
+  output [11:0] io_out_bits_dbID,
+  output [10:0] io_out_bits_fwdNID,
+  output [11:0] io_out_bits_fwdTxnID,
+  output [6:0]  io_out_bits_chiOpcode,
+  output [2:0]  io_out_bits_resp,
+  output [2:0]  io_out_bits_fwdState,
+  output [3:0]  io_out_bits_pCrdType,
+  output        io_out_bits_retToSrc,
+  output        io_out_bits_likelyshared,
+  output        io_out_bits_expCompAck,
+  output        io_out_bits_allowRetry,
+  output        io_out_bits_memAttr_allocate,
+  output        io_out_bits_memAttr_cacheable,
+  output        io_out_bits_memAttr_device,
+  output        io_out_bits_memAttr_ewa,
+  output        io_out_bits_traceTag
+);
+
+  wire        _highArb_io_out_valid;
+  wire [2:0]  _highArb_io_out_bits_channel;
+  wire [2:0]  _highArb_io_out_bits_txChannel;
+  wire [7:0]  _highArb_io_out_bits_set;
+  wire [33:0] _highArb_io_out_bits_tag;
+  wire [5:0]  _highArb_io_out_bits_off;
+  wire        _highArb_io_out_bits_alias;
+  wire [43:0] _highArb_io_out_bits_vaddr;
+  wire        _highArb_io_out_bits_isKeyword;
+  wire [3:0]  _highArb_io_out_bits_opcode;
+  wire [2:0]  _highArb_io_out_bits_param;
+  wire [2:0]  _highArb_io_out_bits_size;
+  wire [6:0]  _highArb_io_out_bits_sourceId;
+  wire [1:0]  _highArb_io_out_bits_bufIdx;
+  wire        _highArb_io_out_bits_needProbeAckData;
+  wire        _highArb_io_out_bits_denied;
+  wire        _highArb_io_out_bits_corrupt;
+  wire        _highArb_io_out_bits_mshrTask;
+  wire [7:0]  _highArb_io_out_bits_mshrId;
+  wire        _highArb_io_out_bits_aliasTask;
+  wire        _highArb_io_out_bits_useProbeData;
+  wire        _highArb_io_out_bits_mshrRetry;
+  wire        _highArb_io_out_bits_readProbeDataDown;
+  wire        _highArb_io_out_bits_fromL2pft;
+  wire        _highArb_io_out_bits_needHint;
+  wire        _highArb_io_out_bits_dirty;
+  wire [2:0]  _highArb_io_out_bits_way;
+  wire        _highArb_io_out_bits_meta_dirty;
+  wire [1:0]  _highArb_io_out_bits_meta_state;
+  wire        _highArb_io_out_bits_meta_clients;
+  wire        _highArb_io_out_bits_meta_alias;
+  wire        _highArb_io_out_bits_meta_prefetch;
+  wire [3:0]  _highArb_io_out_bits_meta_prefetchSrc;
+  wire        _highArb_io_out_bits_meta_accessed;
+  wire        _highArb_io_out_bits_meta_tagErr;
+  wire        _highArb_io_out_bits_meta_dataErr;
+  wire        _highArb_io_out_bits_metaWen;
+  wire        _highArb_io_out_bits_tagWen;
+  wire        _highArb_io_out_bits_dsWen;
+  wire [7:0]  _highArb_io_out_bits_wayMask;
+  wire        _highArb_io_out_bits_replTask;
+  wire        _highArb_io_out_bits_cmoTask;
+  wire        _highArb_io_out_bits_cmoAll;
+  wire [4:0]  _highArb_io_out_bits_reqSource;
+  wire        _highArb_io_out_bits_mergeA;
+  wire [5:0]  _highArb_io_out_bits_aMergeTask_off;
+  wire        _highArb_io_out_bits_aMergeTask_alias;
+  wire [43:0] _highArb_io_out_bits_aMergeTask_vaddr;
+  wire        _highArb_io_out_bits_aMergeTask_isKeyword;
+  wire [2:0]  _highArb_io_out_bits_aMergeTask_opcode;
+  wire [2:0]  _highArb_io_out_bits_aMergeTask_param;
+  wire [6:0]  _highArb_io_out_bits_aMergeTask_sourceId;
+  wire        _highArb_io_out_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _highArb_io_out_bits_aMergeTask_meta_state;
+  wire        _highArb_io_out_bits_aMergeTask_meta_clients;
+  wire        _highArb_io_out_bits_aMergeTask_meta_alias;
+  wire        _highArb_io_out_bits_aMergeTask_meta_prefetch;
+  wire [3:0]  _highArb_io_out_bits_aMergeTask_meta_prefetchSrc;
+  wire        _highArb_io_out_bits_aMergeTask_meta_accessed;
+  wire        _highArb_io_out_bits_aMergeTask_meta_tagErr;
+  wire        _highArb_io_out_bits_aMergeTask_meta_dataErr;
+  wire        _highArb_io_out_bits_snpHitRelease;
+  wire        _highArb_io_out_bits_snpHitReleaseToInval;
+  wire        _highArb_io_out_bits_snpHitReleaseToClean;
+  wire        _highArb_io_out_bits_snpHitReleaseWithData;
+  wire [7:0]  _highArb_io_out_bits_snpHitReleaseIdx;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _highArb_io_out_bits_snpHitReleaseMeta_state;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_clients;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_alias;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _highArb_io_out_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_accessed;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_tagErr;
+  wire        _highArb_io_out_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _highArb_io_out_bits_tgtID;
+  wire [10:0] _highArb_io_out_bits_srcID;
+  wire [11:0] _highArb_io_out_bits_txnID;
+  wire [10:0] _highArb_io_out_bits_homeNID;
+  wire [11:0] _highArb_io_out_bits_dbID;
+  wire [10:0] _highArb_io_out_bits_fwdNID;
+  wire [11:0] _highArb_io_out_bits_fwdTxnID;
+  wire [6:0]  _highArb_io_out_bits_chiOpcode;
+  wire [2:0]  _highArb_io_out_bits_resp;
+  wire [2:0]  _highArb_io_out_bits_fwdState;
+  wire [3:0]  _highArb_io_out_bits_pCrdType;
+  wire        _highArb_io_out_bits_retToSrc;
+  wire        _highArb_io_out_bits_likelyshared;
+  wire        _highArb_io_out_bits_expCompAck;
+  wire        _highArb_io_out_bits_allowRetry;
+  wire        _highArb_io_out_bits_memAttr_allocate;
+  wire        _highArb_io_out_bits_memAttr_cacheable;
+  wire        _highArb_io_out_bits_memAttr_device;
+  wire        _highArb_io_out_bits_memAttr_ewa;
+  wire        _highArb_io_out_bits_traceTag;
+  wire        _lowArb_io_out_valid;
+  wire [2:0]  _lowArb_io_out_bits_channel;
+  wire [2:0]  _lowArb_io_out_bits_txChannel;
+  wire [7:0]  _lowArb_io_out_bits_set;
+  wire [33:0] _lowArb_io_out_bits_tag;
+  wire [5:0]  _lowArb_io_out_bits_off;
+  wire        _lowArb_io_out_bits_alias;
+  wire [43:0] _lowArb_io_out_bits_vaddr;
+  wire        _lowArb_io_out_bits_isKeyword;
+  wire [3:0]  _lowArb_io_out_bits_opcode;
+  wire [2:0]  _lowArb_io_out_bits_param;
+  wire [2:0]  _lowArb_io_out_bits_size;
+  wire [6:0]  _lowArb_io_out_bits_sourceId;
+  wire [1:0]  _lowArb_io_out_bits_bufIdx;
+  wire        _lowArb_io_out_bits_needProbeAckData;
+  wire        _lowArb_io_out_bits_denied;
+  wire        _lowArb_io_out_bits_corrupt;
+  wire        _lowArb_io_out_bits_mshrTask;
+  wire [7:0]  _lowArb_io_out_bits_mshrId;
+  wire        _lowArb_io_out_bits_aliasTask;
+  wire        _lowArb_io_out_bits_useProbeData;
+  wire        _lowArb_io_out_bits_mshrRetry;
+  wire        _lowArb_io_out_bits_readProbeDataDown;
+  wire        _lowArb_io_out_bits_fromL2pft;
+  wire        _lowArb_io_out_bits_needHint;
+  wire        _lowArb_io_out_bits_dirty;
+  wire [2:0]  _lowArb_io_out_bits_way;
+  wire        _lowArb_io_out_bits_meta_dirty;
+  wire [1:0]  _lowArb_io_out_bits_meta_state;
+  wire        _lowArb_io_out_bits_meta_clients;
+  wire        _lowArb_io_out_bits_meta_alias;
+  wire        _lowArb_io_out_bits_meta_prefetch;
+  wire [3:0]  _lowArb_io_out_bits_meta_prefetchSrc;
+  wire        _lowArb_io_out_bits_meta_accessed;
+  wire        _lowArb_io_out_bits_meta_tagErr;
+  wire        _lowArb_io_out_bits_meta_dataErr;
+  wire        _lowArb_io_out_bits_metaWen;
+  wire        _lowArb_io_out_bits_tagWen;
+  wire        _lowArb_io_out_bits_dsWen;
+  wire [7:0]  _lowArb_io_out_bits_wayMask;
+  wire        _lowArb_io_out_bits_replTask;
+  wire        _lowArb_io_out_bits_cmoTask;
+  wire        _lowArb_io_out_bits_cmoAll;
+  wire [4:0]  _lowArb_io_out_bits_reqSource;
+  wire        _lowArb_io_out_bits_mergeA;
+  wire [5:0]  _lowArb_io_out_bits_aMergeTask_off;
+  wire        _lowArb_io_out_bits_aMergeTask_alias;
+  wire [43:0] _lowArb_io_out_bits_aMergeTask_vaddr;
+  wire        _lowArb_io_out_bits_aMergeTask_isKeyword;
+  wire [2:0]  _lowArb_io_out_bits_aMergeTask_opcode;
+  wire [2:0]  _lowArb_io_out_bits_aMergeTask_param;
+  wire [6:0]  _lowArb_io_out_bits_aMergeTask_sourceId;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_dirty;
+  wire [1:0]  _lowArb_io_out_bits_aMergeTask_meta_state;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_clients;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_alias;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_prefetch;
+  wire [3:0]  _lowArb_io_out_bits_aMergeTask_meta_prefetchSrc;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_accessed;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_tagErr;
+  wire        _lowArb_io_out_bits_aMergeTask_meta_dataErr;
+  wire        _lowArb_io_out_bits_snpHitRelease;
+  wire        _lowArb_io_out_bits_snpHitReleaseToInval;
+  wire        _lowArb_io_out_bits_snpHitReleaseToClean;
+  wire        _lowArb_io_out_bits_snpHitReleaseWithData;
+  wire [7:0]  _lowArb_io_out_bits_snpHitReleaseIdx;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_dirty;
+  wire [1:0]  _lowArb_io_out_bits_snpHitReleaseMeta_state;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_clients;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_alias;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_prefetch;
+  wire [3:0]  _lowArb_io_out_bits_snpHitReleaseMeta_prefetchSrc;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_accessed;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_tagErr;
+  wire        _lowArb_io_out_bits_snpHitReleaseMeta_dataErr;
+  wire [10:0] _lowArb_io_out_bits_tgtID;
+  wire [10:0] _lowArb_io_out_bits_srcID;
+  wire [11:0] _lowArb_io_out_bits_txnID;
+  wire [10:0] _lowArb_io_out_bits_homeNID;
+  wire [11:0] _lowArb_io_out_bits_dbID;
+  wire [10:0] _lowArb_io_out_bits_fwdNID;
+  wire [11:0] _lowArb_io_out_bits_fwdTxnID;
+  wire [6:0]  _lowArb_io_out_bits_chiOpcode;
+  wire [2:0]  _lowArb_io_out_bits_resp;
+  wire [2:0]  _lowArb_io_out_bits_fwdState;
+  wire [3:0]  _lowArb_io_out_bits_pCrdType;
+  wire        _lowArb_io_out_bits_retToSrc;
+  wire        _lowArb_io_out_bits_likelyshared;
+  wire        _lowArb_io_out_bits_expCompAck;
+  wire        _lowArb_io_out_bits_allowRetry;
+  wire        _lowArb_io_out_bits_memAttr_allocate;
+  wire        _lowArb_io_out_bits_memAttr_cacheable;
+  wire        _lowArb_io_out_bits_memAttr_device;
+  wire        _lowArb_io_out_bits_memAttr_ewa;
+  wire        _lowArb_io_out_bits_traceTag;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_ready & io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_10 lowArb (
+    .clock                                      (clock),
+    .reset                                      (reset),
+    .io_in_0_ready                              (io_in_0_ready),
+    .io_in_0_valid                              (io_in_0_valid),
+    .io_in_0_bits_channel                       (io_in_0_bits_channel),
+    .io_in_0_bits_txChannel                     (io_in_0_bits_txChannel),
+    .io_in_0_bits_set                           (io_in_0_bits_set),
+    .io_in_0_bits_tag                           (io_in_0_bits_tag),
+    .io_in_0_bits_off                           (io_in_0_bits_off),
+    .io_in_0_bits_alias                         (io_in_0_bits_alias),
+    .io_in_0_bits_vaddr                         (io_in_0_bits_vaddr),
+    .io_in_0_bits_isKeyword                     (io_in_0_bits_isKeyword),
+    .io_in_0_bits_opcode                        (io_in_0_bits_opcode),
+    .io_in_0_bits_param                         (io_in_0_bits_param),
+    .io_in_0_bits_size                          (io_in_0_bits_size),
+    .io_in_0_bits_sourceId                      (io_in_0_bits_sourceId),
+    .io_in_0_bits_bufIdx                        (io_in_0_bits_bufIdx),
+    .io_in_0_bits_needProbeAckData              (io_in_0_bits_needProbeAckData),
+    .io_in_0_bits_denied                        (io_in_0_bits_denied),
+    .io_in_0_bits_corrupt                       (io_in_0_bits_corrupt),
+    .io_in_0_bits_mshrTask                      (io_in_0_bits_mshrTask),
+    .io_in_0_bits_mshrId                        (io_in_0_bits_mshrId),
+    .io_in_0_bits_aliasTask                     (io_in_0_bits_aliasTask),
+    .io_in_0_bits_useProbeData                  (io_in_0_bits_useProbeData),
+    .io_in_0_bits_mshrRetry                     (io_in_0_bits_mshrRetry),
+    .io_in_0_bits_readProbeDataDown             (io_in_0_bits_readProbeDataDown),
+    .io_in_0_bits_fromL2pft                     (io_in_0_bits_fromL2pft),
+    .io_in_0_bits_needHint                      (io_in_0_bits_needHint),
+    .io_in_0_bits_dirty                         (io_in_0_bits_dirty),
+    .io_in_0_bits_way                           (io_in_0_bits_way),
+    .io_in_0_bits_meta_dirty                    (io_in_0_bits_meta_dirty),
+    .io_in_0_bits_meta_state                    (io_in_0_bits_meta_state),
+    .io_in_0_bits_meta_clients                  (io_in_0_bits_meta_clients),
+    .io_in_0_bits_meta_alias                    (io_in_0_bits_meta_alias),
+    .io_in_0_bits_meta_prefetch                 (io_in_0_bits_meta_prefetch),
+    .io_in_0_bits_meta_prefetchSrc              (io_in_0_bits_meta_prefetchSrc),
+    .io_in_0_bits_meta_accessed                 (io_in_0_bits_meta_accessed),
+    .io_in_0_bits_meta_tagErr                   (io_in_0_bits_meta_tagErr),
+    .io_in_0_bits_meta_dataErr                  (io_in_0_bits_meta_dataErr),
+    .io_in_0_bits_metaWen                       (io_in_0_bits_metaWen),
+    .io_in_0_bits_tagWen                        (io_in_0_bits_tagWen),
+    .io_in_0_bits_dsWen                         (io_in_0_bits_dsWen),
+    .io_in_0_bits_wayMask                       (io_in_0_bits_wayMask),
+    .io_in_0_bits_replTask                      (io_in_0_bits_replTask),
+    .io_in_0_bits_cmoTask                       (io_in_0_bits_cmoTask),
+    .io_in_0_bits_cmoAll                        (io_in_0_bits_cmoAll),
+    .io_in_0_bits_reqSource                     (io_in_0_bits_reqSource),
+    .io_in_0_bits_mergeA                        (io_in_0_bits_mergeA),
+    .io_in_0_bits_aMergeTask_off                (io_in_0_bits_aMergeTask_off),
+    .io_in_0_bits_aMergeTask_alias              (io_in_0_bits_aMergeTask_alias),
+    .io_in_0_bits_aMergeTask_vaddr              (io_in_0_bits_aMergeTask_vaddr),
+    .io_in_0_bits_aMergeTask_isKeyword          (io_in_0_bits_aMergeTask_isKeyword),
+    .io_in_0_bits_aMergeTask_opcode             (io_in_0_bits_aMergeTask_opcode),
+    .io_in_0_bits_aMergeTask_param              (io_in_0_bits_aMergeTask_param),
+    .io_in_0_bits_aMergeTask_sourceId           (io_in_0_bits_aMergeTask_sourceId),
+    .io_in_0_bits_aMergeTask_meta_dirty         (io_in_0_bits_aMergeTask_meta_dirty),
+    .io_in_0_bits_aMergeTask_meta_state         (io_in_0_bits_aMergeTask_meta_state),
+    .io_in_0_bits_aMergeTask_meta_clients       (io_in_0_bits_aMergeTask_meta_clients),
+    .io_in_0_bits_aMergeTask_meta_alias         (io_in_0_bits_aMergeTask_meta_alias),
+    .io_in_0_bits_aMergeTask_meta_prefetch      (io_in_0_bits_aMergeTask_meta_prefetch),
+    .io_in_0_bits_aMergeTask_meta_prefetchSrc
+      (io_in_0_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_0_bits_aMergeTask_meta_accessed      (io_in_0_bits_aMergeTask_meta_accessed),
+    .io_in_0_bits_aMergeTask_meta_tagErr        (io_in_0_bits_aMergeTask_meta_tagErr),
+    .io_in_0_bits_aMergeTask_meta_dataErr       (io_in_0_bits_aMergeTask_meta_dataErr),
+    .io_in_0_bits_snpHitRelease                 (io_in_0_bits_snpHitRelease),
+    .io_in_0_bits_snpHitReleaseToInval          (io_in_0_bits_snpHitReleaseToInval),
+    .io_in_0_bits_snpHitReleaseToClean          (io_in_0_bits_snpHitReleaseToClean),
+    .io_in_0_bits_snpHitReleaseWithData         (io_in_0_bits_snpHitReleaseWithData),
+    .io_in_0_bits_snpHitReleaseIdx              (io_in_0_bits_snpHitReleaseIdx),
+    .io_in_0_bits_snpHitReleaseMeta_dirty       (io_in_0_bits_snpHitReleaseMeta_dirty),
+    .io_in_0_bits_snpHitReleaseMeta_state       (io_in_0_bits_snpHitReleaseMeta_state),
+    .io_in_0_bits_snpHitReleaseMeta_clients     (io_in_0_bits_snpHitReleaseMeta_clients),
+    .io_in_0_bits_snpHitReleaseMeta_alias       (io_in_0_bits_snpHitReleaseMeta_alias),
+    .io_in_0_bits_snpHitReleaseMeta_prefetch    (io_in_0_bits_snpHitReleaseMeta_prefetch),
+    .io_in_0_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_0_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_0_bits_snpHitReleaseMeta_accessed    (io_in_0_bits_snpHitReleaseMeta_accessed),
+    .io_in_0_bits_snpHitReleaseMeta_tagErr      (io_in_0_bits_snpHitReleaseMeta_tagErr),
+    .io_in_0_bits_snpHitReleaseMeta_dataErr     (io_in_0_bits_snpHitReleaseMeta_dataErr),
+    .io_in_0_bits_tgtID                         (io_in_0_bits_tgtID),
+    .io_in_0_bits_srcID                         (io_in_0_bits_srcID),
+    .io_in_0_bits_txnID                         (io_in_0_bits_txnID),
+    .io_in_0_bits_homeNID                       (io_in_0_bits_homeNID),
+    .io_in_0_bits_dbID                          (io_in_0_bits_dbID),
+    .io_in_0_bits_fwdNID                        (io_in_0_bits_fwdNID),
+    .io_in_0_bits_fwdTxnID                      (io_in_0_bits_fwdTxnID),
+    .io_in_0_bits_chiOpcode                     (io_in_0_bits_chiOpcode),
+    .io_in_0_bits_resp                          (io_in_0_bits_resp),
+    .io_in_0_bits_fwdState                      (io_in_0_bits_fwdState),
+    .io_in_0_bits_pCrdType                      (io_in_0_bits_pCrdType),
+    .io_in_0_bits_retToSrc                      (io_in_0_bits_retToSrc),
+    .io_in_0_bits_likelyshared                  (io_in_0_bits_likelyshared),
+    .io_in_0_bits_expCompAck                    (io_in_0_bits_expCompAck),
+    .io_in_0_bits_allowRetry                    (io_in_0_bits_allowRetry),
+    .io_in_0_bits_memAttr_allocate              (io_in_0_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable             (io_in_0_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_device                (io_in_0_bits_memAttr_device),
+    .io_in_0_bits_memAttr_ewa                   (io_in_0_bits_memAttr_ewa),
+    .io_in_0_bits_traceTag                      (io_in_0_bits_traceTag),
+    .io_in_1_ready                              (io_in_1_ready),
+    .io_in_1_valid                              (io_in_1_valid),
+    .io_in_1_bits_channel                       (io_in_1_bits_channel),
+    .io_in_1_bits_txChannel                     (io_in_1_bits_txChannel),
+    .io_in_1_bits_set                           (io_in_1_bits_set),
+    .io_in_1_bits_tag                           (io_in_1_bits_tag),
+    .io_in_1_bits_off                           (io_in_1_bits_off),
+    .io_in_1_bits_alias                         (io_in_1_bits_alias),
+    .io_in_1_bits_vaddr                         (io_in_1_bits_vaddr),
+    .io_in_1_bits_isKeyword                     (io_in_1_bits_isKeyword),
+    .io_in_1_bits_opcode                        (io_in_1_bits_opcode),
+    .io_in_1_bits_param                         (io_in_1_bits_param),
+    .io_in_1_bits_size                          (io_in_1_bits_size),
+    .io_in_1_bits_sourceId                      (io_in_1_bits_sourceId),
+    .io_in_1_bits_bufIdx                        (io_in_1_bits_bufIdx),
+    .io_in_1_bits_needProbeAckData              (io_in_1_bits_needProbeAckData),
+    .io_in_1_bits_denied                        (io_in_1_bits_denied),
+    .io_in_1_bits_corrupt                       (io_in_1_bits_corrupt),
+    .io_in_1_bits_mshrTask                      (io_in_1_bits_mshrTask),
+    .io_in_1_bits_mshrId                        (io_in_1_bits_mshrId),
+    .io_in_1_bits_aliasTask                     (io_in_1_bits_aliasTask),
+    .io_in_1_bits_useProbeData                  (io_in_1_bits_useProbeData),
+    .io_in_1_bits_mshrRetry                     (io_in_1_bits_mshrRetry),
+    .io_in_1_bits_readProbeDataDown             (io_in_1_bits_readProbeDataDown),
+    .io_in_1_bits_fromL2pft                     (io_in_1_bits_fromL2pft),
+    .io_in_1_bits_needHint                      (io_in_1_bits_needHint),
+    .io_in_1_bits_dirty                         (io_in_1_bits_dirty),
+    .io_in_1_bits_way                           (io_in_1_bits_way),
+    .io_in_1_bits_meta_dirty                    (io_in_1_bits_meta_dirty),
+    .io_in_1_bits_meta_state                    (io_in_1_bits_meta_state),
+    .io_in_1_bits_meta_clients                  (io_in_1_bits_meta_clients),
+    .io_in_1_bits_meta_alias                    (io_in_1_bits_meta_alias),
+    .io_in_1_bits_meta_prefetch                 (io_in_1_bits_meta_prefetch),
+    .io_in_1_bits_meta_prefetchSrc              (io_in_1_bits_meta_prefetchSrc),
+    .io_in_1_bits_meta_accessed                 (io_in_1_bits_meta_accessed),
+    .io_in_1_bits_meta_tagErr                   (io_in_1_bits_meta_tagErr),
+    .io_in_1_bits_meta_dataErr                  (io_in_1_bits_meta_dataErr),
+    .io_in_1_bits_metaWen                       (io_in_1_bits_metaWen),
+    .io_in_1_bits_tagWen                        (io_in_1_bits_tagWen),
+    .io_in_1_bits_dsWen                         (io_in_1_bits_dsWen),
+    .io_in_1_bits_wayMask                       (io_in_1_bits_wayMask),
+    .io_in_1_bits_replTask                      (io_in_1_bits_replTask),
+    .io_in_1_bits_cmoTask                       (io_in_1_bits_cmoTask),
+    .io_in_1_bits_cmoAll                        (io_in_1_bits_cmoAll),
+    .io_in_1_bits_reqSource                     (io_in_1_bits_reqSource),
+    .io_in_1_bits_mergeA                        (io_in_1_bits_mergeA),
+    .io_in_1_bits_aMergeTask_off                (io_in_1_bits_aMergeTask_off),
+    .io_in_1_bits_aMergeTask_alias              (io_in_1_bits_aMergeTask_alias),
+    .io_in_1_bits_aMergeTask_vaddr              (io_in_1_bits_aMergeTask_vaddr),
+    .io_in_1_bits_aMergeTask_isKeyword          (io_in_1_bits_aMergeTask_isKeyword),
+    .io_in_1_bits_aMergeTask_opcode             (io_in_1_bits_aMergeTask_opcode),
+    .io_in_1_bits_aMergeTask_param              (io_in_1_bits_aMergeTask_param),
+    .io_in_1_bits_aMergeTask_sourceId           (io_in_1_bits_aMergeTask_sourceId),
+    .io_in_1_bits_aMergeTask_meta_dirty         (io_in_1_bits_aMergeTask_meta_dirty),
+    .io_in_1_bits_aMergeTask_meta_state         (io_in_1_bits_aMergeTask_meta_state),
+    .io_in_1_bits_aMergeTask_meta_clients       (io_in_1_bits_aMergeTask_meta_clients),
+    .io_in_1_bits_aMergeTask_meta_alias         (io_in_1_bits_aMergeTask_meta_alias),
+    .io_in_1_bits_aMergeTask_meta_prefetch      (io_in_1_bits_aMergeTask_meta_prefetch),
+    .io_in_1_bits_aMergeTask_meta_prefetchSrc
+      (io_in_1_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_1_bits_aMergeTask_meta_accessed      (io_in_1_bits_aMergeTask_meta_accessed),
+    .io_in_1_bits_aMergeTask_meta_tagErr        (io_in_1_bits_aMergeTask_meta_tagErr),
+    .io_in_1_bits_aMergeTask_meta_dataErr       (io_in_1_bits_aMergeTask_meta_dataErr),
+    .io_in_1_bits_snpHitRelease                 (io_in_1_bits_snpHitRelease),
+    .io_in_1_bits_snpHitReleaseToInval          (io_in_1_bits_snpHitReleaseToInval),
+    .io_in_1_bits_snpHitReleaseToClean          (io_in_1_bits_snpHitReleaseToClean),
+    .io_in_1_bits_snpHitReleaseWithData         (io_in_1_bits_snpHitReleaseWithData),
+    .io_in_1_bits_snpHitReleaseIdx              (io_in_1_bits_snpHitReleaseIdx),
+    .io_in_1_bits_snpHitReleaseMeta_dirty       (io_in_1_bits_snpHitReleaseMeta_dirty),
+    .io_in_1_bits_snpHitReleaseMeta_state       (io_in_1_bits_snpHitReleaseMeta_state),
+    .io_in_1_bits_snpHitReleaseMeta_clients     (io_in_1_bits_snpHitReleaseMeta_clients),
+    .io_in_1_bits_snpHitReleaseMeta_alias       (io_in_1_bits_snpHitReleaseMeta_alias),
+    .io_in_1_bits_snpHitReleaseMeta_prefetch    (io_in_1_bits_snpHitReleaseMeta_prefetch),
+    .io_in_1_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_1_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_1_bits_snpHitReleaseMeta_accessed    (io_in_1_bits_snpHitReleaseMeta_accessed),
+    .io_in_1_bits_snpHitReleaseMeta_tagErr      (io_in_1_bits_snpHitReleaseMeta_tagErr),
+    .io_in_1_bits_snpHitReleaseMeta_dataErr     (io_in_1_bits_snpHitReleaseMeta_dataErr),
+    .io_in_1_bits_tgtID                         (io_in_1_bits_tgtID),
+    .io_in_1_bits_srcID                         (io_in_1_bits_srcID),
+    .io_in_1_bits_txnID                         (io_in_1_bits_txnID),
+    .io_in_1_bits_homeNID                       (io_in_1_bits_homeNID),
+    .io_in_1_bits_dbID                          (io_in_1_bits_dbID),
+    .io_in_1_bits_fwdNID                        (io_in_1_bits_fwdNID),
+    .io_in_1_bits_fwdTxnID                      (io_in_1_bits_fwdTxnID),
+    .io_in_1_bits_chiOpcode                     (io_in_1_bits_chiOpcode),
+    .io_in_1_bits_resp                          (io_in_1_bits_resp),
+    .io_in_1_bits_fwdState                      (io_in_1_bits_fwdState),
+    .io_in_1_bits_pCrdType                      (io_in_1_bits_pCrdType),
+    .io_in_1_bits_retToSrc                      (io_in_1_bits_retToSrc),
+    .io_in_1_bits_likelyshared                  (io_in_1_bits_likelyshared),
+    .io_in_1_bits_expCompAck                    (io_in_1_bits_expCompAck),
+    .io_in_1_bits_allowRetry                    (io_in_1_bits_allowRetry),
+    .io_in_1_bits_memAttr_allocate              (io_in_1_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable             (io_in_1_bits_memAttr_cacheable),
+    .io_in_1_bits_memAttr_device                (io_in_1_bits_memAttr_device),
+    .io_in_1_bits_memAttr_ewa                   (io_in_1_bits_memAttr_ewa),
+    .io_in_1_bits_traceTag                      (io_in_1_bits_traceTag),
+    .io_out_ready                               (io_out_ready & finalSelLow),
+    .io_out_valid                               (_lowArb_io_out_valid),
+    .io_out_bits_channel                        (_lowArb_io_out_bits_channel),
+    .io_out_bits_txChannel                      (_lowArb_io_out_bits_txChannel),
+    .io_out_bits_set                            (_lowArb_io_out_bits_set),
+    .io_out_bits_tag                            (_lowArb_io_out_bits_tag),
+    .io_out_bits_off                            (_lowArb_io_out_bits_off),
+    .io_out_bits_alias                          (_lowArb_io_out_bits_alias),
+    .io_out_bits_vaddr                          (_lowArb_io_out_bits_vaddr),
+    .io_out_bits_isKeyword                      (_lowArb_io_out_bits_isKeyword),
+    .io_out_bits_opcode                         (_lowArb_io_out_bits_opcode),
+    .io_out_bits_param                          (_lowArb_io_out_bits_param),
+    .io_out_bits_size                           (_lowArb_io_out_bits_size),
+    .io_out_bits_sourceId                       (_lowArb_io_out_bits_sourceId),
+    .io_out_bits_bufIdx                         (_lowArb_io_out_bits_bufIdx),
+    .io_out_bits_needProbeAckData               (_lowArb_io_out_bits_needProbeAckData),
+    .io_out_bits_denied                         (_lowArb_io_out_bits_denied),
+    .io_out_bits_corrupt                        (_lowArb_io_out_bits_corrupt),
+    .io_out_bits_mshrTask                       (_lowArb_io_out_bits_mshrTask),
+    .io_out_bits_mshrId                         (_lowArb_io_out_bits_mshrId),
+    .io_out_bits_aliasTask                      (_lowArb_io_out_bits_aliasTask),
+    .io_out_bits_useProbeData                   (_lowArb_io_out_bits_useProbeData),
+    .io_out_bits_mshrRetry                      (_lowArb_io_out_bits_mshrRetry),
+    .io_out_bits_readProbeDataDown              (_lowArb_io_out_bits_readProbeDataDown),
+    .io_out_bits_fromL2pft                      (_lowArb_io_out_bits_fromL2pft),
+    .io_out_bits_needHint                       (_lowArb_io_out_bits_needHint),
+    .io_out_bits_dirty                          (_lowArb_io_out_bits_dirty),
+    .io_out_bits_way                            (_lowArb_io_out_bits_way),
+    .io_out_bits_meta_dirty                     (_lowArb_io_out_bits_meta_dirty),
+    .io_out_bits_meta_state                     (_lowArb_io_out_bits_meta_state),
+    .io_out_bits_meta_clients                   (_lowArb_io_out_bits_meta_clients),
+    .io_out_bits_meta_alias                     (_lowArb_io_out_bits_meta_alias),
+    .io_out_bits_meta_prefetch                  (_lowArb_io_out_bits_meta_prefetch),
+    .io_out_bits_meta_prefetchSrc               (_lowArb_io_out_bits_meta_prefetchSrc),
+    .io_out_bits_meta_accessed                  (_lowArb_io_out_bits_meta_accessed),
+    .io_out_bits_meta_tagErr                    (_lowArb_io_out_bits_meta_tagErr),
+    .io_out_bits_meta_dataErr                   (_lowArb_io_out_bits_meta_dataErr),
+    .io_out_bits_metaWen                        (_lowArb_io_out_bits_metaWen),
+    .io_out_bits_tagWen                         (_lowArb_io_out_bits_tagWen),
+    .io_out_bits_dsWen                          (_lowArb_io_out_bits_dsWen),
+    .io_out_bits_wayMask                        (_lowArb_io_out_bits_wayMask),
+    .io_out_bits_replTask                       (_lowArb_io_out_bits_replTask),
+    .io_out_bits_cmoTask                        (_lowArb_io_out_bits_cmoTask),
+    .io_out_bits_cmoAll                         (_lowArb_io_out_bits_cmoAll),
+    .io_out_bits_reqSource                      (_lowArb_io_out_bits_reqSource),
+    .io_out_bits_mergeA                         (_lowArb_io_out_bits_mergeA),
+    .io_out_bits_aMergeTask_off                 (_lowArb_io_out_bits_aMergeTask_off),
+    .io_out_bits_aMergeTask_alias               (_lowArb_io_out_bits_aMergeTask_alias),
+    .io_out_bits_aMergeTask_vaddr               (_lowArb_io_out_bits_aMergeTask_vaddr),
+    .io_out_bits_aMergeTask_isKeyword
+      (_lowArb_io_out_bits_aMergeTask_isKeyword),
+    .io_out_bits_aMergeTask_opcode              (_lowArb_io_out_bits_aMergeTask_opcode),
+    .io_out_bits_aMergeTask_param               (_lowArb_io_out_bits_aMergeTask_param),
+    .io_out_bits_aMergeTask_sourceId            (_lowArb_io_out_bits_aMergeTask_sourceId),
+    .io_out_bits_aMergeTask_meta_dirty
+      (_lowArb_io_out_bits_aMergeTask_meta_dirty),
+    .io_out_bits_aMergeTask_meta_state
+      (_lowArb_io_out_bits_aMergeTask_meta_state),
+    .io_out_bits_aMergeTask_meta_clients
+      (_lowArb_io_out_bits_aMergeTask_meta_clients),
+    .io_out_bits_aMergeTask_meta_alias
+      (_lowArb_io_out_bits_aMergeTask_meta_alias),
+    .io_out_bits_aMergeTask_meta_prefetch
+      (_lowArb_io_out_bits_aMergeTask_meta_prefetch),
+    .io_out_bits_aMergeTask_meta_prefetchSrc
+      (_lowArb_io_out_bits_aMergeTask_meta_prefetchSrc),
+    .io_out_bits_aMergeTask_meta_accessed
+      (_lowArb_io_out_bits_aMergeTask_meta_accessed),
+    .io_out_bits_aMergeTask_meta_tagErr
+      (_lowArb_io_out_bits_aMergeTask_meta_tagErr),
+    .io_out_bits_aMergeTask_meta_dataErr
+      (_lowArb_io_out_bits_aMergeTask_meta_dataErr),
+    .io_out_bits_snpHitRelease                  (_lowArb_io_out_bits_snpHitRelease),
+    .io_out_bits_snpHitReleaseToInval
+      (_lowArb_io_out_bits_snpHitReleaseToInval),
+    .io_out_bits_snpHitReleaseToClean
+      (_lowArb_io_out_bits_snpHitReleaseToClean),
+    .io_out_bits_snpHitReleaseWithData
+      (_lowArb_io_out_bits_snpHitReleaseWithData),
+    .io_out_bits_snpHitReleaseIdx               (_lowArb_io_out_bits_snpHitReleaseIdx),
+    .io_out_bits_snpHitReleaseMeta_dirty
+      (_lowArb_io_out_bits_snpHitReleaseMeta_dirty),
+    .io_out_bits_snpHitReleaseMeta_state
+      (_lowArb_io_out_bits_snpHitReleaseMeta_state),
+    .io_out_bits_snpHitReleaseMeta_clients
+      (_lowArb_io_out_bits_snpHitReleaseMeta_clients),
+    .io_out_bits_snpHitReleaseMeta_alias
+      (_lowArb_io_out_bits_snpHitReleaseMeta_alias),
+    .io_out_bits_snpHitReleaseMeta_prefetch
+      (_lowArb_io_out_bits_snpHitReleaseMeta_prefetch),
+    .io_out_bits_snpHitReleaseMeta_prefetchSrc
+      (_lowArb_io_out_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_out_bits_snpHitReleaseMeta_accessed
+      (_lowArb_io_out_bits_snpHitReleaseMeta_accessed),
+    .io_out_bits_snpHitReleaseMeta_tagErr
+      (_lowArb_io_out_bits_snpHitReleaseMeta_tagErr),
+    .io_out_bits_snpHitReleaseMeta_dataErr
+      (_lowArb_io_out_bits_snpHitReleaseMeta_dataErr),
+    .io_out_bits_tgtID                          (_lowArb_io_out_bits_tgtID),
+    .io_out_bits_srcID                          (_lowArb_io_out_bits_srcID),
+    .io_out_bits_txnID                          (_lowArb_io_out_bits_txnID),
+    .io_out_bits_homeNID                        (_lowArb_io_out_bits_homeNID),
+    .io_out_bits_dbID                           (_lowArb_io_out_bits_dbID),
+    .io_out_bits_fwdNID                         (_lowArb_io_out_bits_fwdNID),
+    .io_out_bits_fwdTxnID                       (_lowArb_io_out_bits_fwdTxnID),
+    .io_out_bits_chiOpcode                      (_lowArb_io_out_bits_chiOpcode),
+    .io_out_bits_resp                           (_lowArb_io_out_bits_resp),
+    .io_out_bits_fwdState                       (_lowArb_io_out_bits_fwdState),
+    .io_out_bits_pCrdType                       (_lowArb_io_out_bits_pCrdType),
+    .io_out_bits_retToSrc                       (_lowArb_io_out_bits_retToSrc),
+    .io_out_bits_likelyshared                   (_lowArb_io_out_bits_likelyshared),
+    .io_out_bits_expCompAck                     (_lowArb_io_out_bits_expCompAck),
+    .io_out_bits_allowRetry                     (_lowArb_io_out_bits_allowRetry),
+    .io_out_bits_memAttr_allocate               (_lowArb_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable              (_lowArb_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device                 (_lowArb_io_out_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa                    (_lowArb_io_out_bits_memAttr_ewa),
+    .io_out_bits_traceTag                       (_lowArb_io_out_bits_traceTag)
+  );
+  FastArbiter_10 highArb (
+    .clock                                      (clock),
+    .reset                                      (reset),
+    .io_in_0_ready                              (io_in_2_ready),
+    .io_in_0_valid                              (io_in_2_valid),
+    .io_in_0_bits_channel                       (io_in_2_bits_channel),
+    .io_in_0_bits_txChannel                     (io_in_2_bits_txChannel),
+    .io_in_0_bits_set                           (io_in_2_bits_set),
+    .io_in_0_bits_tag                           (io_in_2_bits_tag),
+    .io_in_0_bits_off                           (io_in_2_bits_off),
+    .io_in_0_bits_alias                         (io_in_2_bits_alias),
+    .io_in_0_bits_vaddr                         (io_in_2_bits_vaddr),
+    .io_in_0_bits_isKeyword                     (io_in_2_bits_isKeyword),
+    .io_in_0_bits_opcode                        (io_in_2_bits_opcode),
+    .io_in_0_bits_param                         (io_in_2_bits_param),
+    .io_in_0_bits_size                          (io_in_2_bits_size),
+    .io_in_0_bits_sourceId                      (io_in_2_bits_sourceId),
+    .io_in_0_bits_bufIdx                        (io_in_2_bits_bufIdx),
+    .io_in_0_bits_needProbeAckData              (io_in_2_bits_needProbeAckData),
+    .io_in_0_bits_denied                        (io_in_2_bits_denied),
+    .io_in_0_bits_corrupt                       (io_in_2_bits_corrupt),
+    .io_in_0_bits_mshrTask                      (io_in_2_bits_mshrTask),
+    .io_in_0_bits_mshrId                        (io_in_2_bits_mshrId),
+    .io_in_0_bits_aliasTask                     (io_in_2_bits_aliasTask),
+    .io_in_0_bits_useProbeData                  (io_in_2_bits_useProbeData),
+    .io_in_0_bits_mshrRetry                     (io_in_2_bits_mshrRetry),
+    .io_in_0_bits_readProbeDataDown             (io_in_2_bits_readProbeDataDown),
+    .io_in_0_bits_fromL2pft                     (io_in_2_bits_fromL2pft),
+    .io_in_0_bits_needHint                      (io_in_2_bits_needHint),
+    .io_in_0_bits_dirty                         (io_in_2_bits_dirty),
+    .io_in_0_bits_way                           (io_in_2_bits_way),
+    .io_in_0_bits_meta_dirty                    (io_in_2_bits_meta_dirty),
+    .io_in_0_bits_meta_state                    (io_in_2_bits_meta_state),
+    .io_in_0_bits_meta_clients                  (io_in_2_bits_meta_clients),
+    .io_in_0_bits_meta_alias                    (io_in_2_bits_meta_alias),
+    .io_in_0_bits_meta_prefetch                 (io_in_2_bits_meta_prefetch),
+    .io_in_0_bits_meta_prefetchSrc              (io_in_2_bits_meta_prefetchSrc),
+    .io_in_0_bits_meta_accessed                 (io_in_2_bits_meta_accessed),
+    .io_in_0_bits_meta_tagErr                   (io_in_2_bits_meta_tagErr),
+    .io_in_0_bits_meta_dataErr                  (io_in_2_bits_meta_dataErr),
+    .io_in_0_bits_metaWen                       (io_in_2_bits_metaWen),
+    .io_in_0_bits_tagWen                        (io_in_2_bits_tagWen),
+    .io_in_0_bits_dsWen                         (io_in_2_bits_dsWen),
+    .io_in_0_bits_wayMask                       (io_in_2_bits_wayMask),
+    .io_in_0_bits_replTask                      (io_in_2_bits_replTask),
+    .io_in_0_bits_cmoTask                       (io_in_2_bits_cmoTask),
+    .io_in_0_bits_cmoAll                        (io_in_2_bits_cmoAll),
+    .io_in_0_bits_reqSource                     (io_in_2_bits_reqSource),
+    .io_in_0_bits_mergeA                        (io_in_2_bits_mergeA),
+    .io_in_0_bits_aMergeTask_off                (io_in_2_bits_aMergeTask_off),
+    .io_in_0_bits_aMergeTask_alias              (io_in_2_bits_aMergeTask_alias),
+    .io_in_0_bits_aMergeTask_vaddr              (io_in_2_bits_aMergeTask_vaddr),
+    .io_in_0_bits_aMergeTask_isKeyword          (io_in_2_bits_aMergeTask_isKeyword),
+    .io_in_0_bits_aMergeTask_opcode             (io_in_2_bits_aMergeTask_opcode),
+    .io_in_0_bits_aMergeTask_param              (io_in_2_bits_aMergeTask_param),
+    .io_in_0_bits_aMergeTask_sourceId           (io_in_2_bits_aMergeTask_sourceId),
+    .io_in_0_bits_aMergeTask_meta_dirty         (io_in_2_bits_aMergeTask_meta_dirty),
+    .io_in_0_bits_aMergeTask_meta_state         (io_in_2_bits_aMergeTask_meta_state),
+    .io_in_0_bits_aMergeTask_meta_clients       (io_in_2_bits_aMergeTask_meta_clients),
+    .io_in_0_bits_aMergeTask_meta_alias         (io_in_2_bits_aMergeTask_meta_alias),
+    .io_in_0_bits_aMergeTask_meta_prefetch      (io_in_2_bits_aMergeTask_meta_prefetch),
+    .io_in_0_bits_aMergeTask_meta_prefetchSrc
+      (io_in_2_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_0_bits_aMergeTask_meta_accessed      (io_in_2_bits_aMergeTask_meta_accessed),
+    .io_in_0_bits_aMergeTask_meta_tagErr        (io_in_2_bits_aMergeTask_meta_tagErr),
+    .io_in_0_bits_aMergeTask_meta_dataErr       (io_in_2_bits_aMergeTask_meta_dataErr),
+    .io_in_0_bits_snpHitRelease                 (io_in_2_bits_snpHitRelease),
+    .io_in_0_bits_snpHitReleaseToInval          (io_in_2_bits_snpHitReleaseToInval),
+    .io_in_0_bits_snpHitReleaseToClean          (io_in_2_bits_snpHitReleaseToClean),
+    .io_in_0_bits_snpHitReleaseWithData         (io_in_2_bits_snpHitReleaseWithData),
+    .io_in_0_bits_snpHitReleaseIdx              (io_in_2_bits_snpHitReleaseIdx),
+    .io_in_0_bits_snpHitReleaseMeta_dirty       (io_in_2_bits_snpHitReleaseMeta_dirty),
+    .io_in_0_bits_snpHitReleaseMeta_state       (io_in_2_bits_snpHitReleaseMeta_state),
+    .io_in_0_bits_snpHitReleaseMeta_clients     (io_in_2_bits_snpHitReleaseMeta_clients),
+    .io_in_0_bits_snpHitReleaseMeta_alias       (io_in_2_bits_snpHitReleaseMeta_alias),
+    .io_in_0_bits_snpHitReleaseMeta_prefetch    (io_in_2_bits_snpHitReleaseMeta_prefetch),
+    .io_in_0_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_2_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_0_bits_snpHitReleaseMeta_accessed    (io_in_2_bits_snpHitReleaseMeta_accessed),
+    .io_in_0_bits_snpHitReleaseMeta_tagErr      (io_in_2_bits_snpHitReleaseMeta_tagErr),
+    .io_in_0_bits_snpHitReleaseMeta_dataErr     (io_in_2_bits_snpHitReleaseMeta_dataErr),
+    .io_in_0_bits_tgtID                         (io_in_2_bits_tgtID),
+    .io_in_0_bits_srcID                         (io_in_2_bits_srcID),
+    .io_in_0_bits_txnID                         (io_in_2_bits_txnID),
+    .io_in_0_bits_homeNID                       (io_in_2_bits_homeNID),
+    .io_in_0_bits_dbID                          (io_in_2_bits_dbID),
+    .io_in_0_bits_fwdNID                        (io_in_2_bits_fwdNID),
+    .io_in_0_bits_fwdTxnID                      (io_in_2_bits_fwdTxnID),
+    .io_in_0_bits_chiOpcode                     (io_in_2_bits_chiOpcode),
+    .io_in_0_bits_resp                          (io_in_2_bits_resp),
+    .io_in_0_bits_fwdState                      (io_in_2_bits_fwdState),
+    .io_in_0_bits_pCrdType                      (io_in_2_bits_pCrdType),
+    .io_in_0_bits_retToSrc                      (io_in_2_bits_retToSrc),
+    .io_in_0_bits_likelyshared                  (io_in_2_bits_likelyshared),
+    .io_in_0_bits_expCompAck                    (io_in_2_bits_expCompAck),
+    .io_in_0_bits_allowRetry                    (io_in_2_bits_allowRetry),
+    .io_in_0_bits_memAttr_allocate              (io_in_2_bits_memAttr_allocate),
+    .io_in_0_bits_memAttr_cacheable             (io_in_2_bits_memAttr_cacheable),
+    .io_in_0_bits_memAttr_device                (io_in_2_bits_memAttr_device),
+    .io_in_0_bits_memAttr_ewa                   (io_in_2_bits_memAttr_ewa),
+    .io_in_0_bits_traceTag                      (io_in_2_bits_traceTag),
+    .io_in_1_ready                              (io_in_3_ready),
+    .io_in_1_valid                              (io_in_3_valid),
+    .io_in_1_bits_channel                       (io_in_3_bits_channel),
+    .io_in_1_bits_txChannel                     (io_in_3_bits_txChannel),
+    .io_in_1_bits_set                           (io_in_3_bits_set),
+    .io_in_1_bits_tag                           (io_in_3_bits_tag),
+    .io_in_1_bits_off                           (io_in_3_bits_off),
+    .io_in_1_bits_alias                         (io_in_3_bits_alias),
+    .io_in_1_bits_vaddr                         (io_in_3_bits_vaddr),
+    .io_in_1_bits_isKeyword                     (io_in_3_bits_isKeyword),
+    .io_in_1_bits_opcode                        (io_in_3_bits_opcode),
+    .io_in_1_bits_param                         (io_in_3_bits_param),
+    .io_in_1_bits_size                          (io_in_3_bits_size),
+    .io_in_1_bits_sourceId                      (io_in_3_bits_sourceId),
+    .io_in_1_bits_bufIdx                        (io_in_3_bits_bufIdx),
+    .io_in_1_bits_needProbeAckData              (io_in_3_bits_needProbeAckData),
+    .io_in_1_bits_denied                        (io_in_3_bits_denied),
+    .io_in_1_bits_corrupt                       (io_in_3_bits_corrupt),
+    .io_in_1_bits_mshrTask                      (io_in_3_bits_mshrTask),
+    .io_in_1_bits_mshrId                        (io_in_3_bits_mshrId),
+    .io_in_1_bits_aliasTask                     (io_in_3_bits_aliasTask),
+    .io_in_1_bits_useProbeData                  (io_in_3_bits_useProbeData),
+    .io_in_1_bits_mshrRetry                     (io_in_3_bits_mshrRetry),
+    .io_in_1_bits_readProbeDataDown             (io_in_3_bits_readProbeDataDown),
+    .io_in_1_bits_fromL2pft                     (io_in_3_bits_fromL2pft),
+    .io_in_1_bits_needHint                      (io_in_3_bits_needHint),
+    .io_in_1_bits_dirty                         (io_in_3_bits_dirty),
+    .io_in_1_bits_way                           (io_in_3_bits_way),
+    .io_in_1_bits_meta_dirty                    (io_in_3_bits_meta_dirty),
+    .io_in_1_bits_meta_state                    (io_in_3_bits_meta_state),
+    .io_in_1_bits_meta_clients                  (io_in_3_bits_meta_clients),
+    .io_in_1_bits_meta_alias                    (io_in_3_bits_meta_alias),
+    .io_in_1_bits_meta_prefetch                 (io_in_3_bits_meta_prefetch),
+    .io_in_1_bits_meta_prefetchSrc              (io_in_3_bits_meta_prefetchSrc),
+    .io_in_1_bits_meta_accessed                 (io_in_3_bits_meta_accessed),
+    .io_in_1_bits_meta_tagErr                   (io_in_3_bits_meta_tagErr),
+    .io_in_1_bits_meta_dataErr                  (io_in_3_bits_meta_dataErr),
+    .io_in_1_bits_metaWen                       (io_in_3_bits_metaWen),
+    .io_in_1_bits_tagWen                        (io_in_3_bits_tagWen),
+    .io_in_1_bits_dsWen                         (io_in_3_bits_dsWen),
+    .io_in_1_bits_wayMask                       (io_in_3_bits_wayMask),
+    .io_in_1_bits_replTask                      (io_in_3_bits_replTask),
+    .io_in_1_bits_cmoTask                       (io_in_3_bits_cmoTask),
+    .io_in_1_bits_cmoAll                        (io_in_3_bits_cmoAll),
+    .io_in_1_bits_reqSource                     (io_in_3_bits_reqSource),
+    .io_in_1_bits_mergeA                        (io_in_3_bits_mergeA),
+    .io_in_1_bits_aMergeTask_off                (io_in_3_bits_aMergeTask_off),
+    .io_in_1_bits_aMergeTask_alias              (io_in_3_bits_aMergeTask_alias),
+    .io_in_1_bits_aMergeTask_vaddr              (io_in_3_bits_aMergeTask_vaddr),
+    .io_in_1_bits_aMergeTask_isKeyword          (io_in_3_bits_aMergeTask_isKeyword),
+    .io_in_1_bits_aMergeTask_opcode             (io_in_3_bits_aMergeTask_opcode),
+    .io_in_1_bits_aMergeTask_param              (io_in_3_bits_aMergeTask_param),
+    .io_in_1_bits_aMergeTask_sourceId           (io_in_3_bits_aMergeTask_sourceId),
+    .io_in_1_bits_aMergeTask_meta_dirty         (io_in_3_bits_aMergeTask_meta_dirty),
+    .io_in_1_bits_aMergeTask_meta_state         (io_in_3_bits_aMergeTask_meta_state),
+    .io_in_1_bits_aMergeTask_meta_clients       (io_in_3_bits_aMergeTask_meta_clients),
+    .io_in_1_bits_aMergeTask_meta_alias         (io_in_3_bits_aMergeTask_meta_alias),
+    .io_in_1_bits_aMergeTask_meta_prefetch      (io_in_3_bits_aMergeTask_meta_prefetch),
+    .io_in_1_bits_aMergeTask_meta_prefetchSrc
+      (io_in_3_bits_aMergeTask_meta_prefetchSrc),
+    .io_in_1_bits_aMergeTask_meta_accessed      (io_in_3_bits_aMergeTask_meta_accessed),
+    .io_in_1_bits_aMergeTask_meta_tagErr        (io_in_3_bits_aMergeTask_meta_tagErr),
+    .io_in_1_bits_aMergeTask_meta_dataErr       (io_in_3_bits_aMergeTask_meta_dataErr),
+    .io_in_1_bits_snpHitRelease                 (io_in_3_bits_snpHitRelease),
+    .io_in_1_bits_snpHitReleaseToInval          (io_in_3_bits_snpHitReleaseToInval),
+    .io_in_1_bits_snpHitReleaseToClean          (io_in_3_bits_snpHitReleaseToClean),
+    .io_in_1_bits_snpHitReleaseWithData         (io_in_3_bits_snpHitReleaseWithData),
+    .io_in_1_bits_snpHitReleaseIdx              (io_in_3_bits_snpHitReleaseIdx),
+    .io_in_1_bits_snpHitReleaseMeta_dirty       (io_in_3_bits_snpHitReleaseMeta_dirty),
+    .io_in_1_bits_snpHitReleaseMeta_state       (io_in_3_bits_snpHitReleaseMeta_state),
+    .io_in_1_bits_snpHitReleaseMeta_clients     (io_in_3_bits_snpHitReleaseMeta_clients),
+    .io_in_1_bits_snpHitReleaseMeta_alias       (io_in_3_bits_snpHitReleaseMeta_alias),
+    .io_in_1_bits_snpHitReleaseMeta_prefetch    (io_in_3_bits_snpHitReleaseMeta_prefetch),
+    .io_in_1_bits_snpHitReleaseMeta_prefetchSrc
+      (io_in_3_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_in_1_bits_snpHitReleaseMeta_accessed    (io_in_3_bits_snpHitReleaseMeta_accessed),
+    .io_in_1_bits_snpHitReleaseMeta_tagErr      (io_in_3_bits_snpHitReleaseMeta_tagErr),
+    .io_in_1_bits_snpHitReleaseMeta_dataErr     (io_in_3_bits_snpHitReleaseMeta_dataErr),
+    .io_in_1_bits_tgtID                         (io_in_3_bits_tgtID),
+    .io_in_1_bits_srcID                         (io_in_3_bits_srcID),
+    .io_in_1_bits_txnID                         (io_in_3_bits_txnID),
+    .io_in_1_bits_homeNID                       (io_in_3_bits_homeNID),
+    .io_in_1_bits_dbID                          (io_in_3_bits_dbID),
+    .io_in_1_bits_fwdNID                        (io_in_3_bits_fwdNID),
+    .io_in_1_bits_fwdTxnID                      (io_in_3_bits_fwdTxnID),
+    .io_in_1_bits_chiOpcode                     (io_in_3_bits_chiOpcode),
+    .io_in_1_bits_resp                          (io_in_3_bits_resp),
+    .io_in_1_bits_fwdState                      (io_in_3_bits_fwdState),
+    .io_in_1_bits_pCrdType                      (io_in_3_bits_pCrdType),
+    .io_in_1_bits_retToSrc                      (io_in_3_bits_retToSrc),
+    .io_in_1_bits_likelyshared                  (io_in_3_bits_likelyshared),
+    .io_in_1_bits_expCompAck                    (io_in_3_bits_expCompAck),
+    .io_in_1_bits_allowRetry                    (io_in_3_bits_allowRetry),
+    .io_in_1_bits_memAttr_allocate              (io_in_3_bits_memAttr_allocate),
+    .io_in_1_bits_memAttr_cacheable             (io_in_3_bits_memAttr_cacheable),
+    .io_in_1_bits_memAttr_device                (io_in_3_bits_memAttr_device),
+    .io_in_1_bits_memAttr_ewa                   (io_in_3_bits_memAttr_ewa),
+    .io_in_1_bits_traceTag                      (io_in_3_bits_traceTag),
+    .io_out_ready                               (io_out_ready & ~finalSelLow),
+    .io_out_valid                               (_highArb_io_out_valid),
+    .io_out_bits_channel                        (_highArb_io_out_bits_channel),
+    .io_out_bits_txChannel                      (_highArb_io_out_bits_txChannel),
+    .io_out_bits_set                            (_highArb_io_out_bits_set),
+    .io_out_bits_tag                            (_highArb_io_out_bits_tag),
+    .io_out_bits_off                            (_highArb_io_out_bits_off),
+    .io_out_bits_alias                          (_highArb_io_out_bits_alias),
+    .io_out_bits_vaddr                          (_highArb_io_out_bits_vaddr),
+    .io_out_bits_isKeyword                      (_highArb_io_out_bits_isKeyword),
+    .io_out_bits_opcode                         (_highArb_io_out_bits_opcode),
+    .io_out_bits_param                          (_highArb_io_out_bits_param),
+    .io_out_bits_size                           (_highArb_io_out_bits_size),
+    .io_out_bits_sourceId                       (_highArb_io_out_bits_sourceId),
+    .io_out_bits_bufIdx                         (_highArb_io_out_bits_bufIdx),
+    .io_out_bits_needProbeAckData               (_highArb_io_out_bits_needProbeAckData),
+    .io_out_bits_denied                         (_highArb_io_out_bits_denied),
+    .io_out_bits_corrupt                        (_highArb_io_out_bits_corrupt),
+    .io_out_bits_mshrTask                       (_highArb_io_out_bits_mshrTask),
+    .io_out_bits_mshrId                         (_highArb_io_out_bits_mshrId),
+    .io_out_bits_aliasTask                      (_highArb_io_out_bits_aliasTask),
+    .io_out_bits_useProbeData                   (_highArb_io_out_bits_useProbeData),
+    .io_out_bits_mshrRetry                      (_highArb_io_out_bits_mshrRetry),
+    .io_out_bits_readProbeDataDown              (_highArb_io_out_bits_readProbeDataDown),
+    .io_out_bits_fromL2pft                      (_highArb_io_out_bits_fromL2pft),
+    .io_out_bits_needHint                       (_highArb_io_out_bits_needHint),
+    .io_out_bits_dirty                          (_highArb_io_out_bits_dirty),
+    .io_out_bits_way                            (_highArb_io_out_bits_way),
+    .io_out_bits_meta_dirty                     (_highArb_io_out_bits_meta_dirty),
+    .io_out_bits_meta_state                     (_highArb_io_out_bits_meta_state),
+    .io_out_bits_meta_clients                   (_highArb_io_out_bits_meta_clients),
+    .io_out_bits_meta_alias                     (_highArb_io_out_bits_meta_alias),
+    .io_out_bits_meta_prefetch                  (_highArb_io_out_bits_meta_prefetch),
+    .io_out_bits_meta_prefetchSrc               (_highArb_io_out_bits_meta_prefetchSrc),
+    .io_out_bits_meta_accessed                  (_highArb_io_out_bits_meta_accessed),
+    .io_out_bits_meta_tagErr                    (_highArb_io_out_bits_meta_tagErr),
+    .io_out_bits_meta_dataErr                   (_highArb_io_out_bits_meta_dataErr),
+    .io_out_bits_metaWen                        (_highArb_io_out_bits_metaWen),
+    .io_out_bits_tagWen                         (_highArb_io_out_bits_tagWen),
+    .io_out_bits_dsWen                          (_highArb_io_out_bits_dsWen),
+    .io_out_bits_wayMask                        (_highArb_io_out_bits_wayMask),
+    .io_out_bits_replTask                       (_highArb_io_out_bits_replTask),
+    .io_out_bits_cmoTask                        (_highArb_io_out_bits_cmoTask),
+    .io_out_bits_cmoAll                         (_highArb_io_out_bits_cmoAll),
+    .io_out_bits_reqSource                      (_highArb_io_out_bits_reqSource),
+    .io_out_bits_mergeA                         (_highArb_io_out_bits_mergeA),
+    .io_out_bits_aMergeTask_off                 (_highArb_io_out_bits_aMergeTask_off),
+    .io_out_bits_aMergeTask_alias               (_highArb_io_out_bits_aMergeTask_alias),
+    .io_out_bits_aMergeTask_vaddr               (_highArb_io_out_bits_aMergeTask_vaddr),
+    .io_out_bits_aMergeTask_isKeyword
+      (_highArb_io_out_bits_aMergeTask_isKeyword),
+    .io_out_bits_aMergeTask_opcode              (_highArb_io_out_bits_aMergeTask_opcode),
+    .io_out_bits_aMergeTask_param               (_highArb_io_out_bits_aMergeTask_param),
+    .io_out_bits_aMergeTask_sourceId
+      (_highArb_io_out_bits_aMergeTask_sourceId),
+    .io_out_bits_aMergeTask_meta_dirty
+      (_highArb_io_out_bits_aMergeTask_meta_dirty),
+    .io_out_bits_aMergeTask_meta_state
+      (_highArb_io_out_bits_aMergeTask_meta_state),
+    .io_out_bits_aMergeTask_meta_clients
+      (_highArb_io_out_bits_aMergeTask_meta_clients),
+    .io_out_bits_aMergeTask_meta_alias
+      (_highArb_io_out_bits_aMergeTask_meta_alias),
+    .io_out_bits_aMergeTask_meta_prefetch
+      (_highArb_io_out_bits_aMergeTask_meta_prefetch),
+    .io_out_bits_aMergeTask_meta_prefetchSrc
+      (_highArb_io_out_bits_aMergeTask_meta_prefetchSrc),
+    .io_out_bits_aMergeTask_meta_accessed
+      (_highArb_io_out_bits_aMergeTask_meta_accessed),
+    .io_out_bits_aMergeTask_meta_tagErr
+      (_highArb_io_out_bits_aMergeTask_meta_tagErr),
+    .io_out_bits_aMergeTask_meta_dataErr
+      (_highArb_io_out_bits_aMergeTask_meta_dataErr),
+    .io_out_bits_snpHitRelease                  (_highArb_io_out_bits_snpHitRelease),
+    .io_out_bits_snpHitReleaseToInval
+      (_highArb_io_out_bits_snpHitReleaseToInval),
+    .io_out_bits_snpHitReleaseToClean
+      (_highArb_io_out_bits_snpHitReleaseToClean),
+    .io_out_bits_snpHitReleaseWithData
+      (_highArb_io_out_bits_snpHitReleaseWithData),
+    .io_out_bits_snpHitReleaseIdx               (_highArb_io_out_bits_snpHitReleaseIdx),
+    .io_out_bits_snpHitReleaseMeta_dirty
+      (_highArb_io_out_bits_snpHitReleaseMeta_dirty),
+    .io_out_bits_snpHitReleaseMeta_state
+      (_highArb_io_out_bits_snpHitReleaseMeta_state),
+    .io_out_bits_snpHitReleaseMeta_clients
+      (_highArb_io_out_bits_snpHitReleaseMeta_clients),
+    .io_out_bits_snpHitReleaseMeta_alias
+      (_highArb_io_out_bits_snpHitReleaseMeta_alias),
+    .io_out_bits_snpHitReleaseMeta_prefetch
+      (_highArb_io_out_bits_snpHitReleaseMeta_prefetch),
+    .io_out_bits_snpHitReleaseMeta_prefetchSrc
+      (_highArb_io_out_bits_snpHitReleaseMeta_prefetchSrc),
+    .io_out_bits_snpHitReleaseMeta_accessed
+      (_highArb_io_out_bits_snpHitReleaseMeta_accessed),
+    .io_out_bits_snpHitReleaseMeta_tagErr
+      (_highArb_io_out_bits_snpHitReleaseMeta_tagErr),
+    .io_out_bits_snpHitReleaseMeta_dataErr
+      (_highArb_io_out_bits_snpHitReleaseMeta_dataErr),
+    .io_out_bits_tgtID                          (_highArb_io_out_bits_tgtID),
+    .io_out_bits_srcID                          (_highArb_io_out_bits_srcID),
+    .io_out_bits_txnID                          (_highArb_io_out_bits_txnID),
+    .io_out_bits_homeNID                        (_highArb_io_out_bits_homeNID),
+    .io_out_bits_dbID                           (_highArb_io_out_bits_dbID),
+    .io_out_bits_fwdNID                         (_highArb_io_out_bits_fwdNID),
+    .io_out_bits_fwdTxnID                       (_highArb_io_out_bits_fwdTxnID),
+    .io_out_bits_chiOpcode                      (_highArb_io_out_bits_chiOpcode),
+    .io_out_bits_resp                           (_highArb_io_out_bits_resp),
+    .io_out_bits_fwdState                       (_highArb_io_out_bits_fwdState),
+    .io_out_bits_pCrdType                       (_highArb_io_out_bits_pCrdType),
+    .io_out_bits_retToSrc                       (_highArb_io_out_bits_retToSrc),
+    .io_out_bits_likelyshared                   (_highArb_io_out_bits_likelyshared),
+    .io_out_bits_expCompAck                     (_highArb_io_out_bits_expCompAck),
+    .io_out_bits_allowRetry                     (_highArb_io_out_bits_allowRetry),
+    .io_out_bits_memAttr_allocate               (_highArb_io_out_bits_memAttr_allocate),
+    .io_out_bits_memAttr_cacheable              (_highArb_io_out_bits_memAttr_cacheable),
+    .io_out_bits_memAttr_device                 (_highArb_io_out_bits_memAttr_device),
+    .io_out_bits_memAttr_ewa                    (_highArb_io_out_bits_memAttr_ewa),
+    .io_out_bits_traceTag                       (_highArb_io_out_bits_traceTag)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_channel =
+    finalSelLow ? _lowArb_io_out_bits_channel : _highArb_io_out_bits_channel;
+  assign io_out_bits_txChannel =
+    finalSelLow ? _lowArb_io_out_bits_txChannel : _highArb_io_out_bits_txChannel;
+  assign io_out_bits_set =
+    finalSelLow ? _lowArb_io_out_bits_set : _highArb_io_out_bits_set;
+  assign io_out_bits_tag =
+    finalSelLow ? _lowArb_io_out_bits_tag : _highArb_io_out_bits_tag;
+  assign io_out_bits_off =
+    finalSelLow ? _lowArb_io_out_bits_off : _highArb_io_out_bits_off;
+  assign io_out_bits_alias =
+    finalSelLow ? _lowArb_io_out_bits_alias : _highArb_io_out_bits_alias;
+  assign io_out_bits_vaddr =
+    finalSelLow ? _lowArb_io_out_bits_vaddr : _highArb_io_out_bits_vaddr;
+  assign io_out_bits_isKeyword =
+    finalSelLow ? _lowArb_io_out_bits_isKeyword : _highArb_io_out_bits_isKeyword;
+  assign io_out_bits_opcode =
+    finalSelLow ? _lowArb_io_out_bits_opcode : _highArb_io_out_bits_opcode;
+  assign io_out_bits_param =
+    finalSelLow ? _lowArb_io_out_bits_param : _highArb_io_out_bits_param;
+  assign io_out_bits_size =
+    finalSelLow ? _lowArb_io_out_bits_size : _highArb_io_out_bits_size;
+  assign io_out_bits_sourceId =
+    finalSelLow ? _lowArb_io_out_bits_sourceId : _highArb_io_out_bits_sourceId;
+  assign io_out_bits_bufIdx =
+    finalSelLow ? _lowArb_io_out_bits_bufIdx : _highArb_io_out_bits_bufIdx;
+  assign io_out_bits_needProbeAckData =
+    finalSelLow
+      ? _lowArb_io_out_bits_needProbeAckData
+      : _highArb_io_out_bits_needProbeAckData;
+  assign io_out_bits_denied =
+    finalSelLow ? _lowArb_io_out_bits_denied : _highArb_io_out_bits_denied;
+  assign io_out_bits_corrupt =
+    finalSelLow ? _lowArb_io_out_bits_corrupt : _highArb_io_out_bits_corrupt;
+  assign io_out_bits_mshrTask =
+    finalSelLow ? _lowArb_io_out_bits_mshrTask : _highArb_io_out_bits_mshrTask;
+  assign io_out_bits_mshrId =
+    finalSelLow ? _lowArb_io_out_bits_mshrId : _highArb_io_out_bits_mshrId;
+  assign io_out_bits_aliasTask =
+    finalSelLow ? _lowArb_io_out_bits_aliasTask : _highArb_io_out_bits_aliasTask;
+  assign io_out_bits_useProbeData =
+    finalSelLow ? _lowArb_io_out_bits_useProbeData : _highArb_io_out_bits_useProbeData;
+  assign io_out_bits_mshrRetry =
+    finalSelLow ? _lowArb_io_out_bits_mshrRetry : _highArb_io_out_bits_mshrRetry;
+  assign io_out_bits_readProbeDataDown =
+    finalSelLow
+      ? _lowArb_io_out_bits_readProbeDataDown
+      : _highArb_io_out_bits_readProbeDataDown;
+  assign io_out_bits_fromL2pft =
+    finalSelLow ? _lowArb_io_out_bits_fromL2pft : _highArb_io_out_bits_fromL2pft;
+  assign io_out_bits_needHint =
+    finalSelLow ? _lowArb_io_out_bits_needHint : _highArb_io_out_bits_needHint;
+  assign io_out_bits_dirty =
+    finalSelLow ? _lowArb_io_out_bits_dirty : _highArb_io_out_bits_dirty;
+  assign io_out_bits_way =
+    finalSelLow ? _lowArb_io_out_bits_way : _highArb_io_out_bits_way;
+  assign io_out_bits_meta_dirty =
+    finalSelLow ? _lowArb_io_out_bits_meta_dirty : _highArb_io_out_bits_meta_dirty;
+  assign io_out_bits_meta_state =
+    finalSelLow ? _lowArb_io_out_bits_meta_state : _highArb_io_out_bits_meta_state;
+  assign io_out_bits_meta_clients =
+    finalSelLow ? _lowArb_io_out_bits_meta_clients : _highArb_io_out_bits_meta_clients;
+  assign io_out_bits_meta_alias =
+    finalSelLow ? _lowArb_io_out_bits_meta_alias : _highArb_io_out_bits_meta_alias;
+  assign io_out_bits_meta_prefetch =
+    finalSelLow ? _lowArb_io_out_bits_meta_prefetch : _highArb_io_out_bits_meta_prefetch;
+  assign io_out_bits_meta_prefetchSrc =
+    finalSelLow
+      ? _lowArb_io_out_bits_meta_prefetchSrc
+      : _highArb_io_out_bits_meta_prefetchSrc;
+  assign io_out_bits_meta_accessed =
+    finalSelLow ? _lowArb_io_out_bits_meta_accessed : _highArb_io_out_bits_meta_accessed;
+  assign io_out_bits_meta_tagErr =
+    finalSelLow ? _lowArb_io_out_bits_meta_tagErr : _highArb_io_out_bits_meta_tagErr;
+  assign io_out_bits_meta_dataErr =
+    finalSelLow ? _lowArb_io_out_bits_meta_dataErr : _highArb_io_out_bits_meta_dataErr;
+  assign io_out_bits_metaWen =
+    finalSelLow ? _lowArb_io_out_bits_metaWen : _highArb_io_out_bits_metaWen;
+  assign io_out_bits_tagWen =
+    finalSelLow ? _lowArb_io_out_bits_tagWen : _highArb_io_out_bits_tagWen;
+  assign io_out_bits_dsWen =
+    finalSelLow ? _lowArb_io_out_bits_dsWen : _highArb_io_out_bits_dsWen;
+  assign io_out_bits_wayMask =
+    finalSelLow ? _lowArb_io_out_bits_wayMask : _highArb_io_out_bits_wayMask;
+  assign io_out_bits_replTask =
+    finalSelLow ? _lowArb_io_out_bits_replTask : _highArb_io_out_bits_replTask;
+  assign io_out_bits_cmoTask =
+    finalSelLow ? _lowArb_io_out_bits_cmoTask : _highArb_io_out_bits_cmoTask;
+  assign io_out_bits_cmoAll =
+    finalSelLow ? _lowArb_io_out_bits_cmoAll : _highArb_io_out_bits_cmoAll;
+  assign io_out_bits_reqSource =
+    finalSelLow ? _lowArb_io_out_bits_reqSource : _highArb_io_out_bits_reqSource;
+  assign io_out_bits_mergeA =
+    finalSelLow ? _lowArb_io_out_bits_mergeA : _highArb_io_out_bits_mergeA;
+  assign io_out_bits_aMergeTask_off =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_off
+      : _highArb_io_out_bits_aMergeTask_off;
+  assign io_out_bits_aMergeTask_alias =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_alias
+      : _highArb_io_out_bits_aMergeTask_alias;
+  assign io_out_bits_aMergeTask_vaddr =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_vaddr
+      : _highArb_io_out_bits_aMergeTask_vaddr;
+  assign io_out_bits_aMergeTask_isKeyword =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_isKeyword
+      : _highArb_io_out_bits_aMergeTask_isKeyword;
+  assign io_out_bits_aMergeTask_opcode =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_opcode
+      : _highArb_io_out_bits_aMergeTask_opcode;
+  assign io_out_bits_aMergeTask_param =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_param
+      : _highArb_io_out_bits_aMergeTask_param;
+  assign io_out_bits_aMergeTask_sourceId =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_sourceId
+      : _highArb_io_out_bits_aMergeTask_sourceId;
+  assign io_out_bits_aMergeTask_meta_dirty =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_dirty
+      : _highArb_io_out_bits_aMergeTask_meta_dirty;
+  assign io_out_bits_aMergeTask_meta_state =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_state
+      : _highArb_io_out_bits_aMergeTask_meta_state;
+  assign io_out_bits_aMergeTask_meta_clients =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_clients
+      : _highArb_io_out_bits_aMergeTask_meta_clients;
+  assign io_out_bits_aMergeTask_meta_alias =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_alias
+      : _highArb_io_out_bits_aMergeTask_meta_alias;
+  assign io_out_bits_aMergeTask_meta_prefetch =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_prefetch
+      : _highArb_io_out_bits_aMergeTask_meta_prefetch;
+  assign io_out_bits_aMergeTask_meta_prefetchSrc =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_prefetchSrc
+      : _highArb_io_out_bits_aMergeTask_meta_prefetchSrc;
+  assign io_out_bits_aMergeTask_meta_accessed =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_accessed
+      : _highArb_io_out_bits_aMergeTask_meta_accessed;
+  assign io_out_bits_aMergeTask_meta_tagErr =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_tagErr
+      : _highArb_io_out_bits_aMergeTask_meta_tagErr;
+  assign io_out_bits_aMergeTask_meta_dataErr =
+    finalSelLow
+      ? _lowArb_io_out_bits_aMergeTask_meta_dataErr
+      : _highArb_io_out_bits_aMergeTask_meta_dataErr;
+  assign io_out_bits_snpHitRelease =
+    finalSelLow ? _lowArb_io_out_bits_snpHitRelease : _highArb_io_out_bits_snpHitRelease;
+  assign io_out_bits_snpHitReleaseToInval =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseToInval
+      : _highArb_io_out_bits_snpHitReleaseToInval;
+  assign io_out_bits_snpHitReleaseToClean =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseToClean
+      : _highArb_io_out_bits_snpHitReleaseToClean;
+  assign io_out_bits_snpHitReleaseWithData =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseWithData
+      : _highArb_io_out_bits_snpHitReleaseWithData;
+  assign io_out_bits_snpHitReleaseIdx =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseIdx
+      : _highArb_io_out_bits_snpHitReleaseIdx;
+  assign io_out_bits_snpHitReleaseMeta_dirty =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_dirty
+      : _highArb_io_out_bits_snpHitReleaseMeta_dirty;
+  assign io_out_bits_snpHitReleaseMeta_state =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_state
+      : _highArb_io_out_bits_snpHitReleaseMeta_state;
+  assign io_out_bits_snpHitReleaseMeta_clients =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_clients
+      : _highArb_io_out_bits_snpHitReleaseMeta_clients;
+  assign io_out_bits_snpHitReleaseMeta_alias =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_alias
+      : _highArb_io_out_bits_snpHitReleaseMeta_alias;
+  assign io_out_bits_snpHitReleaseMeta_prefetch =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_prefetch
+      : _highArb_io_out_bits_snpHitReleaseMeta_prefetch;
+  assign io_out_bits_snpHitReleaseMeta_prefetchSrc =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_prefetchSrc
+      : _highArb_io_out_bits_snpHitReleaseMeta_prefetchSrc;
+  assign io_out_bits_snpHitReleaseMeta_accessed =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_accessed
+      : _highArb_io_out_bits_snpHitReleaseMeta_accessed;
+  assign io_out_bits_snpHitReleaseMeta_tagErr =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_tagErr
+      : _highArb_io_out_bits_snpHitReleaseMeta_tagErr;
+  assign io_out_bits_snpHitReleaseMeta_dataErr =
+    finalSelLow
+      ? _lowArb_io_out_bits_snpHitReleaseMeta_dataErr
+      : _highArb_io_out_bits_snpHitReleaseMeta_dataErr;
+  assign io_out_bits_tgtID =
+    finalSelLow ? _lowArb_io_out_bits_tgtID : _highArb_io_out_bits_tgtID;
+  assign io_out_bits_srcID =
+    finalSelLow ? _lowArb_io_out_bits_srcID : _highArb_io_out_bits_srcID;
+  assign io_out_bits_txnID =
+    finalSelLow ? _lowArb_io_out_bits_txnID : _highArb_io_out_bits_txnID;
+  assign io_out_bits_homeNID =
+    finalSelLow ? _lowArb_io_out_bits_homeNID : _highArb_io_out_bits_homeNID;
+  assign io_out_bits_dbID =
+    finalSelLow ? _lowArb_io_out_bits_dbID : _highArb_io_out_bits_dbID;
+  assign io_out_bits_fwdNID =
+    finalSelLow ? _lowArb_io_out_bits_fwdNID : _highArb_io_out_bits_fwdNID;
+  assign io_out_bits_fwdTxnID =
+    finalSelLow ? _lowArb_io_out_bits_fwdTxnID : _highArb_io_out_bits_fwdTxnID;
+  assign io_out_bits_chiOpcode =
+    finalSelLow ? _lowArb_io_out_bits_chiOpcode : _highArb_io_out_bits_chiOpcode;
+  assign io_out_bits_resp =
+    finalSelLow ? _lowArb_io_out_bits_resp : _highArb_io_out_bits_resp;
+  assign io_out_bits_fwdState =
+    finalSelLow ? _lowArb_io_out_bits_fwdState : _highArb_io_out_bits_fwdState;
+  assign io_out_bits_pCrdType =
+    finalSelLow ? _lowArb_io_out_bits_pCrdType : _highArb_io_out_bits_pCrdType;
+  assign io_out_bits_retToSrc =
+    finalSelLow ? _lowArb_io_out_bits_retToSrc : _highArb_io_out_bits_retToSrc;
+  assign io_out_bits_likelyshared =
+    finalSelLow ? _lowArb_io_out_bits_likelyshared : _highArb_io_out_bits_likelyshared;
+  assign io_out_bits_expCompAck =
+    finalSelLow ? _lowArb_io_out_bits_expCompAck : _highArb_io_out_bits_expCompAck;
+  assign io_out_bits_allowRetry =
+    finalSelLow ? _lowArb_io_out_bits_allowRetry : _highArb_io_out_bits_allowRetry;
+  assign io_out_bits_memAttr_allocate =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_allocate
+      : _highArb_io_out_bits_memAttr_allocate;
+  assign io_out_bits_memAttr_cacheable =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_cacheable
+      : _highArb_io_out_bits_memAttr_cacheable;
+  assign io_out_bits_memAttr_device =
+    finalSelLow
+      ? _lowArb_io_out_bits_memAttr_device
+      : _highArb_io_out_bits_memAttr_device;
+  assign io_out_bits_memAttr_ewa =
+    finalSelLow ? _lowArb_io_out_bits_memAttr_ewa : _highArb_io_out_bits_memAttr_ewa;
+  assign io_out_bits_traceTag =
+    finalSelLow ? _lowArb_io_out_bits_traceTag : _highArb_io_out_bits_traceTag;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_5.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_5.sv
new file mode 100644
index 0000000000..f851b09983
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_5.sv
@@ -0,0 +1,405 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_5(
+  input         clock,
+  input         reset,
+  input         io_in_0_valid,
+  input         io_in_0_bits_valid,
+  input         io_in_0_bits_rdy,
+  input  [2:0]  io_in_0_bits_task_channel,
+  input  [7:0]  io_in_0_bits_task_set,
+  input  [33:0] io_in_0_bits_task_tag,
+  input  [5:0]  io_in_0_bits_task_off,
+  input         io_in_0_bits_task_alias,
+  input  [43:0] io_in_0_bits_task_vaddr,
+  input         io_in_0_bits_task_isKeyword,
+  input  [3:0]  io_in_0_bits_task_opcode,
+  input  [2:0]  io_in_0_bits_task_param,
+  input  [2:0]  io_in_0_bits_task_size,
+  input  [6:0]  io_in_0_bits_task_sourceId,
+  input         io_in_0_bits_task_corrupt,
+  input         io_in_0_bits_task_fromL2pft,
+  input         io_in_0_bits_task_needHint,
+  input  [4:0]  io_in_0_bits_task_reqSource,
+  input  [3:0]  io_in_0_bits_waitMP,
+  input  [15:0] io_in_0_bits_waitMS,
+  input         io_in_1_valid,
+  input         io_in_1_bits_valid,
+  input         io_in_1_bits_rdy,
+  input  [2:0]  io_in_1_bits_task_channel,
+  input  [7:0]  io_in_1_bits_task_set,
+  input  [33:0] io_in_1_bits_task_tag,
+  input  [5:0]  io_in_1_bits_task_off,
+  input         io_in_1_bits_task_alias,
+  input  [43:0] io_in_1_bits_task_vaddr,
+  input         io_in_1_bits_task_isKeyword,
+  input  [3:0]  io_in_1_bits_task_opcode,
+  input  [2:0]  io_in_1_bits_task_param,
+  input  [2:0]  io_in_1_bits_task_size,
+  input  [6:0]  io_in_1_bits_task_sourceId,
+  input         io_in_1_bits_task_corrupt,
+  input         io_in_1_bits_task_fromL2pft,
+  input         io_in_1_bits_task_needHint,
+  input  [4:0]  io_in_1_bits_task_reqSource,
+  input  [3:0]  io_in_1_bits_waitMP,
+  input  [15:0] io_in_1_bits_waitMS,
+  input         io_in_2_valid,
+  input         io_in_2_bits_valid,
+  input         io_in_2_bits_rdy,
+  input  [2:0]  io_in_2_bits_task_channel,
+  input  [7:0]  io_in_2_bits_task_set,
+  input  [33:0] io_in_2_bits_task_tag,
+  input  [5:0]  io_in_2_bits_task_off,
+  input         io_in_2_bits_task_alias,
+  input  [43:0] io_in_2_bits_task_vaddr,
+  input         io_in_2_bits_task_isKeyword,
+  input  [3:0]  io_in_2_bits_task_opcode,
+  input  [2:0]  io_in_2_bits_task_param,
+  input  [2:0]  io_in_2_bits_task_size,
+  input  [6:0]  io_in_2_bits_task_sourceId,
+  input         io_in_2_bits_task_corrupt,
+  input         io_in_2_bits_task_fromL2pft,
+  input         io_in_2_bits_task_needHint,
+  input  [4:0]  io_in_2_bits_task_reqSource,
+  input  [3:0]  io_in_2_bits_waitMP,
+  input  [15:0] io_in_2_bits_waitMS,
+  input         io_in_3_valid,
+  input         io_in_3_bits_valid,
+  input         io_in_3_bits_rdy,
+  input  [2:0]  io_in_3_bits_task_channel,
+  input  [7:0]  io_in_3_bits_task_set,
+  input  [33:0] io_in_3_bits_task_tag,
+  input  [5:0]  io_in_3_bits_task_off,
+  input         io_in_3_bits_task_alias,
+  input  [43:0] io_in_3_bits_task_vaddr,
+  input         io_in_3_bits_task_isKeyword,
+  input  [3:0]  io_in_3_bits_task_opcode,
+  input  [2:0]  io_in_3_bits_task_param,
+  input  [2:0]  io_in_3_bits_task_size,
+  input  [6:0]  io_in_3_bits_task_sourceId,
+  input         io_in_3_bits_task_corrupt,
+  input         io_in_3_bits_task_fromL2pft,
+  input         io_in_3_bits_task_needHint,
+  input  [4:0]  io_in_3_bits_task_reqSource,
+  input  [3:0]  io_in_3_bits_waitMP,
+  input  [15:0] io_in_3_bits_waitMS,
+  input         io_out_ready,
+  output        io_out_valid,
+  output        io_out_bits_valid,
+  output        io_out_bits_rdy,
+  output [2:0]  io_out_bits_task_channel,
+  output [7:0]  io_out_bits_task_set,
+  output [33:0] io_out_bits_task_tag,
+  output [5:0]  io_out_bits_task_off,
+  output        io_out_bits_task_alias,
+  output [43:0] io_out_bits_task_vaddr,
+  output        io_out_bits_task_isKeyword,
+  output [3:0]  io_out_bits_task_opcode,
+  output [2:0]  io_out_bits_task_param,
+  output [2:0]  io_out_bits_task_size,
+  output [6:0]  io_out_bits_task_sourceId,
+  output        io_out_bits_task_corrupt,
+  output        io_out_bits_task_fromL2pft,
+  output        io_out_bits_task_needHint,
+  output [4:0]  io_out_bits_task_reqSource,
+  output [3:0]  io_out_bits_waitMP,
+  output [15:0] io_out_bits_waitMS,
+  output [3:0]  io_chosenOH
+);
+
+  wire        _highArb_io_out_valid;
+  wire        _highArb_io_out_bits_valid;
+  wire        _highArb_io_out_bits_rdy;
+  wire [2:0]  _highArb_io_out_bits_task_channel;
+  wire [7:0]  _highArb_io_out_bits_task_set;
+  wire [33:0] _highArb_io_out_bits_task_tag;
+  wire [5:0]  _highArb_io_out_bits_task_off;
+  wire        _highArb_io_out_bits_task_alias;
+  wire [43:0] _highArb_io_out_bits_task_vaddr;
+  wire        _highArb_io_out_bits_task_isKeyword;
+  wire [3:0]  _highArb_io_out_bits_task_opcode;
+  wire [2:0]  _highArb_io_out_bits_task_param;
+  wire [2:0]  _highArb_io_out_bits_task_size;
+  wire [6:0]  _highArb_io_out_bits_task_sourceId;
+  wire        _highArb_io_out_bits_task_corrupt;
+  wire        _highArb_io_out_bits_task_fromL2pft;
+  wire        _highArb_io_out_bits_task_needHint;
+  wire [4:0]  _highArb_io_out_bits_task_reqSource;
+  wire [3:0]  _highArb_io_out_bits_waitMP;
+  wire [15:0] _highArb_io_out_bits_waitMS;
+  wire [1:0]  _highArb_io_chosenOH;
+  wire        _lowArb_io_out_valid;
+  wire        _lowArb_io_out_bits_valid;
+  wire        _lowArb_io_out_bits_rdy;
+  wire [2:0]  _lowArb_io_out_bits_task_channel;
+  wire [7:0]  _lowArb_io_out_bits_task_set;
+  wire [33:0] _lowArb_io_out_bits_task_tag;
+  wire [5:0]  _lowArb_io_out_bits_task_off;
+  wire        _lowArb_io_out_bits_task_alias;
+  wire [43:0] _lowArb_io_out_bits_task_vaddr;
+  wire        _lowArb_io_out_bits_task_isKeyword;
+  wire [3:0]  _lowArb_io_out_bits_task_opcode;
+  wire [2:0]  _lowArb_io_out_bits_task_param;
+  wire [2:0]  _lowArb_io_out_bits_task_size;
+  wire [6:0]  _lowArb_io_out_bits_task_sourceId;
+  wire        _lowArb_io_out_bits_task_corrupt;
+  wire        _lowArb_io_out_bits_task_fromL2pft;
+  wire        _lowArb_io_out_bits_task_needHint;
+  wire [4:0]  _lowArb_io_out_bits_task_reqSource;
+  wire [3:0]  _lowArb_io_out_bits_waitMP;
+  wire [15:0] _lowArb_io_out_bits_waitMS;
+  wire [1:0]  _lowArb_io_chosenOH;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_ready & io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_12 lowArb (
+    .clock                       (clock),
+    .reset                       (reset),
+    .io_in_0_valid               (io_in_0_valid),
+    .io_in_0_bits_valid          (io_in_0_bits_valid),
+    .io_in_0_bits_rdy            (io_in_0_bits_rdy),
+    .io_in_0_bits_task_channel   (io_in_0_bits_task_channel),
+    .io_in_0_bits_task_set       (io_in_0_bits_task_set),
+    .io_in_0_bits_task_tag       (io_in_0_bits_task_tag),
+    .io_in_0_bits_task_off       (io_in_0_bits_task_off),
+    .io_in_0_bits_task_alias     (io_in_0_bits_task_alias),
+    .io_in_0_bits_task_vaddr     (io_in_0_bits_task_vaddr),
+    .io_in_0_bits_task_isKeyword (io_in_0_bits_task_isKeyword),
+    .io_in_0_bits_task_opcode    (io_in_0_bits_task_opcode),
+    .io_in_0_bits_task_param     (io_in_0_bits_task_param),
+    .io_in_0_bits_task_size      (io_in_0_bits_task_size),
+    .io_in_0_bits_task_sourceId  (io_in_0_bits_task_sourceId),
+    .io_in_0_bits_task_corrupt   (io_in_0_bits_task_corrupt),
+    .io_in_0_bits_task_fromL2pft (io_in_0_bits_task_fromL2pft),
+    .io_in_0_bits_task_needHint  (io_in_0_bits_task_needHint),
+    .io_in_0_bits_task_reqSource (io_in_0_bits_task_reqSource),
+    .io_in_0_bits_waitMP         (io_in_0_bits_waitMP),
+    .io_in_0_bits_waitMS         (io_in_0_bits_waitMS),
+    .io_in_1_valid               (io_in_1_valid),
+    .io_in_1_bits_valid          (io_in_1_bits_valid),
+    .io_in_1_bits_rdy            (io_in_1_bits_rdy),
+    .io_in_1_bits_task_channel   (io_in_1_bits_task_channel),
+    .io_in_1_bits_task_set       (io_in_1_bits_task_set),
+    .io_in_1_bits_task_tag       (io_in_1_bits_task_tag),
+    .io_in_1_bits_task_off       (io_in_1_bits_task_off),
+    .io_in_1_bits_task_alias     (io_in_1_bits_task_alias),
+    .io_in_1_bits_task_vaddr     (io_in_1_bits_task_vaddr),
+    .io_in_1_bits_task_isKeyword (io_in_1_bits_task_isKeyword),
+    .io_in_1_bits_task_opcode    (io_in_1_bits_task_opcode),
+    .io_in_1_bits_task_param     (io_in_1_bits_task_param),
+    .io_in_1_bits_task_size      (io_in_1_bits_task_size),
+    .io_in_1_bits_task_sourceId  (io_in_1_bits_task_sourceId),
+    .io_in_1_bits_task_corrupt   (io_in_1_bits_task_corrupt),
+    .io_in_1_bits_task_fromL2pft (io_in_1_bits_task_fromL2pft),
+    .io_in_1_bits_task_needHint  (io_in_1_bits_task_needHint),
+    .io_in_1_bits_task_reqSource (io_in_1_bits_task_reqSource),
+    .io_in_1_bits_waitMP         (io_in_1_bits_waitMP),
+    .io_in_1_bits_waitMS         (io_in_1_bits_waitMS),
+    .io_out_ready                (io_out_ready & finalSelLow),
+    .io_out_valid                (_lowArb_io_out_valid),
+    .io_out_bits_valid           (_lowArb_io_out_bits_valid),
+    .io_out_bits_rdy             (_lowArb_io_out_bits_rdy),
+    .io_out_bits_task_channel    (_lowArb_io_out_bits_task_channel),
+    .io_out_bits_task_set        (_lowArb_io_out_bits_task_set),
+    .io_out_bits_task_tag        (_lowArb_io_out_bits_task_tag),
+    .io_out_bits_task_off        (_lowArb_io_out_bits_task_off),
+    .io_out_bits_task_alias      (_lowArb_io_out_bits_task_alias),
+    .io_out_bits_task_vaddr      (_lowArb_io_out_bits_task_vaddr),
+    .io_out_bits_task_isKeyword  (_lowArb_io_out_bits_task_isKeyword),
+    .io_out_bits_task_opcode     (_lowArb_io_out_bits_task_opcode),
+    .io_out_bits_task_param      (_lowArb_io_out_bits_task_param),
+    .io_out_bits_task_size       (_lowArb_io_out_bits_task_size),
+    .io_out_bits_task_sourceId   (_lowArb_io_out_bits_task_sourceId),
+    .io_out_bits_task_corrupt    (_lowArb_io_out_bits_task_corrupt),
+    .io_out_bits_task_fromL2pft  (_lowArb_io_out_bits_task_fromL2pft),
+    .io_out_bits_task_needHint   (_lowArb_io_out_bits_task_needHint),
+    .io_out_bits_task_reqSource  (_lowArb_io_out_bits_task_reqSource),
+    .io_out_bits_waitMP          (_lowArb_io_out_bits_waitMP),
+    .io_out_bits_waitMS          (_lowArb_io_out_bits_waitMS),
+    .io_chosenOH                 (_lowArb_io_chosenOH)
+  );
+  FastArbiter_12 highArb (
+    .clock                       (clock),
+    .reset                       (reset),
+    .io_in_0_valid               (io_in_2_valid),
+    .io_in_0_bits_valid          (io_in_2_bits_valid),
+    .io_in_0_bits_rdy            (io_in_2_bits_rdy),
+    .io_in_0_bits_task_channel   (io_in_2_bits_task_channel),
+    .io_in_0_bits_task_set       (io_in_2_bits_task_set),
+    .io_in_0_bits_task_tag       (io_in_2_bits_task_tag),
+    .io_in_0_bits_task_off       (io_in_2_bits_task_off),
+    .io_in_0_bits_task_alias     (io_in_2_bits_task_alias),
+    .io_in_0_bits_task_vaddr     (io_in_2_bits_task_vaddr),
+    .io_in_0_bits_task_isKeyword (io_in_2_bits_task_isKeyword),
+    .io_in_0_bits_task_opcode    (io_in_2_bits_task_opcode),
+    .io_in_0_bits_task_param     (io_in_2_bits_task_param),
+    .io_in_0_bits_task_size      (io_in_2_bits_task_size),
+    .io_in_0_bits_task_sourceId  (io_in_2_bits_task_sourceId),
+    .io_in_0_bits_task_corrupt   (io_in_2_bits_task_corrupt),
+    .io_in_0_bits_task_fromL2pft (io_in_2_bits_task_fromL2pft),
+    .io_in_0_bits_task_needHint  (io_in_2_bits_task_needHint),
+    .io_in_0_bits_task_reqSource (io_in_2_bits_task_reqSource),
+    .io_in_0_bits_waitMP         (io_in_2_bits_waitMP),
+    .io_in_0_bits_waitMS         (io_in_2_bits_waitMS),
+    .io_in_1_valid               (io_in_3_valid),
+    .io_in_1_bits_valid          (io_in_3_bits_valid),
+    .io_in_1_bits_rdy            (io_in_3_bits_rdy),
+    .io_in_1_bits_task_channel   (io_in_3_bits_task_channel),
+    .io_in_1_bits_task_set       (io_in_3_bits_task_set),
+    .io_in_1_bits_task_tag       (io_in_3_bits_task_tag),
+    .io_in_1_bits_task_off       (io_in_3_bits_task_off),
+    .io_in_1_bits_task_alias     (io_in_3_bits_task_alias),
+    .io_in_1_bits_task_vaddr     (io_in_3_bits_task_vaddr),
+    .io_in_1_bits_task_isKeyword (io_in_3_bits_task_isKeyword),
+    .io_in_1_bits_task_opcode    (io_in_3_bits_task_opcode),
+    .io_in_1_bits_task_param     (io_in_3_bits_task_param),
+    .io_in_1_bits_task_size      (io_in_3_bits_task_size),
+    .io_in_1_bits_task_sourceId  (io_in_3_bits_task_sourceId),
+    .io_in_1_bits_task_corrupt   (io_in_3_bits_task_corrupt),
+    .io_in_1_bits_task_fromL2pft (io_in_3_bits_task_fromL2pft),
+    .io_in_1_bits_task_needHint  (io_in_3_bits_task_needHint),
+    .io_in_1_bits_task_reqSource (io_in_3_bits_task_reqSource),
+    .io_in_1_bits_waitMP         (io_in_3_bits_waitMP),
+    .io_in_1_bits_waitMS         (io_in_3_bits_waitMS),
+    .io_out_ready                (io_out_ready & ~finalSelLow),
+    .io_out_valid                (_highArb_io_out_valid),
+    .io_out_bits_valid           (_highArb_io_out_bits_valid),
+    .io_out_bits_rdy             (_highArb_io_out_bits_rdy),
+    .io_out_bits_task_channel    (_highArb_io_out_bits_task_channel),
+    .io_out_bits_task_set        (_highArb_io_out_bits_task_set),
+    .io_out_bits_task_tag        (_highArb_io_out_bits_task_tag),
+    .io_out_bits_task_off        (_highArb_io_out_bits_task_off),
+    .io_out_bits_task_alias      (_highArb_io_out_bits_task_alias),
+    .io_out_bits_task_vaddr      (_highArb_io_out_bits_task_vaddr),
+    .io_out_bits_task_isKeyword  (_highArb_io_out_bits_task_isKeyword),
+    .io_out_bits_task_opcode     (_highArb_io_out_bits_task_opcode),
+    .io_out_bits_task_param      (_highArb_io_out_bits_task_param),
+    .io_out_bits_task_size       (_highArb_io_out_bits_task_size),
+    .io_out_bits_task_sourceId   (_highArb_io_out_bits_task_sourceId),
+    .io_out_bits_task_corrupt    (_highArb_io_out_bits_task_corrupt),
+    .io_out_bits_task_fromL2pft  (_highArb_io_out_bits_task_fromL2pft),
+    .io_out_bits_task_needHint   (_highArb_io_out_bits_task_needHint),
+    .io_out_bits_task_reqSource  (_highArb_io_out_bits_task_reqSource),
+    .io_out_bits_waitMP          (_highArb_io_out_bits_waitMP),
+    .io_out_bits_waitMS          (_highArb_io_out_bits_waitMS),
+    .io_chosenOH                 (_highArb_io_chosenOH)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_valid =
+    finalSelLow ? _lowArb_io_out_bits_valid : _highArb_io_out_bits_valid;
+  assign io_out_bits_rdy =
+    finalSelLow ? _lowArb_io_out_bits_rdy : _highArb_io_out_bits_rdy;
+  assign io_out_bits_task_channel =
+    finalSelLow ? _lowArb_io_out_bits_task_channel : _highArb_io_out_bits_task_channel;
+  assign io_out_bits_task_set =
+    finalSelLow ? _lowArb_io_out_bits_task_set : _highArb_io_out_bits_task_set;
+  assign io_out_bits_task_tag =
+    finalSelLow ? _lowArb_io_out_bits_task_tag : _highArb_io_out_bits_task_tag;
+  assign io_out_bits_task_off =
+    finalSelLow ? _lowArb_io_out_bits_task_off : _highArb_io_out_bits_task_off;
+  assign io_out_bits_task_alias =
+    finalSelLow ? _lowArb_io_out_bits_task_alias : _highArb_io_out_bits_task_alias;
+  assign io_out_bits_task_vaddr =
+    finalSelLow ? _lowArb_io_out_bits_task_vaddr : _highArb_io_out_bits_task_vaddr;
+  assign io_out_bits_task_isKeyword =
+    finalSelLow
+      ? _lowArb_io_out_bits_task_isKeyword
+      : _highArb_io_out_bits_task_isKeyword;
+  assign io_out_bits_task_opcode =
+    finalSelLow ? _lowArb_io_out_bits_task_opcode : _highArb_io_out_bits_task_opcode;
+  assign io_out_bits_task_param =
+    finalSelLow ? _lowArb_io_out_bits_task_param : _highArb_io_out_bits_task_param;
+  assign io_out_bits_task_size =
+    finalSelLow ? _lowArb_io_out_bits_task_size : _highArb_io_out_bits_task_size;
+  assign io_out_bits_task_sourceId =
+    finalSelLow ? _lowArb_io_out_bits_task_sourceId : _highArb_io_out_bits_task_sourceId;
+  assign io_out_bits_task_corrupt =
+    finalSelLow ? _lowArb_io_out_bits_task_corrupt : _highArb_io_out_bits_task_corrupt;
+  assign io_out_bits_task_fromL2pft =
+    finalSelLow
+      ? _lowArb_io_out_bits_task_fromL2pft
+      : _highArb_io_out_bits_task_fromL2pft;
+  assign io_out_bits_task_needHint =
+    finalSelLow ? _lowArb_io_out_bits_task_needHint : _highArb_io_out_bits_task_needHint;
+  assign io_out_bits_task_reqSource =
+    finalSelLow
+      ? _lowArb_io_out_bits_task_reqSource
+      : _highArb_io_out_bits_task_reqSource;
+  assign io_out_bits_waitMP =
+    finalSelLow ? _lowArb_io_out_bits_waitMP : _highArb_io_out_bits_waitMP;
+  assign io_out_bits_waitMS =
+    finalSelLow ? _lowArb_io_out_bits_waitMS : _highArb_io_out_bits_waitMS;
+  assign io_chosenOH =
+    {{2{~finalSelLow}} & _highArb_io_chosenOH, {2{finalSelLow}} & _lowArb_io_chosenOH};
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_7.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_7.sv
new file mode 100644
index 0000000000..00174c486b
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_7.sv
@@ -0,0 +1,287 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_7(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [10:0] io_in_0_bits_tgtID,
+  input  [11:0] io_in_0_bits_txnID,
+  input         io_in_0_bits_traceTag,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [10:0] io_in_1_bits_tgtID,
+  input  [11:0] io_in_1_bits_txnID,
+  input         io_in_1_bits_traceTag,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [10:0] io_in_2_bits_tgtID,
+  input  [11:0] io_in_2_bits_txnID,
+  input         io_in_2_bits_traceTag,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [10:0] io_in_3_bits_tgtID,
+  input  [11:0] io_in_3_bits_txnID,
+  input         io_in_3_bits_traceTag,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [10:0] io_in_4_bits_tgtID,
+  input  [11:0] io_in_4_bits_txnID,
+  input         io_in_4_bits_traceTag,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [10:0] io_in_5_bits_tgtID,
+  input  [11:0] io_in_5_bits_txnID,
+  input         io_in_5_bits_traceTag,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [10:0] io_in_6_bits_tgtID,
+  input  [11:0] io_in_6_bits_txnID,
+  input         io_in_6_bits_traceTag,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [10:0] io_in_7_bits_tgtID,
+  input  [11:0] io_in_7_bits_txnID,
+  input         io_in_7_bits_traceTag,
+  output        io_in_8_ready,
+  input         io_in_8_valid,
+  input  [10:0] io_in_8_bits_tgtID,
+  input  [11:0] io_in_8_bits_txnID,
+  input         io_in_8_bits_traceTag,
+  output        io_in_9_ready,
+  input         io_in_9_valid,
+  input  [10:0] io_in_9_bits_tgtID,
+  input  [11:0] io_in_9_bits_txnID,
+  input         io_in_9_bits_traceTag,
+  output        io_in_10_ready,
+  input         io_in_10_valid,
+  input  [10:0] io_in_10_bits_tgtID,
+  input  [11:0] io_in_10_bits_txnID,
+  input         io_in_10_bits_traceTag,
+  output        io_in_11_ready,
+  input         io_in_11_valid,
+  input  [10:0] io_in_11_bits_tgtID,
+  input  [11:0] io_in_11_bits_txnID,
+  input         io_in_11_bits_traceTag,
+  output        io_in_12_ready,
+  input         io_in_12_valid,
+  input  [10:0] io_in_12_bits_tgtID,
+  input  [11:0] io_in_12_bits_txnID,
+  input         io_in_12_bits_traceTag,
+  output        io_in_13_ready,
+  input         io_in_13_valid,
+  input  [10:0] io_in_13_bits_tgtID,
+  input  [11:0] io_in_13_bits_txnID,
+  input         io_in_13_bits_traceTag,
+  output        io_in_14_ready,
+  input         io_in_14_valid,
+  input  [10:0] io_in_14_bits_tgtID,
+  input  [11:0] io_in_14_bits_txnID,
+  input         io_in_14_bits_traceTag,
+  output        io_in_15_ready,
+  input         io_in_15_valid,
+  input  [10:0] io_in_15_bits_tgtID,
+  input  [11:0] io_in_15_bits_txnID,
+  input         io_in_15_bits_traceTag,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [10:0] io_out_bits_tgtID,
+  output [11:0] io_out_bits_txnID,
+  output [4:0]  io_out_bits_opcode,
+  output        io_out_bits_traceTag
+);
+
+  wire        _highArb_io_out_valid;
+  wire [10:0] _highArb_io_out_bits_tgtID;
+  wire [11:0] _highArb_io_out_bits_txnID;
+  wire [4:0]  _highArb_io_out_bits_opcode;
+  wire        _highArb_io_out_bits_traceTag;
+  wire        _lowArb_io_out_valid;
+  wire [10:0] _lowArb_io_out_bits_tgtID;
+  wire [11:0] _lowArb_io_out_bits_txnID;
+  wire [4:0]  _lowArb_io_out_bits_opcode;
+  wire        _lowArb_io_out_bits_traceTag;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_ready & io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_16 lowArb (
+    .clock                 (clock),
+    .reset                 (reset),
+    .io_in_0_ready         (io_in_0_ready),
+    .io_in_0_valid         (io_in_0_valid),
+    .io_in_0_bits_tgtID    (io_in_0_bits_tgtID),
+    .io_in_0_bits_txnID    (io_in_0_bits_txnID),
+    .io_in_0_bits_traceTag (io_in_0_bits_traceTag),
+    .io_in_1_ready         (io_in_1_ready),
+    .io_in_1_valid         (io_in_1_valid),
+    .io_in_1_bits_tgtID    (io_in_1_bits_tgtID),
+    .io_in_1_bits_txnID    (io_in_1_bits_txnID),
+    .io_in_1_bits_traceTag (io_in_1_bits_traceTag),
+    .io_in_2_ready         (io_in_2_ready),
+    .io_in_2_valid         (io_in_2_valid),
+    .io_in_2_bits_tgtID    (io_in_2_bits_tgtID),
+    .io_in_2_bits_txnID    (io_in_2_bits_txnID),
+    .io_in_2_bits_traceTag (io_in_2_bits_traceTag),
+    .io_in_3_ready         (io_in_3_ready),
+    .io_in_3_valid         (io_in_3_valid),
+    .io_in_3_bits_tgtID    (io_in_3_bits_tgtID),
+    .io_in_3_bits_txnID    (io_in_3_bits_txnID),
+    .io_in_3_bits_traceTag (io_in_3_bits_traceTag),
+    .io_in_4_ready         (io_in_4_ready),
+    .io_in_4_valid         (io_in_4_valid),
+    .io_in_4_bits_tgtID    (io_in_4_bits_tgtID),
+    .io_in_4_bits_txnID    (io_in_4_bits_txnID),
+    .io_in_4_bits_traceTag (io_in_4_bits_traceTag),
+    .io_in_5_ready         (io_in_5_ready),
+    .io_in_5_valid         (io_in_5_valid),
+    .io_in_5_bits_tgtID    (io_in_5_bits_tgtID),
+    .io_in_5_bits_txnID    (io_in_5_bits_txnID),
+    .io_in_5_bits_traceTag (io_in_5_bits_traceTag),
+    .io_in_6_ready         (io_in_6_ready),
+    .io_in_6_valid         (io_in_6_valid),
+    .io_in_6_bits_tgtID    (io_in_6_bits_tgtID),
+    .io_in_6_bits_txnID    (io_in_6_bits_txnID),
+    .io_in_6_bits_traceTag (io_in_6_bits_traceTag),
+    .io_in_7_ready         (io_in_7_ready),
+    .io_in_7_valid         (io_in_7_valid),
+    .io_in_7_bits_tgtID    (io_in_7_bits_tgtID),
+    .io_in_7_bits_txnID    (io_in_7_bits_txnID),
+    .io_in_7_bits_traceTag (io_in_7_bits_traceTag),
+    .io_out_ready          (io_out_ready & finalSelLow),
+    .io_out_valid          (_lowArb_io_out_valid),
+    .io_out_bits_tgtID     (_lowArb_io_out_bits_tgtID),
+    .io_out_bits_txnID     (_lowArb_io_out_bits_txnID),
+    .io_out_bits_opcode    (_lowArb_io_out_bits_opcode),
+    .io_out_bits_traceTag  (_lowArb_io_out_bits_traceTag)
+  );
+  FastArbiter_16 highArb (
+    .clock                 (clock),
+    .reset                 (reset),
+    .io_in_0_ready         (io_in_8_ready),
+    .io_in_0_valid         (io_in_8_valid),
+    .io_in_0_bits_tgtID    (io_in_8_bits_tgtID),
+    .io_in_0_bits_txnID    (io_in_8_bits_txnID),
+    .io_in_0_bits_traceTag (io_in_8_bits_traceTag),
+    .io_in_1_ready         (io_in_9_ready),
+    .io_in_1_valid         (io_in_9_valid),
+    .io_in_1_bits_tgtID    (io_in_9_bits_tgtID),
+    .io_in_1_bits_txnID    (io_in_9_bits_txnID),
+    .io_in_1_bits_traceTag (io_in_9_bits_traceTag),
+    .io_in_2_ready         (io_in_10_ready),
+    .io_in_2_valid         (io_in_10_valid),
+    .io_in_2_bits_tgtID    (io_in_10_bits_tgtID),
+    .io_in_2_bits_txnID    (io_in_10_bits_txnID),
+    .io_in_2_bits_traceTag (io_in_10_bits_traceTag),
+    .io_in_3_ready         (io_in_11_ready),
+    .io_in_3_valid         (io_in_11_valid),
+    .io_in_3_bits_tgtID    (io_in_11_bits_tgtID),
+    .io_in_3_bits_txnID    (io_in_11_bits_txnID),
+    .io_in_3_bits_traceTag (io_in_11_bits_traceTag),
+    .io_in_4_ready         (io_in_12_ready),
+    .io_in_4_valid         (io_in_12_valid),
+    .io_in_4_bits_tgtID    (io_in_12_bits_tgtID),
+    .io_in_4_bits_txnID    (io_in_12_bits_txnID),
+    .io_in_4_bits_traceTag (io_in_12_bits_traceTag),
+    .io_in_5_ready         (io_in_13_ready),
+    .io_in_5_valid         (io_in_13_valid),
+    .io_in_5_bits_tgtID    (io_in_13_bits_tgtID),
+    .io_in_5_bits_txnID    (io_in_13_bits_txnID),
+    .io_in_5_bits_traceTag (io_in_13_bits_traceTag),
+    .io_in_6_ready         (io_in_14_ready),
+    .io_in_6_valid         (io_in_14_valid),
+    .io_in_6_bits_tgtID    (io_in_14_bits_tgtID),
+    .io_in_6_bits_txnID    (io_in_14_bits_txnID),
+    .io_in_6_bits_traceTag (io_in_14_bits_traceTag),
+    .io_in_7_ready         (io_in_15_ready),
+    .io_in_7_valid         (io_in_15_valid),
+    .io_in_7_bits_tgtID    (io_in_15_bits_tgtID),
+    .io_in_7_bits_txnID    (io_in_15_bits_txnID),
+    .io_in_7_bits_traceTag (io_in_15_bits_traceTag),
+    .io_out_ready          (io_out_ready & ~finalSelLow),
+    .io_out_valid          (_highArb_io_out_valid),
+    .io_out_bits_tgtID     (_highArb_io_out_bits_tgtID),
+    .io_out_bits_txnID     (_highArb_io_out_bits_txnID),
+    .io_out_bits_opcode    (_highArb_io_out_bits_opcode),
+    .io_out_bits_traceTag  (_highArb_io_out_bits_traceTag)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_tgtID =
+    finalSelLow ? _lowArb_io_out_bits_tgtID : _highArb_io_out_bits_tgtID;
+  assign io_out_bits_txnID =
+    finalSelLow ? _lowArb_io_out_bits_txnID : _highArb_io_out_bits_txnID;
+  assign io_out_bits_opcode =
+    finalSelLow ? _lowArb_io_out_bits_opcode : _highArb_io_out_bits_opcode;
+  assign io_out_bits_traceTag =
+    finalSelLow ? _lowArb_io_out_bits_traceTag : _highArb_io_out_bits_traceTag;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_8.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_8.sv
new file mode 100644
index 0000000000..0d2dce3243
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_8.sv
@@ -0,0 +1,190 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_8(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [33:0] io_in_0_bits_tag,
+  input  [7:0]  io_in_0_bits_set,
+  input  [2:0]  io_in_0_bits_opcode,
+  input  [1:0]  io_in_0_bits_param,
+  input         io_in_0_bits_alias,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [33:0] io_in_1_bits_tag,
+  input  [7:0]  io_in_1_bits_set,
+  input  [2:0]  io_in_1_bits_opcode,
+  input  [1:0]  io_in_1_bits_param,
+  input         io_in_1_bits_alias,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [33:0] io_in_2_bits_tag,
+  input  [7:0]  io_in_2_bits_set,
+  input  [2:0]  io_in_2_bits_opcode,
+  input  [1:0]  io_in_2_bits_param,
+  input         io_in_2_bits_alias,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [33:0] io_in_3_bits_tag,
+  input  [7:0]  io_in_3_bits_set,
+  input  [2:0]  io_in_3_bits_opcode,
+  input  [1:0]  io_in_3_bits_param,
+  input         io_in_3_bits_alias,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [33:0] io_out_bits_tag,
+  output [7:0]  io_out_bits_set,
+  output [2:0]  io_out_bits_opcode,
+  output [1:0]  io_out_bits_param,
+  output        io_out_bits_alias
+);
+
+  wire        _highArb_io_out_valid;
+  wire [33:0] _highArb_io_out_bits_tag;
+  wire [7:0]  _highArb_io_out_bits_set;
+  wire [2:0]  _highArb_io_out_bits_opcode;
+  wire [1:0]  _highArb_io_out_bits_param;
+  wire        _highArb_io_out_bits_alias;
+  wire        _lowArb_io_out_valid;
+  wire [33:0] _lowArb_io_out_bits_tag;
+  wire [7:0]  _lowArb_io_out_bits_set;
+  wire [2:0]  _lowArb_io_out_bits_opcode;
+  wire [1:0]  _lowArb_io_out_bits_param;
+  wire        _lowArb_io_out_bits_alias;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_ready & io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_18 lowArb (
+    .clock               (clock),
+    .reset               (reset),
+    .io_in_0_ready       (io_in_0_ready),
+    .io_in_0_valid       (io_in_0_valid),
+    .io_in_0_bits_tag    (io_in_0_bits_tag),
+    .io_in_0_bits_set    (io_in_0_bits_set),
+    .io_in_0_bits_opcode (io_in_0_bits_opcode),
+    .io_in_0_bits_param  (io_in_0_bits_param),
+    .io_in_0_bits_alias  (io_in_0_bits_alias),
+    .io_in_1_ready       (io_in_1_ready),
+    .io_in_1_valid       (io_in_1_valid),
+    .io_in_1_bits_tag    (io_in_1_bits_tag),
+    .io_in_1_bits_set    (io_in_1_bits_set),
+    .io_in_1_bits_opcode (io_in_1_bits_opcode),
+    .io_in_1_bits_param  (io_in_1_bits_param),
+    .io_in_1_bits_alias  (io_in_1_bits_alias),
+    .io_out_ready        (io_out_ready & finalSelLow),
+    .io_out_valid        (_lowArb_io_out_valid),
+    .io_out_bits_tag     (_lowArb_io_out_bits_tag),
+    .io_out_bits_set     (_lowArb_io_out_bits_set),
+    .io_out_bits_opcode  (_lowArb_io_out_bits_opcode),
+    .io_out_bits_param   (_lowArb_io_out_bits_param),
+    .io_out_bits_alias   (_lowArb_io_out_bits_alias)
+  );
+  FastArbiter_18 highArb (
+    .clock               (clock),
+    .reset               (reset),
+    .io_in_0_ready       (io_in_2_ready),
+    .io_in_0_valid       (io_in_2_valid),
+    .io_in_0_bits_tag    (io_in_2_bits_tag),
+    .io_in_0_bits_set    (io_in_2_bits_set),
+    .io_in_0_bits_opcode (io_in_2_bits_opcode),
+    .io_in_0_bits_param  (io_in_2_bits_param),
+    .io_in_0_bits_alias  (io_in_2_bits_alias),
+    .io_in_1_ready       (io_in_3_ready),
+    .io_in_1_valid       (io_in_3_valid),
+    .io_in_1_bits_tag    (io_in_3_bits_tag),
+    .io_in_1_bits_set    (io_in_3_bits_set),
+    .io_in_1_bits_opcode (io_in_3_bits_opcode),
+    .io_in_1_bits_param  (io_in_3_bits_param),
+    .io_in_1_bits_alias  (io_in_3_bits_alias),
+    .io_out_ready        (io_out_ready & ~finalSelLow),
+    .io_out_valid        (_highArb_io_out_valid),
+    .io_out_bits_tag     (_highArb_io_out_bits_tag),
+    .io_out_bits_set     (_highArb_io_out_bits_set),
+    .io_out_bits_opcode  (_highArb_io_out_bits_opcode),
+    .io_out_bits_param   (_highArb_io_out_bits_param),
+    .io_out_bits_alias   (_highArb_io_out_bits_alias)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_tag =
+    finalSelLow ? _lowArb_io_out_bits_tag : _highArb_io_out_bits_tag;
+  assign io_out_bits_set =
+    finalSelLow ? _lowArb_io_out_bits_set : _highArb_io_out_bits_set;
+  assign io_out_bits_opcode =
+    finalSelLow ? _lowArb_io_out_bits_opcode : _highArb_io_out_bits_opcode;
+  assign io_out_bits_param =
+    finalSelLow ? _lowArb_io_out_bits_param : _highArb_io_out_bits_param;
+  assign io_out_bits_alias =
+    finalSelLow ? _lowArb_io_out_bits_alias : _highArb_io_out_bits_alias;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_9.sv b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_9.sv
new file mode 100644
index 0000000000..3100939c75
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/TwoLevelRRArbiter_9.sv
@@ -0,0 +1,326 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module TwoLevelRRArbiter_9(
+  input         clock,
+  input         reset,
+  output        io_in_0_ready,
+  input         io_in_0_valid,
+  input  [33:0] io_in_0_bits_tag,
+  input  [7:0]  io_in_0_bits_set,
+  input  [1:0]  io_in_0_bits_param,
+  input         io_in_0_bits_alias,
+  output        io_in_1_ready,
+  input         io_in_1_valid,
+  input  [33:0] io_in_1_bits_tag,
+  input  [7:0]  io_in_1_bits_set,
+  input  [1:0]  io_in_1_bits_param,
+  input         io_in_1_bits_alias,
+  output        io_in_2_ready,
+  input         io_in_2_valid,
+  input  [33:0] io_in_2_bits_tag,
+  input  [7:0]  io_in_2_bits_set,
+  input  [1:0]  io_in_2_bits_param,
+  input         io_in_2_bits_alias,
+  output        io_in_3_ready,
+  input         io_in_3_valid,
+  input  [33:0] io_in_3_bits_tag,
+  input  [7:0]  io_in_3_bits_set,
+  input  [1:0]  io_in_3_bits_param,
+  input         io_in_3_bits_alias,
+  output        io_in_4_ready,
+  input         io_in_4_valid,
+  input  [33:0] io_in_4_bits_tag,
+  input  [7:0]  io_in_4_bits_set,
+  input  [1:0]  io_in_4_bits_param,
+  input         io_in_4_bits_alias,
+  output        io_in_5_ready,
+  input         io_in_5_valid,
+  input  [33:0] io_in_5_bits_tag,
+  input  [7:0]  io_in_5_bits_set,
+  input  [1:0]  io_in_5_bits_param,
+  input         io_in_5_bits_alias,
+  output        io_in_6_ready,
+  input         io_in_6_valid,
+  input  [33:0] io_in_6_bits_tag,
+  input  [7:0]  io_in_6_bits_set,
+  input  [1:0]  io_in_6_bits_param,
+  input         io_in_6_bits_alias,
+  output        io_in_7_ready,
+  input         io_in_7_valid,
+  input  [33:0] io_in_7_bits_tag,
+  input  [7:0]  io_in_7_bits_set,
+  input  [1:0]  io_in_7_bits_param,
+  input         io_in_7_bits_alias,
+  output        io_in_8_ready,
+  input         io_in_8_valid,
+  input  [33:0] io_in_8_bits_tag,
+  input  [7:0]  io_in_8_bits_set,
+  input  [1:0]  io_in_8_bits_param,
+  input         io_in_8_bits_alias,
+  output        io_in_9_ready,
+  input         io_in_9_valid,
+  input  [33:0] io_in_9_bits_tag,
+  input  [7:0]  io_in_9_bits_set,
+  input  [1:0]  io_in_9_bits_param,
+  input         io_in_9_bits_alias,
+  output        io_in_10_ready,
+  input         io_in_10_valid,
+  input  [33:0] io_in_10_bits_tag,
+  input  [7:0]  io_in_10_bits_set,
+  input  [1:0]  io_in_10_bits_param,
+  input         io_in_10_bits_alias,
+  output        io_in_11_ready,
+  input         io_in_11_valid,
+  input  [33:0] io_in_11_bits_tag,
+  input  [7:0]  io_in_11_bits_set,
+  input  [1:0]  io_in_11_bits_param,
+  input         io_in_11_bits_alias,
+  output        io_in_12_ready,
+  input         io_in_12_valid,
+  input  [33:0] io_in_12_bits_tag,
+  input  [7:0]  io_in_12_bits_set,
+  input  [1:0]  io_in_12_bits_param,
+  input         io_in_12_bits_alias,
+  output        io_in_13_ready,
+  input         io_in_13_valid,
+  input  [33:0] io_in_13_bits_tag,
+  input  [7:0]  io_in_13_bits_set,
+  input  [1:0]  io_in_13_bits_param,
+  input         io_in_13_bits_alias,
+  output        io_in_14_ready,
+  input         io_in_14_valid,
+  input  [33:0] io_in_14_bits_tag,
+  input  [7:0]  io_in_14_bits_set,
+  input  [1:0]  io_in_14_bits_param,
+  input         io_in_14_bits_alias,
+  output        io_in_15_ready,
+  input         io_in_15_valid,
+  input  [33:0] io_in_15_bits_tag,
+  input  [7:0]  io_in_15_bits_set,
+  input  [1:0]  io_in_15_bits_param,
+  input         io_in_15_bits_alias,
+  input         io_out_ready,
+  output        io_out_valid,
+  output [33:0] io_out_bits_tag,
+  output [7:0]  io_out_bits_set,
+  output [2:0]  io_out_bits_opcode,
+  output [1:0]  io_out_bits_param,
+  output        io_out_bits_alias
+);
+
+  wire        _highArb_io_out_valid;
+  wire [33:0] _highArb_io_out_bits_tag;
+  wire [7:0]  _highArb_io_out_bits_set;
+  wire [2:0]  _highArb_io_out_bits_opcode;
+  wire [1:0]  _highArb_io_out_bits_param;
+  wire        _highArb_io_out_bits_alias;
+  wire        _lowArb_io_out_valid;
+  wire [33:0] _lowArb_io_out_bits_tag;
+  wire [7:0]  _lowArb_io_out_bits_set;
+  wire [2:0]  _lowArb_io_out_bits_opcode;
+  wire [1:0]  _lowArb_io_out_bits_param;
+  wire        _lowArb_io_out_bits_alias;
+  reg         selLow;
+  wire        finalSelLow =
+    _lowArb_io_out_valid & _highArb_io_out_valid & selLow | _lowArb_io_out_valid
+    & ~_highArb_io_out_valid;
+  wire        io_out_valid_0 = _lowArb_io_out_valid | _highArb_io_out_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      selLow <= 1'h0;
+    else if (io_out_ready & io_out_valid_0)
+      selLow <= finalSelLow ? ~_highArb_io_out_valid : _lowArb_io_out_valid;
+  end // always @(posedge, posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:0];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        _RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
+        selLow = _RANDOM[/*Zero width*/ 1'b0][0];
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        selLow = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  FastArbiter_20 lowArb (
+    .clock              (clock),
+    .reset              (reset),
+    .io_in_0_ready      (io_in_0_ready),
+    .io_in_0_valid      (io_in_0_valid),
+    .io_in_0_bits_tag   (io_in_0_bits_tag),
+    .io_in_0_bits_set   (io_in_0_bits_set),
+    .io_in_0_bits_param (io_in_0_bits_param),
+    .io_in_0_bits_alias (io_in_0_bits_alias),
+    .io_in_1_ready      (io_in_1_ready),
+    .io_in_1_valid      (io_in_1_valid),
+    .io_in_1_bits_tag   (io_in_1_bits_tag),
+    .io_in_1_bits_set   (io_in_1_bits_set),
+    .io_in_1_bits_param (io_in_1_bits_param),
+    .io_in_1_bits_alias (io_in_1_bits_alias),
+    .io_in_2_ready      (io_in_2_ready),
+    .io_in_2_valid      (io_in_2_valid),
+    .io_in_2_bits_tag   (io_in_2_bits_tag),
+    .io_in_2_bits_set   (io_in_2_bits_set),
+    .io_in_2_bits_param (io_in_2_bits_param),
+    .io_in_2_bits_alias (io_in_2_bits_alias),
+    .io_in_3_ready      (io_in_3_ready),
+    .io_in_3_valid      (io_in_3_valid),
+    .io_in_3_bits_tag   (io_in_3_bits_tag),
+    .io_in_3_bits_set   (io_in_3_bits_set),
+    .io_in_3_bits_param (io_in_3_bits_param),
+    .io_in_3_bits_alias (io_in_3_bits_alias),
+    .io_in_4_ready      (io_in_4_ready),
+    .io_in_4_valid      (io_in_4_valid),
+    .io_in_4_bits_tag   (io_in_4_bits_tag),
+    .io_in_4_bits_set   (io_in_4_bits_set),
+    .io_in_4_bits_param (io_in_4_bits_param),
+    .io_in_4_bits_alias (io_in_4_bits_alias),
+    .io_in_5_ready      (io_in_5_ready),
+    .io_in_5_valid      (io_in_5_valid),
+    .io_in_5_bits_tag   (io_in_5_bits_tag),
+    .io_in_5_bits_set   (io_in_5_bits_set),
+    .io_in_5_bits_param (io_in_5_bits_param),
+    .io_in_5_bits_alias (io_in_5_bits_alias),
+    .io_in_6_ready      (io_in_6_ready),
+    .io_in_6_valid      (io_in_6_valid),
+    .io_in_6_bits_tag   (io_in_6_bits_tag),
+    .io_in_6_bits_set   (io_in_6_bits_set),
+    .io_in_6_bits_param (io_in_6_bits_param),
+    .io_in_6_bits_alias (io_in_6_bits_alias),
+    .io_in_7_ready      (io_in_7_ready),
+    .io_in_7_valid      (io_in_7_valid),
+    .io_in_7_bits_tag   (io_in_7_bits_tag),
+    .io_in_7_bits_set   (io_in_7_bits_set),
+    .io_in_7_bits_param (io_in_7_bits_param),
+    .io_in_7_bits_alias (io_in_7_bits_alias),
+    .io_out_ready       (io_out_ready & finalSelLow),
+    .io_out_valid       (_lowArb_io_out_valid),
+    .io_out_bits_tag    (_lowArb_io_out_bits_tag),
+    .io_out_bits_set    (_lowArb_io_out_bits_set),
+    .io_out_bits_opcode (_lowArb_io_out_bits_opcode),
+    .io_out_bits_param  (_lowArb_io_out_bits_param),
+    .io_out_bits_alias  (_lowArb_io_out_bits_alias)
+  );
+  FastArbiter_20 highArb (
+    .clock              (clock),
+    .reset              (reset),
+    .io_in_0_ready      (io_in_8_ready),
+    .io_in_0_valid      (io_in_8_valid),
+    .io_in_0_bits_tag   (io_in_8_bits_tag),
+    .io_in_0_bits_set   (io_in_8_bits_set),
+    .io_in_0_bits_param (io_in_8_bits_param),
+    .io_in_0_bits_alias (io_in_8_bits_alias),
+    .io_in_1_ready      (io_in_9_ready),
+    .io_in_1_valid      (io_in_9_valid),
+    .io_in_1_bits_tag   (io_in_9_bits_tag),
+    .io_in_1_bits_set   (io_in_9_bits_set),
+    .io_in_1_bits_param (io_in_9_bits_param),
+    .io_in_1_bits_alias (io_in_9_bits_alias),
+    .io_in_2_ready      (io_in_10_ready),
+    .io_in_2_valid      (io_in_10_valid),
+    .io_in_2_bits_tag   (io_in_10_bits_tag),
+    .io_in_2_bits_set   (io_in_10_bits_set),
+    .io_in_2_bits_param (io_in_10_bits_param),
+    .io_in_2_bits_alias (io_in_10_bits_alias),
+    .io_in_3_ready      (io_in_11_ready),
+    .io_in_3_valid      (io_in_11_valid),
+    .io_in_3_bits_tag   (io_in_11_bits_tag),
+    .io_in_3_bits_set   (io_in_11_bits_set),
+    .io_in_3_bits_param (io_in_11_bits_param),
+    .io_in_3_bits_alias (io_in_11_bits_alias),
+    .io_in_4_ready      (io_in_12_ready),
+    .io_in_4_valid      (io_in_12_valid),
+    .io_in_4_bits_tag   (io_in_12_bits_tag),
+    .io_in_4_bits_set   (io_in_12_bits_set),
+    .io_in_4_bits_param (io_in_12_bits_param),
+    .io_in_4_bits_alias (io_in_12_bits_alias),
+    .io_in_5_ready      (io_in_13_ready),
+    .io_in_5_valid      (io_in_13_valid),
+    .io_in_5_bits_tag   (io_in_13_bits_tag),
+    .io_in_5_bits_set   (io_in_13_bits_set),
+    .io_in_5_bits_param (io_in_13_bits_param),
+    .io_in_5_bits_alias (io_in_13_bits_alias),
+    .io_in_6_ready      (io_in_14_ready),
+    .io_in_6_valid      (io_in_14_valid),
+    .io_in_6_bits_tag   (io_in_14_bits_tag),
+    .io_in_6_bits_set   (io_in_14_bits_set),
+    .io_in_6_bits_param (io_in_14_bits_param),
+    .io_in_6_bits_alias (io_in_14_bits_alias),
+    .io_in_7_ready      (io_in_15_ready),
+    .io_in_7_valid      (io_in_15_valid),
+    .io_in_7_bits_tag   (io_in_15_bits_tag),
+    .io_in_7_bits_set   (io_in_15_bits_set),
+    .io_in_7_bits_param (io_in_15_bits_param),
+    .io_in_7_bits_alias (io_in_15_bits_alias),
+    .io_out_ready       (io_out_ready & ~finalSelLow),
+    .io_out_valid       (_highArb_io_out_valid),
+    .io_out_bits_tag    (_highArb_io_out_bits_tag),
+    .io_out_bits_set    (_highArb_io_out_bits_set),
+    .io_out_bits_opcode (_highArb_io_out_bits_opcode),
+    .io_out_bits_param  (_highArb_io_out_bits_param),
+    .io_out_bits_alias  (_highArb_io_out_bits_alias)
+  );
+  assign io_out_valid = io_out_valid_0;
+  assign io_out_bits_tag =
+    finalSelLow ? _lowArb_io_out_bits_tag : _highArb_io_out_bits_tag;
+  assign io_out_bits_set =
+    finalSelLow ? _lowArb_io_out_bits_set : _highArb_io_out_bits_set;
+  assign io_out_bits_opcode =
+    finalSelLow ? _lowArb_io_out_bits_opcode : _highArb_io_out_bits_opcode;
+  assign io_out_bits_param =
+    finalSelLow ? _lowArb_io_out_bits_param : _highArb_io_out_bits_param;
+  assign io_out_bits_alias =
+    finalSelLow ? _lowArb_io_out_bits_alias : _highArb_io_out_bits_alias;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/VBestOffsetPrefetch.sv b/flow/designs/src/xiangshan_coupledl2/deps/VBestOffsetPrefetch.sv
new file mode 100644
index 0000000000..2fcf6cb989
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/VBestOffsetPrefetch.sv
@@ -0,0 +1,244 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+module VBestOffsetPrefetch(
+  input         clock,
+  input         reset,
+  input         io_enable,
+  input  [9:0]  io_pfCtrlOfDelayLatency,
+  input         io_train_valid,
+  input         io_train_bits_needT,
+  input  [6:0]  io_train_bits_source,
+  input  [43:0] io_train_bits_vaddr,
+  output        io_tlb_req_req_valid,
+  output [49:0] io_tlb_req_req_bits_vaddr,
+  input         io_tlb_req_resp_valid,
+  input  [47:0] io_tlb_req_resp_bits_paddr_0,
+  input  [1:0]  io_tlb_req_resp_bits_pbmt,
+  input         io_tlb_req_resp_bits_miss,
+  input         io_tlb_req_resp_bits_excp_0_gpf_ld,
+  input         io_tlb_req_resp_bits_excp_0_pf_ld,
+  input         io_tlb_req_resp_bits_excp_0_af_ld,
+  input         io_tlb_req_pmp_resp_ld,
+  input         io_tlb_req_pmp_resp_mmio,
+  input         io_req_ready,
+  output        io_req_valid,
+  output [33:0] io_req_bits_tag,
+  output [7:0]  io_req_bits_set,
+  output [43:0] io_req_bits_vaddr,
+  output        io_req_bits_needT,
+  output [6:0]  io_req_bits_source,
+  input  [8:0]  boreChildrenBd_bore_addr,
+  input  [8:0]  boreChildrenBd_bore_addr_rd,
+  input  [12:0] boreChildrenBd_bore_wdata,
+  input         boreChildrenBd_bore_wmask,
+  input         boreChildrenBd_bore_re,
+  input         boreChildrenBd_bore_we,
+  output [12:0] boreChildrenBd_bore_rdata,
+  input         boreChildrenBd_bore_ack,
+  input         boreChildrenBd_bore_selectedOH,
+  input         boreChildrenBd_bore_array,
+  input         sigFromSrams_bore_ram_hold,
+  input         sigFromSrams_bore_ram_bypass,
+  input         sigFromSrams_bore_ram_bp_clken,
+  input         sigFromSrams_bore_ram_aux_clk,
+  input         sigFromSrams_bore_ram_aux_ckbp,
+  input         sigFromSrams_bore_ram_mcp_hold,
+  input         sigFromSrams_bore_cgen
+);
+
+  wire        io_req_valid_0;
+  wire        _reqFilter_io_out_req_valid;
+  wire        _scoreTable_io_req_ready;
+  wire [9:0]  _scoreTable_io_prefetchOffset;
+  wire        _scoreTable_io_prefetchDisable;
+  wire        _scoreTable_io_test_req_valid;
+  wire [49:0] _scoreTable_io_test_req_bits_addr;
+  wire [9:0]  _scoreTable_io_test_req_bits_testOffset;
+  wire [6:0]  _scoreTable_io_test_req_bits_ptr;
+  wire        _rrTable_io_w_ready;
+  wire        _rrTable_io_r_resp_valid;
+  wire [6:0]  _rrTable_io_r_resp_bits_ptr;
+  wire        _rrTable_io_r_resp_bits_hit;
+  wire        _delayQueue_io_out_valid;
+  wire [49:0] _delayQueue_io_out_bits;
+  wire        _s0_fire_T = _scoreTable_io_req_ready & io_train_valid;
+  reg         s1_req_valid;
+  reg         s1_needT;
+  reg  [6:0]  s1_source;
+  reg  [49:0] s1_newFullAddr;
+  reg  [43:0] s1_reqVaddr;
+  assign io_req_valid_0 = io_enable & _reqFilter_io_out_req_valid;
+  always @(posedge clock or posedge reset) begin
+    if (reset)
+      s1_req_valid <= 1'h0;
+    else
+      s1_req_valid <=
+        _s0_fire_T | ~((io_req_ready | ~io_req_valid_0) & s1_req_valid) & s1_req_valid;
+  end // always @(posedge, posedge)
+  always @(posedge clock) begin
+    if (_s0_fire_T) begin
+      s1_needT <= io_train_bits_needT;
+      s1_source <= io_train_bits_source;
+      s1_newFullAddr <=
+        50'({io_train_bits_vaddr, 6'h0}
+            + {{34{_scoreTable_io_prefetchOffset[9]}},
+               _scoreTable_io_prefetchOffset,
+               6'h0});
+      s1_reqVaddr <= io_train_bits_vaddr;
+    end
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_REG_
+    `ifdef FIRRTL_BEFORE_INITIAL
+      `FIRRTL_BEFORE_INITIAL
+    `endif // FIRRTL_BEFORE_INITIAL
+    logic [31:0] _RANDOM[0:3];
+    initial begin
+      `ifdef INIT_RANDOM_PROLOG_
+        `INIT_RANDOM_PROLOG_
+      `endif // INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_REG_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
+          _RANDOM[i[1:0]] = `RANDOM;
+        end
+        s1_req_valid = _RANDOM[2'h0][0];
+        s1_needT = _RANDOM[2'h0][1];
+        s1_source = _RANDOM[2'h0][8:2];
+        s1_newFullAddr = {_RANDOM[2'h0][31:9], _RANDOM[2'h1][26:0]};
+        s1_reqVaddr = {_RANDOM[2'h1][31:27], _RANDOM[2'h2], _RANDOM[2'h3][6:0]};
+      `endif // RANDOMIZE_REG_INIT
+      if (reset)
+        s1_req_valid = 1'h0;
+    end // initial
+    `ifdef FIRRTL_AFTER_INITIAL
+      `FIRRTL_AFTER_INITIAL
+    `endif // FIRRTL_AFTER_INITIAL
+  `endif // ENABLE_INITIAL_REG_
+  DelayQueue_1 delayQueue (
+    .clock                   (clock),
+    .reset                   (reset),
+    .io_pfCtrlOfDelayLatency (io_pfCtrlOfDelayLatency),
+    .io_in_valid             (io_train_valid),
+    .io_in_bits              (io_train_bits_vaddr),
+    .io_out_ready            (_rrTable_io_w_ready),
+    .io_out_valid            (_delayQueue_io_out_valid),
+    .io_out_bits             (_delayQueue_io_out_bits)
+  );
+  RecentRequestTable_1 rrTable (
+    .clock                          (clock),
+    .reset                          (reset),
+    .io_w_ready                     (_rrTable_io_w_ready),
+    .io_w_valid                     (_delayQueue_io_out_valid),
+    .io_w_bits                      (_delayQueue_io_out_bits),
+    .io_r_req_valid                 (_scoreTable_io_test_req_valid),
+    .io_r_req_bits_addr             (_scoreTable_io_test_req_bits_addr),
+    .io_r_req_bits_testOffset       (_scoreTable_io_test_req_bits_testOffset),
+    .io_r_req_bits_ptr              (_scoreTable_io_test_req_bits_ptr),
+    .io_r_resp_valid                (_rrTable_io_r_resp_valid),
+    .io_r_resp_bits_ptr             (_rrTable_io_r_resp_bits_ptr),
+    .io_r_resp_bits_hit             (_rrTable_io_r_resp_bits_hit),
+    .boreChildrenBd_bore_addr       (boreChildrenBd_bore_addr),
+    .boreChildrenBd_bore_addr_rd    (boreChildrenBd_bore_addr_rd),
+    .boreChildrenBd_bore_wdata      (boreChildrenBd_bore_wdata),
+    .boreChildrenBd_bore_wmask      (boreChildrenBd_bore_wmask),
+    .boreChildrenBd_bore_re         (boreChildrenBd_bore_re),
+    .boreChildrenBd_bore_we         (boreChildrenBd_bore_we),
+    .boreChildrenBd_bore_rdata      (boreChildrenBd_bore_rdata),
+    .boreChildrenBd_bore_ack        (boreChildrenBd_bore_ack),
+    .boreChildrenBd_bore_selectedOH (boreChildrenBd_bore_selectedOH),
+    .boreChildrenBd_bore_array      (boreChildrenBd_bore_array),
+    .sigFromSrams_bore_ram_hold     (sigFromSrams_bore_ram_hold),
+    .sigFromSrams_bore_ram_bypass   (sigFromSrams_bore_ram_bypass),
+    .sigFromSrams_bore_ram_bp_clken (sigFromSrams_bore_ram_bp_clken),
+    .sigFromSrams_bore_ram_aux_clk  (sigFromSrams_bore_ram_aux_clk),
+    .sigFromSrams_bore_ram_aux_ckbp (sigFromSrams_bore_ram_aux_ckbp),
+    .sigFromSrams_bore_ram_mcp_hold (sigFromSrams_bore_ram_mcp_hold),
+    .sigFromSrams_bore_cgen         (sigFromSrams_bore_cgen)
+  );
+  OffsetScoreTable_1 scoreTable (
+    .clock                       (clock),
+    .reset                       (reset),
+    .io_req_ready                (_scoreTable_io_req_ready),
+    .io_req_valid                (io_train_valid),
+    .io_req_bits                 ({io_train_bits_vaddr, 6'h0}),
+    .io_prefetchOffset           (_scoreTable_io_prefetchOffset),
+    .io_prefetchDisable          (_scoreTable_io_prefetchDisable),
+    .io_test_req_valid           (_scoreTable_io_test_req_valid),
+    .io_test_req_bits_addr       (_scoreTable_io_test_req_bits_addr),
+    .io_test_req_bits_testOffset (_scoreTable_io_test_req_bits_testOffset),
+    .io_test_req_bits_ptr        (_scoreTable_io_test_req_bits_ptr),
+    .io_test_resp_valid          (_rrTable_io_r_resp_valid),
+    .io_test_resp_bits_ptr       (_rrTable_io_r_resp_bits_ptr),
+    .io_test_resp_bits_hit       (_rrTable_io_r_resp_bits_hit)
+  );
+  PrefetchReqBuffer reqFilter (
+    .clock                              (clock),
+    .reset                              (reset),
+    .io_in_req_valid                    (~_scoreTable_io_prefetchDisable & s1_req_valid),
+    .io_in_req_bits_full_vaddr          (s1_newFullAddr),
+    .io_in_req_bits_base_vaddr          (s1_reqVaddr),
+    .io_in_req_bits_needT               (s1_needT),
+    .io_in_req_bits_source              (s1_source),
+    .io_tlb_req_req_valid               (io_tlb_req_req_valid),
+    .io_tlb_req_req_bits_vaddr          (io_tlb_req_req_bits_vaddr),
+    .io_tlb_req_resp_valid              (io_tlb_req_resp_valid),
+    .io_tlb_req_resp_bits_paddr_0       (io_tlb_req_resp_bits_paddr_0),
+    .io_tlb_req_resp_bits_pbmt          (io_tlb_req_resp_bits_pbmt),
+    .io_tlb_req_resp_bits_miss          (io_tlb_req_resp_bits_miss),
+    .io_tlb_req_resp_bits_excp_0_gpf_ld (io_tlb_req_resp_bits_excp_0_gpf_ld),
+    .io_tlb_req_resp_bits_excp_0_pf_ld  (io_tlb_req_resp_bits_excp_0_pf_ld),
+    .io_tlb_req_resp_bits_excp_0_af_ld  (io_tlb_req_resp_bits_excp_0_af_ld),
+    .io_tlb_req_pmp_resp_ld             (io_tlb_req_pmp_resp_ld),
+    .io_tlb_req_pmp_resp_mmio           (io_tlb_req_pmp_resp_mmio),
+    .io_out_req_ready                   (io_req_ready),
+    .io_out_req_valid                   (_reqFilter_io_out_req_valid),
+    .io_out_req_bits_tag                (io_req_bits_tag),
+    .io_out_req_bits_set                (io_req_bits_set),
+    .io_out_req_bits_vaddr              (io_req_bits_vaddr),
+    .io_out_req_bits_needT              (io_req_bits_needT),
+    .io_out_req_bits_source             (io_req_bits_source)
+  );
+  assign io_req_valid = io_req_valid_0;
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/array_2048x137_wrap.sv b/flow/designs/src/xiangshan_coupledl2/deps/array_2048x137_wrap.sv
new file mode 100644
index 0000000000..be7da8bc19
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/array_2048x137_wrap.sv
@@ -0,0 +1,86 @@
+// banked wrapper (bitline-limited): array_2048x137 = 8 x array_2048x137_bk
+module array_2048x137 (
+  input [10:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [136:0] RW0_wdata,
+  output [136:0] RW0_rdata
+);
+  wire [2:0] RW0_bsel = RW0_addr[10:8];
+  reg [2:0] RW0_bsel_q;
+  always @(posedge RW0_clk) RW0_bsel_q <= RW0_bsel;
+  wire [136:0] RW0_rd0;
+  wire [136:0] RW0_rd1;
+  wire [136:0] RW0_rd2;
+  wire [136:0] RW0_rd3;
+  wire [136:0] RW0_rd4;
+  wire [136:0] RW0_rd5;
+  wire [136:0] RW0_rd6;
+  wire [136:0] RW0_rd7;
+  assign RW0_rdata = (RW0_bsel_q == 3'd0) ? RW0_rd0 : (RW0_bsel_q == 3'd1) ? RW0_rd1 : (RW0_bsel_q == 3'd2) ? RW0_rd2 : (RW0_bsel_q == 3'd3) ? RW0_rd3 : (RW0_bsel_q == 3'd4) ? RW0_rd4 : (RW0_bsel_q == 3'd5) ? RW0_rd5 : (RW0_bsel_q == 3'd6) ? RW0_rd6 : RW0_rd7;
+  array_2048x137_bk bank0 (
+    .RW0_addr(RW0_addr[7:0]),
+    .RW0_en(RW0_en & (RW0_bsel == 3'd0)),
+    .RW0_clk(RW0_clk),
+    .RW0_wmode(RW0_wmode),
+    .RW0_wdata(RW0_wdata),
+    .RW0_rdata(RW0_rd0)
+  );
+  array_2048x137_bk bank1 (
+    .RW0_addr(RW0_addr[7:0]),
+    .RW0_en(RW0_en & (RW0_bsel == 3'd1)),
+    .RW0_clk(RW0_clk),
+    .RW0_wmode(RW0_wmode),
+    .RW0_wdata(RW0_wdata),
+    .RW0_rdata(RW0_rd1)
+  );
+  array_2048x137_bk bank2 (
+    .RW0_addr(RW0_addr[7:0]),
+    .RW0_en(RW0_en & (RW0_bsel == 3'd2)),
+    .RW0_clk(RW0_clk),
+    .RW0_wmode(RW0_wmode),
+    .RW0_wdata(RW0_wdata),
+    .RW0_rdata(RW0_rd2)
+  );
+  array_2048x137_bk bank3 (
+    .RW0_addr(RW0_addr[7:0]),
+    .RW0_en(RW0_en & (RW0_bsel == 3'd3)),
+    .RW0_clk(RW0_clk),
+    .RW0_wmode(RW0_wmode),
+    .RW0_wdata(RW0_wdata),
+    .RW0_rdata(RW0_rd3)
+  );
+  array_2048x137_bk bank4 (
+    .RW0_addr(RW0_addr[7:0]),
+    .RW0_en(RW0_en & (RW0_bsel == 3'd4)),
+    .RW0_clk(RW0_clk),
+    .RW0_wmode(RW0_wmode),
+    .RW0_wdata(RW0_wdata),
+    .RW0_rdata(RW0_rd4)
+  );
+  array_2048x137_bk bank5 (
+    .RW0_addr(RW0_addr[7:0]),
+    .RW0_en(RW0_en & (RW0_bsel == 3'd5)),
+    .RW0_clk(RW0_clk),
+    .RW0_wmode(RW0_wmode),
+    .RW0_wdata(RW0_wdata),
+    .RW0_rdata(RW0_rd5)
+  );
+  array_2048x137_bk bank6 (
+    .RW0_addr(RW0_addr[7:0]),
+    .RW0_en(RW0_en & (RW0_bsel == 3'd6)),
+    .RW0_clk(RW0_clk),
+    .RW0_wmode(RW0_wmode),
+    .RW0_wdata(RW0_wdata),
+    .RW0_rdata(RW0_rd6)
+  );
+  array_2048x137_bk bank7 (
+    .RW0_addr(RW0_addr[7:0]),
+    .RW0_en(RW0_en & (RW0_bsel == 3'd7)),
+    .RW0_clk(RW0_clk),
+    .RW0_wmode(RW0_wmode),
+    .RW0_wdata(RW0_wdata),
+    .RW0_rdata(RW0_rd7)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_16x148.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x148.sv
new file mode 100644
index 0000000000..f38729bcf7
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x148.sv
@@ -0,0 +1,91 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_16x148(
+  input  [3:0]   R0_addr,
+  input          R0_en,
+  input          R0_clk,
+  output [147:0] R0_data,
+  input  [3:0]   W0_addr,
+  input          W0_en,
+  input          W0_clk,
+  input  [147:0] W0_data
+);
+
+  reg [147:0] Memory[0:15];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [159:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
+          for (logic [7:0] j = 8'h0; j < 8'hA0; j += 8'h20) begin
+            _RANDOM_MEM[j +: 32] = `RANDOM;
+          end
+          Memory[i[3:0]] = _RANDOM_MEM[147:0];
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_16x25.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x25.sv
new file mode 100644
index 0000000000..dce84bff88
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x25.sv
@@ -0,0 +1,89 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_16x25(
+  input  [3:0]  R0_addr,
+  input         R0_en,
+  input         R0_clk,
+  output [24:0] R0_data,
+  input  [3:0]  W0_addr,
+  input         W0_en,
+  input         W0_clk,
+  input  [24:0] W0_data
+);
+
+  reg [24:0] Memory[0:15];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [31:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
+          _RANDOM_MEM = `RANDOM;
+          Memory[i[3:0]] = _RANDOM_MEM[24:0];
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_16x73.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x73.sv
new file mode 100644
index 0000000000..1a1ff3c0d8
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x73.sv
@@ -0,0 +1,91 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_16x73(
+  input  [3:0]  R0_addr,
+  input         R0_en,
+  input         R0_clk,
+  output [72:0] R0_data,
+  input  [3:0]  W0_addr,
+  input         W0_en,
+  input         W0_clk,
+  input  [72:0] W0_data
+);
+
+  reg [72:0] Memory[0:15];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [95:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
+          for (logic [6:0] j = 7'h0; j < 7'h60; j += 7'h20) begin
+            _RANDOM_MEM[j +: 32] = `RANDOM;
+          end
+          Memory[i[3:0]] = _RANDOM_MEM[72:0];
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_16x78.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x78.sv
new file mode 100644
index 0000000000..2a9f590baf
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x78.sv
@@ -0,0 +1,91 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_16x78(
+  input  [3:0]  R0_addr,
+  input         R0_en,
+  input         R0_clk,
+  output [77:0] R0_data,
+  input  [3:0]  W0_addr,
+  input         W0_en,
+  input         W0_clk,
+  input  [77:0] W0_data
+);
+
+  reg [77:0] Memory[0:15];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [95:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
+          for (logic [6:0] j = 7'h0; j < 7'h60; j += 7'h20) begin
+            _RANDOM_MEM[j +: 32] = `RANDOM;
+          end
+          Memory[i[3:0]] = _RANDOM_MEM[77:0];
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_16x9.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x9.sv
new file mode 100644
index 0000000000..40b1d0b99d
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_16x9.sv
@@ -0,0 +1,89 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_16x9(
+  input  [3:0] R0_addr,
+  input        R0_en,
+  input        R0_clk,
+  output [8:0] R0_data,
+  input  [3:0] W0_addr,
+  input        W0_en,
+  input        W0_clk,
+  input  [8:0] W0_data
+);
+
+  reg [8:0] Memory[0:15];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [31:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
+          _RANDOM_MEM = `RANDOM;
+          Memory[i[3:0]] = _RANDOM_MEM[8:0];
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_2x15.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_2x15.sv
new file mode 100644
index 0000000000..5512c9c91e
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_2x15.sv
@@ -0,0 +1,89 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_2x15(
+  input         R0_addr,
+  input         R0_en,
+  input         R0_clk,
+  output [14:0] R0_data,
+  input         W0_addr,
+  input         W0_en,
+  input         W0_clk,
+  input  [14:0] W0_data
+);
+
+  reg [14:0] Memory[0:1];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [31:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
+          _RANDOM_MEM = `RANDOM;
+          Memory[i[0]] = _RANDOM_MEM[14:0];
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_2x98.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_2x98.sv
new file mode 100644
index 0000000000..fa9b3b14d2
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_2x98.sv
@@ -0,0 +1,91 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_2x98(
+  input         R0_addr,
+  input         R0_en,
+  input         R0_clk,
+  output [97:0] R0_data,
+  input         W0_addr,
+  input         W0_en,
+  input         W0_clk,
+  input  [97:0] W0_data
+);
+
+  reg [97:0] Memory[0:1];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [127:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
+          for (logic [7:0] j = 8'h0; j < 8'h80; j += 8'h20) begin
+            _RANDOM_MEM[j[6:0] +: 32] = `RANDOM;
+          end
+          Memory[i[0]] = _RANDOM_MEM[97:0];
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_30x15.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_30x15.sv
new file mode 100644
index 0000000000..b245970325
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_30x15.sv
@@ -0,0 +1,89 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_30x15(
+  input  [4:0]  R0_addr,
+  input         R0_en,
+  input         R0_clk,
+  output [14:0] R0_data,
+  input  [4:0]  W0_addr,
+  input         W0_en,
+  input         W0_clk,
+  input  [14:0] W0_data
+);
+
+  reg [14:0] Memory[0:29];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [31:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h1E; i += 5'h1) begin
+          _RANDOM_MEM = `RANDOM;
+          Memory[i] = _RANDOM_MEM[14:0];
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_4x115.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_4x115.sv
new file mode 100644
index 0000000000..64ca9f6aa8
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_4x115.sv
@@ -0,0 +1,91 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_4x115(
+  input  [1:0]   R0_addr,
+  input          R0_en,
+  input          R0_clk,
+  output [114:0] R0_data,
+  input  [1:0]   W0_addr,
+  input          W0_en,
+  input          W0_clk,
+  input  [114:0] W0_data
+);
+
+  reg [114:0] Memory[0:3];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [127:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
+          for (logic [7:0] j = 8'h0; j < 8'h80; j += 8'h20) begin
+            _RANDOM_MEM[j[6:0] +: 32] = `RANDOM;
+          end
+          Memory[i[1:0]] = _RANDOM_MEM[114:0];
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/ram_data_16x256.sv b/flow/designs/src/xiangshan_coupledl2/deps/ram_data_16x256.sv
new file mode 100644
index 0000000000..955250749f
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/ram_data_16x256.sv
@@ -0,0 +1,91 @@
+// Generated by CIRCT firtool-1.135.0
+
+// Include register initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_REG_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_REG_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_REG_
+    `define ENABLE_INITIAL_REG_
+  `endif // not def ENABLE_INITIAL_REG_
+`endif // not def SYNTHESIS
+
+
+// Include rmemory initializers in init blocks unless synthesis is set
+`ifndef RANDOMIZE
+  `ifdef RANDOMIZE_MEM_INIT
+    `define RANDOMIZE
+  `endif // RANDOMIZE_MEM_INIT
+`endif // not def RANDOMIZE
+`ifndef SYNTHESIS
+  `ifndef ENABLE_INITIAL_MEM_
+    `define ENABLE_INITIAL_MEM_
+  `endif // not def ENABLE_INITIAL_MEM_
+`endif // not def SYNTHESIS
+
+// Standard header to adapt well known macros for register randomization.
+
+// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
+`ifndef RANDOM
+  `define RANDOM $random
+`endif // not def RANDOM
+
+// Users can define INIT_RANDOM as general code that gets injected into the
+// initializer block for modules with registers.
+`ifndef INIT_RANDOM
+  `define INIT_RANDOM
+`endif // not def INIT_RANDOM
+
+// If using random initialization, you can also define RANDOMIZE_DELAY to
+// customize the delay used, otherwise 0.002 is used.
+`ifndef RANDOMIZE_DELAY
+  `define RANDOMIZE_DELAY 0.002
+`endif // not def RANDOMIZE_DELAY
+
+// Define INIT_RANDOM_PROLOG_ for use in our modules below.
+`ifndef INIT_RANDOM_PROLOG_
+  `ifdef RANDOMIZE
+    `ifdef VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM
+    `else  // VERILATOR
+      `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
+    `endif // VERILATOR
+  `else  // RANDOMIZE
+    `define INIT_RANDOM_PROLOG_
+  `endif // RANDOMIZE
+`endif // not def INIT_RANDOM_PROLOG_
+// VCS coverage exclude_file
+module ram_data_16x256(
+  input  [3:0]   R0_addr,
+  input          R0_en,
+  input          R0_clk,
+  output [255:0] R0_data,
+  input  [3:0]   W0_addr,
+  input          W0_en,
+  input          W0_clk,
+  input  [255:0] W0_data
+);
+
+  reg [255:0] Memory[0:15];
+  always @(posedge W0_clk) begin
+    if (W0_en)
+      Memory[W0_addr] <= W0_data;
+  end // always @(posedge)
+  `ifdef ENABLE_INITIAL_MEM_
+    reg [255:0] _RANDOM_MEM;
+    initial begin
+      `INIT_RANDOM_PROLOG_
+      `ifdef RANDOMIZE_MEM_INIT
+        for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
+          for (logic [8:0] j = 9'h0; j < 9'h100; j += 9'h20) begin
+            _RANDOM_MEM[j[7:0] +: 32] = `RANDOM;
+          end
+          Memory[i[3:0]] = _RANDOM_MEM;
+        end
+      `endif // RANDOMIZE_MEM_INIT
+    end // initial
+  `endif // ENABLE_INITIAL_MEM_
+  assign R0_data = Memory[R0_addr];
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p2048x137m137s1h1l2b_l2_dat.sv b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p2048x137m137s1h1l2b_l2_dat.sv
new file mode 100644
index 0000000000..b37602acb2
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p2048x137m137s1h1l2b_l2_dat.sv
@@ -0,0 +1,21 @@
+// Generated by CIRCT firtool-1.135.0
+module sram_array_1p2048x137m137s1h1l2b_l2_dat(
+  input          mbist_dft_ram_bypass,
+  input          mbist_dft_ram_bp_clken,
+  input          RW0_clk,
+  input  [10:0]  RW0_addr,
+  input          RW0_en,
+  input          RW0_wmode,
+  input  [136:0] RW0_wdata,
+  output [136:0] RW0_rdata
+);
+
+  array_2048x137 array_ext (
+    .RW0_addr  (RW0_addr),
+    .RW0_en    (RW0_en),
+    .RW0_clk   (RW0_clk),
+    .RW0_wmode (RW0_wmode),
+    .RW0_wdata (RW0_wdata),
+    .RW0_rdata (RW0_rdata)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x104m13s1h0l1b_l2_meta.sv b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x104m13s1h0l1b_l2_meta.sv
new file mode 100644
index 0000000000..0ea9a50dde
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x104m13s1h0l1b_l2_meta.sv
@@ -0,0 +1,47 @@
+// Generated by CIRCT firtool-1.135.0
+module sram_array_1p256x104m13s1h0l1b_l2_meta(
+  input          mbist_dft_ram_bypass,
+  input          mbist_dft_ram_bp_clken,
+  input          RW0_clk,
+  input  [7:0]   RW0_addr,
+  input          RW0_en,
+  input          RW0_wmode,
+  input  [7:0]   RW0_wmask,
+  input  [103:0] RW0_wdata,
+  output [103:0] RW0_rdata
+);
+
+  wire array_RW0_rdata_MPORT_wmask_7;
+  wire array_RW0_rdata_MPORT_wmask_6;
+  wire array_RW0_rdata_MPORT_wmask_5;
+  wire array_RW0_rdata_MPORT_wmask_4;
+  wire array_RW0_rdata_MPORT_wmask_3;
+  wire array_RW0_rdata_MPORT_wmask_2;
+  wire array_RW0_rdata_MPORT_wmask_1;
+  wire array_RW0_rdata_MPORT_wmask_0;
+  assign array_RW0_rdata_MPORT_wmask_0 = RW0_wmode & RW0_wmask[0];
+  assign array_RW0_rdata_MPORT_wmask_1 = RW0_wmode & RW0_wmask[1];
+  assign array_RW0_rdata_MPORT_wmask_2 = RW0_wmode & RW0_wmask[2];
+  assign array_RW0_rdata_MPORT_wmask_3 = RW0_wmode & RW0_wmask[3];
+  assign array_RW0_rdata_MPORT_wmask_4 = RW0_wmode & RW0_wmask[4];
+  assign array_RW0_rdata_MPORT_wmask_5 = RW0_wmode & RW0_wmask[5];
+  assign array_RW0_rdata_MPORT_wmask_6 = RW0_wmode & RW0_wmask[6];
+  assign array_RW0_rdata_MPORT_wmask_7 = RW0_wmode & RW0_wmask[7];
+  array_256x104 array_ext (
+    .RW0_addr  (RW0_addr),
+    .RW0_en    (RW0_en),
+    .RW0_clk   (RW0_clk),
+    .RW0_wmode (RW0_wmode & (|RW0_wmask)),
+    .RW0_wdata (RW0_wdata),
+    .RW0_rdata (RW0_rdata),
+    .RW0_wmask
+      ({array_RW0_rdata_MPORT_wmask_7,
+        array_RW0_rdata_MPORT_wmask_6,
+        array_RW0_rdata_MPORT_wmask_5,
+        array_RW0_rdata_MPORT_wmask_4,
+        array_RW0_rdata_MPORT_wmask_3,
+        array_RW0_rdata_MPORT_wmask_2,
+        array_RW0_rdata_MPORT_wmask_1,
+        array_RW0_rdata_MPORT_wmask_0})
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x13m13s1h0l1b_l2_pftch_rrt.sv b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x13m13s1h0l1b_l2_pftch_rrt.sv
new file mode 100644
index 0000000000..4e9e47824c
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x13m13s1h0l1b_l2_pftch_rrt.sv
@@ -0,0 +1,21 @@
+// Generated by CIRCT firtool-1.135.0
+module sram_array_1p256x13m13s1h0l1b_l2_pftch_rrt(
+  input         mbist_dft_ram_bypass,
+  input         mbist_dft_ram_bp_clken,
+  input         RW0_clk,
+  input  [7:0]  RW0_addr,
+  input         RW0_en,
+  input         RW0_wmode,
+  input  [12:0] RW0_wdata,
+  output [12:0] RW0_rdata
+);
+
+  array_256x13 array_ext (
+    .RW0_addr  (RW0_addr),
+    .RW0_en    (RW0_en),
+    .RW0_clk   (RW0_clk),
+    .RW0_wmode (RW0_wmode),
+    .RW0_wdata (RW0_wdata),
+    .RW0_rdata (RW0_rdata)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x164m41s1h0l1b_l2_tag.sv b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x164m41s1h0l1b_l2_tag.sv
new file mode 100644
index 0000000000..7fc2a4fbf9
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x164m41s1h0l1b_l2_tag.sv
@@ -0,0 +1,35 @@
+// Generated by CIRCT firtool-1.135.0
+module sram_array_1p256x164m41s1h0l1b_l2_tag(
+  input          mbist_dft_ram_bypass,
+  input          mbist_dft_ram_bp_clken,
+  input          RW0_clk,
+  input  [7:0]   RW0_addr,
+  input          RW0_en,
+  input          RW0_wmode,
+  input  [3:0]   RW0_wmask,
+  input  [163:0] RW0_wdata,
+  output [163:0] RW0_rdata
+);
+
+  wire array_RW0_rdata_MPORT_wmask_3;
+  wire array_RW0_rdata_MPORT_wmask_2;
+  wire array_RW0_rdata_MPORT_wmask_1;
+  wire array_RW0_rdata_MPORT_wmask_0;
+  assign array_RW0_rdata_MPORT_wmask_0 = RW0_wmode & RW0_wmask[0];
+  assign array_RW0_rdata_MPORT_wmask_1 = RW0_wmode & RW0_wmask[1];
+  assign array_RW0_rdata_MPORT_wmask_2 = RW0_wmode & RW0_wmask[2];
+  assign array_RW0_rdata_MPORT_wmask_3 = RW0_wmode & RW0_wmask[3];
+  array_256x164 array_ext (
+    .RW0_addr  (RW0_addr),
+    .RW0_en    (RW0_en),
+    .RW0_clk   (RW0_clk),
+    .RW0_wmode (RW0_wmode & (|RW0_wmask)),
+    .RW0_wdata (RW0_wdata),
+    .RW0_rdata (RW0_rdata),
+    .RW0_wmask
+      ({array_RW0_rdata_MPORT_wmask_3,
+        array_RW0_rdata_MPORT_wmask_2,
+        array_RW0_rdata_MPORT_wmask_1,
+        array_RW0_rdata_MPORT_wmask_0})
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x16m16s1h0l1b_l2_repl.sv b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x16m16s1h0l1b_l2_repl.sv
new file mode 100644
index 0000000000..51f0fd14f2
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x16m16s1h0l1b_l2_repl.sv
@@ -0,0 +1,21 @@
+// Generated by CIRCT firtool-1.135.0
+module sram_array_1p256x16m16s1h0l1b_l2_repl(
+  input         mbist_dft_ram_bypass,
+  input         mbist_dft_ram_bp_clken,
+  input         RW0_clk,
+  input  [7:0]  RW0_addr,
+  input         RW0_en,
+  input         RW0_wmode,
+  input  [15:0] RW0_wdata,
+  output [15:0] RW0_rdata
+);
+
+  array_256x16 array_ext (
+    .RW0_addr  (RW0_addr),
+    .RW0_en    (RW0_en),
+    .RW0_clk   (RW0_clk),
+    .RW0_wmode (RW0_wmode),
+    .RW0_wdata (RW0_wdata),
+    .RW0_rdata (RW0_rdata)
+  );
+endmodule
diff --git a/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x8m1s1h0l1b_l2_orgb.sv b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x8m1s1h0l1b_l2_orgb.sv
new file mode 100644
index 0000000000..3e5b281318
--- /dev/null
+++ b/flow/designs/src/xiangshan_coupledl2/deps/sram_array_1p256x8m1s1h0l1b_l2_orgb.sv
@@ -0,0 +1,47 @@
+// Generated by CIRCT firtool-1.135.0
+module sram_array_1p256x8m1s1h0l1b_l2_orgb(
+  input        mbist_dft_ram_bypass,
+  input        mbist_dft_ram_bp_clken,
+  input        RW0_clk,
+  input  [7:0] RW0_addr,
+  input        RW0_en,
+  input        RW0_wmode,
+  input  [7:0] RW0_wmask,
+  input  [7:0] RW0_wdata,
+  output [7:0] RW0_rdata
+);
+
+  wire array_RW0_rdata_MPORT_wmask_7;
+  wire array_RW0_rdata_MPORT_wmask_6;
+  wire array_RW0_rdata_MPORT_wmask_5;
+  wire array_RW0_rdata_MPORT_wmask_4;
+  wire array_RW0_rdata_MPORT_wmask_3;
+  wire array_RW0_rdata_MPORT_wmask_2;
+  wire array_RW0_rdata_MPORT_wmask_1;
+  wire array_RW0_rdata_MPORT_wmask_0;
+  assign array_RW0_rdata_MPORT_wmask_0 = RW0_wmode & RW0_wmask[0];
+  assign array_RW0_rdata_MPORT_wmask_1 = RW0_wmode & RW0_wmask[1];
+  assign array_RW0_rdata_MPORT_wmask_2 = RW0_wmode & RW0_wmask[2];
+  assign array_RW0_rdata_MPORT_wmask_3 = RW0_wmode & RW0_wmask[3];
+  assign array_RW0_rdata_MPORT_wmask_4 = RW0_wmode & RW0_wmask[4];
+  assign array_RW0_rdata_MPORT_wmask_5 = RW0_wmode & RW0_wmask[5];
+  assign array_RW0_rdata_MPORT_wmask_6 = RW0_wmode & RW0_wmask[6];
+  assign array_RW0_rdata_MPORT_wmask_7 = RW0_wmode & RW0_wmask[7];
+  array_256x8_0 array_ext (
+    .RW0_addr  (RW0_addr),
+    .RW0_en    (RW0_en),
+    .RW0_clk   (RW0_clk),
+    .RW0_wmode (RW0_wmode & (|RW0_wmask)),
+    .RW0_wdata (RW0_wdata),
+    .RW0_rdata (RW0_rdata),
+    .RW0_wmask
+      ({array_RW0_rdata_MPORT_wmask_7,
+        array_RW0_rdata_MPORT_wmask_6,
+        array_RW0_rdata_MPORT_wmask_5,
+        array_RW0_rdata_MPORT_wmask_4,
+        array_RW0_rdata_MPORT_wmask_3,
+        array_RW0_rdata_MPORT_wmask_2,
+        array_RW0_rdata_MPORT_wmask_1,
+        array_RW0_rdata_MPORT_wmask_0})
+  );
+endmodule
diff --git a/flow/platforms/asap7/lef/array_2048x137_bk.lef b/flow/platforms/asap7/lef/array_2048x137_bk.lef
new file mode 100644
index 0000000000..640f84c4e2
--- /dev/null
+++ b/flow/platforms/asap7/lef/array_2048x137_bk.lef
@@ -0,0 +1,2670 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-asap7-fakeram-m4-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_2048x137_bk
+  FOREIGN array_2048x137_bk 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 35.511 BY 26.285 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.048 0.024 0.072 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.096 0.024 0.12 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.144 0.024 0.168 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.192 0.024 0.216 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.24 0.024 0.264 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.288 0.024 0.312 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.336 0.024 0.36 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.384 0.024 0.408 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.432 0.024 0.456 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.48 0.024 0.504 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.528 0.024 0.552 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.576 0.024 0.6 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.624 0.024 0.648 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_wdata[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.672 0.024 0.696 ;
+    END
+  END RW0_wdata[13]
+  PIN RW0_wdata[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.72 0.024 0.744 ;
+    END
+  END RW0_wdata[14]
+  PIN RW0_wdata[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.768 0.024 0.792 ;
+    END
+  END RW0_wdata[15]
+  PIN RW0_wdata[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.816 0.024 0.84 ;
+    END
+  END RW0_wdata[16]
+  PIN RW0_wdata[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.864 0.024 0.888 ;
+    END
+  END RW0_wdata[17]
+  PIN RW0_wdata[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.912 0.024 0.936 ;
+    END
+  END RW0_wdata[18]
+  PIN RW0_wdata[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.96 0.024 0.984 ;
+    END
+  END RW0_wdata[19]
+  PIN RW0_wdata[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.008 0.024 1.032 ;
+    END
+  END RW0_wdata[20]
+  PIN RW0_wdata[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.056 0.024 1.08 ;
+    END
+  END RW0_wdata[21]
+  PIN RW0_wdata[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.104 0.024 1.128 ;
+    END
+  END RW0_wdata[22]
+  PIN RW0_wdata[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.152 0.024 1.176 ;
+    END
+  END RW0_wdata[23]
+  PIN RW0_wdata[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.2 0.024 1.224 ;
+    END
+  END RW0_wdata[24]
+  PIN RW0_wdata[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.248 0.024 1.272 ;
+    END
+  END RW0_wdata[25]
+  PIN RW0_wdata[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.296 0.024 1.32 ;
+    END
+  END RW0_wdata[26]
+  PIN RW0_wdata[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.344 0.024 1.368 ;
+    END
+  END RW0_wdata[27]
+  PIN RW0_wdata[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.392 0.024 1.416 ;
+    END
+  END RW0_wdata[28]
+  PIN RW0_wdata[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.44 0.024 1.464 ;
+    END
+  END RW0_wdata[29]
+  PIN RW0_wdata[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.488 0.024 1.512 ;
+    END
+  END RW0_wdata[30]
+  PIN RW0_wdata[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.536 0.024 1.56 ;
+    END
+  END RW0_wdata[31]
+  PIN RW0_wdata[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.584 0.024 1.608 ;
+    END
+  END RW0_wdata[32]
+  PIN RW0_wdata[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.632 0.024 1.656 ;
+    END
+  END RW0_wdata[33]
+  PIN RW0_wdata[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.68 0.024 1.704 ;
+    END
+  END RW0_wdata[34]
+  PIN RW0_wdata[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.728 0.024 1.752 ;
+    END
+  END RW0_wdata[35]
+  PIN RW0_wdata[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.776 0.024 1.8 ;
+    END
+  END RW0_wdata[36]
+  PIN RW0_wdata[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.824 0.024 1.848 ;
+    END
+  END RW0_wdata[37]
+  PIN RW0_wdata[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.872 0.024 1.896 ;
+    END
+  END RW0_wdata[38]
+  PIN RW0_wdata[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.92 0.024 1.944 ;
+    END
+  END RW0_wdata[39]
+  PIN RW0_wdata[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.968 0.024 1.992 ;
+    END
+  END RW0_wdata[40]
+  PIN RW0_wdata[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.016 0.024 2.04 ;
+    END
+  END RW0_wdata[41]
+  PIN RW0_wdata[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.064 0.024 2.088 ;
+    END
+  END RW0_wdata[42]
+  PIN RW0_wdata[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.112 0.024 2.136 ;
+    END
+  END RW0_wdata[43]
+  PIN RW0_wdata[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.16 0.024 2.184 ;
+    END
+  END RW0_wdata[44]
+  PIN RW0_wdata[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.208 0.024 2.232 ;
+    END
+  END RW0_wdata[45]
+  PIN RW0_wdata[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.256 0.024 2.28 ;
+    END
+  END RW0_wdata[46]
+  PIN RW0_wdata[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.304 0.024 2.328 ;
+    END
+  END RW0_wdata[47]
+  PIN RW0_wdata[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.352 0.024 2.376 ;
+    END
+  END RW0_wdata[48]
+  PIN RW0_wdata[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.4 0.024 2.424 ;
+    END
+  END RW0_wdata[49]
+  PIN RW0_wdata[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.448 0.024 2.472 ;
+    END
+  END RW0_wdata[50]
+  PIN RW0_wdata[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.496 0.024 2.52 ;
+    END
+  END RW0_wdata[51]
+  PIN RW0_wdata[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.544 0.024 2.568 ;
+    END
+  END RW0_wdata[52]
+  PIN RW0_wdata[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.592 0.024 2.616 ;
+    END
+  END RW0_wdata[53]
+  PIN RW0_wdata[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.64 0.024 2.664 ;
+    END
+  END RW0_wdata[54]
+  PIN RW0_wdata[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.688 0.024 2.712 ;
+    END
+  END RW0_wdata[55]
+  PIN RW0_wdata[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.736 0.024 2.76 ;
+    END
+  END RW0_wdata[56]
+  PIN RW0_wdata[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.784 0.024 2.808 ;
+    END
+  END RW0_wdata[57]
+  PIN RW0_wdata[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.832 0.024 2.856 ;
+    END
+  END RW0_wdata[58]
+  PIN RW0_wdata[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.88 0.024 2.904 ;
+    END
+  END RW0_wdata[59]
+  PIN RW0_wdata[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.928 0.024 2.952 ;
+    END
+  END RW0_wdata[60]
+  PIN RW0_wdata[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.976 0.024 3 ;
+    END
+  END RW0_wdata[61]
+  PIN RW0_wdata[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.024 0.024 3.048 ;
+    END
+  END RW0_wdata[62]
+  PIN RW0_wdata[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.072 0.024 3.096 ;
+    END
+  END RW0_wdata[63]
+  PIN RW0_wdata[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.12 0.024 3.144 ;
+    END
+  END RW0_wdata[64]
+  PIN RW0_wdata[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.168 0.024 3.192 ;
+    END
+  END RW0_wdata[65]
+  PIN RW0_wdata[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.216 0.024 3.24 ;
+    END
+  END RW0_wdata[66]
+  PIN RW0_wdata[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.264 0.024 3.288 ;
+    END
+  END RW0_wdata[67]
+  PIN RW0_wdata[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.312 0.024 3.336 ;
+    END
+  END RW0_wdata[68]
+  PIN RW0_wdata[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.36 0.024 3.384 ;
+    END
+  END RW0_wdata[69]
+  PIN RW0_wdata[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.408 0.024 3.432 ;
+    END
+  END RW0_wdata[70]
+  PIN RW0_wdata[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.456 0.024 3.48 ;
+    END
+  END RW0_wdata[71]
+  PIN RW0_wdata[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.504 0.024 3.528 ;
+    END
+  END RW0_wdata[72]
+  PIN RW0_wdata[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.552 0.024 3.576 ;
+    END
+  END RW0_wdata[73]
+  PIN RW0_wdata[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.6 0.024 3.624 ;
+    END
+  END RW0_wdata[74]
+  PIN RW0_wdata[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.648 0.024 3.672 ;
+    END
+  END RW0_wdata[75]
+  PIN RW0_wdata[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.696 0.024 3.72 ;
+    END
+  END RW0_wdata[76]
+  PIN RW0_wdata[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.744 0.024 3.768 ;
+    END
+  END RW0_wdata[77]
+  PIN RW0_wdata[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.792 0.024 3.816 ;
+    END
+  END RW0_wdata[78]
+  PIN RW0_wdata[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.84 0.024 3.864 ;
+    END
+  END RW0_wdata[79]
+  PIN RW0_wdata[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.888 0.024 3.912 ;
+    END
+  END RW0_wdata[80]
+  PIN RW0_wdata[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.936 0.024 3.96 ;
+    END
+  END RW0_wdata[81]
+  PIN RW0_wdata[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.984 0.024 4.008 ;
+    END
+  END RW0_wdata[82]
+  PIN RW0_wdata[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.032 0.024 4.056 ;
+    END
+  END RW0_wdata[83]
+  PIN RW0_wdata[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.08 0.024 4.104 ;
+    END
+  END RW0_wdata[84]
+  PIN RW0_wdata[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.128 0.024 4.152 ;
+    END
+  END RW0_wdata[85]
+  PIN RW0_wdata[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.176 0.024 4.2 ;
+    END
+  END RW0_wdata[86]
+  PIN RW0_wdata[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.224 0.024 4.248 ;
+    END
+  END RW0_wdata[87]
+  PIN RW0_wdata[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.272 0.024 4.296 ;
+    END
+  END RW0_wdata[88]
+  PIN RW0_wdata[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.32 0.024 4.344 ;
+    END
+  END RW0_wdata[89]
+  PIN RW0_wdata[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.368 0.024 4.392 ;
+    END
+  END RW0_wdata[90]
+  PIN RW0_wdata[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.416 0.024 4.44 ;
+    END
+  END RW0_wdata[91]
+  PIN RW0_wdata[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.464 0.024 4.488 ;
+    END
+  END RW0_wdata[92]
+  PIN RW0_wdata[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.512 0.024 4.536 ;
+    END
+  END RW0_wdata[93]
+  PIN RW0_wdata[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.56 0.024 4.584 ;
+    END
+  END RW0_wdata[94]
+  PIN RW0_wdata[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.608 0.024 4.632 ;
+    END
+  END RW0_wdata[95]
+  PIN RW0_wdata[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.656 0.024 4.68 ;
+    END
+  END RW0_wdata[96]
+  PIN RW0_wdata[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.704 0.024 4.728 ;
+    END
+  END RW0_wdata[97]
+  PIN RW0_wdata[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.752 0.024 4.776 ;
+    END
+  END RW0_wdata[98]
+  PIN RW0_wdata[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.8 0.024 4.824 ;
+    END
+  END RW0_wdata[99]
+  PIN RW0_wdata[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.848 0.024 4.872 ;
+    END
+  END RW0_wdata[100]
+  PIN RW0_wdata[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.896 0.024 4.92 ;
+    END
+  END RW0_wdata[101]
+  PIN RW0_wdata[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.944 0.024 4.968 ;
+    END
+  END RW0_wdata[102]
+  PIN RW0_wdata[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.992 0.024 5.016 ;
+    END
+  END RW0_wdata[103]
+  PIN RW0_wdata[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.04 0.024 5.064 ;
+    END
+  END RW0_wdata[104]
+  PIN RW0_wdata[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.088 0.024 5.112 ;
+    END
+  END RW0_wdata[105]
+  PIN RW0_wdata[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.136 0.024 5.16 ;
+    END
+  END RW0_wdata[106]
+  PIN RW0_wdata[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.184 0.024 5.208 ;
+    END
+  END RW0_wdata[107]
+  PIN RW0_wdata[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.232 0.024 5.256 ;
+    END
+  END RW0_wdata[108]
+  PIN RW0_wdata[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.28 0.024 5.304 ;
+    END
+  END RW0_wdata[109]
+  PIN RW0_wdata[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.328 0.024 5.352 ;
+    END
+  END RW0_wdata[110]
+  PIN RW0_wdata[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.376 0.024 5.4 ;
+    END
+  END RW0_wdata[111]
+  PIN RW0_wdata[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.424 0.024 5.448 ;
+    END
+  END RW0_wdata[112]
+  PIN RW0_wdata[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.472 0.024 5.496 ;
+    END
+  END RW0_wdata[113]
+  PIN RW0_wdata[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.52 0.024 5.544 ;
+    END
+  END RW0_wdata[114]
+  PIN RW0_wdata[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.568 0.024 5.592 ;
+    END
+  END RW0_wdata[115]
+  PIN RW0_wdata[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.616 0.024 5.64 ;
+    END
+  END RW0_wdata[116]
+  PIN RW0_wdata[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.664 0.024 5.688 ;
+    END
+  END RW0_wdata[117]
+  PIN RW0_wdata[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.712 0.024 5.736 ;
+    END
+  END RW0_wdata[118]
+  PIN RW0_wdata[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.76 0.024 5.784 ;
+    END
+  END RW0_wdata[119]
+  PIN RW0_wdata[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.808 0.024 5.832 ;
+    END
+  END RW0_wdata[120]
+  PIN RW0_wdata[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.856 0.024 5.88 ;
+    END
+  END RW0_wdata[121]
+  PIN RW0_wdata[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.904 0.024 5.928 ;
+    END
+  END RW0_wdata[122]
+  PIN RW0_wdata[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.952 0.024 5.976 ;
+    END
+  END RW0_wdata[123]
+  PIN RW0_wdata[124]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6 0.024 6.024 ;
+    END
+  END RW0_wdata[124]
+  PIN RW0_wdata[125]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.048 0.024 6.072 ;
+    END
+  END RW0_wdata[125]
+  PIN RW0_wdata[126]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.096 0.024 6.12 ;
+    END
+  END RW0_wdata[126]
+  PIN RW0_wdata[127]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.144 0.024 6.168 ;
+    END
+  END RW0_wdata[127]
+  PIN RW0_wdata[128]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.192 0.024 6.216 ;
+    END
+  END RW0_wdata[128]
+  PIN RW0_wdata[129]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.24 0.024 6.264 ;
+    END
+  END RW0_wdata[129]
+  PIN RW0_wdata[130]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.288 0.024 6.312 ;
+    END
+  END RW0_wdata[130]
+  PIN RW0_wdata[131]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.336 0.024 6.36 ;
+    END
+  END RW0_wdata[131]
+  PIN RW0_wdata[132]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.384 0.024 6.408 ;
+    END
+  END RW0_wdata[132]
+  PIN RW0_wdata[133]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.432 0.024 6.456 ;
+    END
+  END RW0_wdata[133]
+  PIN RW0_wdata[134]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.48 0.024 6.504 ;
+    END
+  END RW0_wdata[134]
+  PIN RW0_wdata[135]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.528 0.024 6.552 ;
+    END
+  END RW0_wdata[135]
+  PIN RW0_wdata[136]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.576 0.024 6.6 ;
+    END
+  END RW0_wdata[136]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.624 0.024 6.648 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.672 0.024 6.696 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.72 0.024 6.744 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.768 0.024 6.792 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.816 0.024 6.84 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.864 0.024 6.888 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.912 0.024 6.936 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.96 0.024 6.984 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.008 0.024 7.032 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.056 0.024 7.08 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.104 0.024 7.128 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.152 0.024 7.176 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.2 0.024 7.224 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_rdata[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.248 0.024 7.272 ;
+    END
+  END RW0_rdata[13]
+  PIN RW0_rdata[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.296 0.024 7.32 ;
+    END
+  END RW0_rdata[14]
+  PIN RW0_rdata[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.344 0.024 7.368 ;
+    END
+  END RW0_rdata[15]
+  PIN RW0_rdata[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.392 0.024 7.416 ;
+    END
+  END RW0_rdata[16]
+  PIN RW0_rdata[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.44 0.024 7.464 ;
+    END
+  END RW0_rdata[17]
+  PIN RW0_rdata[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.488 0.024 7.512 ;
+    END
+  END RW0_rdata[18]
+  PIN RW0_rdata[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.536 0.024 7.56 ;
+    END
+  END RW0_rdata[19]
+  PIN RW0_rdata[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.584 0.024 7.608 ;
+    END
+  END RW0_rdata[20]
+  PIN RW0_rdata[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.632 0.024 7.656 ;
+    END
+  END RW0_rdata[21]
+  PIN RW0_rdata[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.68 0.024 7.704 ;
+    END
+  END RW0_rdata[22]
+  PIN RW0_rdata[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.728 0.024 7.752 ;
+    END
+  END RW0_rdata[23]
+  PIN RW0_rdata[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.776 0.024 7.8 ;
+    END
+  END RW0_rdata[24]
+  PIN RW0_rdata[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.824 0.024 7.848 ;
+    END
+  END RW0_rdata[25]
+  PIN RW0_rdata[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.872 0.024 7.896 ;
+    END
+  END RW0_rdata[26]
+  PIN RW0_rdata[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.92 0.024 7.944 ;
+    END
+  END RW0_rdata[27]
+  PIN RW0_rdata[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.968 0.024 7.992 ;
+    END
+  END RW0_rdata[28]
+  PIN RW0_rdata[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.016 0.024 8.04 ;
+    END
+  END RW0_rdata[29]
+  PIN RW0_rdata[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.064 0.024 8.088 ;
+    END
+  END RW0_rdata[30]
+  PIN RW0_rdata[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.112 0.024 8.136 ;
+    END
+  END RW0_rdata[31]
+  PIN RW0_rdata[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.16 0.024 8.184 ;
+    END
+  END RW0_rdata[32]
+  PIN RW0_rdata[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.208 0.024 8.232 ;
+    END
+  END RW0_rdata[33]
+  PIN RW0_rdata[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.256 0.024 8.28 ;
+    END
+  END RW0_rdata[34]
+  PIN RW0_rdata[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.304 0.024 8.328 ;
+    END
+  END RW0_rdata[35]
+  PIN RW0_rdata[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.352 0.024 8.376 ;
+    END
+  END RW0_rdata[36]
+  PIN RW0_rdata[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.4 0.024 8.424 ;
+    END
+  END RW0_rdata[37]
+  PIN RW0_rdata[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.448 0.024 8.472 ;
+    END
+  END RW0_rdata[38]
+  PIN RW0_rdata[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.496 0.024 8.52 ;
+    END
+  END RW0_rdata[39]
+  PIN RW0_rdata[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.544 0.024 8.568 ;
+    END
+  END RW0_rdata[40]
+  PIN RW0_rdata[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.592 0.024 8.616 ;
+    END
+  END RW0_rdata[41]
+  PIN RW0_rdata[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.64 0.024 8.664 ;
+    END
+  END RW0_rdata[42]
+  PIN RW0_rdata[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.688 0.024 8.712 ;
+    END
+  END RW0_rdata[43]
+  PIN RW0_rdata[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.736 0.024 8.76 ;
+    END
+  END RW0_rdata[44]
+  PIN RW0_rdata[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.784 0.024 8.808 ;
+    END
+  END RW0_rdata[45]
+  PIN RW0_rdata[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.832 0.024 8.856 ;
+    END
+  END RW0_rdata[46]
+  PIN RW0_rdata[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.88 0.024 8.904 ;
+    END
+  END RW0_rdata[47]
+  PIN RW0_rdata[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.928 0.024 8.952 ;
+    END
+  END RW0_rdata[48]
+  PIN RW0_rdata[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.976 0.024 9 ;
+    END
+  END RW0_rdata[49]
+  PIN RW0_rdata[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.024 0.024 9.048 ;
+    END
+  END RW0_rdata[50]
+  PIN RW0_rdata[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.072 0.024 9.096 ;
+    END
+  END RW0_rdata[51]
+  PIN RW0_rdata[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.12 0.024 9.144 ;
+    END
+  END RW0_rdata[52]
+  PIN RW0_rdata[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.168 0.024 9.192 ;
+    END
+  END RW0_rdata[53]
+  PIN RW0_rdata[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.216 0.024 9.24 ;
+    END
+  END RW0_rdata[54]
+  PIN RW0_rdata[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.264 0.024 9.288 ;
+    END
+  END RW0_rdata[55]
+  PIN RW0_rdata[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.312 0.024 9.336 ;
+    END
+  END RW0_rdata[56]
+  PIN RW0_rdata[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.36 0.024 9.384 ;
+    END
+  END RW0_rdata[57]
+  PIN RW0_rdata[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.408 0.024 9.432 ;
+    END
+  END RW0_rdata[58]
+  PIN RW0_rdata[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.456 0.024 9.48 ;
+    END
+  END RW0_rdata[59]
+  PIN RW0_rdata[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.504 0.024 9.528 ;
+    END
+  END RW0_rdata[60]
+  PIN RW0_rdata[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.552 0.024 9.576 ;
+    END
+  END RW0_rdata[61]
+  PIN RW0_rdata[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.6 0.024 9.624 ;
+    END
+  END RW0_rdata[62]
+  PIN RW0_rdata[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.648 0.024 9.672 ;
+    END
+  END RW0_rdata[63]
+  PIN RW0_rdata[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.696 0.024 9.72 ;
+    END
+  END RW0_rdata[64]
+  PIN RW0_rdata[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.744 0.024 9.768 ;
+    END
+  END RW0_rdata[65]
+  PIN RW0_rdata[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.792 0.024 9.816 ;
+    END
+  END RW0_rdata[66]
+  PIN RW0_rdata[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.84 0.024 9.864 ;
+    END
+  END RW0_rdata[67]
+  PIN RW0_rdata[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.888 0.024 9.912 ;
+    END
+  END RW0_rdata[68]
+  PIN RW0_rdata[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.936 0.024 9.96 ;
+    END
+  END RW0_rdata[69]
+  PIN RW0_rdata[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.984 0.024 10.008 ;
+    END
+  END RW0_rdata[70]
+  PIN RW0_rdata[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.032 0.024 10.056 ;
+    END
+  END RW0_rdata[71]
+  PIN RW0_rdata[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.08 0.024 10.104 ;
+    END
+  END RW0_rdata[72]
+  PIN RW0_rdata[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.128 0.024 10.152 ;
+    END
+  END RW0_rdata[73]
+  PIN RW0_rdata[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.176 0.024 10.2 ;
+    END
+  END RW0_rdata[74]
+  PIN RW0_rdata[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.224 0.024 10.248 ;
+    END
+  END RW0_rdata[75]
+  PIN RW0_rdata[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.272 0.024 10.296 ;
+    END
+  END RW0_rdata[76]
+  PIN RW0_rdata[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.32 0.024 10.344 ;
+    END
+  END RW0_rdata[77]
+  PIN RW0_rdata[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.368 0.024 10.392 ;
+    END
+  END RW0_rdata[78]
+  PIN RW0_rdata[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.416 0.024 10.44 ;
+    END
+  END RW0_rdata[79]
+  PIN RW0_rdata[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.464 0.024 10.488 ;
+    END
+  END RW0_rdata[80]
+  PIN RW0_rdata[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.512 0.024 10.536 ;
+    END
+  END RW0_rdata[81]
+  PIN RW0_rdata[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.56 0.024 10.584 ;
+    END
+  END RW0_rdata[82]
+  PIN RW0_rdata[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.608 0.024 10.632 ;
+    END
+  END RW0_rdata[83]
+  PIN RW0_rdata[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.656 0.024 10.68 ;
+    END
+  END RW0_rdata[84]
+  PIN RW0_rdata[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.704 0.024 10.728 ;
+    END
+  END RW0_rdata[85]
+  PIN RW0_rdata[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.752 0.024 10.776 ;
+    END
+  END RW0_rdata[86]
+  PIN RW0_rdata[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.8 0.024 10.824 ;
+    END
+  END RW0_rdata[87]
+  PIN RW0_rdata[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.848 0.024 10.872 ;
+    END
+  END RW0_rdata[88]
+  PIN RW0_rdata[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.896 0.024 10.92 ;
+    END
+  END RW0_rdata[89]
+  PIN RW0_rdata[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.944 0.024 10.968 ;
+    END
+  END RW0_rdata[90]
+  PIN RW0_rdata[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.992 0.024 11.016 ;
+    END
+  END RW0_rdata[91]
+  PIN RW0_rdata[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.04 0.024 11.064 ;
+    END
+  END RW0_rdata[92]
+  PIN RW0_rdata[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.088 0.024 11.112 ;
+    END
+  END RW0_rdata[93]
+  PIN RW0_rdata[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.136 0.024 11.16 ;
+    END
+  END RW0_rdata[94]
+  PIN RW0_rdata[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.184 0.024 11.208 ;
+    END
+  END RW0_rdata[95]
+  PIN RW0_rdata[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.232 0.024 11.256 ;
+    END
+  END RW0_rdata[96]
+  PIN RW0_rdata[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.28 0.024 11.304 ;
+    END
+  END RW0_rdata[97]
+  PIN RW0_rdata[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.328 0.024 11.352 ;
+    END
+  END RW0_rdata[98]
+  PIN RW0_rdata[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.376 0.024 11.4 ;
+    END
+  END RW0_rdata[99]
+  PIN RW0_rdata[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.424 0.024 11.448 ;
+    END
+  END RW0_rdata[100]
+  PIN RW0_rdata[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.472 0.024 11.496 ;
+    END
+  END RW0_rdata[101]
+  PIN RW0_rdata[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.52 0.024 11.544 ;
+    END
+  END RW0_rdata[102]
+  PIN RW0_rdata[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.568 0.024 11.592 ;
+    END
+  END RW0_rdata[103]
+  PIN RW0_rdata[104]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.616 0.024 11.64 ;
+    END
+  END RW0_rdata[104]
+  PIN RW0_rdata[105]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.664 0.024 11.688 ;
+    END
+  END RW0_rdata[105]
+  PIN RW0_rdata[106]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.712 0.024 11.736 ;
+    END
+  END RW0_rdata[106]
+  PIN RW0_rdata[107]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.76 0.024 11.784 ;
+    END
+  END RW0_rdata[107]
+  PIN RW0_rdata[108]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.808 0.024 11.832 ;
+    END
+  END RW0_rdata[108]
+  PIN RW0_rdata[109]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.856 0.024 11.88 ;
+    END
+  END RW0_rdata[109]
+  PIN RW0_rdata[110]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.904 0.024 11.928 ;
+    END
+  END RW0_rdata[110]
+  PIN RW0_rdata[111]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.952 0.024 11.976 ;
+    END
+  END RW0_rdata[111]
+  PIN RW0_rdata[112]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12 0.024 12.024 ;
+    END
+  END RW0_rdata[112]
+  PIN RW0_rdata[113]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.048 0.024 12.072 ;
+    END
+  END RW0_rdata[113]
+  PIN RW0_rdata[114]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.096 0.024 12.12 ;
+    END
+  END RW0_rdata[114]
+  PIN RW0_rdata[115]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.144 0.024 12.168 ;
+    END
+  END RW0_rdata[115]
+  PIN RW0_rdata[116]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.192 0.024 12.216 ;
+    END
+  END RW0_rdata[116]
+  PIN RW0_rdata[117]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.24 0.024 12.264 ;
+    END
+  END RW0_rdata[117]
+  PIN RW0_rdata[118]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.288 0.024 12.312 ;
+    END
+  END RW0_rdata[118]
+  PIN RW0_rdata[119]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.336 0.024 12.36 ;
+    END
+  END RW0_rdata[119]
+  PIN RW0_rdata[120]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.384 0.024 12.408 ;
+    END
+  END RW0_rdata[120]
+  PIN RW0_rdata[121]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.432 0.024 12.456 ;
+    END
+  END RW0_rdata[121]
+  PIN RW0_rdata[122]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.48 0.024 12.504 ;
+    END
+  END RW0_rdata[122]
+  PIN RW0_rdata[123]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.528 0.024 12.552 ;
+    END
+  END RW0_rdata[123]
+  PIN RW0_rdata[124]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.576 0.024 12.6 ;
+    END
+  END RW0_rdata[124]
+  PIN RW0_rdata[125]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.624 0.024 12.648 ;
+    END
+  END RW0_rdata[125]
+  PIN RW0_rdata[126]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.672 0.024 12.696 ;
+    END
+  END RW0_rdata[126]
+  PIN RW0_rdata[127]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.72 0.024 12.744 ;
+    END
+  END RW0_rdata[127]
+  PIN RW0_rdata[128]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.768 0.024 12.792 ;
+    END
+  END RW0_rdata[128]
+  PIN RW0_rdata[129]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.816 0.024 12.84 ;
+    END
+  END RW0_rdata[129]
+  PIN RW0_rdata[130]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.864 0.024 12.888 ;
+    END
+  END RW0_rdata[130]
+  PIN RW0_rdata[131]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.912 0.024 12.936 ;
+    END
+  END RW0_rdata[131]
+  PIN RW0_rdata[132]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.96 0.024 12.984 ;
+    END
+  END RW0_rdata[132]
+  PIN RW0_rdata[133]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.008 0.024 13.032 ;
+    END
+  END RW0_rdata[133]
+  PIN RW0_rdata[134]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.056 0.024 13.08 ;
+    END
+  END RW0_rdata[134]
+  PIN RW0_rdata[135]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.104 0.024 13.128 ;
+    END
+  END RW0_rdata[135]
+  PIN RW0_rdata[136]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.152 0.024 13.176 ;
+    END
+  END RW0_rdata[136]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.2 0.024 13.224 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.248 0.024 13.272 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.296 0.024 13.32 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.344 0.024 13.368 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.392 0.024 13.416 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.44 0.024 13.464 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.488 0.024 13.512 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.536 0.024 13.56 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.584 0.024 13.608 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.632 0.024 13.656 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.68 0.024 13.704 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0 35.463 0.096 ;
+      RECT 0.048 0.768 35.463 0.864 ;
+      RECT 0.048 1.536 35.463 1.632 ;
+      RECT 0.048 2.304 35.463 2.4 ;
+      RECT 0.048 3.072 35.463 3.168 ;
+      RECT 0.048 3.84 35.463 3.936 ;
+      RECT 0.048 4.608 35.463 4.704 ;
+      RECT 0.048 5.376 35.463 5.472 ;
+      RECT 0.048 6.144 35.463 6.24 ;
+      RECT 0.048 6.912 35.463 7.008 ;
+      RECT 0.048 7.68 35.463 7.776 ;
+      RECT 0.048 8.448 35.463 8.544 ;
+      RECT 0.048 9.216 35.463 9.312 ;
+      RECT 0.048 9.984 35.463 10.08 ;
+      RECT 0.048 10.752 35.463 10.848 ;
+      RECT 0.048 11.52 35.463 11.616 ;
+      RECT 0.048 12.288 35.463 12.384 ;
+      RECT 0.048 13.056 35.463 13.152 ;
+      RECT 0.048 13.824 35.463 13.92 ;
+      RECT 0.048 14.592 35.463 14.688 ;
+      RECT 0.048 15.36 35.463 15.456 ;
+      RECT 0.048 16.128 35.463 16.224 ;
+      RECT 0.048 16.896 35.463 16.992 ;
+      RECT 0.048 17.664 35.463 17.76 ;
+      RECT 0.048 18.432 35.463 18.528 ;
+      RECT 0.048 19.2 35.463 19.296 ;
+      RECT 0.048 19.968 35.463 20.064 ;
+      RECT 0.048 20.736 35.463 20.832 ;
+      RECT 0.048 21.504 35.463 21.6 ;
+      RECT 0.048 22.272 35.463 22.368 ;
+      RECT 0.048 23.04 35.463 23.136 ;
+      RECT 0.048 23.808 35.463 23.904 ;
+      RECT 0.048 24.576 35.463 24.672 ;
+      RECT 0.048 25.344 35.463 25.44 ;
+      RECT 0.048 26.112 35.463 26.208 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0.384 35.463 0.48 ;
+      RECT 0.048 1.152 35.463 1.248 ;
+      RECT 0.048 1.92 35.463 2.016 ;
+      RECT 0.048 2.688 35.463 2.784 ;
+      RECT 0.048 3.456 35.463 3.552 ;
+      RECT 0.048 4.224 35.463 4.32 ;
+      RECT 0.048 4.992 35.463 5.088 ;
+      RECT 0.048 5.76 35.463 5.856 ;
+      RECT 0.048 6.528 35.463 6.624 ;
+      RECT 0.048 7.296 35.463 7.392 ;
+      RECT 0.048 8.064 35.463 8.16 ;
+      RECT 0.048 8.832 35.463 8.928 ;
+      RECT 0.048 9.6 35.463 9.696 ;
+      RECT 0.048 10.368 35.463 10.464 ;
+      RECT 0.048 11.136 35.463 11.232 ;
+      RECT 0.048 11.904 35.463 12 ;
+      RECT 0.048 12.672 35.463 12.768 ;
+      RECT 0.048 13.44 35.463 13.536 ;
+      RECT 0.048 14.208 35.463 14.304 ;
+      RECT 0.048 14.976 35.463 15.072 ;
+      RECT 0.048 15.744 35.463 15.84 ;
+      RECT 0.048 16.512 35.463 16.608 ;
+      RECT 0.048 17.28 35.463 17.376 ;
+      RECT 0.048 18.048 35.463 18.144 ;
+      RECT 0.048 18.816 35.463 18.912 ;
+      RECT 0.048 19.584 35.463 19.68 ;
+      RECT 0.048 20.352 35.463 20.448 ;
+      RECT 0.048 21.12 35.463 21.216 ;
+      RECT 0.048 21.888 35.463 21.984 ;
+      RECT 0.048 22.656 35.463 22.752 ;
+      RECT 0.048 23.424 35.463 23.52 ;
+      RECT 0.048 24.192 35.463 24.288 ;
+      RECT 0.048 24.96 35.463 25.056 ;
+      RECT 0.048 25.728 35.463 25.824 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 35.511 26.285 ;
+    LAYER M2 ;
+    RECT 0 0 35.511 26.285 ;
+    LAYER M3 ;
+    RECT 0 0 35.511 26.285 ;
+  END
+END array_2048x137_bk
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lef/array_256x104.lef b/flow/platforms/asap7/lef/array_256x104.lef
new file mode 100644
index 0000000000..ab4e1cec37
--- /dev/null
+++ b/flow/platforms/asap7/lef/array_256x104.lef
@@ -0,0 +1,2147 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-asap7-fakeram-m4-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x104
+  FOREIGN array_256x104 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 28.17 BY 26.071 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wmask[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.048 0.024 0.072 ;
+    END
+  END RW0_wmask[0]
+  PIN RW0_wmask[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.144 0.024 0.168 ;
+    END
+  END RW0_wmask[1]
+  PIN RW0_wmask[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.24 0.024 0.264 ;
+    END
+  END RW0_wmask[2]
+  PIN RW0_wmask[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.336 0.024 0.36 ;
+    END
+  END RW0_wmask[3]
+  PIN RW0_wmask[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.432 0.024 0.456 ;
+    END
+  END RW0_wmask[4]
+  PIN RW0_wmask[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.528 0.024 0.552 ;
+    END
+  END RW0_wmask[5]
+  PIN RW0_wmask[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.624 0.024 0.648 ;
+    END
+  END RW0_wmask[6]
+  PIN RW0_wmask[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.72 0.024 0.744 ;
+    END
+  END RW0_wmask[7]
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.816 0.024 0.84 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.912 0.024 0.936 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.008 0.024 1.032 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.104 0.024 1.128 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.2 0.024 1.224 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.296 0.024 1.32 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.392 0.024 1.416 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.488 0.024 1.512 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.584 0.024 1.608 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.68 0.024 1.704 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.776 0.024 1.8 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.872 0.024 1.896 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.968 0.024 1.992 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_wdata[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.064 0.024 2.088 ;
+    END
+  END RW0_wdata[13]
+  PIN RW0_wdata[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.16 0.024 2.184 ;
+    END
+  END RW0_wdata[14]
+  PIN RW0_wdata[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.256 0.024 2.28 ;
+    END
+  END RW0_wdata[15]
+  PIN RW0_wdata[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.352 0.024 2.376 ;
+    END
+  END RW0_wdata[16]
+  PIN RW0_wdata[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.448 0.024 2.472 ;
+    END
+  END RW0_wdata[17]
+  PIN RW0_wdata[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.544 0.024 2.568 ;
+    END
+  END RW0_wdata[18]
+  PIN RW0_wdata[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.64 0.024 2.664 ;
+    END
+  END RW0_wdata[19]
+  PIN RW0_wdata[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.736 0.024 2.76 ;
+    END
+  END RW0_wdata[20]
+  PIN RW0_wdata[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.832 0.024 2.856 ;
+    END
+  END RW0_wdata[21]
+  PIN RW0_wdata[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.928 0.024 2.952 ;
+    END
+  END RW0_wdata[22]
+  PIN RW0_wdata[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.024 0.024 3.048 ;
+    END
+  END RW0_wdata[23]
+  PIN RW0_wdata[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.12 0.024 3.144 ;
+    END
+  END RW0_wdata[24]
+  PIN RW0_wdata[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.216 0.024 3.24 ;
+    END
+  END RW0_wdata[25]
+  PIN RW0_wdata[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.312 0.024 3.336 ;
+    END
+  END RW0_wdata[26]
+  PIN RW0_wdata[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.408 0.024 3.432 ;
+    END
+  END RW0_wdata[27]
+  PIN RW0_wdata[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.504 0.024 3.528 ;
+    END
+  END RW0_wdata[28]
+  PIN RW0_wdata[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.6 0.024 3.624 ;
+    END
+  END RW0_wdata[29]
+  PIN RW0_wdata[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.696 0.024 3.72 ;
+    END
+  END RW0_wdata[30]
+  PIN RW0_wdata[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.792 0.024 3.816 ;
+    END
+  END RW0_wdata[31]
+  PIN RW0_wdata[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.888 0.024 3.912 ;
+    END
+  END RW0_wdata[32]
+  PIN RW0_wdata[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.984 0.024 4.008 ;
+    END
+  END RW0_wdata[33]
+  PIN RW0_wdata[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.08 0.024 4.104 ;
+    END
+  END RW0_wdata[34]
+  PIN RW0_wdata[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.176 0.024 4.2 ;
+    END
+  END RW0_wdata[35]
+  PIN RW0_wdata[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.272 0.024 4.296 ;
+    END
+  END RW0_wdata[36]
+  PIN RW0_wdata[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.368 0.024 4.392 ;
+    END
+  END RW0_wdata[37]
+  PIN RW0_wdata[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.464 0.024 4.488 ;
+    END
+  END RW0_wdata[38]
+  PIN RW0_wdata[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.56 0.024 4.584 ;
+    END
+  END RW0_wdata[39]
+  PIN RW0_wdata[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.656 0.024 4.68 ;
+    END
+  END RW0_wdata[40]
+  PIN RW0_wdata[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.752 0.024 4.776 ;
+    END
+  END RW0_wdata[41]
+  PIN RW0_wdata[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.848 0.024 4.872 ;
+    END
+  END RW0_wdata[42]
+  PIN RW0_wdata[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.944 0.024 4.968 ;
+    END
+  END RW0_wdata[43]
+  PIN RW0_wdata[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.04 0.024 5.064 ;
+    END
+  END RW0_wdata[44]
+  PIN RW0_wdata[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.136 0.024 5.16 ;
+    END
+  END RW0_wdata[45]
+  PIN RW0_wdata[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.232 0.024 5.256 ;
+    END
+  END RW0_wdata[46]
+  PIN RW0_wdata[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.328 0.024 5.352 ;
+    END
+  END RW0_wdata[47]
+  PIN RW0_wdata[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.424 0.024 5.448 ;
+    END
+  END RW0_wdata[48]
+  PIN RW0_wdata[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.52 0.024 5.544 ;
+    END
+  END RW0_wdata[49]
+  PIN RW0_wdata[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.616 0.024 5.64 ;
+    END
+  END RW0_wdata[50]
+  PIN RW0_wdata[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.712 0.024 5.736 ;
+    END
+  END RW0_wdata[51]
+  PIN RW0_wdata[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.808 0.024 5.832 ;
+    END
+  END RW0_wdata[52]
+  PIN RW0_wdata[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.904 0.024 5.928 ;
+    END
+  END RW0_wdata[53]
+  PIN RW0_wdata[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6 0.024 6.024 ;
+    END
+  END RW0_wdata[54]
+  PIN RW0_wdata[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.096 0.024 6.12 ;
+    END
+  END RW0_wdata[55]
+  PIN RW0_wdata[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.192 0.024 6.216 ;
+    END
+  END RW0_wdata[56]
+  PIN RW0_wdata[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.288 0.024 6.312 ;
+    END
+  END RW0_wdata[57]
+  PIN RW0_wdata[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.384 0.024 6.408 ;
+    END
+  END RW0_wdata[58]
+  PIN RW0_wdata[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.48 0.024 6.504 ;
+    END
+  END RW0_wdata[59]
+  PIN RW0_wdata[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.576 0.024 6.6 ;
+    END
+  END RW0_wdata[60]
+  PIN RW0_wdata[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.672 0.024 6.696 ;
+    END
+  END RW0_wdata[61]
+  PIN RW0_wdata[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.768 0.024 6.792 ;
+    END
+  END RW0_wdata[62]
+  PIN RW0_wdata[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.864 0.024 6.888 ;
+    END
+  END RW0_wdata[63]
+  PIN RW0_wdata[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.96 0.024 6.984 ;
+    END
+  END RW0_wdata[64]
+  PIN RW0_wdata[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.056 0.024 7.08 ;
+    END
+  END RW0_wdata[65]
+  PIN RW0_wdata[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.152 0.024 7.176 ;
+    END
+  END RW0_wdata[66]
+  PIN RW0_wdata[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.248 0.024 7.272 ;
+    END
+  END RW0_wdata[67]
+  PIN RW0_wdata[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.344 0.024 7.368 ;
+    END
+  END RW0_wdata[68]
+  PIN RW0_wdata[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.44 0.024 7.464 ;
+    END
+  END RW0_wdata[69]
+  PIN RW0_wdata[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.536 0.024 7.56 ;
+    END
+  END RW0_wdata[70]
+  PIN RW0_wdata[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.632 0.024 7.656 ;
+    END
+  END RW0_wdata[71]
+  PIN RW0_wdata[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.728 0.024 7.752 ;
+    END
+  END RW0_wdata[72]
+  PIN RW0_wdata[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.824 0.024 7.848 ;
+    END
+  END RW0_wdata[73]
+  PIN RW0_wdata[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.92 0.024 7.944 ;
+    END
+  END RW0_wdata[74]
+  PIN RW0_wdata[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.016 0.024 8.04 ;
+    END
+  END RW0_wdata[75]
+  PIN RW0_wdata[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.112 0.024 8.136 ;
+    END
+  END RW0_wdata[76]
+  PIN RW0_wdata[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.208 0.024 8.232 ;
+    END
+  END RW0_wdata[77]
+  PIN RW0_wdata[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.304 0.024 8.328 ;
+    END
+  END RW0_wdata[78]
+  PIN RW0_wdata[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.4 0.024 8.424 ;
+    END
+  END RW0_wdata[79]
+  PIN RW0_wdata[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.496 0.024 8.52 ;
+    END
+  END RW0_wdata[80]
+  PIN RW0_wdata[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.592 0.024 8.616 ;
+    END
+  END RW0_wdata[81]
+  PIN RW0_wdata[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.688 0.024 8.712 ;
+    END
+  END RW0_wdata[82]
+  PIN RW0_wdata[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.784 0.024 8.808 ;
+    END
+  END RW0_wdata[83]
+  PIN RW0_wdata[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.88 0.024 8.904 ;
+    END
+  END RW0_wdata[84]
+  PIN RW0_wdata[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.976 0.024 9 ;
+    END
+  END RW0_wdata[85]
+  PIN RW0_wdata[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.072 0.024 9.096 ;
+    END
+  END RW0_wdata[86]
+  PIN RW0_wdata[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.168 0.024 9.192 ;
+    END
+  END RW0_wdata[87]
+  PIN RW0_wdata[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.264 0.024 9.288 ;
+    END
+  END RW0_wdata[88]
+  PIN RW0_wdata[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.36 0.024 9.384 ;
+    END
+  END RW0_wdata[89]
+  PIN RW0_wdata[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.456 0.024 9.48 ;
+    END
+  END RW0_wdata[90]
+  PIN RW0_wdata[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.552 0.024 9.576 ;
+    END
+  END RW0_wdata[91]
+  PIN RW0_wdata[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.648 0.024 9.672 ;
+    END
+  END RW0_wdata[92]
+  PIN RW0_wdata[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.744 0.024 9.768 ;
+    END
+  END RW0_wdata[93]
+  PIN RW0_wdata[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.84 0.024 9.864 ;
+    END
+  END RW0_wdata[94]
+  PIN RW0_wdata[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.936 0.024 9.96 ;
+    END
+  END RW0_wdata[95]
+  PIN RW0_wdata[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.032 0.024 10.056 ;
+    END
+  END RW0_wdata[96]
+  PIN RW0_wdata[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.128 0.024 10.152 ;
+    END
+  END RW0_wdata[97]
+  PIN RW0_wdata[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.224 0.024 10.248 ;
+    END
+  END RW0_wdata[98]
+  PIN RW0_wdata[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.32 0.024 10.344 ;
+    END
+  END RW0_wdata[99]
+  PIN RW0_wdata[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.416 0.024 10.44 ;
+    END
+  END RW0_wdata[100]
+  PIN RW0_wdata[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.512 0.024 10.536 ;
+    END
+  END RW0_wdata[101]
+  PIN RW0_wdata[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.608 0.024 10.632 ;
+    END
+  END RW0_wdata[102]
+  PIN RW0_wdata[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.704 0.024 10.728 ;
+    END
+  END RW0_wdata[103]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.8 0.024 10.824 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.896 0.024 10.92 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.992 0.024 11.016 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.088 0.024 11.112 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.184 0.024 11.208 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.28 0.024 11.304 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.376 0.024 11.4 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.472 0.024 11.496 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.568 0.024 11.592 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.664 0.024 11.688 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.76 0.024 11.784 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.856 0.024 11.88 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.952 0.024 11.976 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_rdata[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.048 0.024 12.072 ;
+    END
+  END RW0_rdata[13]
+  PIN RW0_rdata[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.144 0.024 12.168 ;
+    END
+  END RW0_rdata[14]
+  PIN RW0_rdata[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.24 0.024 12.264 ;
+    END
+  END RW0_rdata[15]
+  PIN RW0_rdata[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.336 0.024 12.36 ;
+    END
+  END RW0_rdata[16]
+  PIN RW0_rdata[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.432 0.024 12.456 ;
+    END
+  END RW0_rdata[17]
+  PIN RW0_rdata[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.528 0.024 12.552 ;
+    END
+  END RW0_rdata[18]
+  PIN RW0_rdata[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.624 0.024 12.648 ;
+    END
+  END RW0_rdata[19]
+  PIN RW0_rdata[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.72 0.024 12.744 ;
+    END
+  END RW0_rdata[20]
+  PIN RW0_rdata[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.816 0.024 12.84 ;
+    END
+  END RW0_rdata[21]
+  PIN RW0_rdata[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.912 0.024 12.936 ;
+    END
+  END RW0_rdata[22]
+  PIN RW0_rdata[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.008 0.024 13.032 ;
+    END
+  END RW0_rdata[23]
+  PIN RW0_rdata[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.104 0.024 13.128 ;
+    END
+  END RW0_rdata[24]
+  PIN RW0_rdata[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.2 0.024 13.224 ;
+    END
+  END RW0_rdata[25]
+  PIN RW0_rdata[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.296 0.024 13.32 ;
+    END
+  END RW0_rdata[26]
+  PIN RW0_rdata[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.392 0.024 13.416 ;
+    END
+  END RW0_rdata[27]
+  PIN RW0_rdata[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.488 0.024 13.512 ;
+    END
+  END RW0_rdata[28]
+  PIN RW0_rdata[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.584 0.024 13.608 ;
+    END
+  END RW0_rdata[29]
+  PIN RW0_rdata[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.68 0.024 13.704 ;
+    END
+  END RW0_rdata[30]
+  PIN RW0_rdata[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.776 0.024 13.8 ;
+    END
+  END RW0_rdata[31]
+  PIN RW0_rdata[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.872 0.024 13.896 ;
+    END
+  END RW0_rdata[32]
+  PIN RW0_rdata[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.968 0.024 13.992 ;
+    END
+  END RW0_rdata[33]
+  PIN RW0_rdata[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.064 0.024 14.088 ;
+    END
+  END RW0_rdata[34]
+  PIN RW0_rdata[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.16 0.024 14.184 ;
+    END
+  END RW0_rdata[35]
+  PIN RW0_rdata[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.256 0.024 14.28 ;
+    END
+  END RW0_rdata[36]
+  PIN RW0_rdata[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.352 0.024 14.376 ;
+    END
+  END RW0_rdata[37]
+  PIN RW0_rdata[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.448 0.024 14.472 ;
+    END
+  END RW0_rdata[38]
+  PIN RW0_rdata[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.544 0.024 14.568 ;
+    END
+  END RW0_rdata[39]
+  PIN RW0_rdata[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.64 0.024 14.664 ;
+    END
+  END RW0_rdata[40]
+  PIN RW0_rdata[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.736 0.024 14.76 ;
+    END
+  END RW0_rdata[41]
+  PIN RW0_rdata[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.832 0.024 14.856 ;
+    END
+  END RW0_rdata[42]
+  PIN RW0_rdata[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.928 0.024 14.952 ;
+    END
+  END RW0_rdata[43]
+  PIN RW0_rdata[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.024 0.024 15.048 ;
+    END
+  END RW0_rdata[44]
+  PIN RW0_rdata[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.12 0.024 15.144 ;
+    END
+  END RW0_rdata[45]
+  PIN RW0_rdata[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.216 0.024 15.24 ;
+    END
+  END RW0_rdata[46]
+  PIN RW0_rdata[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.312 0.024 15.336 ;
+    END
+  END RW0_rdata[47]
+  PIN RW0_rdata[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.408 0.024 15.432 ;
+    END
+  END RW0_rdata[48]
+  PIN RW0_rdata[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.504 0.024 15.528 ;
+    END
+  END RW0_rdata[49]
+  PIN RW0_rdata[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.6 0.024 15.624 ;
+    END
+  END RW0_rdata[50]
+  PIN RW0_rdata[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.696 0.024 15.72 ;
+    END
+  END RW0_rdata[51]
+  PIN RW0_rdata[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.792 0.024 15.816 ;
+    END
+  END RW0_rdata[52]
+  PIN RW0_rdata[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.888 0.024 15.912 ;
+    END
+  END RW0_rdata[53]
+  PIN RW0_rdata[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.984 0.024 16.008 ;
+    END
+  END RW0_rdata[54]
+  PIN RW0_rdata[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.08 0.024 16.104 ;
+    END
+  END RW0_rdata[55]
+  PIN RW0_rdata[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.176 0.024 16.2 ;
+    END
+  END RW0_rdata[56]
+  PIN RW0_rdata[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.272 0.024 16.296 ;
+    END
+  END RW0_rdata[57]
+  PIN RW0_rdata[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.368 0.024 16.392 ;
+    END
+  END RW0_rdata[58]
+  PIN RW0_rdata[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.464 0.024 16.488 ;
+    END
+  END RW0_rdata[59]
+  PIN RW0_rdata[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.56 0.024 16.584 ;
+    END
+  END RW0_rdata[60]
+  PIN RW0_rdata[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.656 0.024 16.68 ;
+    END
+  END RW0_rdata[61]
+  PIN RW0_rdata[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.752 0.024 16.776 ;
+    END
+  END RW0_rdata[62]
+  PIN RW0_rdata[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.848 0.024 16.872 ;
+    END
+  END RW0_rdata[63]
+  PIN RW0_rdata[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.944 0.024 16.968 ;
+    END
+  END RW0_rdata[64]
+  PIN RW0_rdata[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.04 0.024 17.064 ;
+    END
+  END RW0_rdata[65]
+  PIN RW0_rdata[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.136 0.024 17.16 ;
+    END
+  END RW0_rdata[66]
+  PIN RW0_rdata[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.232 0.024 17.256 ;
+    END
+  END RW0_rdata[67]
+  PIN RW0_rdata[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.328 0.024 17.352 ;
+    END
+  END RW0_rdata[68]
+  PIN RW0_rdata[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.424 0.024 17.448 ;
+    END
+  END RW0_rdata[69]
+  PIN RW0_rdata[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.52 0.024 17.544 ;
+    END
+  END RW0_rdata[70]
+  PIN RW0_rdata[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.616 0.024 17.64 ;
+    END
+  END RW0_rdata[71]
+  PIN RW0_rdata[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.712 0.024 17.736 ;
+    END
+  END RW0_rdata[72]
+  PIN RW0_rdata[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.808 0.024 17.832 ;
+    END
+  END RW0_rdata[73]
+  PIN RW0_rdata[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.904 0.024 17.928 ;
+    END
+  END RW0_rdata[74]
+  PIN RW0_rdata[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18 0.024 18.024 ;
+    END
+  END RW0_rdata[75]
+  PIN RW0_rdata[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.096 0.024 18.12 ;
+    END
+  END RW0_rdata[76]
+  PIN RW0_rdata[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.192 0.024 18.216 ;
+    END
+  END RW0_rdata[77]
+  PIN RW0_rdata[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.288 0.024 18.312 ;
+    END
+  END RW0_rdata[78]
+  PIN RW0_rdata[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.384 0.024 18.408 ;
+    END
+  END RW0_rdata[79]
+  PIN RW0_rdata[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.48 0.024 18.504 ;
+    END
+  END RW0_rdata[80]
+  PIN RW0_rdata[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.576 0.024 18.6 ;
+    END
+  END RW0_rdata[81]
+  PIN RW0_rdata[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.672 0.024 18.696 ;
+    END
+  END RW0_rdata[82]
+  PIN RW0_rdata[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.768 0.024 18.792 ;
+    END
+  END RW0_rdata[83]
+  PIN RW0_rdata[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.864 0.024 18.888 ;
+    END
+  END RW0_rdata[84]
+  PIN RW0_rdata[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.96 0.024 18.984 ;
+    END
+  END RW0_rdata[85]
+  PIN RW0_rdata[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.056 0.024 19.08 ;
+    END
+  END RW0_rdata[86]
+  PIN RW0_rdata[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.152 0.024 19.176 ;
+    END
+  END RW0_rdata[87]
+  PIN RW0_rdata[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.248 0.024 19.272 ;
+    END
+  END RW0_rdata[88]
+  PIN RW0_rdata[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.344 0.024 19.368 ;
+    END
+  END RW0_rdata[89]
+  PIN RW0_rdata[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.44 0.024 19.464 ;
+    END
+  END RW0_rdata[90]
+  PIN RW0_rdata[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.536 0.024 19.56 ;
+    END
+  END RW0_rdata[91]
+  PIN RW0_rdata[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.632 0.024 19.656 ;
+    END
+  END RW0_rdata[92]
+  PIN RW0_rdata[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.728 0.024 19.752 ;
+    END
+  END RW0_rdata[93]
+  PIN RW0_rdata[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.824 0.024 19.848 ;
+    END
+  END RW0_rdata[94]
+  PIN RW0_rdata[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.92 0.024 19.944 ;
+    END
+  END RW0_rdata[95]
+  PIN RW0_rdata[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.016 0.024 20.04 ;
+    END
+  END RW0_rdata[96]
+  PIN RW0_rdata[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.112 0.024 20.136 ;
+    END
+  END RW0_rdata[97]
+  PIN RW0_rdata[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.208 0.024 20.232 ;
+    END
+  END RW0_rdata[98]
+  PIN RW0_rdata[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.304 0.024 20.328 ;
+    END
+  END RW0_rdata[99]
+  PIN RW0_rdata[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.4 0.024 20.424 ;
+    END
+  END RW0_rdata[100]
+  PIN RW0_rdata[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.496 0.024 20.52 ;
+    END
+  END RW0_rdata[101]
+  PIN RW0_rdata[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.592 0.024 20.616 ;
+    END
+  END RW0_rdata[102]
+  PIN RW0_rdata[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.688 0.024 20.712 ;
+    END
+  END RW0_rdata[103]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.784 0.024 20.808 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.88 0.024 20.904 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.976 0.024 21 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 21.072 0.024 21.096 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 21.168 0.024 21.192 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 21.264 0.024 21.288 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 21.36 0.024 21.384 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 21.456 0.024 21.48 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 21.552 0.024 21.576 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 21.648 0.024 21.672 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 21.744 0.024 21.768 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0 28.122 0.096 ;
+      RECT 0.048 0.768 28.122 0.864 ;
+      RECT 0.048 1.536 28.122 1.632 ;
+      RECT 0.048 2.304 28.122 2.4 ;
+      RECT 0.048 3.072 28.122 3.168 ;
+      RECT 0.048 3.84 28.122 3.936 ;
+      RECT 0.048 4.608 28.122 4.704 ;
+      RECT 0.048 5.376 28.122 5.472 ;
+      RECT 0.048 6.144 28.122 6.24 ;
+      RECT 0.048 6.912 28.122 7.008 ;
+      RECT 0.048 7.68 28.122 7.776 ;
+      RECT 0.048 8.448 28.122 8.544 ;
+      RECT 0.048 9.216 28.122 9.312 ;
+      RECT 0.048 9.984 28.122 10.08 ;
+      RECT 0.048 10.752 28.122 10.848 ;
+      RECT 0.048 11.52 28.122 11.616 ;
+      RECT 0.048 12.288 28.122 12.384 ;
+      RECT 0.048 13.056 28.122 13.152 ;
+      RECT 0.048 13.824 28.122 13.92 ;
+      RECT 0.048 14.592 28.122 14.688 ;
+      RECT 0.048 15.36 28.122 15.456 ;
+      RECT 0.048 16.128 28.122 16.224 ;
+      RECT 0.048 16.896 28.122 16.992 ;
+      RECT 0.048 17.664 28.122 17.76 ;
+      RECT 0.048 18.432 28.122 18.528 ;
+      RECT 0.048 19.2 28.122 19.296 ;
+      RECT 0.048 19.968 28.122 20.064 ;
+      RECT 0.048 20.736 28.122 20.832 ;
+      RECT 0.048 21.504 28.122 21.6 ;
+      RECT 0.048 22.272 28.122 22.368 ;
+      RECT 0.048 23.04 28.122 23.136 ;
+      RECT 0.048 23.808 28.122 23.904 ;
+      RECT 0.048 24.576 28.122 24.672 ;
+      RECT 0.048 25.344 28.122 25.44 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0.384 28.122 0.48 ;
+      RECT 0.048 1.152 28.122 1.248 ;
+      RECT 0.048 1.92 28.122 2.016 ;
+      RECT 0.048 2.688 28.122 2.784 ;
+      RECT 0.048 3.456 28.122 3.552 ;
+      RECT 0.048 4.224 28.122 4.32 ;
+      RECT 0.048 4.992 28.122 5.088 ;
+      RECT 0.048 5.76 28.122 5.856 ;
+      RECT 0.048 6.528 28.122 6.624 ;
+      RECT 0.048 7.296 28.122 7.392 ;
+      RECT 0.048 8.064 28.122 8.16 ;
+      RECT 0.048 8.832 28.122 8.928 ;
+      RECT 0.048 9.6 28.122 9.696 ;
+      RECT 0.048 10.368 28.122 10.464 ;
+      RECT 0.048 11.136 28.122 11.232 ;
+      RECT 0.048 11.904 28.122 12 ;
+      RECT 0.048 12.672 28.122 12.768 ;
+      RECT 0.048 13.44 28.122 13.536 ;
+      RECT 0.048 14.208 28.122 14.304 ;
+      RECT 0.048 14.976 28.122 15.072 ;
+      RECT 0.048 15.744 28.122 15.84 ;
+      RECT 0.048 16.512 28.122 16.608 ;
+      RECT 0.048 17.28 28.122 17.376 ;
+      RECT 0.048 18.048 28.122 18.144 ;
+      RECT 0.048 18.816 28.122 18.912 ;
+      RECT 0.048 19.584 28.122 19.68 ;
+      RECT 0.048 20.352 28.122 20.448 ;
+      RECT 0.048 21.12 28.122 21.216 ;
+      RECT 0.048 21.888 28.122 21.984 ;
+      RECT 0.048 22.656 28.122 22.752 ;
+      RECT 0.048 23.424 28.122 23.52 ;
+      RECT 0.048 24.192 28.122 24.288 ;
+      RECT 0.048 24.96 28.122 25.056 ;
+      RECT 0.048 25.728 28.122 25.824 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 28.17 26.071 ;
+    LAYER M2 ;
+    RECT 0 0 28.17 26.071 ;
+    LAYER M3 ;
+    RECT 0 0 28.17 26.071 ;
+  END
+END array_256x104
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lef/array_256x13.lef b/flow/platforms/asap7/lef/array_256x13.lef
new file mode 100644
index 0000000000..c61032c189
--- /dev/null
+++ b/flow/platforms/asap7/lef/array_256x13.lef
@@ -0,0 +1,425 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-asap7-fakeram-m4-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x13
+  FOREIGN array_256x13 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 6.221 BY 21.263 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.048 0.024 0.072 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.576 0.024 0.6 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.104 0.024 1.128 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.632 0.024 1.656 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.16 0.024 2.184 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.688 0.024 2.712 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.216 0.024 3.24 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.744 0.024 3.768 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.272 0.024 4.296 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.8 0.024 4.824 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.328 0.024 5.352 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.856 0.024 5.88 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.384 0.024 6.408 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.912 0.024 6.936 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.44 0.024 7.464 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.968 0.024 7.992 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.496 0.024 8.52 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.024 0.024 9.048 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.552 0.024 9.576 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.08 0.024 10.104 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.608 0.024 10.632 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.136 0.024 11.16 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.664 0.024 11.688 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.192 0.024 12.216 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.72 0.024 12.744 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.248 0.024 13.272 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.776 0.024 13.8 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.304 0.024 14.328 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.832 0.024 14.856 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.36 0.024 15.384 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.888 0.024 15.912 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.416 0.024 16.44 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.944 0.024 16.968 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.472 0.024 17.496 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18 0.024 18.024 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.528 0.024 18.552 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.056 0.024 19.08 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0 6.173 0.096 ;
+      RECT 0.048 0.768 6.173 0.864 ;
+      RECT 0.048 1.536 6.173 1.632 ;
+      RECT 0.048 2.304 6.173 2.4 ;
+      RECT 0.048 3.072 6.173 3.168 ;
+      RECT 0.048 3.84 6.173 3.936 ;
+      RECT 0.048 4.608 6.173 4.704 ;
+      RECT 0.048 5.376 6.173 5.472 ;
+      RECT 0.048 6.144 6.173 6.24 ;
+      RECT 0.048 6.912 6.173 7.008 ;
+      RECT 0.048 7.68 6.173 7.776 ;
+      RECT 0.048 8.448 6.173 8.544 ;
+      RECT 0.048 9.216 6.173 9.312 ;
+      RECT 0.048 9.984 6.173 10.08 ;
+      RECT 0.048 10.752 6.173 10.848 ;
+      RECT 0.048 11.52 6.173 11.616 ;
+      RECT 0.048 12.288 6.173 12.384 ;
+      RECT 0.048 13.056 6.173 13.152 ;
+      RECT 0.048 13.824 6.173 13.92 ;
+      RECT 0.048 14.592 6.173 14.688 ;
+      RECT 0.048 15.36 6.173 15.456 ;
+      RECT 0.048 16.128 6.173 16.224 ;
+      RECT 0.048 16.896 6.173 16.992 ;
+      RECT 0.048 17.664 6.173 17.76 ;
+      RECT 0.048 18.432 6.173 18.528 ;
+      RECT 0.048 19.2 6.173 19.296 ;
+      RECT 0.048 19.968 6.173 20.064 ;
+      RECT 0.048 20.736 6.173 20.832 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0.384 6.173 0.48 ;
+      RECT 0.048 1.152 6.173 1.248 ;
+      RECT 0.048 1.92 6.173 2.016 ;
+      RECT 0.048 2.688 6.173 2.784 ;
+      RECT 0.048 3.456 6.173 3.552 ;
+      RECT 0.048 4.224 6.173 4.32 ;
+      RECT 0.048 4.992 6.173 5.088 ;
+      RECT 0.048 5.76 6.173 5.856 ;
+      RECT 0.048 6.528 6.173 6.624 ;
+      RECT 0.048 7.296 6.173 7.392 ;
+      RECT 0.048 8.064 6.173 8.16 ;
+      RECT 0.048 8.832 6.173 8.928 ;
+      RECT 0.048 9.6 6.173 9.696 ;
+      RECT 0.048 10.368 6.173 10.464 ;
+      RECT 0.048 11.136 6.173 11.232 ;
+      RECT 0.048 11.904 6.173 12 ;
+      RECT 0.048 12.672 6.173 12.768 ;
+      RECT 0.048 13.44 6.173 13.536 ;
+      RECT 0.048 14.208 6.173 14.304 ;
+      RECT 0.048 14.976 6.173 15.072 ;
+      RECT 0.048 15.744 6.173 15.84 ;
+      RECT 0.048 16.512 6.173 16.608 ;
+      RECT 0.048 17.28 6.173 17.376 ;
+      RECT 0.048 18.048 6.173 18.144 ;
+      RECT 0.048 18.816 6.173 18.912 ;
+      RECT 0.048 19.584 6.173 19.68 ;
+      RECT 0.048 20.352 6.173 20.448 ;
+      RECT 0.048 21.12 6.173 21.216 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 6.221 21.263 ;
+    LAYER M2 ;
+    RECT 0 0 6.221 21.263 ;
+    LAYER M3 ;
+    RECT 0 0 6.221 21.263 ;
+  END
+END array_256x13
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lef/array_256x16.lef b/flow/platforms/asap7/lef/array_256x16.lef
new file mode 100644
index 0000000000..7272780b2e
--- /dev/null
+++ b/flow/platforms/asap7/lef/array_256x16.lef
@@ -0,0 +1,479 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-asap7-fakeram-m4-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x16
+  FOREIGN array_256x16 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 6.221 BY 21.384 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.048 0.024 0.072 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.528 0.024 0.552 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.008 0.024 1.032 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.488 0.024 1.512 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.968 0.024 1.992 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.448 0.024 2.472 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.928 0.024 2.952 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.408 0.024 3.432 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.888 0.024 3.912 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.368 0.024 4.392 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.848 0.024 4.872 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.328 0.024 5.352 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.808 0.024 5.832 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_wdata[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.288 0.024 6.312 ;
+    END
+  END RW0_wdata[13]
+  PIN RW0_wdata[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.768 0.024 6.792 ;
+    END
+  END RW0_wdata[14]
+  PIN RW0_wdata[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.248 0.024 7.272 ;
+    END
+  END RW0_wdata[15]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.728 0.024 7.752 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.208 0.024 8.232 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.688 0.024 8.712 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.168 0.024 9.192 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.648 0.024 9.672 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.128 0.024 10.152 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.608 0.024 10.632 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.088 0.024 11.112 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.568 0.024 11.592 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.048 0.024 12.072 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.528 0.024 12.552 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.008 0.024 13.032 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.488 0.024 13.512 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_rdata[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.968 0.024 13.992 ;
+    END
+  END RW0_rdata[13]
+  PIN RW0_rdata[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.448 0.024 14.472 ;
+    END
+  END RW0_rdata[14]
+  PIN RW0_rdata[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.928 0.024 14.952 ;
+    END
+  END RW0_rdata[15]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.408 0.024 15.432 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.888 0.024 15.912 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.368 0.024 16.392 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.848 0.024 16.872 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.328 0.024 17.352 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.808 0.024 17.832 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.288 0.024 18.312 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.768 0.024 18.792 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.248 0.024 19.272 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.728 0.024 19.752 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.208 0.024 20.232 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0 6.173 0.096 ;
+      RECT 0.048 0.768 6.173 0.864 ;
+      RECT 0.048 1.536 6.173 1.632 ;
+      RECT 0.048 2.304 6.173 2.4 ;
+      RECT 0.048 3.072 6.173 3.168 ;
+      RECT 0.048 3.84 6.173 3.936 ;
+      RECT 0.048 4.608 6.173 4.704 ;
+      RECT 0.048 5.376 6.173 5.472 ;
+      RECT 0.048 6.144 6.173 6.24 ;
+      RECT 0.048 6.912 6.173 7.008 ;
+      RECT 0.048 7.68 6.173 7.776 ;
+      RECT 0.048 8.448 6.173 8.544 ;
+      RECT 0.048 9.216 6.173 9.312 ;
+      RECT 0.048 9.984 6.173 10.08 ;
+      RECT 0.048 10.752 6.173 10.848 ;
+      RECT 0.048 11.52 6.173 11.616 ;
+      RECT 0.048 12.288 6.173 12.384 ;
+      RECT 0.048 13.056 6.173 13.152 ;
+      RECT 0.048 13.824 6.173 13.92 ;
+      RECT 0.048 14.592 6.173 14.688 ;
+      RECT 0.048 15.36 6.173 15.456 ;
+      RECT 0.048 16.128 6.173 16.224 ;
+      RECT 0.048 16.896 6.173 16.992 ;
+      RECT 0.048 17.664 6.173 17.76 ;
+      RECT 0.048 18.432 6.173 18.528 ;
+      RECT 0.048 19.2 6.173 19.296 ;
+      RECT 0.048 19.968 6.173 20.064 ;
+      RECT 0.048 20.736 6.173 20.832 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0.384 6.173 0.48 ;
+      RECT 0.048 1.152 6.173 1.248 ;
+      RECT 0.048 1.92 6.173 2.016 ;
+      RECT 0.048 2.688 6.173 2.784 ;
+      RECT 0.048 3.456 6.173 3.552 ;
+      RECT 0.048 4.224 6.173 4.32 ;
+      RECT 0.048 4.992 6.173 5.088 ;
+      RECT 0.048 5.76 6.173 5.856 ;
+      RECT 0.048 6.528 6.173 6.624 ;
+      RECT 0.048 7.296 6.173 7.392 ;
+      RECT 0.048 8.064 6.173 8.16 ;
+      RECT 0.048 8.832 6.173 8.928 ;
+      RECT 0.048 9.6 6.173 9.696 ;
+      RECT 0.048 10.368 6.173 10.464 ;
+      RECT 0.048 11.136 6.173 11.232 ;
+      RECT 0.048 11.904 6.173 12 ;
+      RECT 0.048 12.672 6.173 12.768 ;
+      RECT 0.048 13.44 6.173 13.536 ;
+      RECT 0.048 14.208 6.173 14.304 ;
+      RECT 0.048 14.976 6.173 15.072 ;
+      RECT 0.048 15.744 6.173 15.84 ;
+      RECT 0.048 16.512 6.173 16.608 ;
+      RECT 0.048 17.28 6.173 17.376 ;
+      RECT 0.048 18.048 6.173 18.144 ;
+      RECT 0.048 18.816 6.173 18.912 ;
+      RECT 0.048 19.584 6.173 19.68 ;
+      RECT 0.048 20.352 6.173 20.448 ;
+      RECT 0.048 21.12 6.173 21.216 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 6.221 21.384 ;
+    LAYER M2 ;
+    RECT 0 0 6.221 21.384 ;
+    LAYER M3 ;
+    RECT 0 0 6.221 21.384 ;
+  END
+END array_256x16
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lef/array_256x164.lef b/flow/platforms/asap7/lef/array_256x164.lef
new file mode 100644
index 0000000000..397f715ef2
--- /dev/null
+++ b/flow/platforms/asap7/lef/array_256x164.lef
@@ -0,0 +1,3198 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-asap7-fakeram-m4-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x164
+  FOREIGN array_256x164 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 44.422 BY 28.611 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wmask[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.048 0.024 0.072 ;
+    END
+  END RW0_wmask[0]
+  PIN RW0_wmask[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.096 0.024 0.12 ;
+    END
+  END RW0_wmask[1]
+  PIN RW0_wmask[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.144 0.024 0.168 ;
+    END
+  END RW0_wmask[2]
+  PIN RW0_wmask[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.192 0.024 0.216 ;
+    END
+  END RW0_wmask[3]
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.24 0.024 0.264 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.288 0.024 0.312 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.336 0.024 0.36 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.384 0.024 0.408 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.432 0.024 0.456 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.48 0.024 0.504 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.528 0.024 0.552 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.576 0.024 0.6 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.624 0.024 0.648 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.672 0.024 0.696 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.72 0.024 0.744 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.768 0.024 0.792 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.816 0.024 0.84 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_wdata[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.864 0.024 0.888 ;
+    END
+  END RW0_wdata[13]
+  PIN RW0_wdata[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.912 0.024 0.936 ;
+    END
+  END RW0_wdata[14]
+  PIN RW0_wdata[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.96 0.024 0.984 ;
+    END
+  END RW0_wdata[15]
+  PIN RW0_wdata[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.008 0.024 1.032 ;
+    END
+  END RW0_wdata[16]
+  PIN RW0_wdata[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.056 0.024 1.08 ;
+    END
+  END RW0_wdata[17]
+  PIN RW0_wdata[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.104 0.024 1.128 ;
+    END
+  END RW0_wdata[18]
+  PIN RW0_wdata[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.152 0.024 1.176 ;
+    END
+  END RW0_wdata[19]
+  PIN RW0_wdata[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.2 0.024 1.224 ;
+    END
+  END RW0_wdata[20]
+  PIN RW0_wdata[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.248 0.024 1.272 ;
+    END
+  END RW0_wdata[21]
+  PIN RW0_wdata[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.296 0.024 1.32 ;
+    END
+  END RW0_wdata[22]
+  PIN RW0_wdata[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.344 0.024 1.368 ;
+    END
+  END RW0_wdata[23]
+  PIN RW0_wdata[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.392 0.024 1.416 ;
+    END
+  END RW0_wdata[24]
+  PIN RW0_wdata[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.44 0.024 1.464 ;
+    END
+  END RW0_wdata[25]
+  PIN RW0_wdata[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.488 0.024 1.512 ;
+    END
+  END RW0_wdata[26]
+  PIN RW0_wdata[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.536 0.024 1.56 ;
+    END
+  END RW0_wdata[27]
+  PIN RW0_wdata[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.584 0.024 1.608 ;
+    END
+  END RW0_wdata[28]
+  PIN RW0_wdata[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.632 0.024 1.656 ;
+    END
+  END RW0_wdata[29]
+  PIN RW0_wdata[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.68 0.024 1.704 ;
+    END
+  END RW0_wdata[30]
+  PIN RW0_wdata[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.728 0.024 1.752 ;
+    END
+  END RW0_wdata[31]
+  PIN RW0_wdata[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.776 0.024 1.8 ;
+    END
+  END RW0_wdata[32]
+  PIN RW0_wdata[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.824 0.024 1.848 ;
+    END
+  END RW0_wdata[33]
+  PIN RW0_wdata[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.872 0.024 1.896 ;
+    END
+  END RW0_wdata[34]
+  PIN RW0_wdata[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.92 0.024 1.944 ;
+    END
+  END RW0_wdata[35]
+  PIN RW0_wdata[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.968 0.024 1.992 ;
+    END
+  END RW0_wdata[36]
+  PIN RW0_wdata[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.016 0.024 2.04 ;
+    END
+  END RW0_wdata[37]
+  PIN RW0_wdata[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.064 0.024 2.088 ;
+    END
+  END RW0_wdata[38]
+  PIN RW0_wdata[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.112 0.024 2.136 ;
+    END
+  END RW0_wdata[39]
+  PIN RW0_wdata[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.16 0.024 2.184 ;
+    END
+  END RW0_wdata[40]
+  PIN RW0_wdata[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.208 0.024 2.232 ;
+    END
+  END RW0_wdata[41]
+  PIN RW0_wdata[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.256 0.024 2.28 ;
+    END
+  END RW0_wdata[42]
+  PIN RW0_wdata[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.304 0.024 2.328 ;
+    END
+  END RW0_wdata[43]
+  PIN RW0_wdata[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.352 0.024 2.376 ;
+    END
+  END RW0_wdata[44]
+  PIN RW0_wdata[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.4 0.024 2.424 ;
+    END
+  END RW0_wdata[45]
+  PIN RW0_wdata[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.448 0.024 2.472 ;
+    END
+  END RW0_wdata[46]
+  PIN RW0_wdata[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.496 0.024 2.52 ;
+    END
+  END RW0_wdata[47]
+  PIN RW0_wdata[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.544 0.024 2.568 ;
+    END
+  END RW0_wdata[48]
+  PIN RW0_wdata[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.592 0.024 2.616 ;
+    END
+  END RW0_wdata[49]
+  PIN RW0_wdata[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.64 0.024 2.664 ;
+    END
+  END RW0_wdata[50]
+  PIN RW0_wdata[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.688 0.024 2.712 ;
+    END
+  END RW0_wdata[51]
+  PIN RW0_wdata[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.736 0.024 2.76 ;
+    END
+  END RW0_wdata[52]
+  PIN RW0_wdata[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.784 0.024 2.808 ;
+    END
+  END RW0_wdata[53]
+  PIN RW0_wdata[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.832 0.024 2.856 ;
+    END
+  END RW0_wdata[54]
+  PIN RW0_wdata[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.88 0.024 2.904 ;
+    END
+  END RW0_wdata[55]
+  PIN RW0_wdata[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.928 0.024 2.952 ;
+    END
+  END RW0_wdata[56]
+  PIN RW0_wdata[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.976 0.024 3 ;
+    END
+  END RW0_wdata[57]
+  PIN RW0_wdata[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.024 0.024 3.048 ;
+    END
+  END RW0_wdata[58]
+  PIN RW0_wdata[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.072 0.024 3.096 ;
+    END
+  END RW0_wdata[59]
+  PIN RW0_wdata[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.12 0.024 3.144 ;
+    END
+  END RW0_wdata[60]
+  PIN RW0_wdata[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.168 0.024 3.192 ;
+    END
+  END RW0_wdata[61]
+  PIN RW0_wdata[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.216 0.024 3.24 ;
+    END
+  END RW0_wdata[62]
+  PIN RW0_wdata[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.264 0.024 3.288 ;
+    END
+  END RW0_wdata[63]
+  PIN RW0_wdata[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.312 0.024 3.336 ;
+    END
+  END RW0_wdata[64]
+  PIN RW0_wdata[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.36 0.024 3.384 ;
+    END
+  END RW0_wdata[65]
+  PIN RW0_wdata[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.408 0.024 3.432 ;
+    END
+  END RW0_wdata[66]
+  PIN RW0_wdata[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.456 0.024 3.48 ;
+    END
+  END RW0_wdata[67]
+  PIN RW0_wdata[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.504 0.024 3.528 ;
+    END
+  END RW0_wdata[68]
+  PIN RW0_wdata[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.552 0.024 3.576 ;
+    END
+  END RW0_wdata[69]
+  PIN RW0_wdata[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.6 0.024 3.624 ;
+    END
+  END RW0_wdata[70]
+  PIN RW0_wdata[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.648 0.024 3.672 ;
+    END
+  END RW0_wdata[71]
+  PIN RW0_wdata[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.696 0.024 3.72 ;
+    END
+  END RW0_wdata[72]
+  PIN RW0_wdata[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.744 0.024 3.768 ;
+    END
+  END RW0_wdata[73]
+  PIN RW0_wdata[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.792 0.024 3.816 ;
+    END
+  END RW0_wdata[74]
+  PIN RW0_wdata[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.84 0.024 3.864 ;
+    END
+  END RW0_wdata[75]
+  PIN RW0_wdata[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.888 0.024 3.912 ;
+    END
+  END RW0_wdata[76]
+  PIN RW0_wdata[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.936 0.024 3.96 ;
+    END
+  END RW0_wdata[77]
+  PIN RW0_wdata[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.984 0.024 4.008 ;
+    END
+  END RW0_wdata[78]
+  PIN RW0_wdata[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.032 0.024 4.056 ;
+    END
+  END RW0_wdata[79]
+  PIN RW0_wdata[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.08 0.024 4.104 ;
+    END
+  END RW0_wdata[80]
+  PIN RW0_wdata[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.128 0.024 4.152 ;
+    END
+  END RW0_wdata[81]
+  PIN RW0_wdata[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.176 0.024 4.2 ;
+    END
+  END RW0_wdata[82]
+  PIN RW0_wdata[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.224 0.024 4.248 ;
+    END
+  END RW0_wdata[83]
+  PIN RW0_wdata[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.272 0.024 4.296 ;
+    END
+  END RW0_wdata[84]
+  PIN RW0_wdata[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.32 0.024 4.344 ;
+    END
+  END RW0_wdata[85]
+  PIN RW0_wdata[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.368 0.024 4.392 ;
+    END
+  END RW0_wdata[86]
+  PIN RW0_wdata[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.416 0.024 4.44 ;
+    END
+  END RW0_wdata[87]
+  PIN RW0_wdata[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.464 0.024 4.488 ;
+    END
+  END RW0_wdata[88]
+  PIN RW0_wdata[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.512 0.024 4.536 ;
+    END
+  END RW0_wdata[89]
+  PIN RW0_wdata[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.56 0.024 4.584 ;
+    END
+  END RW0_wdata[90]
+  PIN RW0_wdata[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.608 0.024 4.632 ;
+    END
+  END RW0_wdata[91]
+  PIN RW0_wdata[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.656 0.024 4.68 ;
+    END
+  END RW0_wdata[92]
+  PIN RW0_wdata[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.704 0.024 4.728 ;
+    END
+  END RW0_wdata[93]
+  PIN RW0_wdata[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.752 0.024 4.776 ;
+    END
+  END RW0_wdata[94]
+  PIN RW0_wdata[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.8 0.024 4.824 ;
+    END
+  END RW0_wdata[95]
+  PIN RW0_wdata[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.848 0.024 4.872 ;
+    END
+  END RW0_wdata[96]
+  PIN RW0_wdata[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.896 0.024 4.92 ;
+    END
+  END RW0_wdata[97]
+  PIN RW0_wdata[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.944 0.024 4.968 ;
+    END
+  END RW0_wdata[98]
+  PIN RW0_wdata[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.992 0.024 5.016 ;
+    END
+  END RW0_wdata[99]
+  PIN RW0_wdata[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.04 0.024 5.064 ;
+    END
+  END RW0_wdata[100]
+  PIN RW0_wdata[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.088 0.024 5.112 ;
+    END
+  END RW0_wdata[101]
+  PIN RW0_wdata[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.136 0.024 5.16 ;
+    END
+  END RW0_wdata[102]
+  PIN RW0_wdata[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.184 0.024 5.208 ;
+    END
+  END RW0_wdata[103]
+  PIN RW0_wdata[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.232 0.024 5.256 ;
+    END
+  END RW0_wdata[104]
+  PIN RW0_wdata[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.28 0.024 5.304 ;
+    END
+  END RW0_wdata[105]
+  PIN RW0_wdata[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.328 0.024 5.352 ;
+    END
+  END RW0_wdata[106]
+  PIN RW0_wdata[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.376 0.024 5.4 ;
+    END
+  END RW0_wdata[107]
+  PIN RW0_wdata[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.424 0.024 5.448 ;
+    END
+  END RW0_wdata[108]
+  PIN RW0_wdata[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.472 0.024 5.496 ;
+    END
+  END RW0_wdata[109]
+  PIN RW0_wdata[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.52 0.024 5.544 ;
+    END
+  END RW0_wdata[110]
+  PIN RW0_wdata[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.568 0.024 5.592 ;
+    END
+  END RW0_wdata[111]
+  PIN RW0_wdata[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.616 0.024 5.64 ;
+    END
+  END RW0_wdata[112]
+  PIN RW0_wdata[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.664 0.024 5.688 ;
+    END
+  END RW0_wdata[113]
+  PIN RW0_wdata[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.712 0.024 5.736 ;
+    END
+  END RW0_wdata[114]
+  PIN RW0_wdata[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.76 0.024 5.784 ;
+    END
+  END RW0_wdata[115]
+  PIN RW0_wdata[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.808 0.024 5.832 ;
+    END
+  END RW0_wdata[116]
+  PIN RW0_wdata[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.856 0.024 5.88 ;
+    END
+  END RW0_wdata[117]
+  PIN RW0_wdata[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.904 0.024 5.928 ;
+    END
+  END RW0_wdata[118]
+  PIN RW0_wdata[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.952 0.024 5.976 ;
+    END
+  END RW0_wdata[119]
+  PIN RW0_wdata[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6 0.024 6.024 ;
+    END
+  END RW0_wdata[120]
+  PIN RW0_wdata[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.048 0.024 6.072 ;
+    END
+  END RW0_wdata[121]
+  PIN RW0_wdata[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.096 0.024 6.12 ;
+    END
+  END RW0_wdata[122]
+  PIN RW0_wdata[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.144 0.024 6.168 ;
+    END
+  END RW0_wdata[123]
+  PIN RW0_wdata[124]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.192 0.024 6.216 ;
+    END
+  END RW0_wdata[124]
+  PIN RW0_wdata[125]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.24 0.024 6.264 ;
+    END
+  END RW0_wdata[125]
+  PIN RW0_wdata[126]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.288 0.024 6.312 ;
+    END
+  END RW0_wdata[126]
+  PIN RW0_wdata[127]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.336 0.024 6.36 ;
+    END
+  END RW0_wdata[127]
+  PIN RW0_wdata[128]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.384 0.024 6.408 ;
+    END
+  END RW0_wdata[128]
+  PIN RW0_wdata[129]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.432 0.024 6.456 ;
+    END
+  END RW0_wdata[129]
+  PIN RW0_wdata[130]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.48 0.024 6.504 ;
+    END
+  END RW0_wdata[130]
+  PIN RW0_wdata[131]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.528 0.024 6.552 ;
+    END
+  END RW0_wdata[131]
+  PIN RW0_wdata[132]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.576 0.024 6.6 ;
+    END
+  END RW0_wdata[132]
+  PIN RW0_wdata[133]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.624 0.024 6.648 ;
+    END
+  END RW0_wdata[133]
+  PIN RW0_wdata[134]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.672 0.024 6.696 ;
+    END
+  END RW0_wdata[134]
+  PIN RW0_wdata[135]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.72 0.024 6.744 ;
+    END
+  END RW0_wdata[135]
+  PIN RW0_wdata[136]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.768 0.024 6.792 ;
+    END
+  END RW0_wdata[136]
+  PIN RW0_wdata[137]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.816 0.024 6.84 ;
+    END
+  END RW0_wdata[137]
+  PIN RW0_wdata[138]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.864 0.024 6.888 ;
+    END
+  END RW0_wdata[138]
+  PIN RW0_wdata[139]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.912 0.024 6.936 ;
+    END
+  END RW0_wdata[139]
+  PIN RW0_wdata[140]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.96 0.024 6.984 ;
+    END
+  END RW0_wdata[140]
+  PIN RW0_wdata[141]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.008 0.024 7.032 ;
+    END
+  END RW0_wdata[141]
+  PIN RW0_wdata[142]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.056 0.024 7.08 ;
+    END
+  END RW0_wdata[142]
+  PIN RW0_wdata[143]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.104 0.024 7.128 ;
+    END
+  END RW0_wdata[143]
+  PIN RW0_wdata[144]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.152 0.024 7.176 ;
+    END
+  END RW0_wdata[144]
+  PIN RW0_wdata[145]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.2 0.024 7.224 ;
+    END
+  END RW0_wdata[145]
+  PIN RW0_wdata[146]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.248 0.024 7.272 ;
+    END
+  END RW0_wdata[146]
+  PIN RW0_wdata[147]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.296 0.024 7.32 ;
+    END
+  END RW0_wdata[147]
+  PIN RW0_wdata[148]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.344 0.024 7.368 ;
+    END
+  END RW0_wdata[148]
+  PIN RW0_wdata[149]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.392 0.024 7.416 ;
+    END
+  END RW0_wdata[149]
+  PIN RW0_wdata[150]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.44 0.024 7.464 ;
+    END
+  END RW0_wdata[150]
+  PIN RW0_wdata[151]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.488 0.024 7.512 ;
+    END
+  END RW0_wdata[151]
+  PIN RW0_wdata[152]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.536 0.024 7.56 ;
+    END
+  END RW0_wdata[152]
+  PIN RW0_wdata[153]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.584 0.024 7.608 ;
+    END
+  END RW0_wdata[153]
+  PIN RW0_wdata[154]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.632 0.024 7.656 ;
+    END
+  END RW0_wdata[154]
+  PIN RW0_wdata[155]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.68 0.024 7.704 ;
+    END
+  END RW0_wdata[155]
+  PIN RW0_wdata[156]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.728 0.024 7.752 ;
+    END
+  END RW0_wdata[156]
+  PIN RW0_wdata[157]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.776 0.024 7.8 ;
+    END
+  END RW0_wdata[157]
+  PIN RW0_wdata[158]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.824 0.024 7.848 ;
+    END
+  END RW0_wdata[158]
+  PIN RW0_wdata[159]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.872 0.024 7.896 ;
+    END
+  END RW0_wdata[159]
+  PIN RW0_wdata[160]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.92 0.024 7.944 ;
+    END
+  END RW0_wdata[160]
+  PIN RW0_wdata[161]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.968 0.024 7.992 ;
+    END
+  END RW0_wdata[161]
+  PIN RW0_wdata[162]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.016 0.024 8.04 ;
+    END
+  END RW0_wdata[162]
+  PIN RW0_wdata[163]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.064 0.024 8.088 ;
+    END
+  END RW0_wdata[163]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.112 0.024 8.136 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.16 0.024 8.184 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.208 0.024 8.232 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.256 0.024 8.28 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.304 0.024 8.328 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.352 0.024 8.376 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.4 0.024 8.424 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.448 0.024 8.472 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.496 0.024 8.52 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.544 0.024 8.568 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.592 0.024 8.616 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.64 0.024 8.664 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.688 0.024 8.712 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_rdata[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.736 0.024 8.76 ;
+    END
+  END RW0_rdata[13]
+  PIN RW0_rdata[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.784 0.024 8.808 ;
+    END
+  END RW0_rdata[14]
+  PIN RW0_rdata[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.832 0.024 8.856 ;
+    END
+  END RW0_rdata[15]
+  PIN RW0_rdata[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.88 0.024 8.904 ;
+    END
+  END RW0_rdata[16]
+  PIN RW0_rdata[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.928 0.024 8.952 ;
+    END
+  END RW0_rdata[17]
+  PIN RW0_rdata[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.976 0.024 9 ;
+    END
+  END RW0_rdata[18]
+  PIN RW0_rdata[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.024 0.024 9.048 ;
+    END
+  END RW0_rdata[19]
+  PIN RW0_rdata[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.072 0.024 9.096 ;
+    END
+  END RW0_rdata[20]
+  PIN RW0_rdata[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.12 0.024 9.144 ;
+    END
+  END RW0_rdata[21]
+  PIN RW0_rdata[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.168 0.024 9.192 ;
+    END
+  END RW0_rdata[22]
+  PIN RW0_rdata[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.216 0.024 9.24 ;
+    END
+  END RW0_rdata[23]
+  PIN RW0_rdata[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.264 0.024 9.288 ;
+    END
+  END RW0_rdata[24]
+  PIN RW0_rdata[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.312 0.024 9.336 ;
+    END
+  END RW0_rdata[25]
+  PIN RW0_rdata[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.36 0.024 9.384 ;
+    END
+  END RW0_rdata[26]
+  PIN RW0_rdata[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.408 0.024 9.432 ;
+    END
+  END RW0_rdata[27]
+  PIN RW0_rdata[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.456 0.024 9.48 ;
+    END
+  END RW0_rdata[28]
+  PIN RW0_rdata[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.504 0.024 9.528 ;
+    END
+  END RW0_rdata[29]
+  PIN RW0_rdata[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.552 0.024 9.576 ;
+    END
+  END RW0_rdata[30]
+  PIN RW0_rdata[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.6 0.024 9.624 ;
+    END
+  END RW0_rdata[31]
+  PIN RW0_rdata[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.648 0.024 9.672 ;
+    END
+  END RW0_rdata[32]
+  PIN RW0_rdata[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.696 0.024 9.72 ;
+    END
+  END RW0_rdata[33]
+  PIN RW0_rdata[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.744 0.024 9.768 ;
+    END
+  END RW0_rdata[34]
+  PIN RW0_rdata[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.792 0.024 9.816 ;
+    END
+  END RW0_rdata[35]
+  PIN RW0_rdata[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.84 0.024 9.864 ;
+    END
+  END RW0_rdata[36]
+  PIN RW0_rdata[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.888 0.024 9.912 ;
+    END
+  END RW0_rdata[37]
+  PIN RW0_rdata[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.936 0.024 9.96 ;
+    END
+  END RW0_rdata[38]
+  PIN RW0_rdata[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.984 0.024 10.008 ;
+    END
+  END RW0_rdata[39]
+  PIN RW0_rdata[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.032 0.024 10.056 ;
+    END
+  END RW0_rdata[40]
+  PIN RW0_rdata[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.08 0.024 10.104 ;
+    END
+  END RW0_rdata[41]
+  PIN RW0_rdata[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.128 0.024 10.152 ;
+    END
+  END RW0_rdata[42]
+  PIN RW0_rdata[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.176 0.024 10.2 ;
+    END
+  END RW0_rdata[43]
+  PIN RW0_rdata[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.224 0.024 10.248 ;
+    END
+  END RW0_rdata[44]
+  PIN RW0_rdata[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.272 0.024 10.296 ;
+    END
+  END RW0_rdata[45]
+  PIN RW0_rdata[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.32 0.024 10.344 ;
+    END
+  END RW0_rdata[46]
+  PIN RW0_rdata[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.368 0.024 10.392 ;
+    END
+  END RW0_rdata[47]
+  PIN RW0_rdata[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.416 0.024 10.44 ;
+    END
+  END RW0_rdata[48]
+  PIN RW0_rdata[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.464 0.024 10.488 ;
+    END
+  END RW0_rdata[49]
+  PIN RW0_rdata[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.512 0.024 10.536 ;
+    END
+  END RW0_rdata[50]
+  PIN RW0_rdata[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.56 0.024 10.584 ;
+    END
+  END RW0_rdata[51]
+  PIN RW0_rdata[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.608 0.024 10.632 ;
+    END
+  END RW0_rdata[52]
+  PIN RW0_rdata[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.656 0.024 10.68 ;
+    END
+  END RW0_rdata[53]
+  PIN RW0_rdata[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.704 0.024 10.728 ;
+    END
+  END RW0_rdata[54]
+  PIN RW0_rdata[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.752 0.024 10.776 ;
+    END
+  END RW0_rdata[55]
+  PIN RW0_rdata[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.8 0.024 10.824 ;
+    END
+  END RW0_rdata[56]
+  PIN RW0_rdata[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.848 0.024 10.872 ;
+    END
+  END RW0_rdata[57]
+  PIN RW0_rdata[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.896 0.024 10.92 ;
+    END
+  END RW0_rdata[58]
+  PIN RW0_rdata[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.944 0.024 10.968 ;
+    END
+  END RW0_rdata[59]
+  PIN RW0_rdata[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.992 0.024 11.016 ;
+    END
+  END RW0_rdata[60]
+  PIN RW0_rdata[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.04 0.024 11.064 ;
+    END
+  END RW0_rdata[61]
+  PIN RW0_rdata[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.088 0.024 11.112 ;
+    END
+  END RW0_rdata[62]
+  PIN RW0_rdata[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.136 0.024 11.16 ;
+    END
+  END RW0_rdata[63]
+  PIN RW0_rdata[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.184 0.024 11.208 ;
+    END
+  END RW0_rdata[64]
+  PIN RW0_rdata[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.232 0.024 11.256 ;
+    END
+  END RW0_rdata[65]
+  PIN RW0_rdata[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.28 0.024 11.304 ;
+    END
+  END RW0_rdata[66]
+  PIN RW0_rdata[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.328 0.024 11.352 ;
+    END
+  END RW0_rdata[67]
+  PIN RW0_rdata[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.376 0.024 11.4 ;
+    END
+  END RW0_rdata[68]
+  PIN RW0_rdata[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.424 0.024 11.448 ;
+    END
+  END RW0_rdata[69]
+  PIN RW0_rdata[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.472 0.024 11.496 ;
+    END
+  END RW0_rdata[70]
+  PIN RW0_rdata[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.52 0.024 11.544 ;
+    END
+  END RW0_rdata[71]
+  PIN RW0_rdata[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.568 0.024 11.592 ;
+    END
+  END RW0_rdata[72]
+  PIN RW0_rdata[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.616 0.024 11.64 ;
+    END
+  END RW0_rdata[73]
+  PIN RW0_rdata[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.664 0.024 11.688 ;
+    END
+  END RW0_rdata[74]
+  PIN RW0_rdata[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.712 0.024 11.736 ;
+    END
+  END RW0_rdata[75]
+  PIN RW0_rdata[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.76 0.024 11.784 ;
+    END
+  END RW0_rdata[76]
+  PIN RW0_rdata[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.808 0.024 11.832 ;
+    END
+  END RW0_rdata[77]
+  PIN RW0_rdata[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.856 0.024 11.88 ;
+    END
+  END RW0_rdata[78]
+  PIN RW0_rdata[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.904 0.024 11.928 ;
+    END
+  END RW0_rdata[79]
+  PIN RW0_rdata[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.952 0.024 11.976 ;
+    END
+  END RW0_rdata[80]
+  PIN RW0_rdata[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12 0.024 12.024 ;
+    END
+  END RW0_rdata[81]
+  PIN RW0_rdata[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.048 0.024 12.072 ;
+    END
+  END RW0_rdata[82]
+  PIN RW0_rdata[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.096 0.024 12.12 ;
+    END
+  END RW0_rdata[83]
+  PIN RW0_rdata[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.144 0.024 12.168 ;
+    END
+  END RW0_rdata[84]
+  PIN RW0_rdata[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.192 0.024 12.216 ;
+    END
+  END RW0_rdata[85]
+  PIN RW0_rdata[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.24 0.024 12.264 ;
+    END
+  END RW0_rdata[86]
+  PIN RW0_rdata[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.288 0.024 12.312 ;
+    END
+  END RW0_rdata[87]
+  PIN RW0_rdata[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.336 0.024 12.36 ;
+    END
+  END RW0_rdata[88]
+  PIN RW0_rdata[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.384 0.024 12.408 ;
+    END
+  END RW0_rdata[89]
+  PIN RW0_rdata[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.432 0.024 12.456 ;
+    END
+  END RW0_rdata[90]
+  PIN RW0_rdata[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.48 0.024 12.504 ;
+    END
+  END RW0_rdata[91]
+  PIN RW0_rdata[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.528 0.024 12.552 ;
+    END
+  END RW0_rdata[92]
+  PIN RW0_rdata[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.576 0.024 12.6 ;
+    END
+  END RW0_rdata[93]
+  PIN RW0_rdata[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.624 0.024 12.648 ;
+    END
+  END RW0_rdata[94]
+  PIN RW0_rdata[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.672 0.024 12.696 ;
+    END
+  END RW0_rdata[95]
+  PIN RW0_rdata[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.72 0.024 12.744 ;
+    END
+  END RW0_rdata[96]
+  PIN RW0_rdata[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.768 0.024 12.792 ;
+    END
+  END RW0_rdata[97]
+  PIN RW0_rdata[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.816 0.024 12.84 ;
+    END
+  END RW0_rdata[98]
+  PIN RW0_rdata[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.864 0.024 12.888 ;
+    END
+  END RW0_rdata[99]
+  PIN RW0_rdata[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.912 0.024 12.936 ;
+    END
+  END RW0_rdata[100]
+  PIN RW0_rdata[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.96 0.024 12.984 ;
+    END
+  END RW0_rdata[101]
+  PIN RW0_rdata[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.008 0.024 13.032 ;
+    END
+  END RW0_rdata[102]
+  PIN RW0_rdata[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.056 0.024 13.08 ;
+    END
+  END RW0_rdata[103]
+  PIN RW0_rdata[104]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.104 0.024 13.128 ;
+    END
+  END RW0_rdata[104]
+  PIN RW0_rdata[105]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.152 0.024 13.176 ;
+    END
+  END RW0_rdata[105]
+  PIN RW0_rdata[106]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.2 0.024 13.224 ;
+    END
+  END RW0_rdata[106]
+  PIN RW0_rdata[107]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.248 0.024 13.272 ;
+    END
+  END RW0_rdata[107]
+  PIN RW0_rdata[108]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.296 0.024 13.32 ;
+    END
+  END RW0_rdata[108]
+  PIN RW0_rdata[109]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.344 0.024 13.368 ;
+    END
+  END RW0_rdata[109]
+  PIN RW0_rdata[110]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.392 0.024 13.416 ;
+    END
+  END RW0_rdata[110]
+  PIN RW0_rdata[111]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.44 0.024 13.464 ;
+    END
+  END RW0_rdata[111]
+  PIN RW0_rdata[112]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.488 0.024 13.512 ;
+    END
+  END RW0_rdata[112]
+  PIN RW0_rdata[113]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.536 0.024 13.56 ;
+    END
+  END RW0_rdata[113]
+  PIN RW0_rdata[114]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.584 0.024 13.608 ;
+    END
+  END RW0_rdata[114]
+  PIN RW0_rdata[115]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.632 0.024 13.656 ;
+    END
+  END RW0_rdata[115]
+  PIN RW0_rdata[116]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.68 0.024 13.704 ;
+    END
+  END RW0_rdata[116]
+  PIN RW0_rdata[117]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.728 0.024 13.752 ;
+    END
+  END RW0_rdata[117]
+  PIN RW0_rdata[118]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.776 0.024 13.8 ;
+    END
+  END RW0_rdata[118]
+  PIN RW0_rdata[119]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.824 0.024 13.848 ;
+    END
+  END RW0_rdata[119]
+  PIN RW0_rdata[120]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.872 0.024 13.896 ;
+    END
+  END RW0_rdata[120]
+  PIN RW0_rdata[121]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.92 0.024 13.944 ;
+    END
+  END RW0_rdata[121]
+  PIN RW0_rdata[122]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.968 0.024 13.992 ;
+    END
+  END RW0_rdata[122]
+  PIN RW0_rdata[123]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.016 0.024 14.04 ;
+    END
+  END RW0_rdata[123]
+  PIN RW0_rdata[124]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.064 0.024 14.088 ;
+    END
+  END RW0_rdata[124]
+  PIN RW0_rdata[125]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.112 0.024 14.136 ;
+    END
+  END RW0_rdata[125]
+  PIN RW0_rdata[126]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.16 0.024 14.184 ;
+    END
+  END RW0_rdata[126]
+  PIN RW0_rdata[127]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.208 0.024 14.232 ;
+    END
+  END RW0_rdata[127]
+  PIN RW0_rdata[128]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.256 0.024 14.28 ;
+    END
+  END RW0_rdata[128]
+  PIN RW0_rdata[129]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.304 0.024 14.328 ;
+    END
+  END RW0_rdata[129]
+  PIN RW0_rdata[130]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.352 0.024 14.376 ;
+    END
+  END RW0_rdata[130]
+  PIN RW0_rdata[131]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.4 0.024 14.424 ;
+    END
+  END RW0_rdata[131]
+  PIN RW0_rdata[132]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.448 0.024 14.472 ;
+    END
+  END RW0_rdata[132]
+  PIN RW0_rdata[133]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.496 0.024 14.52 ;
+    END
+  END RW0_rdata[133]
+  PIN RW0_rdata[134]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.544 0.024 14.568 ;
+    END
+  END RW0_rdata[134]
+  PIN RW0_rdata[135]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.592 0.024 14.616 ;
+    END
+  END RW0_rdata[135]
+  PIN RW0_rdata[136]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.64 0.024 14.664 ;
+    END
+  END RW0_rdata[136]
+  PIN RW0_rdata[137]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.688 0.024 14.712 ;
+    END
+  END RW0_rdata[137]
+  PIN RW0_rdata[138]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.736 0.024 14.76 ;
+    END
+  END RW0_rdata[138]
+  PIN RW0_rdata[139]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.784 0.024 14.808 ;
+    END
+  END RW0_rdata[139]
+  PIN RW0_rdata[140]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.832 0.024 14.856 ;
+    END
+  END RW0_rdata[140]
+  PIN RW0_rdata[141]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.88 0.024 14.904 ;
+    END
+  END RW0_rdata[141]
+  PIN RW0_rdata[142]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.928 0.024 14.952 ;
+    END
+  END RW0_rdata[142]
+  PIN RW0_rdata[143]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.976 0.024 15 ;
+    END
+  END RW0_rdata[143]
+  PIN RW0_rdata[144]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.024 0.024 15.048 ;
+    END
+  END RW0_rdata[144]
+  PIN RW0_rdata[145]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.072 0.024 15.096 ;
+    END
+  END RW0_rdata[145]
+  PIN RW0_rdata[146]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.12 0.024 15.144 ;
+    END
+  END RW0_rdata[146]
+  PIN RW0_rdata[147]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.168 0.024 15.192 ;
+    END
+  END RW0_rdata[147]
+  PIN RW0_rdata[148]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.216 0.024 15.24 ;
+    END
+  END RW0_rdata[148]
+  PIN RW0_rdata[149]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.264 0.024 15.288 ;
+    END
+  END RW0_rdata[149]
+  PIN RW0_rdata[150]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.312 0.024 15.336 ;
+    END
+  END RW0_rdata[150]
+  PIN RW0_rdata[151]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.36 0.024 15.384 ;
+    END
+  END RW0_rdata[151]
+  PIN RW0_rdata[152]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.408 0.024 15.432 ;
+    END
+  END RW0_rdata[152]
+  PIN RW0_rdata[153]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.456 0.024 15.48 ;
+    END
+  END RW0_rdata[153]
+  PIN RW0_rdata[154]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.504 0.024 15.528 ;
+    END
+  END RW0_rdata[154]
+  PIN RW0_rdata[155]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.552 0.024 15.576 ;
+    END
+  END RW0_rdata[155]
+  PIN RW0_rdata[156]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.6 0.024 15.624 ;
+    END
+  END RW0_rdata[156]
+  PIN RW0_rdata[157]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.648 0.024 15.672 ;
+    END
+  END RW0_rdata[157]
+  PIN RW0_rdata[158]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.696 0.024 15.72 ;
+    END
+  END RW0_rdata[158]
+  PIN RW0_rdata[159]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.744 0.024 15.768 ;
+    END
+  END RW0_rdata[159]
+  PIN RW0_rdata[160]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.792 0.024 15.816 ;
+    END
+  END RW0_rdata[160]
+  PIN RW0_rdata[161]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.84 0.024 15.864 ;
+    END
+  END RW0_rdata[161]
+  PIN RW0_rdata[162]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.888 0.024 15.912 ;
+    END
+  END RW0_rdata[162]
+  PIN RW0_rdata[163]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.936 0.024 15.96 ;
+    END
+  END RW0_rdata[163]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.984 0.024 16.008 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.032 0.024 16.056 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.08 0.024 16.104 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.128 0.024 16.152 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.176 0.024 16.2 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.224 0.024 16.248 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.272 0.024 16.296 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.32 0.024 16.344 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.368 0.024 16.392 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.416 0.024 16.44 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.464 0.024 16.488 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0 44.374 0.096 ;
+      RECT 0.048 0.768 44.374 0.864 ;
+      RECT 0.048 1.536 44.374 1.632 ;
+      RECT 0.048 2.304 44.374 2.4 ;
+      RECT 0.048 3.072 44.374 3.168 ;
+      RECT 0.048 3.84 44.374 3.936 ;
+      RECT 0.048 4.608 44.374 4.704 ;
+      RECT 0.048 5.376 44.374 5.472 ;
+      RECT 0.048 6.144 44.374 6.24 ;
+      RECT 0.048 6.912 44.374 7.008 ;
+      RECT 0.048 7.68 44.374 7.776 ;
+      RECT 0.048 8.448 44.374 8.544 ;
+      RECT 0.048 9.216 44.374 9.312 ;
+      RECT 0.048 9.984 44.374 10.08 ;
+      RECT 0.048 10.752 44.374 10.848 ;
+      RECT 0.048 11.52 44.374 11.616 ;
+      RECT 0.048 12.288 44.374 12.384 ;
+      RECT 0.048 13.056 44.374 13.152 ;
+      RECT 0.048 13.824 44.374 13.92 ;
+      RECT 0.048 14.592 44.374 14.688 ;
+      RECT 0.048 15.36 44.374 15.456 ;
+      RECT 0.048 16.128 44.374 16.224 ;
+      RECT 0.048 16.896 44.374 16.992 ;
+      RECT 0.048 17.664 44.374 17.76 ;
+      RECT 0.048 18.432 44.374 18.528 ;
+      RECT 0.048 19.2 44.374 19.296 ;
+      RECT 0.048 19.968 44.374 20.064 ;
+      RECT 0.048 20.736 44.374 20.832 ;
+      RECT 0.048 21.504 44.374 21.6 ;
+      RECT 0.048 22.272 44.374 22.368 ;
+      RECT 0.048 23.04 44.374 23.136 ;
+      RECT 0.048 23.808 44.374 23.904 ;
+      RECT 0.048 24.576 44.374 24.672 ;
+      RECT 0.048 25.344 44.374 25.44 ;
+      RECT 0.048 26.112 44.374 26.208 ;
+      RECT 0.048 26.88 44.374 26.976 ;
+      RECT 0.048 27.648 44.374 27.744 ;
+      RECT 0.048 28.416 44.374 28.512 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0.384 44.374 0.48 ;
+      RECT 0.048 1.152 44.374 1.248 ;
+      RECT 0.048 1.92 44.374 2.016 ;
+      RECT 0.048 2.688 44.374 2.784 ;
+      RECT 0.048 3.456 44.374 3.552 ;
+      RECT 0.048 4.224 44.374 4.32 ;
+      RECT 0.048 4.992 44.374 5.088 ;
+      RECT 0.048 5.76 44.374 5.856 ;
+      RECT 0.048 6.528 44.374 6.624 ;
+      RECT 0.048 7.296 44.374 7.392 ;
+      RECT 0.048 8.064 44.374 8.16 ;
+      RECT 0.048 8.832 44.374 8.928 ;
+      RECT 0.048 9.6 44.374 9.696 ;
+      RECT 0.048 10.368 44.374 10.464 ;
+      RECT 0.048 11.136 44.374 11.232 ;
+      RECT 0.048 11.904 44.374 12 ;
+      RECT 0.048 12.672 44.374 12.768 ;
+      RECT 0.048 13.44 44.374 13.536 ;
+      RECT 0.048 14.208 44.374 14.304 ;
+      RECT 0.048 14.976 44.374 15.072 ;
+      RECT 0.048 15.744 44.374 15.84 ;
+      RECT 0.048 16.512 44.374 16.608 ;
+      RECT 0.048 17.28 44.374 17.376 ;
+      RECT 0.048 18.048 44.374 18.144 ;
+      RECT 0.048 18.816 44.374 18.912 ;
+      RECT 0.048 19.584 44.374 19.68 ;
+      RECT 0.048 20.352 44.374 20.448 ;
+      RECT 0.048 21.12 44.374 21.216 ;
+      RECT 0.048 21.888 44.374 21.984 ;
+      RECT 0.048 22.656 44.374 22.752 ;
+      RECT 0.048 23.424 44.374 23.52 ;
+      RECT 0.048 24.192 44.374 24.288 ;
+      RECT 0.048 24.96 44.374 25.056 ;
+      RECT 0.048 25.728 44.374 25.824 ;
+      RECT 0.048 26.496 44.374 26.592 ;
+      RECT 0.048 27.264 44.374 27.36 ;
+      RECT 0.048 28.032 44.374 28.128 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 44.422 28.611 ;
+    LAYER M2 ;
+    RECT 0 0 44.422 28.611 ;
+    LAYER M3 ;
+    RECT 0 0 44.422 28.611 ;
+  END
+END array_256x164
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lef/array_256x8_0.lef b/flow/platforms/asap7/lef/array_256x8_0.lef
new file mode 100644
index 0000000000..352b8a34be
--- /dev/null
+++ b/flow/platforms/asap7/lef/array_256x8_0.lef
@@ -0,0 +1,409 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-asap7-fakeram-m4-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x8_0
+  FOREIGN array_256x8_0 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 6.501 BY 22.008 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wmask[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.048 0.024 0.072 ;
+    END
+  END RW0_wmask[0]
+  PIN RW0_wmask[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 0.672 0.024 0.696 ;
+    END
+  END RW0_wmask[1]
+  PIN RW0_wmask[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.296 0.024 1.32 ;
+    END
+  END RW0_wmask[2]
+  PIN RW0_wmask[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 1.92 0.024 1.944 ;
+    END
+  END RW0_wmask[3]
+  PIN RW0_wmask[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 2.544 0.024 2.568 ;
+    END
+  END RW0_wmask[4]
+  PIN RW0_wmask[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.168 0.024 3.192 ;
+    END
+  END RW0_wmask[5]
+  PIN RW0_wmask[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 3.792 0.024 3.816 ;
+    END
+  END RW0_wmask[6]
+  PIN RW0_wmask[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 4.416 0.024 4.44 ;
+    END
+  END RW0_wmask[7]
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.04 0.024 5.064 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 5.664 0.024 5.688 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.288 0.024 6.312 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 6.912 0.024 6.936 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 7.536 0.024 7.56 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.16 0.024 8.184 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 8.784 0.024 8.808 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 9.408 0.024 9.432 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.032 0.024 10.056 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 10.656 0.024 10.68 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.28 0.024 11.304 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 11.904 0.024 11.928 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 12.528 0.024 12.552 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.152 0.024 13.176 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 13.776 0.024 13.8 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 14.4 0.024 14.424 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.024 0.024 15.048 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 15.648 0.024 15.672 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.272 0.024 16.296 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 16.896 0.024 16.92 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 17.52 0.024 17.544 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.144 0.024 18.168 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 18.768 0.024 18.792 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 19.392 0.024 19.416 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.016 0.024 20.04 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 20.64 0.024 20.664 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER M4 ;
+      RECT 0 21.264 0.024 21.288 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0 6.453 0.096 ;
+      RECT 0.048 0.768 6.453 0.864 ;
+      RECT 0.048 1.536 6.453 1.632 ;
+      RECT 0.048 2.304 6.453 2.4 ;
+      RECT 0.048 3.072 6.453 3.168 ;
+      RECT 0.048 3.84 6.453 3.936 ;
+      RECT 0.048 4.608 6.453 4.704 ;
+      RECT 0.048 5.376 6.453 5.472 ;
+      RECT 0.048 6.144 6.453 6.24 ;
+      RECT 0.048 6.912 6.453 7.008 ;
+      RECT 0.048 7.68 6.453 7.776 ;
+      RECT 0.048 8.448 6.453 8.544 ;
+      RECT 0.048 9.216 6.453 9.312 ;
+      RECT 0.048 9.984 6.453 10.08 ;
+      RECT 0.048 10.752 6.453 10.848 ;
+      RECT 0.048 11.52 6.453 11.616 ;
+      RECT 0.048 12.288 6.453 12.384 ;
+      RECT 0.048 13.056 6.453 13.152 ;
+      RECT 0.048 13.824 6.453 13.92 ;
+      RECT 0.048 14.592 6.453 14.688 ;
+      RECT 0.048 15.36 6.453 15.456 ;
+      RECT 0.048 16.128 6.453 16.224 ;
+      RECT 0.048 16.896 6.453 16.992 ;
+      RECT 0.048 17.664 6.453 17.76 ;
+      RECT 0.048 18.432 6.453 18.528 ;
+      RECT 0.048 19.2 6.453 19.296 ;
+      RECT 0.048 19.968 6.453 20.064 ;
+      RECT 0.048 20.736 6.453 20.832 ;
+      RECT 0.048 21.504 6.453 21.6 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M4 ;
+      RECT 0.048 0.384 6.453 0.48 ;
+      RECT 0.048 1.152 6.453 1.248 ;
+      RECT 0.048 1.92 6.453 2.016 ;
+      RECT 0.048 2.688 6.453 2.784 ;
+      RECT 0.048 3.456 6.453 3.552 ;
+      RECT 0.048 4.224 6.453 4.32 ;
+      RECT 0.048 4.992 6.453 5.088 ;
+      RECT 0.048 5.76 6.453 5.856 ;
+      RECT 0.048 6.528 6.453 6.624 ;
+      RECT 0.048 7.296 6.453 7.392 ;
+      RECT 0.048 8.064 6.453 8.16 ;
+      RECT 0.048 8.832 6.453 8.928 ;
+      RECT 0.048 9.6 6.453 9.696 ;
+      RECT 0.048 10.368 6.453 10.464 ;
+      RECT 0.048 11.136 6.453 11.232 ;
+      RECT 0.048 11.904 6.453 12 ;
+      RECT 0.048 12.672 6.453 12.768 ;
+      RECT 0.048 13.44 6.453 13.536 ;
+      RECT 0.048 14.208 6.453 14.304 ;
+      RECT 0.048 14.976 6.453 15.072 ;
+      RECT 0.048 15.744 6.453 15.84 ;
+      RECT 0.048 16.512 6.453 16.608 ;
+      RECT 0.048 17.28 6.453 17.376 ;
+      RECT 0.048 18.048 6.453 18.144 ;
+      RECT 0.048 18.816 6.453 18.912 ;
+      RECT 0.048 19.584 6.453 19.68 ;
+      RECT 0.048 20.352 6.453 20.448 ;
+      RECT 0.048 21.12 6.453 21.216 ;
+      RECT 0.048 21.888 6.453 21.984 ;
+    END
+  END VDD
+  OBS
+    LAYER M1 ;
+    RECT 0 0 6.501 22.008 ;
+    LAYER M2 ;
+    RECT 0 0 6.501 22.008 ;
+    LAYER M3 ;
+    RECT 0 0 6.501 22.008 ;
+  END
+END array_256x8_0
+
+END LIBRARY
diff --git a/flow/platforms/asap7/lib/NLDM/array_2048x137_bk.lib b/flow/platforms/asap7/lib/NLDM/array_2048x137_bk.lib
new file mode 100644
index 0000000000..9a6d15071f
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/array_2048x137_bk.lib
@@ -0,0 +1,395 @@
+library(array_2048x137_bk) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:24Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.77;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.77;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_2048x137_bk_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_2048x137_bk_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_2048x137_bk_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_2048x137_bk_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_2048x137_bk_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_2048x137_bk_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 137;
+        bit_from : 136;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_2048x137_bk_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_2048x137_bk) {
+    area : 933.407;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 137;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.157 ;
+        internal_power(){
+            rise_power(array_2048x137_bk_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+            fall_power(array_2048x137_bk_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_2048x137_bk_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_2048x137_bk_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            cell_fall(array_2048x137_bk_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            rise_transition(array_2048x137_bk_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_2048x137_bk_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_2048x137_bk_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_2048x137_bk_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    cell_leakage_power : 128.900;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/asap7/lib/NLDM/array_256x104.lib b/flow/platforms/asap7/lib/NLDM/array_256x104.lib
new file mode 100644
index 0000000000..3af1faf4e3
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/array_256x104.lib
@@ -0,0 +1,474 @@
+library(array_256x104) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:24Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.77;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.77;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x104_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x104_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x104_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x104_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x104_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x104_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 104;
+        bit_from : 103;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x104_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x104_WMASK) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x104) {
+    area : 734.420;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 104;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.157 ;
+        internal_power(){
+            rise_power(array_256x104_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+            fall_power(array_256x104_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x104_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x104_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            cell_fall(array_256x104_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            rise_transition(array_256x104_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x104_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x104_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x104_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_wmask)   {
+        bus_type : array_256x104_WMASK;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    cell_leakage_power : 128.900;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/asap7/lib/NLDM/array_256x13.lib b/flow/platforms/asap7/lib/NLDM/array_256x13.lib
new file mode 100644
index 0000000000..8a8aaea8b7
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/array_256x13.lib
@@ -0,0 +1,395 @@
+library(array_256x13) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:24Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.77;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.77;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x13_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x13_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x13_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x13_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x13_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x13_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 13;
+        bit_from : 12;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x13_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x13) {
+    area : 132.277;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 13;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.157 ;
+        internal_power(){
+            rise_power(array_256x13_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+            fall_power(array_256x13_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x13_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x13_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            cell_fall(array_256x13_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            rise_transition(array_256x13_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x13_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x13_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x13_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    cell_leakage_power : 128.900;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/asap7/lib/NLDM/array_256x16.lib b/flow/platforms/asap7/lib/NLDM/array_256x16.lib
new file mode 100644
index 0000000000..6a32121c42
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/array_256x16.lib
@@ -0,0 +1,395 @@
+library(array_256x16) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:24Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.77;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.77;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x16_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x16_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x16_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x16_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x16_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x16_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 16;
+        bit_from : 15;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x16_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x16) {
+    area : 133.030;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 16;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.157 ;
+        internal_power(){
+            rise_power(array_256x16_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+            fall_power(array_256x16_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x16_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x16_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            cell_fall(array_256x16_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            rise_transition(array_256x16_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x16_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x16_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x16_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    cell_leakage_power : 128.900;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/asap7/lib/NLDM/array_256x164.lib b/flow/platforms/asap7/lib/NLDM/array_256x164.lib
new file mode 100644
index 0000000000..2eebdc2528
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/array_256x164.lib
@@ -0,0 +1,474 @@
+library(array_256x164) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:24Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.77;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.77;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x164_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x164_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x164_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x164_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x164_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x164_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 164;
+        bit_from : 163;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x164_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x164_WMASK) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 4;
+        bit_from : 3;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x164) {
+    area : 1270.958;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 164;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.157 ;
+        internal_power(){
+            rise_power(array_256x164_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+            fall_power(array_256x164_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x164_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x164_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            cell_fall(array_256x164_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            rise_transition(array_256x164_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x164_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x164_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x164_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_wmask)   {
+        bus_type : array_256x164_WMASK;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    cell_leakage_power : 128.900;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/asap7/lib/NLDM/array_256x8_0.lib b/flow/platforms/asap7/lib/NLDM/array_256x8_0.lib
new file mode 100644
index 0000000000..46701e0f56
--- /dev/null
+++ b/flow/platforms/asap7/lib/NLDM/array_256x8_0.lib
@@ -0,0 +1,474 @@
+library(array_256x8_0) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:24Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 0.77;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 0.77;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x8_0_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x8_0_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x8_0_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x8_0_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x8_0_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x8_0_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x8_0_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x8_0_WMASK) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x8_0) {
+    area : 143.074;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 8;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.157 ;
+        internal_power(){
+            rise_power(array_256x8_0_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+            fall_power(array_256x8_0_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.345, 1.345")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x8_0_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x8_0_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            cell_fall(array_256x8_0_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.218, 0.218", \
+                  "0.218, 0.218" \
+                )
+            }
+            rise_transition(array_256x8_0_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x8_0_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x8_0_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x8_0_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    bus(RW0_wmask)   {
+        bus_type : array_256x8_0_WMASK;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.013, 0.013")
+            }
+        }
+    }
+    cell_leakage_power : 128.900;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/asap7/verilog/array_2048x137_bk_bb.sv b/flow/platforms/asap7/verilog/array_2048x137_bk_bb.sv
new file mode 100644
index 0000000000..8530061c8f
--- /dev/null
+++ b/flow/platforms/asap7/verilog/array_2048x137_bk_bb.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module array_2048x137_bk (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [136:0] RW0_wdata,
+  output [136:0] RW0_rdata
+);
+endmodule
diff --git a/flow/platforms/asap7/verilog/array_256x104_bb.sv b/flow/platforms/asap7/verilog/array_256x104_bb.sv
new file mode 100644
index 0000000000..075dfa721a
--- /dev/null
+++ b/flow/platforms/asap7/verilog/array_256x104_bb.sv
@@ -0,0 +1,11 @@
+(* blackbox *)
+module array_256x104 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [103:0] RW0_wdata,
+  output [103:0] RW0_rdata,
+  input [7:0] RW0_wmask
+);
+endmodule
diff --git a/flow/platforms/asap7/verilog/array_256x13_bb.sv b/flow/platforms/asap7/verilog/array_256x13_bb.sv
new file mode 100644
index 0000000000..a613508247
--- /dev/null
+++ b/flow/platforms/asap7/verilog/array_256x13_bb.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module array_256x13 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [12:0] RW0_wdata,
+  output [12:0] RW0_rdata
+);
+endmodule
diff --git a/flow/platforms/asap7/verilog/array_256x164_bb.sv b/flow/platforms/asap7/verilog/array_256x164_bb.sv
new file mode 100644
index 0000000000..b15437c66e
--- /dev/null
+++ b/flow/platforms/asap7/verilog/array_256x164_bb.sv
@@ -0,0 +1,11 @@
+(* blackbox *)
+module array_256x164 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [163:0] RW0_wdata,
+  output [163:0] RW0_rdata,
+  input [3:0] RW0_wmask
+);
+endmodule
diff --git a/flow/platforms/asap7/verilog/array_256x16_bb.sv b/flow/platforms/asap7/verilog/array_256x16_bb.sv
new file mode 100644
index 0000000000..8814e1f4d5
--- /dev/null
+++ b/flow/platforms/asap7/verilog/array_256x16_bb.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module array_256x16 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [15:0] RW0_wdata,
+  output [15:0] RW0_rdata
+);
+endmodule
diff --git a/flow/platforms/asap7/verilog/array_256x8_0_bb.sv b/flow/platforms/asap7/verilog/array_256x8_0_bb.sv
new file mode 100644
index 0000000000..a2ba101c7a
--- /dev/null
+++ b/flow/platforms/asap7/verilog/array_256x8_0_bb.sv
@@ -0,0 +1,11 @@
+(* blackbox *)
+module array_256x8_0 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [7:0] RW0_wdata,
+  output [7:0] RW0_rdata,
+  input [7:0] RW0_wmask
+);
+endmodule
diff --git a/flow/platforms/nangate45/lef/array_2048x137_bk.lef b/flow/platforms/nangate45/lef/array_2048x137_bk.lef
new file mode 100644
index 0000000000..f13bf8cdf2
--- /dev/null
+++ b/flow/platforms/nangate45/lef/array_2048x137_bk.lef
@@ -0,0 +1,2714 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-ng45-fakeram-metal3-coupledl2-pg-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_2048x137_bk
+  FOREIGN array_2048x137_bk 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 129.2 BY 254.8 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 0.035 0.07 0.105 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 0.875 0.07 0.945 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 1.715 0.07 1.785 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 2.555 0.07 2.625 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 3.395 0.07 3.465 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 4.235 0.07 4.305 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 5.075 0.07 5.145 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 5.915 0.07 5.985 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 6.755 0.07 6.825 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 7.595 0.07 7.665 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 8.435 0.07 8.505 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 9.275 0.07 9.345 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 10.115 0.07 10.185 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_wdata[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 10.955 0.07 11.025 ;
+    END
+  END RW0_wdata[13]
+  PIN RW0_wdata[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 11.795 0.07 11.865 ;
+    END
+  END RW0_wdata[14]
+  PIN RW0_wdata[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 12.635 0.07 12.705 ;
+    END
+  END RW0_wdata[15]
+  PIN RW0_wdata[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 13.475 0.07 13.545 ;
+    END
+  END RW0_wdata[16]
+  PIN RW0_wdata[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 14.315 0.07 14.385 ;
+    END
+  END RW0_wdata[17]
+  PIN RW0_wdata[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 15.155 0.07 15.225 ;
+    END
+  END RW0_wdata[18]
+  PIN RW0_wdata[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 15.995 0.07 16.065 ;
+    END
+  END RW0_wdata[19]
+  PIN RW0_wdata[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 16.835 0.07 16.905 ;
+    END
+  END RW0_wdata[20]
+  PIN RW0_wdata[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 17.675 0.07 17.745 ;
+    END
+  END RW0_wdata[21]
+  PIN RW0_wdata[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 18.515 0.07 18.585 ;
+    END
+  END RW0_wdata[22]
+  PIN RW0_wdata[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 19.355 0.07 19.425 ;
+    END
+  END RW0_wdata[23]
+  PIN RW0_wdata[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 20.195 0.07 20.265 ;
+    END
+  END RW0_wdata[24]
+  PIN RW0_wdata[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 21.035 0.07 21.105 ;
+    END
+  END RW0_wdata[25]
+  PIN RW0_wdata[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 21.875 0.07 21.945 ;
+    END
+  END RW0_wdata[26]
+  PIN RW0_wdata[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 22.715 0.07 22.785 ;
+    END
+  END RW0_wdata[27]
+  PIN RW0_wdata[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 23.555 0.07 23.625 ;
+    END
+  END RW0_wdata[28]
+  PIN RW0_wdata[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 24.395 0.07 24.465 ;
+    END
+  END RW0_wdata[29]
+  PIN RW0_wdata[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 25.235 0.07 25.305 ;
+    END
+  END RW0_wdata[30]
+  PIN RW0_wdata[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 26.075 0.07 26.145 ;
+    END
+  END RW0_wdata[31]
+  PIN RW0_wdata[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 26.915 0.07 26.985 ;
+    END
+  END RW0_wdata[32]
+  PIN RW0_wdata[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 27.755 0.07 27.825 ;
+    END
+  END RW0_wdata[33]
+  PIN RW0_wdata[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 28.595 0.07 28.665 ;
+    END
+  END RW0_wdata[34]
+  PIN RW0_wdata[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 29.435 0.07 29.505 ;
+    END
+  END RW0_wdata[35]
+  PIN RW0_wdata[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 30.275 0.07 30.345 ;
+    END
+  END RW0_wdata[36]
+  PIN RW0_wdata[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 31.115 0.07 31.185 ;
+    END
+  END RW0_wdata[37]
+  PIN RW0_wdata[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 31.955 0.07 32.025 ;
+    END
+  END RW0_wdata[38]
+  PIN RW0_wdata[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 32.795 0.07 32.865 ;
+    END
+  END RW0_wdata[39]
+  PIN RW0_wdata[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 33.635 0.07 33.705 ;
+    END
+  END RW0_wdata[40]
+  PIN RW0_wdata[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 34.475 0.07 34.545 ;
+    END
+  END RW0_wdata[41]
+  PIN RW0_wdata[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 35.315 0.07 35.385 ;
+    END
+  END RW0_wdata[42]
+  PIN RW0_wdata[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 36.155 0.07 36.225 ;
+    END
+  END RW0_wdata[43]
+  PIN RW0_wdata[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 36.995 0.07 37.065 ;
+    END
+  END RW0_wdata[44]
+  PIN RW0_wdata[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 37.835 0.07 37.905 ;
+    END
+  END RW0_wdata[45]
+  PIN RW0_wdata[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 38.675 0.07 38.745 ;
+    END
+  END RW0_wdata[46]
+  PIN RW0_wdata[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 39.515 0.07 39.585 ;
+    END
+  END RW0_wdata[47]
+  PIN RW0_wdata[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 40.355 0.07 40.425 ;
+    END
+  END RW0_wdata[48]
+  PIN RW0_wdata[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 41.195 0.07 41.265 ;
+    END
+  END RW0_wdata[49]
+  PIN RW0_wdata[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 42.035 0.07 42.105 ;
+    END
+  END RW0_wdata[50]
+  PIN RW0_wdata[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 42.875 0.07 42.945 ;
+    END
+  END RW0_wdata[51]
+  PIN RW0_wdata[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 43.715 0.07 43.785 ;
+    END
+  END RW0_wdata[52]
+  PIN RW0_wdata[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 44.555 0.07 44.625 ;
+    END
+  END RW0_wdata[53]
+  PIN RW0_wdata[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 45.395 0.07 45.465 ;
+    END
+  END RW0_wdata[54]
+  PIN RW0_wdata[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 46.235 0.07 46.305 ;
+    END
+  END RW0_wdata[55]
+  PIN RW0_wdata[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 47.075 0.07 47.145 ;
+    END
+  END RW0_wdata[56]
+  PIN RW0_wdata[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 47.915 0.07 47.985 ;
+    END
+  END RW0_wdata[57]
+  PIN RW0_wdata[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 48.755 0.07 48.825 ;
+    END
+  END RW0_wdata[58]
+  PIN RW0_wdata[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 49.595 0.07 49.665 ;
+    END
+  END RW0_wdata[59]
+  PIN RW0_wdata[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 50.435 0.07 50.505 ;
+    END
+  END RW0_wdata[60]
+  PIN RW0_wdata[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 51.275 0.07 51.345 ;
+    END
+  END RW0_wdata[61]
+  PIN RW0_wdata[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 52.115 0.07 52.185 ;
+    END
+  END RW0_wdata[62]
+  PIN RW0_wdata[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 52.955 0.07 53.025 ;
+    END
+  END RW0_wdata[63]
+  PIN RW0_wdata[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 53.795 0.07 53.865 ;
+    END
+  END RW0_wdata[64]
+  PIN RW0_wdata[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 54.635 0.07 54.705 ;
+    END
+  END RW0_wdata[65]
+  PIN RW0_wdata[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 55.475 0.07 55.545 ;
+    END
+  END RW0_wdata[66]
+  PIN RW0_wdata[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 56.315 0.07 56.385 ;
+    END
+  END RW0_wdata[67]
+  PIN RW0_wdata[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 57.155 0.07 57.225 ;
+    END
+  END RW0_wdata[68]
+  PIN RW0_wdata[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 57.995 0.07 58.065 ;
+    END
+  END RW0_wdata[69]
+  PIN RW0_wdata[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 58.835 0.07 58.905 ;
+    END
+  END RW0_wdata[70]
+  PIN RW0_wdata[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 59.675 0.07 59.745 ;
+    END
+  END RW0_wdata[71]
+  PIN RW0_wdata[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 60.515 0.07 60.585 ;
+    END
+  END RW0_wdata[72]
+  PIN RW0_wdata[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 61.355 0.07 61.425 ;
+    END
+  END RW0_wdata[73]
+  PIN RW0_wdata[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 62.195 0.07 62.265 ;
+    END
+  END RW0_wdata[74]
+  PIN RW0_wdata[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 63.035 0.07 63.105 ;
+    END
+  END RW0_wdata[75]
+  PIN RW0_wdata[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 63.875 0.07 63.945 ;
+    END
+  END RW0_wdata[76]
+  PIN RW0_wdata[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 64.715 0.07 64.785 ;
+    END
+  END RW0_wdata[77]
+  PIN RW0_wdata[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 65.555 0.07 65.625 ;
+    END
+  END RW0_wdata[78]
+  PIN RW0_wdata[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 66.395 0.07 66.465 ;
+    END
+  END RW0_wdata[79]
+  PIN RW0_wdata[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 67.235 0.07 67.305 ;
+    END
+  END RW0_wdata[80]
+  PIN RW0_wdata[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 68.075 0.07 68.145 ;
+    END
+  END RW0_wdata[81]
+  PIN RW0_wdata[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 68.915 0.07 68.985 ;
+    END
+  END RW0_wdata[82]
+  PIN RW0_wdata[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 69.755 0.07 69.825 ;
+    END
+  END RW0_wdata[83]
+  PIN RW0_wdata[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 70.595 0.07 70.665 ;
+    END
+  END RW0_wdata[84]
+  PIN RW0_wdata[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 71.435 0.07 71.505 ;
+    END
+  END RW0_wdata[85]
+  PIN RW0_wdata[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 72.275 0.07 72.345 ;
+    END
+  END RW0_wdata[86]
+  PIN RW0_wdata[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 73.115 0.07 73.185 ;
+    END
+  END RW0_wdata[87]
+  PIN RW0_wdata[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 73.955 0.07 74.025 ;
+    END
+  END RW0_wdata[88]
+  PIN RW0_wdata[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 74.795 0.07 74.865 ;
+    END
+  END RW0_wdata[89]
+  PIN RW0_wdata[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 75.635 0.07 75.705 ;
+    END
+  END RW0_wdata[90]
+  PIN RW0_wdata[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 76.475 0.07 76.545 ;
+    END
+  END RW0_wdata[91]
+  PIN RW0_wdata[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 77.315 0.07 77.385 ;
+    END
+  END RW0_wdata[92]
+  PIN RW0_wdata[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 78.155 0.07 78.225 ;
+    END
+  END RW0_wdata[93]
+  PIN RW0_wdata[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 78.995 0.07 79.065 ;
+    END
+  END RW0_wdata[94]
+  PIN RW0_wdata[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 79.835 0.07 79.905 ;
+    END
+  END RW0_wdata[95]
+  PIN RW0_wdata[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 80.675 0.07 80.745 ;
+    END
+  END RW0_wdata[96]
+  PIN RW0_wdata[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 81.515 0.07 81.585 ;
+    END
+  END RW0_wdata[97]
+  PIN RW0_wdata[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 82.355 0.07 82.425 ;
+    END
+  END RW0_wdata[98]
+  PIN RW0_wdata[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 83.195 0.07 83.265 ;
+    END
+  END RW0_wdata[99]
+  PIN RW0_wdata[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 84.035 0.07 84.105 ;
+    END
+  END RW0_wdata[100]
+  PIN RW0_wdata[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 84.875 0.07 84.945 ;
+    END
+  END RW0_wdata[101]
+  PIN RW0_wdata[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 85.715 0.07 85.785 ;
+    END
+  END RW0_wdata[102]
+  PIN RW0_wdata[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 86.555 0.07 86.625 ;
+    END
+  END RW0_wdata[103]
+  PIN RW0_wdata[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 87.395 0.07 87.465 ;
+    END
+  END RW0_wdata[104]
+  PIN RW0_wdata[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 88.235 0.07 88.305 ;
+    END
+  END RW0_wdata[105]
+  PIN RW0_wdata[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 89.075 0.07 89.145 ;
+    END
+  END RW0_wdata[106]
+  PIN RW0_wdata[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 89.915 0.07 89.985 ;
+    END
+  END RW0_wdata[107]
+  PIN RW0_wdata[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 90.755 0.07 90.825 ;
+    END
+  END RW0_wdata[108]
+  PIN RW0_wdata[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 91.595 0.07 91.665 ;
+    END
+  END RW0_wdata[109]
+  PIN RW0_wdata[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 92.435 0.07 92.505 ;
+    END
+  END RW0_wdata[110]
+  PIN RW0_wdata[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 93.275 0.07 93.345 ;
+    END
+  END RW0_wdata[111]
+  PIN RW0_wdata[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 94.115 0.07 94.185 ;
+    END
+  END RW0_wdata[112]
+  PIN RW0_wdata[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 94.955 0.07 95.025 ;
+    END
+  END RW0_wdata[113]
+  PIN RW0_wdata[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 95.795 0.07 95.865 ;
+    END
+  END RW0_wdata[114]
+  PIN RW0_wdata[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 96.635 0.07 96.705 ;
+    END
+  END RW0_wdata[115]
+  PIN RW0_wdata[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 97.475 0.07 97.545 ;
+    END
+  END RW0_wdata[116]
+  PIN RW0_wdata[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 98.315 0.07 98.385 ;
+    END
+  END RW0_wdata[117]
+  PIN RW0_wdata[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 99.155 0.07 99.225 ;
+    END
+  END RW0_wdata[118]
+  PIN RW0_wdata[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 99.995 0.07 100.065 ;
+    END
+  END RW0_wdata[119]
+  PIN RW0_wdata[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 100.835 0.07 100.905 ;
+    END
+  END RW0_wdata[120]
+  PIN RW0_wdata[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 101.675 0.07 101.745 ;
+    END
+  END RW0_wdata[121]
+  PIN RW0_wdata[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 102.515 0.07 102.585 ;
+    END
+  END RW0_wdata[122]
+  PIN RW0_wdata[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 103.355 0.07 103.425 ;
+    END
+  END RW0_wdata[123]
+  PIN RW0_wdata[124]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 104.195 0.07 104.265 ;
+    END
+  END RW0_wdata[124]
+  PIN RW0_wdata[125]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 105.035 0.07 105.105 ;
+    END
+  END RW0_wdata[125]
+  PIN RW0_wdata[126]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 105.875 0.07 105.945 ;
+    END
+  END RW0_wdata[126]
+  PIN RW0_wdata[127]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 106.715 0.07 106.785 ;
+    END
+  END RW0_wdata[127]
+  PIN RW0_wdata[128]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 107.555 0.07 107.625 ;
+    END
+  END RW0_wdata[128]
+  PIN RW0_wdata[129]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 108.395 0.07 108.465 ;
+    END
+  END RW0_wdata[129]
+  PIN RW0_wdata[130]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 109.235 0.07 109.305 ;
+    END
+  END RW0_wdata[130]
+  PIN RW0_wdata[131]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 110.075 0.07 110.145 ;
+    END
+  END RW0_wdata[131]
+  PIN RW0_wdata[132]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 110.915 0.07 110.985 ;
+    END
+  END RW0_wdata[132]
+  PIN RW0_wdata[133]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 111.755 0.07 111.825 ;
+    END
+  END RW0_wdata[133]
+  PIN RW0_wdata[134]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 112.595 0.07 112.665 ;
+    END
+  END RW0_wdata[134]
+  PIN RW0_wdata[135]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 113.435 0.07 113.505 ;
+    END
+  END RW0_wdata[135]
+  PIN RW0_wdata[136]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 114.275 0.07 114.345 ;
+    END
+  END RW0_wdata[136]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 115.115 0.07 115.185 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 115.955 0.07 116.025 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 116.795 0.07 116.865 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 117.635 0.07 117.705 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 118.475 0.07 118.545 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 119.315 0.07 119.385 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 120.155 0.07 120.225 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 120.995 0.07 121.065 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 121.835 0.07 121.905 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 122.675 0.07 122.745 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 123.515 0.07 123.585 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 124.355 0.07 124.425 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 125.195 0.07 125.265 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_rdata[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 126.035 0.07 126.105 ;
+    END
+  END RW0_rdata[13]
+  PIN RW0_rdata[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 126.875 0.07 126.945 ;
+    END
+  END RW0_rdata[14]
+  PIN RW0_rdata[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 127.715 0.07 127.785 ;
+    END
+  END RW0_rdata[15]
+  PIN RW0_rdata[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 128.555 0.07 128.625 ;
+    END
+  END RW0_rdata[16]
+  PIN RW0_rdata[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 129.395 0.07 129.465 ;
+    END
+  END RW0_rdata[17]
+  PIN RW0_rdata[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 130.235 0.07 130.305 ;
+    END
+  END RW0_rdata[18]
+  PIN RW0_rdata[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 131.075 0.07 131.145 ;
+    END
+  END RW0_rdata[19]
+  PIN RW0_rdata[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 131.915 0.07 131.985 ;
+    END
+  END RW0_rdata[20]
+  PIN RW0_rdata[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 132.755 0.07 132.825 ;
+    END
+  END RW0_rdata[21]
+  PIN RW0_rdata[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 133.595 0.07 133.665 ;
+    END
+  END RW0_rdata[22]
+  PIN RW0_rdata[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 134.435 0.07 134.505 ;
+    END
+  END RW0_rdata[23]
+  PIN RW0_rdata[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 135.275 0.07 135.345 ;
+    END
+  END RW0_rdata[24]
+  PIN RW0_rdata[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 136.115 0.07 136.185 ;
+    END
+  END RW0_rdata[25]
+  PIN RW0_rdata[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 136.955 0.07 137.025 ;
+    END
+  END RW0_rdata[26]
+  PIN RW0_rdata[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 137.795 0.07 137.865 ;
+    END
+  END RW0_rdata[27]
+  PIN RW0_rdata[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 138.635 0.07 138.705 ;
+    END
+  END RW0_rdata[28]
+  PIN RW0_rdata[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 139.475 0.07 139.545 ;
+    END
+  END RW0_rdata[29]
+  PIN RW0_rdata[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 140.315 0.07 140.385 ;
+    END
+  END RW0_rdata[30]
+  PIN RW0_rdata[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 141.155 0.07 141.225 ;
+    END
+  END RW0_rdata[31]
+  PIN RW0_rdata[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 141.995 0.07 142.065 ;
+    END
+  END RW0_rdata[32]
+  PIN RW0_rdata[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 142.835 0.07 142.905 ;
+    END
+  END RW0_rdata[33]
+  PIN RW0_rdata[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 143.675 0.07 143.745 ;
+    END
+  END RW0_rdata[34]
+  PIN RW0_rdata[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 144.515 0.07 144.585 ;
+    END
+  END RW0_rdata[35]
+  PIN RW0_rdata[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 145.355 0.07 145.425 ;
+    END
+  END RW0_rdata[36]
+  PIN RW0_rdata[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 146.195 0.07 146.265 ;
+    END
+  END RW0_rdata[37]
+  PIN RW0_rdata[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 147.035 0.07 147.105 ;
+    END
+  END RW0_rdata[38]
+  PIN RW0_rdata[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 147.875 0.07 147.945 ;
+    END
+  END RW0_rdata[39]
+  PIN RW0_rdata[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 148.715 0.07 148.785 ;
+    END
+  END RW0_rdata[40]
+  PIN RW0_rdata[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 149.555 0.07 149.625 ;
+    END
+  END RW0_rdata[41]
+  PIN RW0_rdata[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 150.395 0.07 150.465 ;
+    END
+  END RW0_rdata[42]
+  PIN RW0_rdata[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 151.235 0.07 151.305 ;
+    END
+  END RW0_rdata[43]
+  PIN RW0_rdata[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 152.075 0.07 152.145 ;
+    END
+  END RW0_rdata[44]
+  PIN RW0_rdata[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 152.915 0.07 152.985 ;
+    END
+  END RW0_rdata[45]
+  PIN RW0_rdata[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 153.755 0.07 153.825 ;
+    END
+  END RW0_rdata[46]
+  PIN RW0_rdata[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 154.595 0.07 154.665 ;
+    END
+  END RW0_rdata[47]
+  PIN RW0_rdata[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 155.435 0.07 155.505 ;
+    END
+  END RW0_rdata[48]
+  PIN RW0_rdata[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 156.275 0.07 156.345 ;
+    END
+  END RW0_rdata[49]
+  PIN RW0_rdata[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 157.115 0.07 157.185 ;
+    END
+  END RW0_rdata[50]
+  PIN RW0_rdata[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 157.955 0.07 158.025 ;
+    END
+  END RW0_rdata[51]
+  PIN RW0_rdata[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 158.795 0.07 158.865 ;
+    END
+  END RW0_rdata[52]
+  PIN RW0_rdata[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 159.635 0.07 159.705 ;
+    END
+  END RW0_rdata[53]
+  PIN RW0_rdata[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 160.475 0.07 160.545 ;
+    END
+  END RW0_rdata[54]
+  PIN RW0_rdata[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 161.315 0.07 161.385 ;
+    END
+  END RW0_rdata[55]
+  PIN RW0_rdata[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 162.155 0.07 162.225 ;
+    END
+  END RW0_rdata[56]
+  PIN RW0_rdata[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 162.995 0.07 163.065 ;
+    END
+  END RW0_rdata[57]
+  PIN RW0_rdata[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 163.835 0.07 163.905 ;
+    END
+  END RW0_rdata[58]
+  PIN RW0_rdata[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 164.675 0.07 164.745 ;
+    END
+  END RW0_rdata[59]
+  PIN RW0_rdata[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 165.515 0.07 165.585 ;
+    END
+  END RW0_rdata[60]
+  PIN RW0_rdata[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 166.355 0.07 166.425 ;
+    END
+  END RW0_rdata[61]
+  PIN RW0_rdata[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 167.195 0.07 167.265 ;
+    END
+  END RW0_rdata[62]
+  PIN RW0_rdata[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 168.035 0.07 168.105 ;
+    END
+  END RW0_rdata[63]
+  PIN RW0_rdata[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 168.875 0.07 168.945 ;
+    END
+  END RW0_rdata[64]
+  PIN RW0_rdata[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 169.715 0.07 169.785 ;
+    END
+  END RW0_rdata[65]
+  PIN RW0_rdata[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 170.555 0.07 170.625 ;
+    END
+  END RW0_rdata[66]
+  PIN RW0_rdata[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 171.395 0.07 171.465 ;
+    END
+  END RW0_rdata[67]
+  PIN RW0_rdata[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 172.235 0.07 172.305 ;
+    END
+  END RW0_rdata[68]
+  PIN RW0_rdata[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 173.075 0.07 173.145 ;
+    END
+  END RW0_rdata[69]
+  PIN RW0_rdata[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 173.915 0.07 173.985 ;
+    END
+  END RW0_rdata[70]
+  PIN RW0_rdata[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 174.755 0.07 174.825 ;
+    END
+  END RW0_rdata[71]
+  PIN RW0_rdata[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 175.595 0.07 175.665 ;
+    END
+  END RW0_rdata[72]
+  PIN RW0_rdata[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 176.435 0.07 176.505 ;
+    END
+  END RW0_rdata[73]
+  PIN RW0_rdata[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 177.275 0.07 177.345 ;
+    END
+  END RW0_rdata[74]
+  PIN RW0_rdata[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 178.115 0.07 178.185 ;
+    END
+  END RW0_rdata[75]
+  PIN RW0_rdata[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 178.955 0.07 179.025 ;
+    END
+  END RW0_rdata[76]
+  PIN RW0_rdata[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 179.795 0.07 179.865 ;
+    END
+  END RW0_rdata[77]
+  PIN RW0_rdata[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 180.635 0.07 180.705 ;
+    END
+  END RW0_rdata[78]
+  PIN RW0_rdata[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 181.475 0.07 181.545 ;
+    END
+  END RW0_rdata[79]
+  PIN RW0_rdata[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 182.315 0.07 182.385 ;
+    END
+  END RW0_rdata[80]
+  PIN RW0_rdata[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 183.155 0.07 183.225 ;
+    END
+  END RW0_rdata[81]
+  PIN RW0_rdata[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 183.995 0.07 184.065 ;
+    END
+  END RW0_rdata[82]
+  PIN RW0_rdata[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 184.835 0.07 184.905 ;
+    END
+  END RW0_rdata[83]
+  PIN RW0_rdata[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 185.675 0.07 185.745 ;
+    END
+  END RW0_rdata[84]
+  PIN RW0_rdata[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 186.515 0.07 186.585 ;
+    END
+  END RW0_rdata[85]
+  PIN RW0_rdata[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 187.355 0.07 187.425 ;
+    END
+  END RW0_rdata[86]
+  PIN RW0_rdata[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 188.195 0.07 188.265 ;
+    END
+  END RW0_rdata[87]
+  PIN RW0_rdata[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 189.035 0.07 189.105 ;
+    END
+  END RW0_rdata[88]
+  PIN RW0_rdata[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 189.875 0.07 189.945 ;
+    END
+  END RW0_rdata[89]
+  PIN RW0_rdata[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 190.715 0.07 190.785 ;
+    END
+  END RW0_rdata[90]
+  PIN RW0_rdata[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 191.555 0.07 191.625 ;
+    END
+  END RW0_rdata[91]
+  PIN RW0_rdata[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 192.395 0.07 192.465 ;
+    END
+  END RW0_rdata[92]
+  PIN RW0_rdata[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 193.235 0.07 193.305 ;
+    END
+  END RW0_rdata[93]
+  PIN RW0_rdata[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 194.075 0.07 194.145 ;
+    END
+  END RW0_rdata[94]
+  PIN RW0_rdata[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 194.915 0.07 194.985 ;
+    END
+  END RW0_rdata[95]
+  PIN RW0_rdata[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 195.755 0.07 195.825 ;
+    END
+  END RW0_rdata[96]
+  PIN RW0_rdata[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 196.595 0.07 196.665 ;
+    END
+  END RW0_rdata[97]
+  PIN RW0_rdata[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 197.435 0.07 197.505 ;
+    END
+  END RW0_rdata[98]
+  PIN RW0_rdata[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 198.275 0.07 198.345 ;
+    END
+  END RW0_rdata[99]
+  PIN RW0_rdata[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 199.115 0.07 199.185 ;
+    END
+  END RW0_rdata[100]
+  PIN RW0_rdata[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 199.955 0.07 200.025 ;
+    END
+  END RW0_rdata[101]
+  PIN RW0_rdata[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 200.795 0.07 200.865 ;
+    END
+  END RW0_rdata[102]
+  PIN RW0_rdata[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 201.635 0.07 201.705 ;
+    END
+  END RW0_rdata[103]
+  PIN RW0_rdata[104]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 202.475 0.07 202.545 ;
+    END
+  END RW0_rdata[104]
+  PIN RW0_rdata[105]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 203.315 0.07 203.385 ;
+    END
+  END RW0_rdata[105]
+  PIN RW0_rdata[106]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 204.155 0.07 204.225 ;
+    END
+  END RW0_rdata[106]
+  PIN RW0_rdata[107]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 204.995 0.07 205.065 ;
+    END
+  END RW0_rdata[107]
+  PIN RW0_rdata[108]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 205.835 0.07 205.905 ;
+    END
+  END RW0_rdata[108]
+  PIN RW0_rdata[109]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 206.675 0.07 206.745 ;
+    END
+  END RW0_rdata[109]
+  PIN RW0_rdata[110]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 207.515 0.07 207.585 ;
+    END
+  END RW0_rdata[110]
+  PIN RW0_rdata[111]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 208.355 0.07 208.425 ;
+    END
+  END RW0_rdata[111]
+  PIN RW0_rdata[112]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 209.195 0.07 209.265 ;
+    END
+  END RW0_rdata[112]
+  PIN RW0_rdata[113]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 210.035 0.07 210.105 ;
+    END
+  END RW0_rdata[113]
+  PIN RW0_rdata[114]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 210.875 0.07 210.945 ;
+    END
+  END RW0_rdata[114]
+  PIN RW0_rdata[115]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 211.715 0.07 211.785 ;
+    END
+  END RW0_rdata[115]
+  PIN RW0_rdata[116]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 212.555 0.07 212.625 ;
+    END
+  END RW0_rdata[116]
+  PIN RW0_rdata[117]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 213.395 0.07 213.465 ;
+    END
+  END RW0_rdata[117]
+  PIN RW0_rdata[118]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 214.235 0.07 214.305 ;
+    END
+  END RW0_rdata[118]
+  PIN RW0_rdata[119]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 215.075 0.07 215.145 ;
+    END
+  END RW0_rdata[119]
+  PIN RW0_rdata[120]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 215.915 0.07 215.985 ;
+    END
+  END RW0_rdata[120]
+  PIN RW0_rdata[121]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 216.755 0.07 216.825 ;
+    END
+  END RW0_rdata[121]
+  PIN RW0_rdata[122]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 217.595 0.07 217.665 ;
+    END
+  END RW0_rdata[122]
+  PIN RW0_rdata[123]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 218.435 0.07 218.505 ;
+    END
+  END RW0_rdata[123]
+  PIN RW0_rdata[124]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 219.275 0.07 219.345 ;
+    END
+  END RW0_rdata[124]
+  PIN RW0_rdata[125]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 220.115 0.07 220.185 ;
+    END
+  END RW0_rdata[125]
+  PIN RW0_rdata[126]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 220.955 0.07 221.025 ;
+    END
+  END RW0_rdata[126]
+  PIN RW0_rdata[127]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 221.795 0.07 221.865 ;
+    END
+  END RW0_rdata[127]
+  PIN RW0_rdata[128]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 222.635 0.07 222.705 ;
+    END
+  END RW0_rdata[128]
+  PIN RW0_rdata[129]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 223.475 0.07 223.545 ;
+    END
+  END RW0_rdata[129]
+  PIN RW0_rdata[130]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 224.315 0.07 224.385 ;
+    END
+  END RW0_rdata[130]
+  PIN RW0_rdata[131]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 225.155 0.07 225.225 ;
+    END
+  END RW0_rdata[131]
+  PIN RW0_rdata[132]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 225.995 0.07 226.065 ;
+    END
+  END RW0_rdata[132]
+  PIN RW0_rdata[133]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 226.835 0.07 226.905 ;
+    END
+  END RW0_rdata[133]
+  PIN RW0_rdata[134]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 227.675 0.07 227.745 ;
+    END
+  END RW0_rdata[134]
+  PIN RW0_rdata[135]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 228.515 0.07 228.585 ;
+    END
+  END RW0_rdata[135]
+  PIN RW0_rdata[136]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 229.355 0.07 229.425 ;
+    END
+  END RW0_rdata[136]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 230.195 0.07 230.265 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 231.035 0.07 231.105 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 231.875 0.07 231.945 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 232.715 0.07 232.785 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 233.555 0.07 233.625 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 234.395 0.07 234.465 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 235.235 0.07 235.305 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 236.075 0.07 236.145 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 236.915 0.07 236.985 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 237.755 0.07 237.825 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 238.595 0.07 238.665 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1 0.84 1.28 253.96 ;
+      RECT 3.24 0.84 3.52 253.96 ;
+      RECT 5.48 0.84 5.76 253.96 ;
+      RECT 7.72 0.84 8 253.96 ;
+      RECT 9.96 0.84 10.24 253.96 ;
+      RECT 12.2 0.84 12.48 253.96 ;
+      RECT 14.44 0.84 14.72 253.96 ;
+      RECT 16.68 0.84 16.96 253.96 ;
+      RECT 18.92 0.84 19.2 253.96 ;
+      RECT 21.16 0.84 21.44 253.96 ;
+      RECT 23.4 0.84 23.68 253.96 ;
+      RECT 25.64 0.84 25.92 253.96 ;
+      RECT 27.88 0.84 28.16 253.96 ;
+      RECT 30.12 0.84 30.4 253.96 ;
+      RECT 32.36 0.84 32.64 253.96 ;
+      RECT 34.6 0.84 34.88 253.96 ;
+      RECT 36.84 0.84 37.12 253.96 ;
+      RECT 39.08 0.84 39.36 253.96 ;
+      RECT 41.32 0.84 41.6 253.96 ;
+      RECT 43.56 0.84 43.84 253.96 ;
+      RECT 45.8 0.84 46.08 253.96 ;
+      RECT 48.04 0.84 48.32 253.96 ;
+      RECT 50.28 0.84 50.56 253.96 ;
+      RECT 52.52 0.84 52.8 253.96 ;
+      RECT 54.76 0.84 55.04 253.96 ;
+      RECT 57 0.84 57.28 253.96 ;
+      RECT 59.24 0.84 59.52 253.96 ;
+      RECT 61.48 0.84 61.76 253.96 ;
+      RECT 63.72 0.84 64 253.96 ;
+      RECT 65.96 0.84 66.24 253.96 ;
+      RECT 68.2 0.84 68.48 253.96 ;
+      RECT 70.44 0.84 70.72 253.96 ;
+      RECT 72.68 0.84 72.96 253.96 ;
+      RECT 74.92 0.84 75.2 253.96 ;
+      RECT 77.16 0.84 77.44 253.96 ;
+      RECT 79.4 0.84 79.68 253.96 ;
+      RECT 81.64 0.84 81.92 253.96 ;
+      RECT 83.88 0.84 84.16 253.96 ;
+      RECT 86.12 0.84 86.4 253.96 ;
+      RECT 88.36 0.84 88.64 253.96 ;
+      RECT 90.6 0.84 90.88 253.96 ;
+      RECT 92.84 0.84 93.12 253.96 ;
+      RECT 95.08 0.84 95.36 253.96 ;
+      RECT 97.32 0.84 97.6 253.96 ;
+      RECT 99.56 0.84 99.84 253.96 ;
+      RECT 101.8 0.84 102.08 253.96 ;
+      RECT 104.04 0.84 104.32 253.96 ;
+      RECT 106.28 0.84 106.56 253.96 ;
+      RECT 108.52 0.84 108.8 253.96 ;
+      RECT 110.76 0.84 111.04 253.96 ;
+      RECT 113 0.84 113.28 253.96 ;
+      RECT 115.24 0.84 115.52 253.96 ;
+      RECT 117.48 0.84 117.76 253.96 ;
+      RECT 119.72 0.84 120 253.96 ;
+      RECT 121.96 0.84 122.24 253.96 ;
+      RECT 124.2 0.84 124.48 253.96 ;
+      RECT 126.44 0.84 126.72 253.96 ;
+      RECT 128.68 0.84 128.96 253.96 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 2.12 0.84 2.4 253.96 ;
+      RECT 4.36 0.84 4.64 253.96 ;
+      RECT 6.6 0.84 6.88 253.96 ;
+      RECT 8.84 0.84 9.12 253.96 ;
+      RECT 11.08 0.84 11.36 253.96 ;
+      RECT 13.32 0.84 13.6 253.96 ;
+      RECT 15.56 0.84 15.84 253.96 ;
+      RECT 17.8 0.84 18.08 253.96 ;
+      RECT 20.04 0.84 20.32 253.96 ;
+      RECT 22.28 0.84 22.56 253.96 ;
+      RECT 24.52 0.84 24.8 253.96 ;
+      RECT 26.76 0.84 27.04 253.96 ;
+      RECT 29 0.84 29.28 253.96 ;
+      RECT 31.24 0.84 31.52 253.96 ;
+      RECT 33.48 0.84 33.76 253.96 ;
+      RECT 35.72 0.84 36 253.96 ;
+      RECT 37.96 0.84 38.24 253.96 ;
+      RECT 40.2 0.84 40.48 253.96 ;
+      RECT 42.44 0.84 42.72 253.96 ;
+      RECT 44.68 0.84 44.96 253.96 ;
+      RECT 46.92 0.84 47.2 253.96 ;
+      RECT 49.16 0.84 49.44 253.96 ;
+      RECT 51.4 0.84 51.68 253.96 ;
+      RECT 53.64 0.84 53.92 253.96 ;
+      RECT 55.88 0.84 56.16 253.96 ;
+      RECT 58.12 0.84 58.4 253.96 ;
+      RECT 60.36 0.84 60.64 253.96 ;
+      RECT 62.6 0.84 62.88 253.96 ;
+      RECT 64.84 0.84 65.12 253.96 ;
+      RECT 67.08 0.84 67.36 253.96 ;
+      RECT 69.32 0.84 69.6 253.96 ;
+      RECT 71.56 0.84 71.84 253.96 ;
+      RECT 73.8 0.84 74.08 253.96 ;
+      RECT 76.04 0.84 76.32 253.96 ;
+      RECT 78.28 0.84 78.56 253.96 ;
+      RECT 80.52 0.84 80.8 253.96 ;
+      RECT 82.76 0.84 83.04 253.96 ;
+      RECT 85 0.84 85.28 253.96 ;
+      RECT 87.24 0.84 87.52 253.96 ;
+      RECT 89.48 0.84 89.76 253.96 ;
+      RECT 91.72 0.84 92 253.96 ;
+      RECT 93.96 0.84 94.24 253.96 ;
+      RECT 96.2 0.84 96.48 253.96 ;
+      RECT 98.44 0.84 98.72 253.96 ;
+      RECT 100.68 0.84 100.96 253.96 ;
+      RECT 102.92 0.84 103.2 253.96 ;
+      RECT 105.16 0.84 105.44 253.96 ;
+      RECT 107.4 0.84 107.68 253.96 ;
+      RECT 109.64 0.84 109.92 253.96 ;
+      RECT 111.88 0.84 112.16 253.96 ;
+      RECT 114.12 0.84 114.4 253.96 ;
+      RECT 116.36 0.84 116.64 253.96 ;
+      RECT 118.6 0.84 118.88 253.96 ;
+      RECT 120.84 0.84 121.12 253.96 ;
+      RECT 123.08 0.84 123.36 253.96 ;
+      RECT 125.32 0.84 125.6 253.96 ;
+      RECT 127.56 0.84 127.84 253.96 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 129.2 254.8 ;
+    LAYER metal2 ;
+    RECT 0 0 129.2 254.8 ;
+  END
+END array_2048x137_bk
+
+END LIBRARY
diff --git a/flow/platforms/nangate45/lef/array_256x104.lef b/flow/platforms/nangate45/lef/array_256x104.lef
new file mode 100644
index 0000000000..0f769d44f8
--- /dev/null
+++ b/flow/platforms/nangate45/lef/array_256x104.lef
@@ -0,0 +1,2182 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-ng45-fakeram-metal3-coupledl2-pg-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x104
+  FOREIGN array_256x104 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 117.99 BY 212.8 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wmask[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 0.035 0.07 0.105 ;
+    END
+  END RW0_wmask[0]
+  PIN RW0_wmask[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 0.875 0.07 0.945 ;
+    END
+  END RW0_wmask[1]
+  PIN RW0_wmask[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 1.715 0.07 1.785 ;
+    END
+  END RW0_wmask[2]
+  PIN RW0_wmask[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 2.555 0.07 2.625 ;
+    END
+  END RW0_wmask[3]
+  PIN RW0_wmask[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 3.395 0.07 3.465 ;
+    END
+  END RW0_wmask[4]
+  PIN RW0_wmask[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 4.235 0.07 4.305 ;
+    END
+  END RW0_wmask[5]
+  PIN RW0_wmask[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 5.075 0.07 5.145 ;
+    END
+  END RW0_wmask[6]
+  PIN RW0_wmask[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 5.915 0.07 5.985 ;
+    END
+  END RW0_wmask[7]
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 6.755 0.07 6.825 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 7.595 0.07 7.665 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 8.435 0.07 8.505 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 9.275 0.07 9.345 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 10.115 0.07 10.185 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 10.955 0.07 11.025 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 11.795 0.07 11.865 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 12.635 0.07 12.705 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 13.475 0.07 13.545 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 14.315 0.07 14.385 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 15.155 0.07 15.225 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 15.995 0.07 16.065 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 16.835 0.07 16.905 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_wdata[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 17.675 0.07 17.745 ;
+    END
+  END RW0_wdata[13]
+  PIN RW0_wdata[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 18.515 0.07 18.585 ;
+    END
+  END RW0_wdata[14]
+  PIN RW0_wdata[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 19.355 0.07 19.425 ;
+    END
+  END RW0_wdata[15]
+  PIN RW0_wdata[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 20.195 0.07 20.265 ;
+    END
+  END RW0_wdata[16]
+  PIN RW0_wdata[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 21.035 0.07 21.105 ;
+    END
+  END RW0_wdata[17]
+  PIN RW0_wdata[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 21.875 0.07 21.945 ;
+    END
+  END RW0_wdata[18]
+  PIN RW0_wdata[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 22.715 0.07 22.785 ;
+    END
+  END RW0_wdata[19]
+  PIN RW0_wdata[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 23.555 0.07 23.625 ;
+    END
+  END RW0_wdata[20]
+  PIN RW0_wdata[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 24.395 0.07 24.465 ;
+    END
+  END RW0_wdata[21]
+  PIN RW0_wdata[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 25.235 0.07 25.305 ;
+    END
+  END RW0_wdata[22]
+  PIN RW0_wdata[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 26.075 0.07 26.145 ;
+    END
+  END RW0_wdata[23]
+  PIN RW0_wdata[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 26.915 0.07 26.985 ;
+    END
+  END RW0_wdata[24]
+  PIN RW0_wdata[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 27.755 0.07 27.825 ;
+    END
+  END RW0_wdata[25]
+  PIN RW0_wdata[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 28.595 0.07 28.665 ;
+    END
+  END RW0_wdata[26]
+  PIN RW0_wdata[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 29.435 0.07 29.505 ;
+    END
+  END RW0_wdata[27]
+  PIN RW0_wdata[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 30.275 0.07 30.345 ;
+    END
+  END RW0_wdata[28]
+  PIN RW0_wdata[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 31.115 0.07 31.185 ;
+    END
+  END RW0_wdata[29]
+  PIN RW0_wdata[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 31.955 0.07 32.025 ;
+    END
+  END RW0_wdata[30]
+  PIN RW0_wdata[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 32.795 0.07 32.865 ;
+    END
+  END RW0_wdata[31]
+  PIN RW0_wdata[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 33.635 0.07 33.705 ;
+    END
+  END RW0_wdata[32]
+  PIN RW0_wdata[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 34.475 0.07 34.545 ;
+    END
+  END RW0_wdata[33]
+  PIN RW0_wdata[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 35.315 0.07 35.385 ;
+    END
+  END RW0_wdata[34]
+  PIN RW0_wdata[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 36.155 0.07 36.225 ;
+    END
+  END RW0_wdata[35]
+  PIN RW0_wdata[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 36.995 0.07 37.065 ;
+    END
+  END RW0_wdata[36]
+  PIN RW0_wdata[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 37.835 0.07 37.905 ;
+    END
+  END RW0_wdata[37]
+  PIN RW0_wdata[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 38.675 0.07 38.745 ;
+    END
+  END RW0_wdata[38]
+  PIN RW0_wdata[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 39.515 0.07 39.585 ;
+    END
+  END RW0_wdata[39]
+  PIN RW0_wdata[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 40.355 0.07 40.425 ;
+    END
+  END RW0_wdata[40]
+  PIN RW0_wdata[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 41.195 0.07 41.265 ;
+    END
+  END RW0_wdata[41]
+  PIN RW0_wdata[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 42.035 0.07 42.105 ;
+    END
+  END RW0_wdata[42]
+  PIN RW0_wdata[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 42.875 0.07 42.945 ;
+    END
+  END RW0_wdata[43]
+  PIN RW0_wdata[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 43.715 0.07 43.785 ;
+    END
+  END RW0_wdata[44]
+  PIN RW0_wdata[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 44.555 0.07 44.625 ;
+    END
+  END RW0_wdata[45]
+  PIN RW0_wdata[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 45.395 0.07 45.465 ;
+    END
+  END RW0_wdata[46]
+  PIN RW0_wdata[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 46.235 0.07 46.305 ;
+    END
+  END RW0_wdata[47]
+  PIN RW0_wdata[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 47.075 0.07 47.145 ;
+    END
+  END RW0_wdata[48]
+  PIN RW0_wdata[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 47.915 0.07 47.985 ;
+    END
+  END RW0_wdata[49]
+  PIN RW0_wdata[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 48.755 0.07 48.825 ;
+    END
+  END RW0_wdata[50]
+  PIN RW0_wdata[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 49.595 0.07 49.665 ;
+    END
+  END RW0_wdata[51]
+  PIN RW0_wdata[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 50.435 0.07 50.505 ;
+    END
+  END RW0_wdata[52]
+  PIN RW0_wdata[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 51.275 0.07 51.345 ;
+    END
+  END RW0_wdata[53]
+  PIN RW0_wdata[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 52.115 0.07 52.185 ;
+    END
+  END RW0_wdata[54]
+  PIN RW0_wdata[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 52.955 0.07 53.025 ;
+    END
+  END RW0_wdata[55]
+  PIN RW0_wdata[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 53.795 0.07 53.865 ;
+    END
+  END RW0_wdata[56]
+  PIN RW0_wdata[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 54.635 0.07 54.705 ;
+    END
+  END RW0_wdata[57]
+  PIN RW0_wdata[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 55.475 0.07 55.545 ;
+    END
+  END RW0_wdata[58]
+  PIN RW0_wdata[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 56.315 0.07 56.385 ;
+    END
+  END RW0_wdata[59]
+  PIN RW0_wdata[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 57.155 0.07 57.225 ;
+    END
+  END RW0_wdata[60]
+  PIN RW0_wdata[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 57.995 0.07 58.065 ;
+    END
+  END RW0_wdata[61]
+  PIN RW0_wdata[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 58.835 0.07 58.905 ;
+    END
+  END RW0_wdata[62]
+  PIN RW0_wdata[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 59.675 0.07 59.745 ;
+    END
+  END RW0_wdata[63]
+  PIN RW0_wdata[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 60.515 0.07 60.585 ;
+    END
+  END RW0_wdata[64]
+  PIN RW0_wdata[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 61.355 0.07 61.425 ;
+    END
+  END RW0_wdata[65]
+  PIN RW0_wdata[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 62.195 0.07 62.265 ;
+    END
+  END RW0_wdata[66]
+  PIN RW0_wdata[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 63.035 0.07 63.105 ;
+    END
+  END RW0_wdata[67]
+  PIN RW0_wdata[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 63.875 0.07 63.945 ;
+    END
+  END RW0_wdata[68]
+  PIN RW0_wdata[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 64.715 0.07 64.785 ;
+    END
+  END RW0_wdata[69]
+  PIN RW0_wdata[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 65.555 0.07 65.625 ;
+    END
+  END RW0_wdata[70]
+  PIN RW0_wdata[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 66.395 0.07 66.465 ;
+    END
+  END RW0_wdata[71]
+  PIN RW0_wdata[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 67.235 0.07 67.305 ;
+    END
+  END RW0_wdata[72]
+  PIN RW0_wdata[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 68.075 0.07 68.145 ;
+    END
+  END RW0_wdata[73]
+  PIN RW0_wdata[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 68.915 0.07 68.985 ;
+    END
+  END RW0_wdata[74]
+  PIN RW0_wdata[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 69.755 0.07 69.825 ;
+    END
+  END RW0_wdata[75]
+  PIN RW0_wdata[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 70.595 0.07 70.665 ;
+    END
+  END RW0_wdata[76]
+  PIN RW0_wdata[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 71.435 0.07 71.505 ;
+    END
+  END RW0_wdata[77]
+  PIN RW0_wdata[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 72.275 0.07 72.345 ;
+    END
+  END RW0_wdata[78]
+  PIN RW0_wdata[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 73.115 0.07 73.185 ;
+    END
+  END RW0_wdata[79]
+  PIN RW0_wdata[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 73.955 0.07 74.025 ;
+    END
+  END RW0_wdata[80]
+  PIN RW0_wdata[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 74.795 0.07 74.865 ;
+    END
+  END RW0_wdata[81]
+  PIN RW0_wdata[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 75.635 0.07 75.705 ;
+    END
+  END RW0_wdata[82]
+  PIN RW0_wdata[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 76.475 0.07 76.545 ;
+    END
+  END RW0_wdata[83]
+  PIN RW0_wdata[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 77.315 0.07 77.385 ;
+    END
+  END RW0_wdata[84]
+  PIN RW0_wdata[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 78.155 0.07 78.225 ;
+    END
+  END RW0_wdata[85]
+  PIN RW0_wdata[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 78.995 0.07 79.065 ;
+    END
+  END RW0_wdata[86]
+  PIN RW0_wdata[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 79.835 0.07 79.905 ;
+    END
+  END RW0_wdata[87]
+  PIN RW0_wdata[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 80.675 0.07 80.745 ;
+    END
+  END RW0_wdata[88]
+  PIN RW0_wdata[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 81.515 0.07 81.585 ;
+    END
+  END RW0_wdata[89]
+  PIN RW0_wdata[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 82.355 0.07 82.425 ;
+    END
+  END RW0_wdata[90]
+  PIN RW0_wdata[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 83.195 0.07 83.265 ;
+    END
+  END RW0_wdata[91]
+  PIN RW0_wdata[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 84.035 0.07 84.105 ;
+    END
+  END RW0_wdata[92]
+  PIN RW0_wdata[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 84.875 0.07 84.945 ;
+    END
+  END RW0_wdata[93]
+  PIN RW0_wdata[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 85.715 0.07 85.785 ;
+    END
+  END RW0_wdata[94]
+  PIN RW0_wdata[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 86.555 0.07 86.625 ;
+    END
+  END RW0_wdata[95]
+  PIN RW0_wdata[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 87.395 0.07 87.465 ;
+    END
+  END RW0_wdata[96]
+  PIN RW0_wdata[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 88.235 0.07 88.305 ;
+    END
+  END RW0_wdata[97]
+  PIN RW0_wdata[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 89.075 0.07 89.145 ;
+    END
+  END RW0_wdata[98]
+  PIN RW0_wdata[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 89.915 0.07 89.985 ;
+    END
+  END RW0_wdata[99]
+  PIN RW0_wdata[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 90.755 0.07 90.825 ;
+    END
+  END RW0_wdata[100]
+  PIN RW0_wdata[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 91.595 0.07 91.665 ;
+    END
+  END RW0_wdata[101]
+  PIN RW0_wdata[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 92.435 0.07 92.505 ;
+    END
+  END RW0_wdata[102]
+  PIN RW0_wdata[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 93.275 0.07 93.345 ;
+    END
+  END RW0_wdata[103]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 94.115 0.07 94.185 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 94.955 0.07 95.025 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 95.795 0.07 95.865 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 96.635 0.07 96.705 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 97.475 0.07 97.545 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 98.315 0.07 98.385 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 99.155 0.07 99.225 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 99.995 0.07 100.065 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 100.835 0.07 100.905 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 101.675 0.07 101.745 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 102.515 0.07 102.585 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 103.355 0.07 103.425 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 104.195 0.07 104.265 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_rdata[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 105.035 0.07 105.105 ;
+    END
+  END RW0_rdata[13]
+  PIN RW0_rdata[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 105.875 0.07 105.945 ;
+    END
+  END RW0_rdata[14]
+  PIN RW0_rdata[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 106.715 0.07 106.785 ;
+    END
+  END RW0_rdata[15]
+  PIN RW0_rdata[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 107.555 0.07 107.625 ;
+    END
+  END RW0_rdata[16]
+  PIN RW0_rdata[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 108.395 0.07 108.465 ;
+    END
+  END RW0_rdata[17]
+  PIN RW0_rdata[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 109.235 0.07 109.305 ;
+    END
+  END RW0_rdata[18]
+  PIN RW0_rdata[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 110.075 0.07 110.145 ;
+    END
+  END RW0_rdata[19]
+  PIN RW0_rdata[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 110.915 0.07 110.985 ;
+    END
+  END RW0_rdata[20]
+  PIN RW0_rdata[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 111.755 0.07 111.825 ;
+    END
+  END RW0_rdata[21]
+  PIN RW0_rdata[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 112.595 0.07 112.665 ;
+    END
+  END RW0_rdata[22]
+  PIN RW0_rdata[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 113.435 0.07 113.505 ;
+    END
+  END RW0_rdata[23]
+  PIN RW0_rdata[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 114.275 0.07 114.345 ;
+    END
+  END RW0_rdata[24]
+  PIN RW0_rdata[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 115.115 0.07 115.185 ;
+    END
+  END RW0_rdata[25]
+  PIN RW0_rdata[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 115.955 0.07 116.025 ;
+    END
+  END RW0_rdata[26]
+  PIN RW0_rdata[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 116.795 0.07 116.865 ;
+    END
+  END RW0_rdata[27]
+  PIN RW0_rdata[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 117.635 0.07 117.705 ;
+    END
+  END RW0_rdata[28]
+  PIN RW0_rdata[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 118.475 0.07 118.545 ;
+    END
+  END RW0_rdata[29]
+  PIN RW0_rdata[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 119.315 0.07 119.385 ;
+    END
+  END RW0_rdata[30]
+  PIN RW0_rdata[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 120.155 0.07 120.225 ;
+    END
+  END RW0_rdata[31]
+  PIN RW0_rdata[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 120.995 0.07 121.065 ;
+    END
+  END RW0_rdata[32]
+  PIN RW0_rdata[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 121.835 0.07 121.905 ;
+    END
+  END RW0_rdata[33]
+  PIN RW0_rdata[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 122.675 0.07 122.745 ;
+    END
+  END RW0_rdata[34]
+  PIN RW0_rdata[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 123.515 0.07 123.585 ;
+    END
+  END RW0_rdata[35]
+  PIN RW0_rdata[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 124.355 0.07 124.425 ;
+    END
+  END RW0_rdata[36]
+  PIN RW0_rdata[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 125.195 0.07 125.265 ;
+    END
+  END RW0_rdata[37]
+  PIN RW0_rdata[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 126.035 0.07 126.105 ;
+    END
+  END RW0_rdata[38]
+  PIN RW0_rdata[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 126.875 0.07 126.945 ;
+    END
+  END RW0_rdata[39]
+  PIN RW0_rdata[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 127.715 0.07 127.785 ;
+    END
+  END RW0_rdata[40]
+  PIN RW0_rdata[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 128.555 0.07 128.625 ;
+    END
+  END RW0_rdata[41]
+  PIN RW0_rdata[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 129.395 0.07 129.465 ;
+    END
+  END RW0_rdata[42]
+  PIN RW0_rdata[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 130.235 0.07 130.305 ;
+    END
+  END RW0_rdata[43]
+  PIN RW0_rdata[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 131.075 0.07 131.145 ;
+    END
+  END RW0_rdata[44]
+  PIN RW0_rdata[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 131.915 0.07 131.985 ;
+    END
+  END RW0_rdata[45]
+  PIN RW0_rdata[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 132.755 0.07 132.825 ;
+    END
+  END RW0_rdata[46]
+  PIN RW0_rdata[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 133.595 0.07 133.665 ;
+    END
+  END RW0_rdata[47]
+  PIN RW0_rdata[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 134.435 0.07 134.505 ;
+    END
+  END RW0_rdata[48]
+  PIN RW0_rdata[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 135.275 0.07 135.345 ;
+    END
+  END RW0_rdata[49]
+  PIN RW0_rdata[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 136.115 0.07 136.185 ;
+    END
+  END RW0_rdata[50]
+  PIN RW0_rdata[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 136.955 0.07 137.025 ;
+    END
+  END RW0_rdata[51]
+  PIN RW0_rdata[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 137.795 0.07 137.865 ;
+    END
+  END RW0_rdata[52]
+  PIN RW0_rdata[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 138.635 0.07 138.705 ;
+    END
+  END RW0_rdata[53]
+  PIN RW0_rdata[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 139.475 0.07 139.545 ;
+    END
+  END RW0_rdata[54]
+  PIN RW0_rdata[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 140.315 0.07 140.385 ;
+    END
+  END RW0_rdata[55]
+  PIN RW0_rdata[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 141.155 0.07 141.225 ;
+    END
+  END RW0_rdata[56]
+  PIN RW0_rdata[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 141.995 0.07 142.065 ;
+    END
+  END RW0_rdata[57]
+  PIN RW0_rdata[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 142.835 0.07 142.905 ;
+    END
+  END RW0_rdata[58]
+  PIN RW0_rdata[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 143.675 0.07 143.745 ;
+    END
+  END RW0_rdata[59]
+  PIN RW0_rdata[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 144.515 0.07 144.585 ;
+    END
+  END RW0_rdata[60]
+  PIN RW0_rdata[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 145.355 0.07 145.425 ;
+    END
+  END RW0_rdata[61]
+  PIN RW0_rdata[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 146.195 0.07 146.265 ;
+    END
+  END RW0_rdata[62]
+  PIN RW0_rdata[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 147.035 0.07 147.105 ;
+    END
+  END RW0_rdata[63]
+  PIN RW0_rdata[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 147.875 0.07 147.945 ;
+    END
+  END RW0_rdata[64]
+  PIN RW0_rdata[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 148.715 0.07 148.785 ;
+    END
+  END RW0_rdata[65]
+  PIN RW0_rdata[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 149.555 0.07 149.625 ;
+    END
+  END RW0_rdata[66]
+  PIN RW0_rdata[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 150.395 0.07 150.465 ;
+    END
+  END RW0_rdata[67]
+  PIN RW0_rdata[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 151.235 0.07 151.305 ;
+    END
+  END RW0_rdata[68]
+  PIN RW0_rdata[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 152.075 0.07 152.145 ;
+    END
+  END RW0_rdata[69]
+  PIN RW0_rdata[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 152.915 0.07 152.985 ;
+    END
+  END RW0_rdata[70]
+  PIN RW0_rdata[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 153.755 0.07 153.825 ;
+    END
+  END RW0_rdata[71]
+  PIN RW0_rdata[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 154.595 0.07 154.665 ;
+    END
+  END RW0_rdata[72]
+  PIN RW0_rdata[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 155.435 0.07 155.505 ;
+    END
+  END RW0_rdata[73]
+  PIN RW0_rdata[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 156.275 0.07 156.345 ;
+    END
+  END RW0_rdata[74]
+  PIN RW0_rdata[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 157.115 0.07 157.185 ;
+    END
+  END RW0_rdata[75]
+  PIN RW0_rdata[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 157.955 0.07 158.025 ;
+    END
+  END RW0_rdata[76]
+  PIN RW0_rdata[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 158.795 0.07 158.865 ;
+    END
+  END RW0_rdata[77]
+  PIN RW0_rdata[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 159.635 0.07 159.705 ;
+    END
+  END RW0_rdata[78]
+  PIN RW0_rdata[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 160.475 0.07 160.545 ;
+    END
+  END RW0_rdata[79]
+  PIN RW0_rdata[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 161.315 0.07 161.385 ;
+    END
+  END RW0_rdata[80]
+  PIN RW0_rdata[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 162.155 0.07 162.225 ;
+    END
+  END RW0_rdata[81]
+  PIN RW0_rdata[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 162.995 0.07 163.065 ;
+    END
+  END RW0_rdata[82]
+  PIN RW0_rdata[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 163.835 0.07 163.905 ;
+    END
+  END RW0_rdata[83]
+  PIN RW0_rdata[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 164.675 0.07 164.745 ;
+    END
+  END RW0_rdata[84]
+  PIN RW0_rdata[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 165.515 0.07 165.585 ;
+    END
+  END RW0_rdata[85]
+  PIN RW0_rdata[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 166.355 0.07 166.425 ;
+    END
+  END RW0_rdata[86]
+  PIN RW0_rdata[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 167.195 0.07 167.265 ;
+    END
+  END RW0_rdata[87]
+  PIN RW0_rdata[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 168.035 0.07 168.105 ;
+    END
+  END RW0_rdata[88]
+  PIN RW0_rdata[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 168.875 0.07 168.945 ;
+    END
+  END RW0_rdata[89]
+  PIN RW0_rdata[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 169.715 0.07 169.785 ;
+    END
+  END RW0_rdata[90]
+  PIN RW0_rdata[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 170.555 0.07 170.625 ;
+    END
+  END RW0_rdata[91]
+  PIN RW0_rdata[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 171.395 0.07 171.465 ;
+    END
+  END RW0_rdata[92]
+  PIN RW0_rdata[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 172.235 0.07 172.305 ;
+    END
+  END RW0_rdata[93]
+  PIN RW0_rdata[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 173.075 0.07 173.145 ;
+    END
+  END RW0_rdata[94]
+  PIN RW0_rdata[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 173.915 0.07 173.985 ;
+    END
+  END RW0_rdata[95]
+  PIN RW0_rdata[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 174.755 0.07 174.825 ;
+    END
+  END RW0_rdata[96]
+  PIN RW0_rdata[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 175.595 0.07 175.665 ;
+    END
+  END RW0_rdata[97]
+  PIN RW0_rdata[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 176.435 0.07 176.505 ;
+    END
+  END RW0_rdata[98]
+  PIN RW0_rdata[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 177.275 0.07 177.345 ;
+    END
+  END RW0_rdata[99]
+  PIN RW0_rdata[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 178.115 0.07 178.185 ;
+    END
+  END RW0_rdata[100]
+  PIN RW0_rdata[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 178.955 0.07 179.025 ;
+    END
+  END RW0_rdata[101]
+  PIN RW0_rdata[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 179.795 0.07 179.865 ;
+    END
+  END RW0_rdata[102]
+  PIN RW0_rdata[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 180.635 0.07 180.705 ;
+    END
+  END RW0_rdata[103]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 181.475 0.07 181.545 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 182.315 0.07 182.385 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 183.155 0.07 183.225 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 183.995 0.07 184.065 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 184.835 0.07 184.905 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 185.675 0.07 185.745 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 186.515 0.07 186.585 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 187.355 0.07 187.425 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 188.195 0.07 188.265 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 189.035 0.07 189.105 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 189.875 0.07 189.945 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1 0.84 1.28 211.96 ;
+      RECT 3.24 0.84 3.52 211.96 ;
+      RECT 5.48 0.84 5.76 211.96 ;
+      RECT 7.72 0.84 8 211.96 ;
+      RECT 9.96 0.84 10.24 211.96 ;
+      RECT 12.2 0.84 12.48 211.96 ;
+      RECT 14.44 0.84 14.72 211.96 ;
+      RECT 16.68 0.84 16.96 211.96 ;
+      RECT 18.92 0.84 19.2 211.96 ;
+      RECT 21.16 0.84 21.44 211.96 ;
+      RECT 23.4 0.84 23.68 211.96 ;
+      RECT 25.64 0.84 25.92 211.96 ;
+      RECT 27.88 0.84 28.16 211.96 ;
+      RECT 30.12 0.84 30.4 211.96 ;
+      RECT 32.36 0.84 32.64 211.96 ;
+      RECT 34.6 0.84 34.88 211.96 ;
+      RECT 36.84 0.84 37.12 211.96 ;
+      RECT 39.08 0.84 39.36 211.96 ;
+      RECT 41.32 0.84 41.6 211.96 ;
+      RECT 43.56 0.84 43.84 211.96 ;
+      RECT 45.8 0.84 46.08 211.96 ;
+      RECT 48.04 0.84 48.32 211.96 ;
+      RECT 50.28 0.84 50.56 211.96 ;
+      RECT 52.52 0.84 52.8 211.96 ;
+      RECT 54.76 0.84 55.04 211.96 ;
+      RECT 57 0.84 57.28 211.96 ;
+      RECT 59.24 0.84 59.52 211.96 ;
+      RECT 61.48 0.84 61.76 211.96 ;
+      RECT 63.72 0.84 64 211.96 ;
+      RECT 65.96 0.84 66.24 211.96 ;
+      RECT 68.2 0.84 68.48 211.96 ;
+      RECT 70.44 0.84 70.72 211.96 ;
+      RECT 72.68 0.84 72.96 211.96 ;
+      RECT 74.92 0.84 75.2 211.96 ;
+      RECT 77.16 0.84 77.44 211.96 ;
+      RECT 79.4 0.84 79.68 211.96 ;
+      RECT 81.64 0.84 81.92 211.96 ;
+      RECT 83.88 0.84 84.16 211.96 ;
+      RECT 86.12 0.84 86.4 211.96 ;
+      RECT 88.36 0.84 88.64 211.96 ;
+      RECT 90.6 0.84 90.88 211.96 ;
+      RECT 92.84 0.84 93.12 211.96 ;
+      RECT 95.08 0.84 95.36 211.96 ;
+      RECT 97.32 0.84 97.6 211.96 ;
+      RECT 99.56 0.84 99.84 211.96 ;
+      RECT 101.8 0.84 102.08 211.96 ;
+      RECT 104.04 0.84 104.32 211.96 ;
+      RECT 106.28 0.84 106.56 211.96 ;
+      RECT 108.52 0.84 108.8 211.96 ;
+      RECT 110.76 0.84 111.04 211.96 ;
+      RECT 113 0.84 113.28 211.96 ;
+      RECT 115.24 0.84 115.52 211.96 ;
+      RECT 117.48 0.84 117.76 211.96 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 2.12 0.84 2.4 211.96 ;
+      RECT 4.36 0.84 4.64 211.96 ;
+      RECT 6.6 0.84 6.88 211.96 ;
+      RECT 8.84 0.84 9.12 211.96 ;
+      RECT 11.08 0.84 11.36 211.96 ;
+      RECT 13.32 0.84 13.6 211.96 ;
+      RECT 15.56 0.84 15.84 211.96 ;
+      RECT 17.8 0.84 18.08 211.96 ;
+      RECT 20.04 0.84 20.32 211.96 ;
+      RECT 22.28 0.84 22.56 211.96 ;
+      RECT 24.52 0.84 24.8 211.96 ;
+      RECT 26.76 0.84 27.04 211.96 ;
+      RECT 29 0.84 29.28 211.96 ;
+      RECT 31.24 0.84 31.52 211.96 ;
+      RECT 33.48 0.84 33.76 211.96 ;
+      RECT 35.72 0.84 36 211.96 ;
+      RECT 37.96 0.84 38.24 211.96 ;
+      RECT 40.2 0.84 40.48 211.96 ;
+      RECT 42.44 0.84 42.72 211.96 ;
+      RECT 44.68 0.84 44.96 211.96 ;
+      RECT 46.92 0.84 47.2 211.96 ;
+      RECT 49.16 0.84 49.44 211.96 ;
+      RECT 51.4 0.84 51.68 211.96 ;
+      RECT 53.64 0.84 53.92 211.96 ;
+      RECT 55.88 0.84 56.16 211.96 ;
+      RECT 58.12 0.84 58.4 211.96 ;
+      RECT 60.36 0.84 60.64 211.96 ;
+      RECT 62.6 0.84 62.88 211.96 ;
+      RECT 64.84 0.84 65.12 211.96 ;
+      RECT 67.08 0.84 67.36 211.96 ;
+      RECT 69.32 0.84 69.6 211.96 ;
+      RECT 71.56 0.84 71.84 211.96 ;
+      RECT 73.8 0.84 74.08 211.96 ;
+      RECT 76.04 0.84 76.32 211.96 ;
+      RECT 78.28 0.84 78.56 211.96 ;
+      RECT 80.52 0.84 80.8 211.96 ;
+      RECT 82.76 0.84 83.04 211.96 ;
+      RECT 85 0.84 85.28 211.96 ;
+      RECT 87.24 0.84 87.52 211.96 ;
+      RECT 89.48 0.84 89.76 211.96 ;
+      RECT 91.72 0.84 92 211.96 ;
+      RECT 93.96 0.84 94.24 211.96 ;
+      RECT 96.2 0.84 96.48 211.96 ;
+      RECT 98.44 0.84 98.72 211.96 ;
+      RECT 100.68 0.84 100.96 211.96 ;
+      RECT 102.92 0.84 103.2 211.96 ;
+      RECT 105.16 0.84 105.44 211.96 ;
+      RECT 107.4 0.84 107.68 211.96 ;
+      RECT 109.64 0.84 109.92 211.96 ;
+      RECT 111.88 0.84 112.16 211.96 ;
+      RECT 114.12 0.84 114.4 211.96 ;
+      RECT 116.36 0.84 116.64 211.96 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 117.99 212.8 ;
+    LAYER metal2 ;
+    RECT 0 0 117.99 212.8 ;
+  END
+END array_256x104
+
+END LIBRARY
diff --git a/flow/platforms/nangate45/lef/array_256x13.lef b/flow/platforms/nangate45/lef/array_256x13.lef
new file mode 100644
index 0000000000..7dc6dd93dd
--- /dev/null
+++ b/flow/platforms/nangate45/lef/array_256x13.lef
@@ -0,0 +1,418 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-ng45-fakeram-metal3-coupledl2-pg-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x13
+  FOREIGN array_256x13 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 57.57 BY 133 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 0.035 0.07 0.105 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 3.535 0.07 3.605 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 7.035 0.07 7.105 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 10.535 0.07 10.605 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 14.035 0.07 14.105 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 17.535 0.07 17.605 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 21.035 0.07 21.105 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 24.535 0.07 24.605 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 28.035 0.07 28.105 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 31.535 0.07 31.605 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 35.035 0.07 35.105 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 38.535 0.07 38.605 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 42.035 0.07 42.105 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 45.535 0.07 45.605 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 49.035 0.07 49.105 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 52.535 0.07 52.605 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 56.035 0.07 56.105 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 59.535 0.07 59.605 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 63.035 0.07 63.105 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 66.535 0.07 66.605 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 70.035 0.07 70.105 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 73.535 0.07 73.605 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 77.035 0.07 77.105 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 80.535 0.07 80.605 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 84.035 0.07 84.105 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 87.535 0.07 87.605 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 91.035 0.07 91.105 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 94.535 0.07 94.605 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 98.035 0.07 98.105 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 101.535 0.07 101.605 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 105.035 0.07 105.105 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 108.535 0.07 108.605 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 112.035 0.07 112.105 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 115.535 0.07 115.605 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 119.035 0.07 119.105 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 122.535 0.07 122.605 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 126.035 0.07 126.105 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1 0.84 1.28 132.16 ;
+      RECT 3.24 0.84 3.52 132.16 ;
+      RECT 5.48 0.84 5.76 132.16 ;
+      RECT 7.72 0.84 8 132.16 ;
+      RECT 9.96 0.84 10.24 132.16 ;
+      RECT 12.2 0.84 12.48 132.16 ;
+      RECT 14.44 0.84 14.72 132.16 ;
+      RECT 16.68 0.84 16.96 132.16 ;
+      RECT 18.92 0.84 19.2 132.16 ;
+      RECT 21.16 0.84 21.44 132.16 ;
+      RECT 23.4 0.84 23.68 132.16 ;
+      RECT 25.64 0.84 25.92 132.16 ;
+      RECT 27.88 0.84 28.16 132.16 ;
+      RECT 30.12 0.84 30.4 132.16 ;
+      RECT 32.36 0.84 32.64 132.16 ;
+      RECT 34.6 0.84 34.88 132.16 ;
+      RECT 36.84 0.84 37.12 132.16 ;
+      RECT 39.08 0.84 39.36 132.16 ;
+      RECT 41.32 0.84 41.6 132.16 ;
+      RECT 43.56 0.84 43.84 132.16 ;
+      RECT 45.8 0.84 46.08 132.16 ;
+      RECT 48.04 0.84 48.32 132.16 ;
+      RECT 50.28 0.84 50.56 132.16 ;
+      RECT 52.52 0.84 52.8 132.16 ;
+      RECT 54.76 0.84 55.04 132.16 ;
+      RECT 57 0.84 57.28 132.16 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 2.12 0.84 2.4 132.16 ;
+      RECT 4.36 0.84 4.64 132.16 ;
+      RECT 6.6 0.84 6.88 132.16 ;
+      RECT 8.84 0.84 9.12 132.16 ;
+      RECT 11.08 0.84 11.36 132.16 ;
+      RECT 13.32 0.84 13.6 132.16 ;
+      RECT 15.56 0.84 15.84 132.16 ;
+      RECT 17.8 0.84 18.08 132.16 ;
+      RECT 20.04 0.84 20.32 132.16 ;
+      RECT 22.28 0.84 22.56 132.16 ;
+      RECT 24.52 0.84 24.8 132.16 ;
+      RECT 26.76 0.84 27.04 132.16 ;
+      RECT 29 0.84 29.28 132.16 ;
+      RECT 31.24 0.84 31.52 132.16 ;
+      RECT 33.48 0.84 33.76 132.16 ;
+      RECT 35.72 0.84 36 132.16 ;
+      RECT 37.96 0.84 38.24 132.16 ;
+      RECT 40.2 0.84 40.48 132.16 ;
+      RECT 42.44 0.84 42.72 132.16 ;
+      RECT 44.68 0.84 44.96 132.16 ;
+      RECT 46.92 0.84 47.2 132.16 ;
+      RECT 49.16 0.84 49.44 132.16 ;
+      RECT 51.4 0.84 51.68 132.16 ;
+      RECT 53.64 0.84 53.92 132.16 ;
+      RECT 55.88 0.84 56.16 132.16 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 57.57 133 ;
+    LAYER metal2 ;
+    RECT 0 0 57.57 133 ;
+  END
+END array_256x13
+
+END LIBRARY
diff --git a/flow/platforms/nangate45/lef/array_256x16.lef b/flow/platforms/nangate45/lef/array_256x16.lef
new file mode 100644
index 0000000000..4311b8b285
--- /dev/null
+++ b/flow/platforms/nangate45/lef/array_256x16.lef
@@ -0,0 +1,472 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-ng45-fakeram-metal3-coupledl2-pg-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x16
+  FOREIGN array_256x16 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 57.57 BY 133 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 0.035 0.07 0.105 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 3.115 0.07 3.185 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 6.195 0.07 6.265 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 9.275 0.07 9.345 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 12.355 0.07 12.425 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 15.435 0.07 15.505 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 18.515 0.07 18.585 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 21.595 0.07 21.665 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 24.675 0.07 24.745 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 27.755 0.07 27.825 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 30.835 0.07 30.905 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 33.915 0.07 33.985 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 36.995 0.07 37.065 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_wdata[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 40.075 0.07 40.145 ;
+    END
+  END RW0_wdata[13]
+  PIN RW0_wdata[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 43.155 0.07 43.225 ;
+    END
+  END RW0_wdata[14]
+  PIN RW0_wdata[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 46.235 0.07 46.305 ;
+    END
+  END RW0_wdata[15]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 49.315 0.07 49.385 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 52.395 0.07 52.465 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 55.475 0.07 55.545 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 58.555 0.07 58.625 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 61.635 0.07 61.705 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 64.715 0.07 64.785 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 67.795 0.07 67.865 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 70.875 0.07 70.945 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 73.955 0.07 74.025 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 77.035 0.07 77.105 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 80.115 0.07 80.185 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 83.195 0.07 83.265 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 86.275 0.07 86.345 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_rdata[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 89.355 0.07 89.425 ;
+    END
+  END RW0_rdata[13]
+  PIN RW0_rdata[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 92.435 0.07 92.505 ;
+    END
+  END RW0_rdata[14]
+  PIN RW0_rdata[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 95.515 0.07 95.585 ;
+    END
+  END RW0_rdata[15]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 98.595 0.07 98.665 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 101.675 0.07 101.745 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 104.755 0.07 104.825 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 107.835 0.07 107.905 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 110.915 0.07 110.985 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 113.995 0.07 114.065 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 117.075 0.07 117.145 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 120.155 0.07 120.225 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 123.235 0.07 123.305 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 126.315 0.07 126.385 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 129.395 0.07 129.465 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1 0.84 1.28 132.16 ;
+      RECT 3.24 0.84 3.52 132.16 ;
+      RECT 5.48 0.84 5.76 132.16 ;
+      RECT 7.72 0.84 8 132.16 ;
+      RECT 9.96 0.84 10.24 132.16 ;
+      RECT 12.2 0.84 12.48 132.16 ;
+      RECT 14.44 0.84 14.72 132.16 ;
+      RECT 16.68 0.84 16.96 132.16 ;
+      RECT 18.92 0.84 19.2 132.16 ;
+      RECT 21.16 0.84 21.44 132.16 ;
+      RECT 23.4 0.84 23.68 132.16 ;
+      RECT 25.64 0.84 25.92 132.16 ;
+      RECT 27.88 0.84 28.16 132.16 ;
+      RECT 30.12 0.84 30.4 132.16 ;
+      RECT 32.36 0.84 32.64 132.16 ;
+      RECT 34.6 0.84 34.88 132.16 ;
+      RECT 36.84 0.84 37.12 132.16 ;
+      RECT 39.08 0.84 39.36 132.16 ;
+      RECT 41.32 0.84 41.6 132.16 ;
+      RECT 43.56 0.84 43.84 132.16 ;
+      RECT 45.8 0.84 46.08 132.16 ;
+      RECT 48.04 0.84 48.32 132.16 ;
+      RECT 50.28 0.84 50.56 132.16 ;
+      RECT 52.52 0.84 52.8 132.16 ;
+      RECT 54.76 0.84 55.04 132.16 ;
+      RECT 57 0.84 57.28 132.16 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 2.12 0.84 2.4 132.16 ;
+      RECT 4.36 0.84 4.64 132.16 ;
+      RECT 6.6 0.84 6.88 132.16 ;
+      RECT 8.84 0.84 9.12 132.16 ;
+      RECT 11.08 0.84 11.36 132.16 ;
+      RECT 13.32 0.84 13.6 132.16 ;
+      RECT 15.56 0.84 15.84 132.16 ;
+      RECT 17.8 0.84 18.08 132.16 ;
+      RECT 20.04 0.84 20.32 132.16 ;
+      RECT 22.28 0.84 22.56 132.16 ;
+      RECT 24.52 0.84 24.8 132.16 ;
+      RECT 26.76 0.84 27.04 132.16 ;
+      RECT 29 0.84 29.28 132.16 ;
+      RECT 31.24 0.84 31.52 132.16 ;
+      RECT 33.48 0.84 33.76 132.16 ;
+      RECT 35.72 0.84 36 132.16 ;
+      RECT 37.96 0.84 38.24 132.16 ;
+      RECT 40.2 0.84 40.48 132.16 ;
+      RECT 42.44 0.84 42.72 132.16 ;
+      RECT 44.68 0.84 44.96 132.16 ;
+      RECT 46.92 0.84 47.2 132.16 ;
+      RECT 49.16 0.84 49.44 132.16 ;
+      RECT 51.4 0.84 51.68 132.16 ;
+      RECT 53.64 0.84 53.92 132.16 ;
+      RECT 55.88 0.84 56.16 132.16 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 57.57 133 ;
+    LAYER metal2 ;
+    RECT 0 0 57.57 133 ;
+  END
+END array_256x16
+
+END LIBRARY
diff --git a/flow/platforms/nangate45/lef/array_256x164.lef b/flow/platforms/nangate45/lef/array_256x164.lef
new file mode 100644
index 0000000000..4aaaba5762
--- /dev/null
+++ b/flow/platforms/nangate45/lef/array_256x164.lef
@@ -0,0 +1,3241 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-ng45-fakeram-metal3-coupledl2-pg-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x164
+  FOREIGN array_256x164 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 134.71 BY 282.8 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wmask[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 0.035 0.07 0.105 ;
+    END
+  END RW0_wmask[0]
+  PIN RW0_wmask[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 0.735 0.07 0.805 ;
+    END
+  END RW0_wmask[1]
+  PIN RW0_wmask[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 1.435 0.07 1.505 ;
+    END
+  END RW0_wmask[2]
+  PIN RW0_wmask[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 2.135 0.07 2.205 ;
+    END
+  END RW0_wmask[3]
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 2.835 0.07 2.905 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 3.535 0.07 3.605 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 4.235 0.07 4.305 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 4.935 0.07 5.005 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 5.635 0.07 5.705 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 6.335 0.07 6.405 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 7.035 0.07 7.105 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 7.735 0.07 7.805 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_wdata[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 8.435 0.07 8.505 ;
+    END
+  END RW0_wdata[8]
+  PIN RW0_wdata[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 9.135 0.07 9.205 ;
+    END
+  END RW0_wdata[9]
+  PIN RW0_wdata[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 9.835 0.07 9.905 ;
+    END
+  END RW0_wdata[10]
+  PIN RW0_wdata[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 10.535 0.07 10.605 ;
+    END
+  END RW0_wdata[11]
+  PIN RW0_wdata[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 11.235 0.07 11.305 ;
+    END
+  END RW0_wdata[12]
+  PIN RW0_wdata[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 11.935 0.07 12.005 ;
+    END
+  END RW0_wdata[13]
+  PIN RW0_wdata[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 12.635 0.07 12.705 ;
+    END
+  END RW0_wdata[14]
+  PIN RW0_wdata[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 13.335 0.07 13.405 ;
+    END
+  END RW0_wdata[15]
+  PIN RW0_wdata[16]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 14.035 0.07 14.105 ;
+    END
+  END RW0_wdata[16]
+  PIN RW0_wdata[17]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 14.735 0.07 14.805 ;
+    END
+  END RW0_wdata[17]
+  PIN RW0_wdata[18]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 15.435 0.07 15.505 ;
+    END
+  END RW0_wdata[18]
+  PIN RW0_wdata[19]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 16.135 0.07 16.205 ;
+    END
+  END RW0_wdata[19]
+  PIN RW0_wdata[20]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 16.835 0.07 16.905 ;
+    END
+  END RW0_wdata[20]
+  PIN RW0_wdata[21]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 17.535 0.07 17.605 ;
+    END
+  END RW0_wdata[21]
+  PIN RW0_wdata[22]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 18.235 0.07 18.305 ;
+    END
+  END RW0_wdata[22]
+  PIN RW0_wdata[23]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 18.935 0.07 19.005 ;
+    END
+  END RW0_wdata[23]
+  PIN RW0_wdata[24]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 19.635 0.07 19.705 ;
+    END
+  END RW0_wdata[24]
+  PIN RW0_wdata[25]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 20.335 0.07 20.405 ;
+    END
+  END RW0_wdata[25]
+  PIN RW0_wdata[26]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 21.035 0.07 21.105 ;
+    END
+  END RW0_wdata[26]
+  PIN RW0_wdata[27]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 21.735 0.07 21.805 ;
+    END
+  END RW0_wdata[27]
+  PIN RW0_wdata[28]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 22.435 0.07 22.505 ;
+    END
+  END RW0_wdata[28]
+  PIN RW0_wdata[29]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 23.135 0.07 23.205 ;
+    END
+  END RW0_wdata[29]
+  PIN RW0_wdata[30]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 23.835 0.07 23.905 ;
+    END
+  END RW0_wdata[30]
+  PIN RW0_wdata[31]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 24.535 0.07 24.605 ;
+    END
+  END RW0_wdata[31]
+  PIN RW0_wdata[32]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 25.235 0.07 25.305 ;
+    END
+  END RW0_wdata[32]
+  PIN RW0_wdata[33]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 25.935 0.07 26.005 ;
+    END
+  END RW0_wdata[33]
+  PIN RW0_wdata[34]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 26.635 0.07 26.705 ;
+    END
+  END RW0_wdata[34]
+  PIN RW0_wdata[35]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 27.335 0.07 27.405 ;
+    END
+  END RW0_wdata[35]
+  PIN RW0_wdata[36]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 28.035 0.07 28.105 ;
+    END
+  END RW0_wdata[36]
+  PIN RW0_wdata[37]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 28.735 0.07 28.805 ;
+    END
+  END RW0_wdata[37]
+  PIN RW0_wdata[38]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 29.435 0.07 29.505 ;
+    END
+  END RW0_wdata[38]
+  PIN RW0_wdata[39]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 30.135 0.07 30.205 ;
+    END
+  END RW0_wdata[39]
+  PIN RW0_wdata[40]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 30.835 0.07 30.905 ;
+    END
+  END RW0_wdata[40]
+  PIN RW0_wdata[41]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 31.535 0.07 31.605 ;
+    END
+  END RW0_wdata[41]
+  PIN RW0_wdata[42]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 32.235 0.07 32.305 ;
+    END
+  END RW0_wdata[42]
+  PIN RW0_wdata[43]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 32.935 0.07 33.005 ;
+    END
+  END RW0_wdata[43]
+  PIN RW0_wdata[44]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 33.635 0.07 33.705 ;
+    END
+  END RW0_wdata[44]
+  PIN RW0_wdata[45]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 34.335 0.07 34.405 ;
+    END
+  END RW0_wdata[45]
+  PIN RW0_wdata[46]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 35.035 0.07 35.105 ;
+    END
+  END RW0_wdata[46]
+  PIN RW0_wdata[47]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 35.735 0.07 35.805 ;
+    END
+  END RW0_wdata[47]
+  PIN RW0_wdata[48]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 36.435 0.07 36.505 ;
+    END
+  END RW0_wdata[48]
+  PIN RW0_wdata[49]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 37.135 0.07 37.205 ;
+    END
+  END RW0_wdata[49]
+  PIN RW0_wdata[50]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 37.835 0.07 37.905 ;
+    END
+  END RW0_wdata[50]
+  PIN RW0_wdata[51]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 38.535 0.07 38.605 ;
+    END
+  END RW0_wdata[51]
+  PIN RW0_wdata[52]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 39.235 0.07 39.305 ;
+    END
+  END RW0_wdata[52]
+  PIN RW0_wdata[53]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 39.935 0.07 40.005 ;
+    END
+  END RW0_wdata[53]
+  PIN RW0_wdata[54]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 40.635 0.07 40.705 ;
+    END
+  END RW0_wdata[54]
+  PIN RW0_wdata[55]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 41.335 0.07 41.405 ;
+    END
+  END RW0_wdata[55]
+  PIN RW0_wdata[56]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 42.035 0.07 42.105 ;
+    END
+  END RW0_wdata[56]
+  PIN RW0_wdata[57]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 42.735 0.07 42.805 ;
+    END
+  END RW0_wdata[57]
+  PIN RW0_wdata[58]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 43.435 0.07 43.505 ;
+    END
+  END RW0_wdata[58]
+  PIN RW0_wdata[59]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 44.135 0.07 44.205 ;
+    END
+  END RW0_wdata[59]
+  PIN RW0_wdata[60]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 44.835 0.07 44.905 ;
+    END
+  END RW0_wdata[60]
+  PIN RW0_wdata[61]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 45.535 0.07 45.605 ;
+    END
+  END RW0_wdata[61]
+  PIN RW0_wdata[62]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 46.235 0.07 46.305 ;
+    END
+  END RW0_wdata[62]
+  PIN RW0_wdata[63]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 46.935 0.07 47.005 ;
+    END
+  END RW0_wdata[63]
+  PIN RW0_wdata[64]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 47.635 0.07 47.705 ;
+    END
+  END RW0_wdata[64]
+  PIN RW0_wdata[65]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 48.335 0.07 48.405 ;
+    END
+  END RW0_wdata[65]
+  PIN RW0_wdata[66]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 49.035 0.07 49.105 ;
+    END
+  END RW0_wdata[66]
+  PIN RW0_wdata[67]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 49.735 0.07 49.805 ;
+    END
+  END RW0_wdata[67]
+  PIN RW0_wdata[68]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 50.435 0.07 50.505 ;
+    END
+  END RW0_wdata[68]
+  PIN RW0_wdata[69]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 51.135 0.07 51.205 ;
+    END
+  END RW0_wdata[69]
+  PIN RW0_wdata[70]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 51.835 0.07 51.905 ;
+    END
+  END RW0_wdata[70]
+  PIN RW0_wdata[71]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 52.535 0.07 52.605 ;
+    END
+  END RW0_wdata[71]
+  PIN RW0_wdata[72]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 53.235 0.07 53.305 ;
+    END
+  END RW0_wdata[72]
+  PIN RW0_wdata[73]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 53.935 0.07 54.005 ;
+    END
+  END RW0_wdata[73]
+  PIN RW0_wdata[74]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 54.635 0.07 54.705 ;
+    END
+  END RW0_wdata[74]
+  PIN RW0_wdata[75]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 55.335 0.07 55.405 ;
+    END
+  END RW0_wdata[75]
+  PIN RW0_wdata[76]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 56.035 0.07 56.105 ;
+    END
+  END RW0_wdata[76]
+  PIN RW0_wdata[77]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 56.735 0.07 56.805 ;
+    END
+  END RW0_wdata[77]
+  PIN RW0_wdata[78]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 57.435 0.07 57.505 ;
+    END
+  END RW0_wdata[78]
+  PIN RW0_wdata[79]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 58.135 0.07 58.205 ;
+    END
+  END RW0_wdata[79]
+  PIN RW0_wdata[80]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 58.835 0.07 58.905 ;
+    END
+  END RW0_wdata[80]
+  PIN RW0_wdata[81]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 59.535 0.07 59.605 ;
+    END
+  END RW0_wdata[81]
+  PIN RW0_wdata[82]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 60.235 0.07 60.305 ;
+    END
+  END RW0_wdata[82]
+  PIN RW0_wdata[83]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 60.935 0.07 61.005 ;
+    END
+  END RW0_wdata[83]
+  PIN RW0_wdata[84]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 61.635 0.07 61.705 ;
+    END
+  END RW0_wdata[84]
+  PIN RW0_wdata[85]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 62.335 0.07 62.405 ;
+    END
+  END RW0_wdata[85]
+  PIN RW0_wdata[86]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 63.035 0.07 63.105 ;
+    END
+  END RW0_wdata[86]
+  PIN RW0_wdata[87]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 63.735 0.07 63.805 ;
+    END
+  END RW0_wdata[87]
+  PIN RW0_wdata[88]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 64.435 0.07 64.505 ;
+    END
+  END RW0_wdata[88]
+  PIN RW0_wdata[89]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 65.135 0.07 65.205 ;
+    END
+  END RW0_wdata[89]
+  PIN RW0_wdata[90]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 65.835 0.07 65.905 ;
+    END
+  END RW0_wdata[90]
+  PIN RW0_wdata[91]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 66.535 0.07 66.605 ;
+    END
+  END RW0_wdata[91]
+  PIN RW0_wdata[92]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 67.235 0.07 67.305 ;
+    END
+  END RW0_wdata[92]
+  PIN RW0_wdata[93]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 67.935 0.07 68.005 ;
+    END
+  END RW0_wdata[93]
+  PIN RW0_wdata[94]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 68.635 0.07 68.705 ;
+    END
+  END RW0_wdata[94]
+  PIN RW0_wdata[95]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 69.335 0.07 69.405 ;
+    END
+  END RW0_wdata[95]
+  PIN RW0_wdata[96]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 70.035 0.07 70.105 ;
+    END
+  END RW0_wdata[96]
+  PIN RW0_wdata[97]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 70.735 0.07 70.805 ;
+    END
+  END RW0_wdata[97]
+  PIN RW0_wdata[98]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 71.435 0.07 71.505 ;
+    END
+  END RW0_wdata[98]
+  PIN RW0_wdata[99]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 72.135 0.07 72.205 ;
+    END
+  END RW0_wdata[99]
+  PIN RW0_wdata[100]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 72.835 0.07 72.905 ;
+    END
+  END RW0_wdata[100]
+  PIN RW0_wdata[101]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 73.535 0.07 73.605 ;
+    END
+  END RW0_wdata[101]
+  PIN RW0_wdata[102]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 74.235 0.07 74.305 ;
+    END
+  END RW0_wdata[102]
+  PIN RW0_wdata[103]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 74.935 0.07 75.005 ;
+    END
+  END RW0_wdata[103]
+  PIN RW0_wdata[104]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 75.635 0.07 75.705 ;
+    END
+  END RW0_wdata[104]
+  PIN RW0_wdata[105]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 76.335 0.07 76.405 ;
+    END
+  END RW0_wdata[105]
+  PIN RW0_wdata[106]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 77.035 0.07 77.105 ;
+    END
+  END RW0_wdata[106]
+  PIN RW0_wdata[107]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 77.735 0.07 77.805 ;
+    END
+  END RW0_wdata[107]
+  PIN RW0_wdata[108]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 78.435 0.07 78.505 ;
+    END
+  END RW0_wdata[108]
+  PIN RW0_wdata[109]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 79.135 0.07 79.205 ;
+    END
+  END RW0_wdata[109]
+  PIN RW0_wdata[110]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 79.835 0.07 79.905 ;
+    END
+  END RW0_wdata[110]
+  PIN RW0_wdata[111]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 80.535 0.07 80.605 ;
+    END
+  END RW0_wdata[111]
+  PIN RW0_wdata[112]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 81.235 0.07 81.305 ;
+    END
+  END RW0_wdata[112]
+  PIN RW0_wdata[113]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 81.935 0.07 82.005 ;
+    END
+  END RW0_wdata[113]
+  PIN RW0_wdata[114]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 82.635 0.07 82.705 ;
+    END
+  END RW0_wdata[114]
+  PIN RW0_wdata[115]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 83.335 0.07 83.405 ;
+    END
+  END RW0_wdata[115]
+  PIN RW0_wdata[116]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 84.035 0.07 84.105 ;
+    END
+  END RW0_wdata[116]
+  PIN RW0_wdata[117]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 84.735 0.07 84.805 ;
+    END
+  END RW0_wdata[117]
+  PIN RW0_wdata[118]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 85.435 0.07 85.505 ;
+    END
+  END RW0_wdata[118]
+  PIN RW0_wdata[119]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 86.135 0.07 86.205 ;
+    END
+  END RW0_wdata[119]
+  PIN RW0_wdata[120]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 86.835 0.07 86.905 ;
+    END
+  END RW0_wdata[120]
+  PIN RW0_wdata[121]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 87.535 0.07 87.605 ;
+    END
+  END RW0_wdata[121]
+  PIN RW0_wdata[122]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 88.235 0.07 88.305 ;
+    END
+  END RW0_wdata[122]
+  PIN RW0_wdata[123]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 88.935 0.07 89.005 ;
+    END
+  END RW0_wdata[123]
+  PIN RW0_wdata[124]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 89.635 0.07 89.705 ;
+    END
+  END RW0_wdata[124]
+  PIN RW0_wdata[125]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 90.335 0.07 90.405 ;
+    END
+  END RW0_wdata[125]
+  PIN RW0_wdata[126]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 91.035 0.07 91.105 ;
+    END
+  END RW0_wdata[126]
+  PIN RW0_wdata[127]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 91.735 0.07 91.805 ;
+    END
+  END RW0_wdata[127]
+  PIN RW0_wdata[128]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 92.435 0.07 92.505 ;
+    END
+  END RW0_wdata[128]
+  PIN RW0_wdata[129]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 93.135 0.07 93.205 ;
+    END
+  END RW0_wdata[129]
+  PIN RW0_wdata[130]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 93.835 0.07 93.905 ;
+    END
+  END RW0_wdata[130]
+  PIN RW0_wdata[131]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 94.535 0.07 94.605 ;
+    END
+  END RW0_wdata[131]
+  PIN RW0_wdata[132]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 95.235 0.07 95.305 ;
+    END
+  END RW0_wdata[132]
+  PIN RW0_wdata[133]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 95.935 0.07 96.005 ;
+    END
+  END RW0_wdata[133]
+  PIN RW0_wdata[134]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 96.635 0.07 96.705 ;
+    END
+  END RW0_wdata[134]
+  PIN RW0_wdata[135]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 97.335 0.07 97.405 ;
+    END
+  END RW0_wdata[135]
+  PIN RW0_wdata[136]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 98.035 0.07 98.105 ;
+    END
+  END RW0_wdata[136]
+  PIN RW0_wdata[137]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 98.735 0.07 98.805 ;
+    END
+  END RW0_wdata[137]
+  PIN RW0_wdata[138]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 99.435 0.07 99.505 ;
+    END
+  END RW0_wdata[138]
+  PIN RW0_wdata[139]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 100.135 0.07 100.205 ;
+    END
+  END RW0_wdata[139]
+  PIN RW0_wdata[140]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 100.835 0.07 100.905 ;
+    END
+  END RW0_wdata[140]
+  PIN RW0_wdata[141]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 101.535 0.07 101.605 ;
+    END
+  END RW0_wdata[141]
+  PIN RW0_wdata[142]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 102.235 0.07 102.305 ;
+    END
+  END RW0_wdata[142]
+  PIN RW0_wdata[143]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 102.935 0.07 103.005 ;
+    END
+  END RW0_wdata[143]
+  PIN RW0_wdata[144]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 103.635 0.07 103.705 ;
+    END
+  END RW0_wdata[144]
+  PIN RW0_wdata[145]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 104.335 0.07 104.405 ;
+    END
+  END RW0_wdata[145]
+  PIN RW0_wdata[146]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 105.035 0.07 105.105 ;
+    END
+  END RW0_wdata[146]
+  PIN RW0_wdata[147]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 105.735 0.07 105.805 ;
+    END
+  END RW0_wdata[147]
+  PIN RW0_wdata[148]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 106.435 0.07 106.505 ;
+    END
+  END RW0_wdata[148]
+  PIN RW0_wdata[149]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 107.135 0.07 107.205 ;
+    END
+  END RW0_wdata[149]
+  PIN RW0_wdata[150]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 107.835 0.07 107.905 ;
+    END
+  END RW0_wdata[150]
+  PIN RW0_wdata[151]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 108.535 0.07 108.605 ;
+    END
+  END RW0_wdata[151]
+  PIN RW0_wdata[152]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 109.235 0.07 109.305 ;
+    END
+  END RW0_wdata[152]
+  PIN RW0_wdata[153]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 109.935 0.07 110.005 ;
+    END
+  END RW0_wdata[153]
+  PIN RW0_wdata[154]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 110.635 0.07 110.705 ;
+    END
+  END RW0_wdata[154]
+  PIN RW0_wdata[155]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 111.335 0.07 111.405 ;
+    END
+  END RW0_wdata[155]
+  PIN RW0_wdata[156]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 112.035 0.07 112.105 ;
+    END
+  END RW0_wdata[156]
+  PIN RW0_wdata[157]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 112.735 0.07 112.805 ;
+    END
+  END RW0_wdata[157]
+  PIN RW0_wdata[158]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 113.435 0.07 113.505 ;
+    END
+  END RW0_wdata[158]
+  PIN RW0_wdata[159]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 114.135 0.07 114.205 ;
+    END
+  END RW0_wdata[159]
+  PIN RW0_wdata[160]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 114.835 0.07 114.905 ;
+    END
+  END RW0_wdata[160]
+  PIN RW0_wdata[161]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 115.535 0.07 115.605 ;
+    END
+  END RW0_wdata[161]
+  PIN RW0_wdata[162]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 116.235 0.07 116.305 ;
+    END
+  END RW0_wdata[162]
+  PIN RW0_wdata[163]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 116.935 0.07 117.005 ;
+    END
+  END RW0_wdata[163]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 117.635 0.07 117.705 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 118.335 0.07 118.405 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 119.035 0.07 119.105 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 119.735 0.07 119.805 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 120.435 0.07 120.505 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 121.135 0.07 121.205 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 121.835 0.07 121.905 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 122.535 0.07 122.605 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_rdata[8]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 123.235 0.07 123.305 ;
+    END
+  END RW0_rdata[8]
+  PIN RW0_rdata[9]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 123.935 0.07 124.005 ;
+    END
+  END RW0_rdata[9]
+  PIN RW0_rdata[10]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 124.635 0.07 124.705 ;
+    END
+  END RW0_rdata[10]
+  PIN RW0_rdata[11]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 125.335 0.07 125.405 ;
+    END
+  END RW0_rdata[11]
+  PIN RW0_rdata[12]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 126.035 0.07 126.105 ;
+    END
+  END RW0_rdata[12]
+  PIN RW0_rdata[13]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 126.735 0.07 126.805 ;
+    END
+  END RW0_rdata[13]
+  PIN RW0_rdata[14]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 127.435 0.07 127.505 ;
+    END
+  END RW0_rdata[14]
+  PIN RW0_rdata[15]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 128.135 0.07 128.205 ;
+    END
+  END RW0_rdata[15]
+  PIN RW0_rdata[16]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 128.835 0.07 128.905 ;
+    END
+  END RW0_rdata[16]
+  PIN RW0_rdata[17]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 129.535 0.07 129.605 ;
+    END
+  END RW0_rdata[17]
+  PIN RW0_rdata[18]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 130.235 0.07 130.305 ;
+    END
+  END RW0_rdata[18]
+  PIN RW0_rdata[19]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 130.935 0.07 131.005 ;
+    END
+  END RW0_rdata[19]
+  PIN RW0_rdata[20]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 131.635 0.07 131.705 ;
+    END
+  END RW0_rdata[20]
+  PIN RW0_rdata[21]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 132.335 0.07 132.405 ;
+    END
+  END RW0_rdata[21]
+  PIN RW0_rdata[22]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 133.035 0.07 133.105 ;
+    END
+  END RW0_rdata[22]
+  PIN RW0_rdata[23]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 133.735 0.07 133.805 ;
+    END
+  END RW0_rdata[23]
+  PIN RW0_rdata[24]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 134.435 0.07 134.505 ;
+    END
+  END RW0_rdata[24]
+  PIN RW0_rdata[25]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 135.135 0.07 135.205 ;
+    END
+  END RW0_rdata[25]
+  PIN RW0_rdata[26]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 135.835 0.07 135.905 ;
+    END
+  END RW0_rdata[26]
+  PIN RW0_rdata[27]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 136.535 0.07 136.605 ;
+    END
+  END RW0_rdata[27]
+  PIN RW0_rdata[28]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 137.235 0.07 137.305 ;
+    END
+  END RW0_rdata[28]
+  PIN RW0_rdata[29]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 137.935 0.07 138.005 ;
+    END
+  END RW0_rdata[29]
+  PIN RW0_rdata[30]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 138.635 0.07 138.705 ;
+    END
+  END RW0_rdata[30]
+  PIN RW0_rdata[31]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 139.335 0.07 139.405 ;
+    END
+  END RW0_rdata[31]
+  PIN RW0_rdata[32]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 140.035 0.07 140.105 ;
+    END
+  END RW0_rdata[32]
+  PIN RW0_rdata[33]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 140.735 0.07 140.805 ;
+    END
+  END RW0_rdata[33]
+  PIN RW0_rdata[34]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 141.435 0.07 141.505 ;
+    END
+  END RW0_rdata[34]
+  PIN RW0_rdata[35]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 142.135 0.07 142.205 ;
+    END
+  END RW0_rdata[35]
+  PIN RW0_rdata[36]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 142.835 0.07 142.905 ;
+    END
+  END RW0_rdata[36]
+  PIN RW0_rdata[37]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 143.535 0.07 143.605 ;
+    END
+  END RW0_rdata[37]
+  PIN RW0_rdata[38]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 144.235 0.07 144.305 ;
+    END
+  END RW0_rdata[38]
+  PIN RW0_rdata[39]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 144.935 0.07 145.005 ;
+    END
+  END RW0_rdata[39]
+  PIN RW0_rdata[40]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 145.635 0.07 145.705 ;
+    END
+  END RW0_rdata[40]
+  PIN RW0_rdata[41]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 146.335 0.07 146.405 ;
+    END
+  END RW0_rdata[41]
+  PIN RW0_rdata[42]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 147.035 0.07 147.105 ;
+    END
+  END RW0_rdata[42]
+  PIN RW0_rdata[43]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 147.735 0.07 147.805 ;
+    END
+  END RW0_rdata[43]
+  PIN RW0_rdata[44]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 148.435 0.07 148.505 ;
+    END
+  END RW0_rdata[44]
+  PIN RW0_rdata[45]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 149.135 0.07 149.205 ;
+    END
+  END RW0_rdata[45]
+  PIN RW0_rdata[46]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 149.835 0.07 149.905 ;
+    END
+  END RW0_rdata[46]
+  PIN RW0_rdata[47]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 150.535 0.07 150.605 ;
+    END
+  END RW0_rdata[47]
+  PIN RW0_rdata[48]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 151.235 0.07 151.305 ;
+    END
+  END RW0_rdata[48]
+  PIN RW0_rdata[49]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 151.935 0.07 152.005 ;
+    END
+  END RW0_rdata[49]
+  PIN RW0_rdata[50]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 152.635 0.07 152.705 ;
+    END
+  END RW0_rdata[50]
+  PIN RW0_rdata[51]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 153.335 0.07 153.405 ;
+    END
+  END RW0_rdata[51]
+  PIN RW0_rdata[52]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 154.035 0.07 154.105 ;
+    END
+  END RW0_rdata[52]
+  PIN RW0_rdata[53]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 154.735 0.07 154.805 ;
+    END
+  END RW0_rdata[53]
+  PIN RW0_rdata[54]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 155.435 0.07 155.505 ;
+    END
+  END RW0_rdata[54]
+  PIN RW0_rdata[55]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 156.135 0.07 156.205 ;
+    END
+  END RW0_rdata[55]
+  PIN RW0_rdata[56]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 156.835 0.07 156.905 ;
+    END
+  END RW0_rdata[56]
+  PIN RW0_rdata[57]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 157.535 0.07 157.605 ;
+    END
+  END RW0_rdata[57]
+  PIN RW0_rdata[58]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 158.235 0.07 158.305 ;
+    END
+  END RW0_rdata[58]
+  PIN RW0_rdata[59]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 158.935 0.07 159.005 ;
+    END
+  END RW0_rdata[59]
+  PIN RW0_rdata[60]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 159.635 0.07 159.705 ;
+    END
+  END RW0_rdata[60]
+  PIN RW0_rdata[61]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 160.335 0.07 160.405 ;
+    END
+  END RW0_rdata[61]
+  PIN RW0_rdata[62]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 161.035 0.07 161.105 ;
+    END
+  END RW0_rdata[62]
+  PIN RW0_rdata[63]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 161.735 0.07 161.805 ;
+    END
+  END RW0_rdata[63]
+  PIN RW0_rdata[64]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 162.435 0.07 162.505 ;
+    END
+  END RW0_rdata[64]
+  PIN RW0_rdata[65]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 163.135 0.07 163.205 ;
+    END
+  END RW0_rdata[65]
+  PIN RW0_rdata[66]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 163.835 0.07 163.905 ;
+    END
+  END RW0_rdata[66]
+  PIN RW0_rdata[67]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 164.535 0.07 164.605 ;
+    END
+  END RW0_rdata[67]
+  PIN RW0_rdata[68]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 165.235 0.07 165.305 ;
+    END
+  END RW0_rdata[68]
+  PIN RW0_rdata[69]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 165.935 0.07 166.005 ;
+    END
+  END RW0_rdata[69]
+  PIN RW0_rdata[70]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 166.635 0.07 166.705 ;
+    END
+  END RW0_rdata[70]
+  PIN RW0_rdata[71]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 167.335 0.07 167.405 ;
+    END
+  END RW0_rdata[71]
+  PIN RW0_rdata[72]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 168.035 0.07 168.105 ;
+    END
+  END RW0_rdata[72]
+  PIN RW0_rdata[73]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 168.735 0.07 168.805 ;
+    END
+  END RW0_rdata[73]
+  PIN RW0_rdata[74]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 169.435 0.07 169.505 ;
+    END
+  END RW0_rdata[74]
+  PIN RW0_rdata[75]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 170.135 0.07 170.205 ;
+    END
+  END RW0_rdata[75]
+  PIN RW0_rdata[76]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 170.835 0.07 170.905 ;
+    END
+  END RW0_rdata[76]
+  PIN RW0_rdata[77]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 171.535 0.07 171.605 ;
+    END
+  END RW0_rdata[77]
+  PIN RW0_rdata[78]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 172.235 0.07 172.305 ;
+    END
+  END RW0_rdata[78]
+  PIN RW0_rdata[79]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 172.935 0.07 173.005 ;
+    END
+  END RW0_rdata[79]
+  PIN RW0_rdata[80]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 173.635 0.07 173.705 ;
+    END
+  END RW0_rdata[80]
+  PIN RW0_rdata[81]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 174.335 0.07 174.405 ;
+    END
+  END RW0_rdata[81]
+  PIN RW0_rdata[82]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 175.035 0.07 175.105 ;
+    END
+  END RW0_rdata[82]
+  PIN RW0_rdata[83]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 175.735 0.07 175.805 ;
+    END
+  END RW0_rdata[83]
+  PIN RW0_rdata[84]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 176.435 0.07 176.505 ;
+    END
+  END RW0_rdata[84]
+  PIN RW0_rdata[85]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 177.135 0.07 177.205 ;
+    END
+  END RW0_rdata[85]
+  PIN RW0_rdata[86]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 177.835 0.07 177.905 ;
+    END
+  END RW0_rdata[86]
+  PIN RW0_rdata[87]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 178.535 0.07 178.605 ;
+    END
+  END RW0_rdata[87]
+  PIN RW0_rdata[88]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 179.235 0.07 179.305 ;
+    END
+  END RW0_rdata[88]
+  PIN RW0_rdata[89]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 179.935 0.07 180.005 ;
+    END
+  END RW0_rdata[89]
+  PIN RW0_rdata[90]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 180.635 0.07 180.705 ;
+    END
+  END RW0_rdata[90]
+  PIN RW0_rdata[91]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 181.335 0.07 181.405 ;
+    END
+  END RW0_rdata[91]
+  PIN RW0_rdata[92]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 182.035 0.07 182.105 ;
+    END
+  END RW0_rdata[92]
+  PIN RW0_rdata[93]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 182.735 0.07 182.805 ;
+    END
+  END RW0_rdata[93]
+  PIN RW0_rdata[94]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 183.435 0.07 183.505 ;
+    END
+  END RW0_rdata[94]
+  PIN RW0_rdata[95]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 184.135 0.07 184.205 ;
+    END
+  END RW0_rdata[95]
+  PIN RW0_rdata[96]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 184.835 0.07 184.905 ;
+    END
+  END RW0_rdata[96]
+  PIN RW0_rdata[97]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 185.535 0.07 185.605 ;
+    END
+  END RW0_rdata[97]
+  PIN RW0_rdata[98]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 186.235 0.07 186.305 ;
+    END
+  END RW0_rdata[98]
+  PIN RW0_rdata[99]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 186.935 0.07 187.005 ;
+    END
+  END RW0_rdata[99]
+  PIN RW0_rdata[100]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 187.635 0.07 187.705 ;
+    END
+  END RW0_rdata[100]
+  PIN RW0_rdata[101]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 188.335 0.07 188.405 ;
+    END
+  END RW0_rdata[101]
+  PIN RW0_rdata[102]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 189.035 0.07 189.105 ;
+    END
+  END RW0_rdata[102]
+  PIN RW0_rdata[103]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 189.735 0.07 189.805 ;
+    END
+  END RW0_rdata[103]
+  PIN RW0_rdata[104]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 190.435 0.07 190.505 ;
+    END
+  END RW0_rdata[104]
+  PIN RW0_rdata[105]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 191.135 0.07 191.205 ;
+    END
+  END RW0_rdata[105]
+  PIN RW0_rdata[106]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 191.835 0.07 191.905 ;
+    END
+  END RW0_rdata[106]
+  PIN RW0_rdata[107]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 192.535 0.07 192.605 ;
+    END
+  END RW0_rdata[107]
+  PIN RW0_rdata[108]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 193.235 0.07 193.305 ;
+    END
+  END RW0_rdata[108]
+  PIN RW0_rdata[109]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 193.935 0.07 194.005 ;
+    END
+  END RW0_rdata[109]
+  PIN RW0_rdata[110]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 194.635 0.07 194.705 ;
+    END
+  END RW0_rdata[110]
+  PIN RW0_rdata[111]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 195.335 0.07 195.405 ;
+    END
+  END RW0_rdata[111]
+  PIN RW0_rdata[112]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 196.035 0.07 196.105 ;
+    END
+  END RW0_rdata[112]
+  PIN RW0_rdata[113]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 196.735 0.07 196.805 ;
+    END
+  END RW0_rdata[113]
+  PIN RW0_rdata[114]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 197.435 0.07 197.505 ;
+    END
+  END RW0_rdata[114]
+  PIN RW0_rdata[115]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 198.135 0.07 198.205 ;
+    END
+  END RW0_rdata[115]
+  PIN RW0_rdata[116]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 198.835 0.07 198.905 ;
+    END
+  END RW0_rdata[116]
+  PIN RW0_rdata[117]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 199.535 0.07 199.605 ;
+    END
+  END RW0_rdata[117]
+  PIN RW0_rdata[118]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 200.235 0.07 200.305 ;
+    END
+  END RW0_rdata[118]
+  PIN RW0_rdata[119]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 200.935 0.07 201.005 ;
+    END
+  END RW0_rdata[119]
+  PIN RW0_rdata[120]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 201.635 0.07 201.705 ;
+    END
+  END RW0_rdata[120]
+  PIN RW0_rdata[121]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 202.335 0.07 202.405 ;
+    END
+  END RW0_rdata[121]
+  PIN RW0_rdata[122]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 203.035 0.07 203.105 ;
+    END
+  END RW0_rdata[122]
+  PIN RW0_rdata[123]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 203.735 0.07 203.805 ;
+    END
+  END RW0_rdata[123]
+  PIN RW0_rdata[124]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 204.435 0.07 204.505 ;
+    END
+  END RW0_rdata[124]
+  PIN RW0_rdata[125]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 205.135 0.07 205.205 ;
+    END
+  END RW0_rdata[125]
+  PIN RW0_rdata[126]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 205.835 0.07 205.905 ;
+    END
+  END RW0_rdata[126]
+  PIN RW0_rdata[127]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 206.535 0.07 206.605 ;
+    END
+  END RW0_rdata[127]
+  PIN RW0_rdata[128]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 207.235 0.07 207.305 ;
+    END
+  END RW0_rdata[128]
+  PIN RW0_rdata[129]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 207.935 0.07 208.005 ;
+    END
+  END RW0_rdata[129]
+  PIN RW0_rdata[130]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 208.635 0.07 208.705 ;
+    END
+  END RW0_rdata[130]
+  PIN RW0_rdata[131]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 209.335 0.07 209.405 ;
+    END
+  END RW0_rdata[131]
+  PIN RW0_rdata[132]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 210.035 0.07 210.105 ;
+    END
+  END RW0_rdata[132]
+  PIN RW0_rdata[133]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 210.735 0.07 210.805 ;
+    END
+  END RW0_rdata[133]
+  PIN RW0_rdata[134]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 211.435 0.07 211.505 ;
+    END
+  END RW0_rdata[134]
+  PIN RW0_rdata[135]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 212.135 0.07 212.205 ;
+    END
+  END RW0_rdata[135]
+  PIN RW0_rdata[136]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 212.835 0.07 212.905 ;
+    END
+  END RW0_rdata[136]
+  PIN RW0_rdata[137]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 213.535 0.07 213.605 ;
+    END
+  END RW0_rdata[137]
+  PIN RW0_rdata[138]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 214.235 0.07 214.305 ;
+    END
+  END RW0_rdata[138]
+  PIN RW0_rdata[139]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 214.935 0.07 215.005 ;
+    END
+  END RW0_rdata[139]
+  PIN RW0_rdata[140]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 215.635 0.07 215.705 ;
+    END
+  END RW0_rdata[140]
+  PIN RW0_rdata[141]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 216.335 0.07 216.405 ;
+    END
+  END RW0_rdata[141]
+  PIN RW0_rdata[142]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 217.035 0.07 217.105 ;
+    END
+  END RW0_rdata[142]
+  PIN RW0_rdata[143]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 217.735 0.07 217.805 ;
+    END
+  END RW0_rdata[143]
+  PIN RW0_rdata[144]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 218.435 0.07 218.505 ;
+    END
+  END RW0_rdata[144]
+  PIN RW0_rdata[145]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 219.135 0.07 219.205 ;
+    END
+  END RW0_rdata[145]
+  PIN RW0_rdata[146]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 219.835 0.07 219.905 ;
+    END
+  END RW0_rdata[146]
+  PIN RW0_rdata[147]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 220.535 0.07 220.605 ;
+    END
+  END RW0_rdata[147]
+  PIN RW0_rdata[148]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 221.235 0.07 221.305 ;
+    END
+  END RW0_rdata[148]
+  PIN RW0_rdata[149]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 221.935 0.07 222.005 ;
+    END
+  END RW0_rdata[149]
+  PIN RW0_rdata[150]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 222.635 0.07 222.705 ;
+    END
+  END RW0_rdata[150]
+  PIN RW0_rdata[151]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 223.335 0.07 223.405 ;
+    END
+  END RW0_rdata[151]
+  PIN RW0_rdata[152]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 224.035 0.07 224.105 ;
+    END
+  END RW0_rdata[152]
+  PIN RW0_rdata[153]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 224.735 0.07 224.805 ;
+    END
+  END RW0_rdata[153]
+  PIN RW0_rdata[154]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 225.435 0.07 225.505 ;
+    END
+  END RW0_rdata[154]
+  PIN RW0_rdata[155]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 226.135 0.07 226.205 ;
+    END
+  END RW0_rdata[155]
+  PIN RW0_rdata[156]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 226.835 0.07 226.905 ;
+    END
+  END RW0_rdata[156]
+  PIN RW0_rdata[157]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 227.535 0.07 227.605 ;
+    END
+  END RW0_rdata[157]
+  PIN RW0_rdata[158]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 228.235 0.07 228.305 ;
+    END
+  END RW0_rdata[158]
+  PIN RW0_rdata[159]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 228.935 0.07 229.005 ;
+    END
+  END RW0_rdata[159]
+  PIN RW0_rdata[160]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 229.635 0.07 229.705 ;
+    END
+  END RW0_rdata[160]
+  PIN RW0_rdata[161]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 230.335 0.07 230.405 ;
+    END
+  END RW0_rdata[161]
+  PIN RW0_rdata[162]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 231.035 0.07 231.105 ;
+    END
+  END RW0_rdata[162]
+  PIN RW0_rdata[163]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 231.735 0.07 231.805 ;
+    END
+  END RW0_rdata[163]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 232.435 0.07 232.505 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 233.135 0.07 233.205 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 233.835 0.07 233.905 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 234.535 0.07 234.605 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 235.235 0.07 235.305 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 235.935 0.07 236.005 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 236.635 0.07 236.705 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 237.335 0.07 237.405 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 238.035 0.07 238.105 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 238.735 0.07 238.805 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 239.435 0.07 239.505 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1 0.84 1.28 281.96 ;
+      RECT 3.24 0.84 3.52 281.96 ;
+      RECT 5.48 0.84 5.76 281.96 ;
+      RECT 7.72 0.84 8 281.96 ;
+      RECT 9.96 0.84 10.24 281.96 ;
+      RECT 12.2 0.84 12.48 281.96 ;
+      RECT 14.44 0.84 14.72 281.96 ;
+      RECT 16.68 0.84 16.96 281.96 ;
+      RECT 18.92 0.84 19.2 281.96 ;
+      RECT 21.16 0.84 21.44 281.96 ;
+      RECT 23.4 0.84 23.68 281.96 ;
+      RECT 25.64 0.84 25.92 281.96 ;
+      RECT 27.88 0.84 28.16 281.96 ;
+      RECT 30.12 0.84 30.4 281.96 ;
+      RECT 32.36 0.84 32.64 281.96 ;
+      RECT 34.6 0.84 34.88 281.96 ;
+      RECT 36.84 0.84 37.12 281.96 ;
+      RECT 39.08 0.84 39.36 281.96 ;
+      RECT 41.32 0.84 41.6 281.96 ;
+      RECT 43.56 0.84 43.84 281.96 ;
+      RECT 45.8 0.84 46.08 281.96 ;
+      RECT 48.04 0.84 48.32 281.96 ;
+      RECT 50.28 0.84 50.56 281.96 ;
+      RECT 52.52 0.84 52.8 281.96 ;
+      RECT 54.76 0.84 55.04 281.96 ;
+      RECT 57 0.84 57.28 281.96 ;
+      RECT 59.24 0.84 59.52 281.96 ;
+      RECT 61.48 0.84 61.76 281.96 ;
+      RECT 63.72 0.84 64 281.96 ;
+      RECT 65.96 0.84 66.24 281.96 ;
+      RECT 68.2 0.84 68.48 281.96 ;
+      RECT 70.44 0.84 70.72 281.96 ;
+      RECT 72.68 0.84 72.96 281.96 ;
+      RECT 74.92 0.84 75.2 281.96 ;
+      RECT 77.16 0.84 77.44 281.96 ;
+      RECT 79.4 0.84 79.68 281.96 ;
+      RECT 81.64 0.84 81.92 281.96 ;
+      RECT 83.88 0.84 84.16 281.96 ;
+      RECT 86.12 0.84 86.4 281.96 ;
+      RECT 88.36 0.84 88.64 281.96 ;
+      RECT 90.6 0.84 90.88 281.96 ;
+      RECT 92.84 0.84 93.12 281.96 ;
+      RECT 95.08 0.84 95.36 281.96 ;
+      RECT 97.32 0.84 97.6 281.96 ;
+      RECT 99.56 0.84 99.84 281.96 ;
+      RECT 101.8 0.84 102.08 281.96 ;
+      RECT 104.04 0.84 104.32 281.96 ;
+      RECT 106.28 0.84 106.56 281.96 ;
+      RECT 108.52 0.84 108.8 281.96 ;
+      RECT 110.76 0.84 111.04 281.96 ;
+      RECT 113 0.84 113.28 281.96 ;
+      RECT 115.24 0.84 115.52 281.96 ;
+      RECT 117.48 0.84 117.76 281.96 ;
+      RECT 119.72 0.84 120 281.96 ;
+      RECT 121.96 0.84 122.24 281.96 ;
+      RECT 124.2 0.84 124.48 281.96 ;
+      RECT 126.44 0.84 126.72 281.96 ;
+      RECT 128.68 0.84 128.96 281.96 ;
+      RECT 130.92 0.84 131.2 281.96 ;
+      RECT 133.16 0.84 133.44 281.96 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 2.12 0.84 2.4 281.96 ;
+      RECT 4.36 0.84 4.64 281.96 ;
+      RECT 6.6 0.84 6.88 281.96 ;
+      RECT 8.84 0.84 9.12 281.96 ;
+      RECT 11.08 0.84 11.36 281.96 ;
+      RECT 13.32 0.84 13.6 281.96 ;
+      RECT 15.56 0.84 15.84 281.96 ;
+      RECT 17.8 0.84 18.08 281.96 ;
+      RECT 20.04 0.84 20.32 281.96 ;
+      RECT 22.28 0.84 22.56 281.96 ;
+      RECT 24.52 0.84 24.8 281.96 ;
+      RECT 26.76 0.84 27.04 281.96 ;
+      RECT 29 0.84 29.28 281.96 ;
+      RECT 31.24 0.84 31.52 281.96 ;
+      RECT 33.48 0.84 33.76 281.96 ;
+      RECT 35.72 0.84 36 281.96 ;
+      RECT 37.96 0.84 38.24 281.96 ;
+      RECT 40.2 0.84 40.48 281.96 ;
+      RECT 42.44 0.84 42.72 281.96 ;
+      RECT 44.68 0.84 44.96 281.96 ;
+      RECT 46.92 0.84 47.2 281.96 ;
+      RECT 49.16 0.84 49.44 281.96 ;
+      RECT 51.4 0.84 51.68 281.96 ;
+      RECT 53.64 0.84 53.92 281.96 ;
+      RECT 55.88 0.84 56.16 281.96 ;
+      RECT 58.12 0.84 58.4 281.96 ;
+      RECT 60.36 0.84 60.64 281.96 ;
+      RECT 62.6 0.84 62.88 281.96 ;
+      RECT 64.84 0.84 65.12 281.96 ;
+      RECT 67.08 0.84 67.36 281.96 ;
+      RECT 69.32 0.84 69.6 281.96 ;
+      RECT 71.56 0.84 71.84 281.96 ;
+      RECT 73.8 0.84 74.08 281.96 ;
+      RECT 76.04 0.84 76.32 281.96 ;
+      RECT 78.28 0.84 78.56 281.96 ;
+      RECT 80.52 0.84 80.8 281.96 ;
+      RECT 82.76 0.84 83.04 281.96 ;
+      RECT 85 0.84 85.28 281.96 ;
+      RECT 87.24 0.84 87.52 281.96 ;
+      RECT 89.48 0.84 89.76 281.96 ;
+      RECT 91.72 0.84 92 281.96 ;
+      RECT 93.96 0.84 94.24 281.96 ;
+      RECT 96.2 0.84 96.48 281.96 ;
+      RECT 98.44 0.84 98.72 281.96 ;
+      RECT 100.68 0.84 100.96 281.96 ;
+      RECT 102.92 0.84 103.2 281.96 ;
+      RECT 105.16 0.84 105.44 281.96 ;
+      RECT 107.4 0.84 107.68 281.96 ;
+      RECT 109.64 0.84 109.92 281.96 ;
+      RECT 111.88 0.84 112.16 281.96 ;
+      RECT 114.12 0.84 114.4 281.96 ;
+      RECT 116.36 0.84 116.64 281.96 ;
+      RECT 118.6 0.84 118.88 281.96 ;
+      RECT 120.84 0.84 121.12 281.96 ;
+      RECT 123.08 0.84 123.36 281.96 ;
+      RECT 125.32 0.84 125.6 281.96 ;
+      RECT 127.56 0.84 127.84 281.96 ;
+      RECT 129.8 0.84 130.08 281.96 ;
+      RECT 132.04 0.84 132.32 281.96 ;
+      RECT 134.28 0.84 134.56 281.96 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 134.71 282.8 ;
+    LAYER metal2 ;
+    RECT 0 0 134.71 282.8 ;
+  END
+END array_256x164
+
+END LIBRARY
diff --git a/flow/platforms/nangate45/lef/array_256x8_0.lef b/flow/platforms/nangate45/lef/array_256x8_0.lef
new file mode 100644
index 0000000000..c7e17e78cf
--- /dev/null
+++ b/flow/platforms/nangate45/lef/array_256x8_0.lef
@@ -0,0 +1,437 @@
+# Generated deterministically by seda-macro-lef-normalizer-v1; recipe orfs-ng45-fakeram-metal3-coupledl2-pg-v1.
+VERSION 5.8 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO array_256x8_0
+  FOREIGN array_256x8_0 0 0 ;
+  CLASS BLOCK ;
+  ORIGIN 0 0 ;
+  SIZE 99.75 BY 109.2 ;
+  SYMMETRY X Y R90 ;
+  PIN RW0_wmask[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 0.035 0.07 0.105 ;
+    END
+  END RW0_wmask[0]
+  PIN RW0_wmask[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 3.115 0.07 3.185 ;
+    END
+  END RW0_wmask[1]
+  PIN RW0_wmask[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 6.195 0.07 6.265 ;
+    END
+  END RW0_wmask[2]
+  PIN RW0_wmask[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 9.275 0.07 9.345 ;
+    END
+  END RW0_wmask[3]
+  PIN RW0_wmask[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 12.355 0.07 12.425 ;
+    END
+  END RW0_wmask[4]
+  PIN RW0_wmask[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 15.435 0.07 15.505 ;
+    END
+  END RW0_wmask[5]
+  PIN RW0_wmask[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 18.515 0.07 18.585 ;
+    END
+  END RW0_wmask[6]
+  PIN RW0_wmask[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 21.595 0.07 21.665 ;
+    END
+  END RW0_wmask[7]
+  PIN RW0_wdata[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 24.675 0.07 24.745 ;
+    END
+  END RW0_wdata[0]
+  PIN RW0_wdata[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 27.755 0.07 27.825 ;
+    END
+  END RW0_wdata[1]
+  PIN RW0_wdata[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 30.835 0.07 30.905 ;
+    END
+  END RW0_wdata[2]
+  PIN RW0_wdata[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 33.915 0.07 33.985 ;
+    END
+  END RW0_wdata[3]
+  PIN RW0_wdata[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 36.995 0.07 37.065 ;
+    END
+  END RW0_wdata[4]
+  PIN RW0_wdata[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 40.075 0.07 40.145 ;
+    END
+  END RW0_wdata[5]
+  PIN RW0_wdata[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 43.155 0.07 43.225 ;
+    END
+  END RW0_wdata[6]
+  PIN RW0_wdata[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 46.235 0.07 46.305 ;
+    END
+  END RW0_wdata[7]
+  PIN RW0_rdata[0]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 49.315 0.07 49.385 ;
+    END
+  END RW0_rdata[0]
+  PIN RW0_rdata[1]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 52.395 0.07 52.465 ;
+    END
+  END RW0_rdata[1]
+  PIN RW0_rdata[2]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 55.475 0.07 55.545 ;
+    END
+  END RW0_rdata[2]
+  PIN RW0_rdata[3]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 58.555 0.07 58.625 ;
+    END
+  END RW0_rdata[3]
+  PIN RW0_rdata[4]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 61.635 0.07 61.705 ;
+    END
+  END RW0_rdata[4]
+  PIN RW0_rdata[5]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 64.715 0.07 64.785 ;
+    END
+  END RW0_rdata[5]
+  PIN RW0_rdata[6]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 67.795 0.07 67.865 ;
+    END
+  END RW0_rdata[6]
+  PIN RW0_rdata[7]
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 70.875 0.07 70.945 ;
+    END
+  END RW0_rdata[7]
+  PIN RW0_addr[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 73.955 0.07 74.025 ;
+    END
+  END RW0_addr[0]
+  PIN RW0_addr[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 77.035 0.07 77.105 ;
+    END
+  END RW0_addr[1]
+  PIN RW0_addr[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 80.115 0.07 80.185 ;
+    END
+  END RW0_addr[2]
+  PIN RW0_addr[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 83.195 0.07 83.265 ;
+    END
+  END RW0_addr[3]
+  PIN RW0_addr[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 86.275 0.07 86.345 ;
+    END
+  END RW0_addr[4]
+  PIN RW0_addr[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 89.355 0.07 89.425 ;
+    END
+  END RW0_addr[5]
+  PIN RW0_addr[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 92.435 0.07 92.505 ;
+    END
+  END RW0_addr[6]
+  PIN RW0_addr[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 95.515 0.07 95.585 ;
+    END
+  END RW0_addr[7]
+  PIN RW0_wmode
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 98.595 0.07 98.665 ;
+    END
+  END RW0_wmode
+  PIN RW0_en
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 101.675 0.07 101.745 ;
+    END
+  END RW0_en
+  PIN RW0_clk
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    SHAPE ABUTMENT ;
+    PORT
+      LAYER metal3 ;
+      RECT 0 104.755 0.07 104.825 ;
+    END
+  END RW0_clk
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER metal4 ;
+      RECT 1 0.84 1.28 108.36 ;
+      RECT 3.24 0.84 3.52 108.36 ;
+      RECT 5.48 0.84 5.76 108.36 ;
+      RECT 7.72 0.84 8 108.36 ;
+      RECT 9.96 0.84 10.24 108.36 ;
+      RECT 12.2 0.84 12.48 108.36 ;
+      RECT 14.44 0.84 14.72 108.36 ;
+      RECT 16.68 0.84 16.96 108.36 ;
+      RECT 18.92 0.84 19.2 108.36 ;
+      RECT 21.16 0.84 21.44 108.36 ;
+      RECT 23.4 0.84 23.68 108.36 ;
+      RECT 25.64 0.84 25.92 108.36 ;
+      RECT 27.88 0.84 28.16 108.36 ;
+      RECT 30.12 0.84 30.4 108.36 ;
+      RECT 32.36 0.84 32.64 108.36 ;
+      RECT 34.6 0.84 34.88 108.36 ;
+      RECT 36.84 0.84 37.12 108.36 ;
+      RECT 39.08 0.84 39.36 108.36 ;
+      RECT 41.32 0.84 41.6 108.36 ;
+      RECT 43.56 0.84 43.84 108.36 ;
+      RECT 45.8 0.84 46.08 108.36 ;
+      RECT 48.04 0.84 48.32 108.36 ;
+      RECT 50.28 0.84 50.56 108.36 ;
+      RECT 52.52 0.84 52.8 108.36 ;
+      RECT 54.76 0.84 55.04 108.36 ;
+      RECT 57 0.84 57.28 108.36 ;
+      RECT 59.24 0.84 59.52 108.36 ;
+      RECT 61.48 0.84 61.76 108.36 ;
+      RECT 63.72 0.84 64 108.36 ;
+      RECT 65.96 0.84 66.24 108.36 ;
+      RECT 68.2 0.84 68.48 108.36 ;
+      RECT 70.44 0.84 70.72 108.36 ;
+      RECT 72.68 0.84 72.96 108.36 ;
+      RECT 74.92 0.84 75.2 108.36 ;
+      RECT 77.16 0.84 77.44 108.36 ;
+      RECT 79.4 0.84 79.68 108.36 ;
+      RECT 81.64 0.84 81.92 108.36 ;
+      RECT 83.88 0.84 84.16 108.36 ;
+      RECT 86.12 0.84 86.4 108.36 ;
+      RECT 88.36 0.84 88.64 108.36 ;
+      RECT 90.6 0.84 90.88 108.36 ;
+      RECT 92.84 0.84 93.12 108.36 ;
+      RECT 95.08 0.84 95.36 108.36 ;
+      RECT 97.32 0.84 97.6 108.36 ;
+    END
+  END VSS
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER metal4 ;
+      RECT 2.12 0.84 2.4 108.36 ;
+      RECT 4.36 0.84 4.64 108.36 ;
+      RECT 6.6 0.84 6.88 108.36 ;
+      RECT 8.84 0.84 9.12 108.36 ;
+      RECT 11.08 0.84 11.36 108.36 ;
+      RECT 13.32 0.84 13.6 108.36 ;
+      RECT 15.56 0.84 15.84 108.36 ;
+      RECT 17.8 0.84 18.08 108.36 ;
+      RECT 20.04 0.84 20.32 108.36 ;
+      RECT 22.28 0.84 22.56 108.36 ;
+      RECT 24.52 0.84 24.8 108.36 ;
+      RECT 26.76 0.84 27.04 108.36 ;
+      RECT 29 0.84 29.28 108.36 ;
+      RECT 31.24 0.84 31.52 108.36 ;
+      RECT 33.48 0.84 33.76 108.36 ;
+      RECT 35.72 0.84 36 108.36 ;
+      RECT 37.96 0.84 38.24 108.36 ;
+      RECT 40.2 0.84 40.48 108.36 ;
+      RECT 42.44 0.84 42.72 108.36 ;
+      RECT 44.68 0.84 44.96 108.36 ;
+      RECT 46.92 0.84 47.2 108.36 ;
+      RECT 49.16 0.84 49.44 108.36 ;
+      RECT 51.4 0.84 51.68 108.36 ;
+      RECT 53.64 0.84 53.92 108.36 ;
+      RECT 55.88 0.84 56.16 108.36 ;
+      RECT 58.12 0.84 58.4 108.36 ;
+      RECT 60.36 0.84 60.64 108.36 ;
+      RECT 62.6 0.84 62.88 108.36 ;
+      RECT 64.84 0.84 65.12 108.36 ;
+      RECT 67.08 0.84 67.36 108.36 ;
+      RECT 69.32 0.84 69.6 108.36 ;
+      RECT 71.56 0.84 71.84 108.36 ;
+      RECT 73.8 0.84 74.08 108.36 ;
+      RECT 76.04 0.84 76.32 108.36 ;
+      RECT 78.28 0.84 78.56 108.36 ;
+      RECT 80.52 0.84 80.8 108.36 ;
+      RECT 82.76 0.84 83.04 108.36 ;
+      RECT 85 0.84 85.28 108.36 ;
+      RECT 87.24 0.84 87.52 108.36 ;
+      RECT 89.48 0.84 89.76 108.36 ;
+      RECT 91.72 0.84 92 108.36 ;
+      RECT 93.96 0.84 94.24 108.36 ;
+      RECT 96.2 0.84 96.48 108.36 ;
+      RECT 98.44 0.84 98.72 108.36 ;
+    END
+  END VDD
+  OBS
+    LAYER metal1 ;
+    RECT 0 0 99.75 109.2 ;
+    LAYER metal2 ;
+    RECT 0 0 99.75 109.2 ;
+  END
+END array_256x8_0
+
+END LIBRARY
diff --git a/flow/platforms/nangate45/lib/array_2048x137_bk.lib b/flow/platforms/nangate45/lib/array_2048x137_bk.lib
new file mode 100644
index 0000000000..1a31b31a6e
--- /dev/null
+++ b/flow/platforms/nangate45/lib/array_2048x137_bk.lib
@@ -0,0 +1,395 @@
+library(array_2048x137_bk) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:28Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_2048x137_bk_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_2048x137_bk_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_2048x137_bk_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_2048x137_bk_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_2048x137_bk_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_2048x137_bk_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 137;
+        bit_from : 136;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_2048x137_bk_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_2048x137_bk) {
+    area : 32920.160;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 137;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.307 ;
+        internal_power(){
+            rise_power(array_2048x137_bk_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("11.862, 11.862")
+            }
+            fall_power(array_2048x137_bk_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("11.862, 11.862")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_2048x137_bk_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_2048x137_bk_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.368, 0.368", \
+                  "0.368, 0.368" \
+                )
+            }
+            cell_fall(array_2048x137_bk_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.368, 0.368", \
+                  "0.368, 0.368" \
+                )
+            }
+            rise_transition(array_2048x137_bk_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_2048x137_bk_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_2048x137_bk_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_2048x137_bk_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_2048x137_bk_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+            fall_power(array_2048x137_bk_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.119, 0.119")
+            }
+        }
+    }
+    cell_leakage_power : 1287.000;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/nangate45/lib/array_256x104.lib b/flow/platforms/nangate45/lib/array_256x104.lib
new file mode 100644
index 0000000000..3e52eae3b0
--- /dev/null
+++ b/flow/platforms/nangate45/lib/array_256x104.lib
@@ -0,0 +1,474 @@
+library(array_256x104) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:29Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x104_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x104_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x104_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x104_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x104_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x104_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 104;
+        bit_from : 103;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x104_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x104_WMASK) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x104) {
+    area : 25108.272;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 104;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.281 ;
+        internal_power(){
+            rise_power(array_256x104_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("7.929, 7.929")
+            }
+            fall_power(array_256x104_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("7.929, 7.929")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x104_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x104_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.300, 0.300", \
+                  "0.300, 0.300" \
+                )
+            }
+            cell_fall(array_256x104_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.300, 0.300", \
+                  "0.300, 0.300" \
+                )
+            }
+            rise_transition(array_256x104_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x104_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x104_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x104_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+        }
+    }
+    bus(RW0_wmask)   {
+        bus_type : array_256x104_WMASK;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x104_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+            fall_power(array_256x104_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.079, 0.079")
+            }
+        }
+    }
+    cell_leakage_power : 1035.450;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/nangate45/lib/array_256x13.lib b/flow/platforms/nangate45/lib/array_256x13.lib
new file mode 100644
index 0000000000..1c32ec13dc
--- /dev/null
+++ b/flow/platforms/nangate45/lib/array_256x13.lib
@@ -0,0 +1,395 @@
+library(array_256x13) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:30Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x13_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x13_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x13_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x13_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x13_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x13_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 13;
+        bit_from : 12;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x13_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x13) {
+    area : 7656.810;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 13;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.210 ;
+        internal_power(){
+            rise_power(array_256x13_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("2.355, 2.355")
+            }
+            fall_power(array_256x13_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("2.355, 2.355")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x13_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x13_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.261, 0.261", \
+                  "0.261, 0.261" \
+                )
+            }
+            cell_fall(array_256x13_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.261, 0.261", \
+                  "0.261, 0.261" \
+                )
+            }
+            rise_transition(array_256x13_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x13_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x13_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x13_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x13_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x13_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+    }
+    cell_leakage_power : 432.350;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/nangate45/lib/array_256x16.lib b/flow/platforms/nangate45/lib/array_256x16.lib
new file mode 100644
index 0000000000..0e3c00d49f
--- /dev/null
+++ b/flow/platforms/nangate45/lib/array_256x16.lib
@@ -0,0 +1,395 @@
+library(array_256x16) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:31Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x16_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x16_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x16_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x16_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x16_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x16_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 16;
+        bit_from : 15;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x16_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x16) {
+    area : 7656.810;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 16;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.210 ;
+        internal_power(){
+            rise_power(array_256x16_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("2.355, 2.355")
+            }
+            fall_power(array_256x16_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("2.355, 2.355")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x16_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x16_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.261, 0.261", \
+                  "0.261, 0.261" \
+                )
+            }
+            cell_fall(array_256x16_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.261, 0.261", \
+                  "0.261, 0.261" \
+                )
+            }
+            rise_transition(array_256x16_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x16_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x16_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x16_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x16_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+            fall_power(array_256x16_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.024, 0.024")
+            }
+        }
+    }
+    cell_leakage_power : 432.350;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/nangate45/lib/array_256x164.lib b/flow/platforms/nangate45/lib/array_256x164.lib
new file mode 100644
index 0000000000..94b74fc78d
--- /dev/null
+++ b/flow/platforms/nangate45/lib/array_256x164.lib
@@ -0,0 +1,474 @@
+library(array_256x164) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:31Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x164_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x164_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x164_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x164_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x164_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x164_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 164;
+        bit_from : 163;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x164_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x164_WMASK) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 4;
+        bit_from : 3;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x164) {
+    area : 38095.988;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 164;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.329 ;
+        internal_power(){
+            rise_power(array_256x164_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("14.686, 14.686")
+            }
+            fall_power(array_256x164_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("14.686, 14.686")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x164_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x164_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.375, 0.375", \
+                  "0.375, 0.375" \
+                )
+            }
+            cell_fall(array_256x164_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.375, 0.375", \
+                  "0.375, 0.375" \
+                )
+            }
+            rise_transition(array_256x164_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x164_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x164_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x164_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+        }
+    }
+    bus(RW0_wmask)   {
+        bus_type : array_256x164_WMASK;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x164_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+            fall_power(array_256x164_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.147, 0.147")
+            }
+        }
+    }
+    cell_leakage_power : 1437.360;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/nangate45/lib/array_256x8_0.lib b/flow/platforms/nangate45/lib/array_256x8_0.lib
new file mode 100644
index 0000000000..3b3c575df3
--- /dev/null
+++ b/flow/platforms/nangate45/lib/array_256x8_0.lib
@@ -0,0 +1,474 @@
+library(array_256x8_0) {
+    technology (cmos);
+    delay_model : table_lookup;
+    revision : 1.0;
+    date : "2026-08-05 23:36:32Z";
+    comment : "SRAM";
+    time_unit : "1ns";
+    voltage_unit : "1V";
+    current_unit : "1uA";
+    leakage_power_unit : "1uW";
+    nom_process : 1;
+    nom_temperature : 25.000;
+    nom_voltage : 1.1;
+    capacitive_load_unit (1,pf);
+
+    pulling_resistance_unit : "1kohm";
+
+    operating_conditions(tt_1.0_25.0) {
+        process : 1;
+        temperature : 25.000;
+        voltage : 1.1;
+        tree_type : balanced_tree;
+    }
+
+    /* default attributes */
+    default_cell_leakage_power : 0;
+    default_fanout_load : 1;
+    default_inout_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_output_pin_cap : 0.0;
+    default_input_pin_cap : 0.0;
+    default_max_transition : 0.227;
+
+    default_operating_conditions : tt_1.0_25.0;
+    default_leakage_power_density : 0.0;
+
+    /* additional header data */
+    slew_derate_from_library : 1.000;
+    slew_lower_threshold_pct_fall : 20.000;
+    slew_upper_threshold_pct_fall : 80.000;
+    slew_lower_threshold_pct_rise : 20.000;
+    slew_upper_threshold_pct_rise : 80.000;
+    input_threshold_pct_fall : 50.000;
+    input_threshold_pct_rise : 50.000;
+    output_threshold_pct_fall : 50.000;
+    output_threshold_pct_rise : 50.000;
+
+
+    lu_table_template(array_256x8_0_mem_out_delay_template) {
+        variable_1 : input_net_transition;
+        variable_2 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    lu_table_template(array_256x8_0_mem_out_slew_template) {
+        variable_1 : total_output_net_capacitance;
+            index_1 ("1000, 1001");
+    }
+    lu_table_template(array_256x8_0_constraint_template) {
+        variable_1 : related_pin_transition;
+        variable_2 : constrained_pin_transition;
+            index_1 ("1000, 1001");
+            index_2 ("1000, 1001");
+    }
+    power_lut_template(array_256x8_0_energy_template_clkslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    power_lut_template(array_256x8_0_energy_template_sigslew) {
+        variable_1 : input_transition_time;
+            index_1 ("1000, 1001");
+    }
+    library_features(report_delay_calculation);
+    type (array_256x8_0_DATA) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x8_0_ADDRESS) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+    type (array_256x8_0_WMASK) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 8;
+        bit_from : 7;
+        bit_to : 0 ;
+        downto : true ;
+    }
+cell(array_256x8_0) {
+    area : 10892.700;
+    interface_timing : true;
+    memory() {
+        type : ram;
+        address_width : 8;
+        word_width : 8;
+    }
+    pin(RW0_clk)   {
+        direction : input;
+        capacitance : 0.025;
+        clock : true;
+        min_period           : 0.211 ;
+        internal_power(){
+            rise_power(array_256x8_0_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.995, 1.995")
+            }
+            fall_power(array_256x8_0_energy_template_clkslew) {
+                index_1 ("0.009, 0.227");
+                values ("1.995, 1.995")
+            }
+        }
+    }
+
+    bus(RW0_rdata)   {
+        bus_type : array_256x8_0_DATA;
+        direction : output;
+        max_capacitance : 0.500;
+        memory_read() {
+            address : r0_addr_in;
+        }
+        timing() {
+            related_pin : "RW0_clk" ;
+            timing_type : rising_edge;
+            timing_sense : non_unate;
+            cell_rise(array_256x8_0_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.307, 0.307", \
+                  "0.307, 0.307" \
+                )
+            }
+            cell_fall(array_256x8_0_mem_out_delay_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.005, 0.500");
+                values ( \
+                  "0.307, 0.307", \
+                  "0.307, 0.307" \
+                )
+            }
+            rise_transition(array_256x8_0_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+            fall_transition(array_256x8_0_mem_out_slew_template) {
+                index_1 ("0.005, 0.500");
+                values ("0.009, 0.227")
+            }
+        }
+    }
+    pin(RW0_wmode)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+        }
+    }
+    pin(RW0_en)   {
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+        }
+    }
+    bus(RW0_addr)   {
+        bus_type : array_256x8_0_ADDRESS;
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin : RW0_clk;
+            timing_type : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+        }
+    }
+    bus(RW0_wdata)   {
+        bus_type : array_256x8_0_DATA;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+        }
+    }
+    bus(RW0_wmask)   {
+        bus_type : array_256x8_0_WMASK;
+        memory_write() {
+            address : RW0_addr;
+            clocked_on : "RW0_clk";
+        }
+        direction : input;
+        capacitance : 0.005;
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : setup_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        timing() {
+            related_pin     : RW0_clk;
+            timing_type     : hold_rising ;
+            rise_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+            fall_constraint(array_256x8_0_constraint_template) {
+                index_1 ("0.009, 0.227");
+                index_2 ("0.009, 0.227");
+                values ( \
+                  "0.050, 0.050", \
+                  "0.050, 0.050" \
+                )
+            }
+        }
+        internal_power(){
+            when : "(! (RW0_wmode) )";
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+        }
+        internal_power(){
+            when : "(RW0_wmode)";
+            rise_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+            fall_power(array_256x8_0_energy_template_sigslew) {
+                index_1 ("0.009, 0.227");
+                values ("0.020, 0.020")
+            }
+        }
+    }
+    cell_leakage_power : 435.962;
+  pg_pin (VDD) {
+    pg_type : primary_power;
+  }
+  pg_pin (VSS) {
+    pg_type : primary_ground;
+  }
+}
+
+}
diff --git a/flow/platforms/nangate45/verilog/array_2048x137_bk_bb.sv b/flow/platforms/nangate45/verilog/array_2048x137_bk_bb.sv
new file mode 100644
index 0000000000..8530061c8f
--- /dev/null
+++ b/flow/platforms/nangate45/verilog/array_2048x137_bk_bb.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module array_2048x137_bk (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [136:0] RW0_wdata,
+  output [136:0] RW0_rdata
+);
+endmodule
diff --git a/flow/platforms/nangate45/verilog/array_256x104_bb.sv b/flow/platforms/nangate45/verilog/array_256x104_bb.sv
new file mode 100644
index 0000000000..075dfa721a
--- /dev/null
+++ b/flow/platforms/nangate45/verilog/array_256x104_bb.sv
@@ -0,0 +1,11 @@
+(* blackbox *)
+module array_256x104 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [103:0] RW0_wdata,
+  output [103:0] RW0_rdata,
+  input [7:0] RW0_wmask
+);
+endmodule
diff --git a/flow/platforms/nangate45/verilog/array_256x13_bb.sv b/flow/platforms/nangate45/verilog/array_256x13_bb.sv
new file mode 100644
index 0000000000..a613508247
--- /dev/null
+++ b/flow/platforms/nangate45/verilog/array_256x13_bb.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module array_256x13 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [12:0] RW0_wdata,
+  output [12:0] RW0_rdata
+);
+endmodule
diff --git a/flow/platforms/nangate45/verilog/array_256x164_bb.sv b/flow/platforms/nangate45/verilog/array_256x164_bb.sv
new file mode 100644
index 0000000000..b15437c66e
--- /dev/null
+++ b/flow/platforms/nangate45/verilog/array_256x164_bb.sv
@@ -0,0 +1,11 @@
+(* blackbox *)
+module array_256x164 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [163:0] RW0_wdata,
+  output [163:0] RW0_rdata,
+  input [3:0] RW0_wmask
+);
+endmodule
diff --git a/flow/platforms/nangate45/verilog/array_256x16_bb.sv b/flow/platforms/nangate45/verilog/array_256x16_bb.sv
new file mode 100644
index 0000000000..8814e1f4d5
--- /dev/null
+++ b/flow/platforms/nangate45/verilog/array_256x16_bb.sv
@@ -0,0 +1,10 @@
+(* blackbox *)
+module array_256x16 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [15:0] RW0_wdata,
+  output [15:0] RW0_rdata
+);
+endmodule
diff --git a/flow/platforms/nangate45/verilog/array_256x8_0_bb.sv b/flow/platforms/nangate45/verilog/array_256x8_0_bb.sv
new file mode 100644
index 0000000000..a2ba101c7a
--- /dev/null
+++ b/flow/platforms/nangate45/verilog/array_256x8_0_bb.sv
@@ -0,0 +1,11 @@
+(* blackbox *)
+module array_256x8_0 (
+  input [7:0] RW0_addr,
+  input RW0_en,
+  input RW0_clk,
+  input RW0_wmode,
+  input [7:0] RW0_wdata,
+  output [7:0] RW0_rdata,
+  input [7:0] RW0_wmask
+);
+endmodule