diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index b9404e06b0..ed03e7b664 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -135,7 +135,7 @@ configuration file. | DETAILED_METRICS| If set, then calls report_metrics prior to repair operations in the CTS and global route stages| 0| | DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| | | DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64| -| DETAIL_PLACEMENT_ARGS| Specify arguments to the detailed_placement call during placement.| | +| DETAIL_PLACEMENT_ARGS| Specify arguments to every detailed_placement call: the one in placement and the re-legalizations after clock tree synthesis, after repair in CTS and after the repairs in global route. A legalizer chosen here (-use_diamond_legalizer, -max_displacement) is therefore the one every stage uses.| | | DFF_LIB_FILE| Single Liberty file for flip-flop technology mapping (dfflibmap) during synthesis. Takes precedence over DFF_MAP_FILE when set.| | | DFF_MAP_FILE| Optional mapping file supplied to Yosys to map D flip-flops| | | DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| | @@ -524,6 +524,7 @@ configuration file. - [CTS_SNAPSHOT](#CTS_SNAPSHOT) - [CTS_SNAPSHOTS](#CTS_SNAPSHOTS) - [DETAILED_METRICS](#DETAILED_METRICS) +- [DETAIL_PLACEMENT_ARGS](#DETAIL_PLACEMENT_ARGS) - [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN) - [LEC_AUX_VERILOG_FILES](#LEC_AUX_VERILOG_FILES) - [LEC_CHECK](#LEC_CHECK) @@ -547,6 +548,7 @@ configuration file. - [CELL_PAD_IN_SITES_DETAIL_PLACEMENT](#CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - [DETAILED_METRICS](#DETAILED_METRICS) +- [DETAIL_PLACEMENT_ARGS](#DETAIL_PLACEMENT_ARGS) - [ENABLE_RESISTANCE_AWARE](#ENABLE_RESISTANCE_AWARE) - [GLOBAL_ROUTE_ARGS](#GLOBAL_ROUTE_ARGS) - [GLOBAL_ROUTE_USE_CUGR](#GLOBAL_ROUTE_USE_CUGR) diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl index 276ed38251..18ebf9c3dd 100644 --- a/flow/scripts/cts.tcl +++ b/flow/scripts/cts.tcl @@ -46,7 +46,7 @@ set_placement_padding -global \ -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) -set result [catch { log_cmd detailed_placement } msg] +set result [catch { detailed_placement_helper } msg] if { $result != 0 } { save_progress 4_1_error error "Detailed placement failed in CTS: $msg" @@ -71,7 +71,7 @@ if { !$::env(SKIP_CTS_REPAIR_TIMING) } { run_lec_test 4_rsz 4_before_rsz_lec.v 4_after_rsz_lec.v } - set result [catch { log_cmd detailed_placement } msg] + set result [catch { detailed_placement_helper } msg] if { $result != 0 } { save_progress 4_1_error error "Detailed placement failed in CTS: $msg" diff --git a/flow/scripts/detail_place.tcl b/flow/scripts/detail_place.tcl index c29d9ab90c..3a748a5df6 100644 --- a/flow/scripts/detail_place.tcl +++ b/flow/scripts/detail_place.tcl @@ -15,8 +15,7 @@ proc do_dpl { } { set_placement_padding -global \ -left $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) \ -right $::env(CELL_PAD_IN_SITES_DETAIL_PLACEMENT) - set dpl_args [env_var_or_empty DETAIL_PLACEMENT_ARGS] - log_cmd detailed_placement {*}$dpl_args + detailed_placement_helper if { $::env(ENABLE_DPO) } { if { [env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT] } { diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl index 4db71be44d..62794ead9a 100644 --- a/flow/scripts/global_route.tcl +++ b/flow/scripts/global_route.tcl @@ -85,7 +85,7 @@ proc global_route_helper { } { # Running DPL to fix overlapped instances # Run to get modified net by DPL log_cmd global_route -start_incremental - log_cmd detailed_placement + detailed_placement_helper # Route only the modified net by DPL if { ![run_global_route_and_catch_failures -end_incremental {*}$res_aware \ @@ -105,7 +105,7 @@ proc global_route_helper { } { } log_cmd global_route -start_incremental - log_cmd detailed_placement + detailed_placement_helper log_cmd check_placement -verbose # Route only the modified net by DPL if { diff --git a/flow/scripts/util.tcl b/flow/scripts/util.tcl index b589303217..912762199a 100644 --- a/flow/scripts/util.tcl +++ b/flow/scripts/util.tcl @@ -45,6 +45,13 @@ proc repair_timing_helper { args } { log_cmd repair_timing {*}$additional_args } +# Every detailed_placement in the flow goes through here, so the design's +# DETAIL_PLACEMENT_ARGS (the legalizer and its window, say) apply to the +# placement stage and to every re-legalization after it alike. +proc detailed_placement_helper { args } { + log_cmd detailed_placement {*}[env_var_or_empty DETAIL_PLACEMENT_ARGS] {*}$args +} + proc repair_design_helper { } { puts "Perform buffer insertion and gate resizing..." diff --git a/flow/scripts/variables.json b/flow/scripts/variables.json index 9327988582..006ff4307a 100644 --- a/flow/scripts/variables.json +++ b/flow/scripts/variables.json @@ -276,9 +276,11 @@ ] }, "DETAIL_PLACEMENT_ARGS": { - "description": "Specify arguments to the detailed_placement call during placement.\n", + "description": "Specify arguments to every detailed_placement call: the one in placement and the re-legalizations after clock tree synthesis, after repair in CTS and after the repairs in global route. A legalizer chosen here (-use_diamond_legalizer, -max_displacement) is therefore the one every stage uses.\n", "stages": [ - "place" + "place", + "cts", + "grt" ] }, "DFF_LIB_FILE": { diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index 7b6a3e1c4a..b00d506179 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -627,9 +627,15 @@ CELL_PAD_IN_SITES_GLOBAL_PLACEMENT: tunable: 1 DETAIL_PLACEMENT_ARGS: description: > - Specify arguments to the detailed_placement call during placement. + Specify arguments to every detailed_placement call: the one in placement + and the re-legalizations after clock tree synthesis, after repair in + CTS and after the repairs in global route. A legalizer chosen here + (-use_diamond_legalizer, -max_displacement) is therefore the one every + stage uses. stages: - place + - cts + - grt CELL_PAD_IN_SITES_DETAIL_PLACEMENT: description: > Cell padding on both sides in site widths to ease routability in detail