From 40154a9d44fe5737f630308b3b0a64ef6ce22e0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Fri, 18 Sep 2026 11:13:59 +0200 Subject: [PATCH] synth: strip src attributes again after techmap under SYNTH_REPEATABLE_BUILD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SYNTH_REPEATABLE_BUILD strips src attributes in synth_canonicalize.tcl so source paths and line numbers cannot perturb the canonical RTLIL hash. The techmap passes that follow in synth.tcl re-attach src attributes, now pointing into the techmap library files (ADDER_MAP_FILE, LATCH_MAP_FILE, DFF_MAP_FILE and yosys' own techmap.v). Under Bazel those live below the output base, so 1_2_yosys.v carries absolute build paths: the same design synthesised in two output bases produced netlists that differed only in those strings, defeating the knob's purpose. Strip src again, under the same guard, right before 1_2_yosys.v is written. Verified on a hierarchical design synthesised in two Bazel output bases: the netlists become byte-identical where they previously differed only in src paths. Signed-off-by: Øyvind Harboe --- flow/scripts/synth.tcl | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/flow/scripts/synth.tcl b/flow/scripts/synth.tcl index bb2d54ed31..f94b68c60f 100644 --- a/flow/scripts/synth.tcl +++ b/flow/scripts/synth.tcl @@ -322,5 +322,13 @@ if { check -assert } +if { $::env(SYNTH_REPEATABLE_BUILD) } { + # techmap re-attaches src attributes that point into the techmap library, + # after synth_canonicalize.tcl stripped them; strip again so the netlist + # carries no build paths. + setattr -unset src * + setattr -mod -unset src * +} + # Write synthesized design write_verilog -nohex -nodec $::env(RESULTS_DIR)/1_2_yosys.v