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Explore evolving SLR/Zlup into a Rust-native QEC HDL #511

Description

@qciaran

Summary

Explore an HDL-inspired user model and common schema for describing QEC artifacts across multiple abstraction levels.

Parent: #509
Architectural discussion: #508

Motivation

Hardware-description languages capture hierarchy, parameterization, multiple implementations of an interface, structural composition, constraints, assertions, testbenches, and progressive refinement. These concepts map naturally onto QEC codes, protocols, circuits, mappings, and target schedules.

The goal is to determine which HDL ideas PECOS should adopt without prematurely committing to Verilog syntax or building a parser before the internal semantic model is understood.

Questions to explore

  • Should the user-facing form be:
    • a dedicated textual QEC HDL;
    • a Python/Rust builder DSL;
    • a declarative serialized schema;
    • multiple front ends over shared typed IRs?
  • How should a module distinguish an abstract interface from one of several implementations?
  • How should parameterized code families and generate-style construction work?
  • How should constraints, assertions, testbenches, and refinement certificates be represented?
  • How should logical programs, adaptive protocols, decoders, and Pauli-frame updates compose?
  • At what point should artifacts lower into HUGR or existing circuit representations?
  • Which representation should be the stable interchange format?

Candidate HDL analogies

HDL concept QEC analogue
Module interface Abstract code or logical operation
Architecture/implementation QEC or syndrome-extraction protocol
Netlist Physical circuit
Place and route Qubit mapping and routing
Timing closure Native schedule and feedback latency
Testbench Code-capacity, phenomenological, or circuit-level experiment
Assertion Code validity, logical action, or fault-tolerance property
Cell library Native gates and target capabilities

Deliverables

  • Compare at least three frontend approaches against representative use cases.
  • Write example descriptions for:
    • a parameterized repetition or surface-code family;
    • the Steane code with two syndrome-extraction implementations;
    • an adaptive protocol with decoder feedback;
    • a target mapping with timing constraints.
  • Identify the common semantic model required beneath all candidate syntaxes.
  • Prototype only enough syntax/builders to validate the model.
  • Recommend whether to proceed with a dedicated HDL and, if so, propose follow-up implementation issues.

Acceptance criteria

  • A design note records the evaluated options and recommendation.
  • Examples demonstrate hierarchy, parameterization, alternate implementations, constraints, and testbench/experiment attachment.
  • The proposed frontend has an explicit lowering path into the IRs agreed in [RFC] Layered abstractions and an HDL-style design model for QEC #508.
  • The exploration does not duplicate HUGR or existing circuit IR responsibilities without a documented reason.

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