From d02bd1d4d569e613a61e70c98e86e49f8f1b6b41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 19 Aug 2026 00:20:46 +0100 Subject: [PATCH 1/3] feat(FPGA): Add support for Smart Zynq SL FPGA board Smart Zynq SL has been verified to work with ethernet under Linux. ZCU104 and Zybo Z7 boards are untested, but will likely fail during booloader ethernet transfers since their wrappers don't currently connect iob_eth to their PHY chips. --- default.nix | 4 ++-- soc_linux.py | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/default.nix b/default.nix index be415b3..aa0adf0 100644 --- a/default.nix +++ b/default.nix @@ -5,8 +5,8 @@ { pkgs ? import (fetchTarball "https://github.com/NixOS/nixpkgs/archive/25.05.tar.gz") {} }: let - py2hwsw_commit = "3ba45fe1420f3b1ef67903c90f652172f8697949"; # Replace with the desired commit. - py2hwsw_sha256 = "5ANpITrAKXw8DX+uCnyPDueEoBRpYpCMgOwSA1gqO70="; # Replace with the actual SHA256 hash. + py2hwsw_commit = "a3c4ccd834954e8c3404954328daa4762b3ec996"; # Replace with the desired commit. + py2hwsw_sha256 = "gFycJ1H66CulHdnH7RZN5T3l6ou1/p7iX6P2hWQUA0g="; # Replace with the actual SHA256 hash. # Get local py2hwsw root from `PY2HWSW_ROOT` env variable py2hwswRoot = builtins.getEnv "PY2HWSW_ROOT"; diff --git a/soc_linux.py b/soc_linux.py index 43dcb9a..a83e4f6 100644 --- a/soc_linux.py +++ b/soc_linux.py @@ -38,6 +38,8 @@ def setup(py_params: dict): "iob_aes_ku040_db_g", "iob_cyclonev_gt_dk", "iob_zybo_z7", + "iob_smart_zynq_sl", + "iob_zcu104", ], "ports": [ { From 441c046f2f8ecc65b7c4b526fa0f8678788d2ab3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 19 Aug 2026 02:29:46 +0100 Subject: [PATCH 2/3] Re-trigger ghactions From b218fc0859184446f8698905042e3ab7a4ecc5c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Artur=20N=C3=B3brega?= Date: Wed, 19 Aug 2026 04:23:49 +0100 Subject: [PATCH 3/3] Re-run ghactions